469 files changed, 10681 insertions, 17163 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2ec4ff36e560..2c370c869beb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -36,7 +36,6 @@ config ARM
        select HAVE_GENERIC_HARDIRQS
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
        select HAVE_IDE if PCI || ISA || PCMCIA
-        select HAVE_IRQ_WORK
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZMA
        select HAVE_KERNEL_LZO
@@ -261,7 +260,8 @@ config MMU
 #
 choice
        prompt "ARM system type"
-        default ARCH_MULTIPLATFORM
+        default ARCH_VERSATILE if !MMU
+        default ARCH_MULTIPLATFORM if MMU
 config ARCH_MULTIPLATFORM
        bool "Allow multiple platforms to be selected"
@@ -344,10 +344,10 @@ config ARCH_BCM2835
        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
        select CLKDEV_LOOKUP
+        select CLKSRC_OF
        select COMMON_CLK
        select CPU_V6
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select MULTI_IRQ_HANDLER
        select PINCTRL
        select PINCTRL_BCM2835
@@ -647,7 +647,6 @@ config ARCH_TEGRA
        select CLKSRC_OF
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
@@ -701,6 +700,7 @@ config ARCH_SHMOBILE
        select MULTI_IRQ_HANDLER
        select NEED_MACH_MEMORY_H
        select NO_IOPORT
+        select PINCTRL
        select PM_GENERIC_DOMAINS if PM
        select SPARSE_IRQ
        help
@@ -747,7 +747,6 @@ config ARCH_S3C24XX
        select ARCH_HAS_CPUFREQ
        select ARCH_USES_GETTIMEOFFSET
        select CLKDEV_LOOKUP
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -790,7 +789,6 @@ config ARCH_S5P64X0
        select CLKSRC_MMIO
        select CPU_V6
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -805,7 +803,6 @@ config ARCH_S5PC100
        select ARCH_USES_GETTIMEOFFSET
        select CLKDEV_LOOKUP
        select CPU_V7
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -823,7 +820,6 @@ config ARCH_S5PV210
        select CLKSRC_MMIO
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -841,7 +837,6 @@ config ARCH_EXYNOS
        select CLKDEV_LOOKUP
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -876,7 +871,6 @@ config ARCH_U300
        select COMMON_CLK
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_TCM
        select SPARSE_IRQ
        help
@@ -940,17 +934,24 @@ config ARCH_DAVINCI
        help
          Support for TI's DaVinci platform.
-config ARCH_OMAP
+config ARCH_OMAP1
-        bool "TI OMAP"
+        bool "TI OMAP1"
        depends on MMU
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_OMAP
        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
        select HAVE_CLK
+        select HAVE_IDE
+        select IRQ_DOMAIN
+        select NEED_MACH_IO_H if PCCARD
+        select NEED_MACH_MEMORY_H
        help
-          Support for TI's OMAP platform (OMAP1/2/3/4).
+          Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 endchoice
@@ -1073,17 +1074,12 @@ source "arch/arm/mach-realview/Kconfig"
 source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
-source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/plat-spear/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
-if ARCH_S3C24XX
-source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2440/Kconfig"
-endif
 if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
@@ -1437,6 +1433,10 @@ config ISA_DMA
        bool
        select ISA_DMA_API
+config ARCH_NO_VIRT_TO_BUS
+        def_bool y
+        depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
 # Select ISA DMA interface
 config ISA_DMA_API
        bool
@@ -1518,7 +1518,6 @@ config SMP
 config SMP_ON_UP
        bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        depends on SMP && !XIP_KERNEL
        default y
        help
@@ -1607,6 +1606,16 @@ config HOTPLUG_CPU
          Say Y here to experiment with turning CPUs off and on.  CPUs
          can be controlled through /sys/devices/system/cpu.
+config ARM_PSCI
+        bool "Support for the ARM Power State Coordination Interface (PSCI)"
+        depends on CPU_V7
+        help
+          Say Y here if you want Linux to communicate with system firmware
+          implementing the PSCI specification for CPU-centric power
+          management operations described in ARM document number ARM DEN
+          0022A ("Power State Coordination Interface System Software on
+          ARM processors").
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP
@@ -1624,7 +1633,7 @@ config ARCH_NR_GPIO
        default 355 if ARCH_U8500
        default 264 if MACH_H4700
        default 512 if SOC_OMAP5
-        default 288 if ARCH_VT8500
+        default 288 if ARCH_VT8500 || ARCH_SUNXI
        default 0
        help
          Maximum number of GPIOs in the system.
@@ -1642,6 +1651,9 @@ config HZ
        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
        default 100
+config SCHED_HRTICK
+        def_bool HIGH_RES_TIMERS
 config THUMB2_KERNEL
        bool "Compile the kernel in Thumb-2 mode"
        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
@@ -1706,7 +1718,7 @@ config AEABI
 config OABI_COMPAT
        bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
-        depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
+        depends on AEABI && !THUMB2_KERNEL
        default y
        help
          This option preserves the old syscall interface along with the
@@ -1830,7 +1842,6 @@ config SECCOMP
 config CC_STACKPROTECTOR
        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        help
          This option turns on the -fstack-protector GCC feature. This
          feature puts, at the beginning of functions, a canary value on
@@ -1847,7 +1858,7 @@ config XEN_DOM0
 config XEN
        bool "Xen guest support on ARM (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && ARM && OF
+        depends on ARM && OF
        depends on CPU_V7 && !CPU_V6
        help
          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
@@ -1916,7 +1927,7 @@ config ZBOOT_ROM
 choice
        prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
-        depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
+        depends on ZBOOT_ROM && ARCH_SH7372
        default ZBOOT_ROM_NONE
        help
          Include experimental SD/MMC loading code in the ROM-able zImage.
@@ -1945,7 +1956,7 @@ endchoice
 config ARM_APPENDED_DTB
        bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
-        depends on OF && !ZBOOT_ROM && EXPERIMENTAL
+        depends on OF && !ZBOOT_ROM
        help
          With this option, the boot code will look for a device tree binary
          (DTB) appended to zImage
@@ -2063,7 +2074,7 @@ config XIP_PHYS_ADDR
 config KEXEC
        bool "Kexec system call (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
+        depends on (!SMP || HOTPLUG_CPU)
        help
          kexec is a system call that implements the ability to shutdown your
          current kernel, and to start another kernel.  It is like a reboot
@@ -2085,7 +2096,6 @@ config ATAGS_PROC
 config CRASH_DUMP
        bool "Build kdump crash kernel (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        help
          Generate crash dump after being started by kexec. This should
          be normally only set in special crash dump kernels which are
@@ -2152,7 +2162,7 @@ config CPU_FREQ_S3C
 config CPU_FREQ_S3C24XX
        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
+        depends on ARCH_S3C24XX && CPU_FREQ
        select CPU_FREQ_S3C
        help
          This enables the CPUfreq driver for the Samsung S3C24XX family
@@ -2164,7 +2174,7 @@ config CPU_FREQ_S3C24XX
 config CPU_FREQ_S3C24XX_PLL
        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
-        depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
+        depends on CPU_FREQ_S3C24XX
        help
          Compile in support for changing the PLL frequency from the
          S3C24XX series CPUfreq driver. The PLL takes time to settle
@@ -2227,7 +2237,7 @@ config FPE_NWFPE_XP
 config FPE_FASTFPE
        bool "FastFPE math emulation (EXPERIMENTAL)"
-        depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
+        depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
        ---help---
          Say Y here to include the FAST floating point emulator in the kernel.
          This is an experimental much faster emulator which now also has full
@@ -2309,3 +2319,5 @@ source "security/Kconfig"
 source "crypto/Kconfig"
 source "lib/Kconfig"
+source "arch/arm/kvm/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 305ceb8ed03d..acddddac7ee4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -32,7 +32,7 @@ config FRAME_POINTER
 config ARM_UNWIND
        bool "Enable stack unwinding support (EXPERIMENTAL)"
-        depends on AEABI && EXPERIMENTAL
+        depends on AEABI
        default y
        help
          This option enables stack unwinding support in the kernel
@@ -298,6 +298,13 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on MVEBU based platforms.
+        config DEBUG_OMAP2PLUS_UART
+                bool "Kernel low-level debugging messages via OMAP2PLUS UART"
+                depends on ARCH_OMAP2PLUS
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on OMAP2PLUS based platforms.
        config DEBUG_PICOXCELL_UART
                depends on ARCH_PICOXCELL
                bool "Use PicoXcell UART for low-level debug"
@@ -494,6 +501,54 @@ config DEBUG_IMX_UART_PORT
 choice
        prompt "Low-level debug console UART"
+        depends on DEBUG_OMAP2PLUS_UART
+        config DEBUG_OMAP2UART1
+                bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
+                help
+                  This covers at least h4, 2430sdp, 3430sdp, 3630sdp,
+                  omap3 torpedo and 3530 lv som.
+        config DEBUG_OMAP2UART2
+                bool "OMAP2/3/4 UART2"
+        config DEBUG_OMAP2UART3
+                bool "OMAP2 UART3 (n8x0)"
+        config DEBUG_OMAP3UART3
+                bool "OMAP3 UART3 (most omap3 boards)"
+                help
+                  This covers at least cm_t3x, beagle, crane, devkit8000,
+                  igep00x0, ldp, n900, n9(50), pandora, overo, touchbook,
+                  and 3517evm.
+        config DEBUG_OMAP4UART3
+                bool "OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)"
+        config DEBUG_OMAP3UART4
+                bool "OMAP36XX UART4"
+        config DEBUG_OMAP4UART4
+                bool "OMAP4/5 UART4"
+        config DEBUG_TI81XXUART1
+                bool "TI81XX UART1 (ti8148evm)"
+        config DEBUG_TI81XXUART2
+                bool "TI81XX UART2"
+        config DEBUG_TI81XXUART3
+                bool "TI81XX UART3 (ti8168evm)"
+        config DEBUG_AM33XXUART1
+                bool "AM33XX UART1"
+        config DEBUG_ZOOM_UART
+                bool "Zoom2/3 UART"
+endchoice
+choice
+        prompt "Low-level debug console UART"
        depends on DEBUG_LL && DEBUG_TEGRA_UART
        config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -535,6 +590,7 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX6Q_UART
        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30c443c406f3..1b7071681a5e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_PRIMA2)		+= prima2
 machine-$(CONFIG_ARCH_PXA)              += pxa
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
 machine-$(CONFIG_ARCH_RPC)              += rpc
-machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
@@ -204,7 +204,7 @@ plat-$(CONFIG_ARCH_S3C64XX)	+= samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
 plat-$(CONFIG_PLAT_ORION)       += orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
-plat-$(CONFIG_PLAT_S3C24XX)     += s3c24xx samsung
+plat-$(CONFIG_PLAT_S3C24XX)     += samsung
 plat-$(CONFIG_PLAT_S5P)         += samsung
 plat-$(CONFIG_PLAT_SPEAR)       += spear
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
@@ -252,6 +252,7 @@ core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
 core-$(CONFIG_XEN)              += arch/arm/xen/
+core-$(CONFIG_KVM_ARM_HOST)     += arch/arm/kvm/
 # If we have a machine-specific directory, then include it in the build.
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 9deb56a702ce..24b0475cb8bf 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -13,8 +13,6 @@ extern void error(char *);
 #define STATIC static
 #define STATIC_RW_DATA  /* non-static please */
-#define ARCH_HAS_DECOMP_WDOG
 /* Diagnostic functions */
 #ifdef DEBUG
 #  define Assert(cond,msg) {if(!(cond)) error(msg);}
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 80e29c605d4e..4801717566dd 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -324,8 +324,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x4000>;
                                interrupts = <5 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -335,8 +333,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x4000>;
                                interrupts = <6 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -346,8 +342,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x4000>;
                                interrupts = <7 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -357,8 +351,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8028000 0x4000>;
                                interrupts = <8 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8ecca6948d81..d112c3af8ce2 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -197,9 +197,9 @@
                                };
                                usart3 {
-                                        pinctrl_uart3: usart3-0 {
+                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <2 23 0x2 0x1   /* PC22 periph B with pullup */
+                                                        <2 22 0x2 0x1   /* PC22 periph B with pullup */
                                                         2 23 0x2 0x0>; /* PC23 periph B */
                                        };
@@ -402,8 +402,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x200>;
                                interrupts = <5 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -413,8 +411,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x200>;
                                interrupts = <6 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -424,8 +420,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x200>;
                                interrupts = <7 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 63f2fbcfe819..69140ba99f46 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -170,10 +170,9 @@
                        gpio-bank = <8>;
                };
-                pinctrl@80157000 {
+                pinctrl {
-                        // This is actually the PRCMU base address
+                        compatible = "stericsson,nmk-pinctrl";
-                        reg = <0x80157000 0x2000>;
+                        prcm = <&prcmu>;
-                        compatible = "stericsson,nmk_pinctrl";
                };
                usb@a03e0000 {
@@ -190,9 +189,10 @@
                        interrupts = <0 25 0x4>;
                };
-                prcmu@80157000 {
+                prcmu: prcmu@80157000 {
                        compatible = "stericsson,db8500-prcmu";
                        reg = <0x80157000 0x1000>;
+                        reg-names = "prcmu";
                        interrupts = <0 47 0x4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index e31bfc4a6f09..2feffc70814c 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -48,13 +48,13 @@
        };
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
        };
        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>;
@@ -66,7 +66,7 @@
        };
        pinctrl_2: pinctrl@03860000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x03860000 0x1000>;
        };
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 8e6115adcd97..099cec79e2ae 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -661,7 +661,7 @@
                sd4_bus8: sd4-bus-width8 {
                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <3>;
+                        samsung,pin-function = <4>;
                        samsung,pin-pud = <4>;
                        samsung,pin-drv = <3>;
                };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 179a62e46c9d..9a8780694909 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -37,13 +37,13 @@
        };
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
        };
        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>;
@@ -55,14 +55,14 @@
        };
        pinctrl_2: pinctrl@03860000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x03860000 0x1000>;
                interrupt-parent = <&combiner>;
                interrupts = <10 0>;
        };
        pinctrl_3: pinctrl@106E0000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x106E0000 0x1000>;
                interrupts = <0 72 0>;
        };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index e05b18f3c33d..4db9db0a8443 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -49,6 +49,11 @@
                        compatible = "samsung,s524ad0xd1";
                        reg = <0x51>;
                };
+                wm8994: wm8994@1a {
+                         compatible = "wlf,wm8994";
+                         reg = <0x1a>;
+                };
        };
        i2c@121D0000 {
@@ -204,4 +209,25 @@
                samsung,mfc-r = <0x43000000 0x800000>;
                samsung,mfc-l = <0x51000000 0x800000>;
        };
+        i2s0: i2s@03830000 {
+                gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>,
+                        <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
+                        <&gpz 6 2 0 0>;
+        };
+        i2s1: i2s@12D60000 {
+                status = "disabled";
+        };
+        i2s2: i2s@12D70000 {
+                status = "disabled";
+        };
+        sound {
+                compatible = "samsung,smdk-wm8994";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&wm8994>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 3acf594ea60b..f50b4e854355 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -211,8 +211,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
                interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                dmas = <&pdma0 5
-                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                        &pdma0 4>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -221,8 +222,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d30000 0x100>;
                interrupts = <0 67 0>;
-                tx-dma-channel = <&pdma1 5>; /* preliminary */
+                dmas = <&pdma1 5
-                rx-dma-channel = <&pdma1 4>; /* preliminary */
+                        &pdma1 4>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -231,8 +233,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d40000 0x100>;
                interrupts = <0 68 0>;
-                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                dmas = <&pdma0 7
-                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                        &pdma0 6>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -269,6 +272,35 @@
                #size-cells = <0>;
        };
+        i2s0: i2s@03830000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x03830000 0x100>;
+                dmas = <&pdma0 10
+                        &pdma0 9
+                        &pdma0 8>;
+                dma-names = "tx", "rx", "tx-sec";
+                samsung,supports-6ch;
+                samsung,supports-rstclr;
+                samsung,supports-secdai;
+                samsung,idma-addr = <0x03000000>;
+        };
+        i2s1: i2s@12D60000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x12D60000 0x100>;
+                dmas = <&pdma1 12
+                        &pdma1 11>;
+                dma-names = "tx", "rx";
+        };
+        i2s2: i2s@12D70000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x12D70000 0x100>;
+                dmas = <&pdma0 12
+                        &pdma0 11>;
+                dma-names = "tx", "rx";
+        };
        amba {
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 024269de8ee5..5f3562ad6746 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -86,7 +86,7 @@
        };
        pinctrl {
-                compatible = "samsung,pinctrl-exynos5440";
+                compatible = "samsung,exynos5440-pinctrl";
                reg = <0xE0000 0x1000>;
                interrupt-controller;
                #interrupt-cells = <2>;
@@ -154,6 +154,6 @@
        rtc {
                compatible = "samsung,s3c6410-rtc";
                reg = <0x130000 0x1000>;
-                interrupts = <0 16 0>, <0 17 0>;
+                interrupts = <0 17 0>, <0 16 0>;
        };
 };
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 5927a8df5625..6aad34ad9517 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -37,6 +37,16 @@
                        next-level-cache = <&L2>;
                        clocks = <&a9pll>;
                        clock-names = "cpu";
+                        operating-points = <
+                                /* kHz    ignored */
+                                 1300000  1000000
+                                 1200000  1000000
+                                 1100000  1000000
+                                  800000  1000000
+                                  400000  1000000
+                                  200000  1000000
+                        >;
+                        clock-latency = <100000>;
                };
                cpu@901 {
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 65415c598a5e..56afcf41aae0 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -391,7 +391,9 @@
                        };
                        lradc@80050000 {
+                                compatible = "fsl,imx23-lradc";
                                reg = <0x80050000 0x2000>;
+                                interrupts = <36 37 38 39 40 41 42 43 44>;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d6265ca97119..ff1205ea5719 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -866,7 +866,7 @@
                                compatible = "fsl,imx6q-fec";
                                reg = <0x02188000 0x4000>;
                                interrupts = <0 118 0x04 0 119 0x04>;
-                                clocks = <&clks 117>, <&clks 117>, <&clks 177>;
+                                clocks = <&clks 117>, <&clks 117>, <&clks 190>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 055fca542120..3329719a9412 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -58,10 +58,11 @@
                        #size-cells = <1>;
                        ranges = <0x88000000 0x88000000 0x40000>;
-                        clock-controller@88000000 {
+                        clks: clock-controller@88000000 {
                                compatible = "sirf,prima2-clkc";
                                reg = <0x88000000 0x1000>;
                                interrupts = <3>;
+                                #clock-cells = <1>;
                        };
                        reset-controller@88010000 {
@@ -85,6 +86,7 @@
                                compatible = "sirf,prima2-memc";
                                reg = <0x90000000 0x10000>;
                                interrupts = <27>;
+                                clocks = <&clks 5>;
                        };
                };
@@ -104,6 +106,7 @@
                                compatible = "sirf,prima2-vpp";
                                reg = <0x90020000 0x10000>;
                                interrupts = <31>;
+                                clocks = <&clks 35>;
                        };
                };
@@ -117,6 +120,7 @@
                                compatible = "powervr,sgx531";
                                reg = <0x98000000 0x8000000>;
                                interrupts = <6>;
+                                clocks = <&clks 32>;
                        };
                };
@@ -130,6 +134,7 @@
                                compatible = "sirf,prima2-video-codec";
                                reg = <0xa0000000 0x8000000>;
                                interrupts = <5>;
+                                clocks = <&clks 33>;
                        };
                };
@@ -149,12 +154,14 @@
                                compatible = "sirf,prima2-gps";
                                reg = <0xa8010000 0x10000>;
                                interrupts = <7>;
+                                clocks = <&clks 9>;
                        };
                        dsp@a9000000 {
                                compatible = "sirf,prima2-dsp";
                                reg = <0xa9000000 0x1000000>;
                                interrupts = <8>;
+                                clocks = <&clks 8>;
                        };
                };
@@ -174,12 +181,14 @@
                                compatible = "sirf,prima2-nand";
                                reg = <0xb0030000 0x10000>;
                                interrupts = <41>;
+                                clocks = <&clks 26>;
                        };
                        audio@b0040000 {
                                compatible = "sirf,prima2-audio";
                                reg = <0xb0040000 0x10000>;
                                interrupts = <35>;
+                                clocks = <&clks 27>;
                        };
                        uart0: uart@b0050000 {
@@ -187,6 +196,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0050000 0x10000>;
                                interrupts = <17>;
+                                clocks = <&clks 13>;
                        };
                        uart1: uart@b0060000 {
@@ -194,6 +204,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0060000 0x10000>;
                                interrupts = <18>;
+                                clocks = <&clks 14>;
                        };
                        uart2: uart@b0070000 {
@@ -201,6 +212,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0070000 0x10000>;
                                interrupts = <19>;
+                                clocks = <&clks 15>;
                        };
                        usp0: usp@b0080000 {
@@ -208,6 +220,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb0080000 0x10000>;
                                interrupts = <20>;
+                                clocks = <&clks 28>;
                        };
                        usp1: usp@b0090000 {
@@ -215,6 +228,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb0090000 0x10000>;
                                interrupts = <21>;
+                                clocks = <&clks 29>;
                        };
                        usp2: usp@b00a0000 {
@@ -222,6 +236,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb00a0000 0x10000>;
                                interrupts = <22>;
+                                clocks = <&clks 30>;
                        };
                        dmac0: dma-controller@b00b0000 {
@@ -229,6 +244,7 @@
                                compatible = "sirf,prima2-dmac";
                                reg = <0xb00b0000 0x10000>;
                                interrupts = <12>;
+                                clocks = <&clks 24>;
                        };
                        dmac1: dma-controller@b0160000 {
@@ -236,11 +252,13 @@
                                compatible = "sirf,prima2-dmac";
                                reg = <0xb0160000 0x10000>;
                                interrupts = <13>;
+                                clocks = <&clks 25>;
                        };
                        vip@b00C0000 {
                                compatible = "sirf,prima2-vip";
                                reg = <0xb00C0000 0x10000>;
+                                clocks = <&clks 31>;
                        };
                        spi0: spi@b00d0000 {
@@ -248,6 +266,7 @@
                                compatible = "sirf,prima2-spi";
                                reg = <0xb00d0000 0x10000>;
                                interrupts = <15>;
+                                clocks = <&clks 19>;
                        };
                        spi1: spi@b0170000 {
@@ -255,6 +274,7 @@
                                compatible = "sirf,prima2-spi";
                                reg = <0xb0170000 0x10000>;
                                interrupts = <16>;
+                                clocks = <&clks 20>;
                        };
                        i2c0: i2c@b00e0000 {
@@ -262,6 +282,7 @@
                                compatible = "sirf,prima2-i2c";
                                reg = <0xb00e0000 0x10000>;
                                interrupts = <24>;
+                                clocks = <&clks 17>;
                        };
                        i2c1: i2c@b00f0000 {
@@ -269,12 +290,14 @@
                                compatible = "sirf,prima2-i2c";
                                reg = <0xb00f0000 0x10000>;
                                interrupts = <25>;
+                                clocks = <&clks 18>;
                        };
                        tsc@b0110000 {
                                compatible = "sirf,prima2-tsc";
                                reg = <0xb0110000 0x10000>;
                                interrupts = <33>;
+                                clocks = <&clks 16>;
                        };
                        gpio: pinctrl@b0120000 {
@@ -507,17 +530,20 @@
                        pwm@b0130000 {
                                compatible = "sirf,prima2-pwm";
                                reg = <0xb0130000 0x10000>;
+                                clocks = <&clks 21>;
                        };
                        efusesys@b0140000 {
                                compatible = "sirf,prima2-efuse";
                                reg = <0xb0140000 0x10000>;
+                                clocks = <&clks 22>;
                        };
                        pulsec@b0150000 {
                                compatible = "sirf,prima2-pulsec";
                                reg = <0xb0150000 0x10000>;
                                interrupts = <48>;
+                                clocks = <&clks 23>;
                        };
                        pci-iobg {
@@ -616,12 +642,14 @@
                                compatible = "chipidea,ci13611a-prima2";
                                reg = <0xb8000000 0x10000>;
                                interrupts = <10>;
+                                clocks = <&clks 40>;
                        };
                        usb1: usb@b00f0000 {
                                compatible = "chipidea,ci13611a-prima2";
                                reg = <0xb8010000 0x10000>;
                                interrupts = <11>;
+                                clocks = <&clks 41>;
                        };
                        sata@b00f0000 {
@@ -634,6 +662,7 @@
                                compatible = "sirf,prima2-security";
                                reg = <0xb8030000 0x10000>;
                                interrupts = <42>;
+                                clocks = <&clks 7>;
                        };
                };
        };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e61fdd47bd01..f99f60dadf5d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,4 +16,34 @@
        memory {
                reg = <0x40000000 0x80000000>;
        };
+        soc {
+                pinctrl@01c20800 {
+                        compatible = "allwinner,sun4i-a10-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart0_pins_b: uart0@1 {
+                                allwinner,pins = "PF2", "PF4";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PA10", "PA11";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 498a091a4ea2..4a1e45d4aace 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -24,6 +24,8 @@
        soc {
                uart1: uart@01c28400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_pins_b>;
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 59a2d265a98e..e1121890fb29 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,4 +17,27 @@
        memory {
                reg = <0x40000000 0x20000000>;
        };
+        soc {
+                pinctrl@01c20800 {
+                        compatible = "allwinner,sun5i-a13-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PE10", "PE11";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart1_pins_b: uart1@1 {
+                                allwinner,pins = "PG3", "PG4";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index a3d37ec2655d..73187173117c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -70,7 +70,7 @@
                compatible = "arm,sp805", "arm,primecell";
                status = "disabled";
                reg = <0 0x2b060000 0 0x1000>;
-                interrupts = <98>;
+                interrupts = <0 98 4>;
                clocks = <&oscclk7>;
                clock-names = "apb_pclk";
        };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index cf8071ad22d5..dfe371ec2749 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -72,7 +72,7 @@
        wdt@2a490000 {
                compatible = "arm,sp805", "arm,primecell";
                reg = <0 0x2a490000 0 0x1000>;
-                interrupts = <98>;
+                interrupts = <0 98 4>;
                clocks = <&oscclk6a>, <&oscclk6a>;
                clock-names = "wdogclk", "apb_pclk";
        };
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index d8645e990b21..cf31ced46602 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -45,6 +45,38 @@
                                        compatible = "fixed-clock";
                                        clock-frequency = <24000000>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <3>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <4>;
+                                };
                        };
                };
@@ -83,28 +115,28 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                uart@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart2>;
                };
                uart@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart3>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 330f833ac3b0..e74a1c0fb9a2 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -59,6 +59,54 @@
                                        compatible = "fixed-clock";
                                        clock-frequency = <24000000>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <3>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <4>;
+                                };
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <22>;
+                                };
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <23>;
+                                };
                        };
                };
@@ -96,42 +144,42 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                uart@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart2>;
                };
                uart@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart3>;
                };
                uart@d8370000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8370000 0x1040>;
                        interrupts = <31>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart4>;
                };
                uart@d8380000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8380000 0x1040>;
                        interrupts = <30>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart5>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 83b9467559bb..db3c0a12e052 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -75,6 +75,22 @@
                                        reg = <0x204>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
                                arm: arm {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
@@ -128,14 +144,14 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 401c1262d4ed..5914b5654591 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -44,14 +44,14 @@
                        compatible = "xlnx,xuartps";
                        reg = <0xE0000000 0x1000>;
                        interrupts = <0 27 4>;
-                        clock = <50000000>;
+                        clocks = <&uart_clk 0>;
                };
                uart1: uart@e0001000 {
                        compatible = "xlnx,xuartps";
                        reg = <0xE0001000 0x1000>;
                        interrupts = <0 50 4>;
-                        clock = <50000000>;
+                        clocks = <&uart_clk 1>;
                };
                slcr: slcr@f8000000 {
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index c5212f43eee6..36fed66bd4b5 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
 CONFIG_MACH_USB_A9263=y
-CONFIG_MACH_NEOCORE926=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 728a43c446f8..afb17d630d44 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -83,7 +83,6 @@ CONFIG_USB=y
 CONFIG_USB_RCAR_PHY=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
-CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2eeff1e64b6e..e31d442343c8 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SUNXI=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
+CONFIG_ARCH_ZYNQ=y
 CONFIG_ARM_ERRATA_754322=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
@@ -39,7 +40,6 @@ CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 82ce8d738fa1..5be2e4be802c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -20,9 +20,10 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_ARCH_VEXPRESS_CA9X4=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
@@ -121,6 +122,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
@@ -194,6 +197,7 @@ CONFIG_USB_ZERO=m
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_SDIO_UART=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index caa07db90cf5..e319b2c56f11 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -73,7 +73,6 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=m
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 231dca604737..426270fe080d 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -66,9 +66,9 @@ CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
-CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY is not set
-CONFIG_AB8500_BM=y
+# CONFIG_AB8500_BM is not set
-CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
+# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_MFD_STMPE=y
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
index e59b1d505d6c..19d6cd6f29f9 100644
--- a/arch/arm/crypto/aes-armv4.S
+++ b/arch/arm/crypto/aes-armv4.S
@@ -34,8 +34,9 @@
 @ A little glue here to select the correct code below for the ARM CPU
 @ that is being targetted.
+#include <linux/linkage.h>
 .text
-.code   32
 .type   AES_Te,%object
 .align  5
@@ -145,10 +146,8 @@ AES_Te:
 @ void AES_encrypt(const unsigned char *in, unsigned char *out,
 @                const AES_KEY *key) {
-.global AES_encrypt
-.type   AES_encrypt,%function
 .align  5
-AES_encrypt:
+ENTRY(AES_encrypt)
        sub     r3,pc,#8                @ AES_encrypt
        stmdb   sp!,{r1,r4-r12,lr}
        mov     r12,r0          @ inp
@@ -239,15 +238,8 @@ AES_encrypt:
        strb    r6,[r12,#14]
        strb    r3,[r12,#15]
 #endif
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(AES_encrypt)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   AES_encrypt,.-AES_encrypt
 .type   _armv4_AES_encrypt,%function
 .align  2
@@ -386,10 +378,8 @@ _armv4_AES_encrypt:
        ldr     pc,[sp],#4              @ pop and return
 .size   _armv4_AES_encrypt,.-_armv4_AES_encrypt
-.global private_AES_set_encrypt_key
-.type   private_AES_set_encrypt_key,%function
 .align  5
-private_AES_set_encrypt_key:
+ENTRY(private_AES_set_encrypt_key)
 _armv4_AES_set_encrypt_key:
        sub     r3,pc,#8                @ AES_set_encrypt_key
        teq     r0,#0
@@ -658,15 +648,11 @@ _armv4_AES_set_encrypt_key:
 .Ldone: mov     r0,#0
        ldmia   sp!,{r4-r12,lr}
-.Labrt: tst     lr,#1
+.Labrt: mov     pc,lr
-        moveq   pc,lr                   @ be binary compatible with V4, yet
+ENDPROC(private_AES_set_encrypt_key)
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-.size   private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
-.global private_AES_set_decrypt_key
-.type   private_AES_set_decrypt_key,%function
 .align  5
-private_AES_set_decrypt_key:
+ENTRY(private_AES_set_decrypt_key)
        str     lr,[sp,#-4]!            @ push lr
 #if 0
        @ kernel does both of these in setkey so optimise this bit out by
@@ -748,15 +734,8 @@ private_AES_set_decrypt_key:
        bne     .Lmix
        mov     r0,#0
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(private_AES_set_decrypt_key)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
 .type   AES_Td,%object
 .align  5
@@ -862,10 +841,8 @@ AES_Td:
 @ void AES_decrypt(const unsigned char *in, unsigned char *out,
 @                const AES_KEY *key) {
-.global AES_decrypt
-.type   AES_decrypt,%function
 .align  5
-AES_decrypt:
+ENTRY(AES_decrypt)
        sub     r3,pc,#8                @ AES_decrypt
        stmdb   sp!,{r1,r4-r12,lr}
        mov     r12,r0          @ inp
@@ -956,15 +933,8 @@ AES_decrypt:
        strb    r6,[r12,#14]
        strb    r3,[r12,#15]
 #endif
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(AES_decrypt)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   AES_decrypt,.-AES_decrypt
 .type   _armv4_AES_decrypt,%function
 .align  2
@@ -1064,7 +1034,9 @@ _armv4_AES_decrypt:
        and     r9,lr,r1,lsr#8
        ldrb    r7,[r10,r7]             @ Td4[s1>>0]
-        ldrb    r1,[r10,r1,lsr#24]      @ Td4[s1>>24]
+ ARM(   ldrb    r1,[r10,r1,lsr#24]  )   @ Td4[s1>>24]
+ THUMB( add     r1,r10,r1,lsr#24    )   @ Td4[s1>>24]
+ THUMB( ldrb    r1,[r1]             )
        ldrb    r8,[r10,r8]             @ Td4[s1>>16]
        eor     r0,r7,r0,lsl#24
        ldrb    r9,[r10,r9]             @ Td4[s1>>8]
@@ -1077,7 +1049,9 @@ _armv4_AES_decrypt:
        ldrb    r8,[r10,r8]             @ Td4[s2>>0]
        and     r9,lr,r2,lsr#16
-        ldrb    r2,[r10,r2,lsr#24]      @ Td4[s2>>24]
+ ARM(   ldrb    r2,[r10,r2,lsr#24]  )   @ Td4[s2>>24]
+ THUMB( add     r2,r10,r2,lsr#24    )   @ Td4[s2>>24]
+ THUMB( ldrb    r2,[r2]             )
        eor     r0,r0,r7,lsl#8
        ldrb    r9,[r10,r9]             @ Td4[s2>>16]
        eor     r1,r8,r1,lsl#16
@@ -1090,7 +1064,9 @@ _armv4_AES_decrypt:
        and     r9,lr,r3                @ i2
        ldrb    r9,[r10,r9]             @ Td4[s3>>0]
-        ldrb    r3,[r10,r3,lsr#24]      @ Td4[s3>>24]
+ ARM(   ldrb    r3,[r10,r3,lsr#24]  )   @ Td4[s3>>24]
+ THUMB( add     r3,r10,r3,lsr#24    )   @ Td4[s3>>24]
+ THUMB( ldrb    r3,[r3]             )
        eor     r0,r0,r7,lsl#16
        ldr     r7,[r11,#0]
        eor     r1,r1,r8,lsl#8
diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
index 7050ab133b9d..92c6eed7aac9 100644
--- a/arch/arm/crypto/sha1-armv4-large.S
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -51,13 +51,12 @@
 @ Profiler-assisted and platform-specific optimization resulted in 10%
 @ improvement on Cortex A8 core and 12.2 cycles per byte.
-.text
+#include <linux/linkage.h>
-.global sha1_block_data_order
+.text
-.type   sha1_block_data_order,%function
 .align  2
-sha1_block_data_order:
+ENTRY(sha1_block_data_order)
        stmdb   sp!,{r4-r12,lr}
        add     r2,r1,r2,lsl#6  @ r2 to point at the end of r1
        ldmia   r0,{r3,r4,r5,r6,r7}
@@ -194,7 +193,7 @@ sha1_block_data_order:
        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
        str     r9,[r14,#-4]!
        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
-        teq     r14,sp
+        cmp     r14,sp
        bne     .L_00_15                @ [((11+4)*5+2)*3]
 #if __ARM_ARCH__<7
        ldrb    r10,[r1,#2]
@@ -374,7 +373,9 @@ sha1_block_data_order:
                                                @ F_xx_xx
        add     r3,r3,r9                        @ E+=X[i]
        add     r3,r3,r10                       @ E+=F_20_39(B,C,D)
-        teq     r14,sp                  @ preserve carry
+ ARM(   teq     r14,sp          )       @ preserve carry
+ THUMB( mov     r11,sp          )
+ THUMB( teq     r14,r11         )       @ preserve carry
        bne     .L_20_39_or_60_79       @ [+((12+3)*5+2)*4]
        bcs     .L_done                 @ [+((12+3)*5+2)*4], spare 300 bytes
@@ -466,7 +467,7 @@ sha1_block_data_order:
        add     r3,r3,r9                        @ E+=X[i]
        add     r3,r3,r10                       @ E+=F_40_59(B,C,D)
        add     r3,r3,r11,ror#2
-        teq     r14,sp
+        cmp     r14,sp
        bne     .L_40_59                @ [+((12+5)*5+2)*4]
        ldr     r8,.LK_60_79
@@ -485,19 +486,12 @@ sha1_block_data_order:
        teq     r1,r2
        bne     .Lloop                  @ [+18], total 1307
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
 .align  2
 .LK_00_19:      .word   0x5a827999
 .LK_20_39:      .word   0x6ed9eba1
 .LK_40_59:      .word   0x8f1bbcdc
 .LK_60_79:      .word   0xca62c1d6
-.size   sha1_block_data_order,.-sha1_block_data_order
+ENDPROC(sha1_block_data_order)
 .asciz  "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
 .align  2
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index eb87200aa4b5..05ee9eebad6b 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -246,18 +246,14 @@
 *
 * This macro is intended for forcing the CPU into SVC mode at boot time.
 * you cannot return to the original mode.
- *
- * Beware, it also clobers LR.
 */
 .macro safe_svcmode_maskall reg:req
 #if __LINUX_ARM_ARCH__ >= 6
        mrs     \reg , cpsr
-        mov     lr , \reg
+        eor     \reg, \reg, #HYP_MODE
-        and     lr , lr , #MODE_MASK
+        tst     \reg, #MODE_MASK
-        cmp     lr , #HYP_MODE
-        orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT
        bic     \reg , \reg , #MODE_MASK
-        orr     \reg , \reg , #SVC_MODE
+        orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
 THUMB(  orr     \reg , \reg , #PSR_T_BIT        )
        bne     1f
        orr     \reg, \reg, #PSR_A_BIT
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index f2e5cad3f306..2381199acb7d 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,6 +2,7 @@
 #define __ASMARM_CTI_H
 #include        <asm/io.h>
+#include        <asm/hardware/coresight.h>
 /* The registers' definition is from section 3.2 of
 * Embedded Cross Trigger Revision: r0p0
@@ -35,11 +36,6 @@
 #define         LOCKACCESS              0xFB0
 #define         LOCKSTATUS              0xFB4
-/* write this value to LOCKACCESS will unlock the module, and
- * other value will lock the module
- */
-#define         LOCKCODE                0xC5ACCE55
 /**
 * struct cti - cross trigger interface struct
 * @base: mapped virtual address for the cti base
@@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
 */
 static inline void cti_unlock(struct cti *cti)
 {
-        __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 /**
@@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
 */
 static inline void cti_lock(struct cti *cti)
 {
-        __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 #endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 5694a0d6576b..58b8c6a0ab1f 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -105,7 +105,7 @@ extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
 */
 extern void __set_dma_addr(unsigned int chan, void *addr);
 #define set_dma_addr(chan, addr)                                \
-        __set_dma_addr(chan, bus_to_virt(addr))
+        __set_dma_addr(chan, (void *)__bus_to_virt(addr))
 /* Set the DMA byte count for this channel
 *
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793b8f5a..0cf7a6b842ff 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -36,7 +36,7 @@
 /* CoreSight Component Registers */
 #define CSCR_CLASS      0xff4
-#define UNLOCK_MAGIC    0xc5acce55
+#define CS_LAR_KEY      0xc5acce55
 /* ETM control register, "ETM Architecture", 3.3.1 */
 #define ETMR_CTRL               0
@@ -147,11 +147,11 @@
 #define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etm_unlock(t) \
-        do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etb_unlock(t) \
-        do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 #endif /* __ASM_HARDWARE_CORESIGHT_H */
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
deleted file mode 100644
index 6636430dd0e6..000000000000
--- a/arch/arm/include/asm/hardware/sp810.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/sp810.h
- *
- * ARM PrimeXsys System Controller SP810 header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARM_SP810_H
-#define __ASM_ARM_SP810_H
-#include <linux/io.h>
-/* sysctl registers offset */
-#define SCCTRL                  0x000
-#define SCSYSSTAT               0x004
-#define SCIMCTRL                0x008
-#define SCIMSTAT                0x00C
-#define SCXTALCTRL              0x010
-#define SCPLLCTRL               0x014
-#define SCPLLFCTRL              0x018
-#define SCPERCTRL0              0x01C
-#define SCPERCTRL1              0x020
-#define SCPEREN                 0x024
-#define SCPERDIS                0x028
-#define SCPERCLKEN              0x02C
-#define SCPERSTAT               0x030
-#define SCSYSID0                0xEE0
-#define SCSYSID1                0xEE4
-#define SCSYSID2                0xEE8
-#define SCSYSID3                0xEEC
-#define SCITCR                  0xF00
-#define SCITIR0                 0xF04
-#define SCITIR1                 0xF08
-#define SCITOR                  0xF0C
-#define SCCNTCTRL               0xF10
-#define SCCNTDATA               0xF14
-#define SCCNTSTEP               0xF18
-#define SCPERIPHID0             0xFE0
-#define SCPERIPHID1             0xFE4
-#define SCPERIPHID2             0xFE8
-#define SCPERIPHID3             0xFEC
-#define SCPCELLID0              0xFF0
-#define SCPCELLID1              0xFF4
-#define SCPCELLID2              0xFF8
-#define SCPCELLID3              0xFFC
-#define SCCTRL_TIMERENnSEL_SHIFT(n)     (15 + ((n) * 2))
-static inline void sysctl_soft_reset(void __iomem *base)
-{
-        /* switch to slow mode */
-        writel(0x2, base + SCCTRL);
-        /* writing any value to SCSYSSTAT reg will reset system */
-        writel(0, base + SCSYSSTAT);
-}
-#endif  /* __ASM_ARM_SP810_H */
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 01169dd723f1..eef55ea9ef00 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DSCR_HDBGEN         (1 << 14)
 #define ARM_DSCR_MDBGEN         (1 << 15)
+/* OSLSR os lock model bits */
+#define ARM_OSLSR_OSLM0         (1 << 0)
 /* opcode2 numbers for the co-processor instructions. */
 #define ARM_OP2_BVR             4
 #define ARM_OP2_BCR             5
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index bf863edb517d..1a66f907e5cc 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -8,6 +8,7 @@
 #define __idmap __section(.idmap.text) noinline notrace
 extern pgd_t *idmap_pgd;
+extern pgd_t *hyp_pgd;
 void setup_mm_for_reboot(void);
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
new file mode 100644
index 000000000000..7c3d813e15df
--- /dev/null
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_ARM_H__
+#define __ARM_KVM_ARM_H__
+#include <linux/types.h>
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_TGE         (1 << 27)
+#define HCR_TVM         (1 << 26)
+#define HCR_TTLB        (1 << 25)
+#define HCR_TPU         (1 << 24)
+#define HCR_TPC         (1 << 23)
+#define HCR_TSW         (1 << 22)
+#define HCR_TAC         (1 << 21)
+#define HCR_TIDCP       (1 << 20)
+#define HCR_TSC         (1 << 19)
+#define HCR_TID3        (1 << 18)
+#define HCR_TID2        (1 << 17)
+#define HCR_TID1        (1 << 16)
+#define HCR_TID0        (1 << 15)
+#define HCR_TWE         (1 << 14)
+#define HCR_TWI         (1 << 13)
+#define HCR_DC          (1 << 12)
+#define HCR_BSU         (3 << 10)
+#define HCR_BSU_IS      (1 << 10)
+#define HCR_FB          (1 << 9)
+#define HCR_VA          (1 << 8)
+#define HCR_VI          (1 << 7)
+#define HCR_VF          (1 << 6)
+#define HCR_AMO         (1 << 5)
+#define HCR_IMO         (1 << 4)
+#define HCR_FMO         (1 << 3)
+#define HCR_PTW         (1 << 2)
+#define HCR_SWIO        (1 << 1)
+#define HCR_VM          1
+/*
+ * The bits we set in HCR:
+ * TAC:         Trap ACTLR
+ * TSC:         Trap SMC
+ * TSW:         Trap cache operations by set/way
+ * TWI:         Trap WFI
+ * TIDCP:       Trap L2CTLR/L2ECTLR
+ * BSU_IS:      Upgrade barriers to the inner shareable domain
+ * FB:          Force broadcast of all maintainance operations
+ * AMO:         Override CPSR.A and enable signaling with VA
+ * IMO:         Override CPSR.I and enable signaling with VI
+ * FMO:         Override CPSR.F and enable signaling with VF
+ * SWIO:        Turn set/way invalidates into set/way clean+invalidate
+ */
+#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
+                        HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
+                        HCR_SWIO | HCR_TIDCP)
+#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
+/* System Control Register (SCTLR) bits */
+#define SCTLR_TE        (1 << 30)
+#define SCTLR_EE        (1 << 25)
+#define SCTLR_V         (1 << 13)
+/* Hyp System Control Register (HSCTLR) bits */
+#define HSCTLR_TE       (1 << 30)
+#define HSCTLR_EE       (1 << 25)
+#define HSCTLR_FI       (1 << 21)
+#define HSCTLR_WXN      (1 << 19)
+#define HSCTLR_I        (1 << 12)
+#define HSCTLR_C        (1 << 2)
+#define HSCTLR_A        (1 << 1)
+#define HSCTLR_M        1
+#define HSCTLR_MASK     (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
+                         HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
+/* TTBCR and HTCR Registers bits */
+#define TTBCR_EAE       (1 << 31)
+#define TTBCR_IMP       (1 << 30)
+#define TTBCR_SH1       (3 << 28)
+#define TTBCR_ORGN1     (3 << 26)
+#define TTBCR_IRGN1     (3 << 24)
+#define TTBCR_EPD1      (1 << 23)
+#define TTBCR_A1        (1 << 22)
+#define TTBCR_T1SZ      (3 << 16)
+#define TTBCR_SH0       (3 << 12)
+#define TTBCR_ORGN0     (3 << 10)
+#define TTBCR_IRGN0     (3 << 8)
+#define TTBCR_EPD0      (1 << 7)
+#define TTBCR_T0SZ      3
+#define HTCR_MASK       (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
+/* Hyp System Trap Register */
+#define HSTR_T(x)       (1 << x)
+#define HSTR_TTEE       (1 << 16)
+#define HSTR_TJDBX      (1 << 17)
+/* Hyp Coprocessor Trap Register */
+#define HCPTR_TCP(x)    (1 << x)
+#define HCPTR_TCP_MASK  (0x3fff)
+#define HCPTR_TASE      (1 << 15)
+#define HCPTR_TTA       (1 << 20)
+#define HCPTR_TCPAC     (1 << 31)
+/* Hyp Debug Configuration Register bits */
+#define HDCR_TDRA       (1 << 11)
+#define HDCR_TDOSA      (1 << 10)
+#define HDCR_TDA        (1 << 9)
+#define HDCR_TDE        (1 << 8)
+#define HDCR_HPME       (1 << 7)
+#define HDCR_TPM        (1 << 6)
+#define HDCR_TPMCR      (1 << 5)
+#define HDCR_HPMN_MASK  (0x1F)
+/*
+ * The architecture supports 40-bit IPA as input to the 2nd stage translations
+ * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
+ * space.
+ */
+#define KVM_PHYS_SHIFT  (40)
+#define KVM_PHYS_SIZE   (1ULL << KVM_PHYS_SHIFT)
+#define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1ULL)
+#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
+#define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
+#define S2_PGD_SIZE     (1 << S2_PGD_ORDER)
+/* Virtualization Translation Control Register (VTCR) bits */
+#define VTCR_SH0        (3 << 12)
+#define VTCR_ORGN0      (3 << 10)
+#define VTCR_IRGN0      (3 << 8)
+#define VTCR_SL0        (3 << 6)
+#define VTCR_S          (1 << 4)
+#define VTCR_T0SZ       (0xf)
+#define VTCR_MASK       (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
+                         VTCR_S | VTCR_T0SZ)
+#define VTCR_HTCR_SH    (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
+#define VTCR_SL_L2      (0 << 6)        /* Starting-level: 2 */
+#define VTCR_SL_L1      (1 << 6)        /* Starting-level: 1 */
+#define KVM_VTCR_SL0    VTCR_SL_L1
+/* stage-2 input address range defined as 2^(32-T0SZ) */
+#define KVM_T0SZ        (32 - KVM_PHYS_SHIFT)
+#define KVM_VTCR_T0SZ   (KVM_T0SZ & VTCR_T0SZ)
+#define KVM_VTCR_S      ((KVM_VTCR_T0SZ << 1) & VTCR_S)
+/* Virtualization Translation Table Base Register (VTTBR) bits */
+#if KVM_VTCR_SL0 == VTCR_SL_L2  /* see ARM DDI 0406C: B4-1720 */
+#define VTTBR_X         (14 - KVM_T0SZ)
+#else
+#define VTTBR_X         (5 - KVM_T0SZ)
+#endif
+#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
+#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
+/* Hyp Syndrome Register (HSR) bits */
+#define HSR_EC_SHIFT    (26)
+#define HSR_EC          (0x3fU << HSR_EC_SHIFT)
+#define HSR_IL          (1U << 25)
+#define HSR_ISS         (HSR_IL - 1)
+#define HSR_ISV_SHIFT   (24)
+#define HSR_ISV         (1U << HSR_ISV_SHIFT)
+#define HSR_SRT_SHIFT   (16)
+#define HSR_SRT_MASK    (0xf << HSR_SRT_SHIFT)
+#define HSR_FSC         (0x3f)
+#define HSR_FSC_TYPE    (0x3c)
+#define HSR_SSE         (1 << 21)
+#define HSR_WNR         (1 << 6)
+#define HSR_CV_SHIFT    (24)
+#define HSR_CV          (1U << HSR_CV_SHIFT)
+#define HSR_COND_SHIFT  (20)
+#define HSR_COND        (0xfU << HSR_COND_SHIFT)
+#define FSC_FAULT       (0x04)
+#define FSC_PERM        (0x0c)
+/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
+#define HPFAR_MASK      (~0xf)
+#define HSR_EC_UNKNOWN  (0x00)
+#define HSR_EC_WFI      (0x01)
+#define HSR_EC_CP15_32  (0x03)
+#define HSR_EC_CP15_64  (0x04)
+#define HSR_EC_CP14_MR  (0x05)
+#define HSR_EC_CP14_LS  (0x06)
+#define HSR_EC_CP_0_13  (0x07)
+#define HSR_EC_CP10_ID  (0x08)
+#define HSR_EC_JAZELLE  (0x09)
+#define HSR_EC_BXJ      (0x0A)
+#define HSR_EC_CP14_64  (0x0C)
+#define HSR_EC_SVC_HYP  (0x11)
+#define HSR_EC_HVC      (0x12)
+#define HSR_EC_SMC      (0x13)
+#define HSR_EC_IABT     (0x20)
+#define HSR_EC_IABT_HYP (0x21)
+#define HSR_EC_DABT     (0x24)
+#define HSR_EC_DABT_HYP (0x25)
+#define HSR_HVC_IMM_MASK        ((1UL << 16) - 1)
+#endif /* __ARM_KVM_ARM_H__ */
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..5e06e8177784
--- /dev/null
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_ASM_H__
+#define __ARM_KVM_ASM_H__
+/* 0 is reserved as an invalid value. */
+#define c0_MPIDR        1       /* MultiProcessor ID Register */
+#define c0_CSSELR       2       /* Cache Size Selection Register */
+#define c1_SCTLR        3       /* System Control Register */
+#define c1_ACTLR        4       /* Auxilliary Control Register */
+#define c1_CPACR        5       /* Coprocessor Access Control */
+#define c2_TTBR0        6       /* Translation Table Base Register 0 */
+#define c2_TTBR0_high   7       /* TTBR0 top 32 bits */
+#define c2_TTBR1        8       /* Translation Table Base Register 1 */
+#define c2_TTBR1_high   9       /* TTBR1 top 32 bits */
+#define c2_TTBCR        10      /* Translation Table Base Control R. */
+#define c3_DACR         11      /* Domain Access Control Register */
+#define c5_DFSR         12      /* Data Fault Status Register */
+#define c5_IFSR         13      /* Instruction Fault Status Register */
+#define c5_ADFSR        14      /* Auxilary Data Fault Status R */
+#define c5_AIFSR        15      /* Auxilary Instrunction Fault Status R */
+#define c6_DFAR         16      /* Data Fault Address Register */
+#define c6_IFAR         17      /* Instruction Fault Address Register */
+#define c9_L2CTLR       18      /* Cortex A15 L2 Control Register */
+#define c10_PRRR        19      /* Primary Region Remap Register */
+#define c10_NMRR        20      /* Normal Memory Remap Register */
+#define c12_VBAR        21      /* Vector Base Address Register */
+#define c13_CID         22      /* Context ID Register */
+#define c13_TID_URW     23      /* Thread ID, User R/W */
+#define c13_TID_URO     24      /* Thread ID, User R/O */
+#define c13_TID_PRIV    25      /* Thread ID, Privileged */
+#define NR_CP15_REGS    26      /* Number of regs (incl. invalid) */
+#define ARM_EXCEPTION_RESET       0
+#define ARM_EXCEPTION_UNDEFINED   1
+#define ARM_EXCEPTION_SOFTWARE    2
+#define ARM_EXCEPTION_PREF_ABORT  3
+#define ARM_EXCEPTION_DATA_ABORT  4
+#define ARM_EXCEPTION_IRQ         5
+#define ARM_EXCEPTION_FIQ         6
+#define ARM_EXCEPTION_HVC         7
+#ifndef __ASSEMBLY__
+struct kvm;
+struct kvm_vcpu;
+extern char __kvm_hyp_init[];
+extern char __kvm_hyp_init_end[];
+extern char __kvm_hyp_exit[];
+extern char __kvm_hyp_exit_end[];
+extern char __kvm_hyp_vector[];
+extern char __kvm_hyp_code_start[];
+extern char __kvm_hyp_code_end[];
+extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
+extern void __kvm_flush_vm_context(void);
+extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
+extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+#endif
+#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h
new file mode 100644
index 000000000000..4917c2f7e459
--- /dev/null
+++ b/arch/arm/include/asm/kvm_coproc.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Rusty Russell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_COPROC_H__
+#define __ARM_KVM_COPROC_H__
+#include <linux/kvm_host.h>
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
+struct kvm_coproc_target_table {
+        unsigned target;
+        const struct coproc_reg *table;
+        size_t num;
+};
+void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table);
+int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
+unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+void kvm_coproc_table_init(void);
+struct kvm_one_reg;
+int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
+#endif /* __ARM_KVM_COPROC_H__ */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
new file mode 100644
index 000000000000..fd611996bfb5
--- /dev/null
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_EMULATE_H__
+#define __ARM_KVM_EMULATE_H__
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu);
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
+void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
+void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
+static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
+{
+        return 1;
+}
+static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
+{
+        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc;
+}
+static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu)
+{
+        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr;
+}
+static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
+{
+        *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+}
+static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
+        return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
+}
+static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
+        return cpsr_mode > USR_MODE;;
+}
+static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
+{
+        return reg == 15;
+}
+#endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
new file mode 100644
index 000000000000..98b4d1a72923
--- /dev/null
+++ b/arch/arm/include/asm/kvm_host.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_HOST_H__
+#define __ARM_KVM_HOST_H__
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+#include <asm/fpstate.h>
+#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#define KVM_MEMORY_SLOTS 32
+#define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+#define KVM_HAVE_ONE_REG
+#define KVM_VCPU_MAX_FEATURES 1
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)  0
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
+struct kvm_vcpu;
+u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
+struct kvm_arch {
+        /* VTTBR value associated with below pgd and vmid */
+        u64    vttbr;
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* The VMID generation used for the virt. memory system */
+        u64    vmid_gen;
+        u32    vmid;
+        /* Stage-2 page table */
+        pgd_t *pgd;
+};
+#define KVM_NR_MEM_OBJS     40
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+        int nobjs;
+        void *objects[KVM_NR_MEM_OBJS];
+};
+struct kvm_vcpu_arch {
+        struct kvm_regs regs;
+        int target; /* Processor target */
+        DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
+        /* System control coprocessor (cp15) */
+        u32 cp15[NR_CP15_REGS];
+        /* The CPU type we expose to the VM */
+        u32 midr;
+        /* Exception Information */
+        u32 hsr;                /* Hyp Syndrome Register */
+        u32 hxfar;              /* Hyp Data/Inst Fault Address Register */
+        u32 hpfar;              /* Hyp IPA Fault Address Register */
+        /* Floating point registers (VFP and Advanced SIMD/NEON) */
+        struct vfp_hard_struct vfp_guest;
+        struct vfp_hard_struct *vfp_host;
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* dcache set/way operation pending */
+        int last_pcpu;
+        cpumask_t require_dcache_flush;
+        /* Don't run the guest on this vcpu */
+        bool pause;
+        /* IO related fields */
+        struct kvm_decode mmio_decode;
+        /* Interrupt related fields */
+        u32 irq_lines;          /* IRQ and FIQ levels */
+        /* Hyp exception information */
+        u32 hyp_pc;             /* PC when exception was taken from Hyp mode */
+        /* Cache some mmu pages needed inside spinlock regions */
+        struct kvm_mmu_memory_cache mmu_page_cache;
+        /* Detect first run of a vcpu */
+        bool has_run_once;
+};
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+struct kvm_vcpu_stat {
+        u32 halt_wakeup;
+};
+struct kvm_vcpu_init;
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+struct kvm_one_reg;
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+u64 kvm_call_hyp(void *hypfn, ...);
+void force_vm_exit(const cpumask_t *mask);
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+struct kvm;
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+/* We do not have shadow page tables, hence the empty hooks */
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h
new file mode 100644
index 000000000000..adcc0d7d3175
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmio.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_MMIO_H__
+#define __ARM_KVM_MMIO_H__
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+struct kvm_decode {
+        unsigned long rt;
+        bool sign_extend;
+};
+/*
+ * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
+ * which is an anonymous type. Use our own type instead.
+ */
+struct kvm_exit_mmio {
+        phys_addr_t     phys_addr;
+        u8              data[8];
+        u32             len;
+        bool            is_write;
+};
+static inline void kvm_prepare_mmio(struct kvm_run *run,
+                                    struct kvm_exit_mmio *mmio)
+{
+        run->mmio.phys_addr     = mmio->phys_addr;
+        run->mmio.len           = mmio->len;
+        run->mmio.is_write      = mmio->is_write;
+        memcpy(run->mmio.data, mmio->data, mmio->len);
+        run->exit_reason        = KVM_EXIT_MMIO;
+}
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa);
+#endif  /* __ARM_KVM_MMIO_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
new file mode 100644
index 000000000000..421a20b34874
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_MMU_H__
+#define __ARM_KVM_MMU_H__
+int create_hyp_mappings(void *from, void *to);
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+void free_hyp_pmds(void);
+int kvm_alloc_stage2_pgd(struct kvm *kvm);
+void kvm_free_stage2_pgd(struct kvm *kvm);
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size);
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+phys_addr_t kvm_mmu_get_httbr(void);
+int kvm_mmu_init(void);
+void kvm_clear_hyp_idmap(void);
+static inline bool kvm_is_write_fault(unsigned long hsr)
+{
+        unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
+        if (hsr_ec == HSR_EC_IABT)
+                return false;
+        else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
+                return false;
+        else
+                return true;
+}
+#endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h
new file mode 100644
index 000000000000..9a83d98bf170
--- /dev/null
+++ b/arch/arm/include/asm/kvm_psci.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ARM_KVM_PSCI_H__
+#define __ARM_KVM_PSCI_H__
+bool kvm_psci_call(struct kvm_vcpu *vcpu);
+#endif /* __ARM_KVM_PSCI_H__ */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index db9fedb57f2c..5cf2e979b4be 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -23,6 +23,7 @@ struct hw_pci {
 #endif
        struct pci_ops  *ops;
        int             nr_controllers;
+        void            **private_data;
        int             (*setup)(int nr, struct pci_sys_data *);
        struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
        void            (*preinit)(void);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 1c4df27f9332..57870ab313c5 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -36,23 +36,23 @@
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
 */
 #define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
-#define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
+#define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
 #define TASK_UNMAPPED_BASE      ALIGN(TASK_SIZE / 3, SZ_16M)
 /*
 * The maximum size of a 26-bit user space task.
 */
-#define TASK_SIZE_26            UL(0x04000000)
+#define TASK_SIZE_26            (UL(1) << 26)
 /*
 * The module space lives between the addresses given by TASK_SIZE
 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
 */
 #ifndef CONFIG_THUMB2_KERNEL
-#define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
+#define MODULES_VADDR           (PAGE_OFFSET - SZ_16M)
 #else
 /* smaller range for Thumb-2 symbols relocation (2^24)*/
-#define MODULES_VADDR           (PAGE_OFFSET - 8*1024*1024)
+#define MODULES_VADDR           (PAGE_OFFSET - SZ_8M)
 #endif
 #if TASK_SIZE > MODULES_VADDR
@@ -245,6 +245,7 @@ static inline void *phys_to_virt(phys_addr_t x)
 #define __bus_to_pfn(x) __phys_to_pfn(x)
 #endif
+#ifdef CONFIG_VIRT_TO_BUS
 static inline __deprecated unsigned long virt_to_bus(void *x)
 {
        return __virt_to_bus((unsigned long)x);
@@ -254,6 +255,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 {
        return (void *)__bus_to_virt(x);
 }
+#endif
 /*
 * Conversion between a struct page and a physical address.
diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h
new file mode 100644
index 000000000000..bc3a9174417c
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-sec.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+#ifndef __ASM_ARM_OPCODES_SEC_H
+#define __ASM_ARM_OPCODES_SEC_H
+#include <asm/opcodes.h>
+#define __SMC(imm4) __inst_arm_thumb32(                                 \
+        0xE1600070 | (((imm4) & 0xF) << 0),                             \
+        0xF7F08000 | (((imm4) & 0xF) << 16)                             \
+)
+#endif /* __ASM_ARM_OPCODES_SEC_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 74e211a6fb24..e796c598513b 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -10,6 +10,7 @@
 #define __ASM_ARM_OPCODES_H
 #ifndef __ASSEMBLY__
+#include <linux/linkage.h>
 extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 #endif
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 53426c66352a..12f71a190422 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -92,6 +92,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
 static inline void outer_flush_all(void) { }
 static inline void outer_inv_all(void) { }
 static inline void outer_disable(void) { }
+static inline void outer_resume(void) { }
 #endif
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d7952824c5c4..18f5cef82ad5 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -32,6 +32,9 @@
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
 #define PMD_BIT4                (_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
+#define PMD_APTABLE_SHIFT       (61)
+#define PMD_APTABLE             (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
+#define PMD_PXNTABLE            (_AT(pgdval_t, 1) << 59)
 /*
 *   - section
@@ -41,9 +44,11 @@
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
+#define PMD_SECT_PXN            (_AT(pmdval_t, 1) << 53)
 #define PMD_SECT_XN             (_AT(pmdval_t, 1) << 54)
 #define PMD_SECT_AP_WRITE       (_AT(pmdval_t, 0))
 #define PMD_SECT_AP_READ        (_AT(pmdval_t, 0))
+#define PMD_SECT_AP1            (_AT(pmdval_t, 1) << 6)
 #define PMD_SECT_TEX(x)         (_AT(pmdval_t, 0))
 /*
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index a3f37929940a..6ef8afd1b64c 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -104,11 +104,29 @@
 */
 #define L_PGD_SWAPPER           (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
+/*
+ * 2nd stage PTE definitions for LPAE.
+ */
+#define L_PTE_S2_MT_UNCACHED     (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITEBACK    (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_RDONLY          (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_RDWR            (_AT(pteval_t, 2) << 6)   /* HAP[2:1] */
+/*
+ * Hyp-mode PL2 PTE definitions for LPAE.
+ */
+#define L_PTE_HYP               L_PTE_USER
 #ifndef __ASSEMBLY__
 #define pud_none(pud)           (!pud_val(pud))
 #define pud_bad(pud)            (!(pud_val(pud) & 2))
 #define pud_present(pud)        (pud_val(pud))
+#define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                                 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                                 PMD_TYPE_SECT)
 #define pud_clear(pudp)                 \
        do {                            \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9c82f988c0e3..f30ac3b55ba9 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
 extern pgprot_t         pgprot_user;
 extern pgprot_t         pgprot_kernel;
+extern pgprot_t         pgprot_hyp_device;
+extern pgprot_t         pgprot_s2;
+extern pgprot_t         pgprot_s2_device;
 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
@@ -82,6 +85,10 @@ extern pgprot_t		pgprot_kernel;
 #define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
 #define PAGE_KERNEL             _MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC        pgprot_kernel
+#define PAGE_HYP                _MOD_PROT(pgprot_kernel, L_PTE_HYP)
+#define PAGE_HYP_DEVICE         _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
+#define PAGE_S2                 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE          _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
 #define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
new file mode 100644
index 000000000000..ce0dbe7c1625
--- /dev/null
+++ b/arch/arm/include/asm/psci.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+#ifndef __ASM_ARM_PSCI_H
+#define __ASM_ARM_PSCI_H
+#define PSCI_POWER_STATE_TYPE_STANDBY           0
+#define PSCI_POWER_STATE_TYPE_POWER_DOWN        1
+struct psci_power_state {
+        u16     id;
+        u8      type;
+        u8      affinity_level;
+};
+struct psci_operations {
+        int (*cpu_suspend)(struct psci_power_state state,
+                           unsigned long entry_point);
+        int (*cpu_off)(struct psci_power_state state);
+        int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
+        int (*migrate)(unsigned long cpuid);
+};
+extern struct psci_operations psci_ops;
+#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 006f02681cd8..18d169373612 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -24,8 +24,14 @@ static inline unsigned long scu_a9_get_base(void)
 }
 unsigned int scu_get_core_count(void __iomem *);
-void scu_enable(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+#ifdef CONFIG_SMP
+void scu_enable(void __iomem *scu_base);
+#else
+static inline void scu_enable(void __iomem *scu_base) {}
+#endif
 #endif
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index b4ca707d0a69..6220e9fdf4c7 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
-        unsigned long tmp;
-        u32 slock;
        smp_mb();
+        lock->tickets.owner++;
-        __asm__ __volatile__(
-"       mov     %1, #1\n"
-"1:     ldrex   %0, [%2]\n"
-"       uadd16  %0, %0, %1\n"
-"       strex   %1, %0, [%2]\n"
-"       teq     %1, #0\n"
-"       bne     1b"
-        : "=&r" (slock), "=&r" (tmp)
-        : "r" (&lock->slock)
-        : "cc");
        dsb_sev();
 }
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 86164df86cb4..50af92bac737 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -24,9 +24,9 @@
 /*
 * Flag indicating that the kernel was not entered in the same mode on every
 * CPU.  The zImage loader stashes this value in an SPSR, so we need an
- * architecturally defined flag bit here (the N flag, as it happens)
+ * architecturally defined flag bit here.
 */
-#define BOOT_CPU_MODE_MISMATCH (1<<31)
+#define BOOT_CPU_MODE_MISMATCH  PSR_N_BIT
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/include/debug/omap2plus.S
index cfaed13d0040..6d867aef18eb 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/omap2plus.S
@@ -1,5 +1,4 @@
-/* arch/arm/mach-omap2/include/mach/debug-macro.S
+/*
- *
 * Debugging macro include header
 *
 *  Copyright (C) 1994-1999 Russell King
@@ -13,7 +12,49 @@
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
+/* OMAP2 serial ports */
+#define OMAP2_UART1_BASE        0x4806a000
+#define OMAP2_UART2_BASE        0x4806c000
+#define OMAP2_UART3_BASE        0x4806e000
+/* OMAP3 serial ports */
+#define OMAP3_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP3_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP3_UART3_BASE        0x49020000
+#define OMAP3_UART4_BASE        0x49042000      /* Only on 36xx */
+#define OMAP3_UART4_AM35XX_BASE 0x4809E000      /* Only on AM35xx */
+/* OMAP4 serial ports */
+#define OMAP4_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP4_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP4_UART3_BASE        0x48020000
+#define OMAP4_UART4_BASE        0x4806e000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE       0x48020000
+#define TI81XX_UART2_BASE       0x48022000
+#define TI81XX_UART3_BASE       0x48024000
+/* AM3505/3517 UART4 */
+#define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE       0x44E09000
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE        OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE        OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE        0x48066000
+#define OMAP5_UART6_BASE        0x48068000
+/* External port on Zoom2/3 */
+#define ZOOM_UART_BASE          0x10000000
+#define ZOOM_UART_VIRT          0xfa400000
+#define OMAP_PORT_SHIFT         2
+#define ZOOM_PORT_SHIFT         1
 #define UART_OFFSET(addr)       ((addr) & 0x00ffffff)
@@ -23,12 +64,6 @@ omap_uart_virt:	.word	0
 omap_uart_lsr:  .word   0
                .popsection
-                /*
-                 * Note that this code won't work if the bootloader passes
-                 * a wrong machine ID number in r1. To debug, just hardcode
-                 * the desired UART phys and virt addresses temporarily into
-                 * the omap_uart_phys and omap_uart_virt above.
-                 */
                .macro  addruart, rp, rv, tmp
                /* Use omap_uart_phys/virt if already configured */
@@ -43,74 +78,64 @@ omap_uart_lsr:	.word	0
                cmpne   \rv, #0
                bne     100f                    @ already configured
-                /* Check the debug UART configuration set in uncompress.h */
-                mov     \rp, pc
-                ldr     \rv, =OMAP_UART_INFO_OFS
-                and     \rp, \rp, #0xff000000
-                ldr     \rp, [\rp, \rv]
-                /* Select the UART to use based on the UART1 scratchpad value */
-                cmp     \rp, #0                 @ no port configured?
-                beq     21f                     @ if none, try to use UART1
-                cmp     \rp, #OMAP2UART1        @ OMAP2/3/4UART1
-                beq     21f                     @ configure OMAP2/3/4UART1
-                cmp     \rp, #OMAP2UART2        @ OMAP2/3/4UART2
-                beq     22f                     @ configure OMAP2/3/4UART2
-                cmp     \rp, #OMAP2UART3        @ only on 24xx
-                beq     23f                     @ configure OMAP2UART3
-                cmp     \rp, #OMAP3UART3        @ only on 34xx
-                beq     33f                     @ configure OMAP3UART3
-                cmp     \rp, #OMAP4UART3        @ only on 44xx/54xx
-                beq     43f                     @ configure OMAP4/5UART3
-                cmp     \rp, #OMAP3UART4        @ only on 36xx
-                beq     34f                     @ configure OMAP3UART4
-                cmp     \rp, #OMAP4UART4        @ only on 44xx/54xx
-                beq     44f                     @ configure OMAP4/5UART4
-                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
-                beq     81f                     @ configure UART1
-                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
-                beq     82f                     @ configure UART2
-                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
-                beq     83f                     @ configure UART3
-                cmp     \rp, #AM33XXUART1       @ AM33XX UART offsets different
-                beq     84f                     @ configure UART1
-                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
-                beq     95f                     @ configure ZOOM_UART
                /* Configure the UART offset from the phys/virt base */
-21:             mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
+#ifdef CONFIG_DEBUG_OMAP2UART1
+                mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
                b       98f
-22:             mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART2
+                mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
                b       98f
-23:             mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART3
+                mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
                b       98f
-33:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART3
+                mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
                add     \rp, \rp, #0x00fb0000
                add     \rp, \rp, #0x00006000           @ OMAP3_UART3_BASE
                b       98f
-34:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP4UART3
+                mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
+                b       98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART4
+                mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
                add     \rp, \rp, #0x00fb0000
                add     \rp, \rp, #0x00028000           @ OMAP3_UART4_BASE
                b       98f
-43:             mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
+#endif
-                b       98f
+#ifdef CONFIG_DEBUG_OMAP4UART4
-44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
+                mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                b       98f
-81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART1
+                mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                b       98f
-82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART2
+                mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                b       98f
-83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART3
+                mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                b       98f
-84:             ldr     \rp, =AM33XX_UART1_BASE
+#endif
+#ifdef CONFIG_DEBUG_AM33XXUART1
+                ldr     \rp, =AM33XX_UART1_BASE
                and     \rp, \rp, #0x00ffffff
                b       97f
-95:             ldr     \rp, =ZOOM_UART_BASE
+#endif
+#ifdef CONFIG_DEBUG_ZOOM_UART
+                ldr     \rp, =ZOOM_UART_BASE
                str     \rp, [\tmp, #0]         @ omap_uart_phys
                ldr     \rp, =ZOOM_UART_VIRT
                str     \rp, [\tmp, #4]         @ omap_uart_virt
                mov     \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
                str     \rp, [\tmp, #8]         @ omap_uart_lsr
+#endif
                b       10b
                /* AM33XX: Store both phys and virt address for the uart */
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..3303ff5adbf3
--- /dev/null
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+#define KVM_REG_SIZE(id)                                                \
+        (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
+#define KVM_ARM_SVC_sp          svc_regs[0]
+#define KVM_ARM_SVC_lr          svc_regs[1]
+#define KVM_ARM_SVC_spsr        svc_regs[2]
+#define KVM_ARM_ABT_sp          abt_regs[0]
+#define KVM_ARM_ABT_lr          abt_regs[1]
+#define KVM_ARM_ABT_spsr        abt_regs[2]
+#define KVM_ARM_UND_sp          und_regs[0]
+#define KVM_ARM_UND_lr          und_regs[1]
+#define KVM_ARM_UND_spsr        und_regs[2]
+#define KVM_ARM_IRQ_sp          irq_regs[0]
+#define KVM_ARM_IRQ_lr          irq_regs[1]
+#define KVM_ARM_IRQ_spsr        irq_regs[2]
+/* Valid only for fiq_regs in struct kvm_regs */
+#define KVM_ARM_FIQ_r8          fiq_regs[0]
+#define KVM_ARM_FIQ_r9          fiq_regs[1]
+#define KVM_ARM_FIQ_r10         fiq_regs[2]
+#define KVM_ARM_FIQ_fp          fiq_regs[3]
+#define KVM_ARM_FIQ_ip          fiq_regs[4]
+#define KVM_ARM_FIQ_sp          fiq_regs[5]
+#define KVM_ARM_FIQ_lr          fiq_regs[6]
+#define KVM_ARM_FIQ_spsr        fiq_regs[7]
+struct kvm_regs {
+        struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
+        __u32 svc_regs[3];      /* SP_svc, LR_svc, SPSR_svc */
+        __u32 abt_regs[3];      /* SP_abt, LR_abt, SPSR_abt */
+        __u32 und_regs[3];      /* SP_und, LR_und, SPSR_und */
+        __u32 irq_regs[3];      /* SP_irq, LR_irq, SPSR_irq */
+        __u32 fiq_regs[8];      /* R8_fiq - R14_fiq, SPSR_fiq */
+};
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_CORTEX_A15       0
+#define KVM_ARM_NUM_TARGETS             1
+#define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
+struct kvm_vcpu_init {
+        __u32 target;
+        __u32 features[7];
+};
+struct kvm_sregs {
+};
+struct kvm_fpu {
+};
+struct kvm_guest_debug_arch {
+};
+struct kvm_debug_exit_arch {
+};
+struct kvm_sync_regs {
+};
+struct kvm_arch_memory_slot {
+};
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT        16
+#define KVM_REG_ARM_32_OPC2_MASK        0x0000000000000007
+#define KVM_REG_ARM_32_OPC2_SHIFT       0
+#define KVM_REG_ARM_OPC1_MASK           0x0000000000000078
+#define KVM_REG_ARM_OPC1_SHIFT          3
+#define KVM_REG_ARM_CRM_MASK            0x0000000000000780
+#define KVM_REG_ARM_CRM_SHIFT           7
+#define KVM_REG_ARM_32_CRN_MASK         0x0000000000007800
+#define KVM_REG_ARM_32_CRN_SHIFT        11
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / 4)
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT      8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
+/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
+#define KVM_REG_ARM_VFP                 (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_VFP_MASK            0x000000000000FFFF
+#define KVM_REG_ARM_VFP_BASE_REG        0x0
+#define KVM_REG_ARM_VFP_FPSID           0x1000
+#define KVM_REG_ARM_VFP_FPSCR           0x1001
+#define KVM_REG_ARM_VFP_MVFR1           0x1006
+#define KVM_REG_ARM_VFP_MVFR0           0x1007
+#define KVM_REG_ARM_VFP_FPEXC           0x1008
+#define KVM_REG_ARM_VFP_FPINST          0x1009
+#define KVM_REG_ARM_VFP_FPINST2         0x100A
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT          24
+#define KVM_ARM_IRQ_TYPE_MASK           0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT          16
+#define KVM_ARM_IRQ_VCPU_MASK           0xff
+#define KVM_ARM_IRQ_NUM_SHIFT           0
+#define KVM_ARM_IRQ_NUM_MASK            0xffff
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU            0
+#define KVM_ARM_IRQ_TYPE_SPI            1
+#define KVM_ARM_IRQ_TYPE_PPI            2
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ             0
+#define KVM_ARM_IRQ_CPU_FIQ             1
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX             127
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE                0x95c1ba5e
+#define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
+#define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
+#define KVM_PSCI_RET_SUCCESS            0
+#define KVM_PSCI_RET_NI                 ((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL              ((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED             ((unsigned long)-3)
+#endif /* __ARM_KVM_H__ */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5bbec7b8183e..5f3338eacad2 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -82,5 +82,6 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
+obj-$(CONFIG_ARM_PSCI)          += psci.o
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index c985b481192c..c8b3272dfed1 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -13,6 +13,9 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#ifdef CONFIG_KVM_ARM_HOST
+#include <linux/kvm_host.h>
+#endif
 #include <asm/cacheflush.h>
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
@@ -146,5 +149,27 @@ int main(void)
  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
  DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
+#ifdef CONFIG_KVM_ARM_HOST
+  DEFINE(VCPU_KVM,              offsetof(struct kvm_vcpu, kvm));
+  DEFINE(VCPU_MIDR,             offsetof(struct kvm_vcpu, arch.midr));
+  DEFINE(VCPU_CP15,             offsetof(struct kvm_vcpu, arch.cp15));
+  DEFINE(VCPU_VFP_GUEST,        offsetof(struct kvm_vcpu, arch.vfp_guest));
+  DEFINE(VCPU_VFP_HOST,         offsetof(struct kvm_vcpu, arch.vfp_host));
+  DEFINE(VCPU_REGS,             offsetof(struct kvm_vcpu, arch.regs));
+  DEFINE(VCPU_USR_REGS,         offsetof(struct kvm_vcpu, arch.regs.usr_regs));
+  DEFINE(VCPU_SVC_REGS,         offsetof(struct kvm_vcpu, arch.regs.svc_regs));
+  DEFINE(VCPU_ABT_REGS,         offsetof(struct kvm_vcpu, arch.regs.abt_regs));
+  DEFINE(VCPU_UND_REGS,         offsetof(struct kvm_vcpu, arch.regs.und_regs));
+  DEFINE(VCPU_IRQ_REGS,         offsetof(struct kvm_vcpu, arch.regs.irq_regs));
+  DEFINE(VCPU_FIQ_REGS,         offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
+  DEFINE(VCPU_PC,               offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
+  DEFINE(VCPU_CPSR,             offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
+  DEFINE(VCPU_IRQ_LINES,        offsetof(struct kvm_vcpu, arch.irq_lines));
+  DEFINE(VCPU_HSR,              offsetof(struct kvm_vcpu, arch.hsr));
+  DEFINE(VCPU_HxFAR,            offsetof(struct kvm_vcpu, arch.hxfar));
+  DEFINE(VCPU_HPFAR,            offsetof(struct kvm_vcpu, arch.hpfar));
+  DEFINE(VCPU_HYP_PC,           offsetof(struct kvm_vcpu, arch.hyp_pc));
+  DEFINE(KVM_VTTBR,             offsetof(struct kvm, arch.vttbr));
+#endif
  return 0; 
 }
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 379cf3292390..a1f73b502ef0 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -413,7 +413,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return irq;
 }
-static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
 {
        int ret;
        struct pci_host_bridge_window *window;
@@ -445,7 +445,7 @@ static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
        return 0;
 }
-static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
        int ret;
@@ -464,6 +464,9 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                sys->map_irq = hw->map_irq;
                INIT_LIST_HEAD(&sys->resources);
+                if (hw->private_data)
+                        sys->private_data = hw->private_data[nr];
                ret = hw->setup(nr, sys);
                if (ret > 0) {
@@ -493,7 +496,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
        }
 }
-void __init pci_common_init(struct hw_pci *hw)
+void pci_common_init(struct hw_pci *hw)
 {
        struct pci_sys_data *sys;
        LIST_HEAD(head);
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 5ff2e77782b1..5eae53e7a2e1 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -28,6 +28,7 @@
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/smp.h>
+#include <linux/cpu_pm.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -35,6 +36,7 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/kdebug.h>
 #include <asm/traps.h>
+#include <asm/hardware/coresight.h>
 /* Breakpoint currently in use for each BRP. */
 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
@@ -49,6 +51,9 @@ static int core_num_wrps;
 /* Debug architecture version. */
 static u8 debug_arch;
+/* Does debug architecture support OS Save and Restore? */
+static bool has_ossr;
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
@@ -903,6 +908,23 @@ static struct undef_hook debug_reg_hook = {
        .fn             = debug_reg_trap,
 };
+/* Does this core support OS Save and Restore? */
+static bool core_has_os_save_restore(void)
+{
+        u32 oslsr;
+        switch (get_debug_arch()) {
+        case ARM_DEBUG_ARCH_V7_1:
+                return true;
+        case ARM_DEBUG_ARCH_V7_ECP14:
+                ARM_DBG_READ(c1, c1, 4, oslsr);
+                if (oslsr & ARM_OSLSR_OSLM0)
+                        return true;
+        default:
+                return false;
+        }
+}
 static void reset_ctrl_regs(void *unused)
 {
        int i, raw_num_brps, err = 0, cpu = smp_processor_id();
@@ -930,11 +952,7 @@ static void reset_ctrl_regs(void *unused)
                if ((val & 0x1) == 0)
                        err = -EPERM;
-                /*
+                if (!has_ossr)
-                 * Check whether we implement OS save and restore.
-                 */
-                ARM_DBG_READ(c1, c1, 4, val);
-                if ((val & 0x9) == 0)
                        goto clear_vcr;
                break;
        case ARM_DEBUG_ARCH_V7_1:
@@ -955,9 +973,9 @@ static void reset_ctrl_regs(void *unused)
        /*
         * Unconditionally clear the OS lock by writing a value
-         * other than 0xC5ACCE55 to the access register.
+         * other than CS_LAR_KEY to the access register.
         */
-        ARM_DBG_WRITE(c1, c0, 4, 0);
+        ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY);
        isb();
        /*
@@ -1015,6 +1033,30 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
        .notifier_call = dbg_reset_notify,
 };
+#ifdef CONFIG_CPU_PM
+static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
+                             void *v)
+{
+        if (action == CPU_PM_EXIT)
+                reset_ctrl_regs(NULL);
+        return NOTIFY_OK;
+}
+static struct notifier_block __cpuinitdata dbg_cpu_pm_nb = {
+        .notifier_call = dbg_cpu_pm_notify,
+};
+static void __init pm_init(void)
+{
+        cpu_pm_register_notifier(&dbg_cpu_pm_nb);
+}
+#else
+static inline void pm_init(void)
+{
+}
+#endif
 static int __init arch_hw_breakpoint_init(void)
 {
        debug_arch = get_debug_arch();
@@ -1024,6 +1066,8 @@ static int __init arch_hw_breakpoint_init(void)
                return 0;
        }
+        has_ossr = core_has_os_save_restore();
        /* Determine how many BRPs/WRPs are available. */
        core_num_brps = get_num_brps();
        core_num_wrps = get_num_wrps();
@@ -1062,8 +1106,9 @@ static int __init arch_hw_breakpoint_init(void)
        hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
                        TRAP_HWBKPT, "breakpoint debug exception");
-        /* Register hotplug notifier. */
+        /* Register hotplug and PM notifiers. */
        register_cpu_notifier(&dbg_reset_nb);
+        pm_init();
        return 0;
 }
 arch_initcall(arch_hw_breakpoint_init);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c6dec5fc20aa..047d3e40e470 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -172,14 +172,9 @@ static void default_idle(void)
        local_irq_enable();
 }
-void (*pm_idle)(void) = default_idle;
-EXPORT_SYMBOL(pm_idle);
 /*
- * The idle thread, has rather strange semantics for calling pm_idle,
+ * The idle thread.
- * but this is what x86 does and we need to do the same, so that
+ * We always respect 'hlt_counter' to prevent low power idle.
- * things like cpuidle get called in the same way.  The only difference
- * is that we always respect 'hlt_counter' to prevent low power idle.
 */
 void cpu_idle(void)
 {
@@ -210,10 +205,10 @@ void cpu_idle(void)
                        } else if (!need_resched()) {
                                stop_critical_timings();
                                if (cpuidle_idle_call())
-                                        pm_idle();
+                                        default_idle();
                                start_critical_timings();
                                /*
-                                 * pm_idle functions must always
+                                 * default_idle functions must always
                                 * return with IRQs enabled.
                                 */
                                WARN_ON(irqs_disabled());
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
new file mode 100644
index 000000000000..36531643cc2c
--- /dev/null
+++ b/arch/arm/kernel/psci.c
@@ -0,0 +1,211 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "psci: " fmt
+#include <linux/init.h>
+#include <linux/of.h>
+#include <asm/compiler.h>
+#include <asm/errno.h>
+#include <asm/opcodes-sec.h>
+#include <asm/opcodes-virt.h>
+#include <asm/psci.h>
+struct psci_operations psci_ops;
+static int (*invoke_psci_fn)(u32, u32, u32, u32);
+enum psci_function {
+        PSCI_FN_CPU_SUSPEND,
+        PSCI_FN_CPU_ON,
+        PSCI_FN_CPU_OFF,
+        PSCI_FN_MIGRATE,
+        PSCI_FN_MAX,
+};
+static u32 psci_function_id[PSCI_FN_MAX];
+#define PSCI_RET_SUCCESS                0
+#define PSCI_RET_EOPNOTSUPP             -1
+#define PSCI_RET_EINVAL                 -2
+#define PSCI_RET_EPERM                  -3
+static int psci_to_linux_errno(int errno)
+{
+        switch (errno) {
+        case PSCI_RET_SUCCESS:
+                return 0;
+        case PSCI_RET_EOPNOTSUPP:
+                return -EOPNOTSUPP;
+        case PSCI_RET_EINVAL:
+                return -EINVAL;
+        case PSCI_RET_EPERM:
+                return -EPERM;
+        };
+        return -EINVAL;
+}
+#define PSCI_POWER_STATE_ID_MASK        0xffff
+#define PSCI_POWER_STATE_ID_SHIFT       0
+#define PSCI_POWER_STATE_TYPE_MASK      0x1
+#define PSCI_POWER_STATE_TYPE_SHIFT     16
+#define PSCI_POWER_STATE_AFFL_MASK      0x3
+#define PSCI_POWER_STATE_AFFL_SHIFT     24
+static u32 psci_power_state_pack(struct psci_power_state state)
+{
+        return  ((state.id & PSCI_POWER_STATE_ID_MASK)
+                        << PSCI_POWER_STATE_ID_SHIFT)   |
+                ((state.type & PSCI_POWER_STATE_TYPE_MASK)
+                        << PSCI_POWER_STATE_TYPE_SHIFT) |
+                ((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK)
+                        << PSCI_POWER_STATE_AFFL_SHIFT);
+}
+/*
+ * The following two functions are invoked via the invoke_psci_fn pointer
+ * and will not be inlined, allowing us to piggyback on the AAPCS.
+ */
+static noinline int __invoke_psci_fn_hvc(u32 function_id, u32 arg0, u32 arg1,
+                                         u32 arg2)
+{
+        asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r1")
+                        __asmeq("%2", "r2")
+                        __asmeq("%3", "r3")
+                        __HVC(0)
+                : "+r" (function_id)
+                : "r" (arg0), "r" (arg1), "r" (arg2));
+        return function_id;
+}
+static noinline int __invoke_psci_fn_smc(u32 function_id, u32 arg0, u32 arg1,
+                                         u32 arg2)
+{
+        asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r1")
+                        __asmeq("%2", "r2")
+                        __asmeq("%3", "r3")
+                        __SMC(0)
+                : "+r" (function_id)
+                : "r" (arg0), "r" (arg1), "r" (arg2));
+        return function_id;
+}
+static int psci_cpu_suspend(struct psci_power_state state,
+                            unsigned long entry_point)
+{
+        int err;
+        u32 fn, power_state;
+        fn = psci_function_id[PSCI_FN_CPU_SUSPEND];
+        power_state = psci_power_state_pack(state);
+        err = invoke_psci_fn(fn, power_state, entry_point, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_cpu_off(struct psci_power_state state)
+{
+        int err;
+        u32 fn, power_state;
+        fn = psci_function_id[PSCI_FN_CPU_OFF];
+        power_state = psci_power_state_pack(state);
+        err = invoke_psci_fn(fn, power_state, 0, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
+{
+        int err;
+        u32 fn;
+        fn = psci_function_id[PSCI_FN_CPU_ON];
+        err = invoke_psci_fn(fn, cpuid, entry_point, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_migrate(unsigned long cpuid)
+{
+        int err;
+        u32 fn;
+        fn = psci_function_id[PSCI_FN_MIGRATE];
+        err = invoke_psci_fn(fn, cpuid, 0, 0);
+        return psci_to_linux_errno(err);
+}
+static const struct of_device_id psci_of_match[] __initconst = {
+        { .compatible = "arm,psci",     },
+        {},
+};
+static int __init psci_init(void)
+{
+        struct device_node *np;
+        const char *method;
+        u32 id;
+        np = of_find_matching_node(NULL, psci_of_match);
+        if (!np)
+                return 0;
+        pr_info("probing function IDs from device-tree\n");
+        if (of_property_read_string(np, "method", &method)) {
+                pr_warning("missing \"method\" property\n");
+                goto out_put_node;
+        }
+        if (!strcmp("hvc", method)) {
+                invoke_psci_fn = __invoke_psci_fn_hvc;
+        } else if (!strcmp("smc", method)) {
+                invoke_psci_fn = __invoke_psci_fn_smc;
+        } else {
+                pr_warning("invalid \"method\" property: %s\n", method);
+                goto out_put_node;
+        }
+        if (!of_property_read_u32(np, "cpu_suspend", &id)) {
+                psci_function_id[PSCI_FN_CPU_SUSPEND] = id;
+                psci_ops.cpu_suspend = psci_cpu_suspend;
+        }
+        if (!of_property_read_u32(np, "cpu_off", &id)) {
+                psci_function_id[PSCI_FN_CPU_OFF] = id;
+                psci_ops.cpu_off = psci_cpu_off;
+        }
+        if (!of_property_read_u32(np, "cpu_on", &id)) {
+                psci_function_id[PSCI_FN_CPU_ON] = id;
+                psci_ops.cpu_on = psci_cpu_on;
+        }
+        if (!of_property_read_u32(np, "migrate", &id)) {
+                psci_function_id[PSCI_FN_MIGRATE] = id;
+                psci_ops.migrate = psci_migrate;
+        }
+out_put_node:
+        of_node_put(np);
+        return 0;
+}
+early_initcall(psci_init);
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index fc6692e2b603..bd6f56b9ec21 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -93,11 +93,11 @@ static void notrace update_sched_clock(void)
         * detectable in cyc_to_fixed_sched_clock().
         */
        raw_local_irq_save(flags);
-        cd.epoch_cyc = cyc;
+        cd.epoch_cyc_copy = cyc;
        smp_wmb();
        cd.epoch_ns = ns;
        smp_wmb();
-        cd.epoch_cyc_copy = cyc;
+        cd.epoch_cyc = cyc;
        raw_local_irq_restore(flags);
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 3fc96db2a4b6..60340fa561d4 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -125,18 +125,6 @@ void __init smp_init_cpus(void)
                smp_ops.smp_init_cpus();
 }
-static void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-        if (smp_ops.smp_prepare_cpus)
-                smp_ops.smp_prepare_cpus(max_cpus);
-}
-static void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-        if (smp_ops.smp_secondary_init)
-                smp_ops.smp_secondary_init(cpu);
-}
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        if (smp_ops.smp_boot_secondary)
@@ -154,12 +142,6 @@ static int platform_cpu_kill(unsigned int cpu)
        return 1;
 }
-static void platform_cpu_die(unsigned int cpu)
-{
-        if (smp_ops.cpu_die)
-                smp_ops.cpu_die(cpu);
-}
 static int platform_cpu_disable(unsigned int cpu)
 {
        if (smp_ops.cpu_disable)
@@ -257,7 +239,8 @@ void __ref cpu_die(void)
         * actual CPU shutdown procedure is at least platform (if not
         * CPU) specific.
         */
-        platform_cpu_die(cpu);
+        if (smp_ops.cpu_die)
+                smp_ops.cpu_die(cpu);
        /*
         * Do not return to the idle loop - jump back to the secondary
@@ -324,7 +307,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        /*
         * Give the platform a chance to do its own initialisation.
         */
-        platform_secondary_init(cpu);
+        if (smp_ops.smp_secondary_init)
+                smp_ops.smp_secondary_init(cpu);
        notify_cpu_starting(cpu);
@@ -399,8 +383,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                /*
                 * Initialise the present map, which describes the set of CPUs
                 * actually populated at the present time. A platform should
-                 * re-initialize the map in platform_smp_prepare_cpus() if
+                 * re-initialize the map in the platforms smp_prepare_cpus()
-                 * present != possible (e.g. physical hotplug).
+                 * if present != possible (e.g. physical hotplug).
                 */
                init_cpu_present(cpu_possible_mask);
@@ -408,7 +392,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 * Initialise the SCU if there are more than one CPU
                 * and let them know where to start.
                 */
-                platform_smp_prepare_cpus(max_cpus);
+                if (smp_ops.smp_prepare_cpus)
+                        smp_ops.smp_prepare_cpus(max_cpus);
        }
 }
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index b9f015e843d8..45eac87ed66a 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
        unsigned int val;
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (mode > 3 || mode == 1 || cpu > 3)
                return -EINVAL;
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index dc9bb0146665..c092115d903a 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -30,7 +30,6 @@ static void __iomem *twd_base;
 static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
-static bool common_setup_called;
 static DEFINE_PER_CPU(bool, percpu_setup_called);
 static struct clock_event_device __percpu **twd_evt;
@@ -238,25 +237,28 @@ static irqreturn_t twd_handler(int irq, void *dev_id)
        return IRQ_NONE;
 }
-static struct clk *twd_get_clock(void)
+static void twd_get_clock(struct device_node *np)
 {
-        struct clk *clk;
        int err;
-        clk = clk_get_sys("smp_twd", NULL);
+        if (np)
-        if (IS_ERR(clk)) {
+                twd_clk = of_clk_get(np, 0);
-                pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
+        else
-                return clk;
+                twd_clk = clk_get_sys("smp_twd", NULL);
+        if (IS_ERR(twd_clk)) {
+                pr_err("smp_twd: clock not found %d\n", (int) PTR_ERR(twd_clk));
+                return;
        }
-        err = clk_prepare_enable(clk);
+        err = clk_prepare_enable(twd_clk);
        if (err) {
                pr_err("smp_twd: clock failed to prepare+enable: %d\n", err);
-                clk_put(clk);
+                clk_put(twd_clk);
-                return ERR_PTR(err);
+                return;
        }
-        return clk;
+        twd_timer_rate = clk_get_rate(twd_clk);
 }
 /*
@@ -279,26 +281,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
        }
        per_cpu(percpu_setup_called, cpu) = true;
-        /*
+        twd_calibrate_rate();
-         * This stuff only need to be done once for the entire TWD cluster
-         * during the runtime of the system.
-         */
-        if (!common_setup_called) {
-                twd_clk = twd_get_clock();
-                /*
-                 * We use IS_ERR_OR_NULL() here, because if the clock stubs
-                 * are active we will get a valid clk reference which is
-                 * however NULL and will return the rate 0. In that case we
-                 * need to calibrate the rate instead.
-                 */
-                if (!IS_ERR_OR_NULL(twd_clk))
-                        twd_timer_rate = clk_get_rate(twd_clk);
-                else
-                        twd_calibrate_rate();
-                common_setup_called = true;
-        }
        /*
         * The following is done once per CPU the first time .setup() is
@@ -329,7 +312,7 @@ static struct local_timer_ops twd_lt_ops __cpuinitdata = {
        .stop   = twd_timer_stop,
 };
-static int __init twd_local_timer_common_register(void)
+static int __init twd_local_timer_common_register(struct device_node *np)
 {
        int err;
@@ -349,6 +332,8 @@ static int __init twd_local_timer_common_register(void)
        if (err)
                goto out_irq;
+        twd_get_clock(np);
        return 0;
 out_irq:
@@ -372,7 +357,7 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
        if (!twd_base)
                return -ENOMEM;
-        return twd_local_timer_common_register();
+        return twd_local_timer_common_register(NULL);
 }
 #ifdef CONFIG_OF
@@ -404,7 +389,7 @@ void __init twd_local_timer_of_register(void)
                goto out;
        }
-        err = twd_local_timer_common_register();
+        err = twd_local_timer_common_register(np);
 out:
        WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 11c1785bf63e..b571484e9f03 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -19,7 +19,11 @@
        ALIGN_FUNCTION();                                               \
        VMLINUX_SYMBOL(__idmap_text_start) = .;                         \
        *(.idmap.text)                                                  \
-        VMLINUX_SYMBOL(__idmap_text_end) = .;
+        VMLINUX_SYMBOL(__idmap_text_end) = .;                           \
+        ALIGN_FUNCTION();                                               \
+        VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;                     \
+        *(.hyp.idmap.text)                                              \
+        VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
 #ifdef CONFIG_HOTPLUG_CPU
 #define ARM_CPU_DISCARD(x)
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
new file mode 100644
index 000000000000..05227cb57a7b
--- /dev/null
+++ b/arch/arm/kvm/Kconfig
@@ -0,0 +1,56 @@
+#
+# KVM configuration
+#
+source "virt/kvm/Kconfig"
+menuconfig VIRTUALIZATION
+        bool "Virtualization"
+        ---help---
+          Say Y here to get to see options for using your Linux host to run
+          other operating systems inside virtual machines (guests).
+          This option alone does not add any kernel code.
+          If you say N, all options in this submenu will be skipped and
+          disabled.
+if VIRTUALIZATION
+config KVM
+        bool "Kernel-based Virtual Machine (KVM) support"
+        select PREEMPT_NOTIFIERS
+        select ANON_INODES
+        select KVM_MMIO
+        select KVM_ARM_HOST
+        depends on ARM_VIRT_EXT && ARM_LPAE
+        ---help---
+          Support hosting virtualized guest machines. You will also
+          need to select one or more of the processor modules below.
+          This module provides access to the hardware capabilities through
+          a character device node named /dev/kvm.
+          If unsure, say N.
+config KVM_ARM_HOST
+        bool "KVM host support for ARM cpus."
+        depends on KVM
+        depends on MMU
+        select  MMU_NOTIFIER
+        ---help---
+          Provides host support for ARM processors.
+config KVM_ARM_MAX_VCPUS
+        int "Number maximum supported virtual CPUs per VM"
+        depends on KVM_ARM_HOST
+        default 4
+        help
+          Static number of max supported virtual CPUs per VM.
+          If you choose a high number, the vcpu structures will be quite
+          large, so only choose a reasonable number that you expect to
+          actually use.
+source drivers/virtio/Kconfig
+endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
new file mode 100644
index 000000000000..ea27987bd07f
--- /dev/null
+++ b/arch/arm/kvm/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for Kernel-based Virtual Machine module
+#
+plus_virt := $(call as-instr,.arch_extension virt,+virt)
+ifeq ($(plus_virt),+virt)
+        plus_virt_def := -DREQUIRES_VIRT=1
+endif
+ccflags-y += -Ivirt/kvm -Iarch/arm/kvm
+CFLAGS_arm.o := -I. $(plus_virt_def)
+CFLAGS_mmu.o := -I.
+AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
+AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
+kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+obj-y += kvm-arm.o init.o interrupts.o
+obj-y += arm.o guest.o mmu.o emulate.o reset.o
+obj-y += coproc.o coproc_a15.o mmio.o psci.o
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
new file mode 100644
index 000000000000..2d30e3afdaf9
--- /dev/null
+++ b/arch/arm/kvm/arm.c
@@ -0,0 +1,1015 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mman.h>
+#include <linux/sched.h>
+#include <linux/kvm.h>
+#include <trace/events/kvm.h>
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+#include <asm/unified.h>
+#include <asm/uaccess.h>
+#include <asm/ptrace.h>
+#include <asm/mman.h>
+#include <asm/cputype.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+#include <asm/virt.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/kvm_psci.h>
+#include <asm/opcodes.h>
+#ifdef REQUIRES_VIRT
+__asm__(".arch_extension        virt");
+#endif
+static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
+static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
+static unsigned long hyp_default_vectors;
+/* The VMID used in the VTTBR */
+static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
+static u8 kvm_next_vmid;
+static DEFINE_SPINLOCK(kvm_vmid_lock);
+int kvm_arch_hardware_enable(void *garbage)
+{
+        return 0;
+}
+int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
+}
+void kvm_arch_hardware_disable(void *garbage)
+{
+}
+int kvm_arch_hardware_setup(void)
+{
+        return 0;
+}
+void kvm_arch_hardware_unsetup(void)
+{
+}
+void kvm_arch_check_processor_compat(void *rtn)
+{
+        *(int *)rtn = 0;
+}
+void kvm_arch_sync_events(struct kvm *kvm)
+{
+}
+/**
+ * kvm_arch_init_vm - initializes a VM data structure
+ * @kvm:        pointer to the KVM struct
+ */
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
+{
+        int ret = 0;
+        if (type)
+                return -EINVAL;
+        ret = kvm_alloc_stage2_pgd(kvm);
+        if (ret)
+                goto out_fail_alloc;
+        ret = create_hyp_mappings(kvm, kvm + 1);
+        if (ret)
+                goto out_free_stage2_pgd;
+        /* Mark the initial VMID generation invalid */
+        kvm->arch.vmid_gen = 0;
+        return ret;
+out_free_stage2_pgd:
+        kvm_free_stage2_pgd(kvm);
+out_fail_alloc:
+        return ret;
+}
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+        return VM_FAULT_SIGBUS;
+}
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+}
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        return 0;
+}
+/**
+ * kvm_arch_destroy_vm - destroy the VM data structure
+ * @kvm:        pointer to the KVM struct
+ */
+void kvm_arch_destroy_vm(struct kvm *kvm)
+{
+        int i;
+        kvm_free_stage2_pgd(kvm);
+        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+                if (kvm->vcpus[i]) {
+                        kvm_arch_vcpu_free(kvm->vcpus[i]);
+                        kvm->vcpus[i] = NULL;
+                }
+        }
+}
+int kvm_dev_ioctl_check_extension(long ext)
+{
+        int r;
+        switch (ext) {
+        case KVM_CAP_USER_MEMORY:
+        case KVM_CAP_SYNC_MMU:
+        case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
+        case KVM_CAP_ONE_REG:
+        case KVM_CAP_ARM_PSCI:
+                r = 1;
+                break;
+        case KVM_CAP_COALESCED_MMIO:
+                r = KVM_COALESCED_MMIO_PAGE_OFFSET;
+                break;
+        case KVM_CAP_NR_VCPUS:
+                r = num_online_cpus();
+                break;
+        case KVM_CAP_MAX_VCPUS:
+                r = KVM_MAX_VCPUS;
+                break;
+        default:
+                r = 0;
+                break;
+        }
+        return r;
+}
+long kvm_arch_dev_ioctl(struct file *filp,
+                        unsigned int ioctl, unsigned long arg)
+{
+        return -EINVAL;
+}
+int kvm_arch_set_memory_region(struct kvm *kvm,
+                               struct kvm_userspace_memory_region *mem,
+                               struct kvm_memory_slot old,
+                               int user_alloc)
+{
+        return 0;
+}
+int kvm_arch_prepare_memory_region(struct kvm *kvm,
+                                   struct kvm_memory_slot *memslot,
+                                   struct kvm_memory_slot old,
+                                   struct kvm_userspace_memory_region *mem,
+                                   int user_alloc)
+{
+        return 0;
+}
+void kvm_arch_commit_memory_region(struct kvm *kvm,
+                                   struct kvm_userspace_memory_region *mem,
+                                   struct kvm_memory_slot old,
+                                   int user_alloc)
+{
+}
+void kvm_arch_flush_shadow_all(struct kvm *kvm)
+{
+}
+void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+                                   struct kvm_memory_slot *slot)
+{
+}
+struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
+{
+        int err;
+        struct kvm_vcpu *vcpu;
+        vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
+        if (!vcpu) {
+                err = -ENOMEM;
+                goto out;
+        }
+        err = kvm_vcpu_init(vcpu, kvm, id);
+        if (err)
+                goto free_vcpu;
+        err = create_hyp_mappings(vcpu, vcpu + 1);
+        if (err)
+                goto vcpu_uninit;
+        return vcpu;
+vcpu_uninit:
+        kvm_vcpu_uninit(vcpu);
+free_vcpu:
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
+out:
+        return ERR_PTR(err);
+}
+int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
+{
+        kvm_mmu_free_memory_caches(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
+}
+void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+        kvm_arch_vcpu_free(vcpu);
+}
+int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+int __attribute_const__ kvm_target_cpu(void)
+{
+        unsigned long implementor = read_cpuid_implementor();
+        unsigned long part_number = read_cpuid_part_number();
+        if (implementor != ARM_CPU_IMP_ARM)
+                return -EINVAL;
+        switch (part_number) {
+        case ARM_CPU_PART_CORTEX_A15:
+                return KVM_ARM_TARGET_CORTEX_A15;
+        default:
+                return -EINVAL;
+        }
+}
+int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
+{
+        /* Force users to call KVM_ARM_VCPU_INIT */
+        vcpu->arch.target = -1;
+        return 0;
+}
+void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
+{
+}
+void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
+{
+        vcpu->cpu = cpu;
+        vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state);
+        /*
+         * Check whether this vcpu requires the cache to be flushed on
+         * this physical CPU. This is a consequence of doing dcache
+         * operations by set/way on this vcpu. We do it here to be in
+         * a non-preemptible section.
+         */
+        if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
+                flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
+}
+void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
+{
+}
+int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
+                                        struct kvm_guest_debug *dbg)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
+                                    struct kvm_mp_state *mp_state)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
+                                    struct kvm_mp_state *mp_state)
+{
+        return -EINVAL;
+}
+/**
+ * kvm_arch_vcpu_runnable - determine if the vcpu can be scheduled
+ * @v:          The VCPU pointer
+ *
+ * If the guest CPU is not waiting for interrupts or an interrupt line is
+ * asserted, the CPU is by definition runnable.
+ */
+int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
+{
+        return !!v->arch.irq_lines;
+}
+/* Just ensure a guest exit from a particular CPU */
+static void exit_vm_noop(void *info)
+{
+}
+void force_vm_exit(const cpumask_t *mask)
+{
+        smp_call_function_many(mask, exit_vm_noop, NULL, true);
+}
+/**
+ * need_new_vmid_gen - check that the VMID is still valid
+ * @kvm: The VM's VMID to checkt
+ *
+ * return true if there is a new generation of VMIDs being used
+ *
+ * The hardware supports only 256 values with the value zero reserved for the
+ * host, so we check if an assigned value belongs to a previous generation,
+ * which which requires us to assign a new value. If we're the first to use a
+ * VMID for the new generation, we must flush necessary caches and TLBs on all
+ * CPUs.
+ */
+static bool need_new_vmid_gen(struct kvm *kvm)
+{
+        return unlikely(kvm->arch.vmid_gen != atomic64_read(&kvm_vmid_gen));
+}
+/**
+ * update_vttbr - Update the VTTBR with a valid VMID before the guest runs
+ * @kvm The guest that we are about to run
+ *
+ * Called from kvm_arch_vcpu_ioctl_run before entering the guest to ensure the
+ * VM has a valid VMID, otherwise assigns a new one and flushes corresponding
+ * caches and TLBs.
+ */
+static void update_vttbr(struct kvm *kvm)
+{
+        phys_addr_t pgd_phys;
+        u64 vmid;
+        if (!need_new_vmid_gen(kvm))
+                return;
+        spin_lock(&kvm_vmid_lock);
+        /*
+         * We need to re-check the vmid_gen here to ensure that if another vcpu
+         * already allocated a valid vmid for this vm, then this vcpu should
+         * use the same vmid.
+         */
+        if (!need_new_vmid_gen(kvm)) {
+                spin_unlock(&kvm_vmid_lock);
+                return;
+        }
+        /* First user of a new VMID generation? */
+        if (unlikely(kvm_next_vmid == 0)) {
+                atomic64_inc(&kvm_vmid_gen);
+                kvm_next_vmid = 1;
+                /*
+                 * On SMP we know no other CPUs can use this CPU's or each
+                 * other's VMID after force_vm_exit returns since the
+                 * kvm_vmid_lock blocks them from reentry to the guest.
+                 */
+                force_vm_exit(cpu_all_mask);
+                /*
+                 * Now broadcast TLB + ICACHE invalidation over the inner
+                 * shareable domain to make sure all data structures are
+                 * clean.
+                 */
+                kvm_call_hyp(__kvm_flush_vm_context);
+        }
+        kvm->arch.vmid_gen = atomic64_read(&kvm_vmid_gen);
+        kvm->arch.vmid = kvm_next_vmid;
+        kvm_next_vmid++;
+        /* update vttbr to be used with the new vmid */
+        pgd_phys = virt_to_phys(kvm->arch.pgd);
+        vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK;
+        kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK;
+        kvm->arch.vttbr |= vmid;
+        spin_unlock(&kvm_vmid_lock);
+}
+static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* SVC called from Hyp mode should never get here */
+        kvm_debug("SVC called from Hyp mode shouldn't go here\n");
+        BUG();
+        return -EINVAL; /* Squash warning */
+}
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
+                      vcpu->arch.hsr & HSR_HVC_IMM_MASK);
+        if (kvm_psci_call(vcpu))
+                return 1;
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        if (kvm_psci_call(vcpu))
+                return 1;
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* The hypervisor should never cause aborts */
+        kvm_err("Prefetch Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+                vcpu->arch.hxfar, vcpu->arch.hsr);
+        return -EFAULT;
+}
+static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* This is either an error in the ws. code or an external abort */
+        kvm_err("Data Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+                vcpu->arch.hxfar, vcpu->arch.hsr);
+        return -EFAULT;
+}
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+static exit_handle_fn arm_exit_handlers[] = {
+        [HSR_EC_WFI]            = kvm_handle_wfi,
+        [HSR_EC_CP15_32]        = kvm_handle_cp15_32,
+        [HSR_EC_CP15_64]        = kvm_handle_cp15_64,
+        [HSR_EC_CP14_MR]        = kvm_handle_cp14_access,
+        [HSR_EC_CP14_LS]        = kvm_handle_cp14_load_store,
+        [HSR_EC_CP14_64]        = kvm_handle_cp14_access,
+        [HSR_EC_CP_0_13]        = kvm_handle_cp_0_13_access,
+        [HSR_EC_CP10_ID]        = kvm_handle_cp10_id,
+        [HSR_EC_SVC_HYP]        = handle_svc_hyp,
+        [HSR_EC_HVC]            = handle_hvc,
+        [HSR_EC_SMC]            = handle_smc,
+        [HSR_EC_IABT]           = kvm_handle_guest_abort,
+        [HSR_EC_IABT_HYP]       = handle_pabt_hyp,
+        [HSR_EC_DABT]           = kvm_handle_guest_abort,
+        [HSR_EC_DABT_HYP]       = handle_dabt_hyp,
+};
+/*
+ * A conditional instruction is allowed to trap, even though it
+ * wouldn't be executed.  So let's re-implement the hardware, in
+ * software!
+ */
+static bool kvm_condition_valid(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr, cond, insn;
+        /*
+         * Exception Code 0 can only happen if we set HCR.TGE to 1, to
+         * catch undefined instructions, and then we won't get past
+         * the arm_exit_handlers test anyway.
+         */
+        BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0);
+        /* Top two bits non-zero?  Unconditional. */
+        if (vcpu->arch.hsr >> 30)
+                return true;
+        cpsr = *vcpu_cpsr(vcpu);
+        /* Is condition field valid? */
+        if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT)
+                cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT;
+        else {
+                /* This can happen in Thumb mode: examine IT state. */
+                unsigned long it;
+                it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+                /* it == 0 => unconditional. */
+                if (it == 0)
+                        return true;
+                /* The cond for this insn works out as the top 4 bits. */
+                cond = (it >> 4);
+        }
+        /* Shift makes it look like an ARM-mode instruction */
+        insn = cond << 28;
+        return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
+}
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to QEMU.
+ */
+static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                       int exception_index)
+{
+        unsigned long hsr_ec;
+        switch (exception_index) {
+        case ARM_EXCEPTION_IRQ:
+                return 1;
+        case ARM_EXCEPTION_UNDEFINED:
+                kvm_err("Undefined exception in Hyp mode at: %#08x\n",
+                        vcpu->arch.hyp_pc);
+                BUG();
+                panic("KVM: Hypervisor undefined exception!\n");
+        case ARM_EXCEPTION_DATA_ABORT:
+        case ARM_EXCEPTION_PREF_ABORT:
+        case ARM_EXCEPTION_HVC:
+                hsr_ec = (vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT;
+                if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers)
+                    || !arm_exit_handlers[hsr_ec]) {
+                        kvm_err("Unkown exception class: %#08lx, "
+                                "hsr: %#08x\n", hsr_ec,
+                                (unsigned int)vcpu->arch.hsr);
+                        BUG();
+                }
+                /*
+                 * See ARM ARM B1.14.1: "Hyp traps on instructions
+                 * that fail their condition code check"
+                 */
+                if (!kvm_condition_valid(vcpu)) {
+                        bool is_wide = vcpu->arch.hsr & HSR_IL;
+                        kvm_skip_instr(vcpu, is_wide);
+                        return 1;
+                }
+                return arm_exit_handlers[hsr_ec](vcpu, run);
+        default:
+                kvm_pr_unimpl("Unsupported exception type: %d",
+                              exception_index);
+                run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+                return 0;
+        }
+}
+static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
+{
+        if (likely(vcpu->arch.has_run_once))
+                return 0;
+        vcpu->arch.has_run_once = true;
+        /*
+         * Handle the "start in power-off" case by calling into the
+         * PSCI code.
+         */
+        if (test_and_clear_bit(KVM_ARM_VCPU_POWER_OFF, vcpu->arch.features)) {
+                *vcpu_reg(vcpu, 0) = KVM_PSCI_FN_CPU_OFF;
+                kvm_psci_call(vcpu);
+        }
+        return 0;
+}
+static void vcpu_pause(struct kvm_vcpu *vcpu)
+{
+        wait_queue_head_t *wq = kvm_arch_vcpu_wq(vcpu);
+        wait_event_interruptible(*wq, !vcpu->arch.pause);
+}
+/**
+ * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
+ * @vcpu:       The VCPU pointer
+ * @run:        The kvm_run structure pointer used for userspace state exchange
+ *
+ * This function is called through the VCPU_RUN ioctl called from user space. It
+ * will execute VM code in a loop until the time slice for the process is used
+ * or some emulation is needed from user space in which case the function will
+ * return with return value 0 and with the kvm_run structure filled in with the
+ * required data for the requested emulation.
+ */
+int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        int ret;
+        sigset_t sigsaved;
+        /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
+        if (unlikely(vcpu->arch.target < 0))
+                return -ENOEXEC;
+        ret = kvm_vcpu_first_run_init(vcpu);
+        if (ret)
+                return ret;
+        if (run->exit_reason == KVM_EXIT_MMIO) {
+                ret = kvm_handle_mmio_return(vcpu, vcpu->run);
+                if (ret)
+                        return ret;
+        }
+        if (vcpu->sigset_active)
+                sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
+        ret = 1;
+        run->exit_reason = KVM_EXIT_UNKNOWN;
+        while (ret > 0) {
+                /*
+                 * Check conditions before entering the guest
+                 */
+                cond_resched();
+                update_vttbr(vcpu->kvm);
+                if (vcpu->arch.pause)
+                        vcpu_pause(vcpu);
+                local_irq_disable();
+                /*
+                 * Re-check atomic conditions
+                 */
+                if (signal_pending(current)) {
+                        ret = -EINTR;
+                        run->exit_reason = KVM_EXIT_INTR;
+                }
+                if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) {
+                        local_irq_enable();
+                        continue;
+                }
+                /**************************************************************
+                 * Enter the guest
+                 */
+                trace_kvm_entry(*vcpu_pc(vcpu));
+                kvm_guest_enter();
+                vcpu->mode = IN_GUEST_MODE;
+                ret = kvm_call_hyp(__kvm_vcpu_run, vcpu);
+                vcpu->mode = OUTSIDE_GUEST_MODE;
+                vcpu->arch.last_pcpu = smp_processor_id();
+                kvm_guest_exit();
+                trace_kvm_exit(*vcpu_pc(vcpu));
+                /*
+                 * We may have taken a host interrupt in HYP mode (ie
+                 * while executing the guest). This interrupt is still
+                 * pending, as we haven't serviced it yet!
+                 *
+                 * We're now back in SVC mode, with interrupts
+                 * disabled.  Enabling the interrupts now will have
+                 * the effect of taking the interrupt again, in SVC
+                 * mode this time.
+                 */
+                local_irq_enable();
+                /*
+                 * Back from guest
+                 *************************************************************/
+                ret = handle_exit(vcpu, run, ret);
+        }
+        if (vcpu->sigset_active)
+                sigprocmask(SIG_SETMASK, &sigsaved, NULL);
+        return ret;
+}
+static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level)
+{
+        int bit_index;
+        bool set;
+        unsigned long *ptr;
+        if (number == KVM_ARM_IRQ_CPU_IRQ)
+                bit_index = __ffs(HCR_VI);
+        else /* KVM_ARM_IRQ_CPU_FIQ */
+                bit_index = __ffs(HCR_VF);
+        ptr = (unsigned long *)&vcpu->arch.irq_lines;
+        if (level)
+                set = test_and_set_bit(bit_index, ptr);
+        else
+                set = test_and_clear_bit(bit_index, ptr);
+        /*
+         * If we didn't change anything, no need to wake up or kick other CPUs
+         */
+        if (set == level)
+                return 0;
+        /*
+         * The vcpu irq_lines field was updated, wake up sleeping VCPUs and
+         * trigger a world-switch round on the running physical CPU to set the
+         * virtual IRQ/FIQ fields in the HCR appropriately.
+         */
+        kvm_vcpu_kick(vcpu);
+        return 0;
+}
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level)
+{
+        u32 irq = irq_level->irq;
+        unsigned int irq_type, vcpu_idx, irq_num;
+        int nrcpus = atomic_read(&kvm->online_vcpus);
+        struct kvm_vcpu *vcpu = NULL;
+        bool level = irq_level->level;
+        irq_type = (irq >> KVM_ARM_IRQ_TYPE_SHIFT) & KVM_ARM_IRQ_TYPE_MASK;
+        vcpu_idx = (irq >> KVM_ARM_IRQ_VCPU_SHIFT) & KVM_ARM_IRQ_VCPU_MASK;
+        irq_num = (irq >> KVM_ARM_IRQ_NUM_SHIFT) & KVM_ARM_IRQ_NUM_MASK;
+        trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level);
+        if (irq_type != KVM_ARM_IRQ_TYPE_CPU)
+                return -EINVAL;
+        if (vcpu_idx >= nrcpus)
+                return -EINVAL;
+        vcpu = kvm_get_vcpu(kvm, vcpu_idx);
+        if (!vcpu)
+                return -EINVAL;
+        if (irq_num > KVM_ARM_IRQ_CPU_FIQ)
+                return -EINVAL;
+        return vcpu_interrupt_line(vcpu, irq_num, level);
+}
+long kvm_arch_vcpu_ioctl(struct file *filp,
+                         unsigned int ioctl, unsigned long arg)
+{
+        struct kvm_vcpu *vcpu = filp->private_data;
+        void __user *argp = (void __user *)arg;
+        switch (ioctl) {
+        case KVM_ARM_VCPU_INIT: {
+                struct kvm_vcpu_init init;
+                if (copy_from_user(&init, argp, sizeof(init)))
+                        return -EFAULT;
+                return kvm_vcpu_set_target(vcpu, &init);
+        }
+        case KVM_SET_ONE_REG:
+        case KVM_GET_ONE_REG: {
+                struct kvm_one_reg reg;
+                if (copy_from_user(&reg, argp, sizeof(reg)))
+                        return -EFAULT;
+                if (ioctl == KVM_SET_ONE_REG)
+                        return kvm_arm_set_reg(vcpu, &reg);
+                else
+                        return kvm_arm_get_reg(vcpu, &reg);
+        }
+        case KVM_GET_REG_LIST: {
+                struct kvm_reg_list __user *user_list = argp;
+                struct kvm_reg_list reg_list;
+                unsigned n;
+                if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
+                        return -EFAULT;
+                n = reg_list.n;
+                reg_list.n = kvm_arm_num_regs(vcpu);
+                if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
+                        return -EFAULT;
+                if (n < reg_list.n)
+                        return -E2BIG;
+                return kvm_arm_copy_reg_indices(vcpu, user_list->reg);
+        }
+        default:
+                return -EINVAL;
+        }
+}
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
+{
+        return -EINVAL;
+}
+long kvm_arch_vm_ioctl(struct file *filp,
+                       unsigned int ioctl, unsigned long arg)
+{
+        return -EINVAL;
+}
+static void cpu_init_hyp_mode(void *vector)
+{
+        unsigned long long pgd_ptr;
+        unsigned long pgd_low, pgd_high;
+        unsigned long hyp_stack_ptr;
+        unsigned long stack_page;
+        unsigned long vector_ptr;
+        /* Switch from the HYP stub to our own HYP init vector */
+        __hyp_set_vectors((unsigned long)vector);
+        pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+        pgd_low = (pgd_ptr & ((1ULL << 32) - 1));
+        pgd_high = (pgd_ptr >> 32ULL);
+        stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
+        hyp_stack_ptr = stack_page + PAGE_SIZE;
+        vector_ptr = (unsigned long)__kvm_hyp_vector;
+        /*
+         * Call initialization code, and switch to the full blown
+         * HYP code. The init code doesn't need to preserve these registers as
+         * r1-r3 and r12 are already callee save according to the AAPCS.
+         * Note that we slightly misuse the prototype by casing the pgd_low to
+         * a void *.
+         */
+        kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr);
+}
+/**
+ * Inits Hyp-mode on all online CPUs
+ */
+static int init_hyp_mode(void)
+{
+        phys_addr_t init_phys_addr;
+        int cpu;
+        int err = 0;
+        /*
+         * Allocate Hyp PGD and setup Hyp identity mapping
+         */
+        err = kvm_mmu_init();
+        if (err)
+                goto out_err;
+        /*
+         * It is probably enough to obtain the default on one
+         * CPU. It's unlikely to be different on the others.
+         */
+        hyp_default_vectors = __hyp_get_vectors();
+        /*
+         * Allocate stack pages for Hypervisor-mode
+         */
+        for_each_possible_cpu(cpu) {
+                unsigned long stack_page;
+                stack_page = __get_free_page(GFP_KERNEL);
+                if (!stack_page) {
+                        err = -ENOMEM;
+                        goto out_free_stack_pages;
+                }
+                per_cpu(kvm_arm_hyp_stack_page, cpu) = stack_page;
+        }
+        /*
+         * Execute the init code on each CPU.
+         *
+         * Note: The stack is not mapped yet, so don't do anything else than
+         * initializing the hypervisor mode on each CPU using a local stack
+         * space for temporary storage.
+         */
+        init_phys_addr = virt_to_phys(__kvm_hyp_init);
+        for_each_online_cpu(cpu) {
+                smp_call_function_single(cpu, cpu_init_hyp_mode,
+                                         (void *)(long)init_phys_addr, 1);
+        }
+        /*
+         * Unmap the identity mapping
+         */
+        kvm_clear_hyp_idmap();
+        /*
+         * Map the Hyp-code called directly from the host
+         */
+        err = create_hyp_mappings(__kvm_hyp_code_start, __kvm_hyp_code_end);
+        if (err) {
+                kvm_err("Cannot map world-switch code\n");
+                goto out_free_mappings;
+        }
+        /*
+         * Map the Hyp stack pages
+         */
+        for_each_possible_cpu(cpu) {
+                char *stack_page = (char *)per_cpu(kvm_arm_hyp_stack_page, cpu);
+                err = create_hyp_mappings(stack_page, stack_page + PAGE_SIZE);
+                if (err) {
+                        kvm_err("Cannot map hyp stack\n");
+                        goto out_free_mappings;
+                }
+        }
+        /*
+         * Map the host VFP structures
+         */
+        kvm_host_vfp_state = alloc_percpu(struct vfp_hard_struct);
+        if (!kvm_host_vfp_state) {
+                err = -ENOMEM;
+                kvm_err("Cannot allocate host VFP state\n");
+                goto out_free_mappings;
+        }
+        for_each_possible_cpu(cpu) {
+                struct vfp_hard_struct *vfp;
+                vfp = per_cpu_ptr(kvm_host_vfp_state, cpu);
+                err = create_hyp_mappings(vfp, vfp + 1);
+                if (err) {
+                        kvm_err("Cannot map host VFP state: %d\n", err);
+                        goto out_free_vfp;
+                }
+        }
+        kvm_info("Hyp mode initialized successfully\n");
+        return 0;
+out_free_vfp:
+        free_percpu(kvm_host_vfp_state);
+out_free_mappings:
+        free_hyp_pmds();
+out_free_stack_pages:
+        for_each_possible_cpu(cpu)
+                free_page(per_cpu(kvm_arm_hyp_stack_page, cpu));
+out_err:
+        kvm_err("error initializing Hyp mode: %d\n", err);
+        return err;
+}
+/**
+ * Initialize Hyp-mode and memory mappings on all CPUs.
+ */
+int kvm_arch_init(void *opaque)
+{
+        int err;
+        if (!is_hyp_mode_available()) {
+                kvm_err("HYP mode not available\n");
+                return -ENODEV;
+        }
+        if (kvm_target_cpu() < 0) {
+                kvm_err("Target CPU not supported!\n");
+                return -ENODEV;
+        }
+        err = init_hyp_mode();
+        if (err)
+                goto out_err;
+        kvm_coproc_table_init();
+        return 0;
+out_err:
+        return err;
+}
+/* NOP: Compiling as a module not supported */
+void kvm_arch_exit(void)
+{
+}
+static int arm_init(void)
+{
+        int rc = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
+        return rc;
+}
+module_init(arm_init);
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
new file mode 100644
index 000000000000..d782638c7ec0
--- /dev/null
+++ b/arch/arm/kvm/coproc.c
@@ -0,0 +1,1046 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.com.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <linux/uaccess.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <trace/events/kvm.h>
+#include <asm/vfp.h>
+#include "../vfp/vfpinstr.h"
+#include "trace.h"
+#include "coproc.h"
+/******************************************************************************
+ * Co-processor emulation
+ *****************************************************************************/
+/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
+static u32 cache_levels;
+/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
+#define CSSELR_MAX 12
+int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /*
+         * We can get here, if the host has been built without VFPv3 support,
+         * but the guest attempted a floating point operation.
+         */
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+/* See note at ARM ARM B1.14.4 */
+static bool access_dcsw(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *p,
+                        const struct coproc_reg *r)
+{
+        u32 val;
+        int cpu;
+        cpu = get_cpu();
+        if (!p->is_write)
+                return read_from_write_only(vcpu, p);
+        cpumask_setall(&vcpu->arch.require_dcache_flush);
+        cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
+        /* If we were already preempted, take the long way around */
+        if (cpu != vcpu->arch.last_pcpu) {
+                flush_cache_all();
+                goto done;
+        }
+        val = *vcpu_reg(vcpu, p->Rt1);
+        switch (p->CRm) {
+        case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
+        case 14:                /* DCCISW */
+                asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
+                break;
+        case 10:                /* DCCSW */
+                asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
+                break;
+        }
+done:
+        put_cpu();
+        return true;
+}
+/*
+ * We could trap ID_DFR0 and tell the guest we don't support performance
+ * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
+ * NAKed, so it will read the PMCR anyway.
+ *
+ * Therefore we tell the guest we have 0 counters.  Unfortunately, we
+ * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
+ * all PM registers, which doesn't crash the guest kernel at least.
+ */
+static bool pm_fake(struct kvm_vcpu *vcpu,
+                    const struct coproc_params *p,
+                    const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        else
+                return read_zero(vcpu, p);
+}
+#define access_pmcr pm_fake
+#define access_pmcntenset pm_fake
+#define access_pmcntenclr pm_fake
+#define access_pmovsr pm_fake
+#define access_pmselr pm_fake
+#define access_pmceid0 pm_fake
+#define access_pmceid1 pm_fake
+#define access_pmccntr pm_fake
+#define access_pmxevtyper pm_fake
+#define access_pmxevcntr pm_fake
+#define access_pmuserenr pm_fake
+#define access_pmintenset pm_fake
+#define access_pmintenclr pm_fake
+/* Architected CP15 registers.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
+ */
+static const struct coproc_reg cp15_regs[] = {
+        /* CSSELR: swapped by interrupt.S. */
+        { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
+                        NULL, reset_unknown, c0_CSSELR },
+        /* TTBR0/TTBR1: swapped by interrupt.S. */
+        { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
+        { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
+        /* TTBCR: swapped by interrupt.S. */
+        { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_val, c2_TTBCR, 0x00000000 },
+        /* DACR: swapped by interrupt.S. */
+        { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c3_DACR },
+        /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
+        { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c5_DFSR },
+        { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c5_IFSR },
+        { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c5_ADFSR },
+        { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c5_AIFSR },
+        /* DFAR/IFAR: swapped by interrupt.S. */
+        { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c6_DFAR },
+        { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_unknown, c6_IFAR },
+        /*
+         * DC{C,I,CI}SW operations:
+         */
+        { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
+        { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
+        { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
+        /*
+         * Dummy performance monitor implementation.
+         */
+        { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
+        /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
+        { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c10_PRRR},
+        { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c10_NMRR},
+        /* VBAR: swapped by interrupt.S. */
+        { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_val, c12_VBAR, 0x00000000 },
+        /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
+        { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
+                        NULL, reset_val, c13_CID, 0x00000000 },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_unknown, c13_TID_URW },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
+                        NULL, reset_unknown, c13_TID_URO },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
+                        NULL, reset_unknown, c13_TID_PRIV },
+};
+/* Target specific emulation tables */
+static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
+void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
+{
+        target_tables[table->target] = table;
+}
+/* Get specific register table for this target. */
+static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
+{
+        struct kvm_coproc_target_table *table;
+        table = target_tables[target];
+        *num = table->num;
+        return table->table;
+}
+static const struct coproc_reg *find_reg(const struct coproc_params *params,
+                                         const struct coproc_reg table[],
+                                         unsigned int num)
+{
+        unsigned int i;
+        for (i = 0; i < num; i++) {
+                const struct coproc_reg *r = &table[i];
+                if (params->is_64bit != r->is_64)
+                        continue;
+                if (params->CRn != r->CRn)
+                        continue;
+                if (params->CRm != r->CRm)
+                        continue;
+                if (params->Op1 != r->Op1)
+                        continue;
+                if (params->Op2 != r->Op2)
+                        continue;
+                return r;
+        }
+        return NULL;
+}
+static int emulate_cp15(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *params)
+{
+        size_t num;
+        const struct coproc_reg *table, *r;
+        trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
+                                   params->CRm, params->Op2, params->is_write);
+        table = get_target_table(vcpu->arch.target, &num);
+        /* Search target-specific then generic table. */
+        r = find_reg(params, table, num);
+        if (!r)
+                r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
+        if (likely(r)) {
+                /* If we don't have an accessor, we should never get here! */
+                BUG_ON(!r->access);
+                if (likely(r->access(vcpu, params, r))) {
+                        /* Skip instruction, since it was emulated */
+                        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+                        return 1;
+                }
+                /* If access function fails, it should complain. */
+        } else {
+                kvm_err("Unsupported guest CP15 access at: %08x\n",
+                        *vcpu_pc(vcpu));
+                print_cp_instr(params);
+        }
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+/**
+ * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct coproc_params params;
+        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.is_64bit = true;
+        params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
+        params.Op2 = 0;
+        params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
+        params.CRn = 0;
+        return emulate_cp15(vcpu, &params);
+}
+static void reset_coproc_regs(struct kvm_vcpu *vcpu,
+                              const struct coproc_reg *table, size_t num)
+{
+        unsigned long i;
+        for (i = 0; i < num; i++)
+                if (table[i].reset)
+                        table[i].reset(vcpu, &table[i]);
+}
+/**
+ * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct coproc_params params;
+        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.is_64bit = false;
+        params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
+        params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
+        params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
+        params.Rt2 = 0;
+        return emulate_cp15(vcpu, &params);
+}
+/******************************************************************************
+ * Userspace API
+ *****************************************************************************/
+static bool index_to_params(u64 id, struct coproc_params *params)
+{
+        switch (id & KVM_REG_SIZE_MASK) {
+        case KVM_REG_SIZE_U32:
+                /* Any unused index bits means it's not valid. */
+                if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+                           | KVM_REG_ARM_COPROC_MASK
+                           | KVM_REG_ARM_32_CRN_MASK
+                           | KVM_REG_ARM_CRM_MASK
+                           | KVM_REG_ARM_OPC1_MASK
+                           | KVM_REG_ARM_32_OPC2_MASK))
+                        return false;
+                params->is_64bit = false;
+                params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
+                               >> KVM_REG_ARM_32_CRN_SHIFT);
+                params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
+                               >> KVM_REG_ARM_CRM_SHIFT);
+                params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
+                               >> KVM_REG_ARM_OPC1_SHIFT);
+                params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
+                               >> KVM_REG_ARM_32_OPC2_SHIFT);
+                return true;
+        case KVM_REG_SIZE_U64:
+                /* Any unused index bits means it's not valid. */
+                if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+                              | KVM_REG_ARM_COPROC_MASK
+                              | KVM_REG_ARM_CRM_MASK
+                              | KVM_REG_ARM_OPC1_MASK))
+                        return false;
+                params->is_64bit = true;
+                params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
+                               >> KVM_REG_ARM_CRM_SHIFT);
+                params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
+                               >> KVM_REG_ARM_OPC1_SHIFT);
+                params->Op2 = 0;
+                params->CRn = 0;
+                return true;
+        default:
+                return false;
+        }
+}
+/* Decode an index value, and find the cp15 coproc_reg entry. */
+static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
+                                                    u64 id)
+{
+        size_t num;
+        const struct coproc_reg *table, *r;
+        struct coproc_params params;
+        /* We only do cp15 for now. */
+        if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
+                return NULL;
+        if (!index_to_params(id, &params))
+                return NULL;
+        table = get_target_table(vcpu->arch.target, &num);
+        r = find_reg(&params, table, num);
+        if (!r)
+                r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
+        /* Not saved in the cp15 array? */
+        if (r && !r->reg)
+                r = NULL;
+        return r;
+}
+/*
+ * These are the invariant cp15 registers: we let the guest see the host
+ * versions of these, so they're part of the guest state.
+ *
+ * A future CPU may provide a mechanism to present different values to
+ * the guest, or a future kvm may trap them.
+ */
+/* Unfortunately, there's no register-argument for mrc, so generate. */
+#define FUNCTION_FOR32(crn, crm, op1, op2, name)                        \
+        static void get_##name(struct kvm_vcpu *v,                      \
+                               const struct coproc_reg *r)              \
+        {                                                               \
+                u32 val;                                                \
+                                                                        \
+                asm volatile("mrc p15, " __stringify(op1)               \
+                             ", %0, c" __stringify(crn)                 \
+                             ", c" __stringify(crm)                     \
+                             ", " __stringify(op2) "\n" : "=r" (val));  \
+                ((struct coproc_reg *)r)->val = val;                    \
+        }
+FUNCTION_FOR32(0, 0, 0, 0, MIDR)
+FUNCTION_FOR32(0, 0, 0, 1, CTR)
+FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
+FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
+FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
+FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
+FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
+FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
+FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
+FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
+FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
+FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
+FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
+FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
+FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
+FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
+FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
+FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
+FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
+FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
+FUNCTION_FOR32(0, 0, 1, 7, AIDR)
+/* ->val is filled in by kvm_invariant_coproc_table_init() */
+static struct coproc_reg invariant_cp15[] = {
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
+        { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
+        { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
+};
+static int reg_from_user(void *val, const void __user *uaddr, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+static int reg_to_user(void __user *uaddr, const void *val, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+static int get_invariant_cp15(u64 id, void __user *uaddr)
+{
+        struct coproc_params params;
+        const struct coproc_reg *r;
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+        r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
+        if (!r)
+                return -ENOENT;
+        return reg_to_user(uaddr, &r->val, id);
+}
+static int set_invariant_cp15(u64 id, void __user *uaddr)
+{
+        struct coproc_params params;
+        const struct coproc_reg *r;
+        int err;
+        u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+        r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
+        if (!r)
+                return -ENOENT;
+        err = reg_from_user(&val, uaddr, id);
+        if (err)
+                return err;
+        /* This is what we mean by invariant: you can't change it. */
+        if (r->val != val)
+                return -EINVAL;
+        return 0;
+}
+static bool is_valid_cache(u32 val)
+{
+        u32 level, ctype;
+        if (val >= CSSELR_MAX)
+                return -ENOENT;
+        /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
+        level = (val >> 1);
+        ctype = (cache_levels >> (level * 3)) & 7;
+        switch (ctype) {
+        case 0: /* No cache */
+                return false;
+        case 1: /* Instruction cache only */
+                return (val & 1);
+        case 2: /* Data cache only */
+        case 4: /* Unified cache */
+                return !(val & 1);
+        case 3: /* Separate instruction and data caches */
+                return true;
+        default: /* Reserved: we can't know instruction or data. */
+                return false;
+        }
+}
+/* Which cache CCSIDR represents depends on CSSELR value. */
+static u32 get_ccsidr(u32 csselr)
+{
+        u32 ccsidr;
+        /* Make sure noone else changes CSSELR during this! */
+        local_irq_disable();
+        /* Put value into CSSELR */
+        asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+        isb();
+        /* Read result out of CCSIDR */
+        asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+        local_irq_enable();
+        return ccsidr;
+}
+static int demux_c15_get(u64 id, void __user *uaddr)
+{
+        u32 val;
+        u32 __user *uval = uaddr;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+                return put_user(get_ccsidr(val), uval);
+        default:
+                return -ENOENT;
+        }
+}
+static int demux_c15_set(u64 id, void __user *uaddr)
+{
+        u32 val, newval;
+        u32 __user *uval = uaddr;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+                if (get_user(newval, uval))
+                        return -EFAULT;
+                /* This is also invariant: you can't change it. */
+                if (newval != get_ccsidr(val))
+                        return -EINVAL;
+                return 0;
+        default:
+                return -ENOENT;
+        }
+}
+#ifdef CONFIG_VFPv3
+static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
+                                   KVM_REG_ARM_VFP_FPSCR,
+                                   KVM_REG_ARM_VFP_FPINST,
+                                   KVM_REG_ARM_VFP_FPINST2,
+                                   KVM_REG_ARM_VFP_MVFR0,
+                                   KVM_REG_ARM_VFP_MVFR1,
+                                   KVM_REG_ARM_VFP_FPSID };
+static unsigned int num_fp_regs(void)
+{
+        if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
+                return 32;
+        else
+                return 16;
+}
+static unsigned int num_vfp_regs(void)
+{
+        /* Normal FP regs + control regs. */
+        return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
+}
+static int copy_vfp_regids(u64 __user *uindices)
+{
+        unsigned int i;
+        const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
+        const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
+        for (i = 0; i < num_fp_regs(); i++) {
+                if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
+                             uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
+                if (put_user(u32reg | vfp_sysregs[i], uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return num_vfp_regs();
+}
+static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
+{
+        u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
+        u32 val;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        if (vfpid < num_fp_regs()) {
+                if (KVM_REG_SIZE(id) != 8)
+                        return -ENOENT;
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
+                                   id);
+        }
+        /* FP control registers are all 32 bit. */
+        if (KVM_REG_SIZE(id) != 4)
+                return -ENOENT;
+        switch (vfpid) {
+        case KVM_REG_ARM_VFP_FPEXC:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
+        case KVM_REG_ARM_VFP_FPSCR:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
+        case KVM_REG_ARM_VFP_FPINST:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
+        case KVM_REG_ARM_VFP_FPINST2:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
+        case KVM_REG_ARM_VFP_MVFR0:
+                val = fmrx(MVFR0);
+                return reg_to_user(uaddr, &val, id);
+        case KVM_REG_ARM_VFP_MVFR1:
+                val = fmrx(MVFR1);
+                return reg_to_user(uaddr, &val, id);
+        case KVM_REG_ARM_VFP_FPSID:
+                val = fmrx(FPSID);
+                return reg_to_user(uaddr, &val, id);
+        default:
+                return -ENOENT;
+        }
+}
+static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
+{
+        u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
+        u32 val;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        if (vfpid < num_fp_regs()) {
+                if (KVM_REG_SIZE(id) != 8)
+                        return -ENOENT;
+                return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
+                                     uaddr, id);
+        }
+        /* FP control registers are all 32 bit. */
+        if (KVM_REG_SIZE(id) != 4)
+                return -ENOENT;
+        switch (vfpid) {
+        case KVM_REG_ARM_VFP_FPEXC:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
+        case KVM_REG_ARM_VFP_FPSCR:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
+        case KVM_REG_ARM_VFP_FPINST:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
+        case KVM_REG_ARM_VFP_FPINST2:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
+        /* These are invariant. */
+        case KVM_REG_ARM_VFP_MVFR0:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(MVFR0))
+                        return -EINVAL;
+                return 0;
+        case KVM_REG_ARM_VFP_MVFR1:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(MVFR1))
+                        return -EINVAL;
+                return 0;
+        case KVM_REG_ARM_VFP_FPSID:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(FPSID))
+                        return -EINVAL;
+                return 0;
+        default:
+                return -ENOENT;
+        }
+}
+#else /* !CONFIG_VFPv3 */
+static unsigned int num_vfp_regs(void)
+{
+        return 0;
+}
+static int copy_vfp_regids(u64 __user *uindices)
+{
+        return 0;
+}
+static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
+{
+        return -ENOENT;
+}
+static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
+{
+        return -ENOENT;
+}
+#endif /* !CONFIG_VFPv3 */
+int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct coproc_reg *r;
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_get(reg->id, uaddr);
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
+                return vfp_get_reg(vcpu, reg->id, uaddr);
+        r = index_to_coproc_reg(vcpu, reg->id);
+        if (!r)
+                return get_invariant_cp15(reg->id, uaddr);
+        /* Note: copies two regs if size is 64 bit. */
+        return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
+}
+int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct coproc_reg *r;
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_set(reg->id, uaddr);
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
+                return vfp_set_reg(vcpu, reg->id, uaddr);
+        r = index_to_coproc_reg(vcpu, reg->id);
+        if (!r)
+                return set_invariant_cp15(reg->id, uaddr);
+        /* Note: copies two regs if size is 64 bit */
+        return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
+}
+static unsigned int num_demux_regs(void)
+{
+        unsigned int i, count = 0;
+        for (i = 0; i < CSSELR_MAX; i++)
+                if (is_valid_cache(i))
+                        count++;
+        return count;
+}
+static int write_demux_regids(u64 __user *uindices)
+{
+        u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
+        unsigned int i;
+        val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
+        for (i = 0; i < CSSELR_MAX; i++) {
+                if (!is_valid_cache(i))
+                        continue;
+                if (put_user(val | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return 0;
+}
+static u64 cp15_to_index(const struct coproc_reg *reg)
+{
+        u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
+        if (reg->is_64) {
+                val |= KVM_REG_SIZE_U64;
+                val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
+                val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
+        } else {
+                val |= KVM_REG_SIZE_U32;
+                val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
+                val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
+                val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
+                val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
+        }
+        return val;
+}
+static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
+{
+        if (!*uind)
+                return true;
+        if (put_user(cp15_to_index(reg), *uind))
+                return false;
+        (*uind)++;
+        return true;
+}
+/* Assumed ordered tables, see kvm_coproc_table_init. */
+static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
+{
+        const struct coproc_reg *i1, *i2, *end1, *end2;
+        unsigned int total = 0;
+        size_t num;
+        /* We check for duplicates here, to allow arch-specific overrides. */
+        i1 = get_target_table(vcpu->arch.target, &num);
+        end1 = i1 + num;
+        i2 = cp15_regs;
+        end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
+        BUG_ON(i1 == end1 || i2 == end2);
+        /* Walk carefully, as both tables may refer to the same register. */
+        while (i1 || i2) {
+                int cmp = cmp_reg(i1, i2);
+                /* target-specific overrides generic entry. */
+                if (cmp <= 0) {
+                        /* Ignore registers we trap but don't save. */
+                        if (i1->reg) {
+                                if (!copy_reg_to_user(i1, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                } else {
+                        /* Ignore registers we trap but don't save. */
+                        if (i2->reg) {
+                                if (!copy_reg_to_user(i2, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                }
+                if (cmp <= 0 && ++i1 == end1)
+                        i1 = NULL;
+                if (cmp >= 0 && ++i2 == end2)
+                        i2 = NULL;
+        }
+        return total;
+}
+unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
+{
+        return ARRAY_SIZE(invariant_cp15)
+                + num_demux_regs()
+                + num_vfp_regs()
+                + walk_cp15(vcpu, (u64 __user *)NULL);
+}
+int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        int err;
+        /* Then give them all the invariant registers' indices. */
+        for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
+                if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        err = walk_cp15(vcpu, uindices);
+        if (err < 0)
+                return err;
+        uindices += err;
+        err = copy_vfp_regids(uindices);
+        if (err < 0)
+                return err;
+        uindices += err;
+        return write_demux_regids(uindices);
+}
+void kvm_coproc_table_init(void)
+{
+        unsigned int i;
+        /* Make sure tables are unique and in order. */
+        for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
+                BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
+        /* We abuse the reset function to overwrite the table itself. */
+        for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
+                invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
+        /*
+         * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
+         *
+         *   If software reads the Cache Type fields from Ctype1
+         *   upwards, once it has seen a value of 0b000, no caches
+         *   exist at further-out levels of the hierarchy. So, for
+         *   example, if Ctype3 is the first Cache Type field with a
+         *   value of 0b000, the values of Ctype4 to Ctype7 must be
+         *   ignored.
+         */
+        asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
+        for (i = 0; i < 7; i++)
+                if (((cache_levels >> (i*3)) & 7) == 0)
+                        break;
+        /* Clear all higher bits. */
+        cache_levels &= (1 << (i*3))-1;
+}
+/**
+ * kvm_reset_coprocs - sets cp15 registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architecturally defined reset values.
+ */
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
+{
+        size_t num;
+        const struct coproc_reg *table;
+        /* Catch someone adding a register without putting in reset entry. */
+        memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
+        /* Generic chip reset first (so target could override). */
+        reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
+        table = get_target_table(vcpu->arch.target, &num);
+        reset_coproc_regs(vcpu, table, num);
+        for (num = 1; num < NR_CP15_REGS; num++)
+                if (vcpu->arch.cp15[num] == 0x42424242)
+                        panic("Didn't reset vcpu->arch.cp15[%zi]", num);
+}
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
new file mode 100644
index 000000000000..992adfafa2ff
--- /dev/null
+++ b/arch/arm/kvm/coproc.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_COPROC_LOCAL_H__
+#define __ARM_KVM_COPROC_LOCAL_H__
+struct coproc_params {
+        unsigned long CRn;
+        unsigned long CRm;
+        unsigned long Op1;
+        unsigned long Op2;
+        unsigned long Rt1;
+        unsigned long Rt2;
+        bool is_64bit;
+        bool is_write;
+};
+struct coproc_reg {
+        /* MRC/MCR/MRRC/MCRR instruction which accesses it. */
+        unsigned long CRn;
+        unsigned long CRm;
+        unsigned long Op1;
+        unsigned long Op2;
+        bool is_64;
+        /* Trapped access from guest, if non-NULL. */
+        bool (*access)(struct kvm_vcpu *,
+                       const struct coproc_params *,
+                       const struct coproc_reg *);
+        /* Initialization for vcpu. */
+        void (*reset)(struct kvm_vcpu *, const struct coproc_reg *);
+        /* Index into vcpu->arch.cp15[], or 0 if we don't need to save it. */
+        unsigned long reg;
+        /* Value (usually reset value) */
+        u64 val;
+};
+static inline void print_cp_instr(const struct coproc_params *p)
+{
+        /* Look, we even formatted it for you to paste into the table! */
+        if (p->is_64bit) {
+                kvm_pr_unimpl(" { CRm(%2lu), Op1(%2lu), is64, func_%s },\n",
+                              p->CRm, p->Op1, p->is_write ? "write" : "read");
+        } else {
+                kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32,"
+                              " func_%s },\n",
+                              p->CRn, p->CRm, p->Op1, p->Op2,
+                              p->is_write ? "write" : "read");
+        }
+}
+static inline bool ignore_write(struct kvm_vcpu *vcpu,
+                                const struct coproc_params *p)
+{
+        return true;
+}
+static inline bool read_zero(struct kvm_vcpu *vcpu,
+                             const struct coproc_params *p)
+{
+        *vcpu_reg(vcpu, p->Rt1) = 0;
+        return true;
+}
+static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
+                                      const struct coproc_params *params)
+{
+        kvm_debug("CP15 write to read-only register at: %08x\n",
+                  *vcpu_pc(vcpu));
+        print_cp_instr(params);
+        return false;
+}
+static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
+                                        const struct coproc_params *params)
+{
+        kvm_debug("CP15 read to write-only register at: %08x\n",
+                  *vcpu_pc(vcpu));
+        print_cp_instr(params);
+        return false;
+}
+/* Reset functions */
+static inline void reset_unknown(struct kvm_vcpu *vcpu,
+                                 const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = 0xdecafbad;
+}
+static inline void reset_val(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = r->val;
+}
+static inline void reset_unknown64(struct kvm_vcpu *vcpu,
+                                   const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg + 1 >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = 0xdecafbad;
+        vcpu->arch.cp15[r->reg+1] = 0xd0c0ffee;
+}
+static inline int cmp_reg(const struct coproc_reg *i1,
+                          const struct coproc_reg *i2)
+{
+        BUG_ON(i1 == i2);
+        if (!i1)
+                return 1;
+        else if (!i2)
+                return -1;
+        if (i1->CRn != i2->CRn)
+                return i1->CRn - i2->CRn;
+        if (i1->CRm != i2->CRm)
+                return i1->CRm - i2->CRm;
+        if (i1->Op1 != i2->Op1)
+                return i1->Op1 - i2->Op1;
+        return i1->Op2 - i2->Op2;
+}
+#define CRn(_x)         .CRn = _x
+#define CRm(_x)         .CRm = _x
+#define Op1(_x)         .Op1 = _x
+#define Op2(_x)         .Op2 = _x
+#define is64            .is_64 = true
+#define is32            .is_64 = false
+#endif /* __ARM_KVM_COPROC_LOCAL_H__ */
diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c
new file mode 100644
index 000000000000..685063a6d0cf
--- /dev/null
+++ b/arch/arm/kvm/coproc_a15.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/kvm_host.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <linux/init.h>
+static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        /*
+         * Compute guest MPIDR:
+         * (Even if we present only one VCPU to the guest on an SMP
+         * host we don't set the U bit in the MPIDR, or vice versa, as
+         * revealing the underlying hardware properties is likely to
+         * be the best choice).
+         */
+        vcpu->arch.cp15[c0_MPIDR] = (read_cpuid_mpidr() & ~MPIDR_LEVEL_MASK)
+                | (vcpu->vcpu_id & MPIDR_LEVEL_MASK);
+}
+#include "coproc.h"
+/* A15 TRM 4.3.28: RO WI */
+static bool access_actlr(struct kvm_vcpu *vcpu,
+                         const struct coproc_params *p,
+                         const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR];
+        return true;
+}
+/* A15 TRM 4.3.60: R/O. */
+static bool access_cbar(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *p,
+                        const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return write_to_read_only(vcpu, p);
+        return read_zero(vcpu, p);
+}
+/* A15 TRM 4.3.48: R/O WI. */
+static bool access_l2ctlr(struct kvm_vcpu *vcpu,
+                          const struct coproc_params *p,
+                          const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR];
+        return true;
+}
+static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        u32 l2ctlr, ncores;
+        asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+        l2ctlr &= ~(3 << 24);
+        ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
+        l2ctlr |= (ncores & 3) << 24;
+        vcpu->arch.cp15[c9_L2CTLR] = l2ctlr;
+}
+static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        u32 actlr;
+        /* ACTLR contains SMP bit: make sure you create all cpus first! */
+        asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
+        /* Make the SMP bit consistent with the guest configuration */
+        if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
+                actlr |= 1U << 6;
+        else
+                actlr &= ~(1U << 6);
+        vcpu->arch.cp15[c1_ACTLR] = actlr;
+}
+/* A15 TRM 4.3.49: R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). */
+static bool access_l2ectlr(struct kvm_vcpu *vcpu,
+                           const struct coproc_params *p,
+                           const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = 0;
+        return true;
+}
+/*
+ * A15-specific CP15 registers.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
+ */
+static const struct coproc_reg a15_regs[] = {
+        /* MPIDR: we use VMPIDR for guest access. */
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
+                        NULL, reset_mpidr, c0_MPIDR },
+        /* SCTLR: swapped by interrupt.S. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_val, c1_SCTLR, 0x00C50078 },
+        /* ACTLR: trapped by HCR.TAC bit. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
+                        access_actlr, reset_actlr, c1_ACTLR },
+        /* CPACR: swapped by interrupt.S. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_val, c1_CPACR, 0x00000000 },
+        /*
+         * L2CTLR access (guest wants to know #CPUs).
+         */
+        { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
+                        access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
+        { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
+        /* The Configuration Base Address Register. */
+        { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
+};
+static struct kvm_coproc_target_table a15_target_table = {
+        .target = KVM_ARM_TARGET_CORTEX_A15,
+        .table = a15_regs,
+        .num = ARRAY_SIZE(a15_regs),
+};
+static int __init coproc_a15_init(void)
+{
+        unsigned int i;
+        for (i = 1; i < ARRAY_SIZE(a15_regs); i++)
+                BUG_ON(cmp_reg(&a15_regs[i-1],
+                               &a15_regs[i]) >= 0);
+        kvm_register_target_coproc_table(&a15_target_table);
+        return 0;
+}
+late_initcall(coproc_a15_init);
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
new file mode 100644
index 000000000000..d61450ac6665
--- /dev/null
+++ b/arch/arm/kvm/emulate.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_emulate.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+#define VCPU_NR_MODES           6
+#define VCPU_REG_OFFSET_USR     0
+#define VCPU_REG_OFFSET_FIQ     1
+#define VCPU_REG_OFFSET_IRQ     2
+#define VCPU_REG_OFFSET_SVC     3
+#define VCPU_REG_OFFSET_ABT     4
+#define VCPU_REG_OFFSET_UND     5
+#define REG_OFFSET(_reg) \
+        (offsetof(struct kvm_regs, _reg) / sizeof(u32))
+#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
+static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
+        /* USR/SYS Registers */
+        [VCPU_REG_OFFSET_USR] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
+        },
+        /* FIQ Registers */
+        [VCPU_REG_OFFSET_FIQ] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7),
+                REG_OFFSET(fiq_regs[0]), /* r8 */
+                REG_OFFSET(fiq_regs[1]), /* r9 */
+                REG_OFFSET(fiq_regs[2]), /* r10 */
+                REG_OFFSET(fiq_regs[3]), /* r11 */
+                REG_OFFSET(fiq_regs[4]), /* r12 */
+                REG_OFFSET(fiq_regs[5]), /* r13 */
+                REG_OFFSET(fiq_regs[6]), /* r14 */
+        },
+        /* IRQ Registers */
+        [VCPU_REG_OFFSET_IRQ] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(irq_regs[0]), /* r13 */
+                REG_OFFSET(irq_regs[1]), /* r14 */
+        },
+        /* SVC Registers */
+        [VCPU_REG_OFFSET_SVC] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(svc_regs[0]), /* r13 */
+                REG_OFFSET(svc_regs[1]), /* r14 */
+        },
+        /* ABT Registers */
+        [VCPU_REG_OFFSET_ABT] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(abt_regs[0]), /* r13 */
+                REG_OFFSET(abt_regs[1]), /* r14 */
+        },
+        /* UND Registers */
+        [VCPU_REG_OFFSET_UND] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(und_regs[0]), /* r13 */
+                REG_OFFSET(und_regs[1]), /* r14 */
+        },
+};
+/*
+ * Return a pointer to the register number valid in the current mode of
+ * the virtual CPU.
+ */
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
+{
+        u32 *reg_array = (u32 *)&vcpu->arch.regs;
+        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        switch (mode) {
+        case USR_MODE...SVC_MODE:
+                mode &= ~MODE32_BIT; /* 0 ... 3 */
+                break;
+        case ABT_MODE:
+                mode = VCPU_REG_OFFSET_ABT;
+                break;
+        case UND_MODE:
+                mode = VCPU_REG_OFFSET_UND;
+                break;
+        case SYSTEM_MODE:
+                mode = VCPU_REG_OFFSET_USR;
+                break;
+        default:
+                BUG();
+        }
+        return reg_array + vcpu_reg_offsets[mode][reg_num];
+}
+/*
+ * Return the SPSR for the current mode of the virtual CPU.
+ */
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
+{
+        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        switch (mode) {
+        case SVC_MODE:
+                return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
+        case ABT_MODE:
+                return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
+        case UND_MODE:
+                return &vcpu->arch.regs.KVM_ARM_UND_spsr;
+        case IRQ_MODE:
+                return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
+        case FIQ_MODE:
+                return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
+        default:
+                BUG();
+        }
+}
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu:       the vcpu pointer
+ * @run:        the kvm_run structure pointer
+ *
+ * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
+ * halt execution of world-switches and schedule other host processes until
+ * there is an incoming IRQ or FIQ to the VM.
+ */
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_wfi(*vcpu_pc(vcpu));
+        kvm_vcpu_block(vcpu);
+        return 1;
+}
+/**
+ * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
+ * @vcpu:       The VCPU pointer
+ *
+ * When exceptions occur while instructions are executed in Thumb IF-THEN
+ * blocks, the ITSTATE field of the CPSR is not advanved (updated), so we have
+ * to do this little bit of work manually. The fields map like this:
+ *
+ * IT[7:0] -> CPSR[26:25],CPSR[15:10]
+ */
+static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
+{
+        unsigned long itbits, cond;
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
+        bool is_arm = !(cpsr & PSR_T_BIT);
+        BUG_ON(is_arm && (cpsr & PSR_IT_MASK));
+        if (!(cpsr & PSR_IT_MASK))
+                return;
+        cond = (cpsr & 0xe000) >> 13;
+        itbits = (cpsr & 0x1c00) >> (10 - 2);
+        itbits |= (cpsr & (0x3 << 25)) >> 25;
+        /* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */
+        if ((itbits & 0x7) == 0)
+                itbits = cond = 0;
+        else
+                itbits = (itbits << 1) & 0x1f;
+        cpsr &= ~PSR_IT_MASK;
+        cpsr |= cond << 13;
+        cpsr |= (itbits & 0x1c) << (10 - 2);
+        cpsr |= (itbits & 0x3) << 25;
+        *vcpu_cpsr(vcpu) = cpsr;
+}
+/**
+ * kvm_skip_instr - skip a trapped instruction and proceed to the next
+ * @vcpu: The vcpu pointer
+ */
+void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+        bool is_thumb;
+        is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_T_BIT);
+        if (is_thumb && !is_wide_instr)
+                *vcpu_pc(vcpu) += 2;
+        else
+                *vcpu_pc(vcpu) += 4;
+        kvm_adjust_itstate(vcpu);
+}
+/******************************************************************************
+ * Inject exceptions into the guest
+ */
+static u32 exc_vector_base(struct kvm_vcpu *vcpu)
+{
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        u32 vbar = vcpu->arch.cp15[c12_VBAR];
+        if (sctlr & SCTLR_V)
+                return 0xffff0000;
+        else /* always have security exceptions */
+                return vbar;
+}
+/**
+ * kvm_inject_undefined - inject an undefined exception into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ *
+ * Modelled after TakeUndefInstrException() pseudocode.
+ */
+void kvm_inject_undefined(struct kvm_vcpu *vcpu)
+{
+        u32 new_lr_value;
+        u32 new_spsr_value;
+        u32 cpsr = *vcpu_cpsr(vcpu);
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        bool is_thumb = (cpsr & PSR_T_BIT);
+        u32 vect_offset = 4;
+        u32 return_offset = (is_thumb) ? 2 : 4;
+        new_spsr_value = cpsr;
+        new_lr_value = *vcpu_pc(vcpu) - return_offset;
+        *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | UND_MODE;
+        *vcpu_cpsr(vcpu) |= PSR_I_BIT;
+        *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
+        if (sctlr & SCTLR_TE)
+                *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+        if (sctlr & SCTLR_EE)
+                *vcpu_cpsr(vcpu) |= PSR_E_BIT;
+        /* Note: These now point to UND banked copies */
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_reg(vcpu, 14) = new_lr_value;
+        /* Branch to exception vector */
+        *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
+}
+/*
+ * Modelled after TakeDataAbortException() and TakePrefetchAbortException
+ * pseudocode.
+ */
+static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
+{
+        u32 new_lr_value;
+        u32 new_spsr_value;
+        u32 cpsr = *vcpu_cpsr(vcpu);
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        bool is_thumb = (cpsr & PSR_T_BIT);
+        u32 vect_offset;
+        u32 return_offset = (is_thumb) ? 4 : 0;
+        bool is_lpae;
+        new_spsr_value = cpsr;
+        new_lr_value = *vcpu_pc(vcpu) + return_offset;
+        *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | ABT_MODE;
+        *vcpu_cpsr(vcpu) |= PSR_I_BIT | PSR_A_BIT;
+        *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
+        if (sctlr & SCTLR_TE)
+                *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+        if (sctlr & SCTLR_EE)
+                *vcpu_cpsr(vcpu) |= PSR_E_BIT;
+        /* Note: These now point to ABT banked copies */
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_reg(vcpu, 14) = new_lr_value;
+        if (is_pabt)
+                vect_offset = 12;
+        else
+                vect_offset = 16;
+        /* Branch to exception vector */
+        *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
+        if (is_pabt) {
+                /* Set DFAR and DFSR */
+                vcpu->arch.cp15[c6_IFAR] = addr;
+                is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
+                /* Always give debug fault for now - should give guest a clue */
+                if (is_lpae)
+                        vcpu->arch.cp15[c5_IFSR] = 1 << 9 | 0x22;
+                else
+                        vcpu->arch.cp15[c5_IFSR] = 2;
+        } else { /* !iabt */
+                /* Set DFAR and DFSR */
+                vcpu->arch.cp15[c6_DFAR] = addr;
+                is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
+                /* Always give debug fault for now - should give guest a clue */
+                if (is_lpae)
+                        vcpu->arch.cp15[c5_DFSR] = 1 << 9 | 0x22;
+                else
+                        vcpu->arch.cp15[c5_DFSR] = 2;
+        }
+}
+/**
+ * kvm_inject_dabt - inject a data abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        inject_abt(vcpu, false, addr);
+}
+/**
+ * kvm_inject_pabt - inject a prefetch abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        inject_abt(vcpu, true, addr);
+}
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
new file mode 100644
index 000000000000..2339d9609d36
--- /dev/null
+++ b/arch/arm/kvm/guest.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
+#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+        { NULL }
+};
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+static u64 core_reg_offset_from_id(u64 id)
+{
+        return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
+static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+        struct kvm_regs *regs = &vcpu->arch.regs;
+        u64 off;
+        if (KVM_REG_SIZE(reg->id) != 4)
+                return -ENOENT;
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+                return -ENOENT;
+        return put_user(((u32 *)regs)[off], uaddr);
+}
+static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+        struct kvm_regs *regs = &vcpu->arch.regs;
+        u64 off, val;
+        if (KVM_REG_SIZE(reg->id) != 4)
+                return -ENOENT;
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+                return -ENOENT;
+        if (get_user(val, uaddr) != 0)
+                return -EFAULT;
+        if (off == KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr)) {
+                unsigned long mode = val & MODE_MASK;
+                switch (mode) {
+                case USR_MODE:
+                case FIQ_MODE:
+                case IRQ_MODE:
+                case SVC_MODE:
+                case ABT_MODE:
+                case UND_MODE:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        }
+        ((u32 *)regs)[off] = val;
+        return 0;
+}
+int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+static unsigned long num_core_regs(void)
+{
+        return sizeof(struct kvm_regs) / sizeof(u32);
+}
+/**
+ * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
+ *
+ * This is for all registers.
+ */
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
+{
+        return num_core_regs() + kvm_arm_num_coproc_regs(vcpu);
+}
+/**
+ * kvm_arm_copy_reg_indices - get indices of all registers.
+ *
+ * We do core registers right here, then we apppend coproc regs.
+ */
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        const u64 core_reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE;
+        for (i = 0; i < sizeof(struct kvm_regs)/sizeof(u32); i++) {
+                if (put_user(core_reg | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return kvm_arm_copy_coproc_indices(vcpu, uindices);
+}
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
+                return -EINVAL;
+        /* Register group 16 means we want a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return get_core_reg(vcpu, reg);
+        return kvm_arm_coproc_get_reg(vcpu, reg);
+}
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
+                return -EINVAL;
+        /* Register group 16 means we set a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return set_core_reg(vcpu, reg);
+        return kvm_arm_coproc_set_reg(vcpu, reg);
+}
+int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init)
+{
+        unsigned int i;
+        /* We can only do a cortex A15 for now. */
+        if (init->target != kvm_target_cpu())
+                return -EINVAL;
+        vcpu->arch.target = init->target;
+        bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES);
+        /* -ENOENT for unknown features, -EINVAL for invalid combinations. */
+        for (i = 0; i < sizeof(init->features) * 8; i++) {
+                if (test_bit(i, (void *)init->features)) {
+                        if (i >= KVM_VCPU_MAX_FEATURES)
+                                return -ENOENT;
+                        set_bit(i, vcpu->arch.features);
+                }
+        }
+        /* Now we know what it is, we can reset it. */
+        return kvm_reset_vcpu(vcpu);
+}
+int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
+                                  struct kvm_translation *tr)
+{
+        return -EINVAL;
+}
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
new file mode 100644
index 000000000000..9f37a79b880b
--- /dev/null
+++ b/arch/arm/kvm/init.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/linkage.h>
+#include <asm/unified.h>
+#include <asm/asm-offsets.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+/********************************************************************
+ * Hypervisor initialization
+ *   - should be called with:
+ *       r0,r1 = Hypervisor pgd pointer
+ *       r2 = top of Hyp stack (kernel VA)
+ *       r3 = pointer to hyp vectors
+ */
+        .text
+        .pushsection    .hyp.idmap.text,"ax"
+        .align 5
+__kvm_hyp_init:
+        .globl __kvm_hyp_init
+        @ Hyp-mode exception vector
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    __do_hyp_init
+        W(b)    .
+        W(b)    .
+__do_hyp_init:
+        @ Set the HTTBR to point to the hypervisor PGD pointer passed
+        mcrr    p15, 4, r0, r1, c2
+        @ Set the HTCR and VTCR to the same shareability and cacheability
+        @ settings as the non-secure TTBCR and with T0SZ == 0.
+        mrc     p15, 4, r0, c2, c0, 2   @ HTCR
+        ldr     r12, =HTCR_MASK
+        bic     r0, r0, r12
+        mrc     p15, 0, r1, c2, c0, 2   @ TTBCR
+        and     r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
+        orr     r0, r0, r1
+        mcr     p15, 4, r0, c2, c0, 2   @ HTCR
+        mrc     p15, 4, r1, c2, c1, 2   @ VTCR
+        ldr     r12, =VTCR_MASK
+        bic     r1, r1, r12
+        bic     r0, r0, #(~VTCR_HTCR_SH)        @ clear non-reusable HTCR bits
+        orr     r1, r0, r1
+        orr     r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S)
+        mcr     p15, 4, r1, c2, c1, 2   @ VTCR
+        @ Use the same memory attributes for hyp. accesses as the kernel
+        @ (copy MAIRx ro HMAIRx).
+        mrc     p15, 0, r0, c10, c2, 0
+        mcr     p15, 4, r0, c10, c2, 0
+        mrc     p15, 0, r0, c10, c2, 1
+        mcr     p15, 4, r0, c10, c2, 1
+        @ Set the HSCTLR to:
+        @  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
+        @  - Endianness: Kernel config
+        @  - Fast Interrupt Features: Kernel config
+        @  - Write permission implies XN: disabled
+        @  - Instruction cache: enabled
+        @  - Data/Unified cache: enabled
+        @  - Memory alignment checks: enabled
+        @  - MMU: enabled (this code must be run from an identity mapping)
+        mrc     p15, 4, r0, c1, c0, 0   @ HSCR
+        ldr     r12, =HSCTLR_MASK
+        bic     r0, r0, r12
+        mrc     p15, 0, r1, c1, c0, 0   @ SCTLR
+        ldr     r12, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
+        and     r1, r1, r12
+ ARM(   ldr     r12, =(HSCTLR_M | HSCTLR_A)                     )
+ THUMB( ldr     r12, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)         )
+        orr     r1, r1, r12
+        orr     r0, r0, r1
+        isb
+        mcr     p15, 4, r0, c1, c0, 0   @ HSCR
+        isb
+        @ Set stack pointer and return to the kernel
+        mov     sp, r2
+        @ Set HVBAR to point to the HYP vectors
+        mcr     p15, 4, r3, c12, c0, 0  @ HVBAR
+        eret
+        .ltorg
+        .globl __kvm_hyp_init_end
+__kvm_hyp_init_end:
+        .popsection
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
new file mode 100644
index 000000000000..c5400d2e97ca
--- /dev/null
+++ b/arch/arm/kvm/interrupts.S
@@ -0,0 +1,478 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/unified.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/vfpmacros.h>
+#include "interrupts_head.S"
+        .text
+__kvm_hyp_code_start:
+        .globl __kvm_hyp_code_start
+/********************************************************************
+ * Flush per-VMID TLBs
+ *
+ * void __kvm_tlb_flush_vmid(struct kvm *kvm);
+ *
+ * We rely on the hardware to broadcast the TLB invalidation to all CPUs
+ * inside the inner-shareable domain (which is the case for all v7
+ * implementations).  If we come across a non-IS SMP implementation, we'll
+ * have to use an IPI based mechanism. Until then, we stick to the simple
+ * hardware assisted version.
+ */
+ENTRY(__kvm_tlb_flush_vmid)
+        push    {r2, r3}
+        add     r0, r0, #KVM_VTTBR
+        ldrd    r2, r3, [r0]
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        isb
+        mcr     p15, 0, r0, c8, c3, 0   @ TLBIALLIS (rt ignored)
+        dsb
+        isb
+        mov     r2, #0
+        mov     r3, #0
+        mcrr    p15, 6, r2, r3, c2      @ Back to VMID #0
+        isb                             @ Not necessary if followed by eret
+        pop     {r2, r3}
+        bx      lr
+ENDPROC(__kvm_tlb_flush_vmid)
+/********************************************************************
+ * Flush TLBs and instruction caches of all CPUs inside the inner-shareable
+ * domain, for all VMIDs
+ *
+ * void __kvm_flush_vm_context(void);
+ */
+ENTRY(__kvm_flush_vm_context)
+        mov     r0, #0                  @ rn parameter for c15 flushes is SBZ
+        /* Invalidate NS Non-Hyp TLB Inner Shareable (TLBIALLNSNHIS) */
+        mcr     p15, 4, r0, c8, c3, 4
+        /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */
+        mcr     p15, 0, r0, c7, c1, 0
+        dsb
+        isb                             @ Not necessary if followed by eret
+        bx      lr
+ENDPROC(__kvm_flush_vm_context)
+/********************************************************************
+ *  Hypervisor world-switch code
+ *
+ *
+ * int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
+ */
+ENTRY(__kvm_vcpu_run)
+        @ Save the vcpu pointer
+        mcr     p15, 4, vcpu, c13, c0, 2        @ HTPIDR
+        save_host_regs
+        @ Store hardware CP15 state and load guest state
+        read_cp15_state store_to_vcpu = 0
+        write_cp15_state read_from_vcpu = 1
+        @ If the host kernel has not been configured with VFPv3 support,
+        @ then it is safer if we deny guests from using it as well.
+#ifdef CONFIG_VFPv3
+        @ Set FPEXC_EN so the guest doesn't trap floating point instructions
+        VFPFMRX r2, FPEXC               @ VMRS
+        push    {r2}
+        orr     r2, r2, #FPEXC_EN
+        VFPFMXR FPEXC, r2               @ VMSR
+#endif
+        @ Configure Hyp-role
+        configure_hyp_role vmentry
+        @ Trap coprocessor CRx accesses
+        set_hstr vmentry
+        set_hcptr vmentry, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+        set_hdcr vmentry
+        @ Write configured ID register into MIDR alias
+        ldr     r1, [vcpu, #VCPU_MIDR]
+        mcr     p15, 4, r1, c0, c0, 0
+        @ Write guest view of MPIDR into VMPIDR
+        ldr     r1, [vcpu, #CP15_OFFSET(c0_MPIDR)]
+        mcr     p15, 4, r1, c0, c0, 5
+        @ Set up guest memory translation
+        ldr     r1, [vcpu, #VCPU_KVM]
+        add     r1, r1, #KVM_VTTBR
+        ldrd    r2, r3, [r1]
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        @ We're all done, just restore the GPRs and go to the guest
+        restore_guest_regs
+        clrex                           @ Clear exclusive monitor
+        eret
+__kvm_vcpu_return:
+        /*
+         * return convention:
+         * guest r0, r1, r2 saved on the stack
+         * r0: vcpu pointer
+         * r1: exception code
+         */
+        save_guest_regs
+        @ Set VMID == 0
+        mov     r2, #0
+        mov     r3, #0
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        @ Don't trap coprocessor accesses for host kernel
+        set_hstr vmexit
+        set_hdcr vmexit
+        set_hcptr vmexit, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+#ifdef CONFIG_VFPv3
+        @ Save floating point registers we if let guest use them.
+        tst     r2, #(HCPTR_TCP(10) | HCPTR_TCP(11))
+        bne     after_vfp_restore
+        @ Switch VFP/NEON hardware state to the host's
+        add     r7, vcpu, #VCPU_VFP_GUEST
+        store_vfp_state r7
+        add     r7, vcpu, #VCPU_VFP_HOST
+        ldr     r7, [r7]
+        restore_vfp_state r7
+after_vfp_restore:
+        @ Restore FPEXC_EN which we clobbered on entry
+        pop     {r2}
+        VFPFMXR FPEXC, r2
+#endif
+        @ Reset Hyp-role
+        configure_hyp_role vmexit
+        @ Let host read hardware MIDR
+        mrc     p15, 0, r2, c0, c0, 0
+        mcr     p15, 4, r2, c0, c0, 0
+        @ Back to hardware MPIDR
+        mrc     p15, 0, r2, c0, c0, 5
+        mcr     p15, 4, r2, c0, c0, 5
+        @ Store guest CP15 state and restore host state
+        read_cp15_state store_to_vcpu = 1
+        write_cp15_state read_from_vcpu = 0
+        restore_host_regs
+        clrex                           @ Clear exclusive monitor
+        mov     r0, r1                  @ Return the return code
+        mov     r1, #0                  @ Clear upper bits in return value
+        bx      lr                      @ return to IOCTL
+/********************************************************************
+ *  Call function in Hyp mode
+ *
+ *
+ * u64 kvm_call_hyp(void *hypfn, ...);
+ *
+ * This is not really a variadic function in the classic C-way and care must
+ * be taken when calling this to ensure parameters are passed in registers
+ * only, since the stack will change between the caller and the callee.
+ *
+ * Call the function with the first argument containing a pointer to the
+ * function you wish to call in Hyp mode, and subsequent arguments will be
+ * passed as r0, r1, and r2 (a maximum of 3 arguments in addition to the
+ * function pointer can be passed).  The function being called must be mapped
+ * in Hyp mode (see init_hyp_mode in arch/arm/kvm/arm.c).  Return values are
+ * passed in r0 and r1.
+ *
+ * The calling convention follows the standard AAPCS:
+ *   r0 - r3: caller save
+ *   r12:     caller save
+ *   rest:    callee save
+ */
+ENTRY(kvm_call_hyp)
+        hvc     #0
+        bx      lr
+/********************************************************************
+ * Hypervisor exception vector and handlers
+ *
+ *
+ * The KVM/ARM Hypervisor ABI is defined as follows:
+ *
+ * Entry to Hyp mode from the host kernel will happen _only_ when an HVC
+ * instruction is issued since all traps are disabled when running the host
+ * kernel as per the Hyp-mode initialization at boot time.
+ *
+ * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc
+ * below) when the HVC instruction is called from SVC mode (i.e. a guest or the
+ * host kernel) and they cause a trap to the vector page + offset 0xc when HVC
+ * instructions are called from within Hyp-mode.
+ *
+ * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
+ *    Switching to Hyp mode is done through a simple HVC #0 instruction. The
+ *    exception vector code will check that the HVC comes from VMID==0 and if
+ *    so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
+ *    - r0 contains a pointer to a HYP function
+ *    - r1, r2, and r3 contain arguments to the above function.
+ *    - The HYP function will be called with its arguments in r0, r1 and r2.
+ *    On HYP function return, we return directly to SVC.
+ *
+ * Note that the above is used to execute code in Hyp-mode from a host-kernel
+ * point of view, and is a different concept from performing a world-switch and
+ * executing guest code SVC mode (with a VMID != 0).
+ */
+/* Handle undef, svc, pabt, or dabt by crashing with a user notice */
+.macro bad_exception exception_code, panic_str
+        push    {r0-r2}
+        mrrc    p15, 6, r0, r1, c2      @ Read VTTBR
+        lsr     r1, r1, #16
+        ands    r1, r1, #0xff
+        beq     99f
+        load_vcpu                       @ Load VCPU pointer
+        .if \exception_code == ARM_EXCEPTION_DATA_ABORT
+        mrc     p15, 4, r2, c5, c2, 0   @ HSR
+        mrc     p15, 4, r1, c6, c0, 0   @ HDFAR
+        str     r2, [vcpu, #VCPU_HSR]
+        str     r1, [vcpu, #VCPU_HxFAR]
+        .endif
+        .if \exception_code == ARM_EXCEPTION_PREF_ABORT
+        mrc     p15, 4, r2, c5, c2, 0   @ HSR
+        mrc     p15, 4, r1, c6, c0, 2   @ HIFAR
+        str     r2, [vcpu, #VCPU_HSR]
+        str     r1, [vcpu, #VCPU_HxFAR]
+        .endif
+        mov     r1, #\exception_code
+        b       __kvm_vcpu_return
+        @ We were in the host already. Let's craft a panic-ing return to SVC.
+99:     mrs     r2, cpsr
+        bic     r2, r2, #MODE_MASK
+        orr     r2, r2, #SVC_MODE
+THUMB(  orr     r2, r2, #PSR_T_BIT      )
+        msr     spsr_cxsf, r2
+        mrs     r1, ELR_hyp
+        ldr     r2, =BSYM(panic)
+        msr     ELR_hyp, r2
+        ldr     r0, =\panic_str
+        eret
+.endm
+        .text
+        .align 5
+__kvm_hyp_vector:
+        .globl __kvm_hyp_vector
+        @ Hyp-mode exception vector
+        W(b)    hyp_reset
+        W(b)    hyp_undef
+        W(b)    hyp_svc
+        W(b)    hyp_pabt
+        W(b)    hyp_dabt
+        W(b)    hyp_hvc
+        W(b)    hyp_irq
+        W(b)    hyp_fiq
+        .align
+hyp_reset:
+        b       hyp_reset
+        .align
+hyp_undef:
+        bad_exception ARM_EXCEPTION_UNDEFINED, und_die_str
+        .align
+hyp_svc:
+        bad_exception ARM_EXCEPTION_HVC, svc_die_str
+        .align
+hyp_pabt:
+        bad_exception ARM_EXCEPTION_PREF_ABORT, pabt_die_str
+        .align
+hyp_dabt:
+        bad_exception ARM_EXCEPTION_DATA_ABORT, dabt_die_str
+        .align
+hyp_hvc:
+        /*
+         * Getting here is either becuase of a trap from a guest or from calling
+         * HVC from the host kernel, which means "switch to Hyp mode".
+         */
+        push    {r0, r1, r2}
+        @ Check syndrome register
+        mrc     p15, 4, r1, c5, c2, 0   @ HSR
+        lsr     r0, r1, #HSR_EC_SHIFT
+#ifdef CONFIG_VFPv3
+        cmp     r0, #HSR_EC_CP_0_13
+        beq     switch_to_guest_vfp
+#endif
+        cmp     r0, #HSR_EC_HVC
+        bne     guest_trap              @ Not HVC instr.
+        /*
+         * Let's check if the HVC came from VMID 0 and allow simple
+         * switch to Hyp mode
+         */
+        mrrc    p15, 6, r0, r2, c2
+        lsr     r2, r2, #16
+        and     r2, r2, #0xff
+        cmp     r2, #0
+        bne     guest_trap              @ Guest called HVC
+host_switch_to_hyp:
+        pop     {r0, r1, r2}
+        push    {lr}
+        mrs     lr, SPSR
+        push    {lr}
+        mov     lr, r0
+        mov     r0, r1
+        mov     r1, r2
+        mov     r2, r3
+THUMB(  orr     lr, #1)
+        blx     lr                      @ Call the HYP function
+        pop     {lr}
+        msr     SPSR_csxf, lr
+        pop     {lr}
+        eret
+guest_trap:
+        load_vcpu                       @ Load VCPU pointer to r0
+        str     r1, [vcpu, #VCPU_HSR]
+        @ Check if we need the fault information
+        lsr     r1, r1, #HSR_EC_SHIFT
+        cmp     r1, #HSR_EC_IABT
+        mrceq   p15, 4, r2, c6, c0, 2   @ HIFAR
+        beq     2f
+        cmp     r1, #HSR_EC_DABT
+        bne     1f
+        mrc     p15, 4, r2, c6, c0, 0   @ HDFAR
+2:      str     r2, [vcpu, #VCPU_HxFAR]
+        /*
+         * B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
+         *
+         * Abort on the stage 2 translation for a memory access from a
+         * Non-secure PL1 or PL0 mode:
+         *
+         * For any Access flag fault or Translation fault, and also for any
+         * Permission fault on the stage 2 translation of a memory access
+         * made as part of a translation table walk for a stage 1 translation,
+         * the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
+         * is UNKNOWN.
+         */
+        /* Check for permission fault, and S1PTW */
+        mrc     p15, 4, r1, c5, c2, 0   @ HSR
+        and     r0, r1, #HSR_FSC_TYPE
+        cmp     r0, #FSC_PERM
+        tsteq   r1, #(1 << 7)           @ S1PTW
+        mrcne   p15, 4, r2, c6, c0, 4   @ HPFAR
+        bne     3f
+        /* Resolve IPA using the xFAR */
+        mcr     p15, 0, r2, c7, c8, 0   @ ATS1CPR
+        isb
+        mrrc    p15, 0, r0, r1, c7      @ PAR
+        tst     r0, #1
+        bne     4f                      @ Failed translation
+        ubfx    r2, r0, #12, #20
+        lsl     r2, r2, #4
+        orr     r2, r2, r1, lsl #24
+3:      load_vcpu                       @ Load VCPU pointer to r0
+        str     r2, [r0, #VCPU_HPFAR]
+1:      mov     r1, #ARM_EXCEPTION_HVC
+        b       __kvm_vcpu_return
+4:      pop     {r0, r1, r2}            @ Failed translation, return to guest
+        eret
+/*
+ * If VFPv3 support is not available, then we will not switch the VFP
+ * registers; however cp10 and cp11 accesses will still trap and fallback
+ * to the regular coprocessor emulation code, which currently will
+ * inject an undefined exception to the guest.
+ */
+#ifdef CONFIG_VFPv3
+switch_to_guest_vfp:
+        load_vcpu                       @ Load VCPU pointer to r0
+        push    {r3-r7}
+        @ NEON/VFP used.  Turn on VFP access.
+        set_hcptr vmexit, (HCPTR_TCP(10) | HCPTR_TCP(11))
+        @ Switch VFP/NEON hardware state to the guest's
+        add     r7, r0, #VCPU_VFP_HOST
+        ldr     r7, [r7]
+        store_vfp_state r7
+        add     r7, r0, #VCPU_VFP_GUEST
+        restore_vfp_state r7
+        pop     {r3-r7}
+        pop     {r0-r2}
+        eret
+#endif
+        .align
+hyp_irq:
+        push    {r0, r1, r2}
+        mov     r1, #ARM_EXCEPTION_IRQ
+        load_vcpu                       @ Load VCPU pointer to r0
+        b       __kvm_vcpu_return
+        .align
+hyp_fiq:
+        b       hyp_fiq
+        .ltorg
+__kvm_hyp_code_end:
+        .globl  __kvm_hyp_code_end
+        .section ".rodata"
+und_die_str:
+        .ascii  "unexpected undefined exception in Hyp mode at: %#08x"
+pabt_die_str:
+        .ascii  "unexpected prefetch abort in Hyp mode at: %#08x"
+dabt_die_str:
+        .ascii  "unexpected data abort in Hyp mode at: %#08x"
+svc_die_str:
+        .ascii  "unexpected HVC/SVC trap in Hyp mode at: %#08x"
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
new file mode 100644
index 000000000000..6a95d341e9c5
--- /dev/null
+++ b/arch/arm/kvm/interrupts_head.S
@@ -0,0 +1,441 @@
+#define VCPU_USR_REG(_reg_nr)   (VCPU_USR_REGS + (_reg_nr * 4))
+#define VCPU_USR_SP             (VCPU_USR_REG(13))
+#define VCPU_USR_LR             (VCPU_USR_REG(14))
+#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4))
+/*
+ * Many of these macros need to access the VCPU structure, which is always
+ * held in r0. These macros should never clobber r1, as it is used to hold the
+ * exception code on the return path (except of course the macro that switches
+ * all the registers before the final jump to the VM).
+ */
+vcpu    .req    r0              @ vcpu pointer always in r0
+/* Clobbers {r2-r6} */
+.macro store_vfp_state vfp_base
+        @ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions
+        VFPFMRX r2, FPEXC
+        @ Make sure VFP is enabled so we can touch the registers.
+        orr     r6, r2, #FPEXC_EN
+        VFPFMXR FPEXC, r6
+        VFPFMRX r3, FPSCR
+        tst     r2, #FPEXC_EX           @ Check for VFP Subarchitecture
+        beq     1f
+        @ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
+        @ we only need to save them if FPEXC_EX is set.
+        VFPFMRX r4, FPINST
+        tst     r2, #FPEXC_FP2V
+        VFPFMRX r5, FPINST2, ne         @ vmrsne
+        bic     r6, r2, #FPEXC_EX       @ FPEXC_EX disable
+        VFPFMXR FPEXC, r6
+1:
+        VFPFSTMIA \vfp_base, r6         @ Save VFP registers
+        stm     \vfp_base, {r2-r5}      @ Save FPEXC, FPSCR, FPINST, FPINST2
+.endm
+/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */
+.macro restore_vfp_state vfp_base
+        VFPFLDMIA \vfp_base, r6         @ Load VFP registers
+        ldm     \vfp_base, {r2-r5}      @ Load FPEXC, FPSCR, FPINST, FPINST2
+        VFPFMXR FPSCR, r3
+        tst     r2, #FPEXC_EX           @ Check for VFP Subarchitecture
+        beq     1f
+        VFPFMXR FPINST, r4
+        tst     r2, #FPEXC_FP2V
+        VFPFMXR FPINST2, r5, ne
+1:
+        VFPFMXR FPEXC, r2       @ FPEXC (last, in case !EN)
+.endm
+/* These are simply for the macros to work - value don't have meaning */
+.equ usr, 0
+.equ svc, 1
+.equ abt, 2
+.equ und, 3
+.equ irq, 4
+.equ fiq, 5
+.macro push_host_regs_mode mode
+        mrs     r2, SP_\mode
+        mrs     r3, LR_\mode
+        mrs     r4, SPSR_\mode
+        push    {r2, r3, r4}
+.endm
+/*
+ * Store all host persistent registers on the stack.
+ * Clobbers all registers, in all modes, except r0 and r1.
+ */
+.macro save_host_regs
+        /* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */
+        mrs     r2, ELR_hyp
+        push    {r2}
+        /* usr regs */
+        push    {r4-r12}        @ r0-r3 are always clobbered
+        mrs     r2, SP_usr
+        mov     r3, lr
+        push    {r2, r3}
+        push_host_regs_mode svc
+        push_host_regs_mode abt
+        push_host_regs_mode und
+        push_host_regs_mode irq
+        /* fiq regs */
+        mrs     r2, r8_fiq
+        mrs     r3, r9_fiq
+        mrs     r4, r10_fiq
+        mrs     r5, r11_fiq
+        mrs     r6, r12_fiq
+        mrs     r7, SP_fiq
+        mrs     r8, LR_fiq
+        mrs     r9, SPSR_fiq
+        push    {r2-r9}
+.endm
+.macro pop_host_regs_mode mode
+        pop     {r2, r3, r4}
+        msr     SP_\mode, r2
+        msr     LR_\mode, r3
+        msr     SPSR_\mode, r4
+.endm
+/*
+ * Restore all host registers from the stack.
+ * Clobbers all registers, in all modes, except r0 and r1.
+ */
+.macro restore_host_regs
+        pop     {r2-r9}
+        msr     r8_fiq, r2
+        msr     r9_fiq, r3
+        msr     r10_fiq, r4
+        msr     r11_fiq, r5
+        msr     r12_fiq, r6
+        msr     SP_fiq, r7
+        msr     LR_fiq, r8
+        msr     SPSR_fiq, r9
+        pop_host_regs_mode irq
+        pop_host_regs_mode und
+        pop_host_regs_mode abt
+        pop_host_regs_mode svc
+        pop     {r2, r3}
+        msr     SP_usr, r2
+        mov     lr, r3
+        pop     {r4-r12}
+        pop     {r2}
+        msr     ELR_hyp, r2
+.endm
+/*
+ * Restore SP, LR and SPSR for a given mode. offset is the offset of
+ * this mode's registers from the VCPU base.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r1, r2, r3, r4.
+ */
+.macro restore_guest_regs_mode mode, offset
+        add     r1, vcpu, \offset
+        ldm     r1, {r2, r3, r4}
+        msr     SP_\mode, r2
+        msr     LR_\mode, r3
+        msr     SPSR_\mode, r4
+.endm
+/*
+ * Restore all guest registers from the vcpu struct.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers *all* registers.
+ */
+.macro restore_guest_regs
+        restore_guest_regs_mode svc, #VCPU_SVC_REGS
+        restore_guest_regs_mode abt, #VCPU_ABT_REGS
+        restore_guest_regs_mode und, #VCPU_UND_REGS
+        restore_guest_regs_mode irq, #VCPU_IRQ_REGS
+        add     r1, vcpu, #VCPU_FIQ_REGS
+        ldm     r1, {r2-r9}
+        msr     r8_fiq, r2
+        msr     r9_fiq, r3
+        msr     r10_fiq, r4
+        msr     r11_fiq, r5
+        msr     r12_fiq, r6
+        msr     SP_fiq, r7
+        msr     LR_fiq, r8
+        msr     SPSR_fiq, r9
+        @ Load return state
+        ldr     r2, [vcpu, #VCPU_PC]
+        ldr     r3, [vcpu, #VCPU_CPSR]
+        msr     ELR_hyp, r2
+        msr     SPSR_cxsf, r3
+        @ Load user registers
+        ldr     r2, [vcpu, #VCPU_USR_SP]
+        ldr     r3, [vcpu, #VCPU_USR_LR]
+        msr     SP_usr, r2
+        mov     lr, r3
+        add     vcpu, vcpu, #(VCPU_USR_REGS)
+        ldm     vcpu, {r0-r12}
+.endm
+/*
+ * Save SP, LR and SPSR for a given mode. offset is the offset of
+ * this mode's registers from the VCPU base.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2, r3, r4, r5.
+ */
+.macro save_guest_regs_mode mode, offset
+        add     r2, vcpu, \offset
+        mrs     r3, SP_\mode
+        mrs     r4, LR_\mode
+        mrs     r5, SPSR_\mode
+        stm     r2, {r3, r4, r5}
+.endm
+/*
+ * Save all guest registers to the vcpu struct
+ * Expects guest's r0, r1, r2 on the stack.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2, r3, r4, r5.
+ */
+.macro save_guest_regs
+        @ Store usr registers
+        add     r2, vcpu, #VCPU_USR_REG(3)
+        stm     r2, {r3-r12}
+        add     r2, vcpu, #VCPU_USR_REG(0)
+        pop     {r3, r4, r5}            @ r0, r1, r2
+        stm     r2, {r3, r4, r5}
+        mrs     r2, SP_usr
+        mov     r3, lr
+        str     r2, [vcpu, #VCPU_USR_SP]
+        str     r3, [vcpu, #VCPU_USR_LR]
+        @ Store return state
+        mrs     r2, ELR_hyp
+        mrs     r3, spsr
+        str     r2, [vcpu, #VCPU_PC]
+        str     r3, [vcpu, #VCPU_CPSR]
+        @ Store other guest registers
+        save_guest_regs_mode svc, #VCPU_SVC_REGS
+        save_guest_regs_mode abt, #VCPU_ABT_REGS
+        save_guest_regs_mode und, #VCPU_UND_REGS
+        save_guest_regs_mode irq, #VCPU_IRQ_REGS
+.endm
+/* Reads cp15 registers from hardware and stores them in memory
+ * @store_to_vcpu: If 0, registers are written in-order to the stack,
+ *                 otherwise to the VCPU struct pointed to by vcpup
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2 - r12
+ */
+.macro read_cp15_state store_to_vcpu
+        mrc     p15, 0, r2, c1, c0, 0   @ SCTLR
+        mrc     p15, 0, r3, c1, c0, 2   @ CPACR
+        mrc     p15, 0, r4, c2, c0, 2   @ TTBCR
+        mrc     p15, 0, r5, c3, c0, 0   @ DACR
+        mrrc    p15, 0, r6, r7, c2      @ TTBR 0
+        mrrc    p15, 1, r8, r9, c2      @ TTBR 1
+        mrc     p15, 0, r10, c10, c2, 0 @ PRRR
+        mrc     p15, 0, r11, c10, c2, 1 @ NMRR
+        mrc     p15, 2, r12, c0, c0, 0  @ CSSELR
+        .if \store_to_vcpu == 0
+        push    {r2-r12}                @ Push CP15 registers
+        .else
+        str     r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
+        str     r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
+        str     r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
+        str     r5, [vcpu, #CP15_OFFSET(c3_DACR)]
+        add     r2, vcpu, #CP15_OFFSET(c2_TTBR0)
+        strd    r6, r7, [r2]
+        add     r2, vcpu, #CP15_OFFSET(c2_TTBR1)
+        strd    r8, r9, [r2]
+        str     r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
+        str     r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
+        str     r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
+        .endif
+        mrc     p15, 0, r2, c13, c0, 1  @ CID
+        mrc     p15, 0, r3, c13, c0, 2  @ TID_URW
+        mrc     p15, 0, r4, c13, c0, 3  @ TID_URO
+        mrc     p15, 0, r5, c13, c0, 4  @ TID_PRIV
+        mrc     p15, 0, r6, c5, c0, 0   @ DFSR
+        mrc     p15, 0, r7, c5, c0, 1   @ IFSR
+        mrc     p15, 0, r8, c5, c1, 0   @ ADFSR
+        mrc     p15, 0, r9, c5, c1, 1   @ AIFSR
+        mrc     p15, 0, r10, c6, c0, 0  @ DFAR
+        mrc     p15, 0, r11, c6, c0, 2  @ IFAR
+        mrc     p15, 0, r12, c12, c0, 0 @ VBAR
+        .if \store_to_vcpu == 0
+        push    {r2-r12}                @ Push CP15 registers
+        .else
+        str     r2, [vcpu, #CP15_OFFSET(c13_CID)]
+        str     r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
+        str     r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
+        str     r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
+        str     r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
+        str     r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
+        str     r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
+        str     r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
+        str     r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
+        str     r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
+        str     r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
+        .endif
+.endm
+/*
+ * Reads cp15 registers from memory and writes them to hardware
+ * @read_from_vcpu: If 0, registers are read in-order from the stack,
+ *                  otherwise from the VCPU struct pointed to by vcpup
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro write_cp15_state read_from_vcpu
+        .if \read_from_vcpu == 0
+        pop     {r2-r12}
+        .else
+        ldr     r2, [vcpu, #CP15_OFFSET(c13_CID)]
+        ldr     r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
+        ldr     r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
+        ldr     r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
+        ldr     r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
+        ldr     r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
+        ldr     r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
+        ldr     r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
+        ldr     r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
+        ldr     r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
+        ldr     r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
+        .endif
+        mcr     p15, 0, r2, c13, c0, 1  @ CID
+        mcr     p15, 0, r3, c13, c0, 2  @ TID_URW
+        mcr     p15, 0, r4, c13, c0, 3  @ TID_URO
+        mcr     p15, 0, r5, c13, c0, 4  @ TID_PRIV
+        mcr     p15, 0, r6, c5, c0, 0   @ DFSR
+        mcr     p15, 0, r7, c5, c0, 1   @ IFSR
+        mcr     p15, 0, r8, c5, c1, 0   @ ADFSR
+        mcr     p15, 0, r9, c5, c1, 1   @ AIFSR
+        mcr     p15, 0, r10, c6, c0, 0  @ DFAR
+        mcr     p15, 0, r11, c6, c0, 2  @ IFAR
+        mcr     p15, 0, r12, c12, c0, 0 @ VBAR
+        .if \read_from_vcpu == 0
+        pop     {r2-r12}
+        .else
+        ldr     r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
+        ldr     r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
+        ldr     r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
+        ldr     r5, [vcpu, #CP15_OFFSET(c3_DACR)]
+        add     r12, vcpu, #CP15_OFFSET(c2_TTBR0)
+        ldrd    r6, r7, [r12]
+        add     r12, vcpu, #CP15_OFFSET(c2_TTBR1)
+        ldrd    r8, r9, [r12]
+        ldr     r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
+        ldr     r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
+        ldr     r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
+        .endif
+        mcr     p15, 0, r2, c1, c0, 0   @ SCTLR
+        mcr     p15, 0, r3, c1, c0, 2   @ CPACR
+        mcr     p15, 0, r4, c2, c0, 2   @ TTBCR
+        mcr     p15, 0, r5, c3, c0, 0   @ DACR
+        mcrr    p15, 0, r6, r7, c2      @ TTBR 0
+        mcrr    p15, 1, r8, r9, c2      @ TTBR 1
+        mcr     p15, 0, r10, c10, c2, 0 @ PRRR
+        mcr     p15, 0, r11, c10, c2, 1 @ NMRR
+        mcr     p15, 2, r12, c0, c0, 0  @ CSSELR
+.endm
+/*
+ * Save the VGIC CPU state into memory
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro save_vgic_state
+.endm
+/*
+ * Restore the VGIC CPU state from memory
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro restore_vgic_state
+.endm
+.equ vmentry,   0
+.equ vmexit,    1
+/* Configures the HSTR (Hyp System Trap Register) on entry/return
+ * (hardware reset value is 0) */
+.macro set_hstr operation
+        mrc     p15, 4, r2, c1, c1, 3
+        ldr     r3, =HSTR_T(15)
+        .if \operation == vmentry
+        orr     r2, r2, r3              @ Trap CR{15}
+        .else
+        bic     r2, r2, r3              @ Don't trap any CRx accesses
+        .endif
+        mcr     p15, 4, r2, c1, c1, 3
+.endm
+/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
+ * (hardware reset value is 0). Keep previous value in r2. */
+.macro set_hcptr operation, mask
+        mrc     p15, 4, r2, c1, c1, 2
+        ldr     r3, =\mask
+        .if \operation == vmentry
+        orr     r3, r2, r3              @ Trap coproc-accesses defined in mask
+        .else
+        bic     r3, r2, r3              @ Don't trap defined coproc-accesses
+        .endif
+        mcr     p15, 4, r3, c1, c1, 2
+.endm
+/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return
+ * (hardware reset value is 0) */
+.macro set_hdcr operation
+        mrc     p15, 4, r2, c1, c1, 1
+        ldr     r3, =(HDCR_TPM|HDCR_TPMCR)
+        .if \operation == vmentry
+        orr     r2, r2, r3              @ Trap some perfmon accesses
+        .else
+        bic     r2, r2, r3              @ Don't trap any perfmon accesses
+        .endif
+        mcr     p15, 4, r2, c1, c1, 1
+.endm
+/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
+.macro configure_hyp_role operation
+        mrc     p15, 4, r2, c1, c1, 0   @ HCR
+        bic     r2, r2, #HCR_VIRT_EXCP_MASK
+        ldr     r3, =HCR_GUEST_MASK
+        .if \operation == vmentry
+        orr     r2, r2, r3
+        ldr     r3, [vcpu, #VCPU_IRQ_LINES]
+        orr     r2, r2, r3
+        .else
+        bic     r2, r2, r3
+        .endif
+        mcr     p15, 4, r2, c1, c1, 0
+.endm
+.macro load_vcpu
+        mrc     p15, 4, vcpu, c13, c0, 2        @ HTPIDR
+.endm
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
new file mode 100644
index 000000000000..0144baf82904
--- /dev/null
+++ b/arch/arm/kvm/mmio.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/kvm_host.h>
+#include <asm/kvm_mmio.h>
+#include <asm/kvm_emulate.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+/**
+ * kvm_handle_mmio_return -- Handle MMIO loads after user space emulation
+ * @vcpu: The VCPU pointer
+ * @run:  The VCPU run struct containing the mmio data
+ *
+ * This should only be called after returning from userspace for MMIO load
+ * emulation.
+ */
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        __u32 *dest;
+        unsigned int len;
+        int mask;
+        if (!run->mmio.is_write) {
+                dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt);
+                memset(dest, 0, sizeof(int));
+                len = run->mmio.len;
+                if (len > 4)
+                        return -EINVAL;
+                memcpy(dest, run->mmio.data, len);
+                trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
+                                *((u64 *)run->mmio.data));
+                if (vcpu->arch.mmio_decode.sign_extend && len < 4) {
+                        mask = 1U << ((len * 8) - 1);
+                        *dest = (*dest ^ mask) - mask;
+                }
+        }
+        return 0;
+}
+static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
+                      struct kvm_exit_mmio *mmio)
+{
+        unsigned long rt, len;
+        bool is_write, sign_extend;
+        if ((vcpu->arch.hsr >> 8) & 1) {
+                /* cache operation on I/O addr, tell guest unsupported */
+                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        if ((vcpu->arch.hsr >> 7) & 1) {
+                /* page table accesses IO mem: tell guest to fix its TTBR */
+                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        switch ((vcpu->arch.hsr >> 22) & 0x3) {
+        case 0:
+                len = 1;
+                break;
+        case 1:
+                len = 2;
+                break;
+        case 2:
+                len = 4;
+                break;
+        default:
+                kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
+                return -EFAULT;
+        }
+        is_write = vcpu->arch.hsr & HSR_WNR;
+        sign_extend = vcpu->arch.hsr & HSR_SSE;
+        rt = (vcpu->arch.hsr & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
+        if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
+                /* IO memory trying to read/write pc */
+                kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        mmio->is_write = is_write;
+        mmio->phys_addr = fault_ipa;
+        mmio->len = len;
+        vcpu->arch.mmio_decode.sign_extend = sign_extend;
+        vcpu->arch.mmio_decode.rt = rt;
+        /*
+         * The MMIO instruction is emulated and should not be re-executed
+         * in the guest.
+         */
+        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+        return 0;
+}
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa)
+{
+        struct kvm_exit_mmio mmio;
+        unsigned long rt;
+        int ret;
+        /*
+         * Prepare MMIO operation. First stash it in a private
+         * structure that we can use for in-kernel emulation. If the
+         * kernel can't handle it, copy it into run->mmio and let user
+         * space do its magic.
+         */
+        if (vcpu->arch.hsr & HSR_ISV) {
+                ret = decode_hsr(vcpu, fault_ipa, &mmio);
+                if (ret)
+                        return ret;
+        } else {
+                kvm_err("load/store instruction decoding not implemented\n");
+                return -ENOSYS;
+        }
+        rt = vcpu->arch.mmio_decode.rt;
+        trace_kvm_mmio((mmio.is_write) ? KVM_TRACE_MMIO_WRITE :
+                                         KVM_TRACE_MMIO_READ_UNSATISFIED,
+                        mmio.len, fault_ipa,
+                        (mmio.is_write) ? *vcpu_reg(vcpu, rt) : 0);
+        if (mmio.is_write)
+                memcpy(mmio.data, vcpu_reg(vcpu, rt), mmio.len);
+        kvm_prepare_mmio(run, &mmio);
+        return 0;
+}
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
new file mode 100644
index 000000000000..f30e13163a96
--- /dev/null
+++ b/arch/arm/kvm/mmu.c
@@ -0,0 +1,787 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mman.h>
+#include <linux/kvm_host.h>
+#include <linux/io.h>
+#include <trace/events/kvm.h>
+#include <asm/idmap.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_mmio.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/mach/map.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
+static void kvm_tlb_flush_vmid(struct kvm *kvm)
+{
+        kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
+}
+static void kvm_set_pte(pte_t *pte, pte_t new_pte)
+{
+        pte_val(*pte) = new_pte;
+        /*
+         * flush_pmd_entry just takes a void pointer and cleans the necessary
+         * cache entries, so we can reuse the function for ptes.
+         */
+        flush_pmd_entry(pte);
+}
+static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
+                                  int min, int max)
+{
+        void *page;
+        BUG_ON(max > KVM_NR_MEM_OBJS);
+        if (cache->nobjs >= min)
+                return 0;
+        while (cache->nobjs < max) {
+                page = (void *)__get_free_page(PGALLOC_GFP);
+                if (!page)
+                        return -ENOMEM;
+                cache->objects[cache->nobjs++] = page;
+        }
+        return 0;
+}
+static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
+{
+        while (mc->nobjs)
+                free_page((unsigned long)mc->objects[--mc->nobjs]);
+}
+static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
+{
+        void *p;
+        BUG_ON(!mc || !mc->nobjs);
+        p = mc->objects[--mc->nobjs];
+        return p;
+}
+static void free_ptes(pmd_t *pmd, unsigned long addr)
+{
+        pte_t *pte;
+        unsigned int i;
+        for (i = 0; i < PTRS_PER_PMD; i++, addr += PMD_SIZE) {
+                if (!pmd_none(*pmd) && pmd_table(*pmd)) {
+                        pte = pte_offset_kernel(pmd, addr);
+                        pte_free_kernel(NULL, pte);
+                }
+                pmd++;
+        }
+}
+/**
+ * free_hyp_pmds - free a Hyp-mode level-2 tables and child level-3 tables
+ *
+ * Assumes this is a page table used strictly in Hyp-mode and therefore contains
+ * only mappings in the kernel memory area, which is above PAGE_OFFSET.
+ */
+void free_hyp_pmds(void)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr;
+        mutex_lock(&kvm_hyp_pgd_mutex);
+        for (addr = PAGE_OFFSET; addr != 0; addr += PGDIR_SIZE) {
+                pgd = hyp_pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none(*pud))
+                        continue;
+                BUG_ON(pud_bad(*pud));
+                pmd = pmd_offset(pud, addr);
+                free_ptes(pmd, addr);
+                pmd_free(NULL, pmd);
+                pud_clear(pud);
+        }
+        mutex_unlock(&kvm_hyp_pgd_mutex);
+}
+static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
+                                    unsigned long end)
+{
+        pte_t *pte;
+        unsigned long addr;
+        struct page *page;
+        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
+                pte = pte_offset_kernel(pmd, addr);
+                BUG_ON(!virt_addr_valid(addr));
+                page = virt_to_page(addr);
+                kvm_set_pte(pte, mk_pte(page, PAGE_HYP));
+        }
+}
+static void create_hyp_io_pte_mappings(pmd_t *pmd, unsigned long start,
+                                       unsigned long end,
+                                       unsigned long *pfn_base)
+{
+        pte_t *pte;
+        unsigned long addr;
+        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
+                pte = pte_offset_kernel(pmd, addr);
+                BUG_ON(pfn_valid(*pfn_base));
+                kvm_set_pte(pte, pfn_pte(*pfn_base, PAGE_HYP_DEVICE));
+                (*pfn_base)++;
+        }
+}
+static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
+                                   unsigned long end, unsigned long *pfn_base)
+{
+        pmd_t *pmd;
+        pte_t *pte;
+        unsigned long addr, next;
+        for (addr = start; addr < end; addr = next) {
+                pmd = pmd_offset(pud, addr);
+                BUG_ON(pmd_sect(*pmd));
+                if (pmd_none(*pmd)) {
+                        pte = pte_alloc_one_kernel(NULL, addr);
+                        if (!pte) {
+                                kvm_err("Cannot allocate Hyp pte\n");
+                                return -ENOMEM;
+                        }
+                        pmd_populate_kernel(NULL, pmd, pte);
+                }
+                next = pmd_addr_end(addr, end);
+                /*
+                 * If pfn_base is NULL, we map kernel pages into HYP with the
+                 * virtual address. Otherwise, this is considered an I/O
+                 * mapping and we map the physical region starting at
+                 * *pfn_base to [start, end[.
+                 */
+                if (!pfn_base)
+                        create_hyp_pte_mappings(pmd, addr, next);
+                else
+                        create_hyp_io_pte_mappings(pmd, addr, next, pfn_base);
+        }
+        return 0;
+}
+static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
+{
+        unsigned long start = (unsigned long)from;
+        unsigned long end = (unsigned long)to;
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr, next;
+        int err = 0;
+        BUG_ON(start > end);
+        if (start < PAGE_OFFSET)
+                return -EINVAL;
+        mutex_lock(&kvm_hyp_pgd_mutex);
+        for (addr = start; addr < end; addr = next) {
+                pgd = hyp_pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none_or_clear_bad(pud)) {
+                        pmd = pmd_alloc_one(NULL, addr);
+                        if (!pmd) {
+                                kvm_err("Cannot allocate Hyp pmd\n");
+                                err = -ENOMEM;
+                                goto out;
+                        }
+                        pud_populate(NULL, pud, pmd);
+                }
+                next = pgd_addr_end(addr, end);
+                err = create_hyp_pmd_mappings(pud, addr, next, pfn_base);
+                if (err)
+                        goto out;
+        }
+out:
+        mutex_unlock(&kvm_hyp_pgd_mutex);
+        return err;
+}
+/**
+ * create_hyp_mappings - map a kernel virtual address range in Hyp mode
+ * @from:       The virtual kernel start address of the range
+ * @to:         The virtual kernel end address of the range (exclusive)
+ *
+ * The same virtual address as the kernel virtual address is also used in
+ * Hyp-mode mapping to the same underlying physical pages.
+ *
+ * Note: Wrapping around zero in the "to" address is not supported.
+ */
+int create_hyp_mappings(void *from, void *to)
+{
+        return __create_hyp_mappings(from, to, NULL);
+}
+/**
+ * create_hyp_io_mappings - map a physical IO range in Hyp mode
+ * @from:       The virtual HYP start address of the range
+ * @to:         The virtual HYP end address of the range (exclusive)
+ * @addr:       The physical start address which gets mapped
+ */
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t addr)
+{
+        unsigned long pfn = __phys_to_pfn(addr);
+        return __create_hyp_mappings(from, to, &pfn);
+}
+/**
+ * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
+ * @kvm:        The KVM struct pointer for the VM.
+ *
+ * Allocates the 1st level table only of size defined by S2_PGD_ORDER (can
+ * support either full 40-bit input addresses or limited to 32-bit input
+ * addresses). Clears the allocated pages.
+ *
+ * Note we don't need locking here as this is only called when the VM is
+ * created, which can only be done once.
+ */
+int kvm_alloc_stage2_pgd(struct kvm *kvm)
+{
+        pgd_t *pgd;
+        if (kvm->arch.pgd != NULL) {
+                kvm_err("kvm_arch already initialized?\n");
+                return -EINVAL;
+        }
+        pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, S2_PGD_ORDER);
+        if (!pgd)
+                return -ENOMEM;
+        /* stage-2 pgd must be aligned to its size */
+        VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
+        memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
+        clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
+        kvm->arch.pgd = pgd;
+        return 0;
+}
+static void clear_pud_entry(pud_t *pud)
+{
+        pmd_t *pmd_table = pmd_offset(pud, 0);
+        pud_clear(pud);
+        pmd_free(NULL, pmd_table);
+        put_page(virt_to_page(pud));
+}
+static void clear_pmd_entry(pmd_t *pmd)
+{
+        pte_t *pte_table = pte_offset_kernel(pmd, 0);
+        pmd_clear(pmd);
+        pte_free_kernel(NULL, pte_table);
+        put_page(virt_to_page(pmd));
+}
+static bool pmd_empty(pmd_t *pmd)
+{
+        struct page *pmd_page = virt_to_page(pmd);
+        return page_count(pmd_page) == 1;
+}
+static void clear_pte_entry(pte_t *pte)
+{
+        if (pte_present(*pte)) {
+                kvm_set_pte(pte, __pte(0));
+                put_page(virt_to_page(pte));
+        }
+}
+static bool pte_empty(pte_t *pte)
+{
+        struct page *pte_page = virt_to_page(pte);
+        return page_count(pte_page) == 1;
+}
+/**
+ * unmap_stage2_range -- Clear stage2 page table entries to unmap a range
+ * @kvm:   The VM pointer
+ * @start: The intermediate physical base address of the range to unmap
+ * @size:  The size of the area to unmap
+ *
+ * Clear a range of stage-2 mappings, lowering the various ref-counts.  Must
+ * be called while holding mmu_lock (unless for freeing the stage2 pgd before
+ * destroying the VM), otherwise another faulting VCPU may come in and mess
+ * with things behind our backs.
+ */
+static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *pte;
+        phys_addr_t addr = start, end = start + size;
+        u64 range;
+        while (addr < end) {
+                pgd = kvm->arch.pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none(*pud)) {
+                        addr += PUD_SIZE;
+                        continue;
+                }
+                pmd = pmd_offset(pud, addr);
+                if (pmd_none(*pmd)) {
+                        addr += PMD_SIZE;
+                        continue;
+                }
+                pte = pte_offset_kernel(pmd, addr);
+                clear_pte_entry(pte);
+                range = PAGE_SIZE;
+                /* If we emptied the pte, walk back up the ladder */
+                if (pte_empty(pte)) {
+                        clear_pmd_entry(pmd);
+                        range = PMD_SIZE;
+                        if (pmd_empty(pmd)) {
+                                clear_pud_entry(pud);
+                                range = PUD_SIZE;
+                        }
+                }
+                addr += range;
+        }
+}
+/**
+ * kvm_free_stage2_pgd - free all stage-2 tables
+ * @kvm:        The KVM struct pointer for the VM.
+ *
+ * Walks the level-1 page table pointed to by kvm->arch.pgd and frees all
+ * underlying level-2 and level-3 tables before freeing the actual level-1 table
+ * and setting the struct pointer to NULL.
+ *
+ * Note we don't need locking here as this is only called when the VM is
+ * destroyed, which can only be done once.
+ */
+void kvm_free_stage2_pgd(struct kvm *kvm)
+{
+        if (kvm->arch.pgd == NULL)
+                return;
+        unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
+        free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER);
+        kvm->arch.pgd = NULL;
+}
+static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
+                          phys_addr_t addr, const pte_t *new_pte, bool iomap)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *pte, old_pte;
+        /* Create 2nd stage page table mapping - Level 1 */
+        pgd = kvm->arch.pgd + pgd_index(addr);
+        pud = pud_offset(pgd, addr);
+        if (pud_none(*pud)) {
+                if (!cache)
+                        return 0; /* ignore calls from kvm_set_spte_hva */
+                pmd = mmu_memory_cache_alloc(cache);
+                pud_populate(NULL, pud, pmd);
+                pmd += pmd_index(addr);
+                get_page(virt_to_page(pud));
+        } else
+                pmd = pmd_offset(pud, addr);
+        /* Create 2nd stage page table mapping - Level 2 */
+        if (pmd_none(*pmd)) {
+                if (!cache)
+                        return 0; /* ignore calls from kvm_set_spte_hva */
+                pte = mmu_memory_cache_alloc(cache);
+                clean_pte_table(pte);
+                pmd_populate_kernel(NULL, pmd, pte);
+                pte += pte_index(addr);
+                get_page(virt_to_page(pmd));
+        } else
+                pte = pte_offset_kernel(pmd, addr);
+        if (iomap && pte_present(*pte))
+                return -EFAULT;
+        /* Create 2nd stage page table mapping - Level 3 */
+        old_pte = *pte;
+        kvm_set_pte(pte, *new_pte);
+        if (pte_present(old_pte))
+                kvm_tlb_flush_vmid(kvm);
+        else
+                get_page(virt_to_page(pte));
+        return 0;
+}
+/**
+ * kvm_phys_addr_ioremap - map a device range to guest IPA
+ *
+ * @kvm:        The KVM pointer
+ * @guest_ipa:  The IPA at which to insert the mapping
+ * @pa:         The physical address of the device
+ * @size:       The size of the mapping
+ */
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size)
+{
+        phys_addr_t addr, end;
+        int ret = 0;
+        unsigned long pfn;
+        struct kvm_mmu_memory_cache cache = { 0, };
+        end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK;
+        pfn = __phys_to_pfn(pa);
+        for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
+                pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR);
+                ret = mmu_topup_memory_cache(&cache, 2, 2);
+                if (ret)
+                        goto out;
+                spin_lock(&kvm->mmu_lock);
+                ret = stage2_set_pte(kvm, &cache, addr, &pte, true);
+                spin_unlock(&kvm->mmu_lock);
+                if (ret)
+                        goto out;
+                pfn++;
+        }
+out:
+        mmu_free_memory_cache(&cache);
+        return ret;
+}
+static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+        /*
+         * If we are going to insert an instruction page and the icache is
+         * either VIPT or PIPT, there is a potential problem where the host
+         * (or another VM) may have used the same page as this guest, and we
+         * read incorrect data from the icache.  If we're using a PIPT cache,
+         * we can invalidate just that page, but if we are using a VIPT cache
+         * we need to invalidate the entire icache - damn shame - as written
+         * in the ARM ARM (DDI 0406C.b - Page B3-1393).
+         *
+         * VIVT caches are tagged using both the ASID and the VMID and doesn't
+         * need any kind of flushing (DDI 0406C.b - Page B3-1392).
+         */
+        if (icache_is_pipt()) {
+                unsigned long hva = gfn_to_hva(kvm, gfn);
+                __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
+        } else if (!icache_is_vivt_asid_tagged()) {
+                /* any kind of VIPT cache */
+                __flush_icache_all();
+        }
+}
+static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
+                          gfn_t gfn, struct kvm_memory_slot *memslot,
+                          unsigned long fault_status)
+{
+        pte_t new_pte;
+        pfn_t pfn;
+        int ret;
+        bool write_fault, writable;
+        unsigned long mmu_seq;
+        struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
+        write_fault = kvm_is_write_fault(vcpu->arch.hsr);
+        if (fault_status == FSC_PERM && !write_fault) {
+                kvm_err("Unexpected L2 read permission error\n");
+                return -EFAULT;
+        }
+        /* We need minimum second+third level pages */
+        ret = mmu_topup_memory_cache(memcache, 2, KVM_NR_MEM_OBJS);
+        if (ret)
+                return ret;
+        mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /*
+         * Ensure the read of mmu_notifier_seq happens before we call
+         * gfn_to_pfn_prot (which calls get_user_pages), so that we don't risk
+         * the page we just got a reference to gets unmapped before we have a
+         * chance to grab the mmu_lock, which ensure that if the page gets
+         * unmapped afterwards, the call to kvm_unmap_hva will take it away
+         * from us again properly. This smp_rmb() interacts with the smp_wmb()
+         * in kvm_mmu_notifier_invalidate_<page|range_end>.
+         */
+        smp_rmb();
+        pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write_fault, &writable);
+        if (is_error_pfn(pfn))
+                return -EFAULT;
+        new_pte = pfn_pte(pfn, PAGE_S2);
+        coherent_icache_guest_page(vcpu->kvm, gfn);
+        spin_lock(&vcpu->kvm->mmu_lock);
+        if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
+                goto out_unlock;
+        if (writable) {
+                pte_val(new_pte) |= L_PTE_S2_RDWR;
+                kvm_set_pfn_dirty(pfn);
+        }
+        stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false);
+out_unlock:
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_release_pfn_clean(pfn);
+        return 0;
+}
+/**
+ * kvm_handle_guest_abort - handles all 2nd stage aborts
+ * @vcpu:       the VCPU pointer
+ * @run:        the kvm_run structure
+ *
+ * Any abort that gets to the host is almost guaranteed to be caused by a
+ * missing second stage translation table entry, which can mean that either the
+ * guest simply needs more memory and we must allocate an appropriate page or it
+ * can mean that the guest tried to access I/O memory, which is emulated by user
+ * space. The distinction is based on the IPA causing the fault and whether this
+ * memory region has been registered as standard RAM by user space.
+ */
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        unsigned long hsr_ec;
+        unsigned long fault_status;
+        phys_addr_t fault_ipa;
+        struct kvm_memory_slot *memslot;
+        bool is_iabt;
+        gfn_t gfn;
+        int ret, idx;
+        hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
+        is_iabt = (hsr_ec == HSR_EC_IABT);
+        fault_ipa = ((phys_addr_t)vcpu->arch.hpfar & HPFAR_MASK) << 8;
+        trace_kvm_guest_fault(*vcpu_pc(vcpu), vcpu->arch.hsr,
+                              vcpu->arch.hxfar, fault_ipa);
+        /* Check the stage-2 fault is trans. fault or write fault */
+        fault_status = (vcpu->arch.hsr & HSR_FSC_TYPE);
+        if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
+                kvm_err("Unsupported fault status: EC=%#lx DFCS=%#lx\n",
+                        hsr_ec, fault_status);
+                return -EFAULT;
+        }
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+        gfn = fault_ipa >> PAGE_SHIFT;
+        if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
+                if (is_iabt) {
+                        /* Prefetch Abort on I/O address */
+                        kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                        ret = 1;
+                        goto out_unlock;
+                }
+                if (fault_status != FSC_FAULT) {
+                        kvm_err("Unsupported fault status on io memory: %#lx\n",
+                                fault_status);
+                        ret = -EFAULT;
+                        goto out_unlock;
+                }
+                /* Adjust page offset */
+                fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK;
+                ret = io_mem_abort(vcpu, run, fault_ipa);
+                goto out_unlock;
+        }
+        memslot = gfn_to_memslot(vcpu->kvm, gfn);
+        if (!memslot->user_alloc) {
+                kvm_err("non user-alloc memslots not supported\n");
+                ret = -EINVAL;
+                goto out_unlock;
+        }
+        ret = user_mem_abort(vcpu, fault_ipa, gfn, memslot, fault_status);
+        if (ret == 0)
+                ret = 1;
+out_unlock:
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+        return ret;
+}
+static void handle_hva_to_gpa(struct kvm *kvm,
+                              unsigned long start,
+                              unsigned long end,
+                              void (*handler)(struct kvm *kvm,
+                                              gpa_t gpa, void *data),
+                              void *data)
+{
+        struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
+        slots = kvm_memslots(kvm);
+        /* we only care about the pages that the guest sees */
+        kvm_for_each_memslot(memslot, slots) {
+                unsigned long hva_start, hva_end;
+                gfn_t gfn, gfn_end;
+                hva_start = max(start, memslot->userspace_addr);
+                hva_end = min(end, memslot->userspace_addr +
+                                        (memslot->npages << PAGE_SHIFT));
+                if (hva_start >= hva_end)
+                        continue;
+                /*
+                 * {gfn(page) | page intersects with [hva_start, hva_end)} =
+                 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
+                 */
+                gfn = hva_to_gfn_memslot(hva_start, memslot);
+                gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
+                for (; gfn < gfn_end; ++gfn) {
+                        gpa_t gpa = gfn << PAGE_SHIFT;
+                        handler(kvm, gpa, data);
+                }
+        }
+}
+static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
+{
+        unmap_stage2_range(kvm, gpa, PAGE_SIZE);
+        kvm_tlb_flush_vmid(kvm);
+}
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
+{
+        unsigned long end = hva + PAGE_SIZE;
+        if (!kvm->arch.pgd)
+                return 0;
+        trace_kvm_unmap_hva(hva);
+        handle_hva_to_gpa(kvm, hva, end, &kvm_unmap_hva_handler, NULL);
+        return 0;
+}
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end)
+{
+        if (!kvm->arch.pgd)
+                return 0;
+        trace_kvm_unmap_hva_range(start, end);
+        handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);
+        return 0;
+}
+static void kvm_set_spte_handler(struct kvm *kvm, gpa_t gpa, void *data)
+{
+        pte_t *pte = (pte_t *)data;
+        stage2_set_pte(kvm, NULL, gpa, pte, false);
+}
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
+{
+        unsigned long end = hva + PAGE_SIZE;
+        pte_t stage2_pte;
+        if (!kvm->arch.pgd)
+                return;
+        trace_kvm_set_spte_hva(hva);
+        stage2_pte = pfn_pte(pte_pfn(pte), PAGE_S2);
+        handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte);
+}
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu)
+{
+        mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
+}
+phys_addr_t kvm_mmu_get_httbr(void)
+{
+        VM_BUG_ON(!virt_addr_valid(hyp_pgd));
+        return virt_to_phys(hyp_pgd);
+}
+int kvm_mmu_init(void)
+{
+        if (!hyp_pgd) {
+                kvm_err("Hyp mode PGD not allocated\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+/**
+ * kvm_clear_idmap - remove all idmaps from the hyp pgd
+ *
+ * Free the underlying pmds for all pgds in range and clear the pgds (but
+ * don't free them) afterwards.
+ */
+void kvm_clear_hyp_idmap(void)
+{
+        unsigned long addr, end;
+        unsigned long next;
+        pgd_t *pgd = hyp_pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        addr = virt_to_phys(__hyp_idmap_text_start);
+        end = virt_to_phys(__hyp_idmap_text_end);
+        pgd += pgd_index(addr);
+        do {
+                next = pgd_addr_end(addr, end);
+                if (pgd_none_or_clear_bad(pgd))
+                        continue;
+                pud = pud_offset(pgd, addr);
+                pmd = pmd_offset(pud, addr);
+                pud_clear(pud);
+                clean_pmd_entry(pmd);
+                pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
+        } while (pgd++, addr = next, addr < end);
+}
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
new file mode 100644
index 000000000000..7ee5bb7a3667
--- /dev/null
+++ b/arch/arm/kvm/psci.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2012 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kvm_host.h>
+#include <linux/wait.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_psci.h>
+/*
+ * This is an implementation of the Power State Coordination Interface
+ * as described in ARM document number ARM DEN 0022A.
+ */
+static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
+{
+        vcpu->arch.pause = true;
+}
+static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
+{
+        struct kvm *kvm = source_vcpu->kvm;
+        struct kvm_vcpu *vcpu;
+        wait_queue_head_t *wq;
+        unsigned long cpu_id;
+        phys_addr_t target_pc;
+        cpu_id = *vcpu_reg(source_vcpu, 1);
+        if (vcpu_mode_is_32bit(source_vcpu))
+                cpu_id &= ~((u32) 0);
+        if (cpu_id >= atomic_read(&kvm->online_vcpus))
+                return KVM_PSCI_RET_INVAL;
+        target_pc = *vcpu_reg(source_vcpu, 2);
+        vcpu = kvm_get_vcpu(kvm, cpu_id);
+        wq = kvm_arch_vcpu_wq(vcpu);
+        if (!waitqueue_active(wq))
+                return KVM_PSCI_RET_INVAL;
+        kvm_reset_vcpu(vcpu);
+        /* Gracefully handle Thumb2 entry point */
+        if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
+                target_pc &= ~((phys_addr_t) 1);
+                vcpu_set_thumb(vcpu);
+        }
+        *vcpu_pc(vcpu) = target_pc;
+        vcpu->arch.pause = false;
+        smp_mb();               /* Make sure the above is visible */
+        wake_up_interruptible(wq);
+        return KVM_PSCI_RET_SUCCESS;
+}
+/**
+ * kvm_psci_call - handle PSCI call if r0 value is in range
+ * @vcpu: Pointer to the VCPU struct
+ *
+ * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * The calling convention is similar to SMC calls to the secure world where
+ * the function number is placed in r0 and this function returns true if the
+ * function number specified in r0 is withing the PSCI range, and false
+ * otherwise.
+ */
+bool kvm_psci_call(struct kvm_vcpu *vcpu)
+{
+        unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
+        unsigned long val;
+        switch (psci_fn) {
+        case KVM_PSCI_FN_CPU_OFF:
+                kvm_psci_vcpu_off(vcpu);
+                val = KVM_PSCI_RET_SUCCESS;
+                break;
+        case KVM_PSCI_FN_CPU_ON:
+                val = kvm_psci_vcpu_on(vcpu);
+                break;
+        case KVM_PSCI_FN_CPU_SUSPEND:
+        case KVM_PSCI_FN_MIGRATE:
+                val = KVM_PSCI_RET_NI;
+                break;
+        default:
+                return false;
+        }
+        *vcpu_reg(vcpu, 0) = val;
+        return true;
+}
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
new file mode 100644
index 000000000000..b80256b554cd
--- /dev/null
+++ b/arch/arm/kvm/reset.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+#include <asm/unified.h>
+#include <asm/ptrace.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_coproc.h>
+/******************************************************************************
+ * Cortex-A15 Reset Values
+ */
+static const int a15_max_cpu_idx = 3;
+static struct kvm_regs a15_regs_reset = {
+        .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
+};
+/*******************************************************************************
+ * Exported reset function
+ */
+/**
+ * kvm_reset_vcpu - sets core registers and cp15 registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architectually defined reset values.
+ */
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
+{
+        struct kvm_regs *cpu_reset;
+        switch (vcpu->arch.target) {
+        case KVM_ARM_TARGET_CORTEX_A15:
+                if (vcpu->vcpu_id > a15_max_cpu_idx)
+                        return -EINVAL;
+                cpu_reset = &a15_regs_reset;
+                vcpu->arch.midr = read_cpuid_id();
+                break;
+        default:
+                return -ENODEV;
+        }
+        /* Reset core registers */
+        memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs));
+        /* Reset CP15 registers */
+        kvm_reset_coprocs(vcpu);
+        return 0;
+}
diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h
new file mode 100644
index 000000000000..a8e73ed5ad5b
--- /dev/null
+++ b/arch/arm/kvm/trace.h
@@ -0,0 +1,235 @@
+#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_KVM_H
+#include <linux/tracepoint.h>
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM kvm
+/*
+ * Tracepoints for entry/exit to guest
+ */
+TRACE_EVENT(kvm_entry,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("PC: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_exit,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("PC: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_guest_fault,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long hsr,
+                 unsigned long hxfar,
+                 unsigned long long ipa),
+        TP_ARGS(vcpu_pc, hsr, hxfar, ipa),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  hsr             )
+                __field(        unsigned long,  hxfar           )
+                __field(   unsigned long long,  ipa             )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->hsr                    = hsr;
+                __entry->hxfar                  = hxfar;
+                __entry->ipa                    = ipa;
+        ),
+        TP_printk("guest fault at PC %#08lx (hxfar %#08lx, "
+                  "ipa %#16llx, hsr %#08lx",
+                  __entry->vcpu_pc, __entry->hxfar,
+                  __entry->ipa, __entry->hsr)
+);
+TRACE_EVENT(kvm_irq_line,
+        TP_PROTO(unsigned int type, int vcpu_idx, int irq_num, int level),
+        TP_ARGS(type, vcpu_idx, irq_num, level),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   type            )
+                __field(        int,            vcpu_idx        )
+                __field(        int,            irq_num         )
+                __field(        int,            level           )
+        ),
+        TP_fast_assign(
+                __entry->type           = type;
+                __entry->vcpu_idx       = vcpu_idx;
+                __entry->irq_num        = irq_num;
+                __entry->level          = level;
+        ),
+        TP_printk("Inject %s interrupt (%d), vcpu->idx: %d, num: %d, level: %d",
+                  (__entry->type == KVM_ARM_IRQ_TYPE_CPU) ? "CPU" :
+                  (__entry->type == KVM_ARM_IRQ_TYPE_PPI) ? "VGIC PPI" :
+                  (__entry->type == KVM_ARM_IRQ_TYPE_SPI) ? "VGIC SPI" : "UNKNOWN",
+                  __entry->type, __entry->vcpu_idx, __entry->irq_num, __entry->level)
+);
+TRACE_EVENT(kvm_mmio_emulate,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long instr,
+                 unsigned long cpsr),
+        TP_ARGS(vcpu_pc, instr, cpsr),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  instr           )
+                __field(        unsigned long,  cpsr            )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->instr                  = instr;
+                __entry->cpsr                   = cpsr;
+        ),
+        TP_printk("Emulate MMIO at: 0x%08lx (instr: %08lx, cpsr: %08lx)",
+                  __entry->vcpu_pc, __entry->instr, __entry->cpsr)
+);
+/* Architecturally implementation defined CP15 register access */
+TRACE_EVENT(kvm_emulate_cp15_imp,
+        TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
+                 unsigned long CRm, unsigned long Op2, bool is_write),
+        TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   Op1             )
+                __field(        unsigned int,   Rt1             )
+                __field(        unsigned int,   CRn             )
+                __field(        unsigned int,   CRm             )
+                __field(        unsigned int,   Op2             )
+                __field(        bool,           is_write        )
+        ),
+        TP_fast_assign(
+                __entry->is_write               = is_write;
+                __entry->Op1                    = Op1;
+                __entry->Rt1                    = Rt1;
+                __entry->CRn                    = CRn;
+                __entry->CRm                    = CRm;
+                __entry->Op2                    = Op2;
+        ),
+        TP_printk("Implementation defined CP15: %s\tp15, %u, r%u, c%u, c%u, %u",
+                        (__entry->is_write) ? "mcr" : "mrc",
+                        __entry->Op1, __entry->Rt1, __entry->CRn,
+                        __entry->CRm, __entry->Op2)
+);
+TRACE_EVENT(kvm_wfi,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("guest executed wfi at: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_unmap_hva,
+        TP_PROTO(unsigned long hva),
+        TP_ARGS(hva),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  hva             )
+        ),
+        TP_fast_assign(
+                __entry->hva            = hva;
+        ),
+        TP_printk("mmu notifier unmap hva: %#08lx", __entry->hva)
+);
+TRACE_EVENT(kvm_unmap_hva_range,
+        TP_PROTO(unsigned long start, unsigned long end),
+        TP_ARGS(start, end),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  start           )
+                __field(        unsigned long,  end             )
+        ),
+        TP_fast_assign(
+                __entry->start          = start;
+                __entry->end            = end;
+        ),
+        TP_printk("mmu notifier unmap range: %#08lx -- %#08lx",
+                  __entry->start, __entry->end)
+);
+TRACE_EVENT(kvm_set_spte_hva,
+        TP_PROTO(unsigned long hva),
+        TP_ARGS(hva),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  hva             )
+        ),
+        TP_fast_assign(
+                __entry->hva            = hva;
+        ),
+        TP_printk("mmu notifier set pte hva: %#08lx", __entry->hva)
+);
+TRACE_EVENT(kvm_hvc,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long r0, unsigned long imm),
+        TP_ARGS(vcpu_pc, r0, imm),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  r0              )
+                __field(        unsigned long,  imm             )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->r0             = r0;
+                __entry->imm            = imm;
+        ),
+        TP_printk("HVC at 0x%08lx (r0: 0x%08lx, imm: 0x%lx",
+                  __entry->vcpu_pc, __entry->r0, __entry->imm)
+);
+#endif /* _TRACE_KVM_H */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH arch/arm/kvm
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE trace
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 958358c91afd..6071f4c3d654 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -352,12 +352,6 @@ config MACH_USB_A9263
          Select this if you are using a Calao Systems USB-A9263.
          <http://www.calao-systems.com>
-config MACH_NEOCORE926
-        bool "Adeneo NEOCORE926"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using the Adeneo Neocore 926 board.
 endif
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b38a1dcb79b8..39218ca6d8e8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,7 +66,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
 obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
-obj-$(CONFIG_MACH_NEOCORE926)   += board-neocore926.o
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
deleted file mode 100644
index 5b4760fe53de..000000000000
--- a/arch/arm/mach-at91/board-neocore926.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-neocore926.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation
- *  Copyright (C) 2008 ADENEO.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/fb.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <video/atmel_lcdc.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/sizes.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-static void __init neocore926_init_early(void)
-{
-        /* Initialize processor: 20 MHz crystal */
-        at91_initialize(20000000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata neocore926_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata neocore926_udc_data = {
-        .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PA15);     /* Touchscreen PENIRQ */
-}
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-static void __init neocore926_add_device_ts(void)
-{
-        at91_set_B_periph(AT91_PIN_PA15, 1);    /* External IRQ1, with pullup */
-        at91_set_gpio_input(AT91_PIN_PC13, 1);  /* Touchscreen BUSY signal */
-}
-#else
-static void __init neocore926_add_device_ts(void) {}
-#endif
-/*
- * SPI devices.
- */
-static struct spi_board_info neocore926_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 1,
-                .max_speed_hz   = 125000 * 16,
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
-        },
-#endif
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata neocore926_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PE18,
-                .wp_pin         = AT91_PIN_PE19,
-        },
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata neocore926_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata neocore926_nand_partition[] = {
-        {
-                .name   = "Linux Kernel",       /* "Partition 1", */
-                .offset = 0,
-                .size   = SZ_8M,
-        },
-        {
-                .name   = "Filesystem",         /* "Partition 2", */
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_32M,
-        },
-        {
-                .name   = "Free",               /* "Partition 3", */
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata neocore926_nand_data = {
-        .ale                    = 21,
-        .cle                    = 22,
-        .rdy_pin                = AT91_PIN_PB19,
-        .rdy_pin_active_low     = 1,
-        .enable_pin             = AT91_PIN_PD15,
-        .ecc_mode               = NAND_ECC_SOFT,
-        .parts                  = neocore926_nand_partition,
-        .num_parts              = ARRAY_SIZE(neocore926_nand_partition),
-        .det_pin                = -EINVAL,
-};
-static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 6,
-        .write_cycle            = 6,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init neocore926_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &neocore926_nand_smc_config);
-        at91_add_device_nand(&neocore926_nand_data);
-}
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(5000),
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(int on)
-{
-        at91_set_gpio_value(AT91_PIN_PA30, on);
-}
-/* Driver datas */
-static struct atmel_lcdfb_info __initdata neocore926_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9263_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB555,
-};
-#else
-static struct atmel_lcdfb_info __initdata neocore926_lcdc_data;
-#endif
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button neocore926_buttons[] = {
-        {       /* BP1, "leftclic" */
-                .code           = BTN_LEFT,
-                .gpio           = AT91_PIN_PC5,
-                .active_low     = 1,
-                .desc           = "left_click",
-                .wakeup         = 1,
-        },
-        {       /* BP2, "rightclic" */
-                .code           = BTN_RIGHT,
-                .gpio           = AT91_PIN_PC4,
-                .active_low     = 1,
-                .desc           = "right_click",
-                .wakeup         = 1,
-        },
-};
-static struct gpio_keys_platform_data neocore926_button_data = {
-        .buttons        = neocore926_buttons,
-        .nbuttons       = ARRAY_SIZE(neocore926_buttons),
-};
-static struct platform_device neocore926_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &neocore926_button_data,
-        }
-};
-static void __init neocore926_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PC5, 0);  /* left button */
-        at91_set_deglitch(AT91_PIN_PC5, 1);
-        at91_set_GPIO_periph(AT91_PIN_PC4, 0);  /* right button */
-        at91_set_deglitch(AT91_PIN_PC4, 1);
-        platform_device_register(&neocore926_button_device);
-}
-#else
-static void __init neocore926_add_device_buttons(void) {}
-#endif
-/*
- * AC97
- */
-static struct ac97c_platform_data neocore926_ac97_data = {
-        .reset_pin      = AT91_PIN_PA13,
-};
-static void __init neocore926_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&neocore926_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&neocore926_udc_data);
-        /* SPI */
-        at91_set_gpio_output(AT91_PIN_PE20, 1);         /* select spi0 clock */
-        at91_add_device_spi(neocore926_spi_devices, ARRAY_SIZE(neocore926_spi_devices));
-        /* Touchscreen */
-        neocore926_add_device_ts();
-        /* MMC */
-        at91_add_device_mci(0, &neocore926_mci0_data);
-        /* Ethernet */
-        at91_add_device_eth(&neocore926_macb_data);
-        /* NAND */
-        neocore926_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LCD Controller */
-        at91_add_device_lcdc(&neocore926_lcdc_data);
-        /* Push Buttons */
-        neocore926_add_device_buttons();
-        /* AC97 */
-        at91_add_device_ac97(&neocore926_ac97_data);
-}
-MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
-        /* Maintainer: ADENEO */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = neocore926_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = neocore926_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 97ad68a826f8..5659f7c72120 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -196,6 +196,4 @@ static inline void flush(void)
                barrier();
 }
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 48705c10a0fe..bf02471d7e7c 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -7,7 +7,6 @@ config ARCH_BCM
        select ARM_GIC
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select GENERIC_TIME
        select GPIO_BCM
        select SPARSE_IRQ
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 1a446a164c8c..6f5785985dd1 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -17,8 +17,8 @@
 #include <linux/irqchip/bcm2835.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
-#include <linux/bcm2835_timer.h>
 #include <linux/clk/bcm2835.h>
+#include <linux/clocksource.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -132,7 +132,7 @@ DT_MACHINE_START(BCM2835, "BCM2835")
        .init_irq = bcm2835_init_irq,
        .handle_irq = bcm2835_handle_irq,
        .init_machine = bcm2835_init,
-        .init_time = bcm2835_timer_init,
+        .init_time = clocksource_of_init,
        .restart = bcm2835_restart,
        .dt_compat = bcm2835_compat
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
index cc46dcc72377..bf86dca3bf71 100644
--- a/arch/arm/mach-bcm2835/include/mach/uncompress.h
+++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h
@@ -42,4 +42,3 @@ static inline void flush(void)
 }
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 7b28d6a47690..5f02d06dc655 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -53,5 +53,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
index a91b6058ab4f..7a030b99df84 100644
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -51,4 +51,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 9107691adbdb..5ac9e9384b15 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -25,35 +25,44 @@
 #define DAVINCI_CPUIDLE_MAX_STATES      2
-struct davinci_ops {
+static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
-        void (*enter) (u32 flags);
+static void __iomem *ddr2_reg_base;
-        void (*exit) (u32 flags);
+static bool ddr2_pdown;
-        u32 flags;
-};
+static void davinci_save_ddr_power(int enter, bool pdown)
+{
+        u32 val;
+        val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
+        if (enter) {
+                if (pdown)
+                        val |= DDR2_SRPD_BIT;
+                else
+                        val &= ~DDR2_SRPD_BIT;
+                val |= DDR2_LPMODEN_BIT;
+        } else {
+                val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
+        }
+        __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
+}
 /* Actual code that puts the SoC in different idle states */
 static int davinci_enter_idle(struct cpuidle_device *dev,
                                struct cpuidle_driver *drv,
                                                int index)
 {
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
+        davinci_save_ddr_power(1, ddr2_pdown);
-        struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
-        if (ops && ops->enter)
-                ops->enter(ops->flags);
        index = cpuidle_wrap_enter(dev, drv, index,
                                arm_cpuidle_simple_enter);
-        if (ops && ops->exit)
+        davinci_save_ddr_power(0, ddr2_pdown);
-                ops->exit(ops->flags);
        return index;
 }
-/* fields in davinci_ops.flags */
-#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
 static struct cpuidle_driver davinci_idle_driver = {
        .name                   = "cpuidle-davinci",
        .owner                  = THIS_MODULE,
@@ -70,45 +79,6 @@ static struct cpuidle_driver davinci_idle_driver = {
        .state_count = DAVINCI_CPUIDLE_MAX_STATES,
 };
-static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
-static void __iomem *ddr2_reg_base;
-static void davinci_save_ddr_power(int enter, bool pdown)
-{
-        u32 val;
-        val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
-        if (enter) {
-                if (pdown)
-                        val |= DDR2_SRPD_BIT;
-                else
-                        val &= ~DDR2_SRPD_BIT;
-                val |= DDR2_LPMODEN_BIT;
-        } else {
-                val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
-        }
-        __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
-}
-static void davinci_c2state_enter(u32 flags)
-{
-        davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
-}
-static void davinci_c2state_exit(u32 flags)
-{
-        davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
-}
-static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
-        [1] = {
-                .enter  = davinci_c2state_enter,
-                .exit   = davinci_c2state_exit,
-        },
-};
 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 {
        int ret;
@@ -124,11 +94,7 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
        ddr2_reg_base = pdata->ddr2_ctlr_base;
-        if (pdata->ddr2_pdown)
+        ddr2_pdown = pdata->ddr2_pdown;
-                davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
-        cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
-        device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
        ret = cpuidle_register_driver(&davinci_idle_driver);
        if (ret) {
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 3a0ff905a69b..f49c2916aa3a 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -101,4 +101,3 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 }
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 0c7911b3e155..ea84c535a110 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -8,35 +8,24 @@
 * warranty of any kind, whether express or implied.
 */
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
-#include <linux/ata_platform.h>
+#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
+#include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
-#include <asm/page.h>
+#include <linux/platform_data/dma-mv_xor.h>
-#include <asm/setup.h>
+#include <linux/platform_data/usb-ehci-orion.h>
-#include <asm/timex.h>
+#include <linux/platform_device.h>
 #include <asm/hardware/cache-tauros2.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/pci.h>
-#include <mach/dove.h>
-#include <mach/pm.h>
 #include <mach/bridge-regs.h>
-#include <asm/mach/arch.h>
+#include <mach/pm.h>
-#include <linux/irq.h>
-#include <plat/time.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <linux/platform_data/dma-mv_xor.h>
-#include <plat/irq.h>
 #include <plat/common.h>
-#include <plat/addr-map.h>
+#include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 /*****************************************************************************
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
index 2c5cdd7a3eed..5c8ae9b9d39a 100644
--- a/arch/arm/mach-dove/include/mach/uncompress.h
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -34,4 +34,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ebsa110/include/mach/uncompress.h b/arch/arm/mach-ebsa110/include/mach/uncompress.h
index 32041509fbf8..ab64bea69c72 100644
--- a/arch/arm/mach-ebsa110/include/mach/uncompress.h
+++ b/arch/arm/mach-ebsa110/include/mach/uncompress.h
@@ -42,4 +42,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d64274fc5760..d2afb4dd82ab 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -86,5 +86,3 @@ static void arch_decomp_setup(void)
 {
        ethernet_reset();
 }
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4ea80bc4ef9b..d63d399c7bae 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/gpio.h>
@@ -36,7 +37,6 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
-#include <mach/pmu.h>
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -300,6 +300,7 @@ void exynos4_restart(char mode, const char *cmd)
 void exynos5_restart(char mode, const char *cmd)
 {
+        struct device_node *np;
        u32 val;
        void __iomem *addr;
@@ -307,8 +308,9 @@ void exynos5_restart(char mode, const char *cmd)
                val = 0x1;
                addr = EXYNOS_SWRESET;
        } else if (of_machine_is_compatible("samsung,exynos5440")) {
-                val = (0x10 << 20) | (0x1 << 16);
+                np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
-                addr = EXYNOS5440_SWRESET;
+                addr = of_iomap(np, 0) + 0xcc;
+                val = (0xfff << 20) | (0x1 << 16);
        } else {
                pr_err("%s: cannot support non-DT\n", __func__);
                return;
@@ -439,218 +441,6 @@ static void __init exynos5_init_clocks(int xtal)
 #endif
 }
-#define COMBINER_ENABLE_SET     0x0
-#define COMBINER_ENABLE_CLEAR   0x4
-#define COMBINER_INT_STATUS     0xC
-static DEFINE_SPINLOCK(irq_controller_lock);
-struct combiner_chip_data {
-        unsigned int irq_offset;
-        unsigned int irq_mask;
-        void __iomem *base;
-};
-static struct irq_domain *combiner_irq_domain;
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-        struct combiner_chip_data *combiner_data =
-                irq_data_get_irq_chip_data(data);
-        return combiner_data->base;
-}
-static void combiner_mask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->hwirq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-static void combiner_unmask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->hwirq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        unsigned int cascade_irq, combiner_irq;
-        unsigned long status;
-        chained_irq_enter(chip, desc);
-        spin_lock(&irq_controller_lock);
-        status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
-        spin_unlock(&irq_controller_lock);
-        status &= chip_data->irq_mask;
-        if (status == 0)
-                goto out;
-        combiner_irq = __ffs(status);
-        cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-        if (unlikely(cascade_irq >= NR_IRQS))
-                do_bad_IRQ(cascade_irq, desc);
-        else
-                generic_handle_irq(cascade_irq);
- out:
-        chained_irq_exit(chip, desc);
-}
-static struct irq_chip combiner_chip = {
-        .name           = "COMBINER",
-        .irq_mask       = combiner_mask_irq,
-        .irq_unmask     = combiner_unmask_irq,
-};
-static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
-{
-        unsigned int max_nr;
-        if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
-        else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
-        if (combiner_nr >= max_nr)
-                BUG();
-        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
-                BUG();
-        irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-static void __init combiner_init_one(unsigned int combiner_nr,
-                                     void __iomem *base)
-{
-        combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
-                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
-        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-        /* Disable all interrupts */
-        __raw_writel(combiner_data[combiner_nr].irq_mask,
-                     base + COMBINER_ENABLE_CLEAR);
-}
-#ifdef CONFIG_OF
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-                                     struct device_node *controller,
-                                     const u32 *intspec, unsigned int intsize,
-                                     unsigned long *out_hwirq,
-                                     unsigned int *out_type)
-{
-        if (d->of_node != controller)
-                return -EINVAL;
-        if (intsize < 2)
-                return -EINVAL;
-        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
-        *out_type = 0;
-        return 0;
-}
-#else
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-                                     struct device_node *controller,
-                                     const u32 *intspec, unsigned int intsize,
-                                     unsigned long *out_hwirq,
-                                     unsigned int *out_type)
-{
-        return -EINVAL;
-}
-#endif
-static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                                   irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
-        irq_set_chip_data(irq, &combiner_data[hw >> 3]);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        return 0;
-}
-static struct irq_domain_ops combiner_irq_domain_ops = {
-        .xlate  = combiner_irq_domain_xlate,
-        .map    = combiner_irq_domain_map,
-};
-static void __init combiner_init(void __iomem *combiner_base,
-                                 struct device_node *np)
-{
-        int i, irq, irq_base;
-        unsigned int max_nr, nr_irq;
-        if (np) {
-                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
-                        pr_warning("%s: number of combiners not specified, "
-                                "setting default as %d.\n",
-                                __func__, EXYNOS4_MAX_COMBINER_NR);
-                        max_nr = EXYNOS4_MAX_COMBINER_NR;
-                }
-        } else {
-                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-                                                EXYNOS4_MAX_COMBINER_NR;
-        }
-        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
-        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
-        if (IS_ERR_VALUE(irq_base)) {
-                irq_base = COMBINER_IRQ(0, 0);
-                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
-        }
-        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
-                                &combiner_irq_domain_ops, &combiner_data);
-        if (WARN_ON(!combiner_irq_domain)) {
-                pr_warning("%s: irq domain init failed\n", __func__);
-                return;
-        }
-        for (i = 0; i < max_nr; i++) {
-                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
-                irq = IRQ_SPI(i);
-#ifdef CONFIG_OF
-                if (np)
-                        irq = irq_of_parse_and_map(np, i);
-#endif
-                combiner_cascade_irq(i, irq);
-        }
-}
-#ifdef CONFIG_OF
-static int __init combiner_of_init(struct device_node *np,
-                                   struct device_node *parent)
-{
-        void __iomem *combiner_base;
-        combiner_base = of_iomap(np, 0);
-        if (!combiner_base) {
-                pr_err("%s: failed to map combiner registers\n", __func__);
-                return -ENXIO;
-        }
-        combiner_init(combiner_base, np);
-        return 0;
-}
-static const struct of_device_id exynos_dt_irq_match[] = {
-        { .compatible = "samsung,exynos4210-combiner",
-                        .data = combiner_of_init, },
-        {},
-};
-#endif
 void __init exynos4_init_irq(void)
 {
        unsigned int gic_bank_offset;
@@ -660,10 +450,8 @@ void __init exynos4_init_irq(void)
        if (!of_have_populated_dt())
                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
-        else {
+        else
                irqchip_init();
-                of_irq_init(exynos_dt_irq_match);
-        }
 #endif
        if (!of_have_populated_dt())
@@ -681,7 +469,6 @@ void __init exynos5_init_irq(void)
 {
 #ifdef CONFIG_OF
        irqchip_init();
-        of_irq_init(exynos_dt_irq_match);
 #endif
        /*
         * The parameters of s5p_init_irq() are for VIC init.
@@ -1033,8 +820,8 @@ static int __init exynos_init_irq_eint(void)
         * interrupt support code here can be completely removed.
         */
        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,pinctrl-exynos4210", },
+                { .compatible = "samsung,exynos4210-pinctrl", },
-                { .compatible = "samsung,pinctrl-exynos4x12", },
+                { .compatible = "samsung,exynos4x12-pinctrl", },
        };
        struct device_node *pctrl_np, *wkup_np;
        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 12f2f1117e99..9339bb8954be 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -60,8 +60,31 @@ void exynos4212_register_clocks(void);
 #define exynos4212_register_clocks()
 #endif
+struct device_node;
+void combiner_init(void __iomem *combiner_base, struct device_node *np);
 extern struct smp_operations exynos_smp_ops;
 extern void exynos_cpu_die(unsigned int cpu);
+/* PMU(Power Management Unit) support */
+#define PMU_TABLE_END   NULL
+enum sys_powerdown {
+        SYS_AFTR,
+        SYS_LPA,
+        SYS_SLEEP,
+        NUM_SYS_POWERDOWN,
+};
+extern unsigned long l2x0_regs_phys;
+struct exynos_pmu_conf {
+        void __iomem *reg;
+        unsigned int val[NUM_SYS_POWERDOWN];
+};
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void s3c_cpu_resume(void);
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 050924152776..fcfe0251aa3e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -23,10 +23,11 @@
 #include <asm/cpuidle.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
-#include <mach/pmu.h>
 #include <plat/cpu.h>
+#include "common.h"
 #define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
                        (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 9d1a60951d7b..c662c89794b2 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -21,7 +21,8 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
-#include <mach/regs-audss.h>
+#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
 static int exynos4_cfg_i2s(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
deleted file mode 100644
index 7517c3f417af..000000000000
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - CPUFreq support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-enum cpufreq_level_index {
-        L0, L1, L2, L3, L4,
-        L5, L6, L7, L8, L9,
-        L10, L11, L12, L13, L14,
-        L15, L16, L17, L18, L19,
-        L20,
-};
-struct exynos_dvfs_info {
-        unsigned long   mpll_freq_khz;
-        unsigned int    pll_safe_idx;
-        unsigned int    pm_lock_idx;
-        unsigned int    max_support_idx;
-        unsigned int    min_support_idx;
-        struct clk      *cpu_clk;
-        unsigned int    *volt_table;
-        struct cpufreq_frequency_table  *freq_table;
-        void (*set_freq)(unsigned int, unsigned int);
-        bool (*need_apll_change)(unsigned int, unsigned int);
-};
-extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
-extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
-extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
deleted file mode 100644
index 7c27c2d4bf44..000000000000
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * EXYNOS4210 - PMU(Power Management Unit) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_PMU_H
-#define __ASM_ARCH_PMU_H __FILE__
-#define PMU_TABLE_END   NULL
-enum sys_powerdown {
-        SYS_AFTR,
-        SYS_LPA,
-        SYS_SLEEP,
-        NUM_SYS_POWERDOWN,
-};
-extern unsigned long l2x0_regs_phys;
-struct exynos_pmu_conf {
-        void __iomem *reg;
-        unsigned int val[NUM_SYS_POWERDOWN];
-};
-extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
-extern void s3c_cpu_resume(void);
-#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
deleted file mode 100644
index ca5a8b64218a..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-audss.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-audss.h
- *
- * Copyright (c) 2011 Samsung Electronics
- *              http://www.samsung.com
- *
- * Exynos4 Audio SubSystem clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_AUDSS_H
-#define __PLAT_REGS_AUDSS_H __FILE__
-#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
-#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0deeecffa3ae..973a06637572 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -103,6 +103,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
                                "exynos-tmu", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
+                                "samsung-i2s.0", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
+                                "samsung-i2s.1", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
+                                "samsung-i2s.2", NULL),
        {},
 };
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index b9b539cac81e..e3faaa812016 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -34,7 +34,8 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
-#include <mach/pmu.h>
+#include "common.h"
 static struct sleep_save exynos4_set_clksrc[] = {
        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
@@ -91,8 +92,8 @@ static int exynos_cpu_suspend(unsigned long arg)
        /* issue the standby signal into the pm unit. */
        cpu_do_idle();
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 static void exynos_pm_prepare(void)
@@ -282,6 +283,8 @@ static void exynos_pm_resume(void)
        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
                tmp |= S5P_CENTRAL_LOWPWR_CFG;
                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+                /* clear the wakeup state register */
+                __raw_writel(0x0, S5P_WAKEUP_STAT);
                /* No need to perform below restore code */
                goto early_wakeup;
        }
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 3a48c852be6c..daebc1abc966 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,7 +14,8 @@
 #include <linux/bug.h>
 #include <mach/regs-clock.h>
-#include <mach/pmu.h>
+#include "common.h"
 static struct exynos_pmu_conf *exynos_pmu_config;
diff --git a/arch/arm/mach-footbridge/include/mach/uncompress.h b/arch/arm/mach-footbridge/include/mach/uncompress.h
index 5dfa44287346..a69398c05a52 100644
--- a/arch/arm/mach-footbridge/include/mach/uncompress.h
+++ b/arch/arm/mach-footbridge/include/mach/uncompress.h
@@ -35,4 +35,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 0efa26247235..02e225673acb 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -39,6 +39,4 @@ static inline void flush(void)
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
index d6623234f61e..43e343c4b50a 100644
--- a/arch/arm/mach-h720x/include/mach/uncompress.h
+++ b/arch/arm/mach-h720x/include/mach/uncompress.h
@@ -32,6 +32,5 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 551c97e87a78..44b12f9c1584 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,5 +1,7 @@
 config ARCH_HIGHBANK
        bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
@@ -11,5 +13,7 @@ config ARCH_HIGHBANK
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
        select HAVE_SMP
+        select MAILBOX
+        select PL320_MBOX
        select SPARSE_IRQ
        select USE_OF
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 80235b46cb58..3f65206a9b92 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -2,7 +2,6 @@
 #define __HIGHBANK_CORE_H
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_clocks_init(void);
 extern void highbank_restart(char, const char *);
 extern void __iomem *scu_base_addr;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index fd630bccbd31..a4f9f50247d4 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -26,9 +26,11 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
 #include <linux/amba/bus.h>
+#include <linux/clk-provider.h>
 #include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
@@ -59,7 +61,7 @@ static void __init highbank_scu_map_io(void)
 void highbank_set_cpu_jump(int cpu, void *jump_addr)
 {
-        cpu = cpu_logical_map(cpu);
+        cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
@@ -110,7 +112,7 @@ static void __init highbank_timer_init(void)
        WARN_ON(!timer_base);
        irq = irq_of_parse_and_map(np, 0);
-        highbank_clocks_init();
+        of_clk_init(NULL);
        lookup.clk = of_clk_get(np, 0);
        clkdev_add(&lookup);
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 70af9d13fcef..5995df7f2622 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
 static inline void highbank_set_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        else
@@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
 static inline void highbank_clear_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
        else
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7b11d3329e81..4c9c6f9d2c55 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -480,7 +480,7 @@ config MACH_MX31ADS_WM1133_EV1
        bool "Support Wolfson Microelectronics 1133-EV1 module"
        depends on MACH_MX31ADS
        depends on MFD_WM8350_I2C
-        depends on REGULATOR_WM8350
+        depends on REGULATOR_WM8350 = y
        select MFD_WM8350_CONFIG_MODE_0
        select MFD_WM8352_CONFIG_MODE_0
        help
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 2c570cdaae7b..69858c78f40d 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -224,6 +224,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
        clk_prepare_enable(clk[emi_ahb]);
+        /* Clock source for gpt must be derived from AHB */
+        clk_set_parent(clk[per5_sel], clk[ahb]);
        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index d24b0d68e83f..30b3242a7d49 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -229,9 +229,12 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
-        clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
+        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
+        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
+        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 00737eb4e00d..67de611e29ab 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -28,12 +28,17 @@ static const char *imx31_dt_board_compat[] __initdata = {
        NULL
 };
+static void __init imx31_dt_timer_init(void)
+{
+        mx31_clocks_init_dt();
+}
 DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
        .map_io         = mx31_map_io,
        .init_early     = imx31_init_early,
        .init_irq       = mx31_init_irq,
        .handle_irq     = imx31_handle_irq,
-        .init_time      = mx31_clocks_init_dt,
+        .init_time      = imx31_dt_timer_init,
        .init_machine   = imx31_dt_init,
        .dt_compat      = imx31_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 79197d8b34aa..72516658be1e 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,10 +1,5 @@
 #include <linux/amba/serial.h>
-#ifdef CONFIG_ARCH_INTEGRATOR_AP
 extern struct amba_pl010_data ap_uart_data;
-#else
-/* Not used without Integrator/AP support anyway */
-struct amba_pl010_data ap_uart_data {};
-#endif
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 39c060f75e47..81461d218717 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -71,7 +71,7 @@ int __init integrator_init(bool is_cp)
         * hard-code them. The Integator/CP and forward have proper cell IDs.
         * Else we leave them undefined to the bus driver can autoprobe them.
         */
-        if (!is_cp) {
+        if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) {
                rtc_device.periphid     = 0x00041030;
                uart0_device.periphid   = 0x00041010;
                uart1_device.periphid   = 0x00041010;
diff --git a/arch/arm/mach-integrator/include/mach/uncompress.h b/arch/arm/mach-integrator/include/mach/uncompress.h
index 30452f00a164..8f3cc9954c16 100644
--- a/arch/arm/mach-integrator/include/mach/uncompress.h
+++ b/arch/arm/mach-integrator/include/mach/uncompress.h
@@ -46,5 +46,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 78f1b3814f77..ea961445e0e9 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -94,7 +94,7 @@ void __iomem *ap_syscon_base;
 * f1b00000     1b000000        GPIO
 */
-static struct map_desc ap_io_desc[] __initdata = {
+static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
@@ -609,7 +609,6 @@ static struct map_desc ap_io_desc_atag[] __initdata = {
 static void __init ap_map_io_atag(void)
 {
        iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
-        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
        ap_map_io();
 }
@@ -677,6 +676,7 @@ static void __init ap_init(void)
        platform_device_register(&cfi_flash_device);
+        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
        for (i = 0; i < 4; i++) {
                struct lm_device *lmdev;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4cef9a0ebbb9..2b0db82a5381 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -78,7 +78,7 @@ static void __iomem *intcp_con_base;
 * fcb00000     cb000000        CP system control
 */
-static struct map_desc intcp_io_desc[] __initdata = {
+static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h
index fa4f80522fad..d3791ece2772 100644
--- a/arch/arm/mach-iop13xx/include/mach/uncompress.h
+++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h
@@ -20,4 +20,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index 4fd715496f45..b3d45fd365e7 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -36,4 +36,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 * nothing to do
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index f99bb848c5a1..ed282e14176d 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -34,4 +34,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 * nothing to do
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index eb945a926d07..7b25c0225e46 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -53,6 +53,4 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index 9f6f496380d8..9a857ae83984 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/input.h>
 #include "common.h"
 static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 56bfe5a1605a..3264925b8318 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -14,7 +14,6 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
index f58d2e1a4042..970174ad4a70 100644
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ b/arch/arm/mach-kirkwood/board-nsa310.c
@@ -10,12 +10,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/i2c.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
+#include <linux/of.h>
 #include "common.h"
 #include "mpp.h"
@@ -79,14 +77,10 @@ static void __init nsa310_gpio_init(void)
 void __init nsa310_init(void)
 {
-        u32 dev, rev;
        kirkwood_mpp_conf(nsa310_mpp_config);
        nsa310_gpio_init();
-        kirkwood_pcie_id(&dev, &rev);
        i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info));
 }
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 77f98f2b0416..060ccf9cb63f 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -19,7 +19,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/include/mach/uncompress.h b/arch/arm/mach-kirkwood/include/mach/uncompress.h
index 75d5497df3a8..5bca5534021f 100644
--- a/arch/arm/mach-kirkwood/include/mach/uncompress.h
+++ b/arch/arm/mach-kirkwood/include/mach/uncompress.h
@@ -44,4 +44,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 8879d610308a..c089a1aea674 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -32,6 +32,5 @@ static inline void flush(void)
 }
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
index c142487d299a..1198a89183cd 100644
--- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -55,6 +55,5 @@ static inline void flush(void)
 /* NULL functions; we don't presently need them */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index d6daeb7e4ef1..8890fa8fa771 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -43,9 +43,3 @@ static inline void arch_decomp_setup(void)
        if (machine_is_avengers_lite())
                UART = (unsigned long *)UART3_BASE;
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index c14011fe832d..fa97a10d8695 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -60,8 +60,4 @@ static inline void arch_decomp_setup(void)
 {
 }
-static inline void arch_decomp_wdog(void)
-{
-}
 #endif
diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h
index 12da4cacd4a8..e8d043a0e990 100644
--- a/arch/arm/mach-msm/proc_comm.h
+++ b/arch/arm/mach-msm/proc_comm.h
@@ -253,6 +253,6 @@ enum {
                (((drvstr) & 0xF) << 17))
 int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
-void __init proc_comm_boot_wait(void);
+void proc_comm_boot_wait(void);
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
index 365264298e79..6a761c44a296 100644
--- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h
+++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
@@ -44,4 +44,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 99df4df680fd..da93bcbc74c1 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,7 +3,8 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
-obj-y += system-controller.o
+obj-y                            += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_ARCH_MVEBU)         += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index ef2811495446..533f5186e200 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -72,6 +72,5 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 }
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
 #endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-netx/include/mach/uncompress.h b/arch/arm/mach-netx/include/mach/uncompress.h
index 84f91284f612..5cb1051b5831 100644
--- a/arch/arm/mach-netx/include/mach/uncompress.h
+++ b/arch/arm/mach-netx/include/mach/uncompress.h
@@ -73,4 +73,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
index 7d4687e9cbdf..f527af6527c8 100644
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -58,6 +58,4 @@ static inline void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog() /* nothing to do here */
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index e190611e4b46..1a4e887f028d 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -24,7 +24,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
@@ -270,11 +270,17 @@ static u32 configure_dma_errata(void)
        return errata;
 }
+static const struct platform_device_info omap_dma_dev_info = {
+        .name = "omap-dma-engine",
+        .id = -1,
+        .dma_mask = DMA_BIT_MASK(32),
+};
 static int __init omap1_system_dma_init(void)
 {
        struct omap_system_dma_plat_info        *p;
        struct omap_dma_dev_attr                *d;
-        struct platform_device                  *pdev;
+        struct platform_device                  *pdev, *dma_pdev;
        int ret;
        pdev = platform_device_alloc("omap_dma_system", 0);
@@ -380,8 +386,16 @@ static int __init omap1_system_dma_init(void)
        dma_common_ch_start     = CPC;
        dma_common_ch_end       = COLOR;
+        dma_pdev = platform_device_register_full(&omap_dma_dev_info);
+        if (IS_ERR(dma_pdev)) {
+                ret = PTR_ERR(dma_pdev);
+                goto exit_release_pdev;
+        }
        return ret;
+exit_release_pdev:
+        platform_device_del(pdev);
 exit_release_chan:
        kfree(d->chan);
 exit_release_d:
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index faca808cb3d9..7f5761cffd2e 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -91,3 +91,9 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
        return platform_device_register(pdev);
 }
+static  int __init omap_i2c_cmdline(void)
+{
+        return omap_register_i2c_bus_cmdline();
+}
+subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h
index ad6fbe7d83f2..4869633de8cd 100644
--- a/arch/arm/mach-omap1/include/mach/uncompress.h
+++ b/arch/arm/mach-omap1/include/mach/uncompress.h
@@ -115,8 +115,3 @@ static inline void arch_decomp_setup(void)
                DEBUG_LL_OMAP1(3, sx1);
        } while (0);
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 41b581fd0213..c3c033f283a9 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,3 +1,26 @@
+config ARCH_OMAP
+        bool
+config ARCH_OMAP2PLUS
+        bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_OMAP
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select HAVE_CLK
+        select OMAP_DM_TIMER
+        select PINCTRL
+        select PROC_DEVICETREE if PROC_FS
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
 if ARCH_OMAP2PLUS
 menu "TI OMAP2/3/4 Specific Features"
@@ -397,7 +420,7 @@ config OMAP3_SDRC_AC_TIMING
 config OMAP4_ERRATA_I688
        bool "OMAP4 errata: Async Bridge Corruption"
-        depends on ARCH_OMAP4
+        depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
        select ARCH_HAS_BARRIERS
        help
          If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 947cafe65aef..65fb6fb38caf 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -2,6 +2,9 @@
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-omap/include
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 5f413968d568..a3e0aaa4886b 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -27,6 +27,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -263,6 +264,7 @@ static void __init omap_2430sdp_init(void)
        omap_hsmmc_init(mmc);
        omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_smc91x_init();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index c22a981086f7..15a3914ab492 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -579,6 +580,7 @@ static void __init omap_3430sdp_init(void)
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
        omap_serial_init();
        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index f8eeef40efe8..508e2752b7de 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -29,6 +29,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap4-keypad.h>
 #include <linux/usb/musb.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -696,6 +697,7 @@ static void __init omap_4430sdp_init(void)
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
        usb_musb_init(&musb_board_data);
        status = omap_ethernet_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 343130c02bb0..10054e3c3482 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
@@ -724,6 +725,7 @@ static void __init cm_t3x_common_init(void)
        cm_t35_init_display();
        omap_twl4030_audio_init("cm-t3x");
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        cm_t35_init_usbh();
        cm_t35_init_camera();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index f3a59c79caeb..4dadb0b7b808 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -622,6 +623,7 @@ static void __init devkit8000_init(void)
        omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(devkit8000_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 8022f563074a..c10738a067cd 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -18,6 +18,7 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/input.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -625,6 +626,7 @@ static void __init igep_init(void)
        omap_serial_init();
        omap_sdrc_init(m65kxxxxam_sdrc_params,
                                  m65kxxxxam_sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        igep_flash_init();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ff440c0d04dd..b12fe966a7b9 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
@@ -418,6 +419,7 @@ static void __init omap_ldp_init(void)
        omap_ads7846_init(1, 54, 310, NULL);
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
                        ZOOM_NAND_CS, 0, nand_default_timings);
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 67769ef6d184..70bc1fc808c8 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -30,6 +30,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -494,7 +495,7 @@ static int __init beagle_opp_init(void)
        }
        return 0;
 }
-device_initcall(beagle_opp_init);
+omap_device_initcall(beagle_opp_init);
 static void __init omap3_beagle_init(void)
 {
@@ -519,6 +520,7 @@ static void __init omap3_beagle_init(void)
        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                                  mt46h32m32lf6_sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3beagle_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b13459bee8cb..8258a78c3dfb 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -41,6 +41,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
 #include <linux/export.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -309,7 +310,7 @@ static struct omap2_hsmmc_info mmc[] = {
                .gpio_wp        = 63,
                .deferred       = true,
        },
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        {
                .name           = "wl1271",
                .mmc            = 2,
@@ -450,7 +451,7 @@ static struct regulator_init_data omap3evm_vio = {
        .consumer_supplies      = omap3evm_vio_supply,
 };
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
 #define OMAP3EVM_WLAN_PMENA_GPIO        (150)
 #define OMAP3EVM_WLAN_IRQ_GPIO          (149)
@@ -563,7 +564,7 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
                                OMAP_PIN_OFF_NONE),
        OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
                                OMAP_PIN_OFF_NONE),
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        /* WLAN IRQ - GPIO 149 */
        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
@@ -601,7 +602,7 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = {
        OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
        OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        /* WLAN IRQ - GPIO 149 */
        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
@@ -637,7 +638,7 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = {
 static void __init omap3_evm_wl12xx_init(void)
 {
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        int ret;
        /* WL12xx WLAN Init */
@@ -734,6 +735,7 @@ static void __init omap3_evm_init(void)
                omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
                usbhs_bdata.reset_gpio_port[1] = 135;
        }
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(&musb_board_data);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3evm_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 0fba43a9b07d..bab51e64c4b5 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -29,6 +29,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,6 +216,7 @@ static void __init omap3logic_init(void)
        board_mmc_init();
        board_smsc911x_init();
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 39806754c875..2bba362148a0 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -35,6 +35,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
@@ -601,6 +602,7 @@ static void __init omap3pandora_init(void)
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
        usbhs_init(&usbhs_bdata);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        gpmc_nand_init(&pandora_nand_data, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 73417474b08c..95c10b3aa678 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -33,6 +33,7 @@
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/i2c/at24.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -404,6 +405,7 @@ static void __init omap3_stalker_init(void)
        omap_serial_init();
        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index fc83c963ba93..bcd44fbcd877 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
@@ -365,6 +366,7 @@ static void __init omap3_touchbook_init(void)
        /* Touchscreen and accelerometer */
        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3touchbook_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 824cdffb129f..b02c2f00609b 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
+#include <linux/usb/phy.h>
 #include <linux/wl12xx.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -447,6 +448,7 @@ static void __init omap4_panda_init(void)
        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
+        usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
        usb_musb_init(&musb_board_data);
        omap4_panda_display_init();
 }
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index e425d53212c7..1bcf39671c35 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -36,6 +36,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
@@ -499,6 +500,7 @@ static void __init overo_init(void)
                                  mt46h32m32lf6_sdrc_params);
        board_nand_init(overo_nand_partitions,
                        ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 386a2ddc1173..345e8c4b8731 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -18,6 +18,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/usb/phy.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -134,6 +135,7 @@ static void __init rm680_init(void)
        sdrc_params = nokia_get_sdram_timings();
        omap_sdrc_init(sdrc_params, sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        rm680_peripherals_init();
 }
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index cf07e289b4ea..f3d075baebb6 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -42,7 +42,7 @@
 #include <media/si4713.h>
 #include <linux/leds-lp5523.h>
-#include <../drivers/staging/iio/light/tsl2563.h>
+#include <linux/platform_data/tsl2563.h>
 #include <linux/lis3lv02d.h>
 #if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 46f4fc982766..eb667261df08 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -18,6 +18,7 @@
 #include <video/omapdss.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include "soc.h"
 #include "board-rx51.h"
 #include "mux.h"
@@ -85,5 +86,5 @@ static int __init rx51_video_init(void)
        return 0;
 }
-subsys_initcall(rx51_video_init);
+omap_subsys_initcall(rx51_video_init);
 #endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 26e07addc9d7..dc5498b1b3a7 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -20,6 +20,7 @@
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -298,6 +299,7 @@ void __init zoom_peripherals_init(void)
        omap_hsmmc_init(mmc);
        omap_i2c_init();
        platform_device_register(&omap_vwlan_device);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        enable_board_wakeup_source();
        omap_serial_init();
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 1ff646908627..b870f6a9e283 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -52,6 +52,6 @@ static int __init omap2xxx_clk_arch_init(void)
        return ret;
 }
-arch_initcall(omap2xxx_clk_arch_init);
+omap_arch_initcall(omap2xxx_clk_arch_init);
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 4eacab8f1176..0b02b4161d71 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -94,6 +94,6 @@ static int __init omap3xxx_clk_arch_init(void)
        return ret;
 }
-arch_initcall(omap3xxx_clk_arch_init);
+omap_arch_initcall(omap3xxx_clk_arch_init);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d8a0cc3b9d2c..142d9c616f1b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,6 +20,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
 #include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/usb/omap_control_usb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -67,7 +68,7 @@ static int __init omap3_l3_init(void)
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap3_l3_init);
+omap_postcore_initcall(omap3_l3_init);
 static int __init omap4_l3_init(void)
 {
@@ -101,7 +102,7 @@ static int __init omap4_l3_init(void)
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap4_l3_init);
+omap_postcore_initcall(omap4_l3_init);
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -252,6 +253,49 @@ static inline void omap_init_camera(void)
 #endif
 }
+#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
+static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
+        .type = 1,
+};
+struct resource omap4_control_usb_res[] = {
+        {
+                .name   = "control_dev_conf",
+                .start  = 0x4a002300,
+                .end    = 0x4a002303,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "otghs_control",
+                .start  = 0x4a00233c,
+                .end    = 0x4a00233f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device omap4_control_usb = {
+        .name = "omap-control-usb",
+        .id = -1,
+        .dev = {
+                .platform_data = &omap4_control_usb_pdata,
+        },
+        .num_resources = 2,
+        .resource = omap4_control_usb_res,
+};
+static inline void __init omap_init_control_usb(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+        if (platform_device_register(&omap4_control_usb))
+                pr_err("Error registering omap_control_usb device\n");
+}
+#else
+static inline void omap_init_control_usb(void) { }
+#endif /* CONFIG_OMAP_CONTROL_USB */
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                        *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
@@ -716,6 +760,7 @@ static int __init omap2_init_devices(void)
        omap_init_mbox();
        /* If dtb is there, the devices will be created dynamically */
        if (!of_have_populated_dt()) {
+                omap_init_control_usb();
                omap_init_dmic();
                omap_init_mcpdm();
                omap_init_mcspi();
@@ -729,4 +774,4 @@ static int __init omap2_init_devices(void)
        return 0;
 }
-arch_initcall(omap2_init_devices);
+omap_arch_initcall(omap2_init_devices);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 491c5c8837fa..dab9fc014b97 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -27,7 +27,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/dma-mapping.h>
 #include <linux/omap-dma.h>
 #include "soc.h"
@@ -288,9 +288,26 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        return 0;
 }
+static const struct platform_device_info omap_dma_dev_info = {
+        .name = "omap-dma-engine",
+        .id = -1,
+        .dma_mask = DMA_BIT_MASK(32),
+};
 static int __init omap2_system_dma_init(void)
 {
-        return omap_hwmod_for_each_by_class("dma",
+        struct platform_device *pdev;
+        int res;
+        res = omap_hwmod_for_each_by_class("dma",
                        omap2_system_dma_init_dev, NULL);
+        if (res)
+                return res;
+        pdev = platform_device_register_full(&omap_dma_dev_info);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+        return res;
 }
-arch_initcall(omap2_system_dma_init);
+omap_arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 4d8d1a52ffe7..59a4af779f42 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -62,6 +62,6 @@ static int __init omap_init_drm(void)
 }
-arch_initcall(omap_init_drm);
+omap_arch_initcall(omap_init_drm);
 #endif
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index b3566f68a559..cbeaca2d7695 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -47,4 +47,4 @@ static int __init emu_init(void)
        return 0;
 }
-subsys_initcall(emu_init);
+omap_subsys_initcall(emu_init);
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index d9bd965f6d07..190ae493c6ef 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -89,7 +89,7 @@ static int __init omap_init_vrfb(void)
                return 0;
 }
-arch_initcall(omap_init_vrfb);
+omap_arch_initcall(omap_init_vrfb);
 #endif
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@@ -113,6 +113,6 @@ static int __init omap_init_fb(void)
        return platform_device_register(&omap_fb_device);
 }
-arch_initcall(omap_init_fb);
+omap_arch_initcall(omap_init_fb);
 #endif
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 482ade1923b0..7a577145b68b 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/platform_data/gpio-omap.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "omap-pm.h"
@@ -146,7 +147,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 /*
 * gpio_init needs to be done before
 * machine_init functions access gpio APIs.
- * Hence gpio_init is a postcore_initcall.
+ * Hence gpio_init is a omap_postcore_initcall.
 */
 static int __init omap2_gpio_init(void)
 {
@@ -156,4 +157,4 @@ static int __init omap2_gpio_init(void)
        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
 }
-postcore_initcall(omap2_gpio_init);
+omap_postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index db969a5c4998..afc1e8c32d6c 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
        return 0;
 }
-static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
        /* support only OMAP3 class */
-        if (!cpu_is_omap34xx()) {
+        if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
                pr_err("BCH ecc is not supported on this CPU\n");
                return 0;
        }
        /*
-         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
+         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
-         * Other chips may be added if confirmed to work.
+         * and AM33xx derivates. Other chips may be added if confirmed to work.
         */
        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
+            (!soc_is_am33xx())) {
                pr_err("BCH 4-bit mode is not supported on this CPU\n");
                return 0;
        }
@@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
        return 1;
 }
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
+int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
-                          struct gpmc_timings *gpmc_t)
+                   struct gpmc_timings *gpmc_t)
 {
        int err = 0;
        struct device *dev = &gpmc_nand_device.dev;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 94a349e4dc96..fadd87435cd0 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
        return ret;
 }
-void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
+void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
        int err;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bc0783364ad3..8d70bd03c5d8 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -25,6 +25,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_mtd.h>
+#include <linux/of_device.h>
+#include <linux/mtd/nand.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
@@ -34,6 +38,8 @@
 #include "common.h"
 #include "omap_device.h"
 #include "gpmc.h"
+#include "gpmc-nand.h"
+#include "gpmc-onenand.h"
 #define DEVICE_NAME             "omap-gpmc"
@@ -145,7 +151,8 @@ static unsigned gpmc_irq_start;
 static struct resource  gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
+/* Define chip-selects as reserved by default until probe completes */
+static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -1118,8 +1125,215 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
        /* TODO: remove, see function definition */
        gpmc_convert_ps_to_ns(gpmc_t);
+        /* Now the GPMC is initialised, unreserve the chip-selects */
+        gpmc_cs_map = 0;
+        return 0;
+}
+#ifdef CONFIG_OF
+static struct of_device_id gpmc_dt_ids[] = {
+        { .compatible = "ti,omap2420-gpmc" },
+        { .compatible = "ti,omap2430-gpmc" },
+        { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
+        { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
+        { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
+        { }
+};
+MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
+static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
+                                                struct gpmc_timings *gpmc_t)
+{
+        u32 val;
+        memset(gpmc_t, 0, sizeof(*gpmc_t));
+        /* minimum clock period for syncronous mode */
+        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
+                gpmc_t->sync_clk = val;
+        /* chip select timtings */
+        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
+                gpmc_t->cs_on = val;
+        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
+                gpmc_t->cs_rd_off = val;
+        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
+                gpmc_t->cs_wr_off = val;
+        /* ADV signal timings */
+        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
+                gpmc_t->adv_on = val;
+        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
+                gpmc_t->adv_rd_off = val;
+        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
+                gpmc_t->adv_wr_off = val;
+        /* WE signal timings */
+        if (!of_property_read_u32(np, "gpmc,we-on", &val))
+                gpmc_t->we_on = val;
+        if (!of_property_read_u32(np, "gpmc,we-off", &val))
+                gpmc_t->we_off = val;
+        /* OE signal timings */
+        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
+                gpmc_t->oe_on = val;
+        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
+                gpmc_t->oe_off = val;
+        /* access and cycle timings */
+        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
+                gpmc_t->page_burst_access = val;
+        if (!of_property_read_u32(np, "gpmc,access", &val))
+                gpmc_t->access = val;
+        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
+                gpmc_t->rd_cycle = val;
+        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
+                gpmc_t->wr_cycle = val;
+        /* only for OMAP3430 */
+        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
+                gpmc_t->wr_access = val;
+        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
+                gpmc_t->wr_data_mux_bus = val;
+}
+#ifdef CONFIG_MTD_NAND
+static const char * const nand_ecc_opts[] = {
+        [OMAP_ECC_HAMMING_CODE_DEFAULT]         = "sw",
+        [OMAP_ECC_HAMMING_CODE_HW]              = "hw",
+        [OMAP_ECC_HAMMING_CODE_HW_ROMCODE]      = "hw-romcode",
+        [OMAP_ECC_BCH4_CODE_HW]                 = "bch4",
+        [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
+};
+static int gpmc_probe_nand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
+        u32 val;
+        const char *s;
+        struct gpmc_timings gpmc_t;
+        struct omap_nand_platform_data *gpmc_nand_data;
+        if (of_property_read_u32(child, "reg", &val) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+        gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
+                                      GFP_KERNEL);
+        if (!gpmc_nand_data)
+                return -ENOMEM;
+        gpmc_nand_data->cs = val;
+        gpmc_nand_data->of_node = child;
+        if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
+                for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
+                        if (!strcasecmp(s, nand_ecc_opts[val])) {
+                                gpmc_nand_data->ecc_opt = val;
+                                break;
+                        }
+        val = of_get_nand_bus_width(child);
+        if (val == 16)
+                gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_nand_init(gpmc_nand_data, &gpmc_t);
+        return 0;
+}
+#else
+static int gpmc_probe_nand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
        return 0;
 }
+#endif
+#ifdef CONFIG_MTD_ONENAND
+static int gpmc_probe_onenand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
+        u32 val;
+        struct omap_onenand_platform_data *gpmc_onenand_data;
+        if (of_property_read_u32(child, "reg", &val) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+        gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
+                                         GFP_KERNEL);
+        if (!gpmc_onenand_data)
+                return -ENOMEM;
+        gpmc_onenand_data->cs = val;
+        gpmc_onenand_data->of_node = child;
+        gpmc_onenand_data->dma_channel = -1;
+        if (!of_property_read_u32(child, "dma-channel", &val))
+                gpmc_onenand_data->dma_channel = val;
+        gpmc_onenand_init(gpmc_onenand_data);
+        return 0;
+}
+#else
+static int gpmc_probe_onenand_child(struct platform_device *pdev,
+                                    struct device_node *child)
+{
+        return 0;
+}
+#endif
+static int gpmc_probe_dt(struct platform_device *pdev)
+{
+        int ret;
+        struct device_node *child;
+        const struct of_device_id *of_id =
+                of_match_device(gpmc_dt_ids, &pdev->dev);
+        if (!of_id)
+                return 0;
+        for_each_node_by_name(child, "nand") {
+                ret = gpmc_probe_nand_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+        for_each_node_by_name(child, "onenand") {
+                ret = gpmc_probe_onenand_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+        return 0;
+}
+#else
+static int gpmc_probe_dt(struct platform_device *pdev)
+{
+        return 0;
+}
+#endif
 static int gpmc_probe(struct platform_device *pdev)
 {
@@ -1134,11 +1348,9 @@ static int gpmc_probe(struct platform_device *pdev)
        phys_base = res->start;
        mem_size = resource_size(res);
-        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
+        gpmc_base = devm_ioremap_resource(&pdev->dev, res);
-        if (!gpmc_base) {
+        if (IS_ERR(gpmc_base))
-                dev_err(&pdev->dev, "error: request memory / ioremap\n");
+                return PTR_ERR(gpmc_base);
-                return -EADDRNOTAVAIL;
-        }
        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
        if (res == NULL)
@@ -1174,6 +1386,14 @@ static int gpmc_probe(struct platform_device *pdev)
        if (IS_ERR_VALUE(gpmc_setup_irq()))
                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+        rc = gpmc_probe_dt(pdev);
+        if (rc < 0) {
+                clk_disable_unprepare(gpmc_l3_clk);
+                clk_put(gpmc_l3_clk);
+                dev_err(gpmc_dev, "failed to probe DT parameters\n");
+                return rc;
+        }
        return 0;
 }
@@ -1191,6 +1411,7 @@ static struct platform_driver gpmc_driver = {
        .driver         = {
                .name   = DEVICE_NAME,
                .owner  = THIS_MODULE,
+                .of_match_table = of_match_ptr(gpmc_dt_ids),
        },
 };
@@ -1205,7 +1426,7 @@ static __exit void gpmc_exit(void)
 }
-postcore_initcall(gpmc_init);
+omap_postcore_initcall(gpmc_init);
 module_exit(gpmc_exit);
 static int __init omap_gpmc_init(void)
@@ -1214,6 +1435,13 @@ static int __init omap_gpmc_init(void)
        struct platform_device *pdev;
        char *oh_name = "gpmc";
+        /*
+         * if the board boots up with a populated DT, do not
+         * manually add the device from this initcall
+         */
+        if (of_have_populated_dt())
+                return -ENODEV;
        oh = omap_hwmod_lookup(oh_name);
        if (!oh) {
                pr_err("Could not look up %s\n", oh_name);
@@ -1225,7 +1453,7 @@ static int __init omap_gpmc_init(void)
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap_gpmc_init);
+omap_postcore_initcall(omap_gpmc_init);
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index b7aa8ba2ccb2..cbc8e3c480e0 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -27,6 +27,7 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "hdq1w.h"
@@ -93,4 +94,4 @@ static int __init omap_init_hdq(void)
        return 0;
 }
-arch_initcall(omap_init_hdq);
+omap_arch_initcall(omap_init_hdq);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index c3688903f3d4..ef175acaeaa2 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/hwspinlock.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
@@ -56,4 +57,4 @@ static int __init hwspinlocks_init(void)
        return retval;
 }
 /* early board code might need to reserve specific hwspinlock instances */
-postcore_initcall(hwspinlocks_init);
+omap_postcore_initcall(hwspinlocks_init);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index c11a23fa9665..d940e53dd9f2 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -184,3 +184,8 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
        return PTR_RET(pdev);
 }
+static  int __init omap_i2c_cmdline(void)
+{
+        return omap_register_i2c_bus_cmdline();
+}
+omap_subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
index 70eda00db7a4..7ca1fcff453b 100644
--- a/arch/arm/mach-omap2/include/mach/serial.h
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -8,20 +8,6 @@
 * GNU General Public License for more details.
 */
-/*
- * Memory entry used for the DEBUG_LL UART configuration, relative to
- * start of RAM. See also uncompress.h and debug-macro.S.
- *
- * Note that using a memory location for storing the UART configuration
- * has at least two limitations:
- *
- * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
- *    uncompress code could then partially overwrite itself
- * 2. We assume printascii is called at least once before paging_init,
- *    and addruart has a chance to read OMAP_UART_INFO
- */
-#define OMAP_UART_INFO_OFS      0x3ffc
 /* OMAP2 serial ports */
 #define OMAP2_UART1_BASE        0x4806a000
 #define OMAP2_UART2_BASE        0x4806c000
@@ -68,29 +54,6 @@
 #define OMAP24XX_BASE_BAUD      (48000000/16)
-/*
- * DEBUG_LL port encoding stored into the UART1 scratchpad register by
- * decomp_setup in uncompress.h
- */
-#define OMAP2UART1              21
-#define OMAP2UART2              22
-#define OMAP2UART3              23
-#define OMAP3UART1              OMAP2UART1
-#define OMAP3UART2              OMAP2UART2
-#define OMAP3UART3              33
-#define OMAP3UART4              34              /* Only on 36xx */
-#define OMAP4UART1              OMAP2UART1
-#define OMAP4UART2              OMAP2UART2
-#define OMAP4UART3              43
-#define OMAP4UART4              44
-#define TI81XXUART1             81
-#define TI81XXUART2             82
-#define TI81XXUART3             83
-#define AM33XXUART1             84
-#define OMAP5UART3              OMAP4UART3
-#define OMAP5UART4              OMAP4UART4
-#define ZOOM_UART               95              /* Only on zoom2/3 */
 #ifndef __ASSEMBLER__
 struct omap_board_data;
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
deleted file mode 100644
index 8e3546d3e041..000000000000
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/serial.h>
-#define MDR1_MODE_MASK                  0x07
-volatile u8 *uart_base;
-int uart_shift;
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
-        /*
-         * Get address of some.bss variable and round it down
-         * a la CONFIG_AUTO_ZRELADDR.
-         */
-        u32 ram_start = (u32)&uart_shift & 0xf8000000;
-        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
-        *uart_info = port;
-}
-static void putc(int c)
-{
-        if (!uart_base)
-                return;
-        /* Check for UART 16x mode */
-        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
-                return;
-        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
-                barrier();
-        uart_base[UART_TX << uart_shift] = c;
-}
-static inline void flush(void)
-{
-}
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
-        if (machine_is_##mach()) {                                      \
-                uart_base = (volatile u8 *)(dbg_uart);                  \
-                uart_shift = (dbg_shft);                                \
-                port = (dbg_id);                                        \
-                set_omap_uart_info(port);                               \
-                break;                                                  \
-        }
-#define DEBUG_LL_OMAP2(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP2UART##p)
-#define DEBUG_LL_OMAP3(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP3UART##p)
-#define DEBUG_LL_OMAP4(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP4UART##p)
-#define DEBUG_LL_OMAP5(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP5UART##p)
-/* Zoom2/3 shift is different for UART1 and external port */
-#define DEBUG_LL_ZOOM(mach)                                             \
-        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI81XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI81XXUART##p)
-#define DEBUG_LL_AM33XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                AM33XXUART##p)
-static inline void arch_decomp_setup(void)
-{
-        int port = 0;
-        /*
-         * Initialize the port based on the machine ID from the bootloader.
-         * Note that we're using macros here instead of switch statement
-         * as machine_is functions are optimized out for the boards that
-         * are not selected.
-         */
-        do {
-                /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap_2430sdp);
-                DEBUG_LL_OMAP2(1, omap_apollon);
-                DEBUG_LL_OMAP2(1, omap_h4);
-                /* omap2 based boards using UART3 */
-                DEBUG_LL_OMAP2(3, nokia_n800);
-                DEBUG_LL_OMAP2(3, nokia_n810);
-                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
-                /* omap3 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap3evm);
-                DEBUG_LL_OMAP3(1, omap_3430sdp);
-                DEBUG_LL_OMAP3(1, omap_3630sdp);
-                DEBUG_LL_OMAP3(1, omap3530_lv_som);
-                DEBUG_LL_OMAP3(1, omap3_torpedo);
-                /* omap3 based boards using UART3 */
-                DEBUG_LL_OMAP3(3, cm_t35);
-                DEBUG_LL_OMAP3(3, cm_t3517);
-                DEBUG_LL_OMAP3(3, cm_t3730);
-                DEBUG_LL_OMAP3(3, craneboard);
-                DEBUG_LL_OMAP3(3, devkit8000);
-                DEBUG_LL_OMAP3(3, igep0020);
-                DEBUG_LL_OMAP3(3, igep0030);
-                DEBUG_LL_OMAP3(3, nokia_rm680);
-                DEBUG_LL_OMAP3(3, nokia_rm696);
-                DEBUG_LL_OMAP3(3, nokia_rx51);
-                DEBUG_LL_OMAP3(3, omap3517evm);
-                DEBUG_LL_OMAP3(3, omap3_beagle);
-                DEBUG_LL_OMAP3(3, omap3_pandora);
-                DEBUG_LL_OMAP3(3, omap_ldp);
-                DEBUG_LL_OMAP3(3, overo);
-                DEBUG_LL_OMAP3(3, touchbook);
-                /* omap4 based boards using UART3 */
-                DEBUG_LL_OMAP4(3, omap_4430sdp);
-                DEBUG_LL_OMAP4(3, omap4_panda);
-                /* omap5 based boards using UART3 */
-                DEBUG_LL_OMAP5(3, omap5_sevm);
-                /* zoom2/3 external uart */
-                DEBUG_LL_ZOOM(omap_zoom2);
-                DEBUG_LL_ZOOM(omap_zoom3);
-                /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI81XX(3, ti8168evm);
-                /* TI8148 base boards using UART1 */
-                DEBUG_LL_TI81XX(1, ti8148evm);
-                /* AM33XX base boards using UART1 */
-                DEBUG_LL_AM33XX(1, am335xevm);
-        } while (0);
-}
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 453580410ae0..5d8768075dd9 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -23,6 +23,7 @@
 #include <linux/omap-dma.h>
+#include "soc.h"
 #include "omap_device.h"
 /*
@@ -118,4 +119,4 @@ static int __init omap2_mcbsp_init(void)
        return 0;
 }
-arch_initcall(omap2_mcbsp_init);
+omap_arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index f7f38c7fd5ff..f6daae821ebb 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/platform_data/iommu-omap.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
@@ -60,7 +61,7 @@ static int __init omap_iommu_init(void)
        return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
 }
 /* must be ready before omap3isp is probed */
-subsys_initcall(omap_iommu_init);
+omap_subsys_initcall(omap_iommu_init);
 static void __exit omap_iommu_exit(void)
 {
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 8c5b5e3e3541..f8bb3b9b6a76 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -45,7 +45,7 @@
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
-static DEFINE_SPINLOCK(wakeupgen_lock);
+static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[MAX_IRQS];
 static unsigned int irq_banks = MAX_NR_REG_BANKS;
 static unsigned int max_irqs = MAX_IRQS;
@@ -133,9 +133,9 @@ static void wakeupgen_mask(struct irq_data *d)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 /*
@@ -145,9 +145,9 @@ static void wakeupgen_unmask(struct irq_data *d)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 #ifdef CONFIG_HOTPLUG_CPU
@@ -188,7 +188,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        if (set) {
                _wakeupgen_save_masks(cpu);
                _wakeupgen_set_all(cpu, WKG_MASK_ALL);
@@ -196,7 +196,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
                _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
                _wakeupgen_restore_masks(cpu);
        }
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index be6bc89ab1e8..719b716a4494 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -13,6 +13,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
+#include "soc.h"
 #include "common.h"
 #include "prm2xxx.h"
@@ -62,4 +63,4 @@ static int __init omap2xxx_common_look_up_clks_for_reset(void)
        return 0;
 }
-core_initcall(omap2xxx_common_look_up_clks_for_reset);
+omap_core_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 547094883606..708bb115a27f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -226,7 +226,7 @@ static int __init omap_l2_cache_init(void)
        return 0;
 }
-early_initcall(omap_l2_cache_init);
+omap_early_initcall(omap_l2_cache_init);
 #endif
 void __iomem *omap4_get_sar_ram_base(void)
@@ -254,7 +254,7 @@ static int __init omap4_sar_ram_init(void)
        return 0;
 }
-early_initcall(omap4_sar_ram_init);
+omap_early_initcall(omap4_sar_ram_init);
 void __init omap_gic_of_init(void)
 {
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 6ee3ad3dd95a..381be7ac0c17 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -36,6 +36,7 @@
 #include <linux/of.h>
 #include <linux/notifier.h>
+#include "soc.h"
 #include "omap_device.h"
 #include "omap_hwmod.h"
@@ -840,7 +841,7 @@ static int __init omap_device_init(void)
        bus_register_notifier(&platform_bus_type, &platform_nb);
        return 0;
 }
-core_initcall(omap_device_init);
+omap_core_initcall(omap_device_init);
 /**
 * omap_device_late_idle - idle devices without drivers
@@ -878,4 +879,4 @@ static int __init omap_device_late_init(void)
        bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
        return 0;
 }
-late_initcall(omap_device_late_init);
+omap_late_initcall(omap_device_late_init);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6804d474a47d..a8984989dec8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3311,7 +3311,7 @@ static int __init omap_hwmod_setup_all(void)
        return 0;
 }
-core_initcall(omap_hwmod_setup_all);
+omap_core_initcall(omap_hwmod_setup_all);
 /**
 * omap_hwmod_enable - enable an omap_hwmod
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index a1849a883702..7ec1083ff604 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2702,13 +2702,6 @@ static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
                .end            = 0x4a0ae000,
                .flags          = IORESOURCE_MEM,
        },
-        {
-                /* XXX: Remove this once control module driver is in place */
-                .name           = "ctrl_dev",
-                .start          = 0x4a002300,
-                .end            = 0x4a002303,
-                .flags          = IORESOURCE_MEM,
-        },
        { }
 };
@@ -6155,12 +6148,6 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
                .pa_end         = 0x4a0ab7ff,
                .flags          = ADDR_TYPE_RT
        },
-        {
-                /* XXX: Remove this once control module driver is in place */
-                .pa_start       = 0x4a00233c,
-                .pa_end         = 0x4a00233f,
-                .flags          = ADDR_TYPE_RT
-        },
        { }
 };
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index e237602e10ea..eb8a25de67ed 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -63,7 +63,7 @@ static int __init omap4430_phy_power_down(void)
        return 0;
 }
-early_initcall(omap4430_phy_power_down);
+omap_early_initcall(omap4430_phy_power_down);
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 62772e0e0d69..fc67add76444 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -168,4 +168,4 @@ int __init omap3_opp_init(void)
        return r;
 }
-device_initcall(omap3_opp_init);
+omap_device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d470b728e720..1ef7a3e5ce4a 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -177,4 +177,4 @@ int __init omap4_opp_init(void)
                        ARRAY_SIZE(omap446x_opp_def_list));
        return r;
 }
-device_initcall(omap4_opp_init);
+omap_device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 6db89ae92389..1edd000a8143 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -277,6 +277,6 @@ static int __init pm_dbg_init(void)
        return 0;
 }
-arch_initcall(pm_dbg_init);
+omap_arch_initcall(pm_dbg_init);
 #endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9a9be3c9f208..cd6682df5625 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -273,7 +273,7 @@ static int __init omap2_common_pm_init(void)
        return 0;
 }
-postcore_initcall(omap2_common_pm_init);
+omap_postcore_initcall(omap2_common_pm_init);
 int __init omap2_common_pm_late_init(void)
 {
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7be3622cfc85..2d93d8b23835 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -351,12 +351,10 @@ static void omap3_pm_idle(void)
        if (omap_irq_pending())
                goto out;
-        trace_power_start(POWER_CSTATE, 1, smp_processor_id());
        trace_cpu_idle(1, smp_processor_id());
        omap_sram_idle();
-        trace_power_end(smp_processor_id());
        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 out:
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 0ef4d6aa758e..9debf822687c 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -88,4 +88,4 @@ static int __init omap_init_pmu(void)
        return omap2_init_pmu(oh_num, oh_names);
 }
-subsys_initcall(omap_init_pmu);
+omap_subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index e648bd55b072..7721990d2006 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -427,7 +427,7 @@ static int __init omap3xxx_prm_late_init(void)
        return ret;
 }
-subsys_initcall(omap3xxx_prm_late_init);
+omap_subsys_initcall(omap3xxx_prm_late_init);
 static void __exit omap3xxx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index c05a343d465d..d35f98aabf7a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -665,7 +665,7 @@ static int __init omap44xx_prm_late_init(void)
        return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 }
-subsys_initcall(omap44xx_prm_late_init);
+omap_subsys_initcall(omap44xx_prm_late_init);
 static void __exit omap44xx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index d01c373cbbef..8396b5b7e912 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -254,7 +254,7 @@ static int __init omap_serial_early_init(void)
        return 0;
 }
-core_initcall(omap_serial_early_init);
+omap_core_initcall(omap_serial_early_init);
 /**
 * omap_serial_init_port() - initialize single serial port
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 1da8f03c479e..aee3c8940a30 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -12,6 +12,7 @@
 */
 #include <linux/power/smartreflex.h>
+#include "soc.h"
 #include "voltage.h"
 static int sr_class3_enable(struct omap_sr *sr)
@@ -58,4 +59,4 @@ static int __init sr_class3_init(void)
        pr_info("SmartReflex Class3 initialized\n");
        return sr_register_class(&class3_data);
 }
-late_initcall(sr_class3_init);
+omap_late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index f31d90774de0..092aedd7ed13 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -42,6 +42,9 @@
 #undef MULTI_OMAP2
 #undef OMAP_NAME
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define MULTI_OMAP2
+#endif
 #ifdef CONFIG_SOC_OMAP2420
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
@@ -112,6 +115,11 @@ int omap_type(void);
 */
 unsigned int omap_rev(void);
+static inline int soc_is_omap(void)
+{
+        return omap_rev() != 0;
+}
 /*
 * Get the CPU revision for OMAP devices
 */
@@ -465,5 +473,26 @@ static inline unsigned int omap4_has_ ##feat(void)	\
 OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
+/*
+ * We need to make sure omap initcalls don't run when
+ * multiplatform kernels are booted on other SoCs.
+ */
+#define omap_initcall(level, fn)                \
+static int __init __used __##fn(void)           \
+{                                               \
+        if (!soc_is_omap())                     \
+                return 0;                       \
+        return fn();                            \
+}                                               \
+level(__##fn);
+#define omap_early_initcall(fn)         omap_initcall(early_initcall, fn)
+#define omap_core_initcall(fn)          omap_initcall(core_initcall, fn)
+#define omap_postcore_initcall(fn)      omap_initcall(postcore_initcall, fn)
+#define omap_arch_initcall(fn)          omap_initcall(arch_initcall, fn)
+#define omap_subsys_initcall(fn)        omap_initcall(subsys_initcall, fn)
+#define omap_device_initcall(fn)        omap_initcall(device_initcall, fn)
+#define omap_late_initcall(fn)          omap_initcall(late_initcall, fn)
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6d1f7b187d7c..2bdd4cf17a8f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -227,7 +227,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        int r = 0;
        if (of_have_populated_dt()) {
-                np = omap_get_timer_dt(omap_timer_match, NULL);
+                np = omap_get_timer_dt(omap_timer_match, property);
                if (!np)
                        return -ENODEV;
@@ -718,7 +718,7 @@ static int __init omap2_dm_timer_init(void)
        return 0;
 }
-arch_initcall(omap2_dm_timer_init);
+omap_arch_initcall(omap2_dm_timer_init);
 /**
 * omap2_override_clocksource - clocksource override with user configuration
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index e49b40b4c90a..6a7aec6d1174 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -23,6 +23,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/gpio.h>
+#include <linux/string.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -56,7 +57,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
                           struct twl4030_platform_data *pmic_data)
 {
        omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-        strncpy(pmic_i2c_board_info.type, pmic_type,
+        strlcpy(pmic_i2c_board_info.type, pmic_type,
                sizeof(pmic_i2c_board_info.type));
        pmic_i2c_board_info.irq = pmic_irq;
        pmic_i2c_board_info.platform_data = pmic_data;
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 8c4de2708cf2..3242a554ad6b 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,6 +85,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
        musb_plat.mode = board_data->mode;
        musb_plat.extvbus = board_data->extvbus;
+        if (cpu_is_omap44xx())
+                musb_plat.has_mailbox = true;
        if (soc_is_am35xx()) {
                oh_name = "am35x_otg_hs";
                name = "musb-am35x";
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 910243f54a05..d15c7bbab8e2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -129,4 +129,4 @@ static int __init omap_init_wdt(void)
             dev_name, oh->name);
        return 0;
 }
-subsys_initcall(omap_init_wdt);
+omap_subsys_initcall(omap_init_wdt);
diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h
index 4322dba468a4..abd26b542c3c 100644
--- a/arch/arm/mach-orion5x/include/mach/uncompress.h
+++ b/arch/arm/mach-orion5x/include/mach/uncompress.h
@@ -46,4 +46,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 868796f8085c..13bae78b215a 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -7,7 +7,6 @@ config ARCH_PICOXCELL
        select DW_APB_TIMER
        select DW_APB_TIMER_OF
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_TCM
        select NO_IOPORT
        select SPARSE_IRQ
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 15f3edcfbb47..d1513a33709a 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -17,8 +17,6 @@ void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog()
 static __inline__ void putc(char c)
 {
        /*
diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h
index 2d3f14e3be29..714b6574393e 100644
--- a/arch/arm/mach-pxa/include/mach/palmtreo.h
+++ b/arch/arm/mach-pxa/include/mach/palmtreo.h
@@ -38,13 +38,14 @@
 #define GPIO_NR_TREO_LCD_POWER  25
 /* Treo680 specific GPIOs */
-#ifdef CONFIG_MACH_TREO680
 #define GPIO_NR_TREO680_SD_READONLY     33
 #define GPIO_NR_TREO680_SD_POWER        42
 #define GPIO_NR_TREO680_VIBRATE_EN      44
 #define GPIO_NR_TREO680_KEYB_BL         24
 #define GPIO_NR_TREO680_BT_EN           43
-#endif /* CONFIG_MACH_TREO680 */
+#define GPIO_NR_TREO680_LCD_POWER       77
+#define GPIO_NR_TREO680_LCD_EN          86
+#define GPIO_NR_TREO680_LCD_EN_N        25
 /* Centro685 specific GPIOs */
 #define GPIO_NR_CENTRO_SD_POWER         21
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
index b7de471b273a..b802f285fe00 100644
--- a/arch/arm/mach-pxa/include/mach/smemc.h
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -37,6 +37,7 @@
 #define CSADRCFG1       (SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
 #define CSADRCFG2       (SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
 #define CSADRCFG3       (SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
+#define CSMSADRCFG      (SMEMC_VIRT + 0xA0)  /* Chip Select Configuration Register */
 /*
 * More handy macros for PCMCIA
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 5519a34b667f..8c27757e68ff 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -72,8 +72,3 @@ static inline void arch_decomp_setup(void)
                uart_is_pxa = 0;
        }
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d17bda278782..a29849d181c8 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -98,9 +98,6 @@ static unsigned long treo_pin_config[] __initdata = {
        GPIO96_KP_MKOUT_6,
        GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,        /* Hotsync button */
-        /* LCD */
-        GPIOxx_LCD_TFT_16BPP,
        /* Quick Capture Interface */
        GPIO84_CIF_FV,
        GPIO85_CIF_LV,
@@ -140,6 +137,12 @@ static unsigned long treo680_pin_config[] __initdata = {
        /* MATRIX KEYPAD - different wake up source */
        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
        GPIO99_KP_MKIN_5,
+        /* LCD... L_BIAS alt fn not configured on Treo680; is GPIO instead */
+        GPIOxx_LCD_16BPP,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
 };
 #endif /* CONFIG_MACH_TREO680 */
@@ -155,6 +158,9 @@ static unsigned long centro685_pin_config[] __initdata = {
        /* MATRIX KEYPAD - different wake up source */
        GPIO100_KP_MKIN_0,
        GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+        /* LCD */
+        GPIOxx_LCD_TFT_16BPP,
 };
 #endif /* CONFIG_MACH_CENTRO */
@@ -328,7 +334,6 @@ static inline void palmtreo_uhc_init(void) {}
 /******************************************************************************
 * Vibra and LEDs
 ******************************************************************************/
-#ifdef CONFIG_MACH_TREO680
 static struct gpio_led treo680_gpio_leds[] = {
        {
                .name                   = "treo680:vibra:vibra",
@@ -379,21 +384,17 @@ static struct gpio_led_platform_data centro_gpio_led_info = {
 static struct platform_device palmtreo_leds = {
        .name   = "leds-gpio",
        .id     = -1,
-        .dev    = {
-                .platform_data  = &treo680_gpio_led_info,
-        }
 };
 static void __init palmtreo_leds_init(void)
 {
        if (machine_is_centro())
                palmtreo_leds.dev.platform_data = &centro_gpio_led_info;
+        else if (machine_is_treo680())
+                palmtreo_leds.dev.platform_data = &treo680_gpio_led_info;
        platform_device_register(&palmtreo_leds);
 }
-#else
-static inline void palmtreo_leds_init(void) {}
-#endif
 /******************************************************************************
 * Machine init
@@ -424,10 +425,59 @@ static void __init palmphone_common_init(void)
 }
 #ifdef CONFIG_MACH_TREO680
+void __init treo680_gpio_init(void)
+{
+        unsigned int gpio;
+        /* drive all three lcd gpios high initially */
+        const unsigned long lcd_flags = GPIOF_INIT_HIGH | GPIOF_DIR_OUT;
+        /*
+         * LCD GPIO initialization...
+         */
+        /*
+         * This is likely the power to the lcd.  Toggling it low/high appears to
+         * turn the lcd off/on.  Can be toggled after lcd is initialized without
+         * any apparent adverse effects to the lcd operation.  Note that this
+         * gpio line is used by the lcd controller as the L_BIAS signal, but
+         * treo680 configures it as gpio.
+         */
+        gpio = GPIO_NR_TREO680_LCD_POWER;
+        if (gpio_request_one(gpio, lcd_flags, "LCD power") < 0)
+                goto fail;
+        /*
+         * These two are called "enables", for lack of a better understanding.
+         * If either of these are toggled after the lcd is initialized, the
+         * image becomes degraded.  N.B. The IPL shipped with the treo
+         * configures GPIO_NR_TREO680_LCD_EN_N as output and drives it high.  If
+         * the IPL is ever reprogrammed, this initialization may be need to be
+         * revisited.
+         */
+        gpio = GPIO_NR_TREO680_LCD_EN;
+        if (gpio_request_one(gpio, lcd_flags, "LCD enable") < 0)
+                goto fail;
+        gpio = GPIO_NR_TREO680_LCD_EN_N;
+        if (gpio_request_one(gpio, lcd_flags, "LCD enable_n") < 0)
+                goto fail;
+        /* driving this low turns LCD on */
+        gpio_set_value(GPIO_NR_TREO680_LCD_EN_N, 0);
+        return;
+ fail:
+        pr_err("gpio %d initialization failed\n", gpio);
+        gpio_free(GPIO_NR_TREO680_LCD_POWER);
+        gpio_free(GPIO_NR_TREO680_LCD_EN);
+        gpio_free(GPIO_NR_TREO680_LCD_EN_N);
+}
 static void __init treo680_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
        palmphone_common_init();
+        treo680_gpio_init();
        palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
                        GPIO_NR_TREO680_SD_POWER, 0);
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 616cb87b6179..69985b06c0da 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -53,17 +53,25 @@ static unsigned long ac97_reset_config[] = {
        GPIO95_AC97_nRESET,
 };
-void pxa27x_assert_ac97reset(int reset_gpio, int on)
+void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
 {
+        /*
+         * This helper function is used to work around a bug in the pxa27x's
+         * ac97 controller during a warm reset.  The configuration of the
+         * reset_gpio is changed as follows:
+         * to_gpio == true: configured to generic output gpio and driven high
+         * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
+         */
        if (reset_gpio == 113)
-                pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
+                pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
-                                       &ac97_reset_config[1], 1);
+                                  &ac97_reset_config[1], 1);
        if (reset_gpio == 95)
-                pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
+                pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
-                                       &ac97_reset_config[3], 1);
+                                  &ac97_reset_config[3], 1);
 }
-EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
+EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
 /* Crystal clock: 13MHz */
 #define BASE_CLK        13000000
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index 79923058d10f..f38aa890b2c9 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void)
        __raw_writel(csadrcfg[1], CSADRCFG1);
        __raw_writel(csadrcfg[2], CSADRCFG2);
        __raw_writel(csadrcfg[3], CSADRCFG3);
+        /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
+        __raw_writel(0x2, CSMSADRCFG);
 }
 static struct syscore_ops smemc_syscore_ops = {
@@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = {
 static int __init smemc_init(void)
 {
-        if (cpu_is_pxa3xx())
+        if (cpu_is_pxa3xx()) {
+                /*
+                 * The only documentation we have on the
+                 * Chip Select Configuration Register (CSMSADRCFG) is that
+                 * it must be programmed to 0x2.
+                 * Moreover, in the bit definitions, the second bit
+                 * (CSMSADRCFG[1]) is called "SETALWAYS".
+                 * Other bits are reserved in this register.
+                 */
+                __raw_writel(0x2, CSMSADRCFG);
                register_syscore_ops(&smemc_syscore_ops);
+        }
        return 0;
 }
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index f90aa27ad599..362726c49c70 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -732,7 +732,7 @@ static inline void spitz_lcd_init(void) {}
 #endif
 /******************************************************************************
- * Framebuffer
+ * NAND Flash
 ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
 static struct mtd_partition spitz_nand_partitions[] = {
@@ -858,7 +858,7 @@ static inline void spitz_nor_init(void) {}
 #endif
 /******************************************************************************
- * GPIO expander
+ * I2C devices
 ******************************************************************************/
 #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
 static struct pca953x_platform_data akita_pca953x_pdata = {
diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h
index 83050378ffd2..cfa30d21783b 100644
--- a/arch/arm/mach-realview/include/mach/uncompress.h
+++ b/arch/arm/mach-realview/include/mach/uncompress.h
@@ -75,4 +75,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 9cd9bcdad6cc..0fd4b0b8ef22 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -189,8 +189,3 @@ static void arch_decomp_setup(void)
        if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
 }
 #endif
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
deleted file mode 100644
index 68d89cb96af0..000000000000
--- a/arch/arm/mach-s3c2410/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-# cpu frequency scaling support
-config S3C2410_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2410
-config S3C2410_PLLTABLE
-        bool
-        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
-        default y
-        help
-          Select the PLL table for the S3C2410
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
deleted file mode 100644
index 6b9a316e0041..000000000000
--- a/arch/arm/mach-s3c2410/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# arch/arm/mach-s3c2410/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
-obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
deleted file mode 100644
index 495f6928cbaa..000000000000
--- a/arch/arm/mach-s3c2412/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-# Note, the S3C2412 IOtiming support is in plat-s3c24xx
-config S3C2412_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
-        default y
-        select S3C2412_IOTIMING
-        help
-          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
deleted file mode 100644
index 41a6c279fb2f..000000000000
--- a/arch/arm/mach-s3c2412/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# arch/arm/mach-s3c2412/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
deleted file mode 100644
index 4526f6ba31a8..000000000000
--- a/arch/arm/mach-s3c2412/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/gpio.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * http://armlinux.simtec.co.uk/.
- *
- * S3C2412/S3C2413 specific GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/hardware.h>
-#include <plat/gpio-core.h>
-int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-        unsigned long flags;
-        unsigned long slpcon;
-        offs *= 2;
-        if (pin < S3C2410_GPB(0))
-                return -EINVAL;
-        if (pin >= S3C2410_GPF(0) &&
-            pin <= S3C2410_GPG(16))
-                return -EINVAL;
-        if (pin > S3C2410_GPH(16))
-                return -EINVAL;
-        local_irq_save(flags);
-        slpcon = __raw_readl(chip->base + 0x0C);
-        slpcon &= ~(3 << offs);
-        slpcon |= state << offs;
-        __raw_writel(slpcon, chip->base + 0x0C);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
deleted file mode 100644
index a4d7fd27bec5..000000000000
--- a/arch/arm/mach-s3c2440/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-config S3C2440_CPUFREQ
-        bool "S3C2440/S3C2442 CPU Frequency scaling support"
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
-        default y
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
-config S3C2440_XTAL_12000000
-        bool
-        help
-          Indicate that the build needs to support 12MHz system
-          crystal.
-config S3C2440_XTAL_16934400
-        bool
-        help
-          Indicate that the build needs to support 16.9344MHz system
-          crystal.
-config S3C2440_PLL_12000000
-        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
-        default y if CPU_FREQ_S3C24XX_PLL
-        help
-          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
-config S3C2440_PLL_16934400
-        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
-        default y if CPU_FREQ_S3C24XX_PLL
-        help
-          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
deleted file mode 100644
index c46092439814..000000000000
--- a/arch/arm/mach-s3c2440/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# arch/arm/mach-s3c2440/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_CPU_S3C2440)       += dsc.o
-obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
-obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
-obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
deleted file mode 100644
index 9ea66e31f626..000000000000
--- a/arch/arm/mach-s3c2440/dsc.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/dsc.c
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C2440 Drive Strength Control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
-#include <plat/cpu.h>
-#include <plat/s3c244x.h>
-int s3c2440_set_dsc(unsigned int pin, unsigned int value)
-{
-        void __iomem *base;
-        unsigned long val;
-        unsigned long flags;
-        unsigned long mask;
-        base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
-        mask = 3 << S3C2440_DSC_GETSHIFT(pin);
-        local_irq_save(flags);
-        val = __raw_readl(base);
-        val &= ~mask;
-        val |= value & mask;
-        __raw_writel(val, base);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2440_set_dsc);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 25df14a9e268..37f513d1588e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -9,6 +9,15 @@
 if ARCH_S3C24XX
+config PLAT_S3C24XX
+        def_bool y
+        select ARCH_REQUIRE_GPIOLIB
+        select NO_IOPORT
+        select S3C_DEV_NAND
+        select IRQ_DOMAIN
+        help
+          Base platform code for any Samsung S3C24XX device
 menu "SAMSUNG S3C24XX SoCs Support"
 comment "S3C24XX SoCs"
@@ -83,6 +92,17 @@ config CPU_S3C2443
 # common code
+config S3C2410_CLOCK
+        bool
+        help
+          Clock code for the S3C2410, and similar processors which
+          is currently includes the S3C2410, S3C2440, S3C2442.
+config S3C24XX_DCLK
+        bool
+        help
+          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
 config S3C24XX_SMDK
        bool
        help
@@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
        help
          Compile in platform device definition for Samsung TouchScreen.
+config S3C24XX_DMA
+        bool "S3C2410 DMA support"
+        depends on ARCH_S3C24XX
+        select S3C_DMA
+        help
+          S3C2410 DMA support. This is needed for drivers like sound which
+          use the S3C2410's DMA system to move data to and from the
+          peripheral blocks.
+config S3C2410_DMA_DEBUG
+        bool "S3C2410 DMA support debug"
+        depends on ARCH_S3C24XX && S3C2410_DMA
+        help
+          Enable debugging output for the DMA code. This option sends info
+          to the kernel log, at priority KERN_DEBUG.
 config S3C2410_DMA
        bool
        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -123,10 +159,92 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
+# low-level serial option nodes
+config CPU_LLSERIAL_S3C2410_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
+config CPU_LLSERIAL_S3C2440_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
+config CPU_LLSERIAL_S3C2410
+        bool
+        help
+          Selected if there is an S3C2410 (or register compatible) serial
+          low-level implementation needed
+config CPU_LLSERIAL_S3C2440
+        bool
+        help
+          Selected if there is an S3C2440 (or register compatible) serial
+          low-level implementation needed
+# gpio configurations
+config S3C24XX_GPIO_EXTRA
+        int
+        default 128 if S3C24XX_GPIO_EXTRA128
+        default 64 if S3C24XX_GPIO_EXTRA64
+        default 16 if ARCH_H1940
+        default 0
+config S3C24XX_GPIO_EXTRA64
+        bool
+        help
+          Add an extra 64 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+config S3C24XX_GPIO_EXTRA128
+        bool
+        help
+          Add an extra 128 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+# cpu frequency items common between s3c2410 and s3c2440/s3c2442
+config S3C2410_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select io timing code that is common to the s3c2410
+          and s3c2440/s3c2442 cpu frequency support.
+config S3C2410_CPUFREQ_UTILS
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select timing code that is common to the s3c2410
+          and s3c2440/s3c244 cpu frequency support.
+# cpu frequency support common to s3c2412, s3c2413 and s3c2442
+config S3C2412_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        help
+          Intel node to select io timing code that is common to the s3c2412
+          and the s3c2443.
 # cpu-specific sections
 if CPU_S3C2410
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+config S3C2410_PLL
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
 config S3C24XX_SIMTEC_NOR
        bool
        help
@@ -226,6 +344,7 @@ config MACH_QT2410
 config ARCH_SMDK2410
        bool "SMDK2410/A9M2410"
        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the SMDK2410 or the derived module A9M2410
          <http://www.fsforth.de>
@@ -266,6 +385,14 @@ config CPU_S3C2412_ONLY
                   !CPU_S3C2443 && CPU_S3C2412
        default y
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        default y
+        select S3C2412_IOTIMING
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
 config S3C2412_DMA
        bool
        help
@@ -273,6 +400,7 @@ config S3C2412_DMA
 config S3C2412_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2412 power management
@@ -291,8 +419,8 @@ config MACH_JIVE
          Say Y here if you are using the Logitech Jive.
 config MACH_JIVE_SHOW_BOOTLOADER
-        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
+        bool "Allow access to bootloader partitions in MTD"
-        depends on MACH_JIVE && EXPERIMENTAL
+        depends on MACH_JIVE
 config MACH_S3C2413
        bool
@@ -365,11 +493,45 @@ endif	# CPU_S3C2416
 if CPU_S3C2440
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        default y
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
 config S3C2440_DMA
        bool
        help
          Support for S3C2440 specific DMA code5A
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
 comment "S3C2440 Boards"
 #
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 0ab6ab15da4c..af53d27d5c36 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,26 +14,32 @@ obj-				:=
 # core
-obj-y                           += common.o
+obj-y                           += common.o irq.o
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o irq-s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o clock-s3c2443.o
 # PM
@@ -41,9 +47,21 @@ obj-$(CONFIG_PM)		+= pm.o irq-pm.o sleep.o
 # common code
+obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
+obj-$(CONFIG_S3C24XX_DMA)       += dma.o
+obj-$(CONFIG_S3C2410_CLOCK)     += clock-s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
+obj-$(CONFIG_S3C2410_IOTIMING)  += iotiming-s3c2410.o
+obj-$(CONFIG_S3C2412_IOTIMING)  += iotiming-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpufreq.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
 #
 # machine support
 # following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c24xx/anubis.h
new file mode 100644
index 000000000000..2691665f27d9
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/anubis.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ * ANUBIS - IRQ Number definitions
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_ANUBIS_H
+#define __MACH_S3C24XX_ANUBIS_H __FILE__
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+/* IDREG - revision */
+#define ANUBIS_IDREG_REVMASK            (0x7)
+/* irq */
+#define ANUBIS_IRQ_IDE0                 IRQ_EINT2
+#define ANUBIS_IRQ_IDE1                 IRQ_EINT3
+#define ANUBIS_IRQ_ASIX                 IRQ_EINT1
+/* map */
+/* start peripherals off after the S3C2410 */
+#define ANUBIS_IOADDR(x)                (S3C2410_ADDR((x) + 0x01800000))
+#define ANUBIS_PA_CPLD                  (S3C2410_CS1 | (1<<26))
+/* we put the CPLD registers next, to get them out of the way */
+#define ANUBIS_VA_CTRL1                 ANUBIS_IOADDR(0x00000000)
+#define ANUBIS_PA_CTRL1                 ANUBIS_PA_CPLD
+#define ANUBIS_VA_IDREG                 ANUBIS_IOADDR(0x00300000)
+#define ANUBIS_PA_IDREG                 (ANUBIS_PA_CPLD + (3 << 23))
+#define ANUBIS_IDEPRI                   ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX                ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC                   ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX                ANUBIS_IOADDR(0x01300000)
+#endif /* __MACH_S3C24XX_ANUBIS_H */
diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index ba02cf8d80a2..3f0288f2f542 100644
--- a/arch/arm/mach-s3c24xx/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
@@ -25,8 +25,8 @@
 #include <asm/mach/irq.h>
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
+#include "bast.h"
 /* IDE ports */
@@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = {
        .ioport_shift   = 5,
 };
-#define IDE_CS  S3C2410_CS5
 static struct resource bast_ide0_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
 };
 static struct platform_device bast_device_ide0 = {
@@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = {
 };
 static struct resource bast_ide1_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE1),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
 };
 static struct platform_device bast_device_ide1 = {
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index ac7b2ad5c405..c0daa9590b4c 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -27,27 +27,20 @@
 #include <linux/device.h>
 #include <linux/io.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/irq.h>
+#include <mach/hardware.h>
 #include <mach/regs-irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
 #include <plat/irq.h>
-#if 0
+#include "bast.h"
-#include <asm/debug-ll.h>
-#endif
 #define irqdbf(x...)
 #define irqdbf2(x...)
 /* handle PC104 ISA interrupts from the system CPLD */
 /* table of ISA irq nos to the relevant mask... zero means
@@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data)
 static void
 bast_pc104_maskack(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_desc + IRQ_ISA;
+        struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
        bast_pc104_mask(data);
        desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq,
        if (unlikely(stat == 0)) {
                /* ack if we get an irq with nothing (ie, startup) */
-                desc = irq_desc + IRQ_ISA;
+                desc = irq_desc + BAST_IRQ_ISA;
                desc->irq_data.chip->irq_ack(&desc->irq_data);
        } else {
                /* handle the IRQ */
@@ -147,7 +140,7 @@ static __init int bast_irq_init(void)
                __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
-                irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
+                irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
                /* register our IRQs */
diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c24xx/bast.h
new file mode 100644
index 000000000000..5c7534bae92d
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/bast.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ * BAST - IRQ Number definitions
+ * BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_BAST_H
+#define __MACH_S3C24XX_BAST_H __FILE__
+/* CTRL1 - Audio LR routing */
+#define BAST_CPLD_CTRL1_LRCOFF          (0x00)
+#define BAST_CPLD_CTRL1_LRCADC          (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC          (0x02)
+#define BAST_CPLD_CTRL1_LRCARM          (0x03)
+#define BAST_CPLD_CTRL1_LRMASK          (0x03)
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+#define BAST_CPLD_CTRL2_WNAND           (0x04)
+#define BAST_CPLD_CTLR2_IDERST          (0x08)
+/* CTRL3 - rom write control, CPLD identity */
+#define BAST_CPLD_CTRL3_IDMASK          (0x0e)
+#define BAST_CPLD_CTRL3_ROMWEN          (0x01)
+/* CTRL4 - 8bit LCD interface control/status */
+#define BAST_CPLD_CTRL4_LLAT            (0x01)
+#define BAST_CPLD_CTRL4_LCDRW           (0x02)
+#define BAST_CPLD_CTRL4_LCDCMD          (0x04)
+#define BAST_CPLD_CTRL4_LCDE2           (0x01)
+/* CTRL5 - DMA routing */
+#define BAST_CPLD_DMA0_PRIIDE           (0)
+#define BAST_CPLD_DMA0_SECIDE           (1)
+#define BAST_CPLD_DMA0_ISA15            (2)
+#define BAST_CPLD_DMA0_ISA36            (3)
+#define BAST_CPLD_DMA1_PRIIDE           (0 << 2)
+#define BAST_CPLD_DMA1_SECIDE           (1 << 2)
+#define BAST_CPLD_DMA1_ISA15            (2 << 2)
+#define BAST_CPLD_DMA1_ISA36            (3 << 2)
+/* irq numbers to onboard peripherals */
+#define BAST_IRQ_USBOC                  IRQ_EINT18
+#define BAST_IRQ_IDE0                   IRQ_EINT16
+#define BAST_IRQ_IDE1                   IRQ_EINT17
+#define BAST_IRQ_PCSERIAL1              IRQ_EINT15
+#define BAST_IRQ_PCSERIAL2              IRQ_EINT14
+#define BAST_IRQ_PCPARALLEL             IRQ_EINT13
+#define BAST_IRQ_ASIX                   IRQ_EINT11
+#define BAST_IRQ_DM9000                 IRQ_EINT10
+#define BAST_IRQ_ISA                    IRQ_EINT9
+#define BAST_IRQ_SMALERT                IRQ_EINT8
+/* map */
+/*
+ * ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+#define BAST_IOADDR(x)                  (S3C2410_ADDR((x) + 0x01300000))
+/* we put the CPLD registers next, to get them out of the way */
+#define BAST_VA_CTRL1                   BAST_IOADDR(0x00000000)
+#define BAST_PA_CTRL1                   (S3C2410_CS5 | 0x7800000)
+#define BAST_VA_CTRL2                   BAST_IOADDR(0x00100000)
+#define BAST_PA_CTRL2                   (S3C2410_CS1 | 0x6000000)
+#define BAST_VA_CTRL3                   BAST_IOADDR(0x00200000)
+#define BAST_PA_CTRL3                   (S3C2410_CS1 | 0x6800000)
+#define BAST_VA_CTRL4                   BAST_IOADDR(0x00300000)
+#define BAST_PA_CTRL4                   (S3C2410_CS1 | 0x7000000)
+/* next, we have the PC104 ISA interrupt registers */
+#define BAST_PA_PC104_IRQREQ            (S3C2410_CS5 | 0x6000000)
+#define BAST_VA_PC104_IRQREQ            BAST_IOADDR(0x00400000)
+#define BAST_PA_PC104_IRQRAW            (S3C2410_CS5 | 0x6800000)
+#define BAST_VA_PC104_IRQRAW            BAST_IOADDR(0x00500000)
+#define BAST_PA_PC104_IRQMASK           (S3C2410_CS5 | 0x7000000)
+#define BAST_VA_PC104_IRQMASK           BAST_IOADDR(0x00600000)
+#define BAST_PA_LCD_RCMD1               (0x8800000)
+#define BAST_VA_LCD_RCMD1               BAST_IOADDR(0x00700000)
+#define BAST_PA_LCD_WCMD1               (0x8000000)
+#define BAST_VA_LCD_WCMD1               BAST_IOADDR(0x00800000)
+#define BAST_PA_LCD_RDATA1              (0x9800000)
+#define BAST_VA_LCD_RDATA1              BAST_IOADDR(0x00900000)
+#define BAST_PA_LCD_WDATA1              (0x9000000)
+#define BAST_VA_LCD_WDATA1              BAST_IOADDR(0x00A00000)
+#define BAST_PA_LCD_RCMD2               (0xA800000)
+#define BAST_VA_LCD_RCMD2               BAST_IOADDR(0x00B00000)
+#define BAST_PA_LCD_WCMD2               (0xA000000)
+#define BAST_VA_LCD_WCMD2               BAST_IOADDR(0x00C00000)
+#define BAST_PA_LCD_RDATA2              (0xB800000)
+#define BAST_VA_LCD_RDATA2              BAST_IOADDR(0x00D00000)
+#define BAST_PA_LCD_WDATA2              (0xB000000)
+#define BAST_VA_LCD_WDATA2              BAST_IOADDR(0x00E00000)
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+#define BAST_VA_MULTISPACE              (0xE0000000)
+#define BAST_VA_ISAIO                   (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM                  (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI                  (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX               (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC                  (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX               (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET                 (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000                  (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO                 (BAST_VA_MULTISPACE + 0x02600000)
+#define BAST_VAM_CS2                    (0x00000000)
+#define BAST_VAM_CS3                    (0x04000000)
+#define BAST_VAM_CS4                    (0x08000000)
+#define BAST_VAM_CS5                    (0x0C000000)
+/* physical offset addresses for the peripherals */
+#define BAST_PA_ISAIO                   (0x00000000)
+#define BAST_PA_ASIXNET                 (0x01000000)
+#define BAST_PA_SUPERIO                 (0x01800000)
+#define BAST_PA_IDEPRI                  (0x02000000)
+#define BAST_PA_IDEPRIAUX               (0x02800000)
+#define BAST_PA_IDESEC                  (0x03000000)
+#define BAST_PA_IDESECAUX               (0x03800000)
+#define BAST_PA_ISAMEM                  (0x04000000)
+#define BAST_PA_DM9000                  (0x05000000)
+/* some configurations for the peripherals */
+#define BAST_PCSIO                      (BAST_VA_SUPERIO + BAST_VAM_CS2)
+#define BAST_ASIXNET_CS                 BAST_VAM_CS5
+#define BAST_DM9000_CS                  BAST_VAM_CS4
+#define BAST_IDE_CS     S3C2410_CS5
+#endif /* __MACH_S3C24XX_BAST_H */
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
index f95d3268ae1f..1edd9b2369c5 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/mach-s3c24xx/clock-dclk.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
+/*
- *
 * Copyright (c) 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 25dc4d4397b1..641266f3d152 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/clock.c
+/*
- *
 * Copyright (c) 2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeb4a24ff3ed..f6b9f2ef01bd 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -132,7 +132,7 @@ static struct clk *clk_msysclk_sources[] = {
        [3] = &clk_mpllref,
 };
-struct clksrc_clk clk_msysclk = {
+static struct clksrc_clk clk_msysclk = {
        .clk    = {
                .name           = "msysclk",
                .parent         = &clk_xtal,
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 0c9e9a785ef6..6bcf87f65f9e 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
 static void s3c24xx_default_idle(void)
 {
-        unsigned long tmp;
+        unsigned long tmp = 0;
        int i;
        /* idle the system by using the idle mode which will wait for an
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index c2f596e7bc2d..ed6276fcaa3b 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -15,4 +15,6 @@
 void s3c2410_restart(char mode, const char *cmd);
 void s3c244x_restart(char mode, const char *cmd);
+extern struct syscore_ops s3c24xx_irq_syscore_ops;
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
index c7adad0e8de0..9b7b4289d66c 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+/*
- *
 * Copyright (c) 2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
index 5404535da1a5..cfa0dd8723ec 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/cpu-freq.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -81,7 +80,7 @@ static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
        cfg->divs.p_divisor = pdiv;
        cfg->divs.h_divisor = hdiv;
-        return 0      ;
+        return 0;
 }
 static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
@@ -131,7 +130,6 @@ static int __init s3c2410_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2410_cpufreq_interface);
 }
 arch_initcall(s3c2410_cpufreq_init);
 static int s3c2410a_cpufreq_add(struct device *dev,
@@ -159,5 +157,4 @@ static int __init s3c2410a_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2410a_cpufreq_interface);
 }
 arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
index 125be7d5fa60..8bf0f3a77476 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2412/cpu-freq.c
+/*
- *
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -26,12 +25,13 @@
 #include <asm/mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-s3c2412-mem.h>
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/cpu-freq-core.h>
+#include "s3c2412.h"
 /* our clock resources. */
 static struct clk *xtal;
 static struct clk *fclk;
@@ -111,7 +111,7 @@ static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
        return 0;
- invalid:
+invalid:
        return -EINVAL;
 }
@@ -255,5 +255,4 @@ static int s3c2412_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2412_cpufreq_interface);
 }
 arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
index 61776764d9f4..72b2cc8a5a85 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+/*
- *
 * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -310,5 +309,4 @@ static int s3c2442_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2442_cpufreq_interface);
 }
 subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 43ea80190d87..ddd8280e3875 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+/*
- *
 * Copyright (c) 2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -17,11 +16,12 @@
 #include <linux/io.h>
 #include <mach/map.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu-freq-core.h>
+#include "regs-mem.h"
 /**
 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
 * @cfg: The frequency configuration
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq.c
index 468079938884..5f181e733eee 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56e..25d085adc93c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920ff..d2408ba372cb 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84f..0b86e74d104f 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 2d94228d2866..05536254a3f8 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index ba3e76c95504..aab64909e9a3 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/dma.c
+/*
- *
 * Copyright 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/gta02.h
index 217393482153..9430a71e9184 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/gta02.h
@@ -1,5 +1,13 @@
-#ifndef _GTA02_H
+/*
-#define _GTA02_H
+ * GTA02 header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_GTA02_H
+#define __MACH_S3C24XX_GTA02_H __FILE__
 #include <mach/regs-gpio.h>
@@ -12,4 +20,4 @@
 #define GTA02_IRQ_PCF50633      IRQ_EINT9
-#endif /* _GTA02_H */
+#endif /* __MACH_S3C24XX_GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index 3f40c61b6e02..5b98bfd1df43 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -19,10 +19,10 @@
 #include <linux/gpio.h>
 #include <linux/rfkill.h>
-#include <mach/regs-gpio.h>
 #include <mach/hardware.h>
-#include <mach/h1940-latch.h>
+#include <mach/regs-gpio.h>
-#include <mach/h1940.h>
+#include "h1940.h"
 #define DRV_NAME "h1940-bt"
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/h1940.h
index fc897d3a056c..2950cc466840 100644
--- a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c24xx/h1940.h
@@ -1,20 +1,30 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+/*
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
 *
 * Copyright (c) 2005 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
- *  iPAQ H1940 series - latch definitions
+ * iPAQ H1940 series definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_H1940_LATCH_H
+#ifndef __MACH_S3C24XX_H1940_H
-#define __ASM_ARCH_H1940_LATCH_H
+#define __MACH_S3C24XX_H1940_H __FILE__
-#include <asm/gpio.h>
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+extern void h1940_pm_return(void);
+extern int h1940_led_blink_set(unsigned gpio, int state,
+                               unsigned long *delay_on,
+                               unsigned long *delay_off);
+#include <linux/gpio.h>
 #define H1940_LATCH_GPIO(x)             (S3C_GPIO_END + (x))
@@ -40,4 +50,4 @@
 #define H1940_LATCH_LED_GREEN           H1940_LATCH_GPIO(14)
 #define H1940_LATCH_LED_FLASH           H1940_LATCH_GPIO(15)
-#endif /* __ASM_ARCH_H1940_LATCH_H */
+#endif /* __MACH_S3C24XX_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
deleted file mode 100644
index 1b614d5a81f3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_ANUBISCPLD_H
-#define __ASM_ARCH_ANUBISCPLD_H
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-#define ANUBIS_CTRL1_NANDSEL            (0x3)
-/* IDREG - revision */
-#define ANUBIS_IDREG_REVMASK            (0x7)
-#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
deleted file mode 100644
index a2a328134e34..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  ANUBIS - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_ANUBISIRQ_H
-#define __ASM_ARCH_ANUBISIRQ_H
-#define IRQ_IDE0       IRQ_EINT2
-#define IRQ_IDE1       IRQ_EINT3
-#define IRQ_ASIX       IRQ_EINT1
-#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
deleted file mode 100644
index c9deb3a5b2c3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-#ifndef __ASM_ARCH_ANUBISMAP_H
-#define __ASM_ARCH_ANUBISMAP_H
-/* start peripherals off after the S3C2410 */
-#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
-#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
-/* we put the CPLD registers next, to get them out of the way */
-#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
-#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
-#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
-#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
-#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
-#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
-#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
deleted file mode 100644
index bee2a7a932a0..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * BAST - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_BASTCPLD_H
-#define __ASM_ARCH_BASTCPLD_H
-/* CTRL1 - Audio LR routing */
-#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
-#define BAST_CPLD_CTRL1_LRCADC      (0x01)
-#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
-#define BAST_CPLD_CTRL1_LRCARM      (0x03)
-#define BAST_CPLD_CTRL1_LRMASK      (0x03)
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-#define BAST_CPLD_CTRL2_WNAND       (0x04)
-#define BAST_CPLD_CTLR2_IDERST      (0x08)
-/* CTRL3 - rom write control, CPLD identity */
-#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
-#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
-/* CTRL4 - 8bit LCD interface control/status */
-#define BAST_CPLD_CTRL4_LLAT        (0x01)
-#define BAST_CPLD_CTRL4_LCDRW       (0x02)
-#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
-#define BAST_CPLD_CTRL4_LCDE2       (0x01)
-/* CTRL5 - DMA routing */
-#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
-#define BAST_CPLD_DMA0_SECIDE      (1<<0)
-#define BAST_CPLD_DMA0_ISA15       (2<<0)
-#define BAST_CPLD_DMA0_ISA36       (3<<0)
-#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
-#define BAST_CPLD_DMA1_SECIDE      (1<<2)
-#define BAST_CPLD_DMA1_ISA15       (2<<2)
-#define BAST_CPLD_DMA1_ISA36       (3<<2)
-#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
deleted file mode 100644
index cac428c42e7f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_BASTIRQ_H
-#define __ASM_ARCH_BASTIRQ_H
-/* irq numbers to onboard peripherals */
-#define IRQ_USBOC      IRQ_EINT18
-#define IRQ_IDE0       IRQ_EINT16
-#define IRQ_IDE1       IRQ_EINT17
-#define IRQ_PCSERIAL1  IRQ_EINT15
-#define IRQ_PCSERIAL2  IRQ_EINT14
-#define IRQ_PCPARALLEL IRQ_EINT13
-#define IRQ_ASIX       IRQ_EINT11
-#define IRQ_DM9000     IRQ_EINT10
-#define IRQ_ISA        IRQ_EINT9
-#define IRQ_SMALERT    IRQ_EINT8
-#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
deleted file mode 100644
index eecea2a50f8f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-map.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-map.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-#ifndef __ASM_ARCH_BASTMAP_H
-#define __ASM_ARCH_BASTMAP_H
-#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
-/* we put the CPLD registers next, to get them out of the way */
-#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
-#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
-#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
-#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
-#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
-#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
-#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
-#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
-/* next, we have the PC104 ISA interrupt registers */
-#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
-#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
-#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
-#define BAST_PA_LCD_RCMD1     (0x8800000)
-#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
-#define BAST_PA_LCD_WCMD1     (0x8000000)
-#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
-#define BAST_PA_LCD_RDATA1    (0x9800000)
-#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
-#define BAST_PA_LCD_WDATA1    (0x9000000)
-#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
-#define BAST_PA_LCD_RCMD2     (0xA800000)
-#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
-#define BAST_PA_LCD_WCMD2     (0xA000000)
-#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
-#define BAST_PA_LCD_RDATA2    (0xB800000)
-#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
-#define BAST_PA_LCD_WDATA2    (0xB000000)
-#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x00000000 to 0x01000000 16MB ISA IO space
- * 0x01000000 to 0x02000000 16MB ISA memory space
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
- * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-#define BAST_VA_MULTISPACE (0xE0000000)
-#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
-#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
-#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
-#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
-#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
-#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
-#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
-#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
-#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
-#define BAST_VA_MULTISPACE (0xE0000000)
-#define BAST_VAM_CS2 (0x00000000)
-#define BAST_VAM_CS3 (0x04000000)
-#define BAST_VAM_CS4 (0x08000000)
-#define BAST_VAM_CS5 (0x0C000000)
-/* physical offset addresses for the peripherals */
-#define BAST_PA_ISAIO     (0x00000000)
-#define BAST_PA_ASIXNET   (0x01000000)
-#define BAST_PA_SUPERIO   (0x01800000)
-#define BAST_PA_IDEPRI    (0x02000000)
-#define BAST_PA_IDEPRIAUX (0x02800000)
-#define BAST_PA_IDESEC    (0x03000000)
-#define BAST_PA_IDESECAUX (0x03800000)
-#define BAST_PA_ISAMEM    (0x04000000)
-#define BAST_PA_DM9000    (0x05000000)
-/* some configurations for the peripherals */
-#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
-/*  */
-#define BAST_ASIXNET_CS  BAST_VAM_CS5
-#define BAST_IDE_CS      BAST_VAM_CS5
-#define BAST_DM9000_CS   BAST_VAM_CS4
-#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 4135de87d1f7..13ed33c69113 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -40,17 +40,17 @@
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
 1004:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                moveq   \rd, \rd, lsr #SHIFT_2440TXF
                tst     \rd, #S3C2410_UFSTAT_TXFULL
        .endm
        .macro  fifo_full_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S3C2410_UFSTAT_TXFULL
        .endm
@@ -68,18 +68,18 @@
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
 10000:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
        .endm
        .macro fifo_level_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
index 7615a14773fa..6a21beeba1da 100644
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -31,10 +31,10 @@
                @@ try the interrupt offset register, since it is there
-                ldr     \irqstat, [ \base, #INTPND ]
+                ldr     \irqstat, [\base, #INTPND ]
                teq     \irqstat, #0
                beq     1002f
-                ldr     \irqnr, [ \base, #INTOFFSET ]
+                ldr     \irqnr, [\base, #INTOFFSET ]
                mov     \tmp, #1
                tst     \irqstat, \tmp, lsl \irqnr
                bne     1001f
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
deleted file mode 100644
index c53ad34c6579..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
deleted file mode 100644
index 3890a05948fb..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - GPIO bank numbering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __MACH_GPIONRS_H
-#define __MACH_GPIONRS_H
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-#define S3C2410_GPIO_BANKG   (32*6)
-#define S3C2410_GPIO_BANKH   (32*7)
-/* GPIO sizes for various SoCs:
- *
- *             2442
- *   2410 2412 2440 2443 2416
- *   ---- ---- ---- ---- ----
- * A 23   22   25   16   25
- * B 11   11   11   11   9
- * C 16   15   16   16   16
- * D 16   16   16   16   16
- * E 16   16   16   16   16
- * F 8    8    8    8    8
- * G 16   16   16   16   8
- * H 11   11   9    15   15
- * J --   --   13   16   --
- * K --   --   --   --   16
- * L --   --   --   15   7
- * M --   --   --   2    2
- */
-/* GPIO bank sizes */
-#define S3C2410_GPIO_A_NR       (32)
-#define S3C2410_GPIO_B_NR       (32)
-#define S3C2410_GPIO_C_NR       (32)
-#define S3C2410_GPIO_D_NR       (32)
-#define S3C2410_GPIO_E_NR       (32)
-#define S3C2410_GPIO_F_NR       (32)
-#define S3C2410_GPIO_G_NR       (32)
-#define S3C2410_GPIO_H_NR       (32)
-#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
-#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
-#if CONFIG_S3C_GPIO_SPACE != 0
-#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
-#endif
-#define S3C2410_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
-#ifndef __ASSEMBLY__
-enum s3c_gpio_number {
-        S3C2410_GPIO_A_START = 0,
-        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
-        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
-        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
-        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
-        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
-        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
-        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
-        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
-        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
-        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
-        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
-};
-#endif /* __ASSEMBLY__ */
-/* S3C2410 GPIO number definitions. */
-#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
-#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
-#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
-#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
-#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
-#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
-#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
-#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
-#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
-#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
-#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
-#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
-#endif /* __MACH_GPIONRS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
deleted file mode 100644
index c410a078622c..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C2410 - GPIO core support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_GPIO_CORE_H
-#define __ASM_ARCH_GPIO_CORE_H __FILE__
-#include <mach/regs-gpio.h>
-extern struct samsung_gpio_chip s3c24xx_gpios[];
-static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip;
-        if (pin > S3C_GPIO_END)
-                return NULL;
-        chip = &s3c24xx_gpios[pin/32];
-        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
-}
-#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
index 6fac70f3484e..14591563ca70 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio.h
+/*
- *
 * Copyright (c) 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -15,6 +14,9 @@
 * devices that need GPIO.
 */
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H __FILE__
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
 #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
@@ -23,8 +25,83 @@
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
-#include <mach/gpio-nrs.h>
+/*
-#include <mach/gpio-fns.h>
+ * GPIO sizes for various SoCs:
+ *
+ *   2410 2412 2440 2443 2416
+ *             2442
+ *   ---- ---- ---- ---- ----
+ * A  23   22   25   16   25
+ * B  11   11   11   11   9
+ * C  16   15   16   16   16
+ * D  16   16   16   16   16
+ * E  16   16   16   16   16
+ * F  8    8    8    8    8
+ * G  16   16   16   16   8
+ * H  11   11   9    15   15
+ * J  --   --   13   16   --
+ * K  --   --   --   --   16
+ * L  --   --   --   15   7
+ * M  --   --   --   2    2
+ */
+/* GPIO bank sizes */
+#define S3C2410_GPIO_A_NR       (32)
+#define S3C2410_GPIO_B_NR       (32)
+#define S3C2410_GPIO_C_NR       (32)
+#define S3C2410_GPIO_D_NR       (32)
+#define S3C2410_GPIO_E_NR       (32)
+#define S3C2410_GPIO_F_NR       (32)
+#define S3C2410_GPIO_G_NR       (32)
+#define S3C2410_GPIO_H_NR       (32)
+#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
+#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
+#if CONFIG_S3C_GPIO_SPACE != 0
+#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
+#endif
+#define S3C2410_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
+#ifndef __ASSEMBLY__
+enum s3c_gpio_number {
+        S3C2410_GPIO_A_START = 0,
+        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
+        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
+        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
+        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
+        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
+        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
+        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
+        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
+        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
+        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
+};
+#endif /* __ASSEMBLY__ */
+/* S3C2410 GPIO number definitions. */
+#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
+#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
+#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
+#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
+#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
+#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
+#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
+#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
+#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
+#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
+#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
+#include <plat/gpio-cfg.h>
 #ifdef CONFIG_CPU_S3C244X
 #define S3C_GPIO_END    (S3C2410_GPJ(0) + 32)
@@ -33,3 +110,5 @@
 #else
 #define S3C_GPIO_END    (S3C2410_GPH(0) + 32)
 #endif
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
deleted file mode 100644
index 2aa683c8d3d6..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/h1940.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940.h
- *
- * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
- *
- * H1940 definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_H1940_H
-#define __ASM_ARCH_H1940_H
-#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
-#define H1940_SUSPEND_RESUMEAT          (0x30081000)
-#define H1940_SUSPEND_CHECK             (0x30080000)
-extern void h1940_pm_return(void);
-extern int h1940_led_blink_set(unsigned gpio, int state,
-        unsigned long *delay_on, unsigned long *delay_off);
-#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac58..a6cc14a092fc 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -23,12 +23,6 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 #endif /* CONFIG_CPU_S3C2440 */
-#ifdef CONFIG_CPU_S3C2412
-extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
-#endif /* CONFIG_CPU_S3C2412 */
 #endif /* __ASSEMBLY__ */
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
deleted file mode 100644
index e9ddd706b16e..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/idle.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/idle.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU Idle controls
-*/
-#ifndef __ASM_ARCH_IDLE_H
-#define __ASM_ARCH_IDLE_H __FILE__
-/* This allows the over-ride of the default idle code, in case there
- * is any other things to be done over idle (like DVS)
-*/
-extern void (*s3c24xx_idle)(void);
-extern void s3c24xx_default_idle(void);
-#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
deleted file mode 100644
index e9e36b0abbac..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
- *
- * Copyright 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * OSIRIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_OSIRISCPLD_H
-#define __ASM_ARCH_OSIRISCPLD_H
-/* CTRL0 - NAND WP control */
-#define OSIRIS_CTRL0_NANDSEL            (0x3)
-#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
-#define OSIRIS_CTRL0_PCMCIA             (1<<4)
-#define OSIRIS_CTRL0_FIX8               (1<<5)
-#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
-#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
-#define OSIRIS_CTRL1_FIX8               (1<<0)
-#define OSIRIS_ID_REVMASK               (0x7)
-#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index a11a638bd599..c2ef016032ab 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -14,8 +14,6 @@
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H
-#include <mach/gpio-nrs.h>
 #define S3C24XX_MISCCR          S3C24XX_GPIOREG2(0x80)
 /* general configuration options */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Memory Control register definitions
-*/
-#ifndef __ASM_ARM_MEMREGS_H
-#define __ASM_ARM_MEMREGS_H
-#ifndef S3C2410_MEMREG
-#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-/* bus width, and wait state control */
-#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
-/* bank zero config - note, pinstrapped from OM pins! */
-#define S3C2410_BWSCON_DW0_16           (1<<1)
-#define S3C2410_BWSCON_DW0_32           (2<<1)
-/* bank one configs */
-#define S3C2410_BWSCON_DW1_8            (0<<4)
-#define S3C2410_BWSCON_DW1_16           (1<<4)
-#define S3C2410_BWSCON_DW1_32           (2<<4)
-#define S3C2410_BWSCON_WS1              (1<<6)
-#define S3C2410_BWSCON_ST1              (1<<7)
-/* bank 2 configurations */
-#define S3C2410_BWSCON_DW2_8            (0<<8)
-#define S3C2410_BWSCON_DW2_16           (1<<8)
-#define S3C2410_BWSCON_DW2_32           (2<<8)
-#define S3C2410_BWSCON_WS2              (1<<10)
-#define S3C2410_BWSCON_ST2              (1<<11)
-/* bank 3 configurations */
-#define S3C2410_BWSCON_DW3_8            (0<<12)
-#define S3C2410_BWSCON_DW3_16           (1<<12)
-#define S3C2410_BWSCON_DW3_32           (2<<12)
-#define S3C2410_BWSCON_WS3              (1<<14)
-#define S3C2410_BWSCON_ST3              (1<<15)
-/* bank 4 configurations */
-#define S3C2410_BWSCON_DW4_8            (0<<16)
-#define S3C2410_BWSCON_DW4_16           (1<<16)
-#define S3C2410_BWSCON_DW4_32           (2<<16)
-#define S3C2410_BWSCON_WS4              (1<<18)
-#define S3C2410_BWSCON_ST4              (1<<19)
-/* bank 5 configurations */
-#define S3C2410_BWSCON_DW5_8            (0<<20)
-#define S3C2410_BWSCON_DW5_16           (1<<20)
-#define S3C2410_BWSCON_DW5_32           (2<<20)
-#define S3C2410_BWSCON_WS5              (1<<22)
-#define S3C2410_BWSCON_ST5              (1<<23)
-/* bank 6 configurations */
-#define S3C2410_BWSCON_DW6_8            (0<<24)
-#define S3C2410_BWSCON_DW6_16           (1<<24)
-#define S3C2410_BWSCON_DW6_32           (2<<24)
-#define S3C2410_BWSCON_WS6              (1<<26)
-#define S3C2410_BWSCON_ST6              (1<<27)
-/* bank 7 configurations */
-#define S3C2410_BWSCON_DW7_8            (0<<28)
-#define S3C2410_BWSCON_DW7_16           (1<<28)
-#define S3C2410_BWSCON_DW7_32           (2<<28)
-#define S3C2410_BWSCON_WS7              (1<<30)
-#define S3C2410_BWSCON_ST7              (1<<31)
-/* accesor functions for getting BANK(n) configuration. (n != 0) */
-#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
-#define S3C2410_BWSCON_DW8              (0)
-#define S3C2410_BWSCON_DW16             (1)
-#define S3C2410_BWSCON_DW32             (2)
-#define S3C2410_BWSCON_WS               (1 << 2)
-#define S3C2410_BWSCON_ST               (1 << 3)
-/* memory set (rom, ram) */
-#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
-#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
-#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
-#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
-#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
-#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
-#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
-#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
-/* bank configuration registers */
-#define S3C2410_BANKCON_PMCnorm         (0x00)
-#define S3C2410_BANKCON_PMC4            (0x01)
-#define S3C2410_BANKCON_PMC8            (0x02)
-#define S3C2410_BANKCON_PMC16           (0x03)
-/* bank configurations for banks 0..7, note banks
- * 6 and 7 have different configurations depending on
- * the memory type bits */
-#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
-#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
-#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
-#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
-#define S3C2410_BANKCON_Tacp_SHIFT      (2)
-#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
-#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
-#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
-#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
-#define S3C2410_BANKCON_Tcah_SHIFT      (4)
-#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
-#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
-#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
-#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
-#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
-#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
-#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
-#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
-#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
-#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
-#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
-#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
-#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
-#define S3C2410_BANKCON_Tacc_SHIFT      (8)
-#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
-#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
-#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
-#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
-#define S3C2410_BANKCON_Tcos_SHIFT      (11)
-#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
-#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
-#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
-#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
-#define S3C2410_BANKCON_Tacs_SHIFT      (13)
-#define S3C2410_BANKCON_SRAM            (0x0 << 15)
-#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
-/* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trcd2           (0x00 << 2)
-#define S3C2410_BANKCON_Trcd3           (0x01 << 2)
-#define S3C2410_BANKCON_Trcd4           (0x02 << 2)
-/* control column address select */
-#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
-#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
-#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
-#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
-#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
-#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
-#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
-/* refresh control */
-#define S3C2410_REFRESH_REFEN           (1<<23)
-#define S3C2410_REFRESH_SELF            (1<<22)
-#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
-#define S3C2410_REFRESH_TRP_MASK        (3<<20)
-#define S3C2410_REFRESH_TRP_2clk        (0<<20)
-#define S3C2410_REFRESH_TRP_3clk        (1<<20)
-#define S3C2410_REFRESH_TRP_4clk        (2<<20)
-#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
-#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
-#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
-#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
-#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
-/* mode select register(s) */
-#define  S3C2410_MRSRB_CL1              (0x00 << 4)
-#define  S3C2410_MRSRB_CL2              (0x02 << 4)
-#define  S3C2410_MRSRB_CL3              (0x03 << 4)
-/* bank size register */
-#define S3C2410_BANKSIZE_128M           (0x2 << 0)
-#define S3C2410_BANKSIZE_64M            (0x1 << 0)
-#define S3C2410_BANKSIZE_32M            (0x0 << 0)
-#define S3C2410_BANKSIZE_16M            (0x7 << 0)
-#define S3C2410_BANKSIZE_8M             (0x6 << 0)
-#define S3C2410_BANKSIZE_4M             (0x5 << 0)
-#define S3C2410_BANKSIZE_2M             (0x4 << 0)
-#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
-#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
-#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
-#define S3C2410_BANKSIZE_BURST          (1<<7)
-#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-power.h
- *
- * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX power control register definitions
-*/
-#ifndef __ASM_ARM_REGS_PWR
-#define __ASM_ARM_REGS_PWR __FILE__
-#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
-#define S3C2412_PWRMODECON      S3C24XX_PWRREG(0x20)
-#define S3C2412_PWRCFG          S3C24XX_PWRREG(0x24)
-#define S3C2412_INFORM0         S3C24XX_PWRREG(0x70)
-#define S3C2412_INFORM1         S3C24XX_PWRREG(0x74)
-#define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
-#define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
-#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
-#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
-#define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
-#define S3C2412_PWRCFG_BATF_MASK                (3<<0)
-#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3<<6)
-#define S3C2412_PWRCFG_RTC_MASKIRQ              (1<<8)
-#define S3C2412_PWRCFG_NAND_NORST               (1<<9)
-#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 memory register definitions
-*/
-#ifndef __ASM_ARM_REGS_S3C2412_MEM
-#define __ASM_ARM_REGS_S3C2412_MEM
-#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
-#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
-#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
-#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
-#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
-#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
-#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
-#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
-#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
-/* EBI control registers */
-#define S3C2412_EBI_PR                  S3C2412_EBIREG(0x00)
-#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x04)
-/* SSMC control registers */
-#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMIDCYR(x)              S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMBWSTRD(x)             S3C2412_SSMC(x, 0x04)
-#define S3C2412_SMBWSTWRR(x)            S3C2412_SSMC(x, 0x08)
-#define S3C2412_SMBWSTOENR(x)           S3C2412_SSMC(x, 0x0C)
-#define S3C2412_SMBWSTWENR(x)           S3C2412_SSMC(x, 0x10)
-#define S3C2412_SMBCR(x)                S3C2412_SSMC(x, 0x14)
-#define S3C2412_SMBSR(x)                S3C2412_SSMC(x, 0x18)
-#define S3C2412_SMBWSTBRDR(x)           S3C2412_SSMC(x, 0x1C)
-#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
deleted file mode 100644
index aa69dc79bc38..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
- *
- * Copyright 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 specific register definitions
-*/
-#ifndef __ASM_ARCH_REGS_S3C2412_H
-#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
-#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
-#define S3C2412_SWRST_RESET     (0x533C2412)
-/* see regs-power.h for the other registers in the power block. */
-#endif  /* __ASM_ARCH_REGS_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
deleted file mode 100644
index 2f31b74974af..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 memory register definitions
-*/
-#ifndef __ASM_ARM_REGS_S3C2416_MEM
-#define __ASM_ARM_REGS_S3C2416_MEM
-#ifndef S3C2416_MEMREG
-#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-#define S3C2416_BANKCFG                 S3C2416_MEMREG(0x00)
-#define S3C2416_BANKCON1                S3C2416_MEMREG(0x04)
-#define S3C2416_BANKCON2                S3C2416_MEMREG(0x08)
-#define S3C2416_BANKCON3                S3C2416_MEMREG(0x0C)
-#define S3C2416_REFRESH                 S3C2416_MEMREG(0x10)
-#define S3C2416_TIMEOUT                 S3C2416_MEMREG(0x14)
-#endif /*  __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
deleted file mode 100644
index e443167efb87..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 specific register definitions
-*/
-#ifndef __ASM_ARCH_REGS_S3C2416_H
-#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
-#define S3C2416_SWRST           (S3C24XX_VA_CLKPWR + 0x44)
-#define S3C2416_SWRST_RESET     (0x533C2416)
-/* see regs-power.h for the other registers in the power block. */
-#endif  /* __ASM_ARCH_REGS_S3C2416_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
deleted file mode 100644
index e4119913d7c5..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * VR1000 - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VR1000CPLD_H
-#define __ASM_ARCH_VR1000CPLD_H
-#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
-#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
deleted file mode 100644
index 47add133b8ee..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VR1000IRQ_H
-#define __ASM_ARCH_VR1000IRQ_H
-/* irq numbers to onboard peripherals */
-#define IRQ_USBOC            IRQ_EINT19
-#define IRQ_IDE0             IRQ_EINT16
-#define IRQ_IDE1             IRQ_EINT17
-#define IRQ_VR1000_SERIAL    IRQ_EINT12
-#define IRQ_VR1000_DM9000A   IRQ_EINT10
-#define IRQ_VR1000_DM9000N   IRQ_EINT9
-#define IRQ_SMALERT          IRQ_EINT8
-#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
deleted file mode 100644
index 28376e56dd3b..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-#ifndef __ASM_ARCH_VR1000MAP_H
-#define __ASM_ARCH_VR1000MAP_H
-#include <mach/bast-map.h>
-#define VR1000_IOADDR(x) BAST_IOADDR(x)
-/* we put the CPLD registers next, to get them out of the way */
-#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
-#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
-#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
-#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
-#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
-#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
-#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
-#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
-/* next, we have the PC104 ISA interrupt registers */
-#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
-#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
-#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
- * 0x02600000 to 0x02700000 1MB
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-#define VR1000_VA_MULTISPACE (0xE0000000)
-#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
-#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
-#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
-#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
-#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
-#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
-#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
-#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
-#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
-/* physical offset addresses for the peripherals */
-#define VR1000_PA_IDEPRI           (0x02000000)
-#define VR1000_PA_IDEPRIAUX        (0x02800000)
-#define VR1000_PA_IDESEC           (0x03000000)
-#define VR1000_PA_IDESECAUX        (0x03800000)
-#define VR1000_PA_DM9000           (0x05000000)
-#define VR1000_PA_SERIAL           (0x11800000)
-#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
-/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
-#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
-/* some configurations for the peripherals */
-#define VR1000_DM9000_CS         VR1000_VAM_CS4
-#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
index b1908e56da1b..4cd13ab6496b 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+/*
- *
 * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -20,11 +19,12 @@
 #include <linux/slab.h>
 #include <mach/map.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu-freq-core.h>
+#include "regs-mem.h"
 #define print_ns(x) ((x) / 10), ((x) % 10)
 /**
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 48eee39ab369..663436d9db01 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -28,12 +27,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/regs-s3c2412-mem.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq-core.h>
 #include <plat/clock.h>
+#include "s3c2412.h"
 #define print_ns(x) ((x) / 10), ((x) % 10)
 /**
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index 0efb2e2848c8..e1199599873e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/syscore_ops.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -29,18 +30,18 @@
 * set bit to 1 in allow bitfield to enable the wakeup settings on it
 */
-unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
+unsigned long s3c_irqwake_intallow      = 1L << 30 | 0xfL;
 unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
-        unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
+        unsigned long irqbit = 1 << data->hwirq;
        if (!(s3c_irqwake_intallow & irqbit))
                return -ENOENT;
-        printk(KERN_INFO "wake %s for irq %d\n",
+        pr_info("wake %s for hwirq %lu\n",
-               state ? "enabled" : "disabled", data->irq);
+                state ? "enabled" : "disabled", data->hwirq);
        if (!state)
                s3c_irqwake_intmask |= irqbit;
@@ -64,7 +65,7 @@ static unsigned long save_extint[3];
 static unsigned long save_eintflt[4];
 static unsigned long save_eintmask;
-int s3c24xx_irq_suspend(void)
+static int s3c24xx_irq_suspend(void)
 {
        unsigned int i;
@@ -80,7 +81,7 @@ int s3c24xx_irq_suspend(void)
        return 0;
 }
-void s3c24xx_irq_resume(void)
+static void s3c24xx_irq_resume(void)
 {
        unsigned int i;
@@ -93,3 +94,31 @@ void s3c24xx_irq_resume(void)
        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
        __raw_writel(save_eintmask, S3C24XX_EINTMASK);
 }
+struct syscore_ops s3c24xx_irq_syscore_ops = {
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+#ifdef CONFIG_CPU_S3C2416
+static struct sleep_save s3c2416_irq_save[] = {
+        SAVE_ITEM(S3C2416_INTMSK2),
+};
+static int s3c2416_irq_suspend(void)
+{
+        s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+        return 0;
+}
+static void s3c2416_irq_resume(void)
+{
+        s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+}
+struct syscore_ops s3c2416_irq_syscore_ops = {
+        .suspend        = s3c2416_irq_suspend,
+        .resume         = s3c2416_irq_resume,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbccc..67d763178d3f 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
@@ -33,12 +33,13 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-power.h>
 #include <plat/cpu.h>
 #include <plat/irq.h>
 #include <plat/pm.h>
+#include "s3c2412-power.h"
 #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
 #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
deleted file mode 100644
index ff141b0af26b..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/irq.c
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-        end = len + irq;
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-                subsrc >>= 1;
-        }
-}
-/* WDT/AC97 sub interrupts */
-static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static struct irq_chip s3c2416_irq_wdtac97 = {
-        .irq_mask       = s3c2416_irq_wdtac97_mask,
-        .irq_unmask     = s3c2416_irq_wdtac97_unmask,
-        .irq_ack        = s3c2416_irq_wdtac97_ack,
-};
-/* LCD sub interrupts */
-static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-static void s3c2416_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static void s3c2416_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-static void s3c2416_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static struct irq_chip s3c2416_irq_lcd = {
-        .irq_mask       = s3c2416_irq_lcd_mask,
-        .irq_unmask     = s3c2416_irq_lcd_unmask,
-        .irq_ack        = s3c2416_irq_lcd_ack,
-};
-/* DMA sub interrupts */
-static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-static void s3c2416_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static void s3c2416_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-static void s3c2416_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static struct irq_chip s3c2416_irq_dma = {
-        .irq_mask       = s3c2416_irq_dma_mask,
-        .irq_unmask     = s3c2416_irq_dma_unmask,
-        .irq_ack        = s3c2416_irq_dma_ack,
-};
-/* UART3 sub interrupts */
-static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-static void s3c2416_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static void s3c2416_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-static void s3c2416_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static struct irq_chip s3c2416_irq_uart3 = {
-        .irq_mask       = s3c2416_irq_uart3_mask,
-        .irq_unmask     = s3c2416_irq_uart3_unmask,
-        .irq_ack        = s3c2416_irq_uart3_ack,
-};
-/* second interrupt register */
-static inline void s3c2416_irq_ack_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        __raw_writel(bitval, S3C2416_SRCPND2);
-        __raw_writel(bitval, S3C2416_INTPND2);
-}
-static void s3c2416_irq_mask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask |= bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-static void s3c2416_irq_unmask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask &= ~bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-struct irq_chip s3c2416_irq_second = {
-        .irq_ack        = s3c2416_irq_ack_second,
-        .irq_mask       = s3c2416_irq_mask_second,
-        .irq_unmask     = s3c2416_irq_unmask_second,
-};
-/* IRQ initialisation code */
-static int s3c2416_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        return 0;
-}
-static void s3c2416_irq_add_second(void)
-{
-        unsigned long pend;
-        unsigned long last;
-        int irqno;
-        int i;
-        /* first, clear all interrupts pending... */
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2416_INTPND2);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C2416_SRCPND2);
-                __raw_writel(pend, S3C2416_INTPND2);
-                printk(KERN_INFO "irq: clearing pending status %08x\n",
-                       (int)pend);
-                last = pend;
-        }
-        for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
-                switch (irqno) {
-                case IRQ_S3C2416_RESERVED2:
-                case IRQ_S3C2416_RESERVED3:
-                        /* no IRQ here */
-                        break;
-                default:
-                        irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
-                                                 handle_edge_irq);
-                        set_irq_flags(irqno, IRQF_VALID);
-                }
-        }
-}
-static int s3c2416_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk(KERN_INFO "S3C2416: IRQ Support\n");
-        s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
-                        IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
-        s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
-                        &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-        s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
-                        &s3c2416_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-        s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
-                        &s3c2416_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-        s3c2416_irq_add_second();
-        return 0;
-}
-static struct subsys_interface s3c2416_irq_interface = {
-        .name           = "s3c2416_irq",
-        .subsys         = &s3c2416_subsys,
-        .add_dev        = s3c2416_irq_add,
-};
-static int __init s3c2416_irq_init(void)
-{
-        return subsys_interface_register(&s3c2416_irq_interface);
-}
-arch_initcall(s3c2416_irq_init);
-#ifdef CONFIG_PM
-static struct sleep_save irq_save[] = {
-        SAVE_ITEM(S3C2416_INTMSK2),
-};
-int s3c2416_irq_suspend(void)
-{
-        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-        return 0;
-}
-void s3c2416_irq_resume(void)
-{
-        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-}
-struct syscore_ops s3c2416_irq_syscore_ops = {
-        .suspend        = s3c2416_irq_suspend,
-        .resume         = s3c2416_irq_resume,
-};
-#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
deleted file mode 100644
index 5e69109c0928..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* linux/arch/arm/mach-s3c2443/irq.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-        end = len + irq;
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-                subsrc >>= 1;
-        }
-}
-/* WDT/AC97 sub interrupts */
-static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static struct irq_chip s3c2443_irq_wdtac97 = {
-        .irq_mask       = s3c2443_irq_wdtac97_mask,
-        .irq_unmask     = s3c2443_irq_wdtac97_unmask,
-        .irq_ack        = s3c2443_irq_wdtac97_ack,
-};
-/* LCD sub interrupts */
-static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-static void s3c2443_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static void s3c2443_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-static void s3c2443_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static struct irq_chip s3c2443_irq_lcd = {
-        .irq_mask       = s3c2443_irq_lcd_mask,
-        .irq_unmask     = s3c2443_irq_lcd_unmask,
-        .irq_ack        = s3c2443_irq_lcd_ack,
-};
-/* DMA sub interrupts */
-static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-static void s3c2443_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static void s3c2443_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-static void s3c2443_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static struct irq_chip s3c2443_irq_dma = {
-        .irq_mask       = s3c2443_irq_dma_mask,
-        .irq_unmask     = s3c2443_irq_dma_unmask,
-        .irq_ack        = s3c2443_irq_dma_ack,
-};
-/* UART3 sub interrupts */
-static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-static void s3c2443_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static void s3c2443_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-static void s3c2443_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static struct irq_chip s3c2443_irq_uart3 = {
-        .irq_mask       = s3c2443_irq_uart3_mask,
-        .irq_unmask     = s3c2443_irq_uart3_unmask,
-        .irq_ack        = s3c2443_irq_uart3_ack,
-};
-/* CAM sub interrupts */
-static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
-}
-#define INTMSK_CAM      (1UL << (IRQ_CAM - IRQ_EINT0))
-#define SUBMSK_CAM      INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
-static void s3c2443_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-static void s3c2443_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-static void s3c2443_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-static struct irq_chip s3c2443_irq_cam = {
-        .irq_mask       = s3c2443_irq_cam_mask,
-        .irq_unmask     = s3c2443_irq_cam_unmask,
-        .irq_ack        = s3c2443_irq_cam_ack,
-};
-/* IRQ initialisation code */
-static int s3c2443_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        return 0;
-}
-static int s3c2443_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk("S3C2443: IRQ Support\n");
-        s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
-                        IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
-        s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
-                        IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
-        s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
-                        &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-        s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
-                        &s3c2443_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-        s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
-                        &s3c2443_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-        return 0;
-}
-static struct subsys_interface s3c2443_irq_interface = {
-        .name           = "s3c2443_irq",
-        .subsys         = &s3c2443_subsys,
-        .add_dev        = s3c2443_irq_add,
-};
-static int __init s3c2443_irq_init(void)
-{
-        return subsys_interface_register(&s3c2443_irq_interface);
-}
-arch_initcall(s3c2443_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
new file mode 100644
index 000000000000..cb9f5e011e73
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -0,0 +1,822 @@
+/*
+ * S3C24XX IRQ handling
+ *
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/irq.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/regs-irqtype.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+#define S3C_IRQTYPE_NONE        0
+#define S3C_IRQTYPE_EINT        1
+#define S3C_IRQTYPE_EDGE        2
+#define S3C_IRQTYPE_LEVEL       3
+struct s3c_irq_data {
+        unsigned int type;
+        unsigned long parent_irq;
+        /* data gets filled during init */
+        struct s3c_irq_intc *intc;
+        unsigned long sub_bits;
+        struct s3c_irq_intc *sub_intc;
+};
+/*
+ * Sructure holding the controller data
+ * @reg_pending         register holding pending irqs
+ * @reg_intpnd          special register intpnd in main intc
+ * @reg_mask            mask register
+ * @domain              irq_domain of the controller
+ * @parent              parent controller for ext and sub irqs
+ * @irqs                irq-data, always s3c_irq_data[32]
+ */
+struct s3c_irq_intc {
+        void __iomem            *reg_pending;
+        void __iomem            *reg_intpnd;
+        void __iomem            *reg_mask;
+        struct irq_domain       *domain;
+        struct s3c_irq_intc     *parent;
+        struct s3c_irq_data     *irqs;
+};
+static void s3c_irq_mask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        struct s3c_irq_data *parent_data;
+        unsigned long mask;
+        unsigned int irqno;
+        mask = __raw_readl(intc->reg_mask);
+        mask |= (1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+        if (parent_intc && irq_data->parent_irq) {
+                parent_data = &parent_intc->irqs[irq_data->parent_irq];
+                /* check to see if we need to mask the parent IRQ */
+                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
+                        irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                        s3c_irq_mask(irq_get_irq_data(irqno));
+                }
+        }
+}
+static void s3c_irq_unmask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        unsigned long mask;
+        unsigned int irqno;
+        mask = __raw_readl(intc->reg_mask);
+        mask &= ~(1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+        if (parent_intc && irq_data->parent_irq) {
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                s3c_irq_unmask(irq_get_irq_data(irqno));
+        }
+}
+static inline void s3c_irq_ack(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        unsigned long bitval = 1UL << data->hwirq;
+        __raw_writel(bitval, intc->reg_pending);
+        if (intc->reg_intpnd)
+                __raw_writel(bitval, intc->reg_intpnd);
+}
+static int s3c_irqext_type_set(void __iomem *gpcon_reg,
+                               void __iomem *extint_reg,
+                               unsigned long gpcon_offset,
+                               unsigned long extint_offset,
+                               unsigned int type)
+{
+        unsigned long newvalue = 0, value;
+        /* Set the GPIO to external interrupt mode */
+        value = __raw_readl(gpcon_reg);
+        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
+        __raw_writel(value, gpcon_reg);
+        /* Set the external interrupt to pointed trigger type */
+        switch (type)
+        {
+                case IRQ_TYPE_NONE:
+                        pr_warn("No edge setting!\n");
+                        break;
+                case IRQ_TYPE_EDGE_RISING:
+                        newvalue = S3C2410_EXTINT_RISEEDGE;
+                        break;
+                case IRQ_TYPE_EDGE_FALLING:
+                        newvalue = S3C2410_EXTINT_FALLEDGE;
+                        break;
+                case IRQ_TYPE_EDGE_BOTH:
+                        newvalue = S3C2410_EXTINT_BOTHEDGE;
+                        break;
+                case IRQ_TYPE_LEVEL_LOW:
+                        newvalue = S3C2410_EXTINT_LOWLEV;
+                        break;
+                case IRQ_TYPE_LEVEL_HIGH:
+                        newvalue = S3C2410_EXTINT_HILEV;
+                        break;
+                default:
+                        pr_err("No such irq type %d", type);
+                        return -EINVAL;
+        }
+        value = __raw_readl(extint_reg);
+        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
+        __raw_writel(value, extint_reg);
+        return 0;
+}
+/* FIXME: make static when it's out of plat-samsung/irq.h */
+int s3c_irqext_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT1;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 8) * 4;
+        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT2;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 16) * 4;
+        } else {
+                return -EINVAL;
+        }
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else {
+                return -EINVAL;
+        }
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+struct irq_chip s3c_irq_chip = {
+        .name           = "s3c",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake
+};
+struct irq_chip s3c_irq_level_chip = {
+        .name           = "s3c-level",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+};
+static struct irq_chip s3c_irqext_chip = {
+        .name           = "s3c-ext",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+        .irq_set_type   = s3c_irqext_type,
+        .irq_set_wake   = s3c_irqext_wake
+};
+static struct irq_chip s3c_irq_eint0t4 = {
+        .name           = "s3c-ext0",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext0_type,
+};
+static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
+        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
+        unsigned long src;
+        unsigned long msk;
+        unsigned int n;
+        chained_irq_enter(chip, desc);
+        src = __raw_readl(sub_intc->reg_pending);
+        msk = __raw_readl(sub_intc->reg_mask);
+        src &= ~msk;
+        src &= irq_data->sub_bits;
+        while (src) {
+                n = __ffs(src);
+                src &= ~(1 << n);
+                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+        }
+        chained_irq_exit(chip, desc);
+}
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ */
+int s3c24xx_set_fiq(unsigned int irq, bool on)
+{
+        u32 intmod;
+        unsigned offs;
+        if (on) {
+                offs = irq - FIQ_START;
+                if (offs > 31)
+                        return -EINVAL;
+                intmod = 1 << offs;
+        } else {
+                intmod = 0;
+        }
+        __raw_writel(intmod, S3C2410_INTMOD);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
+#endif
+static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct s3c_irq_intc *intc = h->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[hw];
+        struct s3c_irq_intc *parent_intc;
+        struct s3c_irq_data *parent_irq_data;
+        unsigned int irqno;
+        if (!intc) {
+                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+        if (!irq_data) {
+                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+        /* attach controller pointer to irq_data */
+        irq_data->intc = intc;
+        /* set handler and flags */
+        switch (irq_data->type) {
+        case S3C_IRQTYPE_NONE:
+                return 0;
+        case S3C_IRQTYPE_EINT:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_EDGE:
+                if (irq_data->parent_irq ||
+                    intc->reg_pending == S3C2416_SRCPND2)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_LEVEL:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_level_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_level_irq);
+                break;
+        default:
+                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
+                return -EINVAL;
+        }
+        set_irq_flags(virq, IRQF_VALID);
+        if (irq_data->parent_irq) {
+                parent_intc = intc->parent;
+                if (!parent_intc) {
+                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+                if (!irq_data) {
+                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+                parent_irq_data->sub_intc = intc;
+                parent_irq_data->sub_bits |= (1UL << hw);
+                /* attach the demuxer to the parent irq */
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                if (!irqno) {
+                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
+                               irq_data->parent_irq);
+                        goto err;
+                }
+                irq_set_chained_handler(irqno, s3c_irq_demux);
+        }
+        return 0;
+err:
+        set_irq_flags(virq, 0);
+        /* the only error can result from bad mapping data*/
+        return -EINVAL;
+}
+static struct irq_domain_ops s3c24xx_irq_ops = {
+        .map = s3c24xx_irq_map,
+        .xlate = irq_domain_xlate_twocell,
+};
+static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
+{
+        void __iomem *reg_source;
+        unsigned long pend;
+        unsigned long last;
+        int i;
+        /* if intpnd is set, read the next pending irq from there */
+        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
+        last = 0;
+        for (i = 0; i < 4; i++) {
+                pend = __raw_readl(reg_source);
+                if (pend == 0 || pend == last)
+                        break;
+                __raw_writel(pend, intc->reg_pending);
+                if (intc->reg_intpnd)
+                        __raw_writel(pend, intc->reg_intpnd);
+                pr_info("irq: clearing pending status %08x\n", (int)pend);
+                last = pend;
+        }
+}
+struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
+                                       struct s3c_irq_data *irq_data,
+                                       struct s3c_irq_intc *parent,
+                                       unsigned long address)
+{
+        struct s3c_irq_intc *intc;
+        void __iomem *base = (void *)0xf6000000; /* static mapping */
+        int irq_num;
+        int irq_start;
+        int irq_offset;
+        int ret;
+        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+        if (!intc)
+                return ERR_PTR(-ENOMEM);
+        intc->irqs = irq_data;
+        if (parent)
+                intc->parent = parent;
+        /* select the correct data for the controller.
+         * Need to hard code the irq num start and offset
+         * to preserve the static mapping for now
+         */
+        switch (address) {
+        case 0x4a000000:
+                pr_debug("irq: found main intc\n");
+                intc->reg_pending = base;
+                intc->reg_mask = base + 0x08;
+                intc->reg_intpnd = base + 0x10;
+                irq_num = 32;
+                irq_start = S3C2410_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000018:
+                pr_debug("irq: found subintc\n");
+                intc->reg_pending = base + 0x18;
+                intc->reg_mask = base + 0x1c;
+                irq_num = 29;
+                irq_start = S3C2410_IRQSUB(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000040:
+                pr_debug("irq: found intc2\n");
+                intc->reg_pending = base + 0x40;
+                intc->reg_mask = base + 0x48;
+                intc->reg_intpnd = base + 0x50;
+                irq_num = 8;
+                irq_start = S3C2416_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x560000a4:
+                pr_debug("irq: found eintc\n");
+                base = (void *)0xfd000000;
+                intc->reg_mask = base + 0xa4;
+                intc->reg_pending = base + 0x08;
+                irq_num = 20;
+                irq_start = S3C2410_IRQ(32);
+                irq_offset = 4;
+                break;
+        default:
+                pr_err("irq: unsupported controller address\n");
+                ret = -EINVAL;
+                goto err;
+        }
+        /* now that all the data is complete, init the irq-domain */
+        s3c24xx_clear_intc(intc);
+        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
+                                             irq_offset, &s3c24xx_irq_ops,
+                                             intc);
+        if (!intc->domain) {
+                pr_err("irq: could not create irq-domain\n");
+                ret = -EINVAL;
+                goto err;
+        }
+        return intc;
+err:
+        kfree(intc);
+        return ERR_PTR(ret);
+}
+/* s3c24xx_init_irq
+ *
+ * Initialise S3C2410 IRQ system
+*/
+static struct s3c_irq_data init_base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_eint[32] = {
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
+static struct s3c_irq_data init_subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+};
+void __init s3c24xx_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+}
+#ifdef CONFIG_CPU_S3C2416
+static struct s3c_irq_data init_s3c2416base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_NONE, },
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_s3c2416subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+static struct s3c_irq_data init_s3c2416_second[32] = {
+        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
+        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
+};
+void __init s3c2416_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+        pr_info("S3C2416: IRQ Support\n");
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
+}
+#endif
+#ifdef CONFIG_CPU_S3C2443
+static struct s3c_irq_data init_s3c2443base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_s3c2443subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+void __init s3c2443_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+        pr_info("S3C2443: IRQ Support\n");
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
+}
+#endif
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 85eefab881af..bb595f15ce36 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -28,17 +28,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/anubis-map.h>
-#include <mach/anubis-irq.h>
-#include <mach/anubis-cpld.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -55,8 +50,9 @@
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include "simtec.h"
+#include "anubis.h"
 #include "common.h"
+#include "simtec.h"
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
@@ -237,7 +233,7 @@ static struct pata_platform_info anubis_ide_platdata = {
 static struct resource anubis_ide0_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
        [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
-        [3] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 static struct platform_device anubis_device_ide0 = {
@@ -254,7 +250,7 @@ static struct platform_device anubis_device_ide0 = {
 static struct resource anubis_ide1_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
        [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 static struct platform_device anubis_device_ide1 = {
@@ -279,7 +275,7 @@ static struct ax_plat_data anubis_asix_platdata = {
 static struct resource anubis_asix_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
-        [1] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
 };
 static struct platform_device anubis_device_asix = {
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b31c4aa724f2..b4bc60c78ebb 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/timer.h>
@@ -34,7 +35,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 526964c19dd8..ca6618081041 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -24,48 +24,41 @@
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <net/ax88796.h>
+#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
 #include <asm/mach-types.h>
-//#include <asm/debug-ll.h>
+#include <mach/fb.h>
-#include <plat/regs-serial.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <linux/platform_data/hwmon-s3c.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/fb.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-#include <linux/serial_8250.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/regs-serial.h>
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
@@ -312,7 +305,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
 static struct resource bast_dm9k_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
                                        | IORESOURCE_IRQ_HIGHLEVEL),
 };
@@ -343,7 +336,7 @@ static struct platform_device bast_device_dm9k = {
 static struct plat_serial8250_port bast_sio_data[] = {
        [0] = {
                .mapbase        = SERIAL_BASE + 0x2f8,
-                .irq            = IRQ_PCSERIAL1,
+                .irq            = BAST_IRQ_PCSERIAL1,
                .flags          = SERIAL_FLAGS,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -351,7 +344,7 @@ static struct plat_serial8250_port bast_sio_data[] = {
        },
        [1] = {
                .mapbase        = SERIAL_BASE + 0x3f8,
-                .irq            = IRQ_PCSERIAL2,
+                .irq            = BAST_IRQ_PCSERIAL2,
                .flags          = SERIAL_FLAGS,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -390,7 +383,7 @@ static struct ax_plat_data bast_asix_platdata = {
 static struct resource bast_asix_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
-        [2] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
 };
 static struct platform_device bast_device_asix = {
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index fb5d3b3b53db..a25e8c5a7b4c 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-s3c2442/mach-gta02.c
- *
 * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
 *
 * Copyright (C) 2006-2009 by Openmoko, Inc.
@@ -23,7 +21,6 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
- *
 */
 #include <linux/kernel.h>
@@ -34,62 +31,59 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/workqueue.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/spi/spi.h>
+#include <linux/input.h>
-#include <linux/spi/s3c24xx.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
 #include <linux/mmc/host.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/backlight.h>
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/pmic.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
 #include <linux/regulator/machine.h>
-#include <linux/mfd/pcf50633/core.h>
+#include <linux/spi/spi.h>
-#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/spi/s3c24xx.h>
-#include <linux/mfd/pcf50633/adc.h>
-#include <linux/mfd/pcf50633/gpio.h>
-#include <linux/mfd/pcf50633/pmic.h>
-#include <linux/mfd/pcf50633/backlight.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <asm/irq.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/fb.h>
-#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <mach/regs-mem.h>
 #include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
-#include <mach/gta02.h>
-#include <plat/regs-serial.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
+#include <plat/devs.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/pm.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/regs-serial.h>
 #include "common.h"
+#include "gta02.h"
 static struct pcf50633 *gta02_pcf;
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 2eb09e27c13c..79bc0830d740 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-h1940.c
+/*
- *
 * Copyright (c) 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
@@ -37,40 +36,36 @@
 #include <linux/mmc/host.h>
 #include <linux/export.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <asm/irq.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
+#include <sound/uda1380.h>
-#include <mach/gpio-fns.h>
-#include <mach/gpio-nrs.h>
-#include <mach/h1940.h>
-#include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <mach/hardware.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/regs-serial.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <sound/uda1380.h>
 #include "common.h"
+#include "h1940.h"
 #define H1940_LATCH             ((void __force __iomem *)0xF8000000)
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index d7a172555238..54e83c1f780c 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -35,9 +35,7 @@
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/fb.h>
@@ -56,6 +54,8 @@
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include "s3c2412-power.h"
 static struct map_desc jive_iodesc[] __initdata = {
 };
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2db09ade9b50..2865e5919f2c 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -40,7 +40,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ba0f5b5ec19e..ae2cbdf3e3ca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-osiris.c
+/*
- *
 * Copyright (c) 2005-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -22,25 +21,16 @@
 #include <linux/clk.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/i2c/tps65010.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/osiris-map.h>
-#include <mach/osiris-cpld.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <plat/cpu-freq.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
-#include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -49,12 +39,20 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 #include "common.h"
+#include "osiris.h"
+#include "regs-mem.h"
 /* onboard perihperal map */
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index e0fdae93aa7b..40a47d6c6a85 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-otom.c
+/*
 *
 * Copyright (c) 2004 Nex Vision
 *   Guillaume GOURAT <guillaume.gourat@nexvision.fr>
@@ -6,7 +6,6 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
- *
 */
 #include <linux/kernel.h>
@@ -19,26 +18,25 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/otom-map.h>
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+#include <plat/s3c2410.h>
 #include "common.h"
+#include "otom.h"
 static struct map_desc otom11_iodesc[] __initdata = {
  /* Device area */
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index e14ec7105a6d..1f9ba2ae5288 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
+/*
- *
 * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
 * Copyright (c) 2007-2010 Vasily Khoruzhick
 *
@@ -37,31 +36,31 @@
 #include <linux/mmc/host.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <sound/uda1380.h>
+#include <mach/fb.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/h1940.h>
-#include <mach/fb.h>
 #include <plat/clock.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-iic.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/regs-iic.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/regs-serial.h>
-#include <sound/uda1380.h>
 #include "common.h"
+#include "h1940.h"
 #define LCD_PWM_PERIOD 192960
 #define LCD_PWM_DUTY 127353
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index d00caa8de922..f20418a2fb1b 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -31,27 +31,27 @@
 #include <linux/mtd/partitions.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
+#include <mach/fb.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/h1940.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <mach/fb.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/regs-serial.h>
 #include "common.h"
+#include "h1940.h"
 static struct map_desc rx3715_iodesc[] __initdata = {
        /* dump ISA space somewhere unused */
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 69f356e83790..86d7847c9d45 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -37,7 +37,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index fe160c7f4b0a..ebb2e61f3d07 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -39,7 +39,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/regs-s3c2443-clock.h>
-#include <mach/idle.h>
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -251,7 +250,7 @@ MACHINE_START(SMDK2416, "SMDK2416")
        /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
        .atag_offset    = 0x100,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2416_init_irq,
        .map_io         = smdk2416_map_io,
        .init_machine   = smdk2416_machine_init,
        .init_time      = s3c24xx_timer_init,
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index a8fdafedc4c1..08cc38c8a4ae 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 7830d7004306..fc65d74d3c73 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -141,7 +140,7 @@ MACHINE_START(SMDK2443, "SMDK2443")
        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
        .atag_offset    = 0x100,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2443_init_irq,
        .map_io         = smdk2443_map_io,
        .init_machine   = smdk2443_machine_init,
        .init_time      = s3c24xx_timer_init,
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index dda21a01e3cc..ec42d1e4e465 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
+/*
- *
 * Copyright (c) 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
@@ -32,27 +31,25 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/vr1000-map.h>
-#include <mach/vr1000-irq.h>
-#include <mach/vr1000-cpld.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/devs.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/regs-serial.h>
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
+#include "vr1000.h"
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 static struct plat_serial8250_port serial_platform_data[] = {
        [0] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(0),
-                .irq            = IRQ_VR1000_SERIAL + 0,
+                .irq            = VR1000_IRQ_SERIAL + 0,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [1] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(1),
-                .irq            = IRQ_VR1000_SERIAL + 1,
+                .irq            = VR1000_IRQ_SERIAL + 1,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [2] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(2),
-                .irq            = IRQ_VR1000_SERIAL + 2,
+                .irq            = VR1000_IRQ_SERIAL + 2,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [3] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(3),
-                .irq            = IRQ_VR1000_SERIAL + 3,
+                .irq            = VR1000_IRQ_SERIAL + 3,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -189,14 +186,14 @@ static struct platform_device serial_device = {
 static struct resource vr1000_dm9k0_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \
                                                | IORESOURCE_IRQ_HIGHLEVEL),
 };
 static struct resource vr1000_dm9k1_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \
                                                | IORESOURCE_IRQ_HIGHLEVEL),
 };
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 7fe7d4f60419..3e2bfddc9df1 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -36,7 +36,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/osiris.h
index 17380f848428..b8d56074abac 100644
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c24xx/osiris.h
@@ -1,9 +1,9 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
+/*
- *
 * Copyright 2005 Simtec Electronics
 *      http://www.simtec.co.uk/products/
 *      Ben Dooks <ben@simtec.co.uk>
 *
+ * OSIRIS - CPLD control constants
 * OSIRIS - Memory map definitions
 *
 * This program is free software; you can redistribute it and/or modify
@@ -11,10 +11,21 @@
 * published by the Free Software Foundation.
 */
-/* needs arch/map.h including with this */
+#ifndef __MACH_S3C24XX_OSIRIS_H
+#define __MACH_S3C24XX_OSIRIS_H __FILE__
+/* CTRL0 - NAND WP control */
+#define OSIRIS_CTRL0_NANDSEL            (0x3)
+#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
+#define OSIRIS_CTRL0_PCMCIA             (1<<4)
+#define OSIRIS_CTRL0_FIX8               (1<<5)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
+#define OSIRIS_CTRL1_FIX8               (1<<0)
-#ifndef __ASM_ARCH_OSIRISMAP_H
+#define OSIRIS_ID_REVMASK               (0x7)
-#define __ASM_ARCH_OSIRISMAP_H
 /* start peripherals off after the S3C2410 */
@@ -39,4 +50,4 @@
 #define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
 #define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
-#endif /* __ASM_ARCH_OSIRISMAP_H */
+#endif /* __MACH_S3C24XX_OSIRIS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/otom.h
index f9277a52c145..321b7be1c0f7 100644
--- a/arch/arm/mach-s3c24xx/include/mach/otom-map.h
+++ b/arch/arm/mach-s3c24xx/otom.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/otom-map.h
+/*
- *
 * (c) 2005 Guillaume GOURAT / NexVision
 *          guillaume.gourat@nexvision.fr
 *
@@ -10,21 +9,20 @@
 * published by the Free Software Foundation.
 */
-/* needs arch/map.h including with this */
+/*
+ * ok, we've used up to 0x01300000, now we need to find space for the
-/* ok, we've used up to 0x01300000, now we need to find space for the
 * peripherals that live in the nGCS[x] areas, which are quite numerous
 * in their space.
 */
-#ifndef __ASM_ARCH_OTOMMAP_H
+#ifndef __MACH_S3C24XX_OTOM_H
-#define __ASM_ARCH_OTOMMAP_H
+#define __MACH_S3C24XX_OTOM_H __FILE__
-#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
+#define OTOM_PA_CS8900A_BASE    (S3C2410_CS3 + 0x01000000)      /* nGCS3 +0x01000000 */
-#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
+#define OTOM_VA_CS8900A_BASE    S3C2410_ADDR(0x04000000)        /* 0xF4000000 */
 /* physical offset addresses for the peripherals */
-#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
+#define OTOM_PA_FLASH0_BASE     (S3C2410_CS0)
-#endif /* __ASM_ARCH_OTOMMAP_H */
+#endif /* __MACH_S3C24XX_OTOM_H */
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index e0b3b347da82..dcf3420a3271 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/pll.c
+/*
- *
 * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -82,7 +81,6 @@ static int __init s3c2410_pll_init(void)
        return subsys_interface_register(&s3c2410_plls_interface);
 }
 arch_initcall(s3c2410_pll_init);
 static struct subsys_interface s3c2410a_plls_interface = {
@@ -95,5 +93,4 @@ static int __init s3c2410a_pll_init(void)
 {
        return subsys_interface_register(&s3c2410a_plls_interface);
 }
 arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 551fb433be87..673781758319 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+/*
- *
 * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -83,7 +82,6 @@ static int __init s3c2440_pll_12mhz(void)
        return subsys_interface_register(&s3c2440_plls12_interface);
 }
 arch_initcall(s3c2440_pll_12mhz);
 static struct subsys_interface s3c2442_plls12_interface = {
@@ -97,5 +95,4 @@ static int __init s3c2442_pll_12mhz(void)
        return subsys_interface_register(&s3c2442_plls12_interface);
 }
 arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index 3f15bcf64290..debfa106289b 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -111,7 +110,6 @@ static int __init s3c2440_pll_16934400(void)
 {
        return subsys_interface_register(&s3c2440_plls169344_interface);
 }
 arch_initcall(s3c2440_pll_16934400);
 static struct subsys_interface s3c2442_plls169344_interface = {
@@ -124,5 +122,4 @@ static int __init s3c2442_pll_16934400(void)
 {
        return subsys_interface_register(&s3c2442_plls169344_interface);
 }
 arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S
index c93bf2db9f4d..6183a688012b 100644
--- a/arch/arm/mach-s3c24xx/pm-h1940.S
+++ b/arch/arm/mach-s3c24xx/pm-h1940.S
@@ -30,4 +30,4 @@
 h1940_pm_return:
        mov     r0, #S3C2410_PA_GPIO
-        ldr     pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
+        ldr     pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 949ae05e07c5..2d82c4f116cd 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -29,16 +29,16 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/h1940.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "h1940.h"
 static void s3c2410_pm_prepare(void)
 {
        /* ensure at least GSTATUS3 has the resume address */
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index c60f67a75aff..668a78a8b195 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -21,19 +21,19 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <asm/cacheflush.h>
 #include <asm/irq.h>
-#include <mach/regs-power.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/s3c2412.h>
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
 extern void s3c2412_sleep_enter(void);
 static int s3c2412_cpu_suspend(unsigned long arg)
@@ -48,7 +48,8 @@ static int s3c2412_cpu_suspend(unsigned long arg)
        s3c2412_sleep_enter();
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 static void s3c2412_pm_prepare(void)
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1bd4817b8eb8..44923895f558 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -16,12 +16,13 @@
 #include <asm/cacheflush.h>
-#include <mach/regs-power.h>
 #include <mach/regs-s3c2443-clock.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "s3c2412-power.h"
 extern void s3c2412_sleep_enter(void);
 static int s3c2416_cpu_suspend(unsigned long arg)
@@ -34,7 +35,8 @@ static int s3c2416_cpu_suspend(unsigned long arg)
        s3c2412_sleep_enter();
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 static void s3c2416_pm_prepare(void)
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 724755f0b0f5..caa5b7211380 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -38,7 +38,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-irq.h>
 #include <asm/mach/time.h>
@@ -46,6 +45,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
+#include "regs-mem.h"
 #define PFX "s3c24xx-pm: "
 static struct sleep_save core_save[] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h
index 98fd4a05587c..98fd4a05587c 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/regs-dsc.h
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h
new file mode 100644
index 000000000000..86b1258368c2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/regs-mem.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
+#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
+#define S3C2410_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+#define S3C2410_BWSCON                  S3C2410_MEMREG(0x00)
+#define S3C2410_BANKCON0                S3C2410_MEMREG(0x04)
+#define S3C2410_BANKCON1                S3C2410_MEMREG(0x08)
+#define S3C2410_BANKCON2                S3C2410_MEMREG(0x0C)
+#define S3C2410_BANKCON3                S3C2410_MEMREG(0x10)
+#define S3C2410_BANKCON4                S3C2410_MEMREG(0x14)
+#define S3C2410_BANKCON5                S3C2410_MEMREG(0x18)
+#define S3C2410_BANKCON6                S3C2410_MEMREG(0x1C)
+#define S3C2410_BANKCON7                S3C2410_MEMREG(0x20)
+#define S3C2410_REFRESH                 S3C2410_MEMREG(0x24)
+#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x28)
+#define S3C2410_BWSCON_ST1              (1 << 7)
+#define S3C2410_BWSCON_ST2              (1 << 11)
+#define S3C2410_BWSCON_ST3              (1 << 15)
+#define S3C2410_BWSCON_ST4              (1 << 19)
+#define S3C2410_BWSCON_ST5              (1 << 23)
+#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
+#define S3C2410_BWSCON_WS               (1 << 2)
+#define S3C2410_BANKCON_PMC16           (0x3)
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
+#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
+#define S3C2410_REFRESH_SELF            (1 << 22)
+#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
+#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index a3c5cb086ee2..9ebef95da721 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -49,6 +49,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 /* Initial IO mappings */
 static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -182,8 +184,8 @@ int __init s3c2410_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
        return device_register(&s3c2410_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c24xx/s3c2412-power.h
new file mode 100644
index 000000000000..1b02c5ddb31b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412-power.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
+#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
+#define S3C24XX_PWRREG(x)                       ((x) + S3C24XX_VA_CLKPWR)
+#define S3C2412_PWRMODECON                      S3C24XX_PWRREG(0x20)
+#define S3C2412_PWRCFG                          S3C24XX_PWRREG(0x24)
+#define S3C2412_INFORM0                         S3C24XX_PWRREG(0x70)
+#define S3C2412_INFORM1                         S3C24XX_PWRREG(0x74)
+#define S3C2412_INFORM2                         S3C24XX_PWRREG(0x78)
+#define S3C2412_INFORM3                         S3C24XX_PWRREG(0x7C)
+#define S3C2412_PWRCFG_BATF_IRQ                 (1 << 0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2 << 0)
+#define S3C2412_PWRCFG_BATF_SLEEP               (3 << 0)
+#define S3C2412_PWRCFG_BATF_MASK                (3 << 0)
+#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3 << 6)
+#define S3C2412_PWRCFG_RTC_MASKIRQ              (1 << 8)
+#define S3C2412_PWRCFG_NAND_NORST               (1 << 9)
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 6c5f4031ff0c..0d592159a5c3 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2412/s3c2412.c
+/*
- *
 * Copyright (c) 2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -28,28 +27,31 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
-#include <plat/cpu-freq.h>
+#include <mach/hardware.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
-#include <plat/regs-spi.h>
-#include <mach/regs-s3c2412.h>
-#include <plat/s3c2412.h>
+#include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/pm.h>
-#include <plat/pll.h>
 #include <plat/nand-core.h>
+#include <plat/pll.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-spi.h>
+#include <plat/s3c2412.h>
+#include "common.h"
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
+#define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
+#define S3C2412_SWRST_RESET             (0x533C2412)
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -244,8 +246,8 @@ int __init s3c2412_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2412_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
        return device_register(&s3c2412_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h
new file mode 100644
index 000000000000..548ced42cbb7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
+#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
+#define S3C2412_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+#define S3C2412_EBIREG(x)               (S3C2412_VA_EBI + (x))
+#define S3C2412_SSMCREG(x)              (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o)              (S3C2412_SSMCREG((x * 0x20) + (o)))
+#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
+#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x4)
+#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x0)
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 77ee0b732237..e30476db0295 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -63,6 +63,8 @@
 #include <plat/rtc-core.h>
 #include <plat/spi-core.h>
+#include "common.h"
 static struct map_desc s3c2416_iodesc[] __initdata = {
        IODESC_ENT(WATCHDOG),
        IODESC_ENT(CLKPWR),
@@ -105,9 +107,9 @@ int __init s3c2416_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2416_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        register_syscore_ops(&s3c2416_irq_syscore_ops);
+#endif
        return device_register(&s3c2416_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 2b3dddb49af7..559e394e8989 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -40,6 +40,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 static struct device s3c2440_dev = {
        .bus            = &s3c2440_subsys,
 };
@@ -57,9 +59,9 @@ int __init s3c2440_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        /* register our system device for everything else */
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 22cb7c94a8c8..f732826c2359 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -51,6 +51,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 /* S3C2442 extended clock support */
 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -172,9 +174,9 @@ int __init s3c2442_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        return device_register(&s3c2442_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index b0b60a1154d6..ad2671baa910 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -36,7 +36,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
@@ -48,6 +47,8 @@
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
+#include "regs-dsc.h"
 static struct map_desc s3c244x_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
        IODESC_ENT(TIMER),
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index fd0ef05763a9..67cb5120dfeb 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -17,16 +17,13 @@
 #include <linux/device.h>
 #include <linux/io.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include <plat/devs.h>
+#include "bast.h"
 #include "simtec.h"
 /* platform ops for audio */
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index 029744fcaacb..8884bffa619a 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -27,9 +27,8 @@
 #include <asm/mach/irq.h>
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-cpld.h>
+#include "bast.h"
 #include "simtec.h"
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f93171297..38a2f1fdebab 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
@@ -28,12 +28,13 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <asm/mach-types.h>
 #include <plat/pm.h>
+#include "regs-mem.h"
 #define COPYRIGHT ", Copyright 2005 Simtec Electronics"
 /* pm_simtec_init
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index ddf7a3c743ac..2ed2e32430dc 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -28,15 +28,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/devs.h>
+#include "bast.h"
 #include "simtec.h"
 /* control power and monitor over-current events on various Simtec
@@ -79,7 +77,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
        int ret;
        if (on) {
-                ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
+                ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
                                  IRQF_DISABLED | IRQF_TRIGGER_RISING |
                                   IRQF_TRIGGER_FALLING,
                                  "USB Over-current", info);
@@ -87,7 +85,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
                        printk(KERN_ERR "failed to request usb oc irq\n");
                }
        } else {
-                free_irq(IRQ_USBOC, info);
+                free_irq(BAST_IRQ_USBOC, info);
        }
 }
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..dd47c8fa07fa 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -31,9 +31,10 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
+#include "regs-mem.h"
        /* s3c2410_cpu_suspend
         *
         * put the cpu into sleep mode
@@ -45,9 +46,9 @@ ENTRY(s3c2410_cpu_suspend)
        ldr     r4, =S3C2410_REFRESH
        ldr     r5, =S3C24XX_MISCCR
        ldr     r6, =S3C2410_CLKCON
-        ldr     r7, [ r4 ]              @ get REFRESH (and ensure in TLB)
+        ldr     r7, [r4]                @ get REFRESH (and ensure in TLB)
-        ldr     r8, [ r5 ]              @ get MISCCR (and ensure in TLB)
+        ldr     r8, [r5]                @ get MISCCR (and ensure in TLB)
-        ldr     r9, [ r6 ]              @ get CLKCON (and ensure in TLB)
+        ldr     r9, [r6]                @ get CLKCON (and ensure in TLB)
        orr     r7, r7, #S3C2410_REFRESH_SELF   @ SDRAM sleep command
        orr     r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
@@ -61,8 +62,8 @@ ENTRY(s3c2410_cpu_suspend)
        @@ align next bit of code to cache line
        .align  5
 s3c2410_do_sleep:
-        streq   r7, [ r4 ]                      @ SDRAM sleep command
+        streq   r7, [r4]                        @ SDRAM sleep command
-        streq   r8, [ r5 ]                      @ SDRAM power-down config
+        streq   r8, [r5]                        @ SDRAM power-down config
-        streq   r9, [ r6 ]                      @ CPU sleep
+        streq   r9, [r6]                        @ CPU sleep
 1:      beq     1b
        mov     pc, r14
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
index c82418ed714d..5adaceb7da13 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
@@ -57,12 +57,12 @@ s3c2412_sleep_enter1:
         * retry, as simply returning causes the system to lock.
        */
-        ldrne   r9, [ r1 ]
+        ldrne   r9, [r1]
-        strne   r9, [ r1 ]
+        strne   r9, [r1]
-        ldrne   r9, [ r2 ]
+        ldrne   r9, [r2]
-        strne   r9, [ r2 ]
+        strne   r9, [r2]
-        ldrne   r9, [ r3 ]
+        ldrne   r9, [r3]
-        strne   r9, [ r3 ]
+        strne   r9, [r3]
        bne     s3c2412_sleep_enter1
        mov     pc, r14
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index c56612569b40..7f378b662da6 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -31,7 +31,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c24xx/vr1000.h
new file mode 100644
index 000000000000..7fcd2c2f183c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/vr1000.h
@@ -0,0 +1,118 @@
+/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ * Machine VR1000 - IRQ Number definitions
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_VR1000_H
+#define __MACH_S3C24XX_VR1000_H __FILE__
+#define VR1000_CPLD_CTRL2_RAMWEN        (0x04)  /* SRAM Write Enable */
+/* irq numbers to onboard peripherals */
+#define VR1000_IRQ_USBOC                IRQ_EINT19
+#define VR1000_IRQ_IDE0                 IRQ_EINT16
+#define VR1000_IRQ_IDE1                 IRQ_EINT17
+#define VR1000_IRQ_SERIAL               IRQ_EINT12
+#define VR1000_IRQ_DM9000A              IRQ_EINT10
+#define VR1000_IRQ_DM9000N              IRQ_EINT9
+#define VR1000_IRQ_SMALERT              IRQ_EINT8
+/* map */
+#define VR1000_IOADDR(x)                (S3C2410_ADDR((x) + 0x01300000))
+/* we put the CPLD registers next, to get them out of the way */
+#define VR1000_VA_CTRL1                 VR1000_IOADDR(0x00000000) /* 0x01300000 */
+#define VR1000_PA_CTRL1                 (S3C2410_CS5 | 0x7800000)
+#define VR1000_VA_CTRL2                 VR1000_IOADDR(0x00100000) /* 0x01400000 */
+#define VR1000_PA_CTRL2                 (S3C2410_CS1 | 0x6000000)
+#define VR1000_VA_CTRL3                 VR1000_IOADDR(0x00200000) /* 0x01500000 */
+#define VR1000_PA_CTRL3                 (S3C2410_CS1 | 0x6800000)
+#define VR1000_VA_CTRL4                 VR1000_IOADDR(0x00300000) /* 0x01600000 */
+#define VR1000_PA_CTRL4                 (S3C2410_CS1 | 0x7000000)
+/* next, we have the PC104 ISA interrupt registers */
+#define VR1000_PA_PC104_IRQREQ          (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ          VR1000_IOADDR(0x00400000)
+#define VR1000_PA_PC104_IRQRAW          (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW          VR1000_IOADDR(0x00500000)
+#define VR1000_PA_PC104_IRQMASK         (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK         VR1000_IOADDR(0x00600000)
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+#define VR1000_VA_MULTISPACE    (0xE0000000)
+#define VR1000_VA_ISAIO         (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM        (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI        (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX     (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC        (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX     (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET       (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000        (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO       (VR1000_VA_MULTISPACE + 0x02600000)
+/* physical offset addresses for the peripherals */
+#define VR1000_PA_IDEPRI        (0x02000000)
+#define VR1000_PA_IDEPRIAUX     (0x02800000)
+#define VR1000_PA_IDESEC        (0x03000000)
+#define VR1000_PA_IDESECAUX     (0x03800000)
+#define VR1000_PA_DM9000        (0x05000000)
+#define VR1000_PA_SERIAL        (0x11800000)
+#define VR1000_VA_SERIAL        (VR1000_IOADDR(0x00700000))
+/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
+#define VR1000_PA_SRAM          (S3C2410_CS1 | 0x05000000)
+/* some configurations for the peripherals */
+#define VR1000_DM9000_CS        VR1000_VAM_CS4
+#endif /* __MACH_S3C24XX_VR1000_H */
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 803711e283b2..8499415be9cd 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu.h>
@@ -33,6 +32,8 @@
 #include <plat/clock-clksrc.h>
 #include <plat/pll.h>
+#include "regs-sys.h"
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
 * ext_xtal_mux for want of an actual name from the manual.
 */
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
index acb197ccf3f7..ead5fab0dbb5 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -20,8 +20,8 @@
 #include <mach/map.h>
-#include <mach/regs-sys.h>
+#include "regs-sys.h"
-#include <mach/regs-syscon-power.h>
+#include "regs-syscon-power.h"
 static int s3c64xx_enter_idle(struct cpuidle_device *dev,
                              struct cpuidle_driver *drv,
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/crag6410.h
index 4c3c9994fc2c..4c3c9994fc2c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/crag6410.h
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index f2a7a1725596..ec29b35f25c0 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -28,10 +28,10 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
-#include <mach/regs-sys.h>
 #include <asm/hardware/pl080.h>
+#include "regs-sys.h"
 /* dma channel state information */
 struct s3c64xx_dmac {
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
deleted file mode 100644
index b91e02093289..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX system register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_SYS_H
-#define __PLAT_REGS_SYS_H __FILE__
-#define S3C_SYSREG(x)           (S3C_VA_SYS + (x))
-#define S3C64XX_AHB_CON0        S3C_SYSREG(0x100)
-#define S3C64XX_AHB_CON1        S3C_SYSREG(0x104)
-#define S3C64XX_AHB_CON2        S3C_SYSREG(0x108)
-#define S3C64XX_SDMA_SEL        S3C_SYSREG(0x110)
-#define S3C64XX_OTHERS          S3C_SYSREG(0x900)
-#define S3C64XX_OTHERS_USBMASK  (1 << 16)
-#define S3C64XX_OTHERS_SYNCMUXSEL       (1 << 6)
-#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index afeae0b5bb28..728eef3296b2 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,9 +49,9 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
 #include "common.h"
+#include "regs-modem.h"
 /* DM9000 */
 #define ANW6410_PA_DM9000       (0x18000000)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 755c0bb119f4..bf3d1c09b085 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/spi-s3c64xx.h>
-#include <mach/crag6410.h>
+#include "crag6410.h"
 static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
        .line = S3C64XX_GPC(3),
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 5b6adc7f1d39..1acf02bace57 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -49,12 +49,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/crag6410.h>
-#include <mach/regs-gpio-memport.h>
 #include <plat/regs-serial.h>
 #include <plat/fb.h>
@@ -71,6 +66,10 @@
 #include <plat/pm.h>
 #include "common.h"
+#include "crag6410.h"
+#include "regs-gpio-memport.h"
+#include "regs-modem.h"
+#include "regs-sys.h"
 /* serial port setup */
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index e173e6e98228..4b41fcdaa7b6 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -30,8 +30,6 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/regs-srom.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
@@ -45,6 +43,8 @@
 #include <video/samsung_fimd.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 4d0d47a66930..fa12bd21ad82 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -31,8 +31,6 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/regs-srom.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
@@ -46,6 +44,8 @@
 #include <video/samsung_fimd.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index c6d7390939ae..fc3e9b32e26f 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -25,7 +25,6 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -41,6 +40,7 @@
 #include <video/platform_lcd.h>
 #include "common.h"
+#include "regs-modem.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 1663d10ba02a..ba7544e2d04d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -56,10 +56,7 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <mach/regs-modem.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-sys.h>
-#include <mach/regs-srom.h>
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
@@ -74,6 +71,9 @@
 #include <plat/backlight.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
+#include "regs-sys.h"
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index d2e1a16690bd..6a1f91fea678 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -26,12 +26,13 @@
 #include <plat/pm.h>
 #include <plat/wakeup-mask.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-syscon-power.h>
-#include <mach/regs-gpio-memport.h>
+#include "regs-gpio-memport.h"
-#include <mach/regs-modem.h>
+#include "regs-modem.h"
+#include "regs-sys.h"
+#include "regs-syscon-power.h"
 struct s3c64xx_pm_domain {
        char *const name;
@@ -296,7 +297,8 @@ static int s3c64xx_cpu_suspend(unsigned long arg)
        /* we should never get past here */
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 /* mapping of interrupts to parts of the wakeup mask */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/regs-gpio-memport.h
index 82342f6fd27d..b927593019f5 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
+++ b/arch/arm/mach-s3c64xx/regs-gpio-memport.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
@@ -8,8 +7,8 @@
 * S3C64XX - GPIO memory port register definitions
 */
-#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#ifndef __MACH_S3C64XX_REGS_GPIO_MEMPORT_H
-#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+#define __MACH_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
 #define S3C64XX_MEM0CONSTOP     S3C64XX_GPIOREG(0x1B0)
 #define S3C64XX_MEM1CONSTOP     S3C64XX_GPIOREG(0x1B4)
@@ -21,5 +20,5 @@
 #define S3C64XX_MEM0DRVCON      S3C64XX_GPIOREG(0x1D0)
 #define S3C64XX_MEM1DRVCON      S3C64XX_GPIOREG(0x1D4)
-#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+#endif /* __MACH_S3C64XX_REGS_GPIO_MEMPORT_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/regs-modem.h
index 49f7759dedfa..073cdd3a03be 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
+++ b/arch/arm/mach-s3c64xx/regs-modem.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
@@ -12,10 +11,10 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#ifndef __MACH_S3C64XX_REGS_MODEM_H
-#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+#define __MACH_S3C64XX_REGS_MODEM_H __FILE__
-#define S3C64XX_MODEMREG(x)     (S3C64XX_VA_MODEM + (x))
+#define S3C64XX_MODEMREG(x)                     (S3C64XX_VA_MODEM + (x))
 #define S3C64XX_MODEM_INT2AP                    S3C64XX_MODEMREG(0x0)
 #define S3C64XX_MODEM_INT2MODEM                 S3C64XX_MODEMREG(0x4)
@@ -28,4 +27,4 @@
 #define MIFPCON_INT2M_LEVEL                     (1 << 4)
 #define MIFPCON_LCD_BYPASS                      (1 << 3)
-#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
+#endif /* __MACH_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/regs-srom.h
index 756731b36297..d56f3386eb00 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
+++ b/arch/arm/mach-s3c64xx/regs-srom.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
+/*
- *
 * Copyright 2009 Andy Green <andy@warmcat.com>
 *
 * S3C64XX SROM definitions
@@ -9,8 +8,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_REGS_SROM_H
+#ifndef __MACH_S3C64XX_REGS_SROM_H
-#define __PLAT_REGS_SROM_H __FILE__
+#define __MACH_S3C64XX_REGS_SROM_H __FILE__
 #define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
@@ -29,7 +28,7 @@
 #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
 #define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
 #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
-#define S3C64XX_SROM_BW__CS_MASK 0xf
+#define S3C64XX_SROM_BW__CS_MASK                0xf
 #define S3C64XX_SROM_BW__NCS0__SHIFT    0
 #define S3C64XX_SROM_BW__NCS1__SHIFT    4
@@ -56,4 +55,4 @@
 #define S3C64XX_SROM_BCX__TACS__SHIFT   28
 #define S3C64XX_SROM_BCX__TACS__MASK    0xf
-#endif /* _PLAT_REGS_SROM_H */
+#endif /* __MACH_S3C64XX_REGS_SROM_H */
diff --git a/arch/arm/mach-s3c64xx/regs-sys.h b/arch/arm/mach-s3c64xx/regs-sys.h
new file mode 100644
index 000000000000..8c411fbb0cd9
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/regs-sys.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX system register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C64XX_REGS_SYS_H
+#define __MACH_S3C64XX_REGS_SYS_H __FILE__
+#define S3C_SYSREG(x)                   (S3C_VA_SYS + (x))
+#define S3C64XX_AHB_CON0                S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1                S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2                S3C_SYSREG(0x108)
+#define S3C64XX_SDMA_SEL                S3C_SYSREG(0x110)
+#define S3C64XX_OTHERS                  S3C_SYSREG(0x900)
+#define S3C64XX_OTHERS_USBMASK          (1 << 16)
+#define S3C64XX_OTHERS_SYNCMUXSEL       (1 << 6)
+#endif /* __MACH_S3C64XX_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/regs-syscon-power.h
index 270d96ac9705..6e16b3404da9 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
+++ b/arch/arm/mach-s3c64xx/regs-syscon-power.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
@@ -12,8 +11,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
-#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
 #define S3C64XX_PWR_CFG                         S3C_SYSREG(0x804)
@@ -113,4 +112,4 @@
 #define S3C64XX_INFORM2                         S3C_SYSREG(0xA08)
 #define S3C64XX_INFORM3                         S3C_SYSREG(0xA0C)
-#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
+#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e02d7db..c8174d95339b 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -15,11 +15,12 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <plat/cpu.h>
 #include <plat/regs-usb-hsotg-phy.h>
 #include <plat/usb-phy.h>
+#include "regs-sys.h"
 static int s3c_usb_otgphy_init(struct platform_device *pdev)
 {
        struct clk *xusbxti;
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 5112371079d0..3537815247f1 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/s5p64x0-clock.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -32,6 +31,7 @@
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include "clock.h"
 #include "common.h"
 static u32 epll_div[][5] = {
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 154dea702d70..af384ddd2dcf 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/s5p64x0-clock.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -32,6 +31,7 @@
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include "clock.h"
 #include "common.h"
 static struct clksrc_clk clk_mout_dpll = {
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/clock.h
index 0ef47d1b7670..28b8e3c6bd24 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/clock.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+/*
- *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
@@ -10,8 +9,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_CLOCK_H
+#ifndef __MACH_S5P64X0_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
+#define __MACH_S5P64X0_CLOCK_H __FILE__
 #include <linux/clk.h>
@@ -36,4 +35,4 @@ extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
 extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
-#endif /* __ASM_ARCH_CLOCK_H */
+#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
deleted file mode 100644
index 700dac6c43f3..000000000000
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/gpiolib.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-/*
- * S5P6440 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * F    2       2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    8       2Bit    Yes     8
- * R    15      4Bit[2] Yes     8
- *
- * S5P6450 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    8       4Bit    Yes     None
- * F    2       2Bit    Yes     None
- * G    14      4Bit[2] Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    5       4Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    11      2Bit    Yes     8
- * Q    14      2Bit    Yes     None
- * R    15      4Bit[2] Yes     None
- * S    8       2Bit    Yes     None
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
-                                             unsigned int offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long flags;
-        switch (offset) {
-        case 6:
-                offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                offset -= 7;
-                break;
-        }
-        s3c_gpio_lock(ourchip, flags);
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
-                                              unsigned int offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned long flags;
-        unsigned con_offset  = offset;
-        switch (con_offset) {
-        case 6:
-                con_offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                con_offset -= 7;
-                break;
-        }
-        s3c_gpio_lock(ourchip, flags);
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-        dat = __raw_readl(base + GPIODAT_OFF);
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
-                                   unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift;
-        u32 con;
-        switch (off) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                shift = (off & 7) * 4;
-                reg -= 4;
-                break;
-        case 6:
-                shift = ((off + 1) & 7) * 4;
-                reg -= 4;
-        default:
-                shift = ((off + 1) & 7) * 4;
-                break;
-        }
-        if (s3c_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-        return 0;
-}
-static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
-        {
-                .cfg_eint       = 0,
-        }, {
-                .cfg_eint       = 7,
-        }, {
-                .cfg_eint       = 3,
-                .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
-        }, {
-                .cfg_eint       = 0,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        }, {
-                .cfg_eint       = 2,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        }, {
-                .cfg_eint       = 3,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
-        {
-                .base   = S5P64X0_GPA_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPA(0),
-                        .ngpio  = S5P6440_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .base   = S5P64X0_GPB_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPB(0),
-                        .ngpio  = S5P6440_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .base   = S5P64X0_GPC_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPC(0),
-                        .ngpio  = S5P6440_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P64X0_GPG_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPG(0),
-                        .ngpio  = S5P6440_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
-        {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPH(0),
-                        .ngpio  = S5P6440_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[2],
-                .chip   = {
-                        .base   = S5P6440_GPR(0),
-                        .ngpio  = S5P6440_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPF(0),
-                        .ngpio  = S5P6440_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6440_GPI(0),
-                        .ngpio  = S5P6440_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6440_GPJ(0),
-                        .ngpio  = S5P6440_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPN(0),
-                        .ngpio  = S5P6440_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPP(0),
-                        .ngpio  = S5P6440_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
-        {
-                .base   = S5P64X0_GPA_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPA(0),
-                        .ngpio  = S5P6450_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .base   = S5P64X0_GPB_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPB(0),
-                        .ngpio  = S5P6450_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .base   = S5P64X0_GPC_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPC(0),
-                        .ngpio  = S5P6450_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P6450_GPD_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPD(0),
-                        .ngpio  = S5P6450_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .base   = S5P6450_GPK_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPK(0),
-                        .ngpio  = S5P6450_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
-        {
-                .base   = S5P64X0_GPG_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPG(0),
-                        .ngpio  = S5P6450_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPH(0),
-                        .ngpio  = S5P6450_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[2],
-                .chip   = {
-                        .base   = S5P6450_GPR(0),
-                        .ngpio  = S5P6450_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPF(0),
-                        .ngpio  = S5P6450_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6450_GPI(0),
-                        .ngpio  = S5P6450_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6450_GPJ(0),
-                        .ngpio  = S5P6450_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPN(0),
-                        .ngpio  = S5P6450_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPP(0),
-                        .ngpio  = S5P6450_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .base   = S5P6450_GPQ_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPQ(0),
-                        .ngpio  = S5P6450_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        }, {
-                .base   = S5P6450_GPS_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPS(0),
-                        .ngpio  = S5P6450_GPIO_S_NR,
-                        .label  = "GPS",
-                },
-        },
-};
-void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chipcfg++) {
-                if (!chipcfg->set_config)
-                        chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
-                if (!chipcfg->get_config)
-                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
-                if (!chipcfg->set_pull)
-                        chipcfg->set_pull       = s3c_gpio_setpull_updown;
-                if (!chipcfg->get_pull)
-                        chipcfg->get_pull       = s3c_gpio_getpull_updown;
-        }
-}
-static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
-                                                int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
-                chip->chip.direction_output =
-                                        s5p64x0_gpiolib_rbank_4bit2_output;
-                s3c_gpiolib_add(chip);
-        }
-}
-static int __init s5p64x0_gpiolib_init(void)
-{
-        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
-                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
-        if (soc_is_s5p6450()) {
-                samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
-                                        ARRAY_SIZE(s5p6450_gpio_2bit));
-                samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
-                                        ARRAY_SIZE(s5p6450_gpio_4bit));
-                samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
-                                        ARRAY_SIZE(s5p6450_gpio_4bit2));
-                s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
-                                        ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
-        } else {
-                samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
-                                        ARRAY_SIZE(s5p6440_gpio_2bit));
-                samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
-                                        ARRAY_SIZE(s5p6440_gpio_4bit));
-                samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
-                                        ARRAY_SIZE(s5p6440_gpio_4bit2));
-                s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
-                                        ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
-        }
-        return 0;
-}
-core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
index 887d25209e8e..1e5bb4ea200d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/i2c.h
+++ b/arch/arm/mach-s5p64x0/i2c.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
+/*
- *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 1608faf870ff..19e0d64d78c5 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -116,33 +116,6 @@ static inline void flush(void)
                *((volatile unsigned int __force *)(ad)) = (d); \
        } while (0)
-/*
- * CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
- */
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-#define WDOG_COUNT (0xff00)
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
@@ -192,7 +165,6 @@ static void arch_decomp_setup(void)
         */
        arch_detect_cpu();
-        arch_decomp_wdog_start();
        /*
         * Enable the UART FIFOs if they where not enabled and our
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index a40d5eb38124..e23723a5a214 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/i2c.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
@@ -55,6 +54,7 @@
 #include <plat/sdhci.h>
 #include "common.h"
+#include "i2c.h"
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 703e576a26e0..ca10963a959e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/i2c.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
@@ -55,6 +54,7 @@
 #include <plat/sdhci.h>
 #include "common.h"
+#include "i2c.h"
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 9cba18bfe47b..97c2a08ad490 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -103,8 +103,8 @@ static int s5p64x0_cpu_suspend(unsigned long arg)
            "mcr p15, 0, %0, c7, c10, 4\n\t"
            "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 /* mapping of interrupts to parts of the wakeup mask */
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index a32edc545e6c..569b76ac98cb 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/i2c.h>
+#include "i2c.h"
 void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index ca2c5c7f8aa6..867374e6d0bc 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/i2c.h>
+#include "i2c.h"
 void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index addfb165c13d..2d67361ef431 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,7 +18,8 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
-#include <mach/regs-audss.h>
+#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
 static int s5pv210_cfg_i2s(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
deleted file mode 100644
index eacc1f790807..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-audss.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
- *
- * Copyright (c) 2011 Samsung Electronics
- *              http://www.samsung.com
- *
- * S5PV210 Audio SubSystem clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_AUDSS_H
-#define __PLAT_REGS_AUDSS_H __FILE__
-#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
-#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
deleted file mode 100644
index cccb1eddaa38..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-sys.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - System registers definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
-#define S5PV210_USB_PHY0_EN     (1 << 0)
-#define S5PV210_USB_PHY1_EN     (1 << 1)
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index 08ff2fda1fb9..ef977ea8546d 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -19,6 +19,8 @@
 static void arch_detect_cpu(void)
 {
        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S5PV210_UFSTAT_TXMASK;
+        fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 736bfb103cbc..2b68a67b6e95 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -104,8 +104,8 @@ static int s5pv210_cpu_suspend(unsigned long arg)
            "mcr p15, 0, %0, c7, c10, 4\n\t"
            "wfi" : : "r" (tmp));
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 static void s5pv210_pm_prepare(void)
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
index be39cf4aa91b..356a0900af03 100644
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ b/arch/arm/mach-s5pv210/setup-usb-phy.c
@@ -12,12 +12,17 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <plat/cpu.h>
 #include <plat/regs-usb-hsotg-phy.h>
 #include <plat/usb-phy.h>
+#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
+#define S5PV210_USB_PHY0_EN     (1 << 0)
+#define S5PV210_USB_PHY1_EN     (1 << 1)
 static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
 {
        struct clk *xusbxti;
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index b38d2525d5db..e838ba27e443 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -16,6 +16,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_data/sa11x0-serial.h>
 #include <linux/serial_core.h>
+#include <linux/platform_device.h>
 #include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 5cf71da60e42..73093dc89829 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -49,4 +49,3 @@ static inline void flush(void)
 * Nothing to do for these
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index a89917653884..51b0eb52c014 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -24,9 +24,6 @@
 #include "generic.h"
-#warning "include/asm/arch-sa1100/ide.h needs fixing for lart"
 static struct mcp_plat_data lart_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h
index 22ccab4c3c5e..a168435aecc9 100644
--- a/arch/arm/mach-shark/include/mach/uncompress.h
+++ b/arch/arm/mach-shark/include/mach/uncompress.h
@@ -48,4 +48,3 @@ static void putr()
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 700e6623aa86..e1fac57514b9 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -19,13 +19,6 @@ smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
 smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
-# Pinmux setup
-pfc-y                           :=
-pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
-pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
-pfc-$(CONFIG_ARCH_R8A7740)      += pfc-r8a7740.o
-pfc-$(CONFIG_ARCH_R8A7779)      += pfc-r8a7779.o
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 obj-$(CONFIG_ARCH_R8A7740)      += entry-intc.o
@@ -52,4 +45,3 @@ obj-$(CONFIG_MACH_KZM9G)	+= board-kzm9g.o
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
-obj-$(CONFIG_GENERIC_GPIO)      += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index c1d4ab630214..2928cd686808 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -657,14 +657,8 @@ static struct platform_device lcdc_device = {
 /* FSI */
 #define IRQ_FSI         evt2irq(0x1840)
 static struct sh_fsi_platform_info fsi_info = {
-        .port_a = {
-                .flags          = SH_FSI_BRS_INV,
-        },
        .port_b = {
-                .flags          = SH_FSI_BRS_INV |
+                .flags          = SH_FSI_CLK_CPG |
-                                  SH_FSI_BRM_INV |
-                                  SH_FSI_LRS_INV |
-                                  SH_FSI_CLK_CPG |
                                  SH_FSI_FMT_SPDIF,
        },
 };
@@ -692,21 +686,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4643_info = {
        .name           = "AK4643",
        .card           = "FSI2A-AK4643",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0013",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4643_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4643_device = {
@@ -815,18 +809,18 @@ static struct platform_device lcdc1_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 65731370da81..81d91fda2d90 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -806,21 +806,21 @@ static struct platform_device fsi_device = {
 };
 /* FSI-WM8978 */
-static struct asoc_simple_dai_init_info fsi_wm8978_init_info = {
-        .fmt            = SND_SOC_DAIFMT_I2S,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 12288000,
-};
 static struct asoc_simple_card_info fsi_wm8978_info = {
        .name           = "wm8978",
        .card           = "FSI2A-WM8978",
-        .cpu_dai        = "fsia-dai",
        .codec          = "wm8978.0-001a",
        .platform       = "sh_fsi2",
-        .codec_dai      = "wm8978-hifi",
+        .daifmt         = SND_SOC_DAIFMT_I2S,
-        .init           = &fsi_wm8978_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "wm8978-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
+                .sysclk = 12288000,
+        },
 };
 static struct platform_device fsi_wm8978_device = {
@@ -832,18 +832,18 @@ static struct platform_device fsi_wm8978_device = {
 };
 /* FSI-HDMI */
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+        },
+        .codec_dai = {
+                .name = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 363c6edfa3cd..3efff2e7b1e7 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -525,21 +525,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4648_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4648_info = {
        .name           = "AK4648",
        .card           = "FSI2A-AK4648",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0012",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4648_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4648_device = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fe4917f2c1a2..e2fafca9432b 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -502,18 +502,18 @@ static struct platform_device hdmi_lcdc_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
@@ -858,16 +858,12 @@ static struct platform_device leds_device = {
 #define IRQ_FSI evt2irq(0x1840)
 static struct sh_fsi_platform_info fsi_info = {
        .port_a = {
-                .flags = SH_FSI_BRS_INV,
                .tx_id = SHDMA_SLAVE_FSIA_TX,
                .rx_id = SHDMA_SLAVE_FSIA_RX,
        },
        .port_b = {
-                .flags = SH_FSI_BRS_INV |
+                .flags = SH_FSI_CLK_CPG |
-                        SH_FSI_BRM_INV  |
+                         SH_FSI_FMT_SPDIF,
-                        SH_FSI_LRS_INV  |
-                        SH_FSI_CLK_CPG  |
-                        SH_FSI_FMT_SPDIF,
        }
 };
@@ -896,21 +892,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4643_info = {
        .name           = "AK4643",
        .card           = "FSI2A-AK4643",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0013",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4643_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4643_device = {
diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h
index 0bd7556b1387..f1aee56781e7 100644
--- a/arch/arm/mach-shmobile/include/mach/uncompress.h
+++ b/arch/arm/mach-shmobile/include/mach/uncompress.h
@@ -16,6 +16,4 @@ static void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog()
 #endif /* __ASM_MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
deleted file mode 100644
index 134d1b9a8821..000000000000
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ /dev/null
@@ -1,2617 +0,0 @@
-/*
- * R8A7740 processor support
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/r8a7740.h>
-#include <mach/irqs.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                                      \
-        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx),          \
-        PORT_10(fn, pfx##10, sfx),      PORT_90(fn, pfx##1, sfx),       \
-        PORT_10(fn, pfx##20, sfx),                                      \
-        PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        /* PORT0_DATA -> PORT211_DATA */
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),
-        PINMUX_DATA_END,
-        /* PORT0_IN -> PORT211_IN */
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),
-        PINMUX_INPUT_END,
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-        /* PORT0_OUT -> PORT211_OUT */
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),        /* PORT0_FN_IN -> PORT211_FN_IN */
-        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT211_FN_OUT */
-        PORT_ALL(FN0),          /* PORT0_FN0 -> PORT211_FN0 */
-        PORT_ALL(FN1),          /* PORT0_FN1 -> PORT211_FN1 */
-        PORT_ALL(FN2),          /* PORT0_FN2 -> PORT211_FN2 */
-        PORT_ALL(FN3),          /* PORT0_FN3 -> PORT211_FN3 */
-        PORT_ALL(FN4),          /* PORT0_FN4 -> PORT211_FN4 */
-        PORT_ALL(FN5),          /* PORT0_FN5 -> PORT211_FN5 */
-        PORT_ALL(FN6),          /* PORT0_FN6 -> PORT211_FN6 */
-        PORT_ALL(FN7),          /* PORT0_FN7 -> PORT211_FN7 */
-        MSEL1CR_31_0,   MSEL1CR_31_1,
-        MSEL1CR_30_0,   MSEL1CR_30_1,
-        MSEL1CR_29_0,   MSEL1CR_29_1,
-        MSEL1CR_28_0,   MSEL1CR_28_1,
-        MSEL1CR_27_0,   MSEL1CR_27_1,
-        MSEL1CR_26_0,   MSEL1CR_26_1,
-        MSEL1CR_16_0,   MSEL1CR_16_1,
-        MSEL1CR_15_0,   MSEL1CR_15_1,
-        MSEL1CR_14_0,   MSEL1CR_14_1,
-        MSEL1CR_13_0,   MSEL1CR_13_1,
-        MSEL1CR_12_0,   MSEL1CR_12_1,
-        MSEL1CR_9_0,    MSEL1CR_9_1,
-        MSEL1CR_7_0,    MSEL1CR_7_1,
-        MSEL1CR_6_0,    MSEL1CR_6_1,
-        MSEL1CR_5_0,    MSEL1CR_5_1,
-        MSEL1CR_4_0,    MSEL1CR_4_1,
-        MSEL1CR_3_0,    MSEL1CR_3_1,
-        MSEL1CR_2_0,    MSEL1CR_2_1,
-        MSEL1CR_0_0,    MSEL1CR_0_1,
-        MSEL3CR_15_0,   MSEL3CR_15_1, /* Trace / Debug ? */
-        MSEL3CR_6_0,    MSEL3CR_6_1,
-        MSEL4CR_19_0,   MSEL4CR_19_1,
-        MSEL4CR_18_0,   MSEL4CR_18_1,
-        MSEL4CR_15_0,   MSEL4CR_15_1,
-        MSEL4CR_10_0,   MSEL4CR_10_1,
-        MSEL4CR_6_0,    MSEL4CR_6_1,
-        MSEL4CR_4_0,    MSEL4CR_4_1,
-        MSEL4CR_1_0,    MSEL4CR_1_1,
-        MSEL5CR_31_0,   MSEL5CR_31_1, /* irq/fiq output */
-        MSEL5CR_30_0,   MSEL5CR_30_1,
-        MSEL5CR_29_0,   MSEL5CR_29_1,
-        MSEL5CR_27_0,   MSEL5CR_27_1,
-        MSEL5CR_25_0,   MSEL5CR_25_1,
-        MSEL5CR_23_0,   MSEL5CR_23_1,
-        MSEL5CR_21_0,   MSEL5CR_21_1,
-        MSEL5CR_19_0,   MSEL5CR_19_1,
-        MSEL5CR_17_0,   MSEL5CR_17_1,
-        MSEL5CR_15_0,   MSEL5CR_15_1,
-        MSEL5CR_14_0,   MSEL5CR_14_1,
-        MSEL5CR_13_0,   MSEL5CR_13_1,
-        MSEL5CR_12_0,   MSEL5CR_12_1,
-        MSEL5CR_11_0,   MSEL5CR_11_1,
-        MSEL5CR_10_0,   MSEL5CR_10_1,
-        MSEL5CR_8_0,    MSEL5CR_8_1,
-        MSEL5CR_7_0,    MSEL5CR_7_1,
-        MSEL5CR_6_0,    MSEL5CR_6_1,
-        MSEL5CR_5_0,    MSEL5CR_5_1,
-        MSEL5CR_4_0,    MSEL5CR_4_1,
-        MSEL5CR_3_0,    MSEL5CR_3_1,
-        MSEL5CR_2_0,    MSEL5CR_2_1,
-        MSEL5CR_0_0,    MSEL5CR_0_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* IRQ */
-        IRQ0_PORT2_MARK,        IRQ0_PORT13_MARK,
-        IRQ1_MARK,
-        IRQ2_PORT11_MARK,       IRQ2_PORT12_MARK,
-        IRQ3_PORT10_MARK,       IRQ3_PORT14_MARK,
-        IRQ4_PORT15_MARK,       IRQ4_PORT172_MARK,
-        IRQ5_PORT0_MARK,        IRQ5_PORT1_MARK,
-        IRQ6_PORT121_MARK,      IRQ6_PORT173_MARK,
-        IRQ7_PORT120_MARK,      IRQ7_PORT209_MARK,
-        IRQ8_MARK,
-        IRQ9_PORT118_MARK,      IRQ9_PORT210_MARK,
-        IRQ10_MARK,
-        IRQ11_MARK,
-        IRQ12_PORT42_MARK,      IRQ12_PORT97_MARK,
-        IRQ13_PORT64_MARK,      IRQ13_PORT98_MARK,
-        IRQ14_PORT63_MARK,      IRQ14_PORT99_MARK,
-        IRQ15_PORT62_MARK,      IRQ15_PORT100_MARK,
-        IRQ16_PORT68_MARK,      IRQ16_PORT211_MARK,
-        IRQ17_MARK,
-        IRQ18_MARK,
-        IRQ19_MARK,
-        IRQ20_MARK,
-        IRQ21_MARK,
-        IRQ22_MARK,
-        IRQ23_MARK,
-        IRQ24_MARK,
-        IRQ25_MARK,
-        IRQ26_PORT58_MARK,      IRQ26_PORT81_MARK,
-        IRQ27_PORT57_MARK,      IRQ27_PORT168_MARK,
-        IRQ28_PORT56_MARK,      IRQ28_PORT169_MARK,
-        IRQ29_PORT50_MARK,      IRQ29_PORT170_MARK,
-        IRQ30_PORT49_MARK,      IRQ30_PORT171_MARK,
-        IRQ31_PORT41_MARK,      IRQ31_PORT167_MARK,
-        /* Function */
-        /* DBGT */
-        DBGMDT2_MARK,   DBGMDT1_MARK,   DBGMDT0_MARK,
-        DBGMD10_MARK,   DBGMD11_MARK,   DBGMD20_MARK,
-        DBGMD21_MARK,
-        /* FSI-A */
-        FSIAISLD_PORT0_MARK,    /* FSIAISLD Port 0/5 */
-        FSIAISLD_PORT5_MARK,
-        FSIASPDIF_PORT9_MARK,   /* FSIASPDIF Port 9/18 */
-        FSIASPDIF_PORT18_MARK,
-        FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
-        FSIAOBT_MARK,   FSIAOSLD_MARK,  FSIAOMC_MARK,
-        FSIACK_MARK,    FSIAILR_MARK,   FSIAIBT_MARK,
-        /* FSI-B */
-        FSIBCK_MARK,
-        /* FMSI */
-        FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
-        FMSISLD_PORT6_MARK,
-        FMSIILR_MARK,   FMSIIBT_MARK,   FMSIOLR_MARK,   FMSIOBT_MARK,
-        FMSICK_MARK,    FMSOILR_MARK,   FMSOIBT_MARK,   FMSOOLR_MARK,
-        FMSOOBT_MARK,   FMSOSLD_MARK,   FMSOCK_MARK,
-        /* SCIFA0 */
-        SCIFA0_SCK_MARK,        SCIFA0_CTS_MARK,        SCIFA0_RTS_MARK,
-        SCIFA0_RXD_MARK,        SCIFA0_TXD_MARK,
-        /* SCIFA1 */
-        SCIFA1_CTS_MARK,        SCIFA1_SCK_MARK,        SCIFA1_RXD_MARK,
-        SCIFA1_TXD_MARK,        SCIFA1_RTS_MARK,
-        /* SCIFA2 */
-        SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
-        SCIFA2_SCK_PORT199_MARK,
-        SCIFA2_RXD_MARK,        SCIFA2_TXD_MARK,
-        SCIFA2_CTS_MARK,        SCIFA2_RTS_MARK,
-        /* SCIFA3 */
-        SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
-        SCIFA3_SCK_PORT116_MARK,
-        SCIFA3_CTS_PORT117_MARK,
-        SCIFA3_RXD_PORT174_MARK,
-        SCIFA3_TXD_PORT175_MARK,
-        SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
-        SCIFA3_SCK_PORT158_MARK,
-        SCIFA3_CTS_PORT162_MARK,
-        SCIFA3_RXD_PORT159_MARK,
-        SCIFA3_TXD_PORT160_MARK,
-        /* SCIFA4 */
-        SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
-        SCIFA4_TXD_PORT13_MARK,
-        SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
-        SCIFA4_TXD_PORT203_MARK,
-        SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
-        SCIFA4_TXD_PORT93_MARK,
-        SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
-        SCIFA4_SCK_PORT205_MARK,
-        /* SCIFA5 */
-        SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
-        SCIFA5_RXD_PORT10_MARK,
-        SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
-        SCIFA5_TXD_PORT208_MARK,
-        SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
-        SCIFA5_RXD_PORT92_MARK,
-        SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
-        SCIFA5_SCK_PORT206_MARK,
-        /* SCIFA6 */
-        SCIFA6_SCK_MARK,        SCIFA6_RXD_MARK,        SCIFA6_TXD_MARK,
-        /* SCIFA7 */
-        SCIFA7_TXD_MARK,        SCIFA7_RXD_MARK,
-        /* SCIFAB */
-        SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
-        SCIFB_RXD_PORT191_MARK,
-        SCIFB_TXD_PORT192_MARK,
-        SCIFB_RTS_PORT186_MARK,
-        SCIFB_CTS_PORT187_MARK,
-        SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
-        SCIFB_RXD_PORT3_MARK,
-        SCIFB_TXD_PORT4_MARK,
-        SCIFB_RTS_PORT172_MARK,
-        SCIFB_CTS_PORT173_MARK,
-        /* LCD0 */
-        LCDC0_SELECT_MARK,
-        LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
-        LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
-        LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
-        LCD0_D12_MARK,  LCD0_D13_MARK,  LCD0_D14_MARK,  LCD0_D15_MARK,
-        LCD0_D16_MARK,  LCD0_D17_MARK,
-        LCD0_DON_MARK,  LCD0_VCPWC_MARK,        LCD0_VEPWC_MARK,
-        LCD0_DCK_MARK,  LCD0_VSYN_MARK, /* for RGB */
-        LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
-        LCD0_WR_MARK,   LCD0_RD_MARK,   /* for SYS */
-        LCD0_CS_MARK,   LCD0_RS_MARK,   /* for SYS */
-        LCD0_D21_PORT158_MARK,  LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
-        LCD0_D22_PORT160_MARK,  LCD0_D20_PORT161_MARK,
-        LCD0_D19_PORT162_MARK,  LCD0_D18_PORT163_MARK,
-        LCD0_LCLK_PORT165_MARK,
-        LCD0_D18_PORT40_MARK,   LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
-        LCD0_D23_PORT1_MARK,    LCD0_D21_PORT2_MARK,
-        LCD0_D20_PORT3_MARK,    LCD0_D19_PORT4_MARK,
-        LCD0_LCLK_PORT102_MARK,
-        /* LCD1 */
-        LCDC1_SELECT_MARK,
-        LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
-        LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
-        LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
-        LCD1_D12_MARK,  LCD1_D13_MARK,  LCD1_D14_MARK,  LCD1_D15_MARK,
-        LCD1_D16_MARK,  LCD1_D17_MARK,  LCD1_D18_MARK,  LCD1_D19_MARK,
-        LCD1_D20_MARK,  LCD1_D21_MARK,  LCD1_D22_MARK,  LCD1_D23_MARK,
-        LCD1_DON_MARK,  LCD1_VCPWC_MARK,
-        LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
-        LCD1_DCK_MARK,  LCD1_VSYN_MARK, /* for RGB */
-        LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
-        LCD1_RS_MARK,   LCD1_CS_MARK,   /* for SYS */
-        LCD1_RD_MARK,   LCD1_WR_MARK,   /* for SYS */
-        /* RSPI */
-        RSPI_SSL0_A_MARK,       RSPI_SSL1_A_MARK,       RSPI_SSL2_A_MARK,
-        RSPI_SSL3_A_MARK,       RSPI_CK_A_MARK,         RSPI_MOSI_A_MARK,
-        RSPI_MISO_A_MARK,
-        /* VIO CKO */
-        VIO_CKO1_MARK, /* needs fixup */
-        VIO_CKO2_MARK,
-        VIO_CKO_1_MARK,
-        VIO_CKO_MARK,
-        /* VIO0 */
-        VIO0_D0_MARK,   VIO0_D1_MARK,   VIO0_D2_MARK,   VIO0_D3_MARK,
-        VIO0_D4_MARK,   VIO0_D5_MARK,   VIO0_D6_MARK,   VIO0_D7_MARK,
-        VIO0_D8_MARK,   VIO0_D9_MARK,   VIO0_D10_MARK,  VIO0_D11_MARK,
-        VIO0_D12_MARK,  VIO0_VD_MARK,   VIO0_HD_MARK,   VIO0_CLK_MARK,
-        VIO0_FIELD_MARK,
-        VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
-        VIO0_D14_PORT25_MARK,
-        VIO0_D15_PORT24_MARK,
-        VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
-        VIO0_D14_PORT95_MARK,
-        VIO0_D15_PORT96_MARK,
-        /* VIO1 */
-        VIO1_D0_MARK,   VIO1_D1_MARK,   VIO1_D2_MARK,   VIO1_D3_MARK,
-        VIO1_D4_MARK,   VIO1_D5_MARK,   VIO1_D6_MARK,   VIO1_D7_MARK,
-        VIO1_VD_MARK,   VIO1_HD_MARK,   VIO1_CLK_MARK,  VIO1_FIELD_MARK,
-        /* TPU0 */
-        TPU0TO0_MARK,   TPU0TO1_MARK,   TPU0TO3_MARK,
-        TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
-        TPU0TO2_PORT202_MARK,
-        /* SSP1 0 */
-        STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
-        STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
-        STP0_IPEN_MARK, STP0_IPCLK_MARK,        STP0_IPSYNC_MARK,
-        /* SSP1 1 */
-        STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
-        STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
-        STP1_IPSYNC_MARK,
-        STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
-        STP1_IPEN_PORT187_MARK,
-        STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
-        STP1_IPEN_PORT193_MARK,
-        /* SIM */
-        SIM_RST_MARK,   SIM_CLK_MARK,
-        SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
-        SIM_D_PORT199_MARK,
-        /* SDHI0 */
-        SDHI0_D0_MARK,  SDHI0_D1_MARK,  SDHI0_D2_MARK,  SDHI0_D3_MARK,
-        SDHI0_CD_MARK,  SDHI0_WP_MARK,  SDHI0_CMD_MARK, SDHI0_CLK_MARK,
-        /* SDHI1 */
-        SDHI1_D0_MARK,  SDHI1_D1_MARK,  SDHI1_D2_MARK,  SDHI1_D3_MARK,
-        SDHI1_CD_MARK,  SDHI1_WP_MARK,  SDHI1_CMD_MARK, SDHI1_CLK_MARK,
-        /* SDHI2 */
-        SDHI2_D0_MARK,  SDHI2_D1_MARK,  SDHI2_D2_MARK,  SDHI2_D3_MARK,
-        SDHI2_CLK_MARK, SDHI2_CMD_MARK,
-        SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
-        SDHI2_WP_PORT25_MARK,
-        SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
-        SDHI2_CD_PORT202_MARK,
-        /* MSIOF2 */
-        MSIOF2_TXD_MARK,        MSIOF2_RXD_MARK,        MSIOF2_TSCK_MARK,
-        MSIOF2_SS2_MARK,        MSIOF2_TSYNC_MARK,      MSIOF2_SS1_MARK,
-        MSIOF2_MCK1_MARK,       MSIOF2_MCK0_MARK,       MSIOF2_RSYNC_MARK,
-        MSIOF2_RSCK_MARK,
-        /* KEYSC */
-        KEYIN4_MARK,    KEYIN5_MARK,    KEYIN6_MARK,    KEYIN7_MARK,
-        KEYOUT0_MARK,   KEYOUT1_MARK,   KEYOUT2_MARK,   KEYOUT3_MARK,
-        KEYOUT4_MARK,   KEYOUT5_MARK,   KEYOUT6_MARK,   KEYOUT7_MARK,
-        KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
-        KEYIN1_PORT44_MARK,
-        KEYIN2_PORT45_MARK,
-        KEYIN3_PORT46_MARK,
-        KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
-        KEYIN1_PORT57_MARK,
-        KEYIN2_PORT56_MARK,
-        KEYIN3_PORT55_MARK,
-        /* VOU */
-        DV_D0_MARK,     DV_D1_MARK,     DV_D2_MARK,     DV_D3_MARK,
-        DV_D4_MARK,     DV_D5_MARK,     DV_D6_MARK,     DV_D7_MARK,
-        DV_D8_MARK,     DV_D9_MARK,     DV_D10_MARK,    DV_D11_MARK,
-        DV_D12_MARK,    DV_D13_MARK,    DV_D14_MARK,    DV_D15_MARK,
-        DV_CLK_MARK,    DV_VSYNC_MARK,  DV_HSYNC_MARK,
-        /* MEMC */
-        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,  MEMC_AD3_MARK,
-        MEMC_AD4_MARK,  MEMC_AD5_MARK,  MEMC_AD6_MARK,  MEMC_AD7_MARK,
-        MEMC_AD8_MARK,  MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
-        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
-        MEMC_CS0_MARK,  MEMC_INT_MARK,  MEMC_NWE_MARK,  MEMC_NOE_MARK,
-        MEMC_CS1_MARK, /* MSEL4CR_6_0 */
-        MEMC_ADV_MARK,
-        MEMC_WAIT_MARK,
-        MEMC_BUSCLK_MARK,
-        MEMC_A1_MARK, /* MSEL4CR_6_1 */
-        MEMC_DREQ0_MARK,
-        MEMC_DREQ1_MARK,
-        MEMC_A0_MARK,
-        /* MMC */
-        MMC0_D0_PORT68_MARK,    MMC0_D1_PORT69_MARK,    MMC0_D2_PORT70_MARK,
-        MMC0_D3_PORT71_MARK,    MMC0_D4_PORT72_MARK,    MMC0_D5_PORT73_MARK,
-        MMC0_D6_PORT74_MARK,    MMC0_D7_PORT75_MARK,    MMC0_CLK_PORT66_MARK,
-        MMC0_CMD_PORT67_MARK,   /* MSEL4CR_15_0 */
-        MMC1_D0_PORT149_MARK,   MMC1_D1_PORT148_MARK,   MMC1_D2_PORT147_MARK,
-        MMC1_D3_PORT146_MARK,   MMC1_D4_PORT145_MARK,   MMC1_D5_PORT144_MARK,
-        MMC1_D6_PORT143_MARK,   MMC1_D7_PORT142_MARK,   MMC1_CLK_PORT103_MARK,
-        MMC1_CMD_PORT104_MARK,  /* MSEL4CR_15_1 */
-        /* MSIOF0 */
-        MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,        MSIOF0_RXD_MARK,
-        MSIOF0_TXD_MARK,        MSIOF0_MCK0_MARK,       MSIOF0_MCK1_MARK,
-        MSIOF0_RSYNC_MARK,      MSIOF0_RSCK_MARK,       MSIOF0_TSCK_MARK,
-        MSIOF0_TSYNC_MARK,
-        /* MSIOF1 */
-        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
-        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
-        MSIOF1_SS2_PORT116_MARK,        MSIOF1_SS1_PORT117_MARK,
-        MSIOF1_RXD_PORT118_MARK,        MSIOF1_TXD_PORT119_MARK,
-        MSIOF1_TSYNC_PORT120_MARK,
-        MSIOF1_TSCK_PORT121_MARK,       /* MSEL4CR_10_0 */
-        MSIOF1_SS1_PORT67_MARK,         MSIOF1_TSCK_PORT72_MARK,
-        MSIOF1_TSYNC_PORT73_MARK,       MSIOF1_TXD_PORT74_MARK,
-        MSIOF1_RXD_PORT75_MARK,
-        MSIOF1_SS2_PORT202_MARK,        /* MSEL4CR_10_1 */
-        /* GPIO */
-        GPO0_MARK,      GPI0_MARK,      GPO1_MARK,      GPI1_MARK,
-        /* USB0 */
-        USB0_OCI_MARK,  USB0_PPON_MARK, VBUS_MARK,
-        /* USB1 */
-        USB1_OCI_MARK,  USB1_PPON_MARK,
-        /* BBIF1 */
-        BBIF1_RXD_MARK,         BBIF1_TXD_MARK,         BBIF1_TSYNC_MARK,
-        BBIF1_TSCK_MARK,        BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
-        BBIF1_FLOW_MARK,        BBIF1_RX_FLOW_N_MARK,
-        /* BBIF2 */
-        BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
-        BBIF2_RXD2_PORT60_MARK,
-        BBIF2_TSYNC2_PORT6_MARK,
-        BBIF2_TSCK2_PORT59_MARK,
-        BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
-        BBIF2_TXD2_PORT183_MARK,
-        BBIF2_TSCK2_PORT89_MARK,
-        BBIF2_TSYNC2_PORT184_MARK,
-        /* BSC / FLCTL / PCMCIA */
-        CS0_MARK,       CS2_MARK,       CS4_MARK,
-        CS5B_MARK,      CS6A_MARK,
-        CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
-        CS5A_PORT19_MARK,
-        IOIS16_MARK, /* ? */
-        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
-        A4_FOE_MARK,    /* share with FLCTL */
-        A5_FCDE_MARK,   /* share with FLCTL */
-        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
-        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
-        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
-        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
-        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
-        A26_MARK,
-        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   /* share with FLCTL */
-        D3_NAF3_MARK,   D4_NAF4_MARK,   D5_NAF5_MARK,   /* share with FLCTL */
-        D6_NAF6_MARK,   D7_NAF7_MARK,   D8_NAF8_MARK,   /* share with FLCTL */
-        D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
-        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
-        D15_NAF15_MARK,                                 /* share with FLCTL */
-        D16_MARK,       D17_MARK,       D18_MARK,       D19_MARK,
-        D20_MARK,       D21_MARK,       D22_MARK,       D23_MARK,
-        D24_MARK,       D25_MARK,       D26_MARK,       D27_MARK,
-        D28_MARK,       D29_MARK,       D30_MARK,       D31_MARK,
-        WE0_FWE_MARK,   /* share with FLCTL */
-        WE1_MARK,
-        WE2_ICIORD_MARK,        /* share with PCMCIA */
-        WE3_ICIOWR_MARK,        /* share with PCMCIA */
-        CKO_MARK,       BS_MARK,        RDWR_MARK,
-        RD_FSC_MARK,    /* share with FLCTL */
-        WAIT_PORT177_MARK, /* WAIT Port 90/177 */
-        WAIT_PORT90_MARK,
-        FCE0_MARK,      FCE1_MARK,      FRB_MARK, /* FLCTL */
-        /* IRDA */
-        IRDA_FIRSEL_MARK,       IRDA_IN_MARK,   IRDA_OUT_MARK,
-        /* ATAPI */
-        IDE_D0_MARK,    IDE_D1_MARK,    IDE_D2_MARK,    IDE_D3_MARK,
-        IDE_D4_MARK,    IDE_D5_MARK,    IDE_D6_MARK,    IDE_D7_MARK,
-        IDE_D8_MARK,    IDE_D9_MARK,    IDE_D10_MARK,   IDE_D11_MARK,
-        IDE_D12_MARK,   IDE_D13_MARK,   IDE_D14_MARK,   IDE_D15_MARK,
-        IDE_A0_MARK,    IDE_A1_MARK,    IDE_A2_MARK,    IDE_CS0_MARK,
-        IDE_CS1_MARK,   IDE_IOWR_MARK,  IDE_IORD_MARK,  IDE_IORDY_MARK,
-        IDE_INT_MARK,           IDE_RST_MARK,           IDE_DIRECTION_MARK,
-        IDE_EXBUF_ENB_MARK,     IDE_IODACK_MARK,        IDE_IODREQ_MARK,
-        /* RMII */
-        RMII_CRS_DV_MARK,       RMII_RX_ER_MARK,        RMII_RXD0_MARK,
-        RMII_RXD1_MARK,         RMII_TX_EN_MARK,        RMII_TXD0_MARK,
-        RMII_MDC_MARK,          RMII_TXD1_MARK,         RMII_MDIO_MARK,
-        RMII_REF50CK_MARK,      /* for RMII */
-        RMII_REF125CK_MARK,     /* for GMII */
-        /* GEther */
-        ET_TX_CLK_MARK, ET_TX_EN_MARK,  ET_ETXD0_MARK,  ET_ETXD1_MARK,
-        ET_ETXD2_MARK,  ET_ETXD3_MARK,
-        ET_ETXD4_MARK,  ET_ETXD5_MARK, /* for GEther */
-        ET_ETXD6_MARK,  ET_ETXD7_MARK, /* for GEther */
-        ET_COL_MARK,    ET_TX_ER_MARK,  ET_RX_CLK_MARK, ET_RX_DV_MARK,
-        ET_ERXD0_MARK,  ET_ERXD1_MARK,  ET_ERXD2_MARK,  ET_ERXD3_MARK,
-        ET_ERXD4_MARK,  ET_ERXD5_MARK, /* for GEther */
-        ET_ERXD6_MARK,  ET_ERXD7_MARK, /* for GEther */
-        ET_RX_ER_MARK,  ET_CRS_MARK,            ET_MDC_MARK,    ET_MDIO_MARK,
-        ET_LINK_MARK,   ET_PHY_INT_MARK,        ET_WOL_MARK,    ET_GTX_CLK_MARK,
-        /* DMA0 */
-        DREQ0_MARK,     DACK0_MARK,
-        /* DMA1 */
-        DREQ1_MARK,     DACK1_MARK,
-        /* SYSC */
-        RESETOUTS_MARK,         RESETP_PULLUP_MARK,     RESETP_PLAIN_MARK,
-        /* IRREM */
-        IROUT_MARK,
-        /* SDENC */
-        SDENC_CPG_MARK,         SDENC_DV_CLKI_MARK,
-        /* HDMI */
-        HDMI_HPD_MARK, HDMI_CEC_MARK,
-        /* DEBUG */
-        EDEBGREQ_PULLUP_MARK,   /* for JTAG */
-        EDEBGREQ_PULLDOWN_MARK,
-        TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
-        TRACEAUD_FROM_LCDC0_MARK,
-        TRACEAUD_FROM_MEMC_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
-        /* Port0 */
-        PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
-        PINMUX_DATA(FSIAISLD_PORT0_MARK,        PORT0_FN2,      MSEL5CR_3_0),
-        PINMUX_DATA(FSIAOSLD1_MARK,             PORT0_FN3),
-        PINMUX_DATA(LCD0_D22_PORT0_MARK,        PORT0_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(SCIFA7_RXD_MARK,            PORT0_FN6),
-        PINMUX_DATA(LCD1_D4_MARK,               PORT0_FN7),
-        PINMUX_DATA(IRQ5_PORT0_MARK,            PORT0_FN0,      MSEL1CR_5_0),
-        /* Port1 */
-        PINMUX_DATA(DBGMDT1_MARK,               PORT1_FN1),
-        PINMUX_DATA(FMSISLD_PORT1_MARK,         PORT1_FN2,      MSEL5CR_5_0),
-        PINMUX_DATA(FSIAOSLD2_MARK,             PORT1_FN3),
-        PINMUX_DATA(LCD0_D23_PORT1_MARK,        PORT1_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(SCIFA7_TXD_MARK,            PORT1_FN6),
-        PINMUX_DATA(LCD1_D3_MARK,               PORT1_FN7),
-        PINMUX_DATA(IRQ5_PORT1_MARK,            PORT1_FN0,      MSEL1CR_5_1),
-        /* Port2 */
-        PINMUX_DATA(DBGMDT0_MARK,               PORT2_FN1),
-        PINMUX_DATA(SCIFB_SCK_PORT2_MARK,       PORT2_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D21_PORT2_MARK,        PORT2_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D2_MARK,               PORT2_FN7),
-        PINMUX_DATA(IRQ0_PORT2_MARK,            PORT2_FN0,      MSEL1CR_0_1),
-        /* Port3 */
-        PINMUX_DATA(DBGMD21_MARK,               PORT3_FN1),
-        PINMUX_DATA(SCIFB_RXD_PORT3_MARK,       PORT3_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D20_PORT3_MARK,        PORT3_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D1_MARK,               PORT3_FN7),
-        /* Port4 */
-        PINMUX_DATA(DBGMD20_MARK,               PORT4_FN1),
-        PINMUX_DATA(SCIFB_TXD_PORT4_MARK,       PORT4_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D19_PORT4_MARK,        PORT4_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D0_MARK,               PORT4_FN7),
-        /* Port5 */
-        PINMUX_DATA(DBGMD11_MARK,               PORT5_FN1),
-        PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,      PORT5_FN2,      MSEL5CR_0_0),
-        PINMUX_DATA(FSIAISLD_PORT5_MARK,        PORT5_FN4,      MSEL5CR_3_1),
-        PINMUX_DATA(RSPI_SSL0_A_MARK,           PORT5_FN6),
-        PINMUX_DATA(LCD1_VCPWC_MARK,            PORT5_FN7),
-        /* Port6 */
-        PINMUX_DATA(DBGMD10_MARK,               PORT6_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,    PORT6_FN2,      MSEL5CR_0_0),
-        PINMUX_DATA(FMSISLD_PORT6_MARK,         PORT6_FN4,      MSEL5CR_5_1),
-        PINMUX_DATA(RSPI_SSL1_A_MARK,           PORT6_FN6),
-        PINMUX_DATA(LCD1_VEPWC_MARK,            PORT6_FN7),
-        /* Port7 */
-        PINMUX_DATA(FSIAOLR_MARK,               PORT7_FN1),
-        /* Port8 */
-        PINMUX_DATA(FSIAOBT_MARK,               PORT8_FN1),
-        /* Port9 */
-        PINMUX_DATA(FSIAOSLD_MARK,              PORT9_FN1),
-        PINMUX_DATA(FSIASPDIF_PORT9_MARK,       PORT9_FN2,      MSEL5CR_4_0),
-        /* Port10 */
-        PINMUX_DATA(FSIAOMC_MARK,               PORT10_FN1),
-        PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,     PORT10_FN3,     MSEL5CR_14_0,   MSEL5CR_15_0),
-        PINMUX_DATA(IRQ3_PORT10_MARK,           PORT10_FN0,     MSEL1CR_3_0),
-        /* Port11 */
-        PINMUX_DATA(FSIACK_MARK,                PORT11_FN1),
-        PINMUX_DATA(FSIBCK_MARK,                PORT11_FN2),
-        PINMUX_DATA(IRQ2_PORT11_MARK,           PORT11_FN0,     MSEL1CR_2_0),
-        /* Port12 */
-        PINMUX_DATA(FSIAILR_MARK,               PORT12_FN1),
-        PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,     PORT12_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
-        PINMUX_DATA(LCD1_RS_MARK,               PORT12_FN6),
-        PINMUX_DATA(LCD1_DISP_MARK,             PORT12_FN7),
-        PINMUX_DATA(IRQ2_PORT12_MARK,           PORT12_FN0,     MSEL1CR_2_1),
-        /* Port13 */
-        PINMUX_DATA(FSIAIBT_MARK,               PORT13_FN1),
-        PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,     PORT13_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
-        PINMUX_DATA(LCD1_RD_MARK,               PORT13_FN7),
-        PINMUX_DATA(IRQ0_PORT13_MARK,           PORT13_FN0,     MSEL1CR_0_0),
-        /* Port14 */
-        PINMUX_DATA(FMSOILR_MARK,               PORT14_FN1),
-        PINMUX_DATA(FMSIILR_MARK,               PORT14_FN2),
-        PINMUX_DATA(VIO_CKO1_MARK,              PORT14_FN3),
-        PINMUX_DATA(LCD1_D23_MARK,              PORT14_FN7),
-        PINMUX_DATA(IRQ3_PORT14_MARK,           PORT14_FN0,     MSEL1CR_3_1),
-        /* Port15 */
-        PINMUX_DATA(FMSOIBT_MARK,               PORT15_FN1),
-        PINMUX_DATA(FMSIIBT_MARK,               PORT15_FN2),
-        PINMUX_DATA(VIO_CKO2_MARK,              PORT15_FN3),
-        PINMUX_DATA(LCD1_D22_MARK,              PORT15_FN7),
-        PINMUX_DATA(IRQ4_PORT15_MARK,           PORT15_FN0,     MSEL1CR_4_0),
-        /* Port16 */
-        PINMUX_DATA(FMSOOLR_MARK,               PORT16_FN1),
-        PINMUX_DATA(FMSIOLR_MARK,               PORT16_FN2),
-        /* Port17 */
-        PINMUX_DATA(FMSOOBT_MARK,               PORT17_FN1),
-        PINMUX_DATA(FMSIOBT_MARK,               PORT17_FN2),
-        /* Port18 */
-        PINMUX_DATA(FMSOSLD_MARK,               PORT18_FN1),
-        PINMUX_DATA(FSIASPDIF_PORT18_MARK,      PORT18_FN2,     MSEL5CR_4_1),
-        /* Port19 */
-        PINMUX_DATA(FMSICK_MARK,                PORT19_FN1),
-        PINMUX_DATA(CS5A_PORT19_MARK,           PORT19_FN7,     MSEL5CR_2_1),
-        PINMUX_DATA(IRQ10_MARK,                 PORT19_FN0),
-        /* Port20 */
-        PINMUX_DATA(FMSOCK_MARK,                PORT20_FN1),
-        PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,     PORT20_FN3,     MSEL5CR_15_0,   MSEL5CR_14_0),
-        PINMUX_DATA(IRQ1_MARK,                  PORT20_FN0),
-        /* Port21 */
-        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT21_FN1),
-        PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,     PORT21_FN2,     MSEL5CR_10_0),
-        PINMUX_DATA(TPU0TO1_MARK,               PORT21_FN4),
-        PINMUX_DATA(VIO1_FIELD_MARK,            PORT21_FN5),
-        PINMUX_DATA(STP0_IPD5_MARK,             PORT21_FN6),
-        PINMUX_DATA(LCD1_D10_MARK,              PORT21_FN7),
-        /* Port22 */
-        PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,     PORT22_FN1,     MSEL5CR_7_0),
-        PINMUX_DATA(SIM_D_PORT22_MARK,          PORT22_FN4,     MSEL5CR_21_0),
-        PINMUX_DATA(VIO0_D13_PORT22_MARK,       PORT22_FN7,     MSEL5CR_27_1),
-        /* Port23 */
-        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT23_FN1),
-        PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,     PORT23_FN3,     MSEL5CR_13_0),
-        PINMUX_DATA(TPU0TO0_MARK,               PORT23_FN4),
-        PINMUX_DATA(VIO_CKO_1_MARK,             PORT23_FN5),
-        PINMUX_DATA(STP0_IPD2_MARK,             PORT23_FN6),
-        PINMUX_DATA(LCD1_D7_MARK,               PORT23_FN7),
-        /* Port24 */
-        PINMUX_DATA(VIO0_D15_PORT24_MARK,       PORT24_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D7_MARK,               PORT24_FN5),
-        PINMUX_DATA(SCIFA6_SCK_MARK,            PORT24_FN6),
-        PINMUX_DATA(SDHI2_CD_PORT24_MARK,       PORT24_FN7,     MSEL5CR_19_0),
-        /* Port25 */
-        PINMUX_DATA(VIO0_D14_PORT25_MARK,       PORT25_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D6_MARK,               PORT25_FN5),
-        PINMUX_DATA(SCIFA6_RXD_MARK,            PORT25_FN6),
-        PINMUX_DATA(SDHI2_WP_PORT25_MARK,       PORT25_FN7,     MSEL5CR_19_0),
-        /* Port26 */
-        PINMUX_DATA(VIO0_D13_PORT26_MARK,       PORT26_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D5_MARK,               PORT26_FN5),
-        PINMUX_DATA(SCIFA6_TXD_MARK,            PORT26_FN6),
-        /* Port27 - Port39 Function */
-        PINMUX_DATA(VIO0_D7_MARK,               PORT27_FN1),
-        PINMUX_DATA(VIO0_D6_MARK,               PORT28_FN1),
-        PINMUX_DATA(VIO0_D5_MARK,               PORT29_FN1),
-        PINMUX_DATA(VIO0_D4_MARK,               PORT30_FN1),
-        PINMUX_DATA(VIO0_D3_MARK,               PORT31_FN1),
-        PINMUX_DATA(VIO0_D2_MARK,               PORT32_FN1),
-        PINMUX_DATA(VIO0_D1_MARK,               PORT33_FN1),
-        PINMUX_DATA(VIO0_D0_MARK,               PORT34_FN1),
-        PINMUX_DATA(VIO0_CLK_MARK,              PORT35_FN1),
-        PINMUX_DATA(VIO_CKO_MARK,               PORT36_FN1),
-        PINMUX_DATA(VIO0_HD_MARK,               PORT37_FN1),
-        PINMUX_DATA(VIO0_FIELD_MARK,            PORT38_FN1),
-        PINMUX_DATA(VIO0_VD_MARK,               PORT39_FN1),
-        /* Port38 IRQ */
-        PINMUX_DATA(IRQ25_MARK,                 PORT38_FN0),
-        /* Port40 */
-        PINMUX_DATA(LCD0_D18_PORT40_MARK,       PORT40_FN4,     MSEL5CR_6_0),
-        PINMUX_DATA(RSPI_CK_A_MARK,             PORT40_FN6),
-        PINMUX_DATA(LCD1_LCLK_MARK,             PORT40_FN7),
-        /* Port41 */
-        PINMUX_DATA(LCD0_D17_MARK,              PORT41_FN1),
-        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT41_FN2),
-        PINMUX_DATA(IRQ31_PORT41_MARK,          PORT41_FN0,     MSEL1CR_31_1),
-        /* Port42 */
-        PINMUX_DATA(LCD0_D16_MARK,              PORT42_FN1),
-        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT42_FN2),
-        PINMUX_DATA(IRQ12_PORT42_MARK,          PORT42_FN0,     MSEL1CR_12_1),
-        /* Port43 */
-        PINMUX_DATA(LCD0_D15_MARK,              PORT43_FN1),
-        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT43_FN2),
-        PINMUX_DATA(KEYIN0_PORT43_MARK,         PORT43_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D15_MARK,                PORT43_FN6),
-        /* Port44 */
-        PINMUX_DATA(LCD0_D14_MARK,              PORT44_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT44_FN2),
-        PINMUX_DATA(KEYIN1_PORT44_MARK,         PORT44_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D14_MARK,                PORT44_FN6),
-        /* Port45 */
-        PINMUX_DATA(LCD0_D13_MARK,              PORT45_FN1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT45_FN2),
-        PINMUX_DATA(KEYIN2_PORT45_MARK,         PORT45_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D13_MARK,                PORT45_FN6),
-        /* Port46 */
-        PINMUX_DATA(LCD0_D12_MARK,              PORT46_FN1),
-        PINMUX_DATA(KEYIN3_PORT46_MARK,         PORT46_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D12_MARK,                PORT46_FN6),
-        /* Port47 */
-        PINMUX_DATA(LCD0_D11_MARK,              PORT47_FN1),
-        PINMUX_DATA(KEYIN4_MARK,                PORT47_FN3),
-        PINMUX_DATA(DV_D11_MARK,                PORT47_FN6),
-        /* Port48 */
-        PINMUX_DATA(LCD0_D10_MARK,              PORT48_FN1),
-        PINMUX_DATA(KEYIN5_MARK,                PORT48_FN3),
-        PINMUX_DATA(DV_D10_MARK,                PORT48_FN6),
-        /* Port49 */
-        PINMUX_DATA(LCD0_D9_MARK,               PORT49_FN1),
-        PINMUX_DATA(KEYIN6_MARK,                PORT49_FN3),
-        PINMUX_DATA(DV_D9_MARK,                 PORT49_FN6),
-        PINMUX_DATA(IRQ30_PORT49_MARK,          PORT49_FN0,     MSEL1CR_30_1),
-        /* Port50 */
-        PINMUX_DATA(LCD0_D8_MARK,               PORT50_FN1),
-        PINMUX_DATA(KEYIN7_MARK,                PORT50_FN3),
-        PINMUX_DATA(DV_D8_MARK,                 PORT50_FN6),
-        PINMUX_DATA(IRQ29_PORT50_MARK,          PORT50_FN0,     MSEL1CR_29_1),
-        /* Port51 */
-        PINMUX_DATA(LCD0_D7_MARK,               PORT51_FN1),
-        PINMUX_DATA(KEYOUT0_MARK,               PORT51_FN3),
-        PINMUX_DATA(DV_D7_MARK,                 PORT51_FN6),
-        /* Port52 */
-        PINMUX_DATA(LCD0_D6_MARK,               PORT52_FN1),
-        PINMUX_DATA(KEYOUT1_MARK,               PORT52_FN3),
-        PINMUX_DATA(DV_D6_MARK,                 PORT52_FN6),
-        /* Port53 */
-        PINMUX_DATA(LCD0_D5_MARK,               PORT53_FN1),
-        PINMUX_DATA(KEYOUT2_MARK,               PORT53_FN3),
-        PINMUX_DATA(DV_D5_MARK,                 PORT53_FN6),
-        /* Port54 */
-        PINMUX_DATA(LCD0_D4_MARK,               PORT54_FN1),
-        PINMUX_DATA(KEYOUT3_MARK,               PORT54_FN3),
-        PINMUX_DATA(DV_D4_MARK,                 PORT54_FN6),
-        /* Port55 */
-        PINMUX_DATA(LCD0_D3_MARK,               PORT55_FN1),
-        PINMUX_DATA(KEYOUT4_MARK,               PORT55_FN3),
-        PINMUX_DATA(KEYIN3_PORT55_MARK,         PORT55_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D3_MARK,                 PORT55_FN6),
-        /* Port56 */
-        PINMUX_DATA(LCD0_D2_MARK,               PORT56_FN1),
-        PINMUX_DATA(KEYOUT5_MARK,               PORT56_FN3),
-        PINMUX_DATA(KEYIN2_PORT56_MARK,         PORT56_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D2_MARK,                 PORT56_FN6),
-        PINMUX_DATA(IRQ28_PORT56_MARK,          PORT56_FN0,     MSEL1CR_28_1),
-        /* Port57 */
-        PINMUX_DATA(LCD0_D1_MARK,               PORT57_FN1),
-        PINMUX_DATA(KEYOUT6_MARK,               PORT57_FN3),
-        PINMUX_DATA(KEYIN1_PORT57_MARK,         PORT57_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D1_MARK,                 PORT57_FN6),
-        PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
-        /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
-        PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
-        PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
-        PINMUX_DATA(IRQ26_PORT58_MARK,          PORT58_FN0,     MSEL1CR_26_1),
-        /* Port59 */
-        PINMUX_DATA(LCD0_VCPWC_MARK,            PORT59_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,    PORT59_FN2,     MSEL5CR_0_0),
-        PINMUX_DATA(RSPI_MOSI_A_MARK,           PORT59_FN6),
-        /* Port60 */
-        PINMUX_DATA(LCD0_VEPWC_MARK,            PORT60_FN1),
-        PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,     PORT60_FN2,     MSEL5CR_0_0),
-        PINMUX_DATA(RSPI_MISO_A_MARK,           PORT60_FN6),
-        /* Port61 */
-        PINMUX_DATA(LCD0_DON_MARK,              PORT61_FN1),
-        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT61_FN2),
-        /* Port62 */
-        PINMUX_DATA(LCD0_DCK_MARK,              PORT62_FN1),
-        PINMUX_DATA(LCD0_WR_MARK,               PORT62_FN4),
-        PINMUX_DATA(DV_CLK_MARK,                PORT62_FN6),
-        PINMUX_DATA(IRQ15_PORT62_MARK,          PORT62_FN0,     MSEL1CR_15_1),
-        /* Port63 */
-        PINMUX_DATA(LCD0_VSYN_MARK,             PORT63_FN1),
-        PINMUX_DATA(DV_VSYNC_MARK,              PORT63_FN6),
-        PINMUX_DATA(IRQ14_PORT63_MARK,          PORT63_FN0,     MSEL1CR_14_1),
-        /* Port64 */
-        PINMUX_DATA(LCD0_HSYN_MARK,             PORT64_FN1),
-        PINMUX_DATA(LCD0_CS_MARK,               PORT64_FN4),
-        PINMUX_DATA(DV_HSYNC_MARK,              PORT64_FN6),
-        PINMUX_DATA(IRQ13_PORT64_MARK,          PORT64_FN0,     MSEL1CR_13_1),
-        /* Port65 */
-        PINMUX_DATA(LCD0_DISP_MARK,             PORT65_FN1),
-        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT65_FN2),
-        PINMUX_DATA(LCD0_RS_MARK,               PORT65_FN4),
-        /* Port66 */
-        PINMUX_DATA(MEMC_INT_MARK,              PORT66_FN1),
-        PINMUX_DATA(TPU0TO2_PORT66_MARK,        PORT66_FN3,     MSEL5CR_25_0),
-        PINMUX_DATA(MMC0_CLK_PORT66_MARK,       PORT66_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(SDHI1_CLK_MARK,             PORT66_FN6),
-        /* Port67 - Port73 Function1 */
-        PINMUX_DATA(MEMC_CS0_MARK,              PORT67_FN1),
-        PINMUX_DATA(MEMC_AD8_MARK,              PORT68_FN1),
-        PINMUX_DATA(MEMC_AD9_MARK,              PORT69_FN1),
-        PINMUX_DATA(MEMC_AD10_MARK,             PORT70_FN1),
-        PINMUX_DATA(MEMC_AD11_MARK,             PORT71_FN1),
-        PINMUX_DATA(MEMC_AD12_MARK,             PORT72_FN1),
-        PINMUX_DATA(MEMC_AD13_MARK,             PORT73_FN1),
-        /* Port67 - Port73 Function2 */
-        PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,     PORT67_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT68_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT69_FN2),
-        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT70_FN2),
-        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT71_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,    PORT72_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,   PORT73_FN2,     MSEL4CR_10_1),
-        /* Port67 - Port73 Function4 */
-        PINMUX_DATA(MMC0_CMD_PORT67_MARK,       PORT67_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D0_PORT68_MARK,        PORT68_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D1_PORT69_MARK,        PORT69_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D2_PORT70_MARK,        PORT70_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D3_PORT71_MARK,        PORT71_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D4_PORT72_MARK,        PORT72_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D5_PORT73_MARK,        PORT73_FN4,     MSEL4CR_15_0),
-        /* Port67 - Port73 Function6 */
-        PINMUX_DATA(SDHI1_CMD_MARK,             PORT67_FN6),
-        PINMUX_DATA(SDHI1_D0_MARK,              PORT68_FN6),
-        PINMUX_DATA(SDHI1_D1_MARK,              PORT69_FN6),
-        PINMUX_DATA(SDHI1_D2_MARK,              PORT70_FN6),
-        PINMUX_DATA(SDHI1_D3_MARK,              PORT71_FN6),
-        PINMUX_DATA(SDHI1_CD_MARK,              PORT72_FN6),
-        PINMUX_DATA(SDHI1_WP_MARK,              PORT73_FN6),
-        /* Port67 - Port71 IRQ */
-        PINMUX_DATA(IRQ20_MARK,                 PORT67_FN0),
-        PINMUX_DATA(IRQ16_PORT68_MARK,          PORT68_FN0,     MSEL1CR_16_0),
-        PINMUX_DATA(IRQ17_MARK,                 PORT69_FN0),
-        PINMUX_DATA(IRQ18_MARK,                 PORT70_FN0),
-        PINMUX_DATA(IRQ19_MARK,                 PORT71_FN0),
-        /* Port74 */
-        PINMUX_DATA(MEMC_AD14_MARK,             PORT74_FN1),
-        PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,     PORT74_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MMC0_D6_PORT74_MARK,        PORT74_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(STP1_IPD7_MARK,             PORT74_FN6),
-        PINMUX_DATA(LCD1_D21_MARK,              PORT74_FN7),
-        /* Port75 */
-        PINMUX_DATA(MEMC_AD15_MARK,             PORT75_FN1),
-        PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,     PORT75_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MMC0_D7_PORT75_MARK,        PORT75_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(STP1_IPD6_MARK,             PORT75_FN6),
-        PINMUX_DATA(LCD1_D20_MARK,              PORT75_FN7),
-        /* Port76 - Port80 Function */
-        PINMUX_DATA(SDHI0_CMD_MARK,             PORT76_FN1),
-        PINMUX_DATA(SDHI0_D0_MARK,              PORT77_FN1),
-        PINMUX_DATA(SDHI0_D1_MARK,              PORT78_FN1),
-        PINMUX_DATA(SDHI0_D2_MARK,              PORT79_FN1),
-        PINMUX_DATA(SDHI0_D3_MARK,              PORT80_FN1),
-        /* Port81 */
-        PINMUX_DATA(SDHI0_CD_MARK,              PORT81_FN1),
-        PINMUX_DATA(IRQ26_PORT81_MARK,          PORT81_FN0,     MSEL1CR_26_0),
-        /* Port82 - Port88 Function */
-        PINMUX_DATA(SDHI0_CLK_MARK,             PORT82_FN1),
-        PINMUX_DATA(SDHI0_WP_MARK,              PORT83_FN1),
-        PINMUX_DATA(RESETOUTS_MARK,             PORT84_FN1),
-        PINMUX_DATA(USB0_PPON_MARK,             PORT85_FN1),
-        PINMUX_DATA(USB0_OCI_MARK,              PORT86_FN1),
-        PINMUX_DATA(USB1_PPON_MARK,             PORT87_FN1),
-        PINMUX_DATA(USB1_OCI_MARK,              PORT88_FN1),
-        /* Port89 */
-        PINMUX_DATA(DREQ0_MARK,                 PORT89_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,    PORT89_FN2,     MSEL5CR_0_1),
-        PINMUX_DATA(RSPI_SSL3_A_MARK,           PORT89_FN6),
-        /* Port90 */
-        PINMUX_DATA(DACK0_MARK,                 PORT90_FN1),
-        PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,     PORT90_FN2,     MSEL5CR_0_1),
-        PINMUX_DATA(RSPI_SSL2_A_MARK,           PORT90_FN6),
-        PINMUX_DATA(WAIT_PORT90_MARK,           PORT90_FN7,     MSEL5CR_2_1),
-        /* Port91 */
-        PINMUX_DATA(MEMC_AD0_MARK,              PORT91_FN1),
-        PINMUX_DATA(BBIF1_RXD_MARK,             PORT91_FN2),
-        PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,     PORT91_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
-        PINMUX_DATA(LCD1_D5_MARK,               PORT91_FN7),
-        /* Port92 */
-        PINMUX_DATA(MEMC_AD1_MARK,              PORT92_FN1),
-        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT92_FN2),
-        PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,     PORT92_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
-        PINMUX_DATA(STP0_IPD1_MARK,             PORT92_FN6),
-        PINMUX_DATA(LCD1_D6_MARK,               PORT92_FN7),
-        /* Port93 */
-        PINMUX_DATA(MEMC_AD2_MARK,              PORT93_FN1),
-        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT93_FN2),
-        PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,     PORT93_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
-        PINMUX_DATA(STP0_IPD3_MARK,             PORT93_FN6),
-        PINMUX_DATA(LCD1_D8_MARK,               PORT93_FN7),
-        /* Port94 */
-        PINMUX_DATA(MEMC_AD3_MARK,              PORT94_FN1),
-        PINMUX_DATA(BBIF1_TXD_MARK,             PORT94_FN2),
-        PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,     PORT94_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
-        PINMUX_DATA(STP0_IPD4_MARK,             PORT94_FN6),
-        PINMUX_DATA(LCD1_D9_MARK,               PORT94_FN7),
-        /* Port95 */
-        PINMUX_DATA(MEMC_CS1_MARK,              PORT95_FN1,     MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_A1_MARK,               PORT95_FN1,     MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_CTS_MARK,            PORT95_FN2),
-        PINMUX_DATA(SIM_RST_MARK,               PORT95_FN4),
-        PINMUX_DATA(VIO0_D14_PORT95_MARK,       PORT95_FN7,     MSEL5CR_27_1),
-        PINMUX_DATA(IRQ22_MARK,                 PORT95_FN0),
-        /* Port96 */
-        PINMUX_DATA(MEMC_ADV_MARK,              PORT96_FN1,     MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_DREQ0_MARK,            PORT96_FN1,     MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_RTS_MARK,            PORT96_FN2),
-        PINMUX_DATA(SIM_CLK_MARK,               PORT96_FN4),
-        PINMUX_DATA(VIO0_D15_PORT96_MARK,       PORT96_FN7,     MSEL5CR_27_1),
-        PINMUX_DATA(IRQ23_MARK,                 PORT96_FN0),
-        /* Port97 */
-        PINMUX_DATA(MEMC_AD4_MARK,              PORT97_FN1),
-        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT97_FN2),
-        PINMUX_DATA(LCD1_CS_MARK,               PORT97_FN6),
-        PINMUX_DATA(LCD1_HSYN_MARK,             PORT97_FN7),
-        PINMUX_DATA(IRQ12_PORT97_MARK,          PORT97_FN0,     MSEL1CR_12_0),
-        /* Port98 */
-        PINMUX_DATA(MEMC_AD5_MARK,              PORT98_FN1),
-        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT98_FN2),
-        PINMUX_DATA(LCD1_VSYN_MARK,             PORT98_FN7),
-        PINMUX_DATA(IRQ13_PORT98_MARK,          PORT98_FN0,     MSEL1CR_13_0),
-        /* Port99 */
-        PINMUX_DATA(MEMC_AD6_MARK,              PORT99_FN1),
-        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT99_FN2),
-        PINMUX_DATA(LCD1_WR_MARK,               PORT99_FN6),
-        PINMUX_DATA(LCD1_DCK_MARK,              PORT99_FN7),
-        PINMUX_DATA(IRQ14_PORT99_MARK,          PORT99_FN0,     MSEL1CR_14_0),
-        /* Port100 */
-        PINMUX_DATA(MEMC_AD7_MARK,              PORT100_FN1),
-        PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,       PORT100_FN2),
-        PINMUX_DATA(LCD1_DON_MARK,              PORT100_FN7),
-        PINMUX_DATA(IRQ15_PORT100_MARK,         PORT100_FN0,    MSEL1CR_15_0),
-        /* Port101 */
-        PINMUX_DATA(FCE0_MARK,                  PORT101_FN1),
-        /* Port102 */
-        PINMUX_DATA(FRB_MARK,                   PORT102_FN1),
-        PINMUX_DATA(LCD0_LCLK_PORT102_MARK,     PORT102_FN4,    MSEL5CR_6_0),
-        /* Port103 */
-        PINMUX_DATA(CS5B_MARK,                  PORT103_FN1),
-        PINMUX_DATA(FCE1_MARK,                  PORT103_FN2),
-        PINMUX_DATA(MMC1_CLK_PORT103_MARK,      PORT103_FN3,    MSEL4CR_15_1),
-        /* Port104 */
-        PINMUX_DATA(CS6A_MARK,                  PORT104_FN1),
-        PINMUX_DATA(MMC1_CMD_PORT104_MARK,      PORT104_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(IRQ11_MARK,                 PORT104_FN0),
-        /* Port105 */
-        PINMUX_DATA(CS5A_PORT105_MARK,          PORT105_FN1,    MSEL5CR_2_0),
-        PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,    PORT105_FN4,    MSEL5CR_8_0),
-        /* Port106 */
-        PINMUX_DATA(IOIS16_MARK,                PORT106_FN1),
-        PINMUX_DATA(IDE_EXBUF_ENB_MARK,         PORT106_FN6),
-        /* Port107 - Port115 Function */
-        PINMUX_DATA(WE3_ICIOWR_MARK,            PORT107_FN1),
-        PINMUX_DATA(WE2_ICIORD_MARK,            PORT108_FN1),
-        PINMUX_DATA(CS0_MARK,                   PORT109_FN1),
-        PINMUX_DATA(CS2_MARK,                   PORT110_FN1),
-        PINMUX_DATA(CS4_MARK,                   PORT111_FN1),
-        PINMUX_DATA(WE1_MARK,                   PORT112_FN1),
-        PINMUX_DATA(WE0_FWE_MARK,               PORT113_FN1),
-        PINMUX_DATA(RDWR_MARK,                  PORT114_FN1),
-        PINMUX_DATA(RD_FSC_MARK,                PORT115_FN1),
-        /* Port116 */
-        PINMUX_DATA(A25_MARK,                   PORT116_FN1),
-        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT116_FN2),
-        PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,    PORT116_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,    PORT116_FN4,    MSEL5CR_8_0),
-        PINMUX_DATA(GPO1_MARK,                  PORT116_FN5),
-        /* Port117 */
-        PINMUX_DATA(A24_MARK,                   PORT117_FN1),
-        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT117_FN2),
-        PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,    PORT117_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,    PORT117_FN4,    MSEL5CR_8_0),
-        PINMUX_DATA(GPO0_MARK,                  PORT117_FN5),
-        /* Port118 */
-        PINMUX_DATA(A23_MARK,                   PORT118_FN1),
-        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT118_FN2),
-        PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,    PORT118_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(GPI1_MARK,                  PORT118_FN5),
-        PINMUX_DATA(IRQ9_PORT118_MARK,          PORT118_FN0,    MSEL1CR_9_0),
-        /* Port119 */
-        PINMUX_DATA(A22_MARK,                   PORT119_FN1),
-        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT119_FN2),
-        PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,    PORT119_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(GPI0_MARK,                  PORT119_FN5),
-        PINMUX_DATA(IRQ8_MARK,                  PORT119_FN0),
-        /* Port120 */
-        PINMUX_DATA(A21_MARK,                   PORT120_FN1),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT120_FN2),
-        PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,  PORT120_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_1),
-        /* Port121 */
-        PINMUX_DATA(A20_MARK,                   PORT121_FN1),
-        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT121_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,   PORT121_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(IRQ6_PORT121_MARK,          PORT121_FN0,    MSEL1CR_6_0),
-        /* Port122 */
-        PINMUX_DATA(A19_MARK,                   PORT122_FN1),
-        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT122_FN2),
-        /* Port123 */
-        PINMUX_DATA(A18_MARK,                   PORT123_FN1),
-        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT123_FN2),
-        /* Port124 */
-        PINMUX_DATA(A17_MARK,                   PORT124_FN1),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT124_FN2),
-        /* Port125 - Port141 Function */
-        PINMUX_DATA(A16_MARK,                   PORT125_FN1),
-        PINMUX_DATA(A15_MARK,                   PORT126_FN1),
-        PINMUX_DATA(A14_MARK,                   PORT127_FN1),
-        PINMUX_DATA(A13_MARK,                   PORT128_FN1),
-        PINMUX_DATA(A12_MARK,                   PORT129_FN1),
-        PINMUX_DATA(A11_MARK,                   PORT130_FN1),
-        PINMUX_DATA(A10_MARK,                   PORT131_FN1),
-        PINMUX_DATA(A9_MARK,                    PORT132_FN1),
-        PINMUX_DATA(A8_MARK,                    PORT133_FN1),
-        PINMUX_DATA(A7_MARK,                    PORT134_FN1),
-        PINMUX_DATA(A6_MARK,                    PORT135_FN1),
-        PINMUX_DATA(A5_FCDE_MARK,               PORT136_FN1),
-        PINMUX_DATA(A4_FOE_MARK,                PORT137_FN1),
-        PINMUX_DATA(A3_MARK,                    PORT138_FN1),
-        PINMUX_DATA(A2_MARK,                    PORT139_FN1),
-        PINMUX_DATA(A1_MARK,                    PORT140_FN1),
-        PINMUX_DATA(CKO_MARK,                   PORT141_FN1),
-        /* Port142 - Port157 Function1 */
-        PINMUX_DATA(D15_NAF15_MARK,             PORT142_FN1),
-        PINMUX_DATA(D14_NAF14_MARK,             PORT143_FN1),
-        PINMUX_DATA(D13_NAF13_MARK,             PORT144_FN1),
-        PINMUX_DATA(D12_NAF12_MARK,             PORT145_FN1),
-        PINMUX_DATA(D11_NAF11_MARK,             PORT146_FN1),
-        PINMUX_DATA(D10_NAF10_MARK,             PORT147_FN1),
-        PINMUX_DATA(D9_NAF9_MARK,               PORT148_FN1),
-        PINMUX_DATA(D8_NAF8_MARK,               PORT149_FN1),
-        PINMUX_DATA(D7_NAF7_MARK,               PORT150_FN1),
-        PINMUX_DATA(D6_NAF6_MARK,               PORT151_FN1),
-        PINMUX_DATA(D5_NAF5_MARK,               PORT152_FN1),
-        PINMUX_DATA(D4_NAF4_MARK,               PORT153_FN1),
-        PINMUX_DATA(D3_NAF3_MARK,               PORT154_FN1),
-        PINMUX_DATA(D2_NAF2_MARK,               PORT155_FN1),
-        PINMUX_DATA(D1_NAF1_MARK,               PORT156_FN1),
-        PINMUX_DATA(D0_NAF0_MARK,               PORT157_FN1),
-        /* Port142 - Port149 Function3 */
-        PINMUX_DATA(MMC1_D7_PORT142_MARK,       PORT142_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D6_PORT143_MARK,       PORT143_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D5_PORT144_MARK,       PORT144_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D4_PORT145_MARK,       PORT145_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D3_PORT146_MARK,       PORT146_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D2_PORT147_MARK,       PORT147_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D1_PORT148_MARK,       PORT148_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D0_PORT149_MARK,       PORT149_FN3,    MSEL4CR_15_1),
-        /* Port158 */
-        PINMUX_DATA(D31_MARK,                   PORT158_FN1),
-        PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,    PORT158_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(RMII_REF125CK_MARK,         PORT158_FN3),
-        PINMUX_DATA(LCD0_D21_PORT158_MARK,      PORT158_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT158_FN5),
-        PINMUX_DATA(IDE_D15_MARK,               PORT158_FN6),
-        /* Port159 */
-        PINMUX_DATA(D30_MARK,                   PORT159_FN1),
-        PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,    PORT159_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(RMII_REF50CK_MARK,          PORT159_FN3),
-        PINMUX_DATA(LCD0_D23_PORT159_MARK,      PORT159_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IDE_D14_MARK,               PORT159_FN6),
-        /* Port160 */
-        PINMUX_DATA(D29_MARK,                   PORT160_FN1),
-        PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,    PORT160_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(LCD0_D22_PORT160_MARK,      PORT160_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(VIO1_HD_MARK,               PORT160_FN5),
-        PINMUX_DATA(IDE_D13_MARK,               PORT160_FN6),
-        /* Port161 */
-        PINMUX_DATA(D28_MARK,                   PORT161_FN1),
-        PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,    PORT161_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(ET_RX_DV_MARK,              PORT161_FN3),
-        PINMUX_DATA(LCD0_D20_PORT161_MARK,      PORT161_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_IN_MARK,               PORT161_FN5),
-        PINMUX_DATA(IDE_D12_MARK,               PORT161_FN6),
-        /* Port162 */
-        PINMUX_DATA(D27_MARK,                   PORT162_FN1),
-        PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,    PORT162_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(LCD0_D19_PORT162_MARK,      PORT162_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_OUT_MARK,              PORT162_FN5),
-        PINMUX_DATA(IDE_D11_MARK,               PORT162_FN6),
-        /* Port163 */
-        PINMUX_DATA(D26_MARK,                   PORT163_FN1),
-        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT163_FN2),
-        PINMUX_DATA(ET_COL_MARK,                PORT163_FN3),
-        PINMUX_DATA(LCD0_D18_PORT163_MARK,      PORT163_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IROUT_MARK,                 PORT163_FN5),
-        PINMUX_DATA(IDE_D10_MARK,               PORT163_FN6),
-        /* Port164 */
-        PINMUX_DATA(D25_MARK,                   PORT164_FN1),
-        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT164_FN2),
-        PINMUX_DATA(ET_PHY_INT_MARK,            PORT164_FN3),
-        PINMUX_DATA(LCD0_RD_MARK,               PORT164_FN4),
-        PINMUX_DATA(IDE_D9_MARK,                PORT164_FN6),
-        /* Port165 */
-        PINMUX_DATA(D24_MARK,                   PORT165_FN1),
-        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT165_FN2),
-        PINMUX_DATA(LCD0_LCLK_PORT165_MARK,     PORT165_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IDE_D8_MARK,                PORT165_FN6),
-        /* Port166 - Port171 Function1 */
-        PINMUX_DATA(D21_MARK,                   PORT166_FN1),
-        PINMUX_DATA(D20_MARK,                   PORT167_FN1),
-        PINMUX_DATA(D19_MARK,                   PORT168_FN1),
-        PINMUX_DATA(D18_MARK,                   PORT169_FN1),
-        PINMUX_DATA(D17_MARK,                   PORT170_FN1),
-        PINMUX_DATA(D16_MARK,                   PORT171_FN1),
-        /* Port166 - Port171 Function3 */
-        PINMUX_DATA(ET_ETXD5_MARK,              PORT166_FN3),
-        PINMUX_DATA(ET_ETXD4_MARK,              PORT167_FN3),
-        PINMUX_DATA(ET_ETXD3_MARK,              PORT168_FN3),
-        PINMUX_DATA(ET_ETXD2_MARK,              PORT169_FN3),
-        PINMUX_DATA(ET_ETXD1_MARK,              PORT170_FN3),
-        PINMUX_DATA(ET_ETXD0_MARK,              PORT171_FN3),
-        /* Port166 - Port171 Function6 */
-        PINMUX_DATA(IDE_D5_MARK,                PORT166_FN6),
-        PINMUX_DATA(IDE_D4_MARK,                PORT167_FN6),
-        PINMUX_DATA(IDE_D3_MARK,                PORT168_FN6),
-        PINMUX_DATA(IDE_D2_MARK,                PORT169_FN6),
-        PINMUX_DATA(IDE_D1_MARK,                PORT170_FN6),
-        PINMUX_DATA(IDE_D0_MARK,                PORT171_FN6),
-        /* Port167 - Port171 IRQ */
-        PINMUX_DATA(IRQ31_PORT167_MARK,         PORT167_FN0,    MSEL1CR_31_0),
-        PINMUX_DATA(IRQ27_PORT168_MARK,         PORT168_FN0,    MSEL1CR_27_0),
-        PINMUX_DATA(IRQ28_PORT169_MARK,         PORT169_FN0,    MSEL1CR_28_0),
-        PINMUX_DATA(IRQ29_PORT170_MARK,         PORT170_FN0,    MSEL1CR_29_0),
-        PINMUX_DATA(IRQ30_PORT171_MARK,         PORT171_FN0,    MSEL1CR_30_0),
-        /* Port172 */
-        PINMUX_DATA(D23_MARK,                   PORT172_FN1),
-        PINMUX_DATA(SCIFB_RTS_PORT172_MARK,     PORT172_FN2,    MSEL5CR_17_1),
-        PINMUX_DATA(ET_ETXD7_MARK,              PORT172_FN3),
-        PINMUX_DATA(IDE_D7_MARK,                PORT172_FN6),
-        PINMUX_DATA(IRQ4_PORT172_MARK,          PORT172_FN0,    MSEL1CR_4_1),
-        /* Port173 */
-        PINMUX_DATA(D22_MARK,                   PORT173_FN1),
-        PINMUX_DATA(SCIFB_CTS_PORT173_MARK,     PORT173_FN2,    MSEL5CR_17_1),
-        PINMUX_DATA(ET_ETXD6_MARK,              PORT173_FN3),
-        PINMUX_DATA(IDE_D6_MARK,                PORT173_FN6),
-        PINMUX_DATA(IRQ6_PORT173_MARK,          PORT173_FN0,    MSEL1CR_6_1),
-        /* Port174 */
-        PINMUX_DATA(A26_MARK,                   PORT174_FN1),
-        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT174_FN2),
-        PINMUX_DATA(ET_RX_CLK_MARK,             PORT174_FN3),
-        PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,    PORT174_FN4,    MSEL5CR_8_0),
-        /* Port175 */
-        PINMUX_DATA(A0_MARK,                    PORT175_FN1),
-        PINMUX_DATA(BS_MARK,                    PORT175_FN2),
-        PINMUX_DATA(ET_WOL_MARK,                PORT175_FN3),
-        PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,    PORT175_FN4,    MSEL5CR_8_0),
-        /* Port176 */
-        PINMUX_DATA(ET_GTX_CLK_MARK,            PORT176_FN3),
-        /* Port177 */
-        PINMUX_DATA(WAIT_PORT177_MARK,          PORT177_FN1,    MSEL5CR_2_0),
-        PINMUX_DATA(ET_LINK_MARK,               PORT177_FN3),
-        PINMUX_DATA(IDE_IOWR_MARK,              PORT177_FN6),
-        PINMUX_DATA(SDHI2_WP_PORT177_MARK,      PORT177_FN7,    MSEL5CR_19_1),
-        /* Port178 */
-        PINMUX_DATA(VIO0_D12_MARK,              PORT178_FN1),
-        PINMUX_DATA(VIO1_D4_MARK,               PORT178_FN5),
-        PINMUX_DATA(IDE_IORD_MARK,              PORT178_FN6),
-        /* Port179 */
-        PINMUX_DATA(VIO0_D11_MARK,              PORT179_FN1),
-        PINMUX_DATA(VIO1_D3_MARK,               PORT179_FN5),
-        PINMUX_DATA(IDE_IORDY_MARK,             PORT179_FN6),
-        /* Port180 */
-        PINMUX_DATA(VIO0_D10_MARK,              PORT180_FN1),
-        PINMUX_DATA(TPU0TO3_MARK,               PORT180_FN4),
-        PINMUX_DATA(VIO1_D2_MARK,               PORT180_FN5),
-        PINMUX_DATA(IDE_INT_MARK,               PORT180_FN6),
-        PINMUX_DATA(IRQ24_MARK,                 PORT180_FN0),
-        /* Port181 */
-        PINMUX_DATA(VIO0_D9_MARK,               PORT181_FN1),
-        PINMUX_DATA(VIO1_D1_MARK,               PORT181_FN5),
-        PINMUX_DATA(IDE_RST_MARK,               PORT181_FN6),
-        /* Port182 */
-        PINMUX_DATA(VIO0_D8_MARK,               PORT182_FN1),
-        PINMUX_DATA(VIO1_D0_MARK,               PORT182_FN5),
-        PINMUX_DATA(IDE_DIRECTION_MARK,         PORT182_FN6),
-        /* Port183 */
-        PINMUX_DATA(DREQ1_MARK,                 PORT183_FN1),
-        PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,    PORT183_FN2,    MSEL5CR_0_1),
-        PINMUX_DATA(ET_TX_EN_MARK,              PORT183_FN3),
-        /* Port184 */
-        PINMUX_DATA(DACK1_MARK,                 PORT184_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,  PORT184_FN2,    MSEL5CR_0_1),
-        PINMUX_DATA(ET_TX_CLK_MARK,             PORT184_FN3),
-        /* Port185 - Port192 Function1 */
-        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT185_FN1),
-        PINMUX_DATA(SCIFB_RTS_PORT186_MARK,     PORT186_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_CTS_PORT187_MARK,     PORT187_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT188_FN1),
-        PINMUX_DATA(SCIFB_SCK_PORT190_MARK,     PORT190_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_RXD_PORT191_MARK,     PORT191_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_TXD_PORT192_MARK,     PORT192_FN1,    MSEL5CR_17_0),
-        /* Port185 - Port192 Function3 */
-        PINMUX_DATA(ET_ERXD0_MARK,              PORT185_FN3),
-        PINMUX_DATA(ET_ERXD1_MARK,              PORT186_FN3),
-        PINMUX_DATA(ET_ERXD2_MARK,              PORT187_FN3),
-        PINMUX_DATA(ET_ERXD3_MARK,              PORT188_FN3),
-        PINMUX_DATA(ET_ERXD4_MARK,              PORT189_FN3),
-        PINMUX_DATA(ET_ERXD5_MARK,              PORT190_FN3),
-        PINMUX_DATA(ET_ERXD6_MARK,              PORT191_FN3),
-        PINMUX_DATA(ET_ERXD7_MARK,              PORT192_FN3),
-        /* Port185 - Port192 Function6 */
-        PINMUX_DATA(STP1_IPCLK_MARK,            PORT185_FN6),
-        PINMUX_DATA(STP1_IPD0_PORT186_MARK,     PORT186_FN6,    MSEL5CR_23_0),
-        PINMUX_DATA(STP1_IPEN_PORT187_MARK,     PORT187_FN6,    MSEL5CR_23_0),
-        PINMUX_DATA(STP1_IPSYNC_MARK,           PORT188_FN6),
-        PINMUX_DATA(STP0_IPCLK_MARK,            PORT189_FN6),
-        PINMUX_DATA(STP0_IPD0_MARK,             PORT190_FN6),
-        PINMUX_DATA(STP0_IPEN_MARK,             PORT191_FN6),
-        PINMUX_DATA(STP0_IPSYNC_MARK,           PORT192_FN6),
-        /* Port193 */
-        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT193_FN1),
-        PINMUX_DATA(RMII_CRS_DV_MARK,           PORT193_FN3),
-        PINMUX_DATA(STP1_IPEN_PORT193_MARK,     PORT193_FN6,    MSEL5CR_23_1), /* ? */
-        PINMUX_DATA(LCD1_D17_MARK,              PORT193_FN7),
-        /* Port194 */
-        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT194_FN1),
-        PINMUX_DATA(RMII_RX_ER_MARK,            PORT194_FN3),
-        PINMUX_DATA(STP1_IPD0_PORT194_MARK,     PORT194_FN6,    MSEL5CR_23_1), /* ? */
-        PINMUX_DATA(LCD1_D16_MARK,              PORT194_FN7),
-        /* Port195 */
-        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT195_FN1),
-        PINMUX_DATA(RMII_RXD0_MARK,             PORT195_FN3),
-        PINMUX_DATA(STP1_IPD3_MARK,             PORT195_FN6),
-        PINMUX_DATA(LCD1_D15_MARK,              PORT195_FN7),
-        /* Port196 */
-        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT196_FN1),
-        PINMUX_DATA(RMII_RXD1_MARK,             PORT196_FN3),
-        PINMUX_DATA(STP1_IPD2_MARK,             PORT196_FN6),
-        PINMUX_DATA(LCD1_D14_MARK,              PORT196_FN7),
-        /* Port197 */
-        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT197_FN1),
-        PINMUX_DATA(VIO1_CLK_MARK,              PORT197_FN5),
-        PINMUX_DATA(STP1_IPD5_MARK,             PORT197_FN6),
-        PINMUX_DATA(LCD1_D19_MARK,              PORT197_FN7),
-        /* Port198 */
-        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT198_FN1),
-        PINMUX_DATA(VIO1_VD_MARK,               PORT198_FN5),
-        PINMUX_DATA(STP1_IPD4_MARK,             PORT198_FN6),
-        PINMUX_DATA(LCD1_D18_MARK,              PORT198_FN7),
-        /* Port199 */
-        PINMUX_DATA(MEMC_NWE_MARK,              PORT199_FN1),
-        PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,    PORT199_FN2,    MSEL5CR_7_1),
-        PINMUX_DATA(RMII_TX_EN_MARK,            PORT199_FN3),
-        PINMUX_DATA(SIM_D_PORT199_MARK,         PORT199_FN4,    MSEL5CR_21_1),
-        PINMUX_DATA(STP1_IPD1_MARK,             PORT199_FN6),
-        PINMUX_DATA(LCD1_D13_MARK,              PORT199_FN7),
-        /* Port200 */
-        PINMUX_DATA(MEMC_NOE_MARK,              PORT200_FN1),
-        PINMUX_DATA(SCIFA2_RXD_MARK,            PORT200_FN2),
-        PINMUX_DATA(RMII_TXD0_MARK,             PORT200_FN3),
-        PINMUX_DATA(STP0_IPD7_MARK,             PORT200_FN6),
-        PINMUX_DATA(LCD1_D12_MARK,              PORT200_FN7),
-        /* Port201 */
-        PINMUX_DATA(MEMC_WAIT_MARK,             PORT201_FN1,    MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_DREQ1_MARK,            PORT201_FN1,    MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_TXD_MARK,            PORT201_FN2),
-        PINMUX_DATA(RMII_TXD1_MARK,             PORT201_FN3),
-        PINMUX_DATA(STP0_IPD6_MARK,             PORT201_FN6),
-        PINMUX_DATA(LCD1_D11_MARK,              PORT201_FN7),
-        /* Port202 */
-        PINMUX_DATA(MEMC_BUSCLK_MARK,           PORT202_FN1,    MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_A0_MARK,               PORT202_FN1,    MSEL4CR_6_1),
-        PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,    PORT202_FN2,    MSEL4CR_10_1),
-        PINMUX_DATA(RMII_MDC_MARK,              PORT202_FN3),
-        PINMUX_DATA(TPU0TO2_PORT202_MARK,       PORT202_FN4,    MSEL5CR_25_1),
-        PINMUX_DATA(IDE_CS0_MARK,               PORT202_FN6),
-        PINMUX_DATA(SDHI2_CD_PORT202_MARK,      PORT202_FN7,    MSEL5CR_19_1),
-        PINMUX_DATA(IRQ21_MARK,                 PORT202_FN0),
-        /* Port203 - Port208 Function1 */
-        PINMUX_DATA(SDHI2_CLK_MARK,             PORT203_FN1),
-        PINMUX_DATA(SDHI2_CMD_MARK,             PORT204_FN1),
-        PINMUX_DATA(SDHI2_D0_MARK,              PORT205_FN1),
-        PINMUX_DATA(SDHI2_D1_MARK,              PORT206_FN1),
-        PINMUX_DATA(SDHI2_D2_MARK,              PORT207_FN1),
-        PINMUX_DATA(SDHI2_D3_MARK,              PORT208_FN1),
-        /* Port203 - Port208 Function3 */
-        PINMUX_DATA(ET_TX_ER_MARK,              PORT203_FN3),
-        PINMUX_DATA(ET_RX_ER_MARK,              PORT204_FN3),
-        PINMUX_DATA(ET_CRS_MARK,                PORT205_FN3),
-        PINMUX_DATA(ET_MDC_MARK,                PORT206_FN3),
-        PINMUX_DATA(ET_MDIO_MARK,               PORT207_FN3),
-        PINMUX_DATA(RMII_MDIO_MARK,             PORT208_FN3),
-        /* Port203 - Port208 Function6 */
-        PINMUX_DATA(IDE_A2_MARK,                PORT203_FN6),
-        PINMUX_DATA(IDE_A1_MARK,                PORT204_FN6),
-        PINMUX_DATA(IDE_A0_MARK,                PORT205_FN6),
-        PINMUX_DATA(IDE_IODACK_MARK,            PORT206_FN6),
-        PINMUX_DATA(IDE_IODREQ_MARK,            PORT207_FN6),
-        PINMUX_DATA(IDE_CS1_MARK,               PORT208_FN6),
-        /* Port203 - Port208 Function7 */
-        PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,    PORT203_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
-        PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,    PORT204_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
-        PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,    PORT205_FN7,    MSEL5CR_10_1),
-        PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,    PORT206_FN7,    MSEL5CR_13_1),
-        PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,    PORT207_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
-        PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,    PORT208_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
-        /* Port209 */
-        PINMUX_DATA(VBUS_MARK,                  PORT209_FN1),
-        PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_0),
-        /* Port210 */
-        PINMUX_DATA(IRQ9_PORT210_MARK,          PORT210_FN0,    MSEL1CR_9_1),
-        PINMUX_DATA(HDMI_HPD_MARK,              PORT210_FN1),
-        /* Port211 */
-        PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
-        PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-        /* SDENC */
-        PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
-        PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
-        /* SYSC */
-        PINMUX_DATA(RESETP_PULLUP_MARK,                         MSEL4CR_4_0),
-        PINMUX_DATA(RESETP_PLAIN_MARK,                          MSEL4CR_4_1),
-        /* DEBUG */
-        PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,                     MSEL4CR_1_0),
-        PINMUX_DATA(EDEBGREQ_PULLUP_MARK,                       MSEL4CR_1_1),
-        PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,                     MSEL5CR_30_0,   MSEL5CR_29_0),
-        PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,                   MSEL5CR_30_0,   MSEL5CR_29_1),
-        PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* PORT */
-        GPIO_PORT_ALL(),
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-        /* Function */
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-        /* LCD0 */
-        GPIO_FN(LCD0_D0),       GPIO_FN(LCD0_D1),       GPIO_FN(LCD0_D2),
-        GPIO_FN(LCD0_D3),       GPIO_FN(LCD0_D4),       GPIO_FN(LCD0_D5),
-        GPIO_FN(LCD0_D6),       GPIO_FN(LCD0_D7),       GPIO_FN(LCD0_D8),
-        GPIO_FN(LCD0_D9),       GPIO_FN(LCD0_D10),      GPIO_FN(LCD0_D11),
-        GPIO_FN(LCD0_D12),      GPIO_FN(LCD0_D13),      GPIO_FN(LCD0_D14),
-        GPIO_FN(LCD0_D15),      GPIO_FN(LCD0_D16),      GPIO_FN(LCD0_D17),
-        GPIO_FN(LCD0_DON),      GPIO_FN(LCD0_VCPWC),    GPIO_FN(LCD0_VEPWC),
-        GPIO_FN(LCD0_DCK),      GPIO_FN(LCD0_VSYN),
-        GPIO_FN(LCD0_HSYN),     GPIO_FN(LCD0_DISP),
-        GPIO_FN(LCD0_WR),       GPIO_FN(LCD0_RD),
-        GPIO_FN(LCD0_CS),       GPIO_FN(LCD0_RS),
-        GPIO_FN(LCD0_D18_PORT163),      GPIO_FN(LCD0_D19_PORT162),
-        GPIO_FN(LCD0_D20_PORT161),      GPIO_FN(LCD0_D21_PORT158),
-        GPIO_FN(LCD0_D22_PORT160),      GPIO_FN(LCD0_D23_PORT159),
-        GPIO_FN(LCD0_LCLK_PORT165),     /* MSEL5CR_6_1 */
-        GPIO_FN(LCD0_D18_PORT40),       GPIO_FN(LCD0_D19_PORT4),
-        GPIO_FN(LCD0_D20_PORT3),        GPIO_FN(LCD0_D21_PORT2),
-        GPIO_FN(LCD0_D22_PORT0),        GPIO_FN(LCD0_D23_PORT1),
-        GPIO_FN(LCD0_LCLK_PORT102),     /* MSEL5CR_6_0 */
-        /* LCD1 */
-        GPIO_FN(LCD1_D0),       GPIO_FN(LCD1_D1),       GPIO_FN(LCD1_D2),
-        GPIO_FN(LCD1_D3),       GPIO_FN(LCD1_D4),       GPIO_FN(LCD1_D5),
-        GPIO_FN(LCD1_D6),       GPIO_FN(LCD1_D7),       GPIO_FN(LCD1_D8),
-        GPIO_FN(LCD1_D9),       GPIO_FN(LCD1_D10),      GPIO_FN(LCD1_D11),
-        GPIO_FN(LCD1_D12),      GPIO_FN(LCD1_D13),      GPIO_FN(LCD1_D14),
-        GPIO_FN(LCD1_D15),      GPIO_FN(LCD1_D16),      GPIO_FN(LCD1_D17),
-        GPIO_FN(LCD1_D18),      GPIO_FN(LCD1_D19),      GPIO_FN(LCD1_D20),
-        GPIO_FN(LCD1_D21),      GPIO_FN(LCD1_D22),      GPIO_FN(LCD1_D23),
-        GPIO_FN(LCD1_RS),       GPIO_FN(LCD1_RD),       GPIO_FN(LCD1_CS),
-        GPIO_FN(LCD1_WR),       GPIO_FN(LCD1_DCK),      GPIO_FN(LCD1_DON),
-        GPIO_FN(LCD1_VCPWC),    GPIO_FN(LCD1_LCLK),     GPIO_FN(LCD1_HSYN),
-        GPIO_FN(LCD1_VSYN),     GPIO_FN(LCD1_VEPWC),    GPIO_FN(LCD1_DISP),
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-        /* SDHI0 */
-        GPIO_FN(SDHI0_D0),      GPIO_FN(SDHI0_D1),      GPIO_FN(SDHI0_D2),
-        GPIO_FN(SDHI0_D3),      GPIO_FN(SDHI0_CD),      GPIO_FN(SDHI0_WP),
-        GPIO_FN(SDHI0_CMD),     GPIO_FN(SDHI0_CLK),
-        /* SDHI1 */
-        GPIO_FN(SDHI1_D0),      GPIO_FN(SDHI1_D1),      GPIO_FN(SDHI1_D2),
-        GPIO_FN(SDHI1_D3),      GPIO_FN(SDHI1_CD),      GPIO_FN(SDHI1_WP),
-        GPIO_FN(SDHI1_CMD),     GPIO_FN(SDHI1_CLK),
-        /* SDHI2 */
-        GPIO_FN(SDHI2_D0),      GPIO_FN(SDHI2_D1),      GPIO_FN(SDHI2_D2),
-        GPIO_FN(SDHI2_D3),      GPIO_FN(SDHI2_CLK),     GPIO_FN(SDHI2_CMD),
-        GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
-        GPIO_FN(SDHI2_WP_PORT25),
-        GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
-        GPIO_FN(SDHI2_CD_PORT202),
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-        /* MMC */
-        GPIO_FN(MMC0_D0_PORT68),        GPIO_FN(MMC0_D1_PORT69),
-        GPIO_FN(MMC0_D2_PORT70),        GPIO_FN(MMC0_D3_PORT71),
-        GPIO_FN(MMC0_D4_PORT72),        GPIO_FN(MMC0_D5_PORT73),
-        GPIO_FN(MMC0_D6_PORT74),        GPIO_FN(MMC0_D7_PORT75),
-        GPIO_FN(MMC0_CLK_PORT66),
-        GPIO_FN(MMC0_CMD_PORT67),       /* MSEL4CR_15_0 */
-        GPIO_FN(MMC1_D0_PORT149),       GPIO_FN(MMC1_D1_PORT148),
-        GPIO_FN(MMC1_D2_PORT147),       GPIO_FN(MMC1_D3_PORT146),
-        GPIO_FN(MMC1_D4_PORT145),       GPIO_FN(MMC1_D5_PORT144),
-        GPIO_FN(MMC1_D6_PORT143),       GPIO_FN(MMC1_D7_PORT142),
-        GPIO_FN(MMC1_CLK_PORT103),
-        GPIO_FN(MMC1_CMD_PORT104),      /* MSEL4CR_15_1 */
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-        /* IRREM */
-        GPIO_FN(IROUT),
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0,       0xe6050000), /* PORT0CR */
-        PORTCR(1,       0xe6050001), /* PORT1CR */
-        PORTCR(2,       0xe6050002), /* PORT2CR */
-        PORTCR(3,       0xe6050003), /* PORT3CR */
-        PORTCR(4,       0xe6050004), /* PORT4CR */
-        PORTCR(5,       0xe6050005), /* PORT5CR */
-        PORTCR(6,       0xe6050006), /* PORT6CR */
-        PORTCR(7,       0xe6050007), /* PORT7CR */
-        PORTCR(8,       0xe6050008), /* PORT8CR */
-        PORTCR(9,       0xe6050009), /* PORT9CR */
-        PORTCR(10,      0xe605000a), /* PORT10CR */
-        PORTCR(11,      0xe605000b), /* PORT11CR */
-        PORTCR(12,      0xe605000c), /* PORT12CR */
-        PORTCR(13,      0xe605000d), /* PORT13CR */
-        PORTCR(14,      0xe605000e), /* PORT14CR */
-        PORTCR(15,      0xe605000f), /* PORT15CR */
-        PORTCR(16,      0xe6050010), /* PORT16CR */
-        PORTCR(17,      0xe6050011), /* PORT17CR */
-        PORTCR(18,      0xe6050012), /* PORT18CR */
-        PORTCR(19,      0xe6050013), /* PORT19CR */
-        PORTCR(20,      0xe6050014), /* PORT20CR */
-        PORTCR(21,      0xe6050015), /* PORT21CR */
-        PORTCR(22,      0xe6050016), /* PORT22CR */
-        PORTCR(23,      0xe6050017), /* PORT23CR */
-        PORTCR(24,      0xe6050018), /* PORT24CR */
-        PORTCR(25,      0xe6050019), /* PORT25CR */
-        PORTCR(26,      0xe605001a), /* PORT26CR */
-        PORTCR(27,      0xe605001b), /* PORT27CR */
-        PORTCR(28,      0xe605001c), /* PORT28CR */
-        PORTCR(29,      0xe605001d), /* PORT29CR */
-        PORTCR(30,      0xe605001e), /* PORT30CR */
-        PORTCR(31,      0xe605001f), /* PORT31CR */
-        PORTCR(32,      0xe6050020), /* PORT32CR */
-        PORTCR(33,      0xe6050021), /* PORT33CR */
-        PORTCR(34,      0xe6050022), /* PORT34CR */
-        PORTCR(35,      0xe6050023), /* PORT35CR */
-        PORTCR(36,      0xe6050024), /* PORT36CR */
-        PORTCR(37,      0xe6050025), /* PORT37CR */
-        PORTCR(38,      0xe6050026), /* PORT38CR */
-        PORTCR(39,      0xe6050027), /* PORT39CR */
-        PORTCR(40,      0xe6050028), /* PORT40CR */
-        PORTCR(41,      0xe6050029), /* PORT41CR */
-        PORTCR(42,      0xe605002a), /* PORT42CR */
-        PORTCR(43,      0xe605002b), /* PORT43CR */
-        PORTCR(44,      0xe605002c), /* PORT44CR */
-        PORTCR(45,      0xe605002d), /* PORT45CR */
-        PORTCR(46,      0xe605002e), /* PORT46CR */
-        PORTCR(47,      0xe605002f), /* PORT47CR */
-        PORTCR(48,      0xe6050030), /* PORT48CR */
-        PORTCR(49,      0xe6050031), /* PORT49CR */
-        PORTCR(50,      0xe6050032), /* PORT50CR */
-        PORTCR(51,      0xe6050033), /* PORT51CR */
-        PORTCR(52,      0xe6050034), /* PORT52CR */
-        PORTCR(53,      0xe6050035), /* PORT53CR */
-        PORTCR(54,      0xe6050036), /* PORT54CR */
-        PORTCR(55,      0xe6050037), /* PORT55CR */
-        PORTCR(56,      0xe6050038), /* PORT56CR */
-        PORTCR(57,      0xe6050039), /* PORT57CR */
-        PORTCR(58,      0xe605003a), /* PORT58CR */
-        PORTCR(59,      0xe605003b), /* PORT59CR */
-        PORTCR(60,      0xe605003c), /* PORT60CR */
-        PORTCR(61,      0xe605003d), /* PORT61CR */
-        PORTCR(62,      0xe605003e), /* PORT62CR */
-        PORTCR(63,      0xe605003f), /* PORT63CR */
-        PORTCR(64,      0xe6050040), /* PORT64CR */
-        PORTCR(65,      0xe6050041), /* PORT65CR */
-        PORTCR(66,      0xe6050042), /* PORT66CR */
-        PORTCR(67,      0xe6050043), /* PORT67CR */
-        PORTCR(68,      0xe6050044), /* PORT68CR */
-        PORTCR(69,      0xe6050045), /* PORT69CR */
-        PORTCR(70,      0xe6050046), /* PORT70CR */
-        PORTCR(71,      0xe6050047), /* PORT71CR */
-        PORTCR(72,      0xe6050048), /* PORT72CR */
-        PORTCR(73,      0xe6050049), /* PORT73CR */
-        PORTCR(74,      0xe605004a), /* PORT74CR */
-        PORTCR(75,      0xe605004b), /* PORT75CR */
-        PORTCR(76,      0xe605004c), /* PORT76CR */
-        PORTCR(77,      0xe605004d), /* PORT77CR */
-        PORTCR(78,      0xe605004e), /* PORT78CR */
-        PORTCR(79,      0xe605004f), /* PORT79CR */
-        PORTCR(80,      0xe6050050), /* PORT80CR */
-        PORTCR(81,      0xe6050051), /* PORT81CR */
-        PORTCR(82,      0xe6050052), /* PORT82CR */
-        PORTCR(83,      0xe6050053), /* PORT83CR */
-        PORTCR(84,      0xe6051054), /* PORT84CR */
-        PORTCR(85,      0xe6051055), /* PORT85CR */
-        PORTCR(86,      0xe6051056), /* PORT86CR */
-        PORTCR(87,      0xe6051057), /* PORT87CR */
-        PORTCR(88,      0xe6051058), /* PORT88CR */
-        PORTCR(89,      0xe6051059), /* PORT89CR */
-        PORTCR(90,      0xe605105a), /* PORT90CR */
-        PORTCR(91,      0xe605105b), /* PORT91CR */
-        PORTCR(92,      0xe605105c), /* PORT92CR */
-        PORTCR(93,      0xe605105d), /* PORT93CR */
-        PORTCR(94,      0xe605105e), /* PORT94CR */
-        PORTCR(95,      0xe605105f), /* PORT95CR */
-        PORTCR(96,      0xe6051060), /* PORT96CR */
-        PORTCR(97,      0xe6051061), /* PORT97CR */
-        PORTCR(98,      0xe6051062), /* PORT98CR */
-        PORTCR(99,      0xe6051063), /* PORT99CR */
-        PORTCR(100,     0xe6051064), /* PORT100CR */
-        PORTCR(101,     0xe6051065), /* PORT101CR */
-        PORTCR(102,     0xe6051066), /* PORT102CR */
-        PORTCR(103,     0xe6051067), /* PORT103CR */
-        PORTCR(104,     0xe6051068), /* PORT104CR */
-        PORTCR(105,     0xe6051069), /* PORT105CR */
-        PORTCR(106,     0xe605106a), /* PORT106CR */
-        PORTCR(107,     0xe605106b), /* PORT107CR */
-        PORTCR(108,     0xe605106c), /* PORT108CR */
-        PORTCR(109,     0xe605106d), /* PORT109CR */
-        PORTCR(110,     0xe605106e), /* PORT110CR */
-        PORTCR(111,     0xe605106f), /* PORT111CR */
-        PORTCR(112,     0xe6051070), /* PORT112CR */
-        PORTCR(113,     0xe6051071), /* PORT113CR */
-        PORTCR(114,     0xe6051072), /* PORT114CR */
-        PORTCR(115,     0xe6052073), /* PORT115CR */
-        PORTCR(116,     0xe6052074), /* PORT116CR */
-        PORTCR(117,     0xe6052075), /* PORT117CR */
-        PORTCR(118,     0xe6052076), /* PORT118CR */
-        PORTCR(119,     0xe6052077), /* PORT119CR */
-        PORTCR(120,     0xe6052078), /* PORT120CR */
-        PORTCR(121,     0xe6052079), /* PORT121CR */
-        PORTCR(122,     0xe605207a), /* PORT122CR */
-        PORTCR(123,     0xe605207b), /* PORT123CR */
-        PORTCR(124,     0xe605207c), /* PORT124CR */
-        PORTCR(125,     0xe605207d), /* PORT125CR */
-        PORTCR(126,     0xe605207e), /* PORT126CR */
-        PORTCR(127,     0xe605207f), /* PORT127CR */
-        PORTCR(128,     0xe6052080), /* PORT128CR */
-        PORTCR(129,     0xe6052081), /* PORT129CR */
-        PORTCR(130,     0xe6052082), /* PORT130CR */
-        PORTCR(131,     0xe6052083), /* PORT131CR */
-        PORTCR(132,     0xe6052084), /* PORT132CR */
-        PORTCR(133,     0xe6052085), /* PORT133CR */
-        PORTCR(134,     0xe6052086), /* PORT134CR */
-        PORTCR(135,     0xe6052087), /* PORT135CR */
-        PORTCR(136,     0xe6052088), /* PORT136CR */
-        PORTCR(137,     0xe6052089), /* PORT137CR */
-        PORTCR(138,     0xe605208a), /* PORT138CR */
-        PORTCR(139,     0xe605208b), /* PORT139CR */
-        PORTCR(140,     0xe605208c), /* PORT140CR */
-        PORTCR(141,     0xe605208d), /* PORT141CR */
-        PORTCR(142,     0xe605208e), /* PORT142CR */
-        PORTCR(143,     0xe605208f), /* PORT143CR */
-        PORTCR(144,     0xe6052090), /* PORT144CR */
-        PORTCR(145,     0xe6052091), /* PORT145CR */
-        PORTCR(146,     0xe6052092), /* PORT146CR */
-        PORTCR(147,     0xe6052093), /* PORT147CR */
-        PORTCR(148,     0xe6052094), /* PORT148CR */
-        PORTCR(149,     0xe6052095), /* PORT149CR */
-        PORTCR(150,     0xe6052096), /* PORT150CR */
-        PORTCR(151,     0xe6052097), /* PORT151CR */
-        PORTCR(152,     0xe6052098), /* PORT152CR */
-        PORTCR(153,     0xe6052099), /* PORT153CR */
-        PORTCR(154,     0xe605209a), /* PORT154CR */
-        PORTCR(155,     0xe605209b), /* PORT155CR */
-        PORTCR(156,     0xe605209c), /* PORT156CR */
-        PORTCR(157,     0xe605209d), /* PORT157CR */
-        PORTCR(158,     0xe605209e), /* PORT158CR */
-        PORTCR(159,     0xe605209f), /* PORT159CR */
-        PORTCR(160,     0xe60520a0), /* PORT160CR */
-        PORTCR(161,     0xe60520a1), /* PORT161CR */
-        PORTCR(162,     0xe60520a2), /* PORT162CR */
-        PORTCR(163,     0xe60520a3), /* PORT163CR */
-        PORTCR(164,     0xe60520a4), /* PORT164CR */
-        PORTCR(165,     0xe60520a5), /* PORT165CR */
-        PORTCR(166,     0xe60520a6), /* PORT166CR */
-        PORTCR(167,     0xe60520a7), /* PORT167CR */
-        PORTCR(168,     0xe60520a8), /* PORT168CR */
-        PORTCR(169,     0xe60520a9), /* PORT169CR */
-        PORTCR(170,     0xe60520aa), /* PORT170CR */
-        PORTCR(171,     0xe60520ab), /* PORT171CR */
-        PORTCR(172,     0xe60520ac), /* PORT172CR */
-        PORTCR(173,     0xe60520ad), /* PORT173CR */
-        PORTCR(174,     0xe60520ae), /* PORT174CR */
-        PORTCR(175,     0xe60520af), /* PORT175CR */
-        PORTCR(176,     0xe60520b0), /* PORT176CR */
-        PORTCR(177,     0xe60520b1), /* PORT177CR */
-        PORTCR(178,     0xe60520b2), /* PORT178CR */
-        PORTCR(179,     0xe60520b3), /* PORT179CR */
-        PORTCR(180,     0xe60520b4), /* PORT180CR */
-        PORTCR(181,     0xe60520b5), /* PORT181CR */
-        PORTCR(182,     0xe60520b6), /* PORT182CR */
-        PORTCR(183,     0xe60520b7), /* PORT183CR */
-        PORTCR(184,     0xe60520b8), /* PORT184CR */
-        PORTCR(185,     0xe60520b9), /* PORT185CR */
-        PORTCR(186,     0xe60520ba), /* PORT186CR */
-        PORTCR(187,     0xe60520bb), /* PORT187CR */
-        PORTCR(188,     0xe60520bc), /* PORT188CR */
-        PORTCR(189,     0xe60520bd), /* PORT189CR */
-        PORTCR(190,     0xe60520be), /* PORT190CR */
-        PORTCR(191,     0xe60520bf), /* PORT191CR */
-        PORTCR(192,     0xe60520c0), /* PORT192CR */
-        PORTCR(193,     0xe60520c1), /* PORT193CR */
-        PORTCR(194,     0xe60520c2), /* PORT194CR */
-        PORTCR(195,     0xe60520c3), /* PORT195CR */
-        PORTCR(196,     0xe60520c4), /* PORT196CR */
-        PORTCR(197,     0xe60520c5), /* PORT197CR */
-        PORTCR(198,     0xe60520c6), /* PORT198CR */
-        PORTCR(199,     0xe60520c7), /* PORT199CR */
-        PORTCR(200,     0xe60520c8), /* PORT200CR */
-        PORTCR(201,     0xe60520c9), /* PORT201CR */
-        PORTCR(202,     0xe60520ca), /* PORT202CR */
-        PORTCR(203,     0xe60520cb), /* PORT203CR */
-        PORTCR(204,     0xe60520cc), /* PORT204CR */
-        PORTCR(205,     0xe60520cd), /* PORT205CR */
-        PORTCR(206,     0xe60520ce), /* PORT206CR */
-        PORTCR(207,     0xe60520cf), /* PORT207CR */
-        PORTCR(208,     0xe60520d0), /* PORT208CR */
-        PORTCR(209,     0xe60520d1), /* PORT209CR */
-        PORTCR(210,     0xe60530d2), /* PORT210CR */
-        PORTCR(211,     0xe60530d3), /* PORT211CR */
-        { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
-                        MSEL1CR_31_0,   MSEL1CR_31_1,
-                        MSEL1CR_30_0,   MSEL1CR_30_1,
-                        MSEL1CR_29_0,   MSEL1CR_29_1,
-                        MSEL1CR_28_0,   MSEL1CR_28_1,
-                        MSEL1CR_27_0,   MSEL1CR_27_1,
-                        MSEL1CR_26_0,   MSEL1CR_26_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL1CR_16_0,   MSEL1CR_16_1,
-                        MSEL1CR_15_0,   MSEL1CR_15_1,
-                        MSEL1CR_14_0,   MSEL1CR_14_1,
-                        MSEL1CR_13_0,   MSEL1CR_13_1,
-                        MSEL1CR_12_0,   MSEL1CR_12_1,
-                        0, 0, 0, 0,
-                        MSEL1CR_9_0,    MSEL1CR_9_1,
-                        0, 0,
-                        MSEL1CR_7_0,    MSEL1CR_7_1,
-                        MSEL1CR_6_0,    MSEL1CR_6_1,
-                        MSEL1CR_5_0,    MSEL1CR_5_1,
-                        MSEL1CR_4_0,    MSEL1CR_4_1,
-                        MSEL1CR_3_0,    MSEL1CR_3_1,
-                        MSEL1CR_2_0,    MSEL1CR_2_1,
-                        0, 0,
-                        MSEL1CR_0_0,    MSEL1CR_0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL3CR_15_0,   MSEL3CR_15_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL3CR_6_0,    MSEL3CR_6_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL4CR_19_0,   MSEL4CR_19_1,
-                        MSEL4CR_18_0,   MSEL4CR_18_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_15_0,   MSEL4CR_15_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL4CR_10_0,   MSEL4CR_10_1,
-                        0, 0, 0, 0, 0, 0,
-                        MSEL4CR_6_0,    MSEL4CR_6_1,
-                        0, 0,
-                        MSEL4CR_4_0,    MSEL4CR_4_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_1_0,    MSEL4CR_1_1,
-                        0, 0,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
-                        MSEL5CR_31_0,   MSEL5CR_31_1,
-                        MSEL5CR_30_0,   MSEL5CR_30_1,
-                        MSEL5CR_29_0,   MSEL5CR_29_1,
-                        0, 0,
-                        MSEL5CR_27_0,   MSEL5CR_27_1,
-                        0, 0,
-                        MSEL5CR_25_0,   MSEL5CR_25_1,
-                        0, 0,
-                        MSEL5CR_23_0,   MSEL5CR_23_1,
-                        0, 0,
-                        MSEL5CR_21_0,   MSEL5CR_21_1,
-                        0, 0,
-                        MSEL5CR_19_0,   MSEL5CR_19_1,
-                        0, 0,
-                        MSEL5CR_17_0,   MSEL5CR_17_1,
-                        0, 0,
-                        MSEL5CR_15_0,   MSEL5CR_15_1,
-                        MSEL5CR_14_0,   MSEL5CR_14_1,
-                        MSEL5CR_13_0,   MSEL5CR_13_1,
-                        MSEL5CR_12_0,   MSEL5CR_12_1,
-                        MSEL5CR_11_0,   MSEL5CR_11_1,
-                        MSEL5CR_10_0,   MSEL5CR_10_1,
-                        0, 0,
-                        MSEL5CR_8_0,    MSEL5CR_8_1,
-                        MSEL5CR_7_0,    MSEL5CR_7_1,
-                        MSEL5CR_6_0,    MSEL5CR_6_1,
-                        MSEL5CR_5_0,    MSEL5CR_5_1,
-                        MSEL5CR_4_0,    MSEL5CR_4_1,
-                        MSEL5CR_3_0,    MSEL5CR_3_1,
-                        MSEL5CR_2_0,    MSEL5CR_2_1,
-                        0, 0,
-                        MSEL5CR_0_0,    MSEL5CR_0_1,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
-                PORT31_DATA,    PORT30_DATA,    PORT29_DATA,    PORT28_DATA,
-                PORT27_DATA,    PORT26_DATA,    PORT25_DATA,    PORT24_DATA,
-                PORT23_DATA,    PORT22_DATA,    PORT21_DATA,    PORT20_DATA,
-                PORT19_DATA,    PORT18_DATA,    PORT17_DATA,    PORT16_DATA,
-                PORT15_DATA,    PORT14_DATA,    PORT13_DATA,    PORT12_DATA,
-                PORT11_DATA,    PORT10_DATA,    PORT9_DATA,     PORT8_DATA,
-                PORT7_DATA,     PORT6_DATA,     PORT5_DATA,     PORT4_DATA,
-                PORT3_DATA,     PORT2_DATA,     PORT1_DATA,     PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
-                PORT63_DATA,    PORT62_DATA,    PORT61_DATA,    PORT60_DATA,
-                PORT59_DATA,    PORT58_DATA,    PORT57_DATA,    PORT56_DATA,
-                PORT55_DATA,    PORT54_DATA,    PORT53_DATA,    PORT52_DATA,
-                PORT51_DATA,    PORT50_DATA,    PORT49_DATA,    PORT48_DATA,
-                PORT47_DATA,    PORT46_DATA,    PORT45_DATA,    PORT44_DATA,
-                PORT43_DATA,    PORT42_DATA,    PORT41_DATA,    PORT40_DATA,
-                PORT39_DATA,    PORT38_DATA,    PORT37_DATA,    PORT36_DATA,
-                PORT35_DATA,    PORT34_DATA,    PORT33_DATA,    PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                PORT83_DATA,    PORT82_DATA,    PORT81_DATA,    PORT80_DATA,
-                PORT79_DATA,    PORT78_DATA,    PORT77_DATA,    PORT76_DATA,
-                PORT75_DATA,    PORT74_DATA,    PORT73_DATA,    PORT72_DATA,
-                PORT71_DATA,    PORT70_DATA,    PORT69_DATA,    PORT68_DATA,
-                PORT67_DATA,    PORT66_DATA,    PORT65_DATA,    PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
-                PORT95_DATA,    PORT94_DATA,    PORT93_DATA,    PORT92_DATA,
-                PORT91_DATA,    PORT90_DATA,    PORT89_DATA,    PORT88_DATA,
-                PORT87_DATA,    PORT86_DATA,    PORT85_DATA,    PORT84_DATA,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0,              PORT114_DATA,   PORT113_DATA,   PORT112_DATA,
-                PORT111_DATA,   PORT110_DATA,   PORT109_DATA,   PORT108_DATA,
-                PORT107_DATA,   PORT106_DATA,   PORT105_DATA,   PORT104_DATA,
-                PORT103_DATA,   PORT102_DATA,   PORT101_DATA,   PORT100_DATA,
-                PORT99_DATA,    PORT98_DATA,    PORT97_DATA,    PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
-                PORT127_DATA,   PORT126_DATA,   PORT125_DATA,   PORT124_DATA,
-                PORT123_DATA,   PORT122_DATA,   PORT121_DATA,   PORT120_DATA,
-                PORT119_DATA,   PORT118_DATA,   PORT117_DATA,   PORT116_DATA,
-                PORT115_DATA,   0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
-                PORT159_DATA,   PORT158_DATA,   PORT157_DATA,   PORT156_DATA,
-                PORT155_DATA,   PORT154_DATA,   PORT153_DATA,   PORT152_DATA,
-                PORT151_DATA,   PORT150_DATA,   PORT149_DATA,   PORT148_DATA,
-                PORT147_DATA,   PORT146_DATA,   PORT145_DATA,   PORT144_DATA,
-                PORT143_DATA,   PORT142_DATA,   PORT141_DATA,   PORT140_DATA,
-                PORT139_DATA,   PORT138_DATA,   PORT137_DATA,   PORT136_DATA,
-                PORT135_DATA,   PORT134_DATA,   PORT133_DATA,   PORT132_DATA,
-                PORT131_DATA,   PORT130_DATA,   PORT129_DATA,   PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
-                PORT191_DATA,   PORT190_DATA,   PORT189_DATA,   PORT188_DATA,
-                PORT187_DATA,   PORT186_DATA,   PORT185_DATA,   PORT184_DATA,
-                PORT183_DATA,   PORT182_DATA,   PORT181_DATA,   PORT180_DATA,
-                PORT179_DATA,   PORT178_DATA,   PORT177_DATA,   PORT176_DATA,
-                PORT175_DATA,   PORT174_DATA,   PORT173_DATA,   PORT172_DATA,
-                PORT171_DATA,   PORT170_DATA,   PORT169_DATA,   PORT168_DATA,
-                PORT167_DATA,   PORT166_DATA,   PORT165_DATA,   PORT164_DATA,
-                PORT163_DATA,   PORT162_DATA,   PORT161_DATA,   PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0,                           PORT209_DATA,   PORT208_DATA,
-                PORT207_DATA,   PORT206_DATA,   PORT205_DATA,   PORT204_DATA,
-                PORT203_DATA,   PORT202_DATA,   PORT201_DATA,   PORT200_DATA,
-                PORT199_DATA,   PORT198_DATA,   PORT197_DATA,   PORT196_DATA,
-                PORT195_DATA,   PORT194_DATA,   PORT193_DATA,   PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                PORT211_DATA,   PORT210_DATA, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { },
-};
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0,   PORT13_FN0),   /* IRQ0A */
-        PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0),                /* IRQ1A */
-        PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0,  PORT12_FN0),   /* IRQ2A */
-        PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0,  PORT14_FN0),   /* IRQ3A */
-        PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0,  PORT172_FN0),  /* IRQ4A */
-        PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0,   PORT1_FN0),    /* IRQ5A */
-        PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0),  /* IRQ6A */
-        PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0),  /* IRQ7A */
-        PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0),               /* IRQ8A */
-        PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0),  /* IRQ9A */
-        PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0),                /* IRQ10A */
-        PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0),               /* IRQ11A */
-        PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0,  PORT97_FN0),   /* IRQ12A */
-        PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0,  PORT98_FN0),   /* IRQ13A */
-        PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0,  PORT99_FN0),   /* IRQ14A */
-        PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0,  PORT100_FN0),  /* IRQ15A */
-        PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0,  PORT211_FN0),  /* IRQ16A */
-        PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0),                /* IRQ17A */
-        PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0),                /* IRQ18A */
-        PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0),                /* IRQ19A */
-        PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0),                /* IRQ20A */
-        PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0),               /* IRQ21A */
-        PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0),                /* IRQ22A */
-        PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0),                /* IRQ23A */
-        PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0),               /* IRQ24A */
-        PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0),                /* IRQ25A */
-        PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0,  PORT81_FN0),   /* IRQ26A */
-        PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0,  PORT168_FN0),  /* IRQ27A */
-        PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0,  PORT169_FN0),  /* IRQ28A */
-        PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0,  PORT170_FN0),  /* IRQ29A */
-        PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0,  PORT171_FN0),  /* IRQ30A */
-        PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0,  PORT167_FN0),  /* IRQ31A */
-};
-static struct pinmux_info r8a7740_pinmux_info = {
-        .name           = "r8a7740_pfc",
-        .reserved_id    = PINMUX_RESERVED,
-        .data           = { PINMUX_DATA_BEGIN,
-                            PINMUX_DATA_END },
-        .input          = { PINMUX_INPUT_BEGIN,
-                            PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
-        .output         = { PINMUX_OUTPUT_BEGIN,
-                            PINMUX_OUTPUT_END },
-        .mark           = { PINMUX_MARK_BEGIN,
-                            PINMUX_MARK_END },
-        .function       = { PINMUX_FUNCTION_BEGIN,
-                            PINMUX_FUNCTION_END },
-        .first_gpio     = GPIO_PORT0,
-        .last_gpio      = GPIO_FN_TRACEAUD_FROM_MEMC,
-        .gpios          = pinmux_gpios,
-        .cfg_regs       = pinmux_config_regs,
-        .data_regs      = pinmux_data_regs,
-        .gpio_data      = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq       = pinmux_irqs,
-        .gpio_irq_size  = ARRAY_SIZE(pinmux_irqs),
-};
-void r8a7740_pinmux_init(void)
-{
-        register_pinmux(&r8a7740_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
deleted file mode 100644
index 9513234d322b..000000000000
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ /dev/null
@@ -1,2645 +0,0 @@
-/*
- * r8a7779 processor support - PFC hardware block
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <linux/ioport.h>
-#include <mach/r8a7779.h>
-#define CPU_32_PORT(fn, pfx, sfx)                               \
-        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
-        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
-        PORT_1(fn, pfx##31, sfx)
-#define CPU_32_PORT6(fn, pfx, sfx)                              \
-        PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
-        PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
-        PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),       \
-        PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),       \
-        PORT_1(fn, pfx##8, sfx)
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        CPU_32_PORT(fn, pfx##_0_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_1_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_2_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_3_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_4_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_5_, sfx),                         \
-        CPU_32_PORT6(fn, pfx##_6_, sfx)
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,    \
-                                       GP##pfx##_IN, GP##pfx##_OUT)
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-#define GP_ALL(str)     CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
-#define PORT_10_REV(fn, pfx, sfx)                               \
-        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
-        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
-        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
-        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
-        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-#define CPU_32_PORT_REV(fn, pfx, sfx)                                   \
-        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),             \
-        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
-        PORT_10_REV(fn, pfx, sfx)
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-                                                          FN_##ipsr, FN_##fn)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
-        PINMUX_INPUT_END,
-        PINMUX_OUTPUT_BEGIN,
-        GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
-        /* GPSR0 */
-        FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
-        FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
-        FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
-        FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
-        FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
-        FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
-        FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
-        FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
-        /* GPSR1 */
-        FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
-        FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
-        FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
-        FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
-        FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
-        FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
-        FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
-        FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
-        /* GPSR2 */
-        FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
-        FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
-        FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
-        FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
-        FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
-        FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
-        FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
-        FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
-        /* GPSR3 */
-        FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
-        FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
-        FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
-        FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
-        FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
-        FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
-        FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
-        FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
-        /* GPSR4 */
-        FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
-        FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
-        FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
-        FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
-        FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
-        FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-        FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
-        FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
-        /* GPSR5 */
-        FN_A1, FN_A2, FN_A3, FN_A4,
-        FN_A5, FN_A6, FN_A7, FN_A8,
-        FN_A9, FN_A10, FN_A11, FN_A12,
-        FN_A13, FN_A14, FN_A15, FN_A16,
-        FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
-        FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
-        FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
-        FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
-        /* GPSR6 */
-        FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
-        FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
-        FN_IP3_20,
-        /* IPSR0 */
-        FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-        FN_HRTS1, FN_RX4_C,
-        FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
-        FN_CS0, FN_HSPI_CS2_B,
-        FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
-        FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-        FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-        FN_CTS0_B,
-        FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-        FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
-        FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-        FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-        FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
-        FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
-        FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-        FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-        FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-        FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-        FN_SCIF_CLK, FN_TCLK0_C,
-        /* IPSR1 */
-        FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
-        FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
-        FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-        FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
-        FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
-        FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
-        FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-        FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-        FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
-        FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
-        FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
-        FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
-        FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
-        FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
-        FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
-        FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
-        /* IPSR2 */
-        FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-        FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-        FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
-        FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
-        FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
-        FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
-        FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
-        FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
-        FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
-        FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
-        FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
-        FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
-        FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
-        FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
-        FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
-        FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
-        FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
-        FN_DREQ1, FN_SCL2, FN_AUDATA2,
-        /* IPSR3 */
-        FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-        FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
-        FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
-        FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
-        FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
-        FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
-        FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
-        FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
-        FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
-        FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
-        FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
-        FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
-        FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-        FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
-        FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
-        FN_TX2_C, FN_SCL2_C, FN_REMOCON,
-        /* IPSR4 */
-        FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
-        FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-        FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
-        FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
-        FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
-        FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
-        FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
-        FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
-        FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
-        FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
-        FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
-        FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-        FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
-        FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
-        FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
-        FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
-        FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
-        FN_SCK0_D,
-        /* IPSR5 */
-        FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-        FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
-        FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
-        FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
-        FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
-        FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
-        FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
-        FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
-        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-        FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-        FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
-        FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-        FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-        FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
-        FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
-        FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
-        FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
-        FN_CAN_DEBUGOUT0, FN_MOUT0,
-        /* IPSR6 */
-        FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
-        FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
-        FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
-        FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
-        FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
-        FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
-        FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-        FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
-        FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
-        FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
-        FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
-        FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
-        FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-        /* IPSR7 */
-        FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
-        FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-        FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-        FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
-        FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
-        FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
-        FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
-        FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
-        FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
-        FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
-        FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
-        FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
-        FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
-        FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
-        /* IPSR8 */
-        FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-        FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-        FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
-        FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
-        FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
-        FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
-        FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
-        FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
-        FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
-        FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
-        FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
-        FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
-        FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
-        FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-        FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
-        FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
-        /* IPSR9 */
-        FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
-        FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-        FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-        FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
-        FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
-        FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
-        FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
-        FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
-        FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
-        FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
-        FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
-        FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
-        FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
-        FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-        /* IPSR10 */
-        FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-        FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
-        FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
-        FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-        FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
-        FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
-        FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
-        FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-        FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
-        FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
-        FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
-        FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
-        FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
-        FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-        FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
-        FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
-        /* IPSR11 */
-        FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-        FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
-        FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
-        FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
-        FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
-        FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-        FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
-        FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
-        FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-        FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
-        FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
-        FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
-        FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
-        FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
-        /* IPSR12 */
-        FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-        FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
-        FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
-        FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-        FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
-        FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
-        FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-        FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
-        FN_GPS_MAG, FN_FCE, FN_SCK4_B,
-        FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-        FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-        FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
-        FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
-        FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-        FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
-        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
-        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-        FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
-        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
-        FN_SEL_VI0_0, FN_SEL_VI0_1,
-        FN_SEL_SD2_0, FN_SEL_SD2_1,
-        FN_SEL_INT3_0, FN_SEL_INT3_1,
-        FN_SEL_INT2_0, FN_SEL_INT2_1,
-        FN_SEL_INT1_0, FN_SEL_INT1_1,
-        FN_SEL_INT0_0, FN_SEL_INT0_1,
-        FN_SEL_IE_0, FN_SEL_IE_1,
-        FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
-        FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-        FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
-        FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
-        FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-        FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-        FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-        FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-        FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
-        FN_SEL_ADI_0, FN_SEL_ADI_1,
-        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-        FN_SEL_SIM_0, FN_SEL_SIM_1,
-        FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-        FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-        FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
-        A19_MARK,
-        RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
-        HRTS1_MARK, RX4_C_MARK,
-        CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
-        CS0_MARK, HSPI_CS2_B_MARK,
-        CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
-        A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
-        HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
-        A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
-        HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
-        A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
-        A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
-        A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
-        A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
-        A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
-        BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
-        ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
-        SCIF_CLK_MARK, TCLK0_C_MARK,
-        EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
-        FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
-        EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
-        ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
-        FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
-        HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
-        EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
-        ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
-        TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
-        SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
-        VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
-        SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
-        MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
-        PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
-        SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
-        CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
-        HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
-        SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
-        CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
-        MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
-        SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
-        CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
-        STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
-        SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
-        RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
-        CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
-        CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
-        GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
-        LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
-        AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
-        DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
-        DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
-        DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
-        DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
-        DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
-        AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
-        LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
-        LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
-        LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
-        SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
-        LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
-        AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
-        DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
-        DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
-        DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
-        TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
-        DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
-        SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
-        QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
-        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
-        TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
-        DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
-        DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
-        DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
-        VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
-        AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
-        PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
-        CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
-        VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
-        VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
-        VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
-        SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
-        DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
-        SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
-        VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
-        VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
-        VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
-        VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
-        SCK0_D_MARK,
-        DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
-        RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
-        DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
-        DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
-        DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
-        HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
-        SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
-        VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
-        VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
-        TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
-        VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
-        GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
-        QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
-        GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
-        RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
-        VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
-        GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
-        USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
-        SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
-        CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
-        MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
-        SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
-        CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
-        SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
-        SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
-        CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
-        SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
-        ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
-        SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
-        SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
-        SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
-        SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
-        SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
-        SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
-        HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
-        SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
-        IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
-        VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
-        ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
-        TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
-        RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
-        SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
-        TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
-        RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
-        RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
-        HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
-        CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
-        CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
-        AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
-        CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
-        CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
-        CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
-        CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
-        AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
-        CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
-        PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
-        VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
-        MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
-        VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
-        MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
-        RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
-        VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
-        VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
-        VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
-        MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
-        VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
-        MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
-        MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
-        IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
-        IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
-        MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
-        ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
-        VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
-        VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
-        VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
-        VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
-        VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
-        ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
-        DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
-        VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
-        ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
-        IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
-        SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
-        TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
-        HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
-        VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
-        TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
-        ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
-        TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
-        VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
-        PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
-        SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
-        VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
-        ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
-        SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
-        SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
-        VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
-        ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
-        SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
-        VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
-        HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
-        MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
-        SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
-        VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
-        DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
-        VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
-        DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
-        VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
-        SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
-        SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
-        VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
-        SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
-        GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
-        VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
-        RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
-        GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-        PINMUX_DATA(AVS1_MARK, FN_AVS1),
-        PINMUX_DATA(AVS1_MARK, FN_AVS1),
-        PINMUX_DATA(A17_MARK, FN_A17),
-        PINMUX_DATA(A18_MARK, FN_A18),
-        PINMUX_DATA(A19_MARK, FN_A19),
-        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP0_2_0, PWM1),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
-        PINMUX_IPSR_DATA(IP0_5_3, BS),
-        PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
-        PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
-        PINMUX_IPSR_DATA(IP0_5_3, FD2),
-        PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
-        PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
-        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
-        PINMUX_IPSR_DATA(IP0_7_6, A0),
-        PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
-        PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
-        PINMUX_IPSR_DATA(IP0_7_6, FD3),
-        PINMUX_IPSR_DATA(IP0_9_8, A20),
-        PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
-        PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
-        PINMUX_IPSR_DATA(IP0_11_10, A21),
-        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
-        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, A22),
-        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
-        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
-        PINMUX_IPSR_DATA(IP0_15_14, A23),
-        PINMUX_IPSR_DATA(IP0_15_14, FCLE),
-        PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
-        PINMUX_IPSR_DATA(IP0_18_16, A24),
-        PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
-        PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
-        PINMUX_IPSR_DATA(IP0_18_16, FD4),
-        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
-        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP0_22_19, A25),
-        PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
-        PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
-        PINMUX_IPSR_DATA(IP0_22_19, FD5),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
-        PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
-        PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
-        PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
-        PINMUX_IPSR_DATA(IP0_25, CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
-        PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
-        PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
-        PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
-        PINMUX_IPSR_DATA(IP0_30_28, FWE),
-        PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
-        PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
-        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
-        PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
-        PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
-        PINMUX_IPSR_DATA(IP1_1_0, FD6),
-        PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
-        PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
-        PINMUX_IPSR_DATA(IP1_3_2, FD7),
-        PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
-        PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, FALE),
-        PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
-        PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
-        PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, FRE),
-        PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
-        PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
-        PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
-        PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
-        PINMUX_IPSR_DATA(IP1_14_11, FD0),
-        PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
-        PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
-        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
-        PINMUX_IPSR_DATA(IP1_14_11, HTX1),
-        PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
-        PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
-        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
-        PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
-        PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
-        PINMUX_IPSR_DATA(IP1_18_15, FD1),
-        PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
-        PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
-        PINMUX_IPSR_DATA(IP1_20_19, PWM2),
-        PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
-        PINMUX_IPSR_DATA(IP1_22_21, PWM3),
-        PINMUX_IPSR_DATA(IP1_22_21, TX4),
-        PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
-        PINMUX_IPSR_DATA(IP1_24_23, PWM4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_28_25, HTX0),
-        PINMUX_IPSR_DATA(IP1_28_25, TX1),
-        PINMUX_IPSR_DATA(IP1_28_25, SDATA),
-        PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_7_4, MTS),
-        PINMUX_IPSR_DATA(IP2_7_4, PWM5),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_11_8, STM),
-        PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
-        PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
-        PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
-        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_15_12, MDATA),
-        PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
-        PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
-        PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
-        PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
-        PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
-        PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
-        PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
-        PINMUX_IPSR_DATA(IP2_21_19, DACK0),
-        PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
-        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
-        PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
-        PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
-        PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
-        PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
-        PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
-        PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
-        PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
-        PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
-        PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
-        PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
-        PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
-        PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
-        PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
-        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
-        PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
-        PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
-        PINMUX_IPSR_DATA(IP3_2_0, DACK1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
-        PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
-        PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
-        PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
-        PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
-        PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
-        PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
-        PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
-        PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
-        PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
-        PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
-        PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
-        PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
-        PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
-        PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
-        PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
-        PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
-        PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
-        PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
-        PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
-        PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
-        PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
-        PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
-        PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
-        PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
-        PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
-        PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
-        PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
-        PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
-        PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
-        PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
-        PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
-        PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
-        PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP3_23, QCLK),
-        PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
-        PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
-        PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
-        PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
-        PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
-        PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
-        PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
-        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
-        PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
-        PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
-        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
-        PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
-        PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
-        PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
-        PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
-        PINMUX_IPSR_DATA(IP4_7_5, PWM6),
-        PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
-        PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
-        PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
-        PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
-        PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
-        PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
-        PINMUX_IPSR_DATA(IP4_10_8, PWM0),
-        PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
-        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
-        PINMUX_IPSR_DATA(IP4_11, VI2_G0),
-        PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
-        PINMUX_IPSR_DATA(IP4_12, VI2_G1),
-        PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
-        PINMUX_IPSR_DATA(IP4_13, VI2_G2),
-        PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
-        PINMUX_IPSR_DATA(IP4_14, VI2_G3),
-        PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
-        PINMUX_IPSR_DATA(IP4_15, VI2_G4),
-        PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
-        PINMUX_IPSR_DATA(IP4_16, VI2_G5),
-        PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
-        PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
-        PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
-        PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
-        PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
-        PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
-        PINMUX_IPSR_DATA(IP4_23, VI2_G6),
-        PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
-        PINMUX_IPSR_DATA(IP4_24, VI2_G7),
-        PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
-        PINMUX_IPSR_DATA(IP4_25, VI2_R0),
-        PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
-        PINMUX_IPSR_DATA(IP4_26, VI2_R1),
-        PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
-        PINMUX_IPSR_DATA(IP4_27, VI2_R2),
-        PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
-        PINMUX_IPSR_DATA(IP4_28, VI2_R3),
-        PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
-        PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
-        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
-        PINMUX_IPSR_DATA(IP4_31_29, TX5),
-        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
-        PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
-        PINMUX_IPSR_DATA(IP5_3, VI2_R4),
-        PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
-        PINMUX_IPSR_DATA(IP5_4, VI2_R5),
-        PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
-        PINMUX_IPSR_DATA(IP5_5, VI2_R6),
-        PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
-        PINMUX_IPSR_DATA(IP5_6, VI2_R7),
-        PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
-        PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
-        PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
-        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
-        PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
-        PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
-        PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
-        PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
-        PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
-        PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
-        PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
-        PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
-        PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
-        PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
-        PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
-        PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
-        PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
-        PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
-        PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
-        PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
-        PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
-        PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
-        PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
-        PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
-        PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
-        PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
-        PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
-        PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
-        PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
-        PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
-        PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
-        PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
-        PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
-        PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
-        PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
-        PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
-        PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
-        PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
-        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
-        PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
-        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP6_14_12, IETX),
-        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
-        PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
-        PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
-        PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
-        PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
-        PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
-        PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
-        PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
-        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
-        PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
-        PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
-        PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
-        PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
-        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
-        PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
-        PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
-        PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
-        PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
-        PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
-        PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
-        PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
-        PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
-        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
-        PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
-        PINMUX_IPSR_DATA(IP7_14_13, VSP),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
-        PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
-        PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
-        PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
-        PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
-        PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
-        PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
-        PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
-        PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
-        PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
-        PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
-        PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
-        PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
-        PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
-        PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
-        PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
-        PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
-        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
-        PINMUX_IPSR_DATA(IP7_30_29, DACK2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
-        PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
-        PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
-        PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
-        PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
-        PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
-        PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
-        PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
-        PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
-        PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
-        PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
-        PINMUX_IPSR_DATA(IP8_18, BPFCLK),
-        PINMUX_IPSR_DATA(IP8_18, PCMWE),
-        PINMUX_IPSR_DATA(IP8_19, FMIN),
-        PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
-        PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
-        PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
-        PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
-        PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
-        PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
-        PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
-        PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
-        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
-        PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
-        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
-        PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
-        PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
-        PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
-        PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
-        PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
-        PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
-        PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
-        PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
-        PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
-        PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
-        PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
-        PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
-        PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
-        PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
-        PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
-        PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
-        PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
-        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
-        PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
-        PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
-        PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
-        PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
-        PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
-        PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
-        PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
-        PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
-        PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
-        PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
-        PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
-        PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
-        PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
-        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
-        PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
-        PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
-        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
-        PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
-        PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
-        PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
-        PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
-        PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
-        PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
-        PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
-        PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
-        PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
-        PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
-        PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
-        PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
-        PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
-        PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
-        PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
-        PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
-        PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
-        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
-        PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
-        PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
-        PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
-        PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
-        PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
-        PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
-        PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
-        PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
-        PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
-        PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
-        PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
-        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
-        PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
-        PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
-        PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
-        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
-        PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
-        PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
-        PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
-        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
-        PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
-        PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
-        PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
-        PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
-        PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
-        PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
-        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
-        PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
-        PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
-        PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
-        PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
-        PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
-        PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
-        PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
-        PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
-        PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
-        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
-        PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
-        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
-        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
-        PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
-        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
-        PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
-        PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
-        PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
-        PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
-        PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
-        PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
-        PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
-        PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
-        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
-        PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
-        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
-        PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
-        PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
-        PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
-        PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
-        PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
-        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
-        PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
-        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
-        PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
-        PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
-        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
-        PINMUX_IPSR_DATA(IP11_26_24, TX2),
-        PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
-        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
-        PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
-        PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
-        PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
-        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
-        PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
-        PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
-        PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
-        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
-        PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
-        PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
-        PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
-        PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
-        PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
-        PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
-        PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
-        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
-        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
-        PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_11_9, FSE),
-        PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
-        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
-        PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
-        PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
-        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_14_12, FRB),
-        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
-        PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
-        PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
-        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_17_15, FCE),
-        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        PINMUX_GPIO_GP_ALL(),
-        GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
-        GPIO_FN(A19),
-        /* IPSR0 */
-        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
-        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
-        GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
-        GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
-        GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
-        GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
-        GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
-        GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
-        GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
-        GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
-        GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
-        GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
-        GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
-        GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
-        GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
-        GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
-        GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
-        /* IPSR1 */
-        GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
-        GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
-        GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
-        GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
-        GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
-        GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
-        GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
-        GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
-        GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
-        GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
-        GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
-        GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
-        GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
-        GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
-        GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
-        GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
-        GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
-        GPIO_FN(CC5_STATE34),
-        /* IPSR2 */
-        GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
-        GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
-        GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
-        GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
-        GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
-        GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
-        GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
-        GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
-        GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
-        GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
-        GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
-        GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
-        GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
-        GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
-        GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
-        GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
-        GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
-        GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
-        GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
-        GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
-        GPIO_FN(AUDATA2),
-        /* IPSR3 */
-        GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
-        GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
-        GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
-        GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
-        GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
-        GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
-        GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
-        GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
-        GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
-        GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
-        GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
-        GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
-        GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
-        GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
-        GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
-        GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
-        GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
-        GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
-        GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
-        GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
-        GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
-        /* IPSR4 */
-        GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
-        GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
-        GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
-        GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
-        GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
-        GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
-        GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
-        GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
-        GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
-        GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
-        GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
-        GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
-        GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
-        GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
-        GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
-        GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
-        GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
-        GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
-        GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
-        GPIO_FN(TX5), GPIO_FN(SCK0_D),
-        /* IPSR5 */
-        GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
-        GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
-        GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
-        GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
-        GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
-        GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
-        GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
-        GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
-        GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
-        GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
-        GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
-        GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
-        GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
-        GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
-        GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
-        GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
-        GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
-        GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
-        GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
-        GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
-        GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
-        /* IPSR6 */
-        GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
-        GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
-        GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
-        GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
-        GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
-        GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
-        GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
-        GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
-        GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
-        GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
-        GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
-        GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
-        GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
-        GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
-        GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
-        GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
-        GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
-        /* IPSR7 */
-        GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
-        GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
-        GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
-        GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
-        GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
-        GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
-        GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
-        GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
-        GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
-        GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
-        GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
-        GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
-        GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
-        GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
-        GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
-        GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
-        GPIO_FN(CTS1_B),
-        /* IPSR8 */
-        GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
-        GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
-        GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
-        GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
-        GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
-        GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
-        GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
-        GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
-        GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
-        GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
-        GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
-        GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
-        GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
-        GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
-        GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
-        GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
-        GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
-        GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
-        GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
-        GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
-        /* IPSR9 */
-        GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
-        GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
-        GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
-        GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
-        GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
-        GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
-        GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
-        GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
-        GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
-        GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
-        GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
-        GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
-        GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
-        GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
-        GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
-        GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
-        GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
-        GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
-        /* IPSR10 */
-        GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
-        GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
-        GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
-        GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
-        GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
-        GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
-        GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
-        GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
-        GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
-        GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
-        GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
-        GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
-        GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
-        GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
-        GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
-        GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
-        GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
-        GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
-        GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
-        GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
-        GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
-        /* IPSR11 */
-        GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
-        GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
-        GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
-        GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
-        GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
-        GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
-        GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
-        GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
-        GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
-        GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
-        GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
-        GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
-        GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
-        GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
-        GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
-        GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
-        GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
-        GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
-        GPIO_FN(HRTS0_B),
-        /* IPSR12 */
-        GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
-        GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
-        GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
-        GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
-        GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
-        GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
-        GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
-        GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
-        GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
-        GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
-                GP_0_31_FN, FN_IP3_31_29,
-                GP_0_30_FN, FN_IP3_26_24,
-                GP_0_29_FN, FN_IP3_22_21,
-                GP_0_28_FN, FN_IP3_14_12,
-                GP_0_27_FN, FN_IP3_11_9,
-                GP_0_26_FN, FN_IP3_2_0,
-                GP_0_25_FN, FN_IP2_30_28,
-                GP_0_24_FN, FN_IP2_21_19,
-                GP_0_23_FN, FN_IP2_18_16,
-                GP_0_22_FN, FN_IP0_30_28,
-                GP_0_21_FN, FN_IP0_5_3,
-                GP_0_20_FN, FN_IP1_18_15,
-                GP_0_19_FN, FN_IP1_14_11,
-                GP_0_18_FN, FN_IP1_10_7,
-                GP_0_17_FN, FN_IP1_6_4,
-                GP_0_16_FN, FN_IP1_3_2,
-                GP_0_15_FN, FN_IP1_1_0,
-                GP_0_14_FN, FN_IP0_27_26,
-                GP_0_13_FN, FN_IP0_25,
-                GP_0_12_FN, FN_IP0_24_23,
-                GP_0_11_FN, FN_IP0_22_19,
-                GP_0_10_FN, FN_IP0_18_16,
-                GP_0_9_FN, FN_IP0_15_14,
-                GP_0_8_FN, FN_IP0_13_12,
-                GP_0_7_FN, FN_IP0_11_10,
-                GP_0_6_FN, FN_IP0_9_8,
-                GP_0_5_FN, FN_A19,
-                GP_0_4_FN, FN_A18,
-                GP_0_3_FN, FN_A17,
-                GP_0_2_FN, FN_IP0_7_6,
-                GP_0_1_FN, FN_AVS2,
-                GP_0_0_FN, FN_AVS1 }
-        },
-        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
-                GP_1_31_FN, FN_IP5_23_21,
-                GP_1_30_FN, FN_IP5_20_17,
-                GP_1_29_FN, FN_IP5_16_15,
-                GP_1_28_FN, FN_IP5_14_13,
-                GP_1_27_FN, FN_IP5_12_11,
-                GP_1_26_FN, FN_IP5_10_9,
-                GP_1_25_FN, FN_IP5_8,
-                GP_1_24_FN, FN_IP5_7,
-                GP_1_23_FN, FN_IP5_6,
-                GP_1_22_FN, FN_IP5_5,
-                GP_1_21_FN, FN_IP5_4,
-                GP_1_20_FN, FN_IP5_3,
-                GP_1_19_FN, FN_IP5_2_0,
-                GP_1_18_FN, FN_IP4_31_29,
-                GP_1_17_FN, FN_IP4_28,
-                GP_1_16_FN, FN_IP4_27,
-                GP_1_15_FN, FN_IP4_26,
-                GP_1_14_FN, FN_IP4_25,
-                GP_1_13_FN, FN_IP4_24,
-                GP_1_12_FN, FN_IP4_23,
-                GP_1_11_FN, FN_IP4_22_20,
-                GP_1_10_FN, FN_IP4_19_17,
-                GP_1_9_FN, FN_IP4_16,
-                GP_1_8_FN, FN_IP4_15,
-                GP_1_7_FN, FN_IP4_14,
-                GP_1_6_FN, FN_IP4_13,
-                GP_1_5_FN, FN_IP4_12,
-                GP_1_4_FN, FN_IP4_11,
-                GP_1_3_FN, FN_IP4_10_8,
-                GP_1_2_FN, FN_IP4_7_5,
-                GP_1_1_FN, FN_IP4_4_2,
-                GP_1_0_FN, FN_IP4_1_0 }
-        },
-        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
-                GP_2_31_FN, FN_IP10_28_26,
-                GP_2_30_FN, FN_IP10_25_24,
-                GP_2_29_FN, FN_IP10_23_21,
-                GP_2_28_FN, FN_IP10_20_18,
-                GP_2_27_FN, FN_IP10_17_15,
-                GP_2_26_FN, FN_IP10_14_12,
-                GP_2_25_FN, FN_IP10_11_9,
-                GP_2_24_FN, FN_IP10_8_6,
-                GP_2_23_FN, FN_IP10_5_3,
-                GP_2_22_FN, FN_IP10_2_0,
-                GP_2_21_FN, FN_IP9_29_28,
-                GP_2_20_FN, FN_IP9_27_26,
-                GP_2_19_FN, FN_IP9_25_24,
-                GP_2_18_FN, FN_IP9_23_22,
-                GP_2_17_FN, FN_IP9_21_19,
-                GP_2_16_FN, FN_IP9_18_16,
-                GP_2_15_FN, FN_IP9_15_14,
-                GP_2_14_FN, FN_IP9_13_12,
-                GP_2_13_FN, FN_IP9_11_10,
-                GP_2_12_FN, FN_IP9_9_8,
-                GP_2_11_FN, FN_IP9_7,
-                GP_2_10_FN, FN_IP9_6,
-                GP_2_9_FN, FN_IP9_5,
-                GP_2_8_FN, FN_IP9_4,
-                GP_2_7_FN, FN_IP9_3_2,
-                GP_2_6_FN, FN_IP9_1_0,
-                GP_2_5_FN, FN_IP8_30_28,
-                GP_2_4_FN, FN_IP8_27_25,
-                GP_2_3_FN, FN_IP8_24_23,
-                GP_2_2_FN, FN_IP8_22_21,
-                GP_2_1_FN, FN_IP8_20,
-                GP_2_0_FN, FN_IP5_27_24 }
-        },
-        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
-                GP_3_31_FN, FN_IP6_3_2,
-                GP_3_30_FN, FN_IP6_1_0,
-                GP_3_29_FN, FN_IP5_30_29,
-                GP_3_28_FN, FN_IP5_28,
-                GP_3_27_FN, FN_IP1_24_23,
-                GP_3_26_FN, FN_IP1_22_21,
-                GP_3_25_FN, FN_IP1_20_19,
-                GP_3_24_FN, FN_IP7_26_25,
-                GP_3_23_FN, FN_IP7_24_23,
-                GP_3_22_FN, FN_IP7_22_21,
-                GP_3_21_FN, FN_IP7_20_19,
-                GP_3_20_FN, FN_IP7_30_29,
-                GP_3_19_FN, FN_IP7_28_27,
-                GP_3_18_FN, FN_IP7_18_17,
-                GP_3_17_FN, FN_IP7_16_15,
-                GP_3_16_FN, FN_IP12_17_15,
-                GP_3_15_FN, FN_IP12_14_12,
-                GP_3_14_FN, FN_IP12_11_9,
-                GP_3_13_FN, FN_IP12_8_6,
-                GP_3_12_FN, FN_IP12_5_3,
-                GP_3_11_FN, FN_IP12_2_0,
-                GP_3_10_FN, FN_IP11_29_27,
-                GP_3_9_FN, FN_IP11_26_24,
-                GP_3_8_FN, FN_IP11_23_21,
-                GP_3_7_FN, FN_IP11_20_18,
-                GP_3_6_FN, FN_IP11_17_15,
-                GP_3_5_FN, FN_IP11_14_12,
-                GP_3_4_FN, FN_IP11_11_9,
-                GP_3_3_FN, FN_IP11_8_6,
-                GP_3_2_FN, FN_IP11_5_3,
-                GP_3_1_FN, FN_IP11_2_0,
-                GP_3_0_FN, FN_IP10_31_29 }
-        },
-        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
-                GP_4_31_FN, FN_IP8_19,
-                GP_4_30_FN, FN_IP8_18,
-                GP_4_29_FN, FN_IP8_17_16,
-                GP_4_28_FN, FN_IP0_2_0,
-                GP_4_27_FN, FN_USB_PENC1,
-                GP_4_26_FN, FN_USB_PENC0,
-                GP_4_25_FN, FN_IP8_15_12,
-                GP_4_24_FN, FN_IP8_11_8,
-                GP_4_23_FN, FN_IP8_7_4,
-                GP_4_22_FN, FN_IP8_3_0,
-                GP_4_21_FN, FN_IP2_3_0,
-                GP_4_20_FN, FN_IP1_28_25,
-                GP_4_19_FN, FN_IP2_15_12,
-                GP_4_18_FN, FN_IP2_11_8,
-                GP_4_17_FN, FN_IP2_7_4,
-                GP_4_16_FN, FN_IP7_14_13,
-                GP_4_15_FN, FN_IP7_12_10,
-                GP_4_14_FN, FN_IP7_9_7,
-                GP_4_13_FN, FN_IP7_6_4,
-                GP_4_12_FN, FN_IP7_3_2,
-                GP_4_11_FN, FN_IP7_1_0,
-                GP_4_10_FN, FN_IP6_30_29,
-                GP_4_9_FN, FN_IP6_26_25,
-                GP_4_8_FN, FN_IP6_24_23,
-                GP_4_7_FN, FN_IP6_22_20,
-                GP_4_6_FN, FN_IP6_19_18,
-                GP_4_5_FN, FN_IP6_17_15,
-                GP_4_4_FN, FN_IP6_14_12,
-                GP_4_3_FN, FN_IP6_11_9,
-                GP_4_2_FN, FN_IP6_8,
-                GP_4_1_FN, FN_IP6_7_6,
-                GP_4_0_FN, FN_IP6_5_4 }
-        },
-        { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
-                GP_5_31_FN, FN_IP3_5,
-                GP_5_30_FN, FN_IP3_4,
-                GP_5_29_FN, FN_IP3_3,
-                GP_5_28_FN, FN_IP2_27,
-                GP_5_27_FN, FN_IP2_26,
-                GP_5_26_FN, FN_IP2_25,
-                GP_5_25_FN, FN_IP2_24,
-                GP_5_24_FN, FN_IP2_23,
-                GP_5_23_FN, FN_IP2_22,
-                GP_5_22_FN, FN_IP3_28,
-                GP_5_21_FN, FN_IP3_27,
-                GP_5_20_FN, FN_IP3_23,
-                GP_5_19_FN, FN_EX_WAIT0,
-                GP_5_18_FN, FN_WE1,
-                GP_5_17_FN, FN_WE0,
-                GP_5_16_FN, FN_RD,
-                GP_5_15_FN, FN_A16,
-                GP_5_14_FN, FN_A15,
-                GP_5_13_FN, FN_A14,
-                GP_5_12_FN, FN_A13,
-                GP_5_11_FN, FN_A12,
-                GP_5_10_FN, FN_A11,
-                GP_5_9_FN, FN_A10,
-                GP_5_8_FN, FN_A9,
-                GP_5_7_FN, FN_A8,
-                GP_5_6_FN, FN_A7,
-                GP_5_5_FN, FN_A6,
-                GP_5_4_FN, FN_A5,
-                GP_5_3_FN, FN_A4,
-                GP_5_2_FN, FN_A3,
-                GP_5_1_FN, FN_A2,
-                GP_5_0_FN, FN_A1 }
-        },
-        { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                GP_6_8_FN, FN_IP3_20,
-                GP_6_7_FN, FN_IP3_19,
-                GP_6_6_FN, FN_IP3_18,
-                GP_6_5_FN, FN_IP3_17,
-                GP_6_4_FN, FN_IP3_16,
-                GP_6_3_FN, FN_IP3_15,
-                GP_6_2_FN, FN_IP3_8,
-                GP_6_1_FN, FN_IP3_7,
-                GP_6_0_FN, FN_IP3_6 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
-                             1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
-                /* IP0_31 [1] */
-                0, 0,
-                /* IP0_30_28 [3] */
-                FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-                FN_HRTS1, FN_RX4_C, 0, 0,
-                /* IP0_27_26 [2] */
-                FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
-                /* IP0_25 [1] */
-                FN_CS0, FN_HSPI_CS2_B,
-                /* IP0_24_23 [2] */
-                FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
-                /* IP0_22_19 [4] */
-                FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-                FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-                FN_CTS0_B, 0, 0, 0,
-                0, 0, 0, 0,
-                /* IP0_18_16 [3] */
-                FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-                FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
-                /* IP0_15_14 [2] */
-                FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-                /* IP0_13_12 [2] */
-                FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-                /* IP0_11_10 [2] */
-                FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
-                /* IP0_9_8 [2] */
-                FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
-                /* IP0_7_6 [2] */
-                FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-                /* IP0_5_3 [3] */
-                FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-                FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-                /* IP0_2_0 [3] */
-                FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-                FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-                             3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
-                /* IP1_31_29 [3] */
-                0, 0, 0, 0, 0, 0, 0, 0,
-                /* IP1_28_25 [4] */
-                FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
-                FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
-                FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
-                0, 0, 0, 0,
-                /* IP1_24_23 [2] */
-                FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
-                /* IP1_22_21 [2] */
-                FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
-                /* IP1_20_19 [2] */
-                FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
-                /* IP1_18_15 [4] */
-                FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
-                FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
-                FN_RX0_B, FN_SSI_WS9, 0, 0,
-                0, 0, 0, 0,
-                /* IP1_14_11 [4] */
-                FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-                FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-                FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
-                0, 0, 0, 0,
-                /* IP1_10_7 [4] */
-                FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
-                FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
-                FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
-                0, 0, 0, 0,
-                /* IP1_6_4 [3] */
-                FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-                FN_ATACS00, 0, 0, 0,
-                /* IP1_3_2 [2] */
-                FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
-                /* IP1_1_0 [2] */
-                FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
-                             1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
-                /* IP2_31 [1] */
-                0, 0,
-                /* IP2_30_28 [3] */
-                FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
-                FN_AUDATA2, 0, 0, 0,
-                /* IP2_27 [1] */
-                FN_DU0_DR7, FN_LCDOUT7,
-                /* IP2_26 [1] */
-                FN_DU0_DR6, FN_LCDOUT6,
-                /* IP2_25 [1] */
-                FN_DU0_DR5, FN_LCDOUT5,
-                /* IP2_24 [1] */
-                FN_DU0_DR4, FN_LCDOUT4,
-                /* IP2_23 [1] */
-                FN_DU0_DR3, FN_LCDOUT3,
-                /* IP2_22 [1] */
-                FN_DU0_DR2, FN_LCDOUT2,
-                /* IP2_21_19 [3] */
-                FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
-                FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
-                /* IP2_18_16 [3] */
-                FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
-                FN_AUDATA0, FN_TX5_C, 0, 0,
-                /* IP2_15_12 [4] */
-                FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
-                FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
-                FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
-                0, 0, 0, 0,
-                /* IP2_11_8 [4] */
-                FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
-                FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
-                FN_CC5_OSCOUT, 0, 0, 0,
-                0, 0, 0, 0,
-                /* IP2_7_4 [4] */
-                FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
-                FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
-                FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
-                0, 0, 0, 0,
-                /* IP2_3_0 [4] */
-                FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-                FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-                FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
-                             3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
-                             1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
-            /* IP3_31_29 [3] */
-            FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
-            FN_SCL2_C, FN_REMOCON, 0, 0,
-            /* IP3_28 [1] */
-            FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-            /* IP3_27 [1] */
-            FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
-            /* IP3_26_24 [3] */
-            FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-            FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
-            /* IP3_23 [1] */
-            FN_DU0_DOTCLKOUT0, FN_QCLK,
-            /* IP3_22_21 [2] */
-            FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
-            /* IP3_20 [1] */
-            FN_DU0_DB7, FN_LCDOUT23,
-            /* IP3_19 [1] */
-            FN_DU0_DB6, FN_LCDOUT22,
-            /* IP3_18 [1] */
-            FN_DU0_DB5, FN_LCDOUT21,
-            /* IP3_17 [1] */
-            FN_DU0_DB4, FN_LCDOUT20,
-            /* IP3_16 [1] */
-            FN_DU0_DB3, FN_LCDOUT19,
-            /* IP3_15 [1] */
-            FN_DU0_DB2, FN_LCDOUT18,
-            /* IP3_14_12 [3] */
-            FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
-            FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
-            /* IP3_11_9 [3] */
-            FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
-            FN_TCLK1, FN_AUDATA4, 0, 0,
-            /* IP3_8 [1] */
-            FN_DU0_DG7, FN_LCDOUT15,
-            /* IP3_7 [1] */
-            FN_DU0_DG6, FN_LCDOUT14,
-            /* IP3_6 [1] */
-            FN_DU0_DG5, FN_LCDOUT13,
-            /* IP3_5 [1] */
-            FN_DU0_DG4, FN_LCDOUT12,
-            /* IP3_4 [1] */
-            FN_DU0_DG3, FN_LCDOUT11,
-            /* IP3_3 [1] */
-            FN_DU0_DG2, FN_LCDOUT10,
-            /* IP3_2_0 [3] */
-            FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-            FN_AUDATA3, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
-                             3, 1, 1, 1, 1, 1, 1, 3, 3,
-                             1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
-            /* IP4_31_29 [3] */
-            FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
-            FN_TX5, FN_SCK0_D, 0, 0,
-            /* IP4_28 [1] */
-            FN_DU1_DG7, FN_VI2_R3,
-            /* IP4_27 [1] */
-            FN_DU1_DG6, FN_VI2_R2,
-            /* IP4_26 [1] */
-            FN_DU1_DG5, FN_VI2_R1,
-            /* IP4_25 [1] */
-            FN_DU1_DG4, FN_VI2_R0,
-            /* IP4_24 [1] */
-            FN_DU1_DG3, FN_VI2_G7,
-            /* IP4_23 [1] */
-            FN_DU1_DG2, FN_VI2_G6,
-            /* IP4_22_20 [3] */
-            FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-            FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
-            /* IP4_19_17 [3] */
-            FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
-            FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
-            /* IP4_16 [1] */
-            FN_DU1_DR7, FN_VI2_G5,
-            /* IP4_15 [1] */
-            FN_DU1_DR6, FN_VI2_G4,
-            /* IP4_14 [1] */
-            FN_DU1_DR5, FN_VI2_G3,
-            /* IP4_13 [1] */
-            FN_DU1_DR4, FN_VI2_G2,
-            /* IP4_12 [1] */
-            FN_DU1_DR3, FN_VI2_G1,
-            /* IP4_11 [1] */
-            FN_DU1_DR2, FN_VI2_G0,
-            /* IP4_10_8 [3] */
-            FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
-            FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
-            /* IP4_7_5 [3] */
-            FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
-            FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
-            /* IP4_4_2 [3] */
-            FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-            FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
-            /* IP4_1_0 [2] */
-            FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
-                             1, 2, 1, 4, 3, 4, 2, 2,
-                             2, 2, 1, 1, 1, 1, 1, 1, 3) {
-            /* IP5_31 [1] */
-            0, 0,
-            /* IP5_30_29 [2] */
-            FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
-            /* IP5_28 [1] */
-            FN_AUDIO_CLKA, FN_CAN_TXCLK,
-            /* IP5_27_24 [4] */
-            FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
-            FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
-            FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
-            0, 0, 0, 0,
-            /* IP5_23_21 [3] */
-            FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-            FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-            /* IP5_20_17 [4] */
-            FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-            FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-            FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
-            0, 0, 0, 0,
-            /* IP5_16_15 [2] */
-            FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
-            /* IP5_14_13 [2] */
-            FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
-            /* IP5_12_11 [2] */
-            FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
-            /* IP5_10_9 [2] */
-            FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
-            /* IP5_8 [1] */
-            FN_DU1_DB7, FN_SDA2_D,
-            /* IP5_7 [1] */
-            FN_DU1_DB6, FN_SCL2_D,
-            /* IP5_6 [1] */
-            FN_DU1_DB5, FN_VI2_R7,
-            /* IP5_5 [1] */
-            FN_DU1_DB4, FN_VI2_R6,
-            /* IP5_4 [1] */
-            FN_DU1_DB3, FN_VI2_R5,
-            /* IP5_3 [1] */
-            FN_DU1_DB2, FN_VI2_R4,
-            /* IP5_2_0 [3] */
-            FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-            FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
-                             1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
-            /* IP6_31 [1] */
-            0, 0,
-            /* IP6_30_29 [2] */
-            FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-            /* IP_28_27 [2] */
-            0, 0, 0, 0,
-            /* IP6_26_25 [2] */
-            FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
-            /* IP6_24_23 [2] */
-            FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
-            /* IP6_22_20 [3] */
-            FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
-            FN_TCLK0_D, 0, 0, 0,
-            /* IP6_19_18 [2] */
-            FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
-            /* IP6_17_15 [3] */
-            FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-            FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
-            /* IP6_14_12 [3] */
-            FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
-            FN_SSI_WS9_C, 0, 0, 0,
-            /* IP6_11_9 [3] */
-            FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
-            FN_SSI_SCK9_C, 0, 0, 0,
-            /* IP6_8 [1] */
-            FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
-            /* IP6_7_6 [2] */
-            FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
-            /* IP6_5_4 [2] */
-            FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
-            /* IP6_3_2 [2] */
-            FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
-            /* IP6_1_0 [2] */
-            FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
-                             1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
-            /* IP7_31 [1] */
-            0, 0,
-            /* IP7_30_29 [2] */
-            FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
-            /* IP7_28_27 [2] */
-            FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
-            /* IP7_26_25 [2] */
-            FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
-            /* IP7_24_23 [2] */
-            FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
-            /* IP7_22_21 [2] */
-            FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
-            /* IP7_20_19 [2] */
-            FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
-            /* IP7_18_17 [2] */
-            FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
-            /* IP7_16_15 [2] */
-            FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
-            /* IP7_14_13 [2] */
-            FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
-            /* IP7_12_10 [3] */
-            FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
-            FN_HSPI_TX1_C, 0, 0, 0,
-            /* IP7_9_7 [3] */
-            FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
-            FN_HSPI_CS1_C, 0, 0, 0,
-            /* IP7_6_4 [3] */
-            FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-            FN_HSPI_CLK1_C, 0, 0, 0,
-            /* IP7_3_2 [2] */
-            FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-            /* IP7_1_0 [2] */
-            FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
-                             1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
-            /* IP8_31 [1] */
-            0, 0,
-            /* IP8_30_28 [3] */
-            FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
-            FN_PWMFSW0_C, 0, 0, 0,
-            /* IP8_27_25 [3] */
-            FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-            FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
-            /* IP8_24_23 [2] */
-            FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
-            /* IP8_22_21 [2] */
-            FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
-            /* IP8_20 [1] */
-            FN_VI0_CLK, FN_MMC1_CLK,
-            /* IP8_19 [1] */
-            FN_FMIN, FN_RDS_DATA,
-            /* IP8_18 [1] */
-            FN_BPFCLK, FN_PCMWE,
-            /* IP8_17_16 [2] */
-            FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
-            /* IP8_15_12 [4] */
-            FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
-            FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
-            FN_CC5_STATE39, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_11_8 [4] */
-            FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
-            FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
-            FN_CC5_STATE38, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_7_4 [4] */
-            FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
-            FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
-            FN_CC5_STATE37, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_3_0 [4] */
-            FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-            FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-            FN_CC5_STATE36, 0, 0, 0,
-            0, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
-                             2, 2, 2, 2, 2, 3, 3, 2, 2,
-                             2, 2, 1, 1, 1, 1, 2, 2) {
-            /* IP9_31_30 [2] */
-            0, 0, 0, 0,
-            /* IP9_29_28 [2] */
-            FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-            /* IP9_27_26 [2] */
-            FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
-            /* IP9_25_24 [2] */
-            FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
-            /* IP9_23_22 [2] */
-            FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
-            /* IP9_21_19 [3] */
-            FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
-            FN_TS_SDAT0, 0, 0, 0,
-            /* IP9_18_16 [3] */
-            FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
-            FN_TS_SPSYNC0, 0, 0, 0,
-            /* IP9_15_14 [2] */
-            FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
-            /* IP9_13_12 [2] */
-            FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
-            /* IP9_11_10 [2] */
-            FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
-            /* IP9_9_8 [2] */
-            FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
-            /* IP9_7 [1] */
-            FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
-            /* IP9_6 [1] */
-            FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-            /* IP9_5 [1] */
-            FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
-            /* IP9_4 [1] */
-            FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-            /* IP9_3_2 [2] */
-            FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
-            /* IP9_1_0 [2] */
-            FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
-                             3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
-            /* IP10_31_29 [3] */
-            FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
-            FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
-            /* IP10_28_26 [3] */
-            FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-            FN_PWMFSW0_E, 0, 0, 0,
-            /* IP10_25_24 [2] */
-            FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
-            /* IP10_23_21 [3] */
-            FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
-            FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
-            /* IP10_20_18 [3] */
-            FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
-            FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
-            /* IP10_17_15 [3] */
-            FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-            FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
-            /* IP10_14_12 [3] */
-            FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
-            FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
-            /* IP10_11_9 [3] */
-            FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
-            FN_ARM_TRACEDATA_13, 0, 0, 0,
-            /* IP10_8_6 [3] */
-            FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-            FN_ARM_TRACEDATA_12, 0, 0, 0,
-            /* IP10_5_3 [3] */
-            FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
-            FN_DACK0_C, FN_DRACK0_C, 0, 0,
-            /* IP10_2_0 [3] */
-            FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-            FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
-                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
-            /* IP11_31_30 [2] */
-            0, 0, 0, 0,
-            /* IP11_29_27 [3] */
-            FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
-            FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
-            /* IP11_26_24 [3] */
-            FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
-            FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
-            /* IP11_23_21 [3] */
-            FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
-            FN_HSPI_RX1_D, 0, 0, 0,
-            /* IP11_20_18 [3] */
-            FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-            FN_HSPI_TX1_D, 0, 0, 0,
-            /* IP11_17_15 [3] */
-            FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
-            FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
-            /* IP11_14_12 [3] */
-            FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-            FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
-            /* IP11_11_9 [3] */
-            FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
-            FN_ADICHS0_B, 0, 0, 0,
-            /* IP11_8_6 [3] */
-            FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
-            FN_ADIDATA_B, 0, 0, 0,
-            /* IP11_5_3 [3] */
-            FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
-            FN_ADICS_B_SAMP_B, 0, 0, 0,
-            /* IP11_2_0 [3] */
-            FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-            FN_ADICLK_B, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
-                             4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
-            /* IP12_31_28 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_27_24 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_23_20 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_19_18 [2] */
-            0, 0, 0, 0,
-            /* IP12_17_15 [3] */
-            FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
-            FN_SCK4_B, 0, 0, 0,
-            /* IP12_14_12 [3] */
-            FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-            FN_RX4_B, FN_SIM_CLK_B, 0, 0,
-            /* IP12_11_9 [3] */
-            FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
-            FN_TX4_B, FN_SIM_D_B, 0, 0,
-            /* IP12_8_6 [3] */
-            FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-            FN_SIM_RST_B, FN_HRX0_B, 0, 0,
-            /* IP12_5_3 [3] */
-            FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
-            FN_SCL1_C, FN_HTX0_B, 0, 0,
-            /* IP12_2_0 [3] */
-            FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-            FN_SCK2, FN_HSCK0_B, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
-                             2, 2, 3, 3, 2, 2, 2, 2, 2,
-                             1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
-            /* SEL_SCIF5 [2] */
-            FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-            /* SEL_SCIF4 [2] */
-            FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-            /* SEL_SCIF3 [3] */
-            FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-            FN_SEL_SCIF3_4, 0, 0, 0,
-            /* SEL_SCIF2 [3] */
-            FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
-            FN_SEL_SCIF2_4, 0, 0, 0,
-            /* SEL_SCIF1 [2] */
-            FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
-            /* SEL_SCIF0 [2] */
-            FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-            /* SEL_SSI9 [2] */
-            FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
-            /* SEL_SSI8 [2] */
-            FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
-            /* SEL_SSI7 [2] */
-            FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
-            /* SEL_VI0 [1] */
-            FN_SEL_VI0_0, FN_SEL_VI0_1,
-            /* SEL_SD2 [1] */
-            FN_SEL_SD2_0, FN_SEL_SD2_1,
-            /* SEL_INT3 [1] */
-            FN_SEL_INT3_0, FN_SEL_INT3_1,
-            /* SEL_INT2 [1] */
-            FN_SEL_INT2_0, FN_SEL_INT2_1,
-            /* SEL_INT1 [1] */
-            FN_SEL_INT1_0, FN_SEL_INT1_1,
-            /* SEL_INT0 [1] */
-            FN_SEL_INT0_0, FN_SEL_INT0_1,
-            /* SEL_IE [1] */
-            FN_SEL_IE_0, FN_SEL_IE_1,
-            /* SEL_EXBUS2 [2] */
-            FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
-            /* SEL_EXBUS1 [1] */
-            FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-            /* SEL_EXBUS0 [2] */
-            FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
-                             2, 2, 2, 2, 1, 1, 1, 3, 1,
-                             2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
-            /* SEL_TMU1 [2] */
-            FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
-            /* SEL_TMU0 [2] */
-            FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-            /* SEL_SCIF [2] */
-            FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-            /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-            /* SEL_CAN0 [1] */
-            FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-            /* SEL_HSCIF1 [1] */
-            FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-            /* SEL_HSCIF0 [1] */
-            FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-            /* SEL_PWMFSW [3] */
-            FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-            FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
-            /* SEL_ADI [1] */
-            FN_SEL_ADI_0, FN_SEL_ADI_1,
-            /* [2] */
-            0, 0, 0, 0,
-            /* [2] */
-            0, 0, 0, 0,
-            /* [2] */
-            0, 0, 0, 0,
-            /* SEL_GPS [2] */
-            FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-            /* SEL_SIM [1] */
-            FN_SEL_SIM_0, FN_SEL_SIM_1,
-            /* SEL_HSPI2 [1] */
-            FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-            /* SEL_HSPI1 [2] */
-            FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-            /* SEL_I2C3 [1] */
-            FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-            /* SEL_I2C2 [2] */
-            FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-            /* SEL_I2C1 [2] */
-            FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
-        },
-        { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
-        { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
-        { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
-        { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
-        { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
-        { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
-        { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                GP_6_8_IN, GP_6_8_OUT,
-                GP_6_7_IN, GP_6_7_OUT,
-                GP_6_6_IN, GP_6_6_OUT,
-                GP_6_5_IN, GP_6_5_OUT,
-                GP_6_4_IN, GP_6_4_OUT,
-                GP_6_3_IN, GP_6_3_OUT,
-                GP_6_2_IN, GP_6_2_OUT,
-                GP_6_1_IN, GP_6_1_OUT,
-                GP_6_0_IN, GP_6_0_OUT, }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
-        { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
-        { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
-        { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
-        { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
-        { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
-        { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
-                GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
-                GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
-        },
-        { },
-};
-static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xffc40000,
-                .end    = 0xffc46fff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct pinmux_info r8a7779_pinmux_info = {
-        .name = "r8a7779_pfc",
-        .resource = r8a7779_pfc_resources,
-        .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
-        .unlock_reg = 0xfffc0000, /* PMMR */
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_GP_0_0,
-        .last_gpio = GPIO_FN_SCK4_B,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-void r8a7779_pinmux_init(void)
-{
-        register_pinmux(&r8a7779_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
deleted file mode 100644
index 7a1525fd6ada..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ /dev/null
@@ -1,1663 +0,0 @@
-/*
- * sh7372 processor support - PFC hardware block
- *
- * Copyright (C) 2010  Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on
- * sh7367 processor support - PFC hardware block
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-#define CPU_ALL_PORT(fn, pfx, sfx) \
-        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx), \
-        PORT_10(fn, pfx##10, sfx),      PORT_10(fn, pfx##11, sfx), \
-        PORT_10(fn, pfx##12, sfx),      PORT_10(fn, pfx##13, sfx), \
-        PORT_10(fn, pfx##14, sfx),      PORT_10(fn, pfx##15, sfx), \
-        PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
-        PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        /* PORT0_DATA -> PORT190_DATA */
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),
-        PINMUX_DATA_END,
-        /* PORT0_IN -> PORT190_IN */
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),
-        PINMUX_INPUT_END,
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-        /* PORT0_OUT -> PORT190_OUT */
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),        /* PORT0_FN_IN  -> PORT190_FN_IN */
-        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT190_FN_OUT */
-        PORT_ALL(FN0),          /* PORT0_FN0    -> PORT190_FN0 */
-        PORT_ALL(FN1),          /* PORT0_FN1    -> PORT190_FN1 */
-        PORT_ALL(FN2),          /* PORT0_FN2    -> PORT190_FN2 */
-        PORT_ALL(FN3),          /* PORT0_FN3    -> PORT190_FN3 */
-        PORT_ALL(FN4),          /* PORT0_FN4    -> PORT190_FN4 */
-        PORT_ALL(FN5),          /* PORT0_FN5    -> PORT190_FN5 */
-        PORT_ALL(FN6),          /* PORT0_FN6    -> PORT190_FN6 */
-        PORT_ALL(FN7),          /* PORT0_FN7    -> PORT190_FN7 */
-        MSEL1CR_31_0,   MSEL1CR_31_1,
-        MSEL1CR_30_0,   MSEL1CR_30_1,
-        MSEL1CR_29_0,   MSEL1CR_29_1,
-        MSEL1CR_28_0,   MSEL1CR_28_1,
-        MSEL1CR_27_0,   MSEL1CR_27_1,
-        MSEL1CR_26_0,   MSEL1CR_26_1,
-        MSEL1CR_16_0,   MSEL1CR_16_1,
-        MSEL1CR_15_0,   MSEL1CR_15_1,
-        MSEL1CR_14_0,   MSEL1CR_14_1,
-        MSEL1CR_13_0,   MSEL1CR_13_1,
-        MSEL1CR_12_0,   MSEL1CR_12_1,
-        MSEL1CR_9_0,    MSEL1CR_9_1,
-        MSEL1CR_8_0,    MSEL1CR_8_1,
-        MSEL1CR_7_0,    MSEL1CR_7_1,
-        MSEL1CR_6_0,    MSEL1CR_6_1,
-        MSEL1CR_4_0,    MSEL1CR_4_1,
-        MSEL1CR_3_0,    MSEL1CR_3_1,
-        MSEL1CR_2_0,    MSEL1CR_2_1,
-        MSEL1CR_0_0,    MSEL1CR_0_1,
-        MSEL3CR_27_0,   MSEL3CR_27_1,
-        MSEL3CR_26_0,   MSEL3CR_26_1,
-        MSEL3CR_21_0,   MSEL3CR_21_1,
-        MSEL3CR_20_0,   MSEL3CR_20_1,
-        MSEL3CR_15_0,   MSEL3CR_15_1,
-        MSEL3CR_9_0,    MSEL3CR_9_1,
-        MSEL3CR_6_0,    MSEL3CR_6_1,
-        MSEL4CR_19_0,   MSEL4CR_19_1,
-        MSEL4CR_18_0,   MSEL4CR_18_1,
-        MSEL4CR_17_0,   MSEL4CR_17_1,
-        MSEL4CR_16_0,   MSEL4CR_16_1,
-        MSEL4CR_15_0,   MSEL4CR_15_1,
-        MSEL4CR_14_0,   MSEL4CR_14_1,
-        MSEL4CR_10_0,   MSEL4CR_10_1,
-        MSEL4CR_6_0,    MSEL4CR_6_1,
-        MSEL4CR_4_0,    MSEL4CR_4_1,
-        MSEL4CR_1_0,    MSEL4CR_1_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* IRQ */
-        IRQ0_6_MARK,    IRQ0_162_MARK,  IRQ1_MARK,      IRQ2_4_MARK,
-        IRQ2_5_MARK,    IRQ3_8_MARK,    IRQ3_16_MARK,   IRQ4_17_MARK,
-        IRQ4_163_MARK,  IRQ5_MARK,      IRQ6_39_MARK,   IRQ6_164_MARK,
-        IRQ7_40_MARK,   IRQ7_167_MARK,  IRQ8_41_MARK,   IRQ8_168_MARK,
-        IRQ9_42_MARK,   IRQ9_169_MARK,  IRQ10_MARK,     IRQ11_MARK,
-        IRQ12_80_MARK,  IRQ12_137_MARK, IRQ13_81_MARK,  IRQ13_145_MARK,
-        IRQ14_82_MARK,  IRQ14_146_MARK, IRQ15_83_MARK,  IRQ15_147_MARK,
-        IRQ16_84_MARK,  IRQ16_170_MARK, IRQ17_MARK,     IRQ18_MARK,
-        IRQ19_MARK,     IRQ20_MARK,     IRQ21_MARK,     IRQ22_MARK,
-        IRQ23_MARK,     IRQ24_MARK,     IRQ25_MARK,     IRQ26_121_MARK,
-        IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
-        IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
-        IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
-        /* MSIOF0 */
-        MSIOF0_TSYNC_MARK,      MSIOF0_TSCK_MARK,       MSIOF0_RXD_MARK,
-        MSIOF0_RSCK_MARK,       MSIOF0_RSYNC_MARK,      MSIOF0_MCK0_MARK,
-        MSIOF0_MCK1_MARK,       MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,
-        MSIOF0_TXD_MARK,
-        /* MSIOF1 */
-        MSIOF1_TSCK_39_MARK,    MSIOF1_TSYNC_40_MARK,
-        MSIOF1_TSCK_88_MARK,    MSIOF1_TSYNC_89_MARK,
-        MSIOF1_TXD_41_MARK,     MSIOF1_RXD_42_MARK,
-        MSIOF1_TXD_90_MARK,     MSIOF1_RXD_91_MARK,
-        MSIOF1_SS1_43_MARK,     MSIOF1_SS2_44_MARK,
-        MSIOF1_SS1_92_MARK,     MSIOF1_SS2_93_MARK,
-        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
-        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
-        /* MSIOF2 */
-        MSIOF2_RSCK_MARK,       MSIOF2_RSYNC_MARK,      MSIOF2_MCK0_MARK,
-        MSIOF2_MCK1_MARK,       MSIOF2_SS1_MARK,        MSIOF2_SS2_MARK,
-        MSIOF2_TSYNC_MARK,      MSIOF2_TSCK_MARK,       MSIOF2_RXD_MARK,
-        MSIOF2_TXD_MARK,
-        /* BBIF1 */
-        BBIF1_RXD_MARK,         BBIF1_TSYNC_MARK,       BBIF1_TSCK_MARK,
-        BBIF1_TXD_MARK,         BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
-        BBIF1_FLOW_MARK,        BB_RX_FLOW_N_MARK,
-        /* BBIF2 */
-        BBIF2_TSCK1_MARK,       BBIF2_TSYNC1_MARK,
-        BBIF2_TXD1_MARK,        BBIF2_RXD_MARK,
-        /* FSI */
-        FSIACK_MARK,    FSIBCK_MARK,            FSIAILR_MARK,   FSIAIBT_MARK,
-        FSIAISLD_MARK,  FSIAOMC_MARK,           FSIAOLR_MARK,   FSIAOBT_MARK,
-        FSIAOSLD_MARK,  FSIASPDIF_11_MARK,      FSIASPDIF_15_MARK,
-        /* FMSI */
-        FMSOCK_MARK,    FMSOOLR_MARK,   FMSIOLR_MARK,   FMSOOBT_MARK,
-        FMSIOBT_MARK,   FMSOSLD_MARK,   FMSOILR_MARK,   FMSIILR_MARK,
-        FMSOIBT_MARK,   FMSIIBT_MARK,   FMSISLD_MARK,   FMSICK_MARK,
-        /* SCIFA0 */
-        SCIFA0_TXD_MARK,        SCIFA0_RXD_MARK,        SCIFA0_SCK_MARK,
-        SCIFA0_RTS_MARK,        SCIFA0_CTS_MARK,
-        /* SCIFA1 */
-        SCIFA1_TXD_MARK,        SCIFA1_RXD_MARK,        SCIFA1_SCK_MARK,
-        SCIFA1_RTS_MARK,        SCIFA1_CTS_MARK,
-        /* SCIFA2 */
-        SCIFA2_CTS1_MARK,       SCIFA2_RTS1_MARK,       SCIFA2_TXD1_MARK,
-        SCIFA2_RXD1_MARK,       SCIFA2_SCK1_MARK,
-        /* SCIFA3 */
-        SCIFA3_CTS_43_MARK,     SCIFA3_CTS_140_MARK,    SCIFA3_RTS_44_MARK,
-        SCIFA3_RTS_141_MARK,    SCIFA3_SCK_MARK,        SCIFA3_TXD_MARK,
-        SCIFA3_RXD_MARK,
-        /* SCIFA4 */
-        SCIFA4_RXD_MARK,        SCIFA4_TXD_MARK,
-        /* SCIFA5 */
-        SCIFA5_RXD_MARK,        SCIFA5_TXD_MARK,
-        /* SCIFB */
-        SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
-        SCIFB_TXD_MARK, SCIFB_RXD_MARK,
-        /* CEU */
-        VIO_HD_MARK,    VIO_CKO1_MARK,  VIO_CKO2_MARK,  VIO_VD_MARK,
-        VIO_CLK_MARK,   VIO_FIELD_MARK, VIO_CKO_MARK,
-        VIO_D0_MARK,    VIO_D1_MARK,    VIO_D2_MARK,    VIO_D3_MARK,
-        VIO_D4_MARK,    VIO_D5_MARK,    VIO_D6_MARK,    VIO_D7_MARK,
-        VIO_D8_MARK,    VIO_D9_MARK,    VIO_D10_MARK,   VIO_D11_MARK,
-        VIO_D12_MARK,   VIO_D13_MARK,   VIO_D14_MARK,   VIO_D15_MARK,
-        /* USB0 */
-        IDIN_0_MARK,    EXTLP_0_MARK,   OVCN2_0_MARK,   PWEN_0_MARK,
-        OVCN_0_MARK,    VBUS0_0_MARK,
-        /* USB1 */
-        IDIN_1_18_MARK,         IDIN_1_113_MARK,
-        PWEN_1_115_MARK,        PWEN_1_138_MARK,
-        OVCN_1_114_MARK,        OVCN_1_162_MARK,
-        EXTLP_1_MARK,           OVCN2_1_MARK,
-        VBUS0_1_MARK,
-        /* GPIO */
-        GPI0_MARK,      GPI1_MARK,      GPO0_MARK,      GPO1_MARK,
-        /* BSC */
-        BS_MARK,        WE1_MARK,
-        CKO_MARK,       WAIT_MARK,      RDWR_MARK,
-        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
-        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
-        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
-        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
-        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
-        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
-        A26_MARK,
-        CS0_MARK,       CS2_MARK,       CS4_MARK,
-        CS5A_MARK,      CS5B_MARK,      CS6A_MARK,
-        /* BSC/FLCTL */
-        RD_FSC_MARK,    WE0_FWE_MARK,   A4_FOE_MARK,    A5_FCDE_MARK,
-        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   D3_NAF3_MARK,
-        D4_NAF4_MARK,   D5_NAF5_MARK,   D6_NAF6_MARK,   D7_NAF7_MARK,
-        D8_NAF8_MARK,   D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK,
-        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-        /* MMCIF(1) */
-        MMCD0_0_MARK,   MMCD0_1_MARK,   MMCD0_2_MARK,   MMCD0_3_MARK,
-        MMCD0_4_MARK,   MMCD0_5_MARK,   MMCD0_6_MARK,   MMCD0_7_MARK,
-        MMCCMD0_MARK,   MMCCLK0_MARK,
-        /* MMCIF(2) */
-        MMCD1_0_MARK,   MMCD1_1_MARK,   MMCD1_2_MARK,   MMCD1_3_MARK,
-        MMCD1_4_MARK,   MMCD1_5_MARK,   MMCD1_6_MARK,   MMCD1_7_MARK,
-        MMCCLK1_MARK,   MMCCMD1_MARK,
-        /* SPU2 */
-        VINT_I_MARK,
-        /* FLCTL */
-        FCE1_MARK,      FCE0_MARK,      FRB_MARK,
-        /* HSI */
-        GP_RX_FLAG_MARK,        GP_RX_DATA_MARK,        GP_TX_READY_MARK,
-        GP_RX_WAKE_MARK,        MP_TX_FLAG_MARK,        MP_TX_DATA_MARK,
-        MP_RX_READY_MARK,       MP_TX_WAKE_MARK,
-        /* MFI */
-        MFIv6_MARK,
-        MFIv4_MARK,
-        MEMC_CS0_MARK,                  MEMC_BUSCLK_MEMC_A0_MARK,
-        MEMC_CS1_MEMC_A1_MARK,          MEMC_ADV_MEMC_DREQ0_MARK,
-        MEMC_WAIT_MEMC_DREQ1_MARK,      MEMC_NOE_MARK,
-        MEMC_NWE_MARK,                  MEMC_INT_MARK,
-        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,
-        MEMC_AD3_MARK,  MEMC_AD4_MARK,  MEMC_AD5_MARK,
-        MEMC_AD6_MARK,  MEMC_AD7_MARK,  MEMC_AD8_MARK,
-        MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
-        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
-        MEMC_AD15_MARK,
-        /* SIM */
-        SIM_RST_MARK,   SIM_CLK_MARK,   SIM_D_MARK,
-        /* TPU */
-        TPU0TO0_MARK,           TPU0TO1_MARK,
-        TPU0TO2_93_MARK,        TPU0TO2_99_MARK,
-        TPU0TO3_MARK,
-        /* I2C2 */
-        I2C_SCL2_MARK,  I2C_SDA2_MARK,
-        /* I2C3(1) */
-        I2C_SCL3_MARK,  I2C_SDA3_MARK,
-        /* I2C3(2) */
-        I2C_SCL3S_MARK, I2C_SDA3S_MARK,
-        /* I2C4(2) */
-        I2C_SCL4_MARK,  I2C_SDA4_MARK,
-        /* I2C4(2) */
-        I2C_SCL4S_MARK, I2C_SDA4S_MARK,
-        /* KEYSC */
-        KEYOUT0_MARK,   KEYIN0_121_MARK,        KEYIN0_136_MARK,
-        KEYOUT1_MARK,   KEYIN1_122_MARK,        KEYIN1_135_MARK,
-        KEYOUT2_MARK,   KEYIN2_123_MARK,        KEYIN2_134_MARK,
-        KEYOUT3_MARK,   KEYIN3_124_MARK,        KEYIN3_133_MARK,
-        KEYOUT4_MARK,   KEYIN4_MARK,
-        KEYOUT5_MARK,   KEYIN5_MARK,
-        KEYOUT6_MARK,   KEYIN6_MARK,
-        KEYOUT7_MARK,   KEYIN7_MARK,
-        /* LCDC */
-        LCDC0_SELECT_MARK,
-        LCDC1_SELECT_MARK,
-        LCDHSYN_MARK,   LCDCS_MARK,     LCDVSYN_MARK,   LCDDCK_MARK,
-        LCDWR_MARK,     LCDRD_MARK,     LCDDISP_MARK,   LCDRS_MARK,
-        LCDLCLK_MARK,   LCDDON_MARK,
-        LCDD0_MARK,     LCDD1_MARK,     LCDD2_MARK,     LCDD3_MARK,
-        LCDD4_MARK,     LCDD5_MARK,     LCDD6_MARK,     LCDD7_MARK,
-        LCDD8_MARK,     LCDD9_MARK,     LCDD10_MARK,    LCDD11_MARK,
-        LCDD12_MARK,    LCDD13_MARK,    LCDD14_MARK,    LCDD15_MARK,
-        LCDD16_MARK,    LCDD17_MARK,    LCDD18_MARK,    LCDD19_MARK,
-        LCDD20_MARK,    LCDD21_MARK,    LCDD22_MARK,    LCDD23_MARK,
-        /* IRDA */
-        IRDA_OUT_MARK,  IRDA_IN_MARK,   IRDA_FIRSEL_MARK,
-        IROUT_139_MARK, IROUT_140_MARK,
-        /* TSIF1 */
-        TS0_1SELECT_MARK,
-        TS0_2SELECT_MARK,
-        TS1_1SELECT_MARK,
-        TS1_2SELECT_MARK,
-        TS_SPSYNC1_MARK,        TS_SDAT1_MARK,
-        TS_SDEN1_MARK,          TS_SCK1_MARK,
-        /* TSIF2 */
-        TS_SPSYNC2_MARK,        TS_SDAT2_MARK,
-        TS_SDEN2_MARK,          TS_SCK2_MARK,
-        /* HDMI */
-        HDMI_HPD_MARK,  HDMI_CEC_MARK,
-        /* SDHI0 */
-        SDHICLK0_MARK,  SDHICD0_MARK,
-        SDHICMD0_MARK,  SDHIWP0_MARK,
-        SDHID0_0_MARK,  SDHID0_1_MARK,
-        SDHID0_2_MARK,  SDHID0_3_MARK,
-        /* SDHI1 */
-        SDHICLK1_MARK,  SDHICMD1_MARK,  SDHID1_0_MARK,
-        SDHID1_1_MARK,  SDHID1_2_MARK,  SDHID1_3_MARK,
-        /* SDHI2 */
-        SDHICLK2_MARK,  SDHICMD2_MARK,  SDHID2_0_MARK,
-        SDHID2_1_MARK,  SDHID2_2_MARK,  SDHID2_3_MARK,
-        /* SDENC */
-        SDENC_CPG_MARK,
-        SDENC_DV_CLKI_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-        PORT_DATA_IO_PU_PD(190),
-        /* IRQ */
-        PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
-        PINMUX_DATA(IRQ0_162_MARK,      PORT162_FN0,    MSEL1CR_0_1),
-        PINMUX_DATA(IRQ1_MARK,          PORT12_FN0),
-        PINMUX_DATA(IRQ2_4_MARK,        PORT4_FN0,      MSEL1CR_2_0),
-        PINMUX_DATA(IRQ2_5_MARK,        PORT5_FN0,      MSEL1CR_2_1),
-        PINMUX_DATA(IRQ3_8_MARK,        PORT8_FN0,      MSEL1CR_3_0),
-        PINMUX_DATA(IRQ3_16_MARK,       PORT16_FN0,     MSEL1CR_3_1),
-        PINMUX_DATA(IRQ4_17_MARK,       PORT17_FN0,     MSEL1CR_4_0),
-        PINMUX_DATA(IRQ4_163_MARK,      PORT163_FN0,    MSEL1CR_4_1),
-        PINMUX_DATA(IRQ5_MARK,          PORT18_FN0),
-        PINMUX_DATA(IRQ6_39_MARK,       PORT39_FN0,     MSEL1CR_6_0),
-        PINMUX_DATA(IRQ6_164_MARK,      PORT164_FN0,    MSEL1CR_6_1),
-        PINMUX_DATA(IRQ7_40_MARK,       PORT40_FN0,     MSEL1CR_7_1),
-        PINMUX_DATA(IRQ7_167_MARK,      PORT167_FN0,    MSEL1CR_7_0),
-        PINMUX_DATA(IRQ8_41_MARK,       PORT41_FN0,     MSEL1CR_8_1),
-        PINMUX_DATA(IRQ8_168_MARK,      PORT168_FN0,    MSEL1CR_8_0),
-        PINMUX_DATA(IRQ9_42_MARK,       PORT42_FN0,     MSEL1CR_9_0),
-        PINMUX_DATA(IRQ9_169_MARK,      PORT169_FN0,    MSEL1CR_9_1),
-        PINMUX_DATA(IRQ10_MARK,         PORT65_FN0,     MSEL1CR_9_1),
-        PINMUX_DATA(IRQ11_MARK,         PORT67_FN0),
-        PINMUX_DATA(IRQ12_80_MARK,      PORT80_FN0,     MSEL1CR_12_0),
-        PINMUX_DATA(IRQ12_137_MARK,     PORT137_FN0,    MSEL1CR_12_1),
-        PINMUX_DATA(IRQ13_81_MARK,      PORT81_FN0,     MSEL1CR_13_0),
-        PINMUX_DATA(IRQ13_145_MARK,     PORT145_FN0,    MSEL1CR_13_1),
-        PINMUX_DATA(IRQ14_82_MARK,      PORT82_FN0,     MSEL1CR_14_0),
-        PINMUX_DATA(IRQ14_146_MARK,     PORT146_FN0,    MSEL1CR_14_1),
-        PINMUX_DATA(IRQ15_83_MARK,      PORT83_FN0,     MSEL1CR_15_0),
-        PINMUX_DATA(IRQ15_147_MARK,     PORT147_FN0,    MSEL1CR_15_1),
-        PINMUX_DATA(IRQ16_84_MARK,      PORT84_FN0,     MSEL1CR_16_0),
-        PINMUX_DATA(IRQ16_170_MARK,     PORT170_FN0,    MSEL1CR_16_1),
-        PINMUX_DATA(IRQ17_MARK,         PORT85_FN0),
-        PINMUX_DATA(IRQ18_MARK,         PORT86_FN0),
-        PINMUX_DATA(IRQ19_MARK,         PORT87_FN0),
-        PINMUX_DATA(IRQ20_MARK,         PORT92_FN0),
-        PINMUX_DATA(IRQ21_MARK,         PORT93_FN0),
-        PINMUX_DATA(IRQ22_MARK,         PORT94_FN0),
-        PINMUX_DATA(IRQ23_MARK,         PORT95_FN0),
-        PINMUX_DATA(IRQ24_MARK,         PORT112_FN0),
-        PINMUX_DATA(IRQ25_MARK,         PORT119_FN0),
-        PINMUX_DATA(IRQ26_121_MARK,     PORT121_FN0,    MSEL1CR_26_1),
-        PINMUX_DATA(IRQ26_172_MARK,     PORT172_FN0,    MSEL1CR_26_0),
-        PINMUX_DATA(IRQ27_122_MARK,     PORT122_FN0,    MSEL1CR_27_1),
-        PINMUX_DATA(IRQ27_180_MARK,     PORT180_FN0,    MSEL1CR_27_0),
-        PINMUX_DATA(IRQ28_123_MARK,     PORT123_FN0,    MSEL1CR_28_1),
-        PINMUX_DATA(IRQ28_181_MARK,     PORT181_FN0,    MSEL1CR_28_0),
-        PINMUX_DATA(IRQ29_129_MARK,     PORT129_FN0,    MSEL1CR_29_1),
-        PINMUX_DATA(IRQ29_182_MARK,     PORT182_FN0,    MSEL1CR_29_0),
-        PINMUX_DATA(IRQ30_130_MARK,     PORT130_FN0,    MSEL1CR_30_1),
-        PINMUX_DATA(IRQ30_183_MARK,     PORT183_FN0,    MSEL1CR_30_0),
-        PINMUX_DATA(IRQ31_138_MARK,     PORT138_FN0,    MSEL1CR_31_1),
-        PINMUX_DATA(IRQ31_184_MARK,     PORT184_FN0,    MSEL1CR_31_0),
-        /* Function 1 */
-        PINMUX_DATA(BBIF2_TSCK1_MARK,           PORT0_FN1),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK,          PORT1_FN1),
-        PINMUX_DATA(BBIF2_TXD1_MARK,            PORT2_FN1),
-        PINMUX_DATA(BBIF2_RXD_MARK,             PORT3_FN1),
-        PINMUX_DATA(FSIACK_MARK,                PORT4_FN1),
-        PINMUX_DATA(FSIAILR_MARK,               PORT5_FN1),
-        PINMUX_DATA(FSIAIBT_MARK,               PORT6_FN1),
-        PINMUX_DATA(FSIAISLD_MARK,              PORT7_FN1),
-        PINMUX_DATA(FSIAOMC_MARK,               PORT8_FN1),
-        PINMUX_DATA(FSIAOLR_MARK,               PORT9_FN1),
-        PINMUX_DATA(FSIAOBT_MARK,               PORT10_FN1),
-        PINMUX_DATA(FSIAOSLD_MARK,              PORT11_FN1),
-        PINMUX_DATA(FMSOCK_MARK,                PORT12_FN1),
-        PINMUX_DATA(FMSOOLR_MARK,               PORT13_FN1),
-        PINMUX_DATA(FMSOOBT_MARK,               PORT14_FN1),
-        PINMUX_DATA(FMSOSLD_MARK,               PORT15_FN1),
-        PINMUX_DATA(FMSOILR_MARK,               PORT16_FN1),
-        PINMUX_DATA(FMSOIBT_MARK,               PORT17_FN1),
-        PINMUX_DATA(FMSISLD_MARK,               PORT18_FN1),
-        PINMUX_DATA(A0_MARK,                    PORT19_FN1),
-        PINMUX_DATA(A1_MARK,                    PORT20_FN1),
-        PINMUX_DATA(A2_MARK,                    PORT21_FN1),
-        PINMUX_DATA(A3_MARK,                    PORT22_FN1),
-        PINMUX_DATA(A4_FOE_MARK,                PORT23_FN1),
-        PINMUX_DATA(A5_FCDE_MARK,               PORT24_FN1),
-        PINMUX_DATA(A6_MARK,                    PORT25_FN1),
-        PINMUX_DATA(A7_MARK,                    PORT26_FN1),
-        PINMUX_DATA(A8_MARK,                    PORT27_FN1),
-        PINMUX_DATA(A9_MARK,                    PORT28_FN1),
-        PINMUX_DATA(A10_MARK,                   PORT29_FN1),
-        PINMUX_DATA(A11_MARK,                   PORT30_FN1),
-        PINMUX_DATA(A12_MARK,                   PORT31_FN1),
-        PINMUX_DATA(A13_MARK,                   PORT32_FN1),
-        PINMUX_DATA(A14_MARK,                   PORT33_FN1),
-        PINMUX_DATA(A15_MARK,                   PORT34_FN1),
-        PINMUX_DATA(A16_MARK,                   PORT35_FN1),
-        PINMUX_DATA(A17_MARK,                   PORT36_FN1),
-        PINMUX_DATA(A18_MARK,                   PORT37_FN1),
-        PINMUX_DATA(A19_MARK,                   PORT38_FN1),
-        PINMUX_DATA(A20_MARK,                   PORT39_FN1),
-        PINMUX_DATA(A21_MARK,                   PORT40_FN1),
-        PINMUX_DATA(A22_MARK,                   PORT41_FN1),
-        PINMUX_DATA(A23_MARK,                   PORT42_FN1),
-        PINMUX_DATA(A24_MARK,                   PORT43_FN1),
-        PINMUX_DATA(A25_MARK,                   PORT44_FN1),
-        PINMUX_DATA(A26_MARK,                   PORT45_FN1),
-        PINMUX_DATA(D0_NAF0_MARK,               PORT46_FN1),
-        PINMUX_DATA(D1_NAF1_MARK,               PORT47_FN1),
-        PINMUX_DATA(D2_NAF2_MARK,               PORT48_FN1),
-        PINMUX_DATA(D3_NAF3_MARK,               PORT49_FN1),
-        PINMUX_DATA(D4_NAF4_MARK,               PORT50_FN1),
-        PINMUX_DATA(D5_NAF5_MARK,               PORT51_FN1),
-        PINMUX_DATA(D6_NAF6_MARK,               PORT52_FN1),
-        PINMUX_DATA(D7_NAF7_MARK,               PORT53_FN1),
-        PINMUX_DATA(D8_NAF8_MARK,               PORT54_FN1),
-        PINMUX_DATA(D9_NAF9_MARK,               PORT55_FN1),
-        PINMUX_DATA(D10_NAF10_MARK,             PORT56_FN1),
-        PINMUX_DATA(D11_NAF11_MARK,             PORT57_FN1),
-        PINMUX_DATA(D12_NAF12_MARK,             PORT58_FN1),
-        PINMUX_DATA(D13_NAF13_MARK,             PORT59_FN1),
-        PINMUX_DATA(D14_NAF14_MARK,             PORT60_FN1),
-        PINMUX_DATA(D15_NAF15_MARK,             PORT61_FN1),
-        PINMUX_DATA(CS0_MARK,                   PORT62_FN1),
-        PINMUX_DATA(CS2_MARK,                   PORT63_FN1),
-        PINMUX_DATA(CS4_MARK,                   PORT64_FN1),
-        PINMUX_DATA(CS5A_MARK,                  PORT65_FN1),
-        PINMUX_DATA(CS5B_MARK,                  PORT66_FN1),
-        PINMUX_DATA(CS6A_MARK,                  PORT67_FN1),
-        PINMUX_DATA(FCE0_MARK,                  PORT68_FN1),
-        PINMUX_DATA(RD_FSC_MARK,                PORT69_FN1),
-        PINMUX_DATA(WE0_FWE_MARK,               PORT70_FN1),
-        PINMUX_DATA(WE1_MARK,                   PORT71_FN1),
-        PINMUX_DATA(CKO_MARK,                   PORT72_FN1),
-        PINMUX_DATA(FRB_MARK,                   PORT73_FN1),
-        PINMUX_DATA(WAIT_MARK,                  PORT74_FN1),
-        PINMUX_DATA(RDWR_MARK,                  PORT75_FN1),
-        PINMUX_DATA(MEMC_AD0_MARK,              PORT76_FN1),
-        PINMUX_DATA(MEMC_AD1_MARK,              PORT77_FN1),
-        PINMUX_DATA(MEMC_AD2_MARK,              PORT78_FN1),
-        PINMUX_DATA(MEMC_AD3_MARK,              PORT79_FN1),
-        PINMUX_DATA(MEMC_AD4_MARK,              PORT80_FN1),
-        PINMUX_DATA(MEMC_AD5_MARK,              PORT81_FN1),
-        PINMUX_DATA(MEMC_AD6_MARK,              PORT82_FN1),
-        PINMUX_DATA(MEMC_AD7_MARK,              PORT83_FN1),
-        PINMUX_DATA(MEMC_AD8_MARK,              PORT84_FN1),
-        PINMUX_DATA(MEMC_AD9_MARK,              PORT85_FN1),
-        PINMUX_DATA(MEMC_AD10_MARK,             PORT86_FN1),
-        PINMUX_DATA(MEMC_AD11_MARK,             PORT87_FN1),
-        PINMUX_DATA(MEMC_AD12_MARK,             PORT88_FN1),
-        PINMUX_DATA(MEMC_AD13_MARK,             PORT89_FN1),
-        PINMUX_DATA(MEMC_AD14_MARK,             PORT90_FN1),
-        PINMUX_DATA(MEMC_AD15_MARK,             PORT91_FN1),
-        PINMUX_DATA(MEMC_CS0_MARK,              PORT92_FN1),
-        PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK,   PORT93_FN1),
-        PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK,      PORT94_FN1),
-        PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK,   PORT95_FN1),
-        PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK,  PORT96_FN1),
-        PINMUX_DATA(MEMC_NOE_MARK,              PORT97_FN1),
-        PINMUX_DATA(MEMC_NWE_MARK,              PORT98_FN1),
-        PINMUX_DATA(MEMC_INT_MARK,              PORT99_FN1),
-        PINMUX_DATA(VIO_VD_MARK,                PORT100_FN1),
-        PINMUX_DATA(VIO_HD_MARK,                PORT101_FN1),
-        PINMUX_DATA(VIO_D0_MARK,                PORT102_FN1),
-        PINMUX_DATA(VIO_D1_MARK,                PORT103_FN1),
-        PINMUX_DATA(VIO_D2_MARK,                PORT104_FN1),
-        PINMUX_DATA(VIO_D3_MARK,                PORT105_FN1),
-        PINMUX_DATA(VIO_D4_MARK,                PORT106_FN1),
-        PINMUX_DATA(VIO_D5_MARK,                PORT107_FN1),
-        PINMUX_DATA(VIO_D6_MARK,                PORT108_FN1),
-        PINMUX_DATA(VIO_D7_MARK,                PORT109_FN1),
-        PINMUX_DATA(VIO_D8_MARK,                PORT110_FN1),
-        PINMUX_DATA(VIO_D9_MARK,                PORT111_FN1),
-        PINMUX_DATA(VIO_D10_MARK,               PORT112_FN1),
-        PINMUX_DATA(VIO_D11_MARK,               PORT113_FN1),
-        PINMUX_DATA(VIO_D12_MARK,               PORT114_FN1),
-        PINMUX_DATA(VIO_D13_MARK,               PORT115_FN1),
-        PINMUX_DATA(VIO_D14_MARK,               PORT116_FN1),
-        PINMUX_DATA(VIO_D15_MARK,               PORT117_FN1),
-        PINMUX_DATA(VIO_CLK_MARK,               PORT118_FN1),
-        PINMUX_DATA(VIO_FIELD_MARK,             PORT119_FN1),
-        PINMUX_DATA(VIO_CKO_MARK,               PORT120_FN1),
-        PINMUX_DATA(LCDD0_MARK,                 PORT121_FN1),
-        PINMUX_DATA(LCDD1_MARK,                 PORT122_FN1),
-        PINMUX_DATA(LCDD2_MARK,                 PORT123_FN1),
-        PINMUX_DATA(LCDD3_MARK,                 PORT124_FN1),
-        PINMUX_DATA(LCDD4_MARK,                 PORT125_FN1),
-        PINMUX_DATA(LCDD5_MARK,                 PORT126_FN1),
-        PINMUX_DATA(LCDD6_MARK,                 PORT127_FN1),
-        PINMUX_DATA(LCDD7_MARK,                 PORT128_FN1),
-        PINMUX_DATA(LCDD8_MARK,                 PORT129_FN1),
-        PINMUX_DATA(LCDD9_MARK,                 PORT130_FN1),
-        PINMUX_DATA(LCDD10_MARK,                PORT131_FN1),
-        PINMUX_DATA(LCDD11_MARK,                PORT132_FN1),
-        PINMUX_DATA(LCDD12_MARK,                PORT133_FN1),
-        PINMUX_DATA(LCDD13_MARK,                PORT134_FN1),
-        PINMUX_DATA(LCDD14_MARK,                PORT135_FN1),
-        PINMUX_DATA(LCDD15_MARK,                PORT136_FN1),
-        PINMUX_DATA(LCDD16_MARK,                PORT137_FN1),
-        PINMUX_DATA(LCDD17_MARK,                PORT138_FN1),
-        PINMUX_DATA(LCDD18_MARK,                PORT139_FN1),
-        PINMUX_DATA(LCDD19_MARK,                PORT140_FN1),
-        PINMUX_DATA(LCDD20_MARK,                PORT141_FN1),
-        PINMUX_DATA(LCDD21_MARK,                PORT142_FN1),
-        PINMUX_DATA(LCDD22_MARK,                PORT143_FN1),
-        PINMUX_DATA(LCDD23_MARK,                PORT144_FN1),
-        PINMUX_DATA(LCDHSYN_MARK,               PORT145_FN1),
-        PINMUX_DATA(LCDVSYN_MARK,               PORT146_FN1),
-        PINMUX_DATA(LCDDCK_MARK,                PORT147_FN1),
-        PINMUX_DATA(LCDRD_MARK,                 PORT148_FN1),
-        PINMUX_DATA(LCDDISP_MARK,               PORT149_FN1),
-        PINMUX_DATA(LCDLCLK_MARK,               PORT150_FN1),
-        PINMUX_DATA(LCDDON_MARK,                PORT151_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT152_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT153_FN1),
-        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT154_FN1),
-        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT155_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK,            PORT156_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK,              PORT157_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK,              PORT158_FN1),
-        PINMUX_DATA(TS_SCK1_MARK,               PORT159_FN1),
-        PINMUX_DATA(TPU0TO0_MARK,               PORT160_FN1),
-        PINMUX_DATA(TPU0TO1_MARK,               PORT161_FN1),
-        PINMUX_DATA(SCIFB_SCK_MARK,             PORT162_FN1),
-        PINMUX_DATA(SCIFB_RTS_MARK,             PORT163_FN1),
-        PINMUX_DATA(SCIFB_CTS_MARK,             PORT164_FN1),
-        PINMUX_DATA(SCIFB_TXD_MARK,             PORT165_FN1),
-        PINMUX_DATA(SCIFB_RXD_MARK,             PORT166_FN1),
-        PINMUX_DATA(VBUS0_0_MARK,               PORT167_FN1),
-        PINMUX_DATA(VBUS0_1_MARK,               PORT168_FN1),
-        PINMUX_DATA(HDMI_HPD_MARK,              PORT169_FN1),
-        PINMUX_DATA(HDMI_CEC_MARK,              PORT170_FN1),
-        PINMUX_DATA(SDHICLK0_MARK,              PORT171_FN1),
-        PINMUX_DATA(SDHICD0_MARK,               PORT172_FN1),
-        PINMUX_DATA(SDHID0_0_MARK,              PORT173_FN1),
-        PINMUX_DATA(SDHID0_1_MARK,              PORT174_FN1),
-        PINMUX_DATA(SDHID0_2_MARK,              PORT175_FN1),
-        PINMUX_DATA(SDHID0_3_MARK,              PORT176_FN1),
-        PINMUX_DATA(SDHICMD0_MARK,              PORT177_FN1),
-        PINMUX_DATA(SDHIWP0_MARK,               PORT178_FN1),
-        PINMUX_DATA(SDHICLK1_MARK,              PORT179_FN1),
-        PINMUX_DATA(SDHID1_0_MARK,              PORT180_FN1),
-        PINMUX_DATA(SDHID1_1_MARK,              PORT181_FN1),
-        PINMUX_DATA(SDHID1_2_MARK,              PORT182_FN1),
-        PINMUX_DATA(SDHID1_3_MARK,              PORT183_FN1),
-        PINMUX_DATA(SDHICMD1_MARK,              PORT184_FN1),
-        PINMUX_DATA(SDHICLK2_MARK,              PORT185_FN1),
-        PINMUX_DATA(SDHID2_0_MARK,              PORT186_FN1),
-        PINMUX_DATA(SDHID2_1_MARK,              PORT187_FN1),
-        PINMUX_DATA(SDHID2_2_MARK,              PORT188_FN1),
-        PINMUX_DATA(SDHID2_3_MARK,              PORT189_FN1),
-        PINMUX_DATA(SDHICMD2_MARK,              PORT190_FN1),
-        /* Function 2 */
-        PINMUX_DATA(FSIBCK_MARK,                PORT4_FN2),
-        PINMUX_DATA(SCIFA4_RXD_MARK,            PORT5_FN2),
-        PINMUX_DATA(SCIFA4_TXD_MARK,            PORT6_FN2),
-        PINMUX_DATA(SCIFA5_RXD_MARK,            PORT8_FN2),
-        PINMUX_DATA(FSIASPDIF_11_MARK,          PORT11_FN2),
-        PINMUX_DATA(SCIFA5_TXD_MARK,            PORT12_FN2),
-        PINMUX_DATA(FMSIOLR_MARK,               PORT13_FN2),
-        PINMUX_DATA(FMSIOBT_MARK,               PORT14_FN2),
-        PINMUX_DATA(FSIASPDIF_15_MARK,          PORT15_FN2),
-        PINMUX_DATA(FMSIILR_MARK,               PORT16_FN2),
-        PINMUX_DATA(FMSIIBT_MARK,               PORT17_FN2),
-        PINMUX_DATA(BS_MARK,                    PORT19_FN2),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT36_FN2),
-        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT37_FN2),
-        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT38_FN2),
-        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT39_FN2),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT40_FN2),
-        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT41_FN2),
-        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT42_FN2),
-        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT43_FN2),
-        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT44_FN2),
-        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT45_FN2),
-        PINMUX_DATA(FMSICK_MARK,                PORT65_FN2),
-        PINMUX_DATA(FCE1_MARK,                  PORT66_FN2),
-        PINMUX_DATA(BBIF1_RXD_MARK,             PORT76_FN2),
-        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT77_FN2),
-        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT78_FN2),
-        PINMUX_DATA(BBIF1_TXD_MARK,             PORT79_FN2),
-        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT80_FN2),
-        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT81_FN2),
-        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT82_FN2),
-        PINMUX_DATA(BB_RX_FLOW_N_MARK,          PORT83_FN2),
-        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT84_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT85_FN2),
-        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT86_FN2),
-        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT87_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_88_MARK,        PORT88_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TSYNC_89_MARK,       PORT89_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TXD_90_MARK,         PORT90_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_RXD_91_MARK,         PORT91_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_SS1_92_MARK,         PORT92_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_SS2_93_MARK,         PORT93_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK,           PORT94_FN2),
-        PINMUX_DATA(SCIFA2_RTS1_MARK,           PORT95_FN2),
-        PINMUX_DATA(SCIFA2_TXD1_MARK,           PORT96_FN2),
-        PINMUX_DATA(SCIFA2_RXD1_MARK,           PORT97_FN2),
-        PINMUX_DATA(SCIFA2_SCK1_MARK,           PORT98_FN2),
-        PINMUX_DATA(I2C_SCL2_MARK,              PORT110_FN2),
-        PINMUX_DATA(I2C_SDA2_MARK,              PORT111_FN2),
-        PINMUX_DATA(I2C_SCL3_MARK,              PORT114_FN2, MSEL4CR_16_1),
-        PINMUX_DATA(I2C_SDA3_MARK,              PORT115_FN2, MSEL4CR_16_1),
-        PINMUX_DATA(I2C_SCL4_MARK,              PORT116_FN2, MSEL4CR_17_1),
-        PINMUX_DATA(I2C_SDA4_MARK,              PORT117_FN2, MSEL4CR_17_1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT134_FN2),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT135_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT136_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT137_FN2),
-        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT138_FN2),
-        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT139_FN2),
-        PINMUX_DATA(SCIFA3_CTS_140_MARK,        PORT140_FN2, MSEL3CR_9_1),
-        PINMUX_DATA(SCIFA3_RTS_141_MARK,        PORT141_FN2),
-        PINMUX_DATA(SCIFA3_SCK_MARK,            PORT142_FN2),
-        PINMUX_DATA(SCIFA3_TXD_MARK,            PORT143_FN2),
-        PINMUX_DATA(SCIFA3_RXD_MARK,            PORT144_FN2),
-        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT148_FN2),
-        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT149_FN2),
-        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT150_FN2),
-        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT151_FN2),
-        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT156_FN2),
-        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT157_FN2),
-        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT158_FN2),
-        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT159_FN2),
-        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT160_FN2),
-        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT161_FN2),
-        /* Function 3 */
-        PINMUX_DATA(VIO_CKO1_MARK,              PORT16_FN3),
-        PINMUX_DATA(VIO_CKO2_MARK,              PORT17_FN3),
-        PINMUX_DATA(IDIN_1_18_MARK,             PORT18_FN3, MSEL4CR_14_1),
-        PINMUX_DATA(MSIOF1_TSCK_39_MARK,        PORT39_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_TSYNC_40_MARK,       PORT40_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_TXD_41_MARK,         PORT41_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_RXD_42_MARK,         PORT42_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_SS1_43_MARK,         PORT43_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_SS2_44_MARK,         PORT44_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MMCD1_0_MARK,               PORT54_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_1_MARK,               PORT55_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_2_MARK,               PORT56_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_3_MARK,               PORT57_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_4_MARK,               PORT58_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_5_MARK,               PORT59_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_6_MARK,               PORT60_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_7_MARK,               PORT61_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(VINT_I_MARK,                PORT65_FN3),
-        PINMUX_DATA(MMCCLK1_MARK,               PORT66_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCCMD1_MARK,               PORT67_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(TPU0TO2_93_MARK,            PORT93_FN3),
-        PINMUX_DATA(TPU0TO2_99_MARK,            PORT99_FN3),
-        PINMUX_DATA(TPU0TO3_MARK,               PORT112_FN3),
-        PINMUX_DATA(IDIN_0_MARK,                PORT113_FN3),
-        PINMUX_DATA(EXTLP_0_MARK,               PORT114_FN3),
-        PINMUX_DATA(OVCN2_0_MARK,               PORT115_FN3),
-        PINMUX_DATA(PWEN_0_MARK,                PORT116_FN3),
-        PINMUX_DATA(OVCN_0_MARK,                PORT117_FN3),
-        PINMUX_DATA(KEYOUT7_MARK,               PORT121_FN3),
-        PINMUX_DATA(KEYOUT6_MARK,               PORT122_FN3),
-        PINMUX_DATA(KEYOUT5_MARK,               PORT123_FN3),
-        PINMUX_DATA(KEYOUT4_MARK,               PORT124_FN3),
-        PINMUX_DATA(KEYOUT3_MARK,               PORT125_FN3),
-        PINMUX_DATA(KEYOUT2_MARK,               PORT126_FN3),
-        PINMUX_DATA(KEYOUT1_MARK,               PORT127_FN3),
-        PINMUX_DATA(KEYOUT0_MARK,               PORT128_FN3),
-        PINMUX_DATA(KEYIN7_MARK,                PORT129_FN3),
-        PINMUX_DATA(KEYIN6_MARK,                PORT130_FN3),
-        PINMUX_DATA(KEYIN5_MARK,                PORT131_FN3),
-        PINMUX_DATA(KEYIN4_MARK,                PORT132_FN3),
-        PINMUX_DATA(KEYIN3_133_MARK,            PORT133_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN2_134_MARK,            PORT134_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN1_135_MARK,            PORT135_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN0_136_MARK,            PORT136_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(TS_SPSYNC2_MARK,            PORT137_FN3),
-        PINMUX_DATA(IROUT_139_MARK,             PORT139_FN3),
-        PINMUX_DATA(IRDA_OUT_MARK,              PORT140_FN3),
-        PINMUX_DATA(IRDA_IN_MARK,               PORT141_FN3),
-        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT142_FN3),
-        PINMUX_DATA(TS_SDAT2_MARK,              PORT145_FN3),
-        PINMUX_DATA(TS_SDEN2_MARK,              PORT146_FN3),
-        PINMUX_DATA(TS_SCK2_MARK,               PORT147_FN3),
-        /* Function 4 */
-        PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
-        PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
-        PINMUX_DATA(GP_RX_FLAG_MARK,    PORT76_FN4),
-        PINMUX_DATA(GP_RX_DATA_MARK,    PORT77_FN4),
-        PINMUX_DATA(GP_TX_READY_MARK,   PORT78_FN4),
-        PINMUX_DATA(GP_RX_WAKE_MARK,    PORT79_FN4),
-        PINMUX_DATA(MP_TX_FLAG_MARK,    PORT80_FN4),
-        PINMUX_DATA(MP_TX_DATA_MARK,    PORT81_FN4),
-        PINMUX_DATA(MP_RX_READY_MARK,   PORT82_FN4),
-        PINMUX_DATA(MP_TX_WAKE_MARK,    PORT83_FN4),
-        PINMUX_DATA(MMCD0_0_MARK,       PORT84_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_1_MARK,       PORT85_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_2_MARK,       PORT86_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_3_MARK,       PORT87_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_4_MARK,       PORT88_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_5_MARK,       PORT89_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_6_MARK,       PORT90_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_7_MARK,       PORT91_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCCMD0_MARK,       PORT92_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(SIM_RST_MARK,       PORT94_FN4),
-        PINMUX_DATA(SIM_CLK_MARK,       PORT95_FN4),
-        PINMUX_DATA(SIM_D_MARK,         PORT98_FN4),
-        PINMUX_DATA(MMCCLK0_MARK,       PORT99_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(IDIN_1_113_MARK,    PORT113_FN4, MSEL4CR_14_0),
-        PINMUX_DATA(OVCN_1_114_MARK,    PORT114_FN4, MSEL4CR_14_0),
-        PINMUX_DATA(PWEN_1_115_MARK,    PORT115_FN4),
-        PINMUX_DATA(EXTLP_1_MARK,       PORT116_FN4),
-        PINMUX_DATA(OVCN2_1_MARK,       PORT117_FN4),
-        PINMUX_DATA(KEYIN0_121_MARK,    PORT121_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN1_122_MARK,    PORT122_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN2_123_MARK,    PORT123_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN3_124_MARK,    PORT124_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(PWEN_1_138_MARK,    PORT138_FN4),
-        PINMUX_DATA(IROUT_140_MARK,     PORT140_FN4),
-        PINMUX_DATA(LCDCS_MARK,         PORT145_FN4),
-        PINMUX_DATA(LCDWR_MARK,         PORT147_FN4),
-        PINMUX_DATA(LCDRS_MARK,         PORT149_FN4),
-        PINMUX_DATA(OVCN_1_162_MARK,    PORT162_FN4, MSEL4CR_14_1),
-        /* Function 5 */
-        PINMUX_DATA(GPI0_MARK,          PORT41_FN5),
-        PINMUX_DATA(GPI1_MARK,          PORT42_FN5),
-        PINMUX_DATA(GPO0_MARK,          PORT43_FN5),
-        PINMUX_DATA(GPO1_MARK,          PORT44_FN5),
-        PINMUX_DATA(I2C_SCL3S_MARK,     PORT137_FN5, MSEL4CR_16_0),
-        PINMUX_DATA(I2C_SDA3S_MARK,     PORT145_FN5, MSEL4CR_16_0),
-        PINMUX_DATA(I2C_SCL4S_MARK,     PORT146_FN5, MSEL4CR_17_0),
-        PINMUX_DATA(I2C_SDA4S_MARK,     PORT147_FN5, MSEL4CR_17_0),
-        /* Function select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,  MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,  MSEL3CR_6_1),
-        PINMUX_DATA(TS0_1SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_0),
-        PINMUX_DATA(TS0_2SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_1),
-        PINMUX_DATA(TS1_1SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_0),
-        PINMUX_DATA(TS1_2SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_1),
-        PINMUX_DATA(SDENC_CPG_MARK,     MSEL4CR_19_0),
-        PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
-        PINMUX_DATA(MFIv6_MARK,         MSEL4CR_6_0),
-        PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* PORT */
-        GPIO_PORT_ALL(),
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-        /* MMCIF(1) */
-        GPIO_FN(MMCD0_0),       GPIO_FN(MMCD0_1),       GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),       GPIO_FN(MMCD0_4),       GPIO_FN(MMCD0_5),
-        GPIO_FN(MMCD0_6),       GPIO_FN(MMCD0_7),       GPIO_FN(MMCCMD0),
-        GPIO_FN(MMCCLK0),
-        /* MMCIF(2) */
-        GPIO_FN(MMCD1_0),       GPIO_FN(MMCD1_1),       GPIO_FN(MMCD1_2),
-        GPIO_FN(MMCD1_3),       GPIO_FN(MMCD1_4),       GPIO_FN(MMCD1_5),
-        GPIO_FN(MMCD1_6),       GPIO_FN(MMCD1_7),       GPIO_FN(MMCCLK1),
-        GPIO_FN(MMCCMD1),
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-        /* SDHI0 */
-        GPIO_FN(SDHICLK0),      GPIO_FN(SDHICD0),       GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),       GPIO_FN(SDHID0_0),      GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),      GPIO_FN(SDHID0_3),
-        /* SDHI1 */
-        GPIO_FN(SDHICLK1),      GPIO_FN(SDHICMD1),      GPIO_FN(SDHID1_0),
-        GPIO_FN(SDHID1_1),      GPIO_FN(SDHID1_2),      GPIO_FN(SDHID1_3),
-        /* SDHI2 */
-        GPIO_FN(SDHICLK2),      GPIO_FN(SDHICMD2),      GPIO_FN(SDHID2_0),
-        GPIO_FN(SDHID2_1),      GPIO_FN(SDHID2_2),      GPIO_FN(SDHID2_3),
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0,       0xE6051000), /* PORT0CR */
-        PORTCR(1,       0xE6051001), /* PORT1CR */
-        PORTCR(2,       0xE6051002), /* PORT2CR */
-        PORTCR(3,       0xE6051003), /* PORT3CR */
-        PORTCR(4,       0xE6051004), /* PORT4CR */
-        PORTCR(5,       0xE6051005), /* PORT5CR */
-        PORTCR(6,       0xE6051006), /* PORT6CR */
-        PORTCR(7,       0xE6051007), /* PORT7CR */
-        PORTCR(8,       0xE6051008), /* PORT8CR */
-        PORTCR(9,       0xE6051009), /* PORT9CR */
-        PORTCR(10,      0xE605100A), /* PORT10CR */
-        PORTCR(11,      0xE605100B), /* PORT11CR */
-        PORTCR(12,      0xE605100C), /* PORT12CR */
-        PORTCR(13,      0xE605100D), /* PORT13CR */
-        PORTCR(14,      0xE605100E), /* PORT14CR */
-        PORTCR(15,      0xE605100F), /* PORT15CR */
-        PORTCR(16,      0xE6051010), /* PORT16CR */
-        PORTCR(17,      0xE6051011), /* PORT17CR */
-        PORTCR(18,      0xE6051012), /* PORT18CR */
-        PORTCR(19,      0xE6051013), /* PORT19CR */
-        PORTCR(20,      0xE6051014), /* PORT20CR */
-        PORTCR(21,      0xE6051015), /* PORT21CR */
-        PORTCR(22,      0xE6051016), /* PORT22CR */
-        PORTCR(23,      0xE6051017), /* PORT23CR */
-        PORTCR(24,      0xE6051018), /* PORT24CR */
-        PORTCR(25,      0xE6051019), /* PORT25CR */
-        PORTCR(26,      0xE605101A), /* PORT26CR */
-        PORTCR(27,      0xE605101B), /* PORT27CR */
-        PORTCR(28,      0xE605101C), /* PORT28CR */
-        PORTCR(29,      0xE605101D), /* PORT29CR */
-        PORTCR(30,      0xE605101E), /* PORT30CR */
-        PORTCR(31,      0xE605101F), /* PORT31CR */
-        PORTCR(32,      0xE6051020), /* PORT32CR */
-        PORTCR(33,      0xE6051021), /* PORT33CR */
-        PORTCR(34,      0xE6051022), /* PORT34CR */
-        PORTCR(35,      0xE6051023), /* PORT35CR */
-        PORTCR(36,      0xE6051024), /* PORT36CR */
-        PORTCR(37,      0xE6051025), /* PORT37CR */
-        PORTCR(38,      0xE6051026), /* PORT38CR */
-        PORTCR(39,      0xE6051027), /* PORT39CR */
-        PORTCR(40,      0xE6051028), /* PORT40CR */
-        PORTCR(41,      0xE6051029), /* PORT41CR */
-        PORTCR(42,      0xE605102A), /* PORT42CR */
-        PORTCR(43,      0xE605102B), /* PORT43CR */
-        PORTCR(44,      0xE605102C), /* PORT44CR */
-        PORTCR(45,      0xE605102D), /* PORT45CR */
-        PORTCR(46,      0xE605202E), /* PORT46CR */
-        PORTCR(47,      0xE605202F), /* PORT47CR */
-        PORTCR(48,      0xE6052030), /* PORT48CR */
-        PORTCR(49,      0xE6052031), /* PORT49CR */
-        PORTCR(50,      0xE6052032), /* PORT50CR */
-        PORTCR(51,      0xE6052033), /* PORT51CR */
-        PORTCR(52,      0xE6052034), /* PORT52CR */
-        PORTCR(53,      0xE6052035), /* PORT53CR */
-        PORTCR(54,      0xE6052036), /* PORT54CR */
-        PORTCR(55,      0xE6052037), /* PORT55CR */
-        PORTCR(56,      0xE6052038), /* PORT56CR */
-        PORTCR(57,      0xE6052039), /* PORT57CR */
-        PORTCR(58,      0xE605203A), /* PORT58CR */
-        PORTCR(59,      0xE605203B), /* PORT59CR */
-        PORTCR(60,      0xE605203C), /* PORT60CR */
-        PORTCR(61,      0xE605203D), /* PORT61CR */
-        PORTCR(62,      0xE605203E), /* PORT62CR */
-        PORTCR(63,      0xE605203F), /* PORT63CR */
-        PORTCR(64,      0xE6052040), /* PORT64CR */
-        PORTCR(65,      0xE6052041), /* PORT65CR */
-        PORTCR(66,      0xE6052042), /* PORT66CR */
-        PORTCR(67,      0xE6052043), /* PORT67CR */
-        PORTCR(68,      0xE6052044), /* PORT68CR */
-        PORTCR(69,      0xE6052045), /* PORT69CR */
-        PORTCR(70,      0xE6052046), /* PORT70CR */
-        PORTCR(71,      0xE6052047), /* PORT71CR */
-        PORTCR(72,      0xE6052048), /* PORT72CR */
-        PORTCR(73,      0xE6052049), /* PORT73CR */
-        PORTCR(74,      0xE605204A), /* PORT74CR */
-        PORTCR(75,      0xE605204B), /* PORT75CR */
-        PORTCR(76,      0xE605004C), /* PORT76CR */
-        PORTCR(77,      0xE605004D), /* PORT77CR */
-        PORTCR(78,      0xE605004E), /* PORT78CR */
-        PORTCR(79,      0xE605004F), /* PORT79CR */
-        PORTCR(80,      0xE6050050), /* PORT80CR */
-        PORTCR(81,      0xE6050051), /* PORT81CR */
-        PORTCR(82,      0xE6050052), /* PORT82CR */
-        PORTCR(83,      0xE6050053), /* PORT83CR */
-        PORTCR(84,      0xE6050054), /* PORT84CR */
-        PORTCR(85,      0xE6050055), /* PORT85CR */
-        PORTCR(86,      0xE6050056), /* PORT86CR */
-        PORTCR(87,      0xE6050057), /* PORT87CR */
-        PORTCR(88,      0xE6050058), /* PORT88CR */
-        PORTCR(89,      0xE6050059), /* PORT89CR */
-        PORTCR(90,      0xE605005A), /* PORT90CR */
-        PORTCR(91,      0xE605005B), /* PORT91CR */
-        PORTCR(92,      0xE605005C), /* PORT92CR */
-        PORTCR(93,      0xE605005D), /* PORT93CR */
-        PORTCR(94,      0xE605005E), /* PORT94CR */
-        PORTCR(95,      0xE605005F), /* PORT95CR */
-        PORTCR(96,      0xE6050060), /* PORT96CR */
-        PORTCR(97,      0xE6050061), /* PORT97CR */
-        PORTCR(98,      0xE6050062), /* PORT98CR */
-        PORTCR(99,      0xE6050063), /* PORT99CR */
-        PORTCR(100,     0xE6053064), /* PORT100CR */
-        PORTCR(101,     0xE6053065), /* PORT101CR */
-        PORTCR(102,     0xE6053066), /* PORT102CR */
-        PORTCR(103,     0xE6053067), /* PORT103CR */
-        PORTCR(104,     0xE6053068), /* PORT104CR */
-        PORTCR(105,     0xE6053069), /* PORT105CR */
-        PORTCR(106,     0xE605306A), /* PORT106CR */
-        PORTCR(107,     0xE605306B), /* PORT107CR */
-        PORTCR(108,     0xE605306C), /* PORT108CR */
-        PORTCR(109,     0xE605306D), /* PORT109CR */
-        PORTCR(110,     0xE605306E), /* PORT110CR */
-        PORTCR(111,     0xE605306F), /* PORT111CR */
-        PORTCR(112,     0xE6053070), /* PORT112CR */
-        PORTCR(113,     0xE6053071), /* PORT113CR */
-        PORTCR(114,     0xE6053072), /* PORT114CR */
-        PORTCR(115,     0xE6053073), /* PORT115CR */
-        PORTCR(116,     0xE6053074), /* PORT116CR */
-        PORTCR(117,     0xE6053075), /* PORT117CR */
-        PORTCR(118,     0xE6053076), /* PORT118CR */
-        PORTCR(119,     0xE6053077), /* PORT119CR */
-        PORTCR(120,     0xE6053078), /* PORT120CR */
-        PORTCR(121,     0xE6050079), /* PORT121CR */
-        PORTCR(122,     0xE605007A), /* PORT122CR */
-        PORTCR(123,     0xE605007B), /* PORT123CR */
-        PORTCR(124,     0xE605007C), /* PORT124CR */
-        PORTCR(125,     0xE605007D), /* PORT125CR */
-        PORTCR(126,     0xE605007E), /* PORT126CR */
-        PORTCR(127,     0xE605007F), /* PORT127CR */
-        PORTCR(128,     0xE6050080), /* PORT128CR */
-        PORTCR(129,     0xE6050081), /* PORT129CR */
-        PORTCR(130,     0xE6050082), /* PORT130CR */
-        PORTCR(131,     0xE6050083), /* PORT131CR */
-        PORTCR(132,     0xE6050084), /* PORT132CR */
-        PORTCR(133,     0xE6050085), /* PORT133CR */
-        PORTCR(134,     0xE6050086), /* PORT134CR */
-        PORTCR(135,     0xE6050087), /* PORT135CR */
-        PORTCR(136,     0xE6050088), /* PORT136CR */
-        PORTCR(137,     0xE6050089), /* PORT137CR */
-        PORTCR(138,     0xE605008A), /* PORT138CR */
-        PORTCR(139,     0xE605008B), /* PORT139CR */
-        PORTCR(140,     0xE605008C), /* PORT140CR */
-        PORTCR(141,     0xE605008D), /* PORT141CR */
-        PORTCR(142,     0xE605008E), /* PORT142CR */
-        PORTCR(143,     0xE605008F), /* PORT143CR */
-        PORTCR(144,     0xE6050090), /* PORT144CR */
-        PORTCR(145,     0xE6050091), /* PORT145CR */
-        PORTCR(146,     0xE6050092), /* PORT146CR */
-        PORTCR(147,     0xE6050093), /* PORT147CR */
-        PORTCR(148,     0xE6050094), /* PORT148CR */
-        PORTCR(149,     0xE6050095), /* PORT149CR */
-        PORTCR(150,     0xE6050096), /* PORT150CR */
-        PORTCR(151,     0xE6050097), /* PORT151CR */
-        PORTCR(152,     0xE6053098), /* PORT152CR */
-        PORTCR(153,     0xE6053099), /* PORT153CR */
-        PORTCR(154,     0xE605309A), /* PORT154CR */
-        PORTCR(155,     0xE605309B), /* PORT155CR */
-        PORTCR(156,     0xE605009C), /* PORT156CR */
-        PORTCR(157,     0xE605009D), /* PORT157CR */
-        PORTCR(158,     0xE605009E), /* PORT158CR */
-        PORTCR(159,     0xE605009F), /* PORT159CR */
-        PORTCR(160,     0xE60500A0), /* PORT160CR */
-        PORTCR(161,     0xE60500A1), /* PORT161CR */
-        PORTCR(162,     0xE60500A2), /* PORT162CR */
-        PORTCR(163,     0xE60500A3), /* PORT163CR */
-        PORTCR(164,     0xE60500A4), /* PORT164CR */
-        PORTCR(165,     0xE60500A5), /* PORT165CR */
-        PORTCR(166,     0xE60500A6), /* PORT166CR */
-        PORTCR(167,     0xE60520A7), /* PORT167CR */
-        PORTCR(168,     0xE60520A8), /* PORT168CR */
-        PORTCR(169,     0xE60520A9), /* PORT169CR */
-        PORTCR(170,     0xE60520AA), /* PORT170CR */
-        PORTCR(171,     0xE60520AB), /* PORT171CR */
-        PORTCR(172,     0xE60520AC), /* PORT172CR */
-        PORTCR(173,     0xE60520AD), /* PORT173CR */
-        PORTCR(174,     0xE60520AE), /* PORT174CR */
-        PORTCR(175,     0xE60520AF), /* PORT175CR */
-        PORTCR(176,     0xE60520B0), /* PORT176CR */
-        PORTCR(177,     0xE60520B1), /* PORT177CR */
-        PORTCR(178,     0xE60520B2), /* PORT178CR */
-        PORTCR(179,     0xE60520B3), /* PORT179CR */
-        PORTCR(180,     0xE60520B4), /* PORT180CR */
-        PORTCR(181,     0xE60520B5), /* PORT181CR */
-        PORTCR(182,     0xE60520B6), /* PORT182CR */
-        PORTCR(183,     0xE60520B7), /* PORT183CR */
-        PORTCR(184,     0xE60520B8), /* PORT184CR */
-        PORTCR(185,     0xE60520B9), /* PORT185CR */
-        PORTCR(186,     0xE60520BA), /* PORT186CR */
-        PORTCR(187,     0xE60520BB), /* PORT187CR */
-        PORTCR(188,     0xE60520BC), /* PORT188CR */
-        PORTCR(189,     0xE60520BD), /* PORT189CR */
-        PORTCR(190,     0xE60520BE), /* PORT190CR */
-        { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
-                        MSEL1CR_31_0,   MSEL1CR_31_1,
-                        MSEL1CR_30_0,   MSEL1CR_30_1,
-                        MSEL1CR_29_0,   MSEL1CR_29_1,
-                        MSEL1CR_28_0,   MSEL1CR_28_1,
-                        MSEL1CR_27_0,   MSEL1CR_27_1,
-                        MSEL1CR_26_0,   MSEL1CR_26_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL1CR_16_0,   MSEL1CR_16_1,
-                        MSEL1CR_15_0,   MSEL1CR_15_1,
-                        MSEL1CR_14_0,   MSEL1CR_14_1,
-                        MSEL1CR_13_0,   MSEL1CR_13_1,
-                        MSEL1CR_12_0,   MSEL1CR_12_1,
-                        0, 0, 0, 0,
-                        MSEL1CR_9_0,    MSEL1CR_9_1,
-                        MSEL1CR_8_0,    MSEL1CR_8_1,
-                        MSEL1CR_7_0,    MSEL1CR_7_1,
-                        MSEL1CR_6_0,    MSEL1CR_6_1,
-                        0, 0,
-                        MSEL1CR_4_0,    MSEL1CR_4_1,
-                        MSEL1CR_3_0,    MSEL1CR_3_1,
-                        MSEL1CR_2_0,    MSEL1CR_2_1,
-                        0, 0,
-                        MSEL1CR_0_0,    MSEL1CR_0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_27_0,   MSEL3CR_27_1,
-                        MSEL3CR_26_0,   MSEL3CR_26_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_21_0,   MSEL3CR_21_1,
-                        MSEL3CR_20_0,   MSEL3CR_20_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_15_0,   MSEL3CR_15_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL3CR_9_0,    MSEL3CR_9_1,
-                        0, 0, 0, 0,
-                        MSEL3CR_6_0,    MSEL3CR_6_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL4CR_19_0,   MSEL4CR_19_1,
-                        MSEL4CR_18_0,   MSEL4CR_18_1,
-                        MSEL4CR_17_0,   MSEL4CR_17_1,
-                        MSEL4CR_16_0,   MSEL4CR_16_1,
-                        MSEL4CR_15_0,   MSEL4CR_15_1,
-                        MSEL4CR_14_0,   MSEL4CR_14_1,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL4CR_10_0,   MSEL4CR_10_1,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL4CR_6_0,    MSEL4CR_6_1,
-                        0, 0,
-                        MSEL4CR_4_0,    MSEL4CR_4_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_1_0,    MSEL4CR_1_1,
-                        0, 0,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
-                        PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
-                        PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        PORT99_DATA,  PORT98_DATA,  PORT97_DATA,  PORT96_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        0, 0, 0, 0,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0,            PORT166_DATA, PORT165_DATA, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA,  PORT8_DATA,
-                        PORT7_DATA,  PORT6_DATA,  PORT5_DATA,  PORT4_DATA,
-                        PORT3_DATA,  PORT2_DATA,  PORT1_DATA,  PORT0_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0,           0,           PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
-                        0,            PORT190_DATA, PORT189_DATA, PORT188_DATA,
-                        PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
-                        PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
-                        PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
-                        PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
-                        PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
-                        PORT167_DATA, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT120_DATA,
-                        PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
-                        0, 0, 0, 0,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { },
-};
-#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
-#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
-};
-static struct pinmux_info sh7372_pinmux_info = {
-        .name = "sh7372_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_SDENC_DV_CLKI,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq = pinmux_irqs,
-        .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
-void sh7372_pinmux_init(void)
-{
-        register_pinmux(&sh7372_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
deleted file mode 100644
index b442f9d8c716..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ /dev/null
@@ -1,2803 +0,0 @@
-/*
- * sh73a0 processor support - PFC hardware block
- *
- * Copyright (C) 2010 Renesas Solutions Corp.
- * Copyright (C) 2010 NISHIMOTO Hiroki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh73a0.h>
-#include <mach/irqs.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx,    sfx), PORT_10(fn, pfx##1, sfx),     \
-        PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx),     \
-        PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx),     \
-        PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx),     \
-        PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx),     \
-        PORT_10(fn, pfx##10, sfx),                              \
-        PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),   \
-        PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),   \
-        PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),   \
-        PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),   \
-        PORT_1(fn, pfx##118, sfx),                              \
-        PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),   \
-        PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),   \
-        PORT_10(fn, pfx##15, sfx),                              \
-        PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),   \
-        PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),   \
-        PORT_1(fn, pfx##164, sfx),                              \
-        PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),   \
-        PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),   \
-        PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),   \
-        PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),   \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx),   \
-        PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx),   \
-        PORT_1(fn, pfx##282, sfx),                              \
-        PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx),   \
-        PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
-        PINMUX_INPUT_END,
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
-        PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
-        PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
-        PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
-        PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
-        PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
-        PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
-        PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
-        PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
-        PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
-        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* Hardware manual Table 25-1 (Function 0-7) */
-        VBUS_0_MARK,
-        GPI0_MARK,
-        GPI1_MARK,
-        GPI2_MARK,
-        GPI3_MARK,
-        GPI4_MARK,
-        GPI5_MARK,
-        GPI6_MARK,
-        GPI7_MARK,
-        SCIFA7_RXD_MARK,
-        SCIFA7_CTS__MARK,
-        GPO7_MARK, MFG0_OUT2_MARK,
-        GPO6_MARK, MFG1_OUT2_MARK,
-        GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
-        SCIFA0_TXD_MARK,
-        SCIFA7_TXD_MARK,
-        SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
-        GPO0_MARK,
-        GPO1_MARK,
-        GPO2_MARK, STATUS0_MARK,
-        GPO3_MARK, STATUS1_MARK,
-        GPO4_MARK, STATUS2_MARK,
-        VINT_MARK,
-        TCKON_MARK,
-        XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
-        MFG0_OUT1_MARK, PORT27_IROUT_MARK,
-        XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
-        PORT28_TPU1TO1_MARK,
-        SIM_RST_MARK, PORT29_TPU1TO1_MARK,
-        SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
-        SIM_D_MARK, PORT31_IROUT_MARK,
-        SCIFA4_TXD_MARK,
-        SCIFA4_RXD_MARK, XWUP_MARK,
-        SCIFA4_RTS__MARK,
-        SCIFA4_CTS__MARK,
-        FSIBOBT_MARK, FSIBIBT_MARK,
-        FSIBOLR_MARK, FSIBILR_MARK,
-        FSIBOSLD_MARK,
-        FSIBISLD_MARK,
-        VACK_MARK,
-        XTAL1L_MARK,
-        SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
-        SCIFA0_RXD_MARK,
-        SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
-        FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
-        FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
-        FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
-        FSICISLD_MARK, FSIDISLD_MARK,
-        FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
-        FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
-        FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
-        FSIAOSLD_MARK, BBIF2_TXD2_MARK,
-        FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
-        PORT53_FSICSPDIF_MARK,
-        FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
-        FSICCK_MARK, FSICOMC_MARK,
-        FSIAISLD_MARK, TPU0TO0_MARK,
-        A0_MARK, BS__MARK,
-        A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
-        A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
-        A14_MARK, KEYOUT5_MARK,
-        A15_MARK, KEYOUT4_MARK,
-        A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
-        A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
-        A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
-        A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
-        A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
-        A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
-        A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
-        A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
-        A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
-        A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, KEYIN6_MARK,
-        KEYIN7_MARK,
-        D0_NAF0_MARK,
-        D1_NAF1_MARK,
-        D2_NAF2_MARK,
-        D3_NAF3_MARK,
-        D4_NAF4_MARK,
-        D5_NAF5_MARK,
-        D6_NAF6_MARK,
-        D7_NAF7_MARK,
-        D8_NAF8_MARK,
-        D9_NAF9_MARK,
-        D10_NAF10_MARK,
-        D11_NAF11_MARK,
-        D12_NAF12_MARK,
-        D13_NAF13_MARK,
-        D14_NAF14_MARK,
-        D15_NAF15_MARK,
-        CS4__MARK,
-        CS5A__MARK, PORT91_RDWR_MARK,
-        CS5B__MARK, FCE1__MARK,
-        CS6B__MARK, DACK0_MARK,
-        FCE0__MARK, CS6A__MARK,
-        WAIT__MARK, DREQ0_MARK,
-        RD__FSC_MARK,
-        WE0__FWE_MARK, RDWR_FWE_MARK,
-        WE1__MARK,
-        FRB_MARK,
-        CKO_MARK,
-        NBRSTOUT__MARK,
-        NBRST__MARK,
-        BBIF2_TXD_MARK,
-        BBIF2_RXD_MARK,
-        BBIF2_SYNC_MARK,
-        BBIF2_SCK_MARK,
-        SCIFA3_CTS__MARK, MFG3_IN2_MARK,
-        SCIFA3_RXD_MARK, MFG3_IN1_MARK,
-        BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
-        SCIFA3_TXD_MARK,
-        HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
-        HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
-        HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
-        HSI_TX_READY_MARK, BBIF1_TXD_MARK,
-        HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
-        PORT115_I2C_SCL3_MARK,
-        HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
-        PORT116_I2C_SDA3_MARK,
-        HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
-        HSI_TX_FLAG_MARK,
-        VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
-        VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
-        VIO2_HD_MARK, LCD2D1_MARK,
-        VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
-        VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
-        PORT131_KEYOUT11_MARK, LCD2D11_MARK,
-        VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
-        PORT132_KEYOUT10_MARK, LCD2D12_MARK,
-        VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
-        VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
-        VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
-        VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
-        VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
-        VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
-        VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
-        VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
-        VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
-        VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
-        VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
-        VIO2_D5_MARK, LCD2D3_MARK,
-        VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
-        VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
-        PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
-        VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
-        LCD2D18_MARK,
-        VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
-        VIO_CKO_MARK,
-        A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
-        MFG0_IN2_MARK,
-        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
-        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
-        SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
-        SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
-        SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
-        SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
-        DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
-        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
-        PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
-        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
-        PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
-        LCDD0_MARK,
-        LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
-        LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
-        LCDD6_MARK,
-        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
-        LCDD8_MARK, D16_MARK,
-        LCDD9_MARK, D17_MARK,
-        LCDD10_MARK, D18_MARK,
-        LCDD11_MARK, D19_MARK,
-        LCDD12_MARK, D20_MARK,
-        LCDD13_MARK, D21_MARK,
-        LCDD14_MARK, D22_MARK,
-        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
-        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
-        LCDD17_MARK, D25_MARK,
-        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
-        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
-        LCDDCK_MARK, LCDWR__MARK,
-        LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
-        VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
-        LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
-        PORT218_VIO_CKOR_MARK,
-        LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
-        MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
-        LCDVSYN_MARK, LCDVSYN2_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
-        MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
-        VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
-        SCIFA1_TXD_MARK, OVCN2_MARK,
-        EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
-        SCIFA1_RTS__MARK, IDIN_MARK,
-        SCIFA1_RXD_MARK,
-        SCIFA1_CTS__MARK, MFG1_IN1_MARK,
-        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
-        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
-        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
-        MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
-        MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
-        MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
-        MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
-        MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
-        MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
-        SCIFA6_TXD_MARK,
-        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
-        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
-        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
-        PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
-        MSIOF2R_RXD_MARK,
-        PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
-        MSIOF2R_TXD_MARK,
-        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
-        TPU1TO0_MARK,
-        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
-        TPU3TO1_MARK,
-        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
-        TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
-        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
-        MSIOF2R_TSYNC_MARK,
-        SDHICLK0_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK,
-        SDHID0_1_MARK,
-        SDHID0_2_MARK,
-        SDHID0_3_MARK,
-        SDHICMD0_MARK,
-        SDHIWP0_MARK,
-        SDHICLK1_MARK,
-        SDHID1_0_MARK, TS_SPSYNC2_MARK,
-        SDHID1_1_MARK, TS_SDAT2_MARK,
-        SDHID1_2_MARK, TS_SDEN2_MARK,
-        SDHID1_3_MARK, TS_SCK2_MARK,
-        SDHICMD1_MARK,
-        SDHICLK2_MARK,
-        SDHID2_0_MARK, TS_SPSYNC4_MARK,
-        SDHID2_1_MARK, TS_SDAT4_MARK,
-        SDHID2_2_MARK, TS_SDEN4_MARK,
-        SDHID2_3_MARK, TS_SCK4_MARK,
-        SDHICMD2_MARK,
-        MMCCLK0_MARK,
-        MMCD0_0_MARK,
-        MMCD0_1_MARK,
-        MMCD0_2_MARK,
-        MMCD0_3_MARK,
-        MMCD0_4_MARK, TS_SPSYNC5_MARK,
-        MMCD0_5_MARK, TS_SDAT5_MARK,
-        MMCD0_6_MARK, TS_SDEN5_MARK,
-        MMCD0_7_MARK, TS_SCK5_MARK,
-        MMCCMD0_MARK,
-        RESETOUTS__MARK, EXTAL2OUT_MARK,
-        MCP_WAIT__MCP_FRB_MARK,
-        MCP_CKO_MARK, MMCCLK1_MARK,
-        MCP_D15_MCP_NAF15_MARK,
-        MCP_D14_MCP_NAF14_MARK,
-        MCP_D13_MCP_NAF13_MARK,
-        MCP_D12_MCP_NAF12_MARK,
-        MCP_D11_MCP_NAF11_MARK,
-        MCP_D10_MCP_NAF10_MARK,
-        MCP_D9_MCP_NAF9_MARK,
-        MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
-        MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
-        MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
-        MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
-        MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
-        MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
-        MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
-        MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
-        MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
-        MCP_NBRSTOUT__MARK,
-        MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
-        /* MSEL2 special cases */
-        TSIF2_TS_XX1_MARK,
-        TSIF2_TS_XX2_MARK,
-        TSIF2_TS_XX3_MARK,
-        TSIF2_TS_XX4_MARK,
-        TSIF2_TS_XX5_MARK,
-        TSIF1_TS_XX1_MARK,
-        TSIF1_TS_XX2_MARK,
-        TSIF1_TS_XX3_MARK,
-        TSIF1_TS_XX4_MARK,
-        TSIF1_TS_XX5_MARK,
-        TSIF0_TS_XX1_MARK,
-        TSIF0_TS_XX2_MARK,
-        TSIF0_TS_XX3_MARK,
-        TSIF0_TS_XX4_MARK,
-        TSIF0_TS_XX5_MARK,
-        MST1_TS_XX1_MARK,
-        MST1_TS_XX2_MARK,
-        MST1_TS_XX3_MARK,
-        MST1_TS_XX4_MARK,
-        MST1_TS_XX5_MARK,
-        MST0_TS_XX1_MARK,
-        MST0_TS_XX2_MARK,
-        MST0_TS_XX3_MARK,
-        MST0_TS_XX4_MARK,
-        MST0_TS_XX5_MARK,
-        /* MSEL3 special cases */
-        SDHI0_VCCQ_MC0_ON_MARK,
-        SDHI0_VCCQ_MC0_OFF_MARK,
-        DEBUG_MON_VIO_MARK,
-        DEBUG_MON_LCDD_MARK,
-        LCDC_LCDC0_MARK,
-        LCDC_LCDC1_MARK,
-        /* MSEL4 special cases */
-        IRQ9_MEM_INT_MARK,
-        IRQ9_MCP_INT_MARK,
-        A11_MARK,
-        KEYOUT8_MARK,
-        TPU4TO3_MARK,
-        RESETA_N_PU_ON_MARK,
-        RESETA_N_PU_OFF_MARK,
-        EDBGREQ_PD_MARK,
-        EDBGREQ_PU_MARK,
-        /* Functions with pull-ups */
-        KEYIN0_PU_MARK,
-        KEYIN1_PU_MARK,
-        KEYIN2_PU_MARK,
-        KEYIN3_PU_MARK,
-        KEYIN4_PU_MARK,
-        KEYIN5_PU_MARK,
-        KEYIN6_PU_MARK,
-        KEYIN7_PU_MARK,
-        SDHICD0_PU_MARK,
-        SDHID0_0_PU_MARK,
-        SDHID0_1_PU_MARK,
-        SDHID0_2_PU_MARK,
-        SDHID0_3_PU_MARK,
-        SDHICMD0_PU_MARK,
-        SDHIWP0_PU_MARK,
-        SDHID1_0_PU_MARK,
-        SDHID1_1_PU_MARK,
-        SDHID1_2_PU_MARK,
-        SDHID1_3_PU_MARK,
-        SDHICMD1_PU_MARK,
-        SDHID2_0_PU_MARK,
-        SDHID2_1_PU_MARK,
-        SDHID2_2_PU_MARK,
-        SDHID2_3_PU_MARK,
-        SDHICMD2_PU_MARK,
-        MMCCMD0_PU_MARK,
-        MMCCMD1_PU_MARK,
-        MMCD0_0_PU_MARK,
-        MMCD0_1_PU_MARK,
-        MMCD0_2_PU_MARK,
-        MMCD0_3_PU_MARK,
-        MMCD0_4_PU_MARK,
-        MMCD0_5_PU_MARK,
-        MMCD0_6_PU_MARK,
-        MMCD0_7_PU_MARK,
-        FSIBISLD_PU_MARK,
-        FSIACK_PU_MARK,
-        FSIAILR_PU_MARK,
-        FSIAIBT_PU_MARK,
-        FSIAISLD_PU_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* Table 25-1 (I/O and Pull U/D) */
-        PORT_DATA_I_PD(0),
-        PORT_DATA_I_PU(1),
-        PORT_DATA_I_PU(2),
-        PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4),
-        PORT_DATA_I_PU(5),
-        PORT_DATA_I_PU(6),
-        PORT_DATA_I_PU(7),
-        PORT_DATA_I_PU(8),
-        PORT_DATA_I_PD(9),
-        PORT_DATA_I_PD(10),
-        PORT_DATA_I_PU_PD(11),
-        PORT_DATA_IO_PU_PD(12),
-        PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PU_PD(14),
-        PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_IO_PD(16),
-        PORT_DATA_IO_PD(17),
-        PORT_DATA_IO_PU(18),
-        PORT_DATA_IO_PU(19),
-        PORT_DATA_O(20),
-        PORT_DATA_O(21),
-        PORT_DATA_O(22),
-        PORT_DATA_O(23),
-        PORT_DATA_O(24),
-        PORT_DATA_I_PD(25),
-        PORT_DATA_I_PD(26),
-        PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),
-        PORT_DATA_IO_PD(29),
-        PORT_DATA_IO_PD(30),
-        PORT_DATA_IO_PU(31),
-        PORT_DATA_IO_PD(32),
-        PORT_DATA_I_PU_PD(33),
-        PORT_DATA_IO_PD(34),
-        PORT_DATA_I_PU_PD(35),
-        PORT_DATA_IO_PD(36),
-        PORT_DATA_IO(37),
-        PORT_DATA_O(38),
-        PORT_DATA_I_PU(39),
-        PORT_DATA_I_PU_PD(40),
-        PORT_DATA_O(41),
-        PORT_DATA_IO_PD(42),
-        PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),
-        PORT_DATA_IO_PD(45),
-        PORT_DATA_IO_PD(46),
-        PORT_DATA_IO_PD(47),
-        PORT_DATA_I_PD(48),
-        PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PD(50),
-        PORT_DATA_IO_PD(51),
-        PORT_DATA_O(52),
-        PORT_DATA_IO_PU_PD(53),
-        PORT_DATA_IO_PU_PD(54),
-        PORT_DATA_IO_PD(55),
-        PORT_DATA_I_PU_PD(56),
-        PORT_DATA_IO(57),
-        PORT_DATA_IO(58),
-        PORT_DATA_IO(59),
-        PORT_DATA_IO(60),
-        PORT_DATA_IO(61),
-        PORT_DATA_IO_PD(62),
-        PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PU_PD(64),
-        PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),
-        PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),
-        PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70),
-        PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),
-        PORT_DATA_I_PU_PD(73),
-        PORT_DATA_IO_PU(74),
-        PORT_DATA_IO_PU(75),
-        PORT_DATA_IO_PU(76),
-        PORT_DATA_IO_PU(77),
-        PORT_DATA_IO_PU(78),
-        PORT_DATA_IO_PU(79),
-        PORT_DATA_IO_PU(80),
-        PORT_DATA_IO_PU(81),
-        PORT_DATA_IO_PU(82),
-        PORT_DATA_IO_PU(83),
-        PORT_DATA_IO_PU(84),
-        PORT_DATA_IO_PU(85),
-        PORT_DATA_IO_PU(86),
-        PORT_DATA_IO_PU(87),
-        PORT_DATA_IO_PU(88),
-        PORT_DATA_IO_PU(89),
-        PORT_DATA_O(90),
-        PORT_DATA_IO_PU(91),
-        PORT_DATA_O(92),
-        PORT_DATA_IO_PU(93),
-        PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO(96),
-        PORT_DATA_IO(97),
-        PORT_DATA_IO(98),
-        PORT_DATA_I_PU(99),
-        PORT_DATA_O(100),
-        PORT_DATA_O(101),
-        PORT_DATA_I_PU(102),
-        PORT_DATA_IO_PD(103),
-        PORT_DATA_I_PU_PD(104),
-        PORT_DATA_I_PD(105),
-        PORT_DATA_I_PD(106),
-        PORT_DATA_I_PU_PD(107),
-        PORT_DATA_I_PU_PD(108),
-        PORT_DATA_IO_PD(109),
-        PORT_DATA_IO_PD(110),
-        PORT_DATA_IO_PU_PD(111),
-        PORT_DATA_IO_PU_PD(112),
-        PORT_DATA_IO_PU_PD(113),
-        PORT_DATA_IO_PD(114),
-        PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),
-        PORT_DATA_IO_PU_PD(117),
-        PORT_DATA_IO_PU_PD(118),
-        PORT_DATA_IO_PD(128),
-        PORT_DATA_IO_PD(129),
-        PORT_DATA_IO_PU_PD(130),
-        PORT_DATA_IO_PD(131),
-        PORT_DATA_IO_PD(132),
-        PORT_DATA_IO_PD(133),
-        PORT_DATA_IO_PU_PD(134),
-        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PU_PD(136),
-        PORT_DATA_IO_PU_PD(137),
-        PORT_DATA_IO_PD(138),
-        PORT_DATA_IO_PD(139),
-        PORT_DATA_IO_PD(140),
-        PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),
-        PORT_DATA_IO_PD(143),
-        PORT_DATA_IO_PU_PD(144),
-        PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PU_PD(146),
-        PORT_DATA_IO_PU_PD(147),
-        PORT_DATA_IO_PU_PD(148),
-        PORT_DATA_IO_PU_PD(149),
-        PORT_DATA_I_PU_PD(150),
-        PORT_DATA_IO_PU_PD(151),
-        PORT_DATA_IO_PU_PD(152),
-        PORT_DATA_IO_PD(153),
-        PORT_DATA_IO_PD(154),
-        PORT_DATA_I_PU_PD(155),
-        PORT_DATA_IO_PU_PD(156),
-        PORT_DATA_I_PD(157),
-        PORT_DATA_IO_PD(158),
-        PORT_DATA_IO_PU_PD(159),
-        PORT_DATA_IO_PU_PD(160),
-        PORT_DATA_I_PU_PD(161),
-        PORT_DATA_I_PU_PD(162),
-        PORT_DATA_IO_PU_PD(163),
-        PORT_DATA_I_PU_PD(164),
-        PORT_DATA_IO_PD(192),
-        PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PD(194),
-        PORT_DATA_IO_PU_PD(195),
-        PORT_DATA_IO_PD(196),
-        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PD(198),
-        PORT_DATA_IO_PD(199),
-        PORT_DATA_IO_PU_PD(200),
-        PORT_DATA_IO_PU_PD(201),
-        PORT_DATA_IO_PU_PD(202),
-        PORT_DATA_IO_PU_PD(203),
-        PORT_DATA_IO_PU_PD(204),
-        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),
-        PORT_DATA_IO_PD(207),
-        PORT_DATA_IO_PD(208),
-        PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210),
-        PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212),
-        PORT_DATA_IO_PD(213),
-        PORT_DATA_IO_PU_PD(214),
-        PORT_DATA_IO_PU_PD(215),
-        PORT_DATA_IO_PD(216),
-        PORT_DATA_IO_PD(217),
-        PORT_DATA_O(218),
-        PORT_DATA_IO_PD(219),
-        PORT_DATA_IO_PD(220),
-        PORT_DATA_IO_PU_PD(221),
-        PORT_DATA_IO_PU_PD(222),
-        PORT_DATA_I_PU_PD(223),
-        PORT_DATA_I_PU_PD(224),
-        PORT_DATA_IO_PU_PD(225),
-        PORT_DATA_O(226),
-        PORT_DATA_IO_PU_PD(227),
-        PORT_DATA_I_PU_PD(228),
-        PORT_DATA_I_PD(229),
-        PORT_DATA_IO(230),
-        PORT_DATA_IO_PU_PD(231),
-        PORT_DATA_IO_PU_PD(232),
-        PORT_DATA_I_PU_PD(233),
-        PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_IO_PU_PD(235),
-        PORT_DATA_IO_PU_PD(236),
-        PORT_DATA_IO_PD(237),
-        PORT_DATA_IO_PU_PD(238),
-        PORT_DATA_IO_PU_PD(239),
-        PORT_DATA_IO_PU_PD(240),
-        PORT_DATA_O(241),
-        PORT_DATA_I_PD(242),
-        PORT_DATA_IO_PU_PD(243),
-        PORT_DATA_IO_PU_PD(244),
-        PORT_DATA_IO_PU_PD(245),
-        PORT_DATA_IO_PU_PD(246),
-        PORT_DATA_IO_PU_PD(247),
-        PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_IO_PU_PD(249),
-        PORT_DATA_IO_PU_PD(250),
-        PORT_DATA_IO_PU_PD(251),
-        PORT_DATA_IO_PU_PD(252),
-        PORT_DATA_IO_PU_PD(253),
-        PORT_DATA_IO_PU_PD(254),
-        PORT_DATA_IO_PU_PD(255),
-        PORT_DATA_IO_PU_PD(256),
-        PORT_DATA_IO_PU_PD(257),
-        PORT_DATA_IO_PU_PD(258),
-        PORT_DATA_IO_PU_PD(259),
-        PORT_DATA_IO_PU_PD(260),
-        PORT_DATA_IO_PU_PD(261),
-        PORT_DATA_IO_PU_PD(262),
-        PORT_DATA_IO_PU_PD(263),
-        PORT_DATA_IO_PU_PD(264),
-        PORT_DATA_IO_PU_PD(265),
-        PORT_DATA_IO_PU_PD(266),
-        PORT_DATA_IO_PU_PD(267),
-        PORT_DATA_IO_PU_PD(268),
-        PORT_DATA_IO_PU_PD(269),
-        PORT_DATA_IO_PU_PD(270),
-        PORT_DATA_IO_PU_PD(271),
-        PORT_DATA_IO_PU_PD(272),
-        PORT_DATA_IO_PU_PD(273),
-        PORT_DATA_IO_PU_PD(274),
-        PORT_DATA_IO_PU_PD(275),
-        PORT_DATA_IO_PU_PD(276),
-        PORT_DATA_IO_PU_PD(277),
-        PORT_DATA_IO_PU_PD(278),
-        PORT_DATA_IO_PU_PD(279),
-        PORT_DATA_IO_PU_PD(280),
-        PORT_DATA_O(281),
-        PORT_DATA_O(282),
-        PORT_DATA_I_PU(288),
-        PORT_DATA_IO_PU_PD(289),
-        PORT_DATA_IO_PU_PD(290),
-        PORT_DATA_IO_PU_PD(291),
-        PORT_DATA_IO_PU_PD(292),
-        PORT_DATA_IO_PU_PD(293),
-        PORT_DATA_IO_PU_PD(294),
-        PORT_DATA_IO_PU_PD(295),
-        PORT_DATA_IO_PU_PD(296),
-        PORT_DATA_IO_PU_PD(297),
-        PORT_DATA_IO_PU_PD(298),
-        PORT_DATA_IO_PU_PD(299),
-        PORT_DATA_IO_PU_PD(300),
-        PORT_DATA_IO_PU_PD(301),
-        PORT_DATA_IO_PU_PD(302),
-        PORT_DATA_IO_PU_PD(303),
-        PORT_DATA_IO_PU_PD(304),
-        PORT_DATA_IO_PU_PD(305),
-        PORT_DATA_O(306),
-        PORT_DATA_O(307),
-        PORT_DATA_I_PU(308),
-        PORT_DATA_O(309),
-        /* Table 25-1 (Function 0-7) */
-        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
-        PINMUX_DATA(GPI0_MARK, PORT1_FN1),
-        PINMUX_DATA(GPI1_MARK, PORT2_FN1),
-        PINMUX_DATA(GPI2_MARK, PORT3_FN1),
-        PINMUX_DATA(GPI3_MARK, PORT4_FN1),
-        PINMUX_DATA(GPI4_MARK, PORT5_FN1),
-        PINMUX_DATA(GPI5_MARK, PORT6_FN1),
-        PINMUX_DATA(GPI6_MARK, PORT7_FN1),
-        PINMUX_DATA(GPI7_MARK, PORT8_FN1),
-        PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
-        PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
-        PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
-        PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
-        PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
-        PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
-        PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
-        PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
-        PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
-        PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
-        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
-        PINMUX_DATA(GPO0_MARK, PORT20_FN1),
-        PINMUX_DATA(GPO1_MARK, PORT21_FN1),
-        PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(VINT_MARK, PORT25_FN1),
-        PINMUX_DATA(TCKON_MARK, PORT26_FN1),
-        PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
-        PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_1), \
-        PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_1), \
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
-        PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
-        PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
-        PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_1), \
-        PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_1), \
-        PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
-        PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
-        PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
-        PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
-        PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
-        PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
-        PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
-        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
-        PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
-        PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
-        PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
-        PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
-        PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
-        PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
-        PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
-        PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
-        PINMUX_DATA(VACK_MARK, PORT40_FN1),
-        PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
-        PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
-        PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
-        PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
-        PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
-        PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
-        PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
-        PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
-        PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
-        PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
-        PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
-        PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
-        PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
-        PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
-        PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
-        PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
-        PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
-        PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
-        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
-        PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
-        PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
-        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
-        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
-        PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
-        PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
-        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
-        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
-        PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
-        PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
-        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
-        PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
-        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
-        PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
-        PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
-        PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
-        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
-        PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
-        PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
-        PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
-        PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
-        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
-        PINMUX_DATA(A0_MARK, PORT57_FN1), \
-        PINMUX_DATA(BS__MARK, PORT57_FN2),
-        PINMUX_DATA(A12_MARK, PORT58_FN1), \
-        PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
-        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
-        PINMUX_DATA(A13_MARK, PORT59_FN1), \
-        PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
-        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
-        PINMUX_DATA(A14_MARK, PORT60_FN1), \
-        PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
-        PINMUX_DATA(A15_MARK, PORT61_FN1), \
-        PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
-        PINMUX_DATA(A16_MARK, PORT62_FN1), \
-        PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A17_MARK, PORT63_FN1), \
-        PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A18_MARK, PORT64_FN1), \
-        PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A19_MARK, PORT65_FN1), \
-        PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A20_MARK, PORT66_FN1), \
-        PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A21_MARK, PORT67_FN1), \
-        PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A22_MARK, PORT68_FN1), \
-        PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A23_MARK, PORT69_FN1), \
-        PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A24_MARK, PORT70_FN1), \
-        PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A25_MARK, PORT71_FN1), \
-        PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A26_MARK, PORT72_FN1), \
-        PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
-        PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
-        PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
-        PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
-        PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
-        PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
-        PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
-        PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
-        PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
-        PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
-        PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
-        PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
-        PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
-        PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
-        PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
-        PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
-        PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
-        PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
-        PINMUX_DATA(CS4__MARK, PORT90_FN1),
-        PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
-        PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
-        PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
-        PINMUX_DATA(FCE1__MARK, PORT92_FN2),
-        PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
-        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
-        PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
-        PINMUX_DATA(CS6A__MARK, PORT94_FN2),
-        PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
-        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
-        PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
-        PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
-        PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
-        PINMUX_DATA(WE1__MARK, PORT98_FN1),
-        PINMUX_DATA(FRB_MARK, PORT99_FN1),
-        PINMUX_DATA(CKO_MARK, PORT100_FN1),
-        PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
-        PINMUX_DATA(NBRST__MARK, PORT102_FN1),
-        PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
-        PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
-        PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
-        PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
-        PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
-        PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
-        PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
-        PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
-        PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
-        PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
-        PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
-        PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
-        PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
-        PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
-        PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
-        PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
-        PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
-        PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
-        PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
-        PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
-        PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
-        PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
-        PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
-        PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
-        PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
-        PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
-        PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
-        PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
-        PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
-        PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
-        PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
-        PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
-        PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
-        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
-        PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
-        PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
-        PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
-        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
-        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
-                MSEL4CR_MSEL10_1), \
-        PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
-        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
-        PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
-        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
-        PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
-        PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
-        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
-        PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
-        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
-        PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
-        PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
-        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
-        PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
-        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
-        PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
-        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
-        PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
-        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
-        PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
-        PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
-        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
-        PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
-        PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
-        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
-        PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
-        PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
-        PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
-        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
-        PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
-        PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
-        PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
-        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
-        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
-        PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
-        PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
-        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
-        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
-        PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
-        PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
-        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
-        PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
-        PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
-        PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
-        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
-        PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
-        PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
-        PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
-        PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
-        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
-        PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
-        PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
-        PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
-        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
-        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
-        PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
-        PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
-        PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
-        PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
-        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
-        PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
-        PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
-        PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
-        PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
-        PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
-        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
-        PINMUX_DATA(A27_MARK, PORT149_FN1), \
-        PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
-        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
-        PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
-        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
-        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
-        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
-        PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
-        PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
-                MSEL4CR_MSEL10_0),
-        PINMUX_DATA(DINT__MARK, PORT158_FN1), \
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
-        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
-        PINMUX_DATA(NMI_MARK, PORT159_FN3),
-        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
-        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
-        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
-        PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
-        PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
-        PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
-        PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
-        PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
-        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
-        PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
-        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1),
-        PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
-        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
-        PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
-        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
-        PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
-        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
-        PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
-        PINMUX_DATA(D16_MARK, PORT200_FN6),
-        PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
-        PINMUX_DATA(D17_MARK, PORT201_FN6),
-        PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
-        PINMUX_DATA(D18_MARK, PORT202_FN6),
-        PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
-        PINMUX_DATA(D19_MARK, PORT203_FN6),
-        PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
-        PINMUX_DATA(D20_MARK, PORT204_FN6),
-        PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
-        PINMUX_DATA(D21_MARK, PORT205_FN6),
-        PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
-        PINMUX_DATA(D22_MARK, PORT206_FN6),
-        PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
-        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D23_MARK, PORT207_FN6),
-        PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
-        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D24_MARK, PORT208_FN6),
-        PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
-        PINMUX_DATA(D25_MARK, PORT209_FN6),
-        PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
-        PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
-        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D26_MARK, PORT210_FN6),
-        PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
-        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D27_MARK, PORT211_FN6),
-        PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D28_MARK, PORT212_FN6),
-        PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
-        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D29_MARK, PORT213_FN6),
-        PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
-        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D30_MARK, PORT214_FN6),
-        PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
-        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D31_MARK, PORT215_FN6),
-        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
-        PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
-        PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
-        PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
-        PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
-        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
-        PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
-        PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
-        PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
-        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
-        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
-        PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
-        PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
-        PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
-        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
-        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
-        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
-        PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
-        PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
-        PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
-        PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
-        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
-        PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
-        PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
-        PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
-        PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
-        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
-        PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
-        PINMUX_DATA(IDIN_MARK, PORT227_FN4),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
-        PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
-        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
-        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
-        PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
-        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
-        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
-        PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
-        PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
-        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
-        PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
-        PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_0),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
-        PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_0),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
-        PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
-        PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
-        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
-        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
-        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
-        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
-        PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
-        PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
-        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
-        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
-        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
-        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
-        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
-        PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
-        PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
-        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
-        PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
-        PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
-        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
-        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
-        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
-        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
-        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
-        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
-        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
-        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
-        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
-        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
-        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
-        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
-        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
-        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
-        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
-        PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
-        PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
-        PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
-        PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
-        PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
-        PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
-        PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
-        PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
-        PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
-        PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
-        PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
-        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
-        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
-        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
-        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
-        PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
-        PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
-        PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
-        PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
-        PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
-        PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
-        PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
-        PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
-        PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
-        PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
-        PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
-        PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
-        PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
-        PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
-        PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
-        PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
-        PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
-        PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
-        PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
-        PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
-        PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
-        PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
-        /* MSEL2 special cases */
-        PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_1),
-        PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-                MSEL2CR_MSEL12_1),
-        PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_1),
-        PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-                MSEL2CR_MSEL9_1),
-        PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_1),
-        PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-                MSEL2CR_MSEL6_1),
-        PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_1),
-        PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-                MSEL2CR_MSEL3_1),
-        PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_0),
-        PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_1),
-        PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-                MSEL2CR_MSEL0_0),
-        PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-                MSEL2CR_MSEL0_1),
-        PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_0),
-        /* MSEL3 special cases */
-        PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
-        PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
-        PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
-        PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
-        PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
-        PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
-        /* MSEL4 special cases */
-        PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
-        PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
-        PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
-        PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
-        PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
-        PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
-        PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
-        PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
-        PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
-        /* Functions with pull-ups */
-        PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
-        PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
-        PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
-        PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
-        PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
-        PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
-        PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
-        PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
-        PINMUX_DATA(SDHICD0_PU_MARK,  PORT251_FN1, PORT251_IN_PU),
-        PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
-        PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
-        PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
-        PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
-        PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHIWP0_PU_MARK,  PORT257_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
-        PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
-        PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
-        PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
-        PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
-        PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
-        PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
-        PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
-        PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
-        PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
-        PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
-                MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MMCD0_0_PU_MARK,
-                    PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_PU_MARK,
-                    PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_PU_MARK,
-                    PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_PU_MARK,
-                    PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_PU_MARK,
-                    PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_5_PU_MARK,
-                    PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_6_PU_MARK,
-                    PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_7_PU_MARK,
-                    PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
-        PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
-        PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
-        PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
-        PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        GPIO_PORT_ALL(),
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(VBUS_0),
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(SCIFA7_RXD),
-        GPIO_FN(SCIFA7_CTS_),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(SCIFA0_SCK), \
-        GPIO_FN(FSICOSLDT3), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(SCIFA0_TXD),
-        GPIO_FN(SCIFA7_TXD),
-        GPIO_FN(SCIFA7_RTS_), \
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(PORT27_I2C_SCL2), \
-        GPIO_FN(PORT27_I2C_SCL3), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_I2C_SDA2), \
-        GPIO_FN(PORT28_I2C_SDA3), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(SCIFA4_TXD),
-        GPIO_FN(SCIFA4_RXD), \
-        GPIO_FN(XWUP),
-        GPIO_FN(SCIFA4_RTS_),
-        GPIO_FN(SCIFA4_CTS_),
-        GPIO_FN(FSIBOBT), \
-        GPIO_FN(FSIBIBT),
-        GPIO_FN(FSIBOLR), \
-        GPIO_FN(FSIBILR),
-        GPIO_FN(FSIBOSLD),
-        GPIO_FN(FSIBISLD),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(SCIFA0_RTS_), \
-        GPIO_FN(FSICOSLDT2),
-        GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(SCIFA0_CTS_), \
-        GPIO_FN(FSICOSLDT1),
-        GPIO_FN(FSICOBT), \
-        GPIO_FN(FSICIBT), \
-        GPIO_FN(FSIDOBT), \
-        GPIO_FN(FSIDIBT),
-        GPIO_FN(FSICOLR), \
-        GPIO_FN(FSICILR), \
-        GPIO_FN(FSIDOLR), \
-        GPIO_FN(FSIDILR),
-        GPIO_FN(FSICOSLD), \
-        GPIO_FN(PORT47_FSICSPDIF),
-        GPIO_FN(FSICISLD), \
-        GPIO_FN(FSIDISLD),
-        GPIO_FN(FSIACK), \
-        GPIO_FN(PORT49_IRDA_OUT), \
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAOBT), \
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(FSIAIBT),
-        GPIO_FN(FSIAOSLD), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(FSIASPDIF), \
-        GPIO_FN(PORT53_IRDA_IN), \
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(FSIBSPDIF), \
-        GPIO_FN(PORT53_FSICSPDIF),
-        GPIO_FN(FSIBCK), \
-        GPIO_FN(PORT54_IRDA_FIRSEL), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(FSIBOMC), \
-        GPIO_FN(FSICCK), \
-        GPIO_FN(FSICOMC),
-        GPIO_FN(FSIAISLD), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(PORT58_KEYOUT7), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(PORT59_KEYOUT6), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(KEYOUT5),
-        GPIO_FN(A15), \
-        GPIO_FN(KEYOUT4),
-        GPIO_FN(A16), \
-        GPIO_FN(KEYOUT3), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(KEYOUT2), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(KEYOUT1), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(KEYOUT0), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(KEYIN0), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(KEYIN1), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(KEYIN2), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(KEYIN3), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(KEYIN4), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(KEYIN5), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(KEYIN6),
-        GPIO_FN(KEYIN7),
-        GPIO_FN(D0_NAF0),
-        GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),
-        GPIO_FN(D3_NAF3),
-        GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),
-        GPIO_FN(D6_NAF6),
-        GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),
-        GPIO_FN(D9_NAF9),
-        GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),
-        GPIO_FN(D12_NAF12),
-        GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),
-        GPIO_FN(D15_NAF15),
-        GPIO_FN(CS4_),
-        GPIO_FN(CS5A_), \
-        GPIO_FN(PORT91_RDWR),
-        GPIO_FN(CS5B_), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(CS6B_), \
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(CS6A_),
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(RD__FSC),
-        GPIO_FN(WE0__FWE), \
-        GPIO_FN(RDWR_FWE),
-        GPIO_FN(WE1_),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(SCIFA3_CTS_), \
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(SCIFA3_RXD), \
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(SCIFA3_RTS_), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(PORT115_I2C_SCL2), \
-        GPIO_FN(PORT115_I2C_SCL3),
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(PORT116_I2C_SDA2), \
-        GPIO_FN(PORT116_I2C_SDA3),
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(PORT128_LCD2VSYN), \
-        GPIO_FN(VIO2_VD), \
-        GPIO_FN(LCD2D0),
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(PORT129_LCD2HSYN), \
-        GPIO_FN(PORT129_LCD2CS_), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(LCD2D1),
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(LCD2D10),
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_KEYOUT6), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(PORT131_KEYOUT11), \
-        GPIO_FN(LCD2D11),
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_KEYOUT7), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(PORT132_KEYOUT10), \
-        GPIO_FN(LCD2D12),
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(LCD2D13),
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(LCD2D14),
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(LCD2D15),
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(PORT136_KEYOUT8), \
-        GPIO_FN(LCD2D16),
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(PORT137_KEYOUT9), \
-        GPIO_FN(LCD2D17),
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(PORT138_KEYOUT8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(LCD2D6),
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(PORT139_KEYOUT9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(LCD2D7),
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(LCD2D8),
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(LCD2D9),
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(PORT142_KEYOUT10), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(LCD2D2),
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(PORT143_KEYOUT11), \
-        GPIO_FN(PORT143_KEYOUT6), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(LCD2D3),
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(PORT144_KEYOUT7), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(LCD2D4),
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(PORT145_LCD2DISP), \
-        GPIO_FN(PORT145_LCD2RS), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(LCD2D5),
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(LCD2DCK), \
-        GPIO_FN(PORT146_LCD2WR_), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(LCD2D18),
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(LCD2RD_), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(LCD2D19),
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(PORT149_RDWR), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(PORT149_KEYOUT9),
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(SCIFA2_TXD1), \
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(SCIFA2_RXD1), \
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(SCIFA2_RTS1_), \
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(SCIFA2_CTS1_), \
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(SCIFA2_SCK1), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(PORT159_SCIFB_SCK), \
-        GPIO_FN(PORT159_SCIFA5_SCK), \
-        GPIO_FN(NMI),
-        GPIO_FN(PORT160_SCIFB_TXD), \
-        GPIO_FN(PORT160_SCIFA5_TXD),
-        GPIO_FN(PORT161_SCIFB_CTS_), \
-        GPIO_FN(PORT161_SCIFA5_CTS_),
-        GPIO_FN(PORT162_SCIFB_RXD), \
-        GPIO_FN(PORT162_SCIFA5_RXD),
-        GPIO_FN(PORT163_SCIFB_RTS_), \
-        GPIO_FN(PORT163_SCIFA5_RTS_), \
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(LCDD0),
-        GPIO_FN(LCDD1), \
-        GPIO_FN(PORT193_SCIFA5_CTS_), \
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), \
-        GPIO_FN(PORT194_SCIFA5_RTS_), \
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), \
-        GPIO_FN(PORT195_SCIFA5_RXD), \
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), \
-        GPIO_FN(PORT196_SCIFA5_TXD),
-        GPIO_FN(LCDD5), \
-        GPIO_FN(PORT197_SCIFA5_SCK), \
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(LCDD6),
-        GPIO_FN(LCDD7), \
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(LCDD8), \
-        GPIO_FN(D16),
-        GPIO_FN(LCDD9), \
-        GPIO_FN(D17),
-        GPIO_FN(LCDD10), \
-        GPIO_FN(D18),
-        GPIO_FN(LCDD11), \
-        GPIO_FN(D19),
-        GPIO_FN(LCDD12), \
-        GPIO_FN(D20),
-        GPIO_FN(LCDD13), \
-        GPIO_FN(D21),
-        GPIO_FN(LCDD14), \
-        GPIO_FN(D22),
-        GPIO_FN(LCDD15), \
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(LCDD16), \
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(LCDD17), \
-        GPIO_FN(D25),
-        GPIO_FN(LCDD18), \
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(LCDD19), \
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(LCDD20), \
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(LCDD21), \
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(LCDD22), \
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(LCDD23), \
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(LCDDCK), \
-        GPIO_FN(LCDWR_),
-        GPIO_FN(LCDRD_), \
-        GPIO_FN(DACK2), \
-        GPIO_FN(PORT217_LCD2RS), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(PORT217_LCD2DISP),
-        GPIO_FN(LCDHSYN), \
-        GPIO_FN(LCDCS_), \
-        GPIO_FN(LCDCS2_), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(LCDDISP), \
-        GPIO_FN(LCDRS), \
-        GPIO_FN(PORT219_LCD2WR_), \
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(LCD2DCK_2),
-        GPIO_FN(LCDVSYN), \
-        GPIO_FN(LCDVSYN2),
-        GPIO_FN(LCDLCLK), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PORT221_LCD2CS_), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(PORT221_LCD2HSYN),
-        GPIO_FN(LCDDON), \
-        GPIO_FN(LCDDON2), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-        GPIO_FN(PORT222_LCD2VSYN),
-        GPIO_FN(SCIFA1_TXD), \
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(SCIFA1_SCK), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(SCIFA1_RTS_), \
-        GPIO_FN(IDIN),
-        GPIO_FN(SCIFA1_RXD),
-        GPIO_FN(SCIFA1_CTS_), \
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(SCIFA2_TXD2),
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(SCIFA2_CTS2_),
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(SCIFA2_SCK2),
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(SCIFA2_RXD2),
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(SCIFA2_RTS2_), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(LCD2D20),
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(LCD2D21),
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(PORT236_I2C_SDA2),
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(PORT237_I2C_SCL2),
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(LCD2D22),
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(LCD2D23),
-        GPIO_FN(SCIFA6_TXD),
-        GPIO_FN(PORT241_IRDA_OUT), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(PORT242_IRDA_IN), \
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_IRDA_FIRSEL), \
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(PORT244_SCIFA5_CTS_), \
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(PORT244_SCIFB_CTS_), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(PORT245_SCIFA5_RTS_), \
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(PORT245_SCIFB_RTS_), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(PORT246_SCIFA5_RXD), \
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(PORT246_SCIFB_RXD), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(PORT247_SCIFA5_TXD), \
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(PORT247_SCIFB_TXD), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(PORT248_SCIFA5_SCK), \
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(PORT248_SCIFB_SCK), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(PORT248_I2C_SCL3), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(PORT249_I2C_SDA3), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(KEYOUT8),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-        /* Functions with pull-ups */
-        GPIO_FN(KEYIN0_PU),
-        GPIO_FN(KEYIN1_PU),
-        GPIO_FN(KEYIN2_PU),
-        GPIO_FN(KEYIN3_PU),
-        GPIO_FN(KEYIN4_PU),
-        GPIO_FN(KEYIN5_PU),
-        GPIO_FN(KEYIN6_PU),
-        GPIO_FN(KEYIN7_PU),
-        GPIO_FN(SDHICD0_PU),
-        GPIO_FN(SDHID0_0_PU),
-        GPIO_FN(SDHID0_1_PU),
-        GPIO_FN(SDHID0_2_PU),
-        GPIO_FN(SDHID0_3_PU),
-        GPIO_FN(SDHICMD0_PU),
-        GPIO_FN(SDHIWP0_PU),
-        GPIO_FN(SDHID1_0_PU),
-        GPIO_FN(SDHID1_1_PU),
-        GPIO_FN(SDHID1_2_PU),
-        GPIO_FN(SDHID1_3_PU),
-        GPIO_FN(SDHICMD1_PU),
-        GPIO_FN(SDHID2_0_PU),
-        GPIO_FN(SDHID2_1_PU),
-        GPIO_FN(SDHID2_2_PU),
-        GPIO_FN(SDHID2_3_PU),
-        GPIO_FN(SDHICMD2_PU),
-        GPIO_FN(MMCCMD0_PU),
-        GPIO_FN(MMCCMD1_PU),
-        GPIO_FN(MMCD0_0_PU),
-        GPIO_FN(MMCD0_1_PU),
-        GPIO_FN(MMCD0_2_PU),
-        GPIO_FN(MMCD0_3_PU),
-        GPIO_FN(MMCD0_4_PU),
-        GPIO_FN(MMCD0_5_PU),
-        GPIO_FN(MMCD0_6_PU),
-        GPIO_FN(MMCD0_7_PU),
-        GPIO_FN(FSIACK_PU),
-        GPIO_FN(FSIAILR_PU),
-        GPIO_FN(FSIAIBT_PU),
-        GPIO_FN(FSIAISLD_PU),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6051020), /* PORT32CR */
-        PORTCR(33, 0xe6051021), /* PORT33CR */
-        PORTCR(34, 0xe6051022), /* PORT34CR */
-        PORTCR(35, 0xe6051023), /* PORT35CR */
-        PORTCR(36, 0xe6051024), /* PORT36CR */
-        PORTCR(37, 0xe6051025), /* PORT37CR */
-        PORTCR(38, 0xe6051026), /* PORT38CR */
-        PORTCR(39, 0xe6051027), /* PORT39CR */
-        PORTCR(40, 0xe6051028), /* PORT40CR */
-        PORTCR(41, 0xe6051029), /* PORT41CR */
-        PORTCR(42, 0xe605102a), /* PORT42CR */
-        PORTCR(43, 0xe605102b), /* PORT43CR */
-        PORTCR(44, 0xe605102c), /* PORT44CR */
-        PORTCR(45, 0xe605102d), /* PORT45CR */
-        PORTCR(46, 0xe605102e), /* PORT46CR */
-        PORTCR(47, 0xe605102f), /* PORT47CR */
-        PORTCR(48, 0xe6051030), /* PORT48CR */
-        PORTCR(49, 0xe6051031), /* PORT49CR */
-        PORTCR(50, 0xe6051032), /* PORT50CR */
-        PORTCR(51, 0xe6051033), /* PORT51CR */
-        PORTCR(52, 0xe6051034), /* PORT52CR */
-        PORTCR(53, 0xe6051035), /* PORT53CR */
-        PORTCR(54, 0xe6051036), /* PORT54CR */
-        PORTCR(55, 0xe6051037), /* PORT55CR */
-        PORTCR(56, 0xe6051038), /* PORT56CR */
-        PORTCR(57, 0xe6051039), /* PORT57CR */
-        PORTCR(58, 0xe605103a), /* PORT58CR */
-        PORTCR(59, 0xe605103b), /* PORT59CR */
-        PORTCR(60, 0xe605103c), /* PORT60CR */
-        PORTCR(61, 0xe605103d), /* PORT61CR */
-        PORTCR(62, 0xe605103e), /* PORT62CR */
-        PORTCR(63, 0xe605103f), /* PORT63CR */
-        PORTCR(64, 0xe6051040), /* PORT64CR */
-        PORTCR(65, 0xe6051041), /* PORT65CR */
-        PORTCR(66, 0xe6051042), /* PORT66CR */
-        PORTCR(67, 0xe6051043), /* PORT67CR */
-        PORTCR(68, 0xe6051044), /* PORT68CR */
-        PORTCR(69, 0xe6051045), /* PORT69CR */
-        PORTCR(70, 0xe6051046), /* PORT70CR */
-        PORTCR(71, 0xe6051047), /* PORT71CR */
-        PORTCR(72, 0xe6051048), /* PORT72CR */
-        PORTCR(73, 0xe6051049), /* PORT73CR */
-        PORTCR(74, 0xe605104a), /* PORT74CR */
-        PORTCR(75, 0xe605104b), /* PORT75CR */
-        PORTCR(76, 0xe605104c), /* PORT76CR */
-        PORTCR(77, 0xe605104d), /* PORT77CR */
-        PORTCR(78, 0xe605104e), /* PORT78CR */
-        PORTCR(79, 0xe605104f), /* PORT79CR */
-        PORTCR(80, 0xe6051050), /* PORT80CR */
-        PORTCR(81, 0xe6051051), /* PORT81CR */
-        PORTCR(82, 0xe6051052), /* PORT82CR */
-        PORTCR(83, 0xe6051053), /* PORT83CR */
-        PORTCR(84, 0xe6051054), /* PORT84CR */
-        PORTCR(85, 0xe6051055), /* PORT85CR */
-        PORTCR(86, 0xe6051056), /* PORT86CR */
-        PORTCR(87, 0xe6051057), /* PORT87CR */
-        PORTCR(88, 0xe6051058), /* PORT88CR */
-        PORTCR(89, 0xe6051059), /* PORT89CR */
-        PORTCR(90, 0xe605105a), /* PORT90CR */
-        PORTCR(91, 0xe605105b), /* PORT91CR */
-        PORTCR(92, 0xe605105c), /* PORT92CR */
-        PORTCR(93, 0xe605105d), /* PORT93CR */
-        PORTCR(94, 0xe605105e), /* PORT94CR */
-        PORTCR(95, 0xe605105f), /* PORT95CR */
-        PORTCR(96, 0xe6052060), /* PORT96CR */
-        PORTCR(97, 0xe6052061), /* PORT97CR */
-        PORTCR(98, 0xe6052062), /* PORT98CR */
-        PORTCR(99, 0xe6052063), /* PORT99CR */
-        PORTCR(100, 0xe6052064), /* PORT100CR */
-        PORTCR(101, 0xe6052065), /* PORT101CR */
-        PORTCR(102, 0xe6052066), /* PORT102CR */
-        PORTCR(103, 0xe6052067), /* PORT103CR */
-        PORTCR(104, 0xe6052068), /* PORT104CR */
-        PORTCR(105, 0xe6052069), /* PORT105CR */
-        PORTCR(106, 0xe605206a), /* PORT106CR */
-        PORTCR(107, 0xe605206b), /* PORT107CR */
-        PORTCR(108, 0xe605206c), /* PORT108CR */
-        PORTCR(109, 0xe605206d), /* PORT109CR */
-        PORTCR(110, 0xe605206e), /* PORT110CR */
-        PORTCR(111, 0xe605206f), /* PORT111CR */
-        PORTCR(112, 0xe6052070), /* PORT112CR */
-        PORTCR(113, 0xe6052071), /* PORT113CR */
-        PORTCR(114, 0xe6052072), /* PORT114CR */
-        PORTCR(115, 0xe6052073), /* PORT115CR */
-        PORTCR(116, 0xe6052074), /* PORT116CR */
-        PORTCR(117, 0xe6052075), /* PORT117CR */
-        PORTCR(118, 0xe6052076), /* PORT118CR */
-        PORTCR(128, 0xe6052080), /* PORT128CR */
-        PORTCR(129, 0xe6052081), /* PORT129CR */
-        PORTCR(130, 0xe6052082), /* PORT130CR */
-        PORTCR(131, 0xe6052083), /* PORT131CR */
-        PORTCR(132, 0xe6052084), /* PORT132CR */
-        PORTCR(133, 0xe6052085), /* PORT133CR */
-        PORTCR(134, 0xe6052086), /* PORT134CR */
-        PORTCR(135, 0xe6052087), /* PORT135CR */
-        PORTCR(136, 0xe6052088), /* PORT136CR */
-        PORTCR(137, 0xe6052089), /* PORT137CR */
-        PORTCR(138, 0xe605208a), /* PORT138CR */
-        PORTCR(139, 0xe605208b), /* PORT139CR */
-        PORTCR(140, 0xe605208c), /* PORT140CR */
-        PORTCR(141, 0xe605208d), /* PORT141CR */
-        PORTCR(142, 0xe605208e), /* PORT142CR */
-        PORTCR(143, 0xe605208f), /* PORT143CR */
-        PORTCR(144, 0xe6052090), /* PORT144CR */
-        PORTCR(145, 0xe6052091), /* PORT145CR */
-        PORTCR(146, 0xe6052092), /* PORT146CR */
-        PORTCR(147, 0xe6052093), /* PORT147CR */
-        PORTCR(148, 0xe6052094), /* PORT148CR */
-        PORTCR(149, 0xe6052095), /* PORT149CR */
-        PORTCR(150, 0xe6052096), /* PORT150CR */
-        PORTCR(151, 0xe6052097), /* PORT151CR */
-        PORTCR(152, 0xe6052098), /* PORT152CR */
-        PORTCR(153, 0xe6052099), /* PORT153CR */
-        PORTCR(154, 0xe605209a), /* PORT154CR */
-        PORTCR(155, 0xe605209b), /* PORT155CR */
-        PORTCR(156, 0xe605209c), /* PORT156CR */
-        PORTCR(157, 0xe605209d), /* PORT157CR */
-        PORTCR(158, 0xe605209e), /* PORT158CR */
-        PORTCR(159, 0xe605209f), /* PORT159CR */
-        PORTCR(160, 0xe60520a0), /* PORT160CR */
-        PORTCR(161, 0xe60520a1), /* PORT161CR */
-        PORTCR(162, 0xe60520a2), /* PORT162CR */
-        PORTCR(163, 0xe60520a3), /* PORT163CR */
-        PORTCR(164, 0xe60520a4), /* PORT164CR */
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60530e0), /* PORT224CR */
-        PORTCR(225, 0xe60530e1), /* PORT225CR */
-        PORTCR(226, 0xe60530e2), /* PORT226CR */
-        PORTCR(227, 0xe60530e3), /* PORT227CR */
-        PORTCR(228, 0xe60530e4), /* PORT228CR */
-        PORTCR(229, 0xe60530e5), /* PORT229CR */
-        PORTCR(230, 0xe60530e6), /* PORT230CR */
-        PORTCR(231, 0xe60530e7), /* PORT231CR */
-        PORTCR(232, 0xe60530e8), /* PORT232CR */
-        PORTCR(233, 0xe60530e9), /* PORT233CR */
-        PORTCR(234, 0xe60530ea), /* PORT234CR */
-        PORTCR(235, 0xe60530eb), /* PORT235CR */
-        PORTCR(236, 0xe60530ec), /* PORT236CR */
-        PORTCR(237, 0xe60530ed), /* PORT237CR */
-        PORTCR(238, 0xe60530ee), /* PORT238CR */
-        PORTCR(239, 0xe60530ef), /* PORT239CR */
-        PORTCR(240, 0xe60530f0), /* PORT240CR */
-        PORTCR(241, 0xe60530f1), /* PORT241CR */
-        PORTCR(242, 0xe60530f2), /* PORT242CR */
-        PORTCR(243, 0xe60530f3), /* PORT243CR */
-        PORTCR(244, 0xe60530f4), /* PORT244CR */
-        PORTCR(245, 0xe60530f5), /* PORT245CR */
-        PORTCR(246, 0xe60530f6), /* PORT246CR */
-        PORTCR(247, 0xe60530f7), /* PORT247CR */
-        PORTCR(248, 0xe60530f8), /* PORT248CR */
-        PORTCR(249, 0xe60530f9), /* PORT249CR */
-        PORTCR(250, 0xe60530fa), /* PORT250CR */
-        PORTCR(251, 0xe60530fb), /* PORT251CR */
-        PORTCR(252, 0xe60530fc), /* PORT252CR */
-        PORTCR(253, 0xe60530fd), /* PORT253CR */
-        PORTCR(254, 0xe60530fe), /* PORT254CR */
-        PORTCR(255, 0xe60530ff), /* PORT255CR */
-        PORTCR(256, 0xe6053100), /* PORT256CR */
-        PORTCR(257, 0xe6053101), /* PORT257CR */
-        PORTCR(258, 0xe6053102), /* PORT258CR */
-        PORTCR(259, 0xe6053103), /* PORT259CR */
-        PORTCR(260, 0xe6053104), /* PORT260CR */
-        PORTCR(261, 0xe6053105), /* PORT261CR */
-        PORTCR(262, 0xe6053106), /* PORT262CR */
-        PORTCR(263, 0xe6053107), /* PORT263CR */
-        PORTCR(264, 0xe6053108), /* PORT264CR */
-        PORTCR(265, 0xe6053109), /* PORT265CR */
-        PORTCR(266, 0xe605310a), /* PORT266CR */
-        PORTCR(267, 0xe605310b), /* PORT267CR */
-        PORTCR(268, 0xe605310c), /* PORT268CR */
-        PORTCR(269, 0xe605310d), /* PORT269CR */
-        PORTCR(270, 0xe605310e), /* PORT270CR */
-        PORTCR(271, 0xe605310f), /* PORT271CR */
-        PORTCR(272, 0xe6053110), /* PORT272CR */
-        PORTCR(273, 0xe6053111), /* PORT273CR */
-        PORTCR(274, 0xe6053112), /* PORT274CR */
-        PORTCR(275, 0xe6053113), /* PORT275CR */
-        PORTCR(276, 0xe6053114), /* PORT276CR */
-        PORTCR(277, 0xe6053115), /* PORT277CR */
-        PORTCR(278, 0xe6053116), /* PORT278CR */
-        PORTCR(279, 0xe6053117), /* PORT279CR */
-        PORTCR(280, 0xe6053118), /* PORT280CR */
-        PORTCR(281, 0xe6053119), /* PORT281CR */
-        PORTCR(282, 0xe605311a), /* PORT282CR */
-        PORTCR(288, 0xe6052120), /* PORT288CR */
-        PORTCR(289, 0xe6052121), /* PORT289CR */
-        PORTCR(290, 0xe6052122), /* PORT290CR */
-        PORTCR(291, 0xe6052123), /* PORT291CR */
-        PORTCR(292, 0xe6052124), /* PORT292CR */
-        PORTCR(293, 0xe6052125), /* PORT293CR */
-        PORTCR(294, 0xe6052126), /* PORT294CR */
-        PORTCR(295, 0xe6052127), /* PORT295CR */
-        PORTCR(296, 0xe6052128), /* PORT296CR */
-        PORTCR(297, 0xe6052129), /* PORT297CR */
-        PORTCR(298, 0xe605212a), /* PORT298CR */
-        PORTCR(299, 0xe605212b), /* PORT299CR */
-        PORTCR(300, 0xe605212c), /* PORT300CR */
-        PORTCR(301, 0xe605212d), /* PORT301CR */
-        PORTCR(302, 0xe605212e), /* PORT302CR */
-        PORTCR(303, 0xe605212f), /* PORT303CR */
-        PORTCR(304, 0xe6052130), /* PORT304CR */
-        PORTCR(305, 0xe6052131), /* PORT305CR */
-        PORTCR(306, 0xe6052132), /* PORT306CR */
-        PORTCR(307, 0xe6052133), /* PORT307CR */
-        PORTCR(308, 0xe6052134), /* PORT308CR */
-        PORTCR(309, 0xe6052135), /* PORT309CR */
-        { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-                        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-                        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-                        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-                        0, 0,
-                        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-                        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-                        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-                        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-                        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-                        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-                        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-                        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-                        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-                        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-                        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-                        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-                        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-                        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-                        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-                        0, 0,
-                        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-                        0, 0,
-                        0, 0,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-                        0, 0,
-                        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-                        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-                        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-                        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-                        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-                        0, 0,
-                        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-                        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-                        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-                        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-                        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-                        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-                        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-                        0, 0,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
-                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
-                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
-                        0, 0, 0, 0,
-                        0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
-                        PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
-                        PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
-                        PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-                        PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, PORT309_DATA, PORT308_DATA,
-                        PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
-                        PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
-                        PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
-                        PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
-                        PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
-        },
-        { },
-};
-/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
-#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
-#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
-};
-static struct pinmux_info sh73a0_pinmux_info = {
-        .name = "sh73a0_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_FSIAISLD_PU,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq = pinmux_irqs,
-        .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
-void sh73a0_pinmux_init(void)
-{
-        register_pinmux(&sh73a0_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 847567d55487..30ac79c7c687 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -67,6 +67,32 @@ void __init r8a7740_map_io(void)
        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
 }
+/* PFC */
+static struct resource r8a7740_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605800c,
+                .end    = 0xe605802b,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device r8a7740_pfc_device = {
+        .name           = "pfc-r8a7740",
+        .id             = -1,
+        .resource       = r8a7740_pfc_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+};
+void __init r8a7740_pinmux_init(void)
+{
+        platform_device_register(&r8a7740_pfc_device);
+}
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 7e87ab3eb8d3..c54ff9b29fe5 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -60,6 +60,31 @@ void __init r8a7779_map_io(void)
        iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
 }
+static struct resource r8a7779_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffc0000,
+                .end    = 0xfffc023b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffc40000,
+                .end    = 0xffc46fff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device r8a7779_pfc_device = {
+        .name           = "pfc-r8a7779",
+        .id             = -1,
+        .resource       = r8a7779_pfc_resources,
+        .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
+};
+void __init r8a7779_pinmux_init(void)
+{
+        platform_device_register(&r8a7779_pfc_device);
+}
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xffe40000,
        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 191ae72e21ba..d2079d5e3334 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -60,6 +60,32 @@ void __init sh7372_map_io(void)
        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
 }
+/* PFC */
+static struct resource sh7372_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605800c,
+                .end    = 0xe6058027,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device sh7372_pfc_device = {
+        .name           = "pfc-sh7372",
+        .id             = -1,
+        .resource       = sh7372_pfc_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
+};
+void __init sh7372_pinmux_init(void)
+{
+        platform_device_register(&sh7372_pfc_device);
+}
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index f7ecb0bc1bec..2ecd6681692f 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -58,6 +58,31 @@ void __init sh73a0_map_io(void)
        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
+static struct resource sh73a0_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605801c,
+                .end    = 0xe6058027,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device sh73a0_pfc_device = {
+        .name           = "pfc-sh73a0",
+        .id             = -1,
+        .resource       = sh73a0_pfc_resources,
+        .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
+};
+void __init sh73a0_pinmux_init(void)
+{
+        platform_device_register(&sh73a0_pfc_device);
+}
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
        .flags          = UPF_BOOT_AUTOCONF,
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3fdd0085e306..8709a39bd34c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -7,3 +7,4 @@ config ARCH_SUNXI
        select PINCTRL
        select SPARSE_IRQ
        select SUNXI_TIMER
+        select PINCTRL_SUNXI
+\ No newline at end of file
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index fb8fbcecb17f..23afb732cb40 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -27,7 +27,10 @@
 #include "sunxi.h"
 #define WATCHDOG_CTRL_REG       0x00
+#define WATCHDOG_CTRL_RESTART           (1 << 0)
 #define WATCHDOG_MODE_REG       0x04
+#define WATCHDOG_MODE_ENABLE            (1 << 0)
+#define WATCHDOG_MODE_RESET_ENABLE      (1 << 1)
 static void __iomem *wdt_base;
@@ -48,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd)
                return;
        /* Enable timer and set reset bit in the watchdog */
-        writel(3, wdt_base + WATCHDOG_MODE_REG);
+        writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-        writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
+                wdt_base + WATCHDOG_MODE_REG);
-        while(1) {
+        /*
+         * Restart the watchdog. The default (and lowest) interval
+         * value for the watchdog is 0.5s.
+         */
+        writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
+        while (1) {
                mdelay(5);
-                writel(3, wdt_base + WATCHDOG_MODE_REG);
+                writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
+                        wdt_base + WATCHDOG_MODE_REG);
        }
 }
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ebffed67e2f5..e3d6e15ff188 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -225,8 +225,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
        /* FIXME: what's the actual transition time? */
        policy->cpuinfo.transition_latency = 300 * 1000;
-        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+        cpumask_copy(policy->cpus, cpu_possible_mask);
-        cpumask_copy(policy->related_cpus, cpu_possible_mask);
        if (policy->cpu == 0)
                register_pm_notifier(&tegra_cpu_pm_notifier);
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 485003f9b636..08386418196f 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -172,8 +172,4 @@ static inline void arch_decomp_setup(void)
        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
 }
-static inline void arch_decomp_wdog(void)
-{
-}
 #endif
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index e18aa2f83ebf..ce7ce42a1ac9 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -312,11 +312,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
                return -ENOMEM;
        }
-        emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
+        emc_regbase = devm_ioremap_resource(&pdev->dev, res);
-        if (!emc_regbase) {
+        if (IS_ERR(emc_regbase))
-                dev_err(&pdev->dev, "failed to remap registers\n");
+                return PTR_ERR(emc_regbase);
-                return -ENOMEM;
-        }
        pdata = pdev->dev.platform_data;
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 12060ae4e8f1..a683d17b2ce4 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -31,6 +31,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
 #include <linux/platform_data/pinctrl-coh901.h>
+#include <linux/platform_data/dma-coh901318.h>
 #include <linux/irqchip/arm-vic.h>
 #include <asm/types.h>
@@ -40,7 +41,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include <mach/irqs.h>
@@ -49,7 +49,6 @@
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
-#include "dma_channels.h"
 /*
 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -327,1089 +326,6 @@ static struct resource dma_resource[] = {
        }
 };
-/* points out all dma slave channels.
- * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
- * Select all channels from A to B, end of list is marked with -1,-1
- */
-static int dma_slave_channels[] = {
-        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
-        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
-/* points out all dma memcpy channels. */
-static int dma_memcpy_channels[] = {
-        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-/** register dma for memory access
- *
- * active  1 means dma intends to access memory
- *         0 means dma wont access memory
- */
-static void coh901318_access_memory_state(struct device *dev, bool active)
-{
-}
-#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
-                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
-                        COH901318_CX_CFG_LCR_DISABLE | \
-                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
-                        COH901318_CX_CFG_BE_IRQ_ENABLE)
-#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
-        {
-                .number = U300_DMA_MSL_TX_0,
-                .name = "MSL TX 0",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_TX_1,
-                .name = "MSL TX 1",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_2,
-                .name = "MSL TX 2",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .desc_nbr_max = 10,
-        },
-        {
-                .number = U300_DMA_MSL_TX_3,
-                .name = "MSL TX 3",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_4,
-                .name = "MSL TX 4",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_5,
-                .name = "MSL TX 5",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_TX_6,
-                .name = "MSL TX 6",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_RX_0,
-                .name = "MSL RX 0",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
-        },
-        {
-                .number = U300_DMA_MSL_RX_1,
-                .name = "MSL RX 1",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_2,
-                .name = "MSL RX 2",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_3,
-                .name = "MSL RX 3",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_4,
-                .name = "MSL RX 4",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_5,
-                .name = "MSL RX 5",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_6,
-                .name = "MSL RX 6",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_MMCSD_RX_TX,
-                .name = "MMCSD RX TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_MSPRO_TX,
-                .name = "MSPRO TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_MSPRO_RX,
-                .name = "MSPRO RX",
-                .priority_high = 0,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_UART0_TX,
-                .name = "UART0 TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_UART0_RX,
-                .name = "UART0 RX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_APEX_TX,
-                .name = "APEX TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_APEX_RX,
-                .name = "APEX RX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_PCM_I2S0_TX,
-                .name = "PCM I2S0 TX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_PCM_I2S0_RX,
-                .name = "PCM I2S0 RX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_PCM_I2S1_TX,
-                .name = "PCM I2S1 TX",
-                .priority_high = 1,
-                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_PCM_I2S1_RX,
-                .name = "PCM I2S1 RX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_XGAM_CDI,
-                .name = "XGAM CDI",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_XGAM_PDI,
-                .name = "XGAM PDI",
-                .priority_high = 0,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_SPI_TX,
-                .name = "SPI TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_SPI_RX,
-                .name = "SPI RX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_0,
-                .name = "GENERAL 00",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_1,
-                .name = "GENERAL 01",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_2,
-                .name = "GENERAL 02",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_3,
-                .name = "GENERAL 03",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_4,
-                .name = "GENERAL 04",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_5,
-                .name = "GENERAL 05",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_6,
-                .name = "GENERAL 06",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_7,
-                .name = "GENERAL 07",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_8,
-                .name = "GENERAL 08",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_UART1_TX,
-                .name = "UART1 TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_UART1_RX,
-                .name = "UART1 RX",
-                .priority_high = 0,
-        }
-};
-static struct coh901318_platform coh901318_platform = {
-        .chans_slave = dma_slave_channels,
-        .chans_memcpy = dma_memcpy_channels,
-        .access_memory_state = coh901318_access_memory_state,
-        .chan_conf = chan_config,
-        .max_channels = U300_DMA_CHANNELS,
-};
 static struct resource pinctrl_resources[] = {
        {
@@ -1521,7 +437,6 @@ static struct platform_device dma_device = {
        .resource       = dma_resource,
        .num_resources  = ARRAY_SIZE(dma_resource),
        .dev = {
-                .platform_data = &coh901318_platform,
                .coherent_dma_mask = ~0,
        },
 };
diff --git a/arch/arm/mach-u300/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
deleted file mode 100644
index 4e8a88fbca49..000000000000
--- a/arch/arm/mach-u300/dma_channels.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/dma_channels.h
- *
- *
- * Copyright (C) 2007-2012 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * Map file for the U300 dma driver.
- * Author: Per Friden <per.friden@stericsson.com>
- */
-#ifndef DMA_CHANNELS_H
-#define DMA_CHANNELS_H
-#define U300_DMA_MSL_TX_0             0
-#define U300_DMA_MSL_TX_1             1
-#define U300_DMA_MSL_TX_2             2
-#define U300_DMA_MSL_TX_3             3
-#define U300_DMA_MSL_TX_4             4
-#define U300_DMA_MSL_TX_5             5
-#define U300_DMA_MSL_TX_6             6
-#define U300_DMA_MSL_RX_0             7
-#define U300_DMA_MSL_RX_1             8
-#define U300_DMA_MSL_RX_2             9
-#define U300_DMA_MSL_RX_3             10
-#define U300_DMA_MSL_RX_4             11
-#define U300_DMA_MSL_RX_5             12
-#define U300_DMA_MSL_RX_6             13
-#define U300_DMA_MMCSD_RX_TX          14
-#define U300_DMA_MSPRO_TX             15
-#define U300_DMA_MSPRO_RX             16
-#define U300_DMA_UART0_TX             17
-#define U300_DMA_UART0_RX             18
-#define U300_DMA_APEX_TX              19
-#define U300_DMA_APEX_RX              20
-#define U300_DMA_PCM_I2S0_TX          21
-#define U300_DMA_PCM_I2S0_RX          22
-#define U300_DMA_PCM_I2S1_TX          23
-#define U300_DMA_PCM_I2S1_RX          24
-#define U300_DMA_XGAM_CDI             25
-#define U300_DMA_XGAM_PDI             26
-#define U300_DMA_SPI_TX               27
-#define U300_DMA_SPI_RX               28
-#define U300_DMA_GENERAL_PURPOSE_0    29
-#define U300_DMA_GENERAL_PURPOSE_1    30
-#define U300_DMA_GENERAL_PURPOSE_2    31
-#define U300_DMA_GENERAL_PURPOSE_3    32
-#define U300_DMA_GENERAL_PURPOSE_4    33
-#define U300_DMA_GENERAL_PURPOSE_5    34
-#define U300_DMA_GENERAL_PURPOSE_6    35
-#define U300_DMA_GENERAL_PURPOSE_7    36
-#define U300_DMA_GENERAL_PURPOSE_8    37
-#define U300_DMA_UART1_TX             38
-#define U300_DMA_UART1_RX             39
-#define U300_DMA_DEVICE_CHANNELS      32
-#define U300_DMA_CHANNELS             40
-#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
deleted file mode 100644
index 7c3b2b2d25b6..000000000000
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- *
- * include/linux/coh901318.h
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * DMA driver for COH 901 318
- * Author: Per Friden <per.friden@stericsson.com>
- */
-#ifndef COH901318_H
-#define COH901318_H
-#include <linux/device.h>
-#include <linux/dmaengine.h>
-#define MAX_DMA_PACKET_SIZE_SHIFT 11
-#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
-/**
- * struct coh901318_lli - linked list item for DMAC
- * @control: control settings for DMAC
- * @src_addr: transfer source address
- * @dst_addr: transfer destination address
- * @link_addr:  physical address to next lli
- * @virt_link_addr: virtual address of next lli (only used by pool_free)
- * @phy_this: physical address of current lli (only used by pool_free)
- */
-struct coh901318_lli {
-        u32 control;
-        dma_addr_t src_addr;
-        dma_addr_t dst_addr;
-        dma_addr_t link_addr;
-        void *virt_link_addr;
-        dma_addr_t phy_this;
-};
-/**
- * struct coh901318_params - parameters for DMAC configuration
- * @config: DMA config register
- * @ctrl_lli_last: DMA control register for the last lli in the list
- * @ctrl_lli: DMA control register for an lli
- * @ctrl_lli_chained: DMA control register for a chained lli
- */
-struct coh901318_params {
-        u32 config;
-        u32 ctrl_lli_last;
-        u32 ctrl_lli;
-        u32 ctrl_lli_chained;
-};
-/**
- * struct coh_dma_channel - dma channel base
- * @name: ascii name of dma channel
- * @number: channel id number
- * @desc_nbr_max: number of preallocated descriptors
- * @priority_high: prio of channel, 0 low otherwise high.
- * @param: configuration parameters
- * @dev_addr: physical address of periphal connected to channel
- */
-struct coh_dma_channel {
-        const char name[32];
-        const int number;
-        const int desc_nbr_max;
-        const int priority_high;
-        const struct coh901318_params param;
-        const dma_addr_t dev_addr;
-};
-/**
- * dma_access_memory_state_t - register dma for memory access
- *
- * @dev: The dma device
- * @active:  1 means dma intends to access memory
- *           0 means dma wont access memory
- */
-typedef void (*dma_access_memory_state_t)(struct device *dev,
-                                          bool active);
-/**
- * struct powersave - DMA power save structure
- * @lock: lock protecting data in this struct
- * @started_channels: bit mask indicating active dma channels
- */
-struct powersave {
-        spinlock_t lock;
-        u64 started_channels;
-};
-/**
- * struct coh901318_platform - platform arch structure
- * @chans_slave: specifying dma slave channels
- * @chans_memcpy: specifying dma memcpy channels
- * @access_memory_state: requesting DMA memory access (on / off)
- * @chan_conf: dma channel configurations
- * @max_channels: max number of dma chanenls
- */
-struct coh901318_platform {
-        const int *chans_slave;
-        const int *chans_memcpy;
-        const dma_access_memory_state_t access_memory_state;
-        const struct coh_dma_channel *chan_conf;
-        const int max_channels;
-};
-#ifdef CONFIG_COH901318
-/**
- * coh901318_filter_id() - DMA channel filter function
- * @chan: dma channel handle
- * @chan_id: id of dma channel to be filter out
- *
- * In dma_request_channel() it specifies what channel id to be requested
- */
-bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
-#else
-static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
-{
-        return false;
-}
-#endif
-/*
- * DMA Controller - this access the static mappings of the coh901318 dma.
- *
- */
-#define COH901318_MOD32_MASK                                    (0x1F)
-#define COH901318_WORD_MASK                                     (0xFFFFFFFF)
-/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
-#define COH901318_INT_STATUS1                                   (0x0000)
-#define COH901318_INT_STATUS2                                   (0x0004)
-/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_TC_INT_STATUS1                                (0x0008)
-#define COH901318_TC_INT_STATUS2                                (0x000C)
-/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
-#define COH901318_TC_INT_CLEAR1                                 (0x0010)
-#define COH901318_TC_INT_CLEAR2                                 (0x0014)
-/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_RAW_TC_INT_STATUS1                            (0x0018)
-#define COH901318_RAW_TC_INT_STATUS2                            (0x001C)
-/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
-#define COH901318_BE_INT_STATUS1                                (0x0020)
-#define COH901318_BE_INT_STATUS2                                (0x0024)
-/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
-#define COH901318_BE_INT_CLEAR1                                 (0x0028)
-#define COH901318_BE_INT_CLEAR2                                 (0x002C)
-/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_RAW_BE_INT_STATUS1                            (0x0030)
-#define COH901318_RAW_BE_INT_STATUS2                            (0x0034)
-/*
- * CX_CFG - Channel Configuration Registers 32bit (R/W)
- */
-#define COH901318_CX_CFG                                        (0x0100)
-#define COH901318_CX_CFG_SPACING                                (0x04)
-/* Channel enable activates tha dma job */
-#define COH901318_CX_CFG_CH_ENABLE                              (0x00000001)
-#define COH901318_CX_CFG_CH_DISABLE                             (0x00000000)
-/* Request Mode */
-#define COH901318_CX_CFG_RM_MASK                                (0x00000006)
-#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY                    (0x0 << 1)
-#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY                   (0x1 << 1)
-#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY                   (0x1 << 1)
-#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY                (0x3 << 1)
-#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY                (0x3 << 1)
-/* Linked channel request field. RM must == 11 */
-#define COH901318_CX_CFG_LCRF_SHIFT                             3
-#define COH901318_CX_CFG_LCRF_MASK                              (0x000001F8)
-#define COH901318_CX_CFG_LCR_DISABLE                            (0x00000000)
-/* Terminal Counter Interrupt Request Mask */
-#define COH901318_CX_CFG_TC_IRQ_ENABLE                          (0x00000200)
-#define COH901318_CX_CFG_TC_IRQ_DISABLE                         (0x00000000)
-/* Bus Error interrupt Mask */
-#define COH901318_CX_CFG_BE_IRQ_ENABLE                          (0x00000400)
-#define COH901318_CX_CFG_BE_IRQ_DISABLE                         (0x00000000)
-/*
- * CX_STAT - Channel Status Registers 32bit (R/-)
- */
-#define COH901318_CX_STAT                                       (0x0200)
-#define COH901318_CX_STAT_SPACING                               (0x04)
-#define COH901318_CX_STAT_RBE_IRQ_IND                           (0x00000008)
-#define COH901318_CX_STAT_RTC_IRQ_IND                           (0x00000004)
-#define COH901318_CX_STAT_ACTIVE                                (0x00000002)
-#define COH901318_CX_STAT_ENABLED                               (0x00000001)
-/*
- * CX_CTRL - Channel Control Registers 32bit (R/W)
- */
-#define COH901318_CX_CTRL                                       (0x0400)
-#define COH901318_CX_CTRL_SPACING                               (0x10)
-/* Transfer Count Enable */
-#define COH901318_CX_CTRL_TC_ENABLE                             (0x00001000)
-#define COH901318_CX_CTRL_TC_DISABLE                            (0x00000000)
-/* Transfer Count Value 0 - 4095 */
-#define COH901318_CX_CTRL_TC_VALUE_MASK                         (0x00000FFF)
-/* Burst count */
-#define COH901318_CX_CTRL_BURST_COUNT_MASK                      (0x0000E000)
-#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES                  (0x7 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES                  (0x6 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES                  (0x5 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES                  (0x4 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES                   (0x3 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES                   (0x2 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES                   (0x1 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE                    (0x0 << 13)
-/* Source bus size  */
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK                     (0x00030000)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS                  (0x2 << 16)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS                  (0x1 << 16)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS                   (0x0 << 16)
-/* Source address increment */
-#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE                   (0x00040000)
-#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE                  (0x00000000)
-/* Destination Bus Size */
-#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK                     (0x00180000)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS                  (0x2 << 19)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS                  (0x1 << 19)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS                   (0x0 << 19)
-/* Destination address increment */
-#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE                   (0x00200000)
-#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE                  (0x00000000)
-/* Master Mode (Master2 is only connected to MSL) */
-#define COH901318_CX_CTRL_MASTER_MODE_MASK                      (0x00C00000)
-#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W                   (0x3 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W                   (0x2 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M2RW                      (0x1 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M1RW                      (0x0 << 22)
-/* Terminal Count flag to PER enable */
-#define COH901318_CX_CTRL_TCP_ENABLE                            (0x01000000)
-#define COH901318_CX_CTRL_TCP_DISABLE                           (0x00000000)
-/* Terminal Count flags to CPU enable */
-#define COH901318_CX_CTRL_TC_IRQ_ENABLE                         (0x02000000)
-#define COH901318_CX_CTRL_TC_IRQ_DISABLE                        (0x00000000)
-/* Hand shake to peripheral */
-#define COH901318_CX_CTRL_HSP_ENABLE                            (0x04000000)
-#define COH901318_CX_CTRL_HSP_DISABLE                           (0x00000000)
-#define COH901318_CX_CTRL_HSS_ENABLE                            (0x08000000)
-#define COH901318_CX_CTRL_HSS_DISABLE                           (0x00000000)
-/* DMA mode */
-#define COH901318_CX_CTRL_DDMA_MASK                             (0x30000000)
-#define COH901318_CX_CTRL_DDMA_LEGACY                           (0x0 << 28)
-#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1                      (0x1 << 28)
-#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2                      (0x2 << 28)
-/* Primary Request Data Destination */
-#define COH901318_CX_CTRL_PRDD_MASK                             (0x40000000)
-#define COH901318_CX_CTRL_PRDD_DEST                             (0x1 << 30)
-#define COH901318_CX_CTRL_PRDD_SOURCE                           (0x0 << 30)
-/*
- * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
- */
-#define COH901318_CX_SRC_ADDR                                   (0x0404)
-#define COH901318_CX_SRC_ADDR_SPACING                           (0x10)
-/*
- * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
- */
-#define COH901318_CX_DST_ADDR                                   (0x0408)
-#define COH901318_CX_DST_ADDR_SPACING                           (0x10)
-/*
- * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
- */
-#define COH901318_CX_LNK_ADDR                                   (0x040C)
-#define COH901318_CX_LNK_ADDR_SPACING                           (0x10)
-#define COH901318_CX_LNK_LINK_IMMEDIATE                         (0x00000001)
-#endif /* COH901318_H */
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
index 29acb718acf7..783e7e60101b 100644
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ b/arch/arm/mach-u300/include/mach/uncompress.h
@@ -43,4 +43,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 02e6659286d5..910698293d64 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -10,9 +10,8 @@
 #include <linux/amba/bus.h>
 #include <linux/spi/spi.h>
 #include <linux/amba/pl022.h>
+#include <linux/platform_data/dma-coh901318.h>
 #include <linux/err.h>
-#include <mach/coh901318.h>
-#include "dma_channels.h"
 /*
 * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5dea90636d94..3e5bbd0e5b23 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
        select COMMON_CLK
        select PINCTRL
        select PINCTRL_NOMADIK
+        select PINCTRL_ABX500
        select PL310_ERRATA_753970 if CACHE_PL310
 config UX500_SOC_DB8500
@@ -18,6 +19,11 @@ config UX500_SOC_DB8500
        select CPU_FREQ_TABLE if CPU_FREQ
        select MFD_DB8500_PRCMU
        select PINCTRL_DB8500
+        select PINCTRL_DB8540
+        select PINCTRL_AB8500
+        select PINCTRL_AB8505
+        select PINCTRL_AB9540
+        select PINCTRL_AB8540
        select REGULATOR
        select REGULATOR_DB8500_PRCMU
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 1f47d962e3a1..7037d3687e9f 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -13,6 +13,7 @@
 #include <mach/hardware.h>
 #include "board-mop500.h"
+#include "id.h"
 enum mop500_uib {
        STUIB,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0e928d281759..3868aa4ff15e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -89,26 +89,8 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
       },
 };
-static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
+static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
-        .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
-        /* config_reg is the initial configuration of ab8500 pins.
-         * The pins can be configured as GPIO or alt functions based
-         * on value present in GpioSel1 to GpioSel6 and AlternatFunction
-         * register. This is the array of 7 configuration settings.
-         * One has to compile time decide these settings. Below is the
-         * explanation of these setting
-         * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
-         * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
-         * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
-         * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
-         * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
-         * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
-         * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
-         * as GPIO then this register selectes the alternate fucntions
-         */
-        .config_reg             = {0x00, 0x1E, 0x80, 0x01,
-                                        0x7A, 0x00, 0x00},
 };
 /* ab8500-codec */
@@ -214,7 +196,7 @@ static struct platform_device snowball_sbnet_dev = {
        },
 };
-static struct ab8500_platform_data ab8500_platdata = {
+struct ab8500_platform_data ab8500_platdata = {
        .irq_base       = MOP500_AB8500_IRQ_BASE,
        .regulator_reg_init = ab8500_regulator_reg_init,
        .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
@@ -650,6 +632,7 @@ static void __init mop500_init_machine(void)
        int i2c0_devs;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
        mop500_pinmaps_init();
@@ -684,6 +667,7 @@ static void __init snowball_init_machine(void)
        struct device *parent = NULL;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        snowball_pinmaps_init();
        parent = u8500_init_devices(&ab8500_platdata);
@@ -709,6 +693,7 @@ static void __init hrefv60_init_machine(void)
        int i2c0_devs;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        /*
         * The HREFv60 board removed a GPIO expander and routed
         * all these GPIO pins to the internal GPIO controller
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 75d5b512a3d5..1c1609da76ce 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -10,7 +10,8 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/hardware.h>
-#include <mach/id.h>
+#include "id.h"
 static void __iomem *l2x0_base;
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 218a6b1ada7e..19235cf7bbe3 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -36,7 +36,9 @@
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
+#include "id.h"
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -136,14 +138,9 @@ static struct platform_device db8500_pmu_device = {
        .dev.platform_data      = &db8500_pmu_platdata,
 };
-static struct platform_device db8500_prcmu_device = {
-        .name                   = "db8500-prcmu",
-};
 static struct platform_device *platform_devs[] __initdata = {
        &u8500_dma40_device,
        &db8500_pmu_device,
-        &db8500_prcmu_device,
 };
 static resource_size_t __initdata db8500_gpio_base[] = {
@@ -283,8 +280,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
+                        &db8500_prcmu_pdata),
        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE,
+        OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
                "pinctrl-db8500", NULL),
        /* Requires clock name and DMA bindings. */
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5dd90d31ffc3..537870d3fea8 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -28,6 +28,7 @@
 #include <mach/devices.h>
 #include "board-mop500.h"
+#include "id.h"
 void __iomem *_PRCMU_BASE;
@@ -67,13 +68,11 @@ void __init ux500_init_irq(void)
         * Init clocks here so that they are available for system timer
         * initialization.
         */
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_u9540())
                db8500_prcmu_early_init();
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_u9540())
                u8500_clk_init();
-        else if (cpu_is_u9540())
-                u9540_clk_init();
        else if (cpu_is_u8540())
                u8540_clk_init();
 }
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index b54884bd2549..ce9149302cc3 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -40,8 +40,10 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev,
                        goto wfi;
                /* decouple the gic from the A9 cores */
-                if (prcmu_gic_decouple())
+                if (prcmu_gic_decouple()) {
+                        spin_unlock(&master_lock);
                        goto out;
+                }
                /* If an error occur, we will have to recouple the gic
                 * manually */
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 318d49020894..f3d9419f75d3 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -13,11 +13,13 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/platform_data/dma-ste-dma40.h>
+#include <linux/mfd/dbx500-prcmu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
+#include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
 static struct resource dma40_resources[] = {
@@ -194,3 +196,45 @@ struct platform_device u8500_ske_keypad_device = {
        .num_resources = ARRAY_SIZE(keypad_resources),
        .resource = keypad_resources,
 };
+struct prcmu_pdata db8500_prcmu_pdata = {
+        .ab_platdata    = &ab8500_platdata,
+        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
+        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
+};
+static struct resource db8500_prcmu_res[] = {
+        {
+                .name  = "prcmu",
+                .start = U8500_PRCMU_BASE,
+                .end   = U8500_PRCMU_BASE + SZ_8K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "prcmu-tcdm",
+                .start = U8500_PRCMU_TCDM_BASE,
+                .end   = U8500_PRCMU_TCDM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "irq",
+                .start = IRQ_DB8500_PRCMU1,
+                .end   = IRQ_DB8500_PRCMU1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "prcmu-tcpm",
+                .start = U8500_PRCMU_TCPM_BASE,
+                .end   = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device db8500_prcmu_device = {
+        .name                   = "db8500-prcmu",
+        .resource               = db8500_prcmu_res,
+        .num_resources          = ARRAY_SIZE(db8500_prcmu_res),
+        .dev = {
+                .platform_data = &db8500_prcmu_pdata,
+        },
+};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index a5e05f6e256f..dbcb35c48f06 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -14,6 +14,11 @@
 struct ske_keypad_platform_data;
 struct pl022_ssp_controller;
+struct platform_device;
+extern struct ab8500_platform_data ab8500_platdata;
+extern struct prcmu_pdata db8500_prcmu_pdata;
+extern struct platform_device db8500_prcmu_device;
 static inline struct platform_device *
 db8500_add_ske_keypad(struct device *parent,
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index d1579920139f..9f951842e1e5 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -17,6 +17,8 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
+#include "id.h"
 struct dbx500_asic_id dbx500_id;
 static unsigned int ux500_read_asicid(phys_addr_t addr)
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/id.h
index 9c42642ab168..bcc58a8cccbc 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/id.h
@@ -61,9 +61,14 @@ static inline bool __attribute_const__ cpu_is_u8540(void)
        return dbx500_partnumber() == 0x8540;
 }
+static inline bool __attribute_const__ cpu_is_u8580(void)
+{
+        return dbx500_partnumber() == 0x8580;
+}
 static inline bool cpu_is_ux540_family(void)
 {
-        return cpu_is_u9540() || cpu_is_u8540();
+        return cpu_is_u9540() || cpu_is_u8540() || cpu_is_u8580();
 }
 /*
@@ -115,6 +120,20 @@ static inline bool cpu_is_u8500v20_or_later(void)
        return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
+/*
+ * 8540 revisions
+ */
+static inline bool __attribute_const__ cpu_is_u8540v10(void)
+{
+        return cpu_is_u8540() && dbx500_revision() == 0xA0;
+}
+static inline bool __attribute_const__ cpu_is_u8580v10(void)
+{
+        return cpu_is_u8580() && dbx500_revision() == 0xA0;
+}
 static inline bool ux500_is_svp(void)
 {
        return false;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 28d16e744bfd..5201ddace503 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -39,7 +39,6 @@
 #ifndef __ASSEMBLY__
-#include <mach/id.h>
 extern void __iomem *_PRCMU_BASE;
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 7d34c52798b5..d526dd8e87d3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -38,15 +38,7 @@
 #define MOP500_STMPE1601_IRQ_END        \
        MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
-/* AB8500 virtual gpio IRQ */
+#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ_END
-#define AB8500_VIR_GPIO_NR_IRQS                 16
-#define MOP500_AB8500_VIR_GPIO_IRQ_BASE         \
-        MOP500_STMPE1601_IRQ_END
-#define MOP500_AB8500_VIR_GPIO_IRQ_END          \
-        (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS)
-#define MOP500_NR_IRQS          MOP500_AB8500_VIR_GPIO_IRQ_END
 #define MOP500_IRQ_END          MOP500_NR_IRQS
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index d60ecd1753f0..36969d52e53a 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -54,6 +54,4 @@ static inline void arch_decomp_setup(void)
        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
 }
-#define arch_decomp_wdog() /* nothing to do here */
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index b8adac93421f..18f7af339dc9 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -21,9 +21,12 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
+#include "id.h"
 /* This is called from headsmp.S to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index aa2a78acb59e..a6af0b8732ba 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -17,6 +17,8 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include "id.h"
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
                              U8500_TWD_BASE, IRQ_LOCALTIMER);
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index 63d8e9f81b99..1dba3688275f 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -25,4 +25,9 @@ config MACH_VERSATILE_DT
          Include support for the ARM(R) Versatile/PB platform,
          using the device tree for discovery
+config MACH_VERSATILE_AUTO
+        def_bool y
+        depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB
+        select MACH_VERSATILE_DT
 endmenu
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index a42b89083eb2..25160aeaa3b7 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -37,6 +37,7 @@
 #include <linux/gfp.h>
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
+#include <linux/bitops.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -65,16 +66,28 @@
 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
+/* These PIC IRQs are valid in each configuration */
+#define PIC_VALID_ALL   BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
+                        BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
+                        BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
+                        BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
+                        BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
+                        BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
+                        BIT(SIC_INT_PCI3)
 #if 1
 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 #define IRQ_AACI        IRQ_VICSOURCE24
 #define IRQ_ETH         IRQ_VICSOURCE25
 #define PIC_MASK        0xFFD00000
+#define PIC_VALID       PIC_VALID_ALL
 #else
 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 #define IRQ_AACI        IRQ_SIC_AACI
 #define IRQ_ETH         IRQ_SIC_ETH
 #define PIC_MASK        0
+#define PIC_VALID       PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
+                        BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
+                        BIT(SIC_INT_ETH)
 #endif
 /* Lookup table for finding a DT node that represents the vic instance */
@@ -102,7 +115,7 @@ void __init versatile_init_irq(void)
                                              VERSATILE_SIC_BASE);
        fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                IRQ_VICSOURCE31, ~PIC_MASK, np);
+                IRQ_VICSOURCE31, PIC_VALID, np);
        /*
         * Interrupts on secondary controller from 0 to 8 are routed to
@@ -114,7 +127,7 @@ void __init versatile_init_irq(void)
        writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 }
-static struct map_desc versatile_io_desc[] __initdata = {
+static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
                .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
diff --git a/arch/arm/mach-versatile/include/mach/uncompress.h b/arch/arm/mach-versatile/include/mach/uncompress.h
index 3dd0048afb34..986e3d303f3c 100644
--- a/arch/arm/mach-versatile/include/mach/uncompress.h
+++ b/arch/arm/mach-versatile/include/mach/uncompress.h
@@ -43,4 +43,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 2f84f4094f13..e92e5e0705bc 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -327,12 +328,12 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        int irq;
        /* slot,  pin,  irq
-         *  24     1     27
+         *  24     1     IRQ_SIC_PCI0
-         *  25     1     28
+         *  25     1     IRQ_SIC_PCI1
-         *  26     1     29
+         *  26     1     IRQ_SIC_PCI2
-         *  27     1     30
+         *  27     1     IRQ_SIC_PCI3
         */
-        irq = 27 + ((slot - 24 + pin - 1) & 3);
+        irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
        return irq;
 }
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index c0b1c604ccf8..e3e94b2fa145 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -3,8 +3,8 @@ config ARCH_VT8500
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
+        select CLKSRC_OF
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select VT8500_TIMER
        help
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 6141868b9a3c..49e80053d828 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -18,9 +18,9 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/clocksource.h>
 #include <linux/io.h>
 #include <linux/pm.h>
-#include <linux/vt8500_timer.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -188,8 +188,8 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
        .dt_compat      = vt8500_dt_compat,
        .map_io         = vt8500_map_io,
        .init_irq       = vt8500_init_irq,
-        .init_time      = vt8500_timer_init,
        .init_machine   = vt8500_init,
+        .init_time      = clocksource_of_init,
        .restart        = vt8500_restart,
        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S
index e286daca6827..0ff612ac95ba 100644
--- a/arch/arm/mach-w90x900/include/mach/entry-macro.S
+++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S
@@ -19,8 +19,8 @@
                mov     \base, #AIC_BA
-                ldr     \irqnr, [ \base, #AIC_IPER]
+                ldr     \irqnr, [\base, #AIC_IPER]
-                ldr     \irqnr, [ \base, #AIC_ISNR]
+                ldr     \irqnr, [\base, #AIC_ISNR]
                cmp     \irqnr, #0
        .endm
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 03130212ace2..4b7c324ff664 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -24,8 +24,6 @@
 #include <mach/map.h>
 #include <linux/serial_reg.h>
-#define arch_decomp_wdog()
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
 static volatile u32 * const uart_base = (u32 *)UART0_PA;
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 6472a69cbfe1..5c8983218183 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -24,6 +24,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
+#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -76,7 +77,7 @@ static void __init xilinx_zynq_timer_init(void)
        xilinx_zynq_clocks_init(slcr);
-        xttcpss_timer_init();
+        xttcps_timer_init();
 }
 /**
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 954b91c13c91..8b4dbbaa01cf 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,6 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
-void __init xttcpss_timer_init(void);
+void __init xttcps_timer_init(void);
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index de3df283da74..f9fbc9c1e7a6 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -15,39 +15,29 @@
 * GNU General Public License for more details.
 */
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/clocksource.h>
 #include <linux/clockchips.h>
-#include <linux/io.h>
-#include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/slab.h>
 #include <linux/clk-provider.h>
 #include "common.h"
 /*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
-#define XTTCPSS_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
+#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPSS_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
+#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPSS_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
+#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPSS_INTR_VAL_OFFSET         0x24 /* Interval Count Reg, RW */
+#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPSS_MATCH_1_OFFSET          0x30 /* Match 1 Value Reg, RW */
+#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPSS_MATCH_2_OFFSET          0x3C /* Match 2 Value Reg, RW */
+#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-#define XTTCPSS_MATCH_3_OFFSET          0x48 /* Match 3 Value Reg, RW */
-#define XTTCPSS_ISR_OFFSET              0x54 /* Interrupt Status Reg, RO */
+#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-#define XTTCPSS_IER_OFFSET              0x60 /* Interrupt Enable Reg, RW */
+/*
-#define XTTCPSS_CNT_CNTRL_DISABLE_MASK  0x1
+ * Setup the timers to use pre-scaling, using a fixed value for now that will
-/* Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
@@ -57,72 +47,73 @@
 #define CNT_CNTRL_RESET         (1<<4)
 /**
- * struct xttcpss_timer - This definition defines local timer structure
+ * struct xttcps_timer - This definition defines local timer structure
 *
 * @base_addr:  Base address of timer
 **/
-struct xttcpss_timer {
+struct xttcps_timer {
        void __iomem    *base_addr;
 };
-struct xttcpss_timer_clocksource {
+struct xttcps_timer_clocksource {
-        struct xttcpss_timer    xttc;
+        struct xttcps_timer     xttc;
        struct clocksource      cs;
 };
-#define to_xttcpss_timer_clksrc(x) \
+#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcpss_timer_clocksource, cs)
+                container_of(x, struct xttcps_timer_clocksource, cs)
-struct xttcpss_timer_clockevent {
+struct xttcps_timer_clockevent {
-        struct xttcpss_timer            xttc;
+        struct xttcps_timer             xttc;
        struct clock_event_device       ce;
        struct clk                      *clk;
 };
-#define to_xttcpss_timer_clkevent(x) \
+#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcpss_timer_clockevent, ce)
+                container_of(x, struct xttcps_timer_clockevent, ce)
 /**
- * xttcpss_set_interval - Set the timer interval value
+ * xttcps_set_interval - Set the timer interval value
 *
 * @timer:      Pointer to the timer instance
 * @cycles:     Timer interval ticks
 **/
-static void xttcpss_set_interval(struct xttcpss_timer *timer,
+static void xttcps_set_interval(struct xttcps_timer *timer,
                                        unsigned long cycles)
 {
        u32 ctrl_reg;
        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-        /* Reset the counter (0x10) so that it starts from 0, one-shot
+        /*
-           mode makes this needed for timing to be right. */
+         * Reset the counter (0x10) so that it starts from 0, one-shot
+         * mode makes this needed for timing to be right.
+         */
        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 }
 /**
- * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcpss_timer instance
+ * @dev_id:     void pointer to the xttcps_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
-static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
 {
-        struct xttcpss_timer_clockevent *xttce = dev_id;
+        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
        /* Acknowledge the interrupt and call event handler */
-        __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-                        timer->base_addr + XTTCPSS_ISR_OFFSET);
        xttce->ce.event_handler(&xttce->ce);
@@ -136,46 +127,46 @@ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
 **/
 static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 {
-        struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
+        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPSS_COUNT_VAL_OFFSET);
+                                XTTCPS_COUNT_VAL_OFFSET);
 }
 /**
- * xttcpss_set_next_event - Sets the time interval for next event
+ * xttcps_set_next_event - Sets the time interval for next event
 *
 * @cycles:     Timer interval ticks
 * @evt:        Address of clock event instance
 *
 * returns: Always 0 - success
 **/
-static int xttcpss_set_next_event(unsigned long cycles,
+static int xttcps_set_next_event(unsigned long cycles,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
-        xttcpss_set_interval(timer, cycles);
+        xttcps_set_interval(timer, cycles);
        return 0;
 }
 /**
- * xttcpss_set_mode - Sets the mode of timer
+ * xttcps_set_mode - Sets the mode of timer
 *
 * @mode:       Mode to be set
 * @evt:        Address of clock event instance
 **/
-static void xttcpss_set_mode(enum clock_event_mode mode,
+static void xttcps_set_mode(enum clock_event_mode mode,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
        u32 ctrl_reg;
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                xttcpss_set_interval(timer,
+                xttcps_set_interval(timer,
                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
                                                       PRESCALE * HZ));
                break;
@@ -183,17 +174,17 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPSS_CNT_CNTRL_OFFSET);
+                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
                break;
        case CLOCK_EVT_MODE_RESUME:
                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPSS_CNT_CNTRL_OFFSET);
+                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
                break;
        }
 }
@@ -201,7 +192,7 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
 static void __init zynq_ttc_setup_clocksource(struct device_node *np,
                                             void __iomem *base)
 {
-        struct xttcpss_timer_clocksource *ttccs;
+        struct xttcps_timer_clocksource *ttccs;
        struct clk *clk;
        int err;
        u32 reg;
@@ -230,11 +221,11 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np,
        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
        if (WARN_ON(err))
@@ -244,7 +235,7 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np,
 static void __init zynq_ttc_setup_clockevent(struct device_node *np,
                                            void __iomem *base)
 {
-        struct xttcpss_timer_clockevent *ttcce;
+        struct xttcps_timer_clockevent *ttcce;
        int err, irq;
        u32 reg;
@@ -272,17 +263,18 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np,
        ttcce->ce.name = np->name;
        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcpss_set_next_event;
+        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcpss_set_mode;
+        ttcce->ce.set_mode = xttcps_set_mode;
        ttcce->ce.rating = 200;
        ttcce->ce.irq = irq;
+        ttcce->ce.cpumask = cpu_possible_mask;
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-        err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
+        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
                          np->name, ttcce);
        if (WARN_ON(err))
                return;
@@ -301,12 +293,12 @@ static const __initconst struct of_device_id zynq_ttc_match[] = {
 };
 /**
- * xttcpss_timer_init - Initialize the timer
+ * xttcps_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
-void __init xttcpss_timer_init(void)
+void __init xttcps_timer_init(void)
 {
        struct device_node *np;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3fd629d5a513..025d17328730 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -629,8 +629,9 @@ config ARM_THUMBEE
          make use of it. Say N for code that can run on CPUs without ThumbEE.
 config ARM_VIRT_EXT
-        bool "Native support for the ARM Virtualization Extensions"
+        bool
-        depends on MMU && CPU_V7
+        depends on MMU
+        default y if CPU_V7
        help
          Enable the kernel to make use of the ARM Virtualization
          Extensions to install hypervisors without run-time firmware
@@ -640,11 +641,6 @@ config ARM_VIRT_EXT
          use of this feature.  Refer to Documentation/arm/Booting for
          details.
-          It is safe to enable this option even if the kernel may not be
-          booted in HYP mode, may not have support for the
-          virtualization extensions, or may be booted with a
-          non-compliant bootloader.
 config SWP_EMULATE
        bool "Emulate SWP/SWPB instructions"
        depends on !CPU_USE_DOMAINS && CPU_V7
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 8a9c4cb50a93..4e333fa2756f 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -6,7 +6,7 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
                                   iomap.o
 obj-$(CONFIG_MMU)               += fault-armv.o flush.o idmap.o ioremap.o \
-                                   mmap.o pgd.o mmu.o vmregion.o
+                                   mmap.o pgd.o mmu.o
 ifneq ($(CONFIG_MMU),y)
 obj-y                           += nommu.o
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index bc4a5e9ebb78..7a0511191f6b 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -34,6 +34,9 @@
 * The ASID is used to tag entries in the CPU caches and TLBs.
 * The context ID is used by debuggers and trace logic, and
 * should be unique within all running processes.
+ *
+ * In big endian operation, the two 32 bit words are swapped if accesed by
+ * non 64-bit operations.
 */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
 #define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 99db769307ec..2dffc010cc41 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -1,4 +1,6 @@
+#include <linux/module.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <asm/cputype.h>
 #include <asm/idmap.h>
@@ -6,6 +8,7 @@
 #include <asm/pgtable.h>
 #include <asm/sections.h>
 #include <asm/system_info.h>
+#include <asm/virt.h>
 pgd_t *idmap_pgd;
@@ -59,11 +62,17 @@ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
        } while (pud++, addr = next, addr != end);
 }
-static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
+static void identity_mapping_add(pgd_t *pgd, const char *text_start,
+                                 const char *text_end, unsigned long prot)
 {
-        unsigned long prot, next;
+        unsigned long addr, end;
+        unsigned long next;
+        addr = virt_to_phys(text_start);
+        end = virt_to_phys(text_end);
+        prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
-        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
                prot |= PMD_BIT4;
@@ -74,28 +83,52 @@ static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long e
        } while (pgd++, addr = next, addr != end);
 }
+#if defined(CONFIG_ARM_VIRT_EXT) && defined(CONFIG_ARM_LPAE)
+pgd_t *hyp_pgd;
+extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+static int __init init_static_idmap_hyp(void)
+{
+        hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        if (!hyp_pgd)
+                return -ENOMEM;
+        pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n",
+                __hyp_idmap_text_start, __hyp_idmap_text_end);
+        identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
+                             __hyp_idmap_text_end, PMD_SECT_AP1);
+        return 0;
+}
+#else
+static int __init init_static_idmap_hyp(void)
+{
+        return 0;
+}
+#endif
 extern char  __idmap_text_start[], __idmap_text_end[];
 static int __init init_static_idmap(void)
 {
-        phys_addr_t idmap_start, idmap_end;
+        int ret;
        idmap_pgd = pgd_alloc(&init_mm);
        if (!idmap_pgd)
                return -ENOMEM;
-        /* Add an identity mapping for the physical address of the section. */
+        pr_info("Setting up static identity map for 0x%p - 0x%p\n",
-        idmap_start = virt_to_phys((void *)__idmap_text_start);
+                __idmap_text_start, __idmap_text_end);
-        idmap_end = virt_to_phys((void *)__idmap_text_end);
+        identity_mapping_add(idmap_pgd, __idmap_text_start,
+                             __idmap_text_end, 0);
-        pr_info("Setting up static identity map for 0x%llx - 0x%llx\n",
+        ret = init_static_idmap_hyp();
-                (long long)idmap_start, (long long)idmap_end);
-        identity_mapping_add(idmap_pgd, idmap_start, idmap_end);
        /* Flush L1 for the hardware to see this page table content */
        flush_cache_louis();
-        return 0;
+        return ret;
 }
 early_initcall(init_static_idmap);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 88fd86cf3d9a..04d9006eab1f 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -39,6 +39,70 @@
 #include <asm/mach/pci.h>
 #include "mm.h"
+LIST_HEAD(static_vmlist);
+static struct static_vm *find_static_vm_paddr(phys_addr_t paddr,
+                        size_t size, unsigned int mtype)
+{
+        struct static_vm *svm;
+        struct vm_struct *vm;
+        list_for_each_entry(svm, &static_vmlist, list) {
+                vm = &svm->vm;
+                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                        continue;
+                if ((vm->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
+                        continue;
+                if (vm->phys_addr > paddr ||
+                        paddr + size - 1 > vm->phys_addr + vm->size - 1)
+                        continue;
+                return svm;
+        }
+        return NULL;
+}
+struct static_vm *find_static_vm_vaddr(void *vaddr)
+{
+        struct static_vm *svm;
+        struct vm_struct *vm;
+        list_for_each_entry(svm, &static_vmlist, list) {
+                vm = &svm->vm;
+                /* static_vmlist is ascending order */
+                if (vm->addr > vaddr)
+                        break;
+                if (vm->addr <= vaddr && vm->addr + vm->size > vaddr)
+                        return svm;
+        }
+        return NULL;
+}
+void __init add_static_vm_early(struct static_vm *svm)
+{
+        struct static_vm *curr_svm;
+        struct vm_struct *vm;
+        void *vaddr;
+        vm = &svm->vm;
+        vm_area_add_early(vm);
+        vaddr = vm->addr;
+        list_for_each_entry(curr_svm, &static_vmlist, list) {
+                vm = &curr_svm->vm;
+                if (vm->addr > vaddr)
+                        break;
+        }
+        list_add_tail(&svm->list, &curr_svm->list);
+}
 int ioremap_page(unsigned long virt, unsigned long phys,
                 const struct mem_type *mtype)
 {
@@ -197,13 +261,14 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        const struct mem_type *type;
        int err;
        unsigned long addr;
-        struct vm_struct * area;
+        struct vm_struct *area;
+        phys_addr_t paddr = __pfn_to_phys(pfn);
 #ifndef CONFIG_ARM_LPAE
        /*
         * High mappings must be supersection aligned
         */
-        if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
+        if (pfn >= 0x100000 && (paddr & ~SUPERSECTION_MASK))
                return NULL;
 #endif
@@ -219,24 +284,16 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        /*
         * Try to reuse one of the static mapping whenever possible.
         */
-        read_lock(&vmlist_lock);
+        if (size && !(sizeof(phys_addr_t) == 4 && pfn >= 0x100000)) {
-        for (area = vmlist; area; area = area->next) {
+                struct static_vm *svm;
-                if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
-                        break;
+                svm = find_static_vm_paddr(paddr, size, mtype);
-                if (!(area->flags & VM_ARM_STATIC_MAPPING))
+                if (svm) {
-                        continue;
+                        addr = (unsigned long)svm->vm.addr;
-                if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
+                        addr += paddr - svm->vm.phys_addr;
-                        continue;
+                        return (void __iomem *) (offset + addr);
-                if (__phys_to_pfn(area->phys_addr) > pfn ||
+                }
-                    __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
-                        continue;
-                /* we can drop the lock here as we know *area is static */
-                read_unlock(&vmlist_lock);
-                addr = (unsigned long)area->addr;
-                addr += __pfn_to_phys(pfn) - area->phys_addr;
-                return (void __iomem *) (offset + addr);
        }
-        read_unlock(&vmlist_lock);
        /*
         * Don't allow RAM to be mapped - this causes problems with ARMv6+
@@ -248,21 +305,21 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        if (!area)
                return NULL;
        addr = (unsigned long)area->addr;
-        area->phys_addr = __pfn_to_phys(pfn);
+        area->phys_addr = paddr;
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
        if (DOMAIN_IO == 0 &&
            (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
               cpu_is_xsc3()) && pfn >= 0x100000 &&
-               !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
+               !((paddr | size | addr) & ~SUPERSECTION_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
                err = remap_area_supersections(addr, pfn, size, type);
-        } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
+        } else if (!((paddr | size | addr) & ~PMD_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
                err = remap_area_sections(addr, pfn, size, type);
        } else
 #endif
-                err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
+                err = ioremap_page_range(addr, addr + size, paddr,
                                         __pgprot(type->prot_pte));
        if (err) {
@@ -346,34 +403,28 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
 void __iounmap(volatile void __iomem *io_addr)
 {
        void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
-        struct vm_struct *vm;
+        struct static_vm *svm;
+        /* If this is a static mapping, we must leave it alone */
+        svm = find_static_vm_vaddr(addr);
+        if (svm)
+                return;
-        read_lock(&vmlist_lock);
-        for (vm = vmlist; vm; vm = vm->next) {
-                if (vm->addr > addr)
-                        break;
-                if (!(vm->flags & VM_IOREMAP))
-                        continue;
-                /* If this is a static mapping we must leave it alone */
-                if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
-                    (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
-                        read_unlock(&vmlist_lock);
-                        return;
-                }
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
+        {
+                struct vm_struct *vm;
+                vm = find_vm_area(addr);
                /*
                 * If this is a section based mapping we need to handle it
                 * specially as the VM subsystem does not know how to handle
                 * such a beast.
                 */
-                if ((vm->addr == addr) &&
+                if (vm && (vm->flags & VM_ARM_SECTION_MAPPING))
-                    (vm->flags & VM_ARM_SECTION_MAPPING)) {
                        unmap_area_sections((unsigned long)vm->addr, vm->size);
-                        break;
-                }
-#endif
        }
-        read_unlock(&vmlist_lock);
+#endif
        vunmap(addr);
 }
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index a8ee92da3544..d5a4e9ad8f0f 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,4 +1,6 @@
 #ifdef CONFIG_MMU
+#include <linux/list.h>
+#include <linux/vmalloc.h>
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
@@ -65,6 +67,16 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 /* consistent regions used by dma_alloc_attrs() */
 #define VM_ARM_DMA_CONSISTENT   0x20000000
+struct static_vm {
+        struct vm_struct vm;
+        struct list_head list;
+};
+extern struct list_head static_vmlist;
+extern struct static_vm *find_static_vm_vaddr(void *vaddr);
+extern __init void add_static_vm_early(struct static_vm *svm);
 #endif
 #ifdef CONFIG_ZONE_DMA
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ce328c7f5c94..e95a996ab78f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -57,6 +57,9 @@ static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
 static unsigned int ecc_mask __initdata = 0;
 pgprot_t pgprot_user;
 pgprot_t pgprot_kernel;
+pgprot_t pgprot_hyp_device;
+pgprot_t pgprot_s2;
+pgprot_t pgprot_s2_device;
 EXPORT_SYMBOL(pgprot_user);
 EXPORT_SYMBOL(pgprot_kernel);
@@ -66,34 +69,46 @@ struct cachepolicy {
        unsigned int    cr_mask;
        pmdval_t        pmd;
        pteval_t        pte;
+        pteval_t        pte_s2;
 };
+#ifdef CONFIG_ARM_LPAE
+#define s2_policy(policy)       policy
+#else
+#define s2_policy(policy)       0
+#endif
 static struct cachepolicy cache_policies[] __initdata = {
        {
                .policy         = "uncached",
                .cr_mask        = CR_W|CR_C,
                .pmd            = PMD_SECT_UNCACHED,
                .pte            = L_PTE_MT_UNCACHED,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
        }, {
                .policy         = "buffered",
                .cr_mask        = CR_C,
                .pmd            = PMD_SECT_BUFFERED,
                .pte            = L_PTE_MT_BUFFERABLE,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
        }, {
                .policy         = "writethrough",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WT,
                .pte            = L_PTE_MT_WRITETHROUGH,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
        }, {
                .policy         = "writeback",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WB,
                .pte            = L_PTE_MT_WRITEBACK,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
        }, {
                .policy         = "writealloc",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WBWA,
                .pte            = L_PTE_MT_WRITEALLOC,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
        }
 };
@@ -310,6 +325,7 @@ static void __init build_mem_type_table(void)
        struct cachepolicy *cp;
        unsigned int cr = get_cr();
        pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
+        pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
        int cpu_arch = cpu_architecture();
        int i;
@@ -421,6 +437,8 @@ static void __init build_mem_type_table(void)
         */
        cp = &cache_policies[cachepolicy];
        vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+        s2_pgprot = cp->pte_s2;
+        hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
        /*
         * ARMv6 and above have extended page tables.
@@ -444,6 +462,7 @@ static void __init build_mem_type_table(void)
                        user_pgprot |= L_PTE_SHARED;
                        kern_pgprot |= L_PTE_SHARED;
                        vecs_pgprot |= L_PTE_SHARED;
+                        s2_pgprot |= L_PTE_SHARED;
                        mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
                        mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
                        mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
@@ -498,6 +517,9 @@ static void __init build_mem_type_table(void)
        pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
        pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
                                 L_PTE_DIRTY | kern_pgprot);
+        pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
+        pgprot_s2_device  = __pgprot(s2_device_pgprot);
+        pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
        mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
        mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
@@ -757,21 +779,24 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 {
        struct map_desc *md;
        struct vm_struct *vm;
+        struct static_vm *svm;
        if (!nr)
                return;
-        vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
+        svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
        for (md = io_desc; nr; md++, nr--) {
                create_mapping(md);
+                vm = &svm->vm;
                vm->addr = (void *)(md->virtual & PAGE_MASK);
                vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
                vm->phys_addr = __pfn_to_phys(md->pfn);
                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
                vm->flags |= VM_ARM_MTYPE(md->type);
                vm->caller = iotable_init;
-                vm_area_add_early(vm++);
+                add_static_vm_early(svm++);
        }
 }
@@ -779,13 +804,16 @@ void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
                                  void *caller)
 {
        struct vm_struct *vm;
+        struct static_vm *svm;
+        svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
-        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+        vm = &svm->vm;
        vm->addr = (void *)addr;
        vm->size = size;
        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
        vm->caller = caller;
-        vm_area_add_early(vm);
+        add_static_vm_early(svm);
 }
 #ifndef CONFIG_ARM_LPAE
@@ -810,14 +838,13 @@ static void __init pmd_empty_section_gap(unsigned long addr)
 static void __init fill_pmd_gaps(void)
 {
+        struct static_vm *svm;
        struct vm_struct *vm;
        unsigned long addr, next = 0;
        pmd_t *pmd;
-        /* we're still single threaded hence no lock needed here */
+        list_for_each_entry(svm, &static_vmlist, list) {
-        for (vm = vmlist; vm; vm = vm->next) {
+                vm = &svm->vm;
-                if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
-                        continue;
                addr = (unsigned long)vm->addr;
                if (addr < next)
                        continue;
@@ -857,19 +884,12 @@ static void __init fill_pmd_gaps(void)
 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 static void __init pci_reserve_io(void)
 {
-        struct vm_struct *vm;
+        struct static_vm *svm;
-        unsigned long addr;
-        /* we're still single threaded hence no lock needed here */
+        svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
-        for (vm = vmlist; vm; vm = vm->next) {
+        if (svm)
-                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                return;
-                        continue;
-                addr = (unsigned long)vm->addr;
-                addr &= ~(SZ_2M - 1);
-                if (addr == PCI_IO_VIRT_BASE)
-                        return;
-        }
        vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 }
 #else
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index eb6aa73bc8b7..f9a0aa725ea9 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -38,9 +38,14 @@
 /*
 * mmid - get context id from mm pointer (mm->context.id)
+ * note, this field is 64bit, so in big-endian the two words are swapped too.
 */
        .macro  mmid, rd, rn
+#ifdef __ARMEB__
+        ldr     \rd, [\rn, #MM_CONTEXT_ID + 4 ]
+#else
        ldr     \rd, [\rn, #MM_CONTEXT_ID]
+#endif
        .endm
 /*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 09c5233f4dfc..bcaaa8de9325 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -101,7 +101,7 @@ ENTRY(cpu_v6_dcache_clean_area)
 ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 6d98c13ab827..78f520bc0e99 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -40,7 +40,7 @@
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 7b56386f9496..50bf1dafc9ea 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -47,7 +47,7 @@
 */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        and     r3, r1, #0xff
        mov     r3, r3, lsl #(48 - 32)          @ ASID
        mcrr    p15, 0, r0, r3, c2              @ set TTB 0
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
deleted file mode 100644
index a631016e1f8f..000000000000
--- a/arch/arm/mm/vmregion.c
+++ /dev/null
@@ -1,205 +0,0 @@
-#include <linux/fs.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-#include "vmregion.h"
-/*
- * VM region handling support.
- *
- * This should become something generic, handling VM region allocations for
- * vmalloc and similar (ioremap, module space, etc).
- *
- * I envisage vmalloc()'s supporting vm_struct becoming:
- *
- *  struct vm_struct {
- *    struct vmregion   region;
- *    unsigned long     flags;
- *    struct page       **pages;
- *    unsigned int      nr_pages;
- *    unsigned long     phys_addr;
- *  };
- *
- * get_vm_area() would then call vmregion_alloc with an appropriate
- * struct vmregion head (eg):
- *
- *  struct vmregion vmalloc_head = {
- *      .vm_list        = LIST_HEAD_INIT(vmalloc_head.vm_list),
- *      .vm_start       = VMALLOC_START,
- *      .vm_end         = VMALLOC_END,
- *  };
- *
- * However, vmalloc_head.vm_start is variable (typically, it is dependent on
- * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
- * would have to initialise this each time prior to calling vmregion_alloc().
- */
-struct arm_vmregion *
-arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
-                   size_t size, gfp_t gfp, const void *caller)
-{
-        unsigned long start = head->vm_start, addr = head->vm_end;
-        unsigned long flags;
-        struct arm_vmregion *c, *new;
-        if (head->vm_end - head->vm_start < size) {
-                printk(KERN_WARNING "%s: allocation too big (requested %#x)\n",
-                        __func__, size);
-                goto out;
-        }
-        new = kmalloc(sizeof(struct arm_vmregion), gfp);
-        if (!new)
-                goto out;
-        new->caller = caller;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        addr = rounddown(addr - size, align);
-        list_for_each_entry_reverse(c, &head->vm_list, vm_list) {
-                if (addr >= c->vm_end)
-                        goto found;
-                addr = rounddown(c->vm_start - size, align);
-                if (addr < start)
-                        goto nospc;
-        }
- found:
-        /*
-         * Insert this entry after the one we found.
-         */
-        list_add(&new->vm_list, &c->vm_list);
-        new->vm_start = addr;
-        new->vm_end = addr + size;
-        new->vm_active = 1;
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return new;
- nospc:
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        kfree(new);
- out:
-        return NULL;
-}
-static struct arm_vmregion *__arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        list_for_each_entry(c, &head->vm_list, vm_list) {
-                if (c->vm_active && c->vm_start == addr)
-                        goto out;
-        }
-        c = NULL;
- out:
-        return c;
-}
-struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        c = __arm_vmregion_find(head, addr);
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return c;
-}
-struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        c = __arm_vmregion_find(head, addr);
-        if (c)
-                c->vm_active = 0;
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return c;
-}
-void arm_vmregion_free(struct arm_vmregion_head *head, struct arm_vmregion *c)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        list_del(&c->vm_list);
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        kfree(c);
-}
-#ifdef CONFIG_PROC_FS
-static int arm_vmregion_show(struct seq_file *m, void *p)
-{
-        struct arm_vmregion *c = list_entry(p, struct arm_vmregion, vm_list);
-        seq_printf(m, "0x%08lx-0x%08lx %7lu", c->vm_start, c->vm_end,
-                c->vm_end - c->vm_start);
-        if (c->caller)
-                seq_printf(m, " %pS", (void *)c->caller);
-        seq_putc(m, '\n');
-        return 0;
-}
-static void *arm_vmregion_start(struct seq_file *m, loff_t *pos)
-{
-        struct arm_vmregion_head *h = m->private;
-        spin_lock_irq(&h->vm_lock);
-        return seq_list_start(&h->vm_list, *pos);
-}
-static void *arm_vmregion_next(struct seq_file *m, void *p, loff_t *pos)
-{
-        struct arm_vmregion_head *h = m->private;
-        return seq_list_next(p, &h->vm_list, pos);
-}
-static void arm_vmregion_stop(struct seq_file *m, void *p)
-{
-        struct arm_vmregion_head *h = m->private;
-        spin_unlock_irq(&h->vm_lock);
-}
-static const struct seq_operations arm_vmregion_ops = {
-        .start  = arm_vmregion_start,
-        .stop   = arm_vmregion_stop,
-        .next   = arm_vmregion_next,
-        .show   = arm_vmregion_show,
-};
-static int arm_vmregion_open(struct inode *inode, struct file *file)
-{
-        struct arm_vmregion_head *h = PDE(inode)->data;
-        int ret = seq_open(file, &arm_vmregion_ops);
-        if (!ret) {
-                struct seq_file *m = file->private_data;
-                m->private = h;
-        }
-        return ret;
-}
-static const struct file_operations arm_vmregion_fops = {
-        .open   = arm_vmregion_open,
-        .read   = seq_read,
-        .llseek = seq_lseek,
-        .release = seq_release,
-};
-int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h)
-{
-        proc_create_data(path, S_IRUSR, NULL, &arm_vmregion_fops, h);
-        return 0;
-}
-#else
-int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h)
-{
-        return 0;
-}
-#endif
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
deleted file mode 100644
index 0f5a5f2a2c7b..000000000000
--- a/arch/arm/mm/vmregion.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef VMREGION_H
-#define VMREGION_H
-#include <linux/spinlock.h>
-#include <linux/list.h>
-struct page;
-struct arm_vmregion_head {
-        spinlock_t              vm_lock;
-        struct list_head        vm_list;
-        unsigned long           vm_start;
-        unsigned long           vm_end;
-};
-struct arm_vmregion {
-        struct list_head        vm_list;
-        unsigned long           vm_start;
-        unsigned long           vm_end;
-        int                     vm_active;
-        const void              *caller;
-};
-struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t, const void *);
-struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
-struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
-void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
-int arm_vmregion_create_proc(const char *, struct arm_vmregion_head *);
-#endif
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index a34f1e214116..6828ef6ce80e 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
 static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
 {
-        emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
+        /* r_dst = (r_src << 8) | (r_src >> 8) */
-        emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
+        emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
-        emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
+        emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
-        emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
+        /*
+         * we need to mask out the bits set in r_dst[23:16] due to
+         * the first shift instruction.
+         *
+         * note that 0x8ff is the encoded immediate 0x00ff0000.
+         */
+        emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
 }
 #else  /* ARMv6+ */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 665870dce3c8..67c859cf16bc 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -5,36 +5,6 @@ menu "TI OMAP Common Features"
 config ARCH_OMAP_OTG
        bool
-choice
-        prompt "OMAP System Type"
-        default ARCH_OMAP2PLUS
-config ARCH_OMAP1
-        bool "TI OMAP1"
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select GENERIC_IRQ_CHIP
-        select HAVE_IDE
-        select IRQ_DOMAIN
-        select NEED_MACH_IO_H if PCCARD
-        select NEED_MACH_MEMORY_H
-        help
-          "Systems based on omap7xx, omap15xx or omap16xx"
-config ARCH_OMAP2PLUS
-        bool "TI OMAP2/3/4"
-        select CLKDEV_LOOKUP
-        select GENERIC_IRQ_CHIP
-        select OMAP_DM_TIMER
-        select PINCTRL
-        select PROC_DEVICETREE if PROC_FS
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
-endchoice
 comment "OMAP Feature Selections"
 config OMAP_DEBUG_DEVICES
@@ -118,7 +88,7 @@ config OMAP_MUX_WARNINGS
 config OMAP_MBOX_FWK
        tristate "Mailbox framework support"
-        depends on ARCH_OMAP
+        depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
        help
          Say Y here if you want to use OMAP Mailbox framework support for
          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a14a78a2f149..31199417b56a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
 # Common support
 obj-y := sram.o dma.o counter_32k.o
 obj-m :=
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 4136b20cba3c..e06c34bdc34a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2019,7 +2019,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
        errata                  = p->errata;
        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
-                        && (omap_dma_reserve_channels <= dma_lch_count))
+                        && (omap_dma_reserve_channels < d->lch_count))
                d->lch_count    = omap_dma_reserve_channels;
        dma_lch_count           = d->lch_count;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 7b433f3bddca..a0daa2fb5de6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -808,11 +808,9 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
                return  -ENOMEM;
        }
-        timer->io_base = devm_request_and_ioremap(dev, mem);
+        timer->io_base = devm_ioremap_resource(dev, mem);
-        if (!timer->io_base) {
+        if (IS_ERR(timer->io_base))
-                dev_err(dev, "%s: region already claimed.\n", __func__);
+                return PTR_ERR(timer->io_base);
-                return -ENOMEM;
-        }
        if (dev->of_node) {
                if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index f9df624d108c..58213d9714cd 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -68,7 +68,7 @@ __setup("i2c_bus=", omap_i2c_bus_setup);
 * Register busses defined in command line but that are not registered with
 * omap_register_i2c_bus from board initialization code.
 */
-static int __init omap_register_i2c_bus_cmdline(void)
+int __init omap_register_i2c_bus_cmdline(void)
 {
        int i, err = 0;
@@ -83,7 +83,6 @@ static int __init omap_register_i2c_bus_cmdline(void)
 out:
        return err;
 }
-subsys_initcall(omap_register_i2c_bus_cmdline);
 /**
 * omap_register_i2c_bus - register I2C bus with device descriptors
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7a9028cb5a75..810629d79668 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -32,6 +32,7 @@ int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
                                 struct i2c_board_info const *info,
                                 unsigned len);
+extern int omap_register_i2c_bus_cmdline(void);
 #else
 static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
                                 struct i2c_board_info const *info,
@@ -39,6 +40,11 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 {
        return 0;
 }
+static inline int omap_register_i2c_bus_cmdline(void)
+{
+        return 0;
+}
 #endif
 struct omap_hwmod;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
deleted file mode 100644
index eef3b6a2f8a8..000000000000
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-config PLAT_S3C24XX
-        bool
-        depends on ARCH_S3C24XX
-        default y
-        select ARCH_REQUIRE_GPIOLIB
-        select NO_IOPORT
-        select S3C_DEV_NAND
-        help
-          Base platform code for any Samsung S3C24XX device
-if PLAT_S3C24XX
-# low-level serial option nodes
-config CPU_LLSERIAL_S3C2410_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
-config CPU_LLSERIAL_S3C2440_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
-config CPU_LLSERIAL_S3C2410
-        bool
-        help
-          Selected if there is an S3C2410 (or register compatible) serial
-          low-level implementation needed
-config CPU_LLSERIAL_S3C2440
-        bool
-        help
-          Selected if there is an S3C2440 (or register compatible) serial
-          low-level implementation needed
-# code that is shared between a number of the s3c24xx implementations
-config S3C2410_CLOCK
-        bool
-        help
-          Clock code for the S3C2410, and similar processors which
-          is currently includes the S3C2410, S3C2440, S3C2442.
-config S3C24XX_DCLK
-        bool
-        help
-          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-# gpio configurations
-config S3C24XX_GPIO_EXTRA
-        int
-        default 128 if S3C24XX_GPIO_EXTRA128
-        default 64 if S3C24XX_GPIO_EXTRA64
-        default 16 if ARCH_H1940
-        default 0
-config S3C24XX_GPIO_EXTRA64
-        bool
-        help
-          Add an extra 64 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-config S3C24XX_GPIO_EXTRA128
-        bool
-        help
-          Add an extra 128 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-config S3C24XX_DMA
-        bool "S3C2410 DMA support"
-        depends on ARCH_S3C24XX
-        select S3C_DMA
-        help
-          S3C2410 DMA support. This is needed for drivers like sound which
-          use the S3C2410's DMA system to move data to and from the
-          peripheral blocks.
-config S3C2410_DMA_DEBUG
-        bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C24XX && S3C2410_DMA
-        help
-          Enable debugging output for the DMA code. This option sends info
-          to the kernel log, at priority KERN_DEBUG.
-# common code for s3c24xx based machines, such as the SMDKs.
-# cpu frequency items common between s3c2410 and s3c2440/s3c2442
-config S3C2410_IOTIMING
-        bool
-        depends on CPU_FREQ_S3C24XX
-        help
-          Internal node to select io timing code that is common to the s3c2410
-          and s3c2440/s3c2442 cpu frequency support.
-config S3C2410_CPUFREQ_UTILS
-        bool
-        depends on CPU_FREQ_S3C24XX
-        help
-          Internal node to select timing code that is common to the s3c2410
-          and s3c2440/s3c244 cpu frequency support.
-# cpu frequency support common to s3c2412, s3c2413 and s3c2442
-config S3C2412_IOTIMING
-        bool
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
-        help
-          Intel node to select io timing code that is common to the s3c2412
-          and the s3c2443.
-endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
deleted file mode 100644
index 9f60549c8da1..000000000000
--- a/arch/arm/plat-s3c24xx/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-# arch/arm/plat-s3c24xx/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-# Core files
-obj-y                           += irq.o
-obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpu-freq.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
-# Architecture dependent builds
-obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
-obj-$(CONFIG_S3C24XX_DMA)       += dma.o
-obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
-obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
-obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
deleted file mode 100644
index fe57bbbf166b..000000000000
--- a/arch/arm/plat-s3c24xx/irq.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <plat/regs-irqtype.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-static void
-s3c_irq_mask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - IRQ_EINT0;
-        unsigned long mask;
-        mask = __raw_readl(S3C2410_INTMSK);
-        mask |= 1UL << irqno;
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-static inline void
-s3c_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-static inline void
-s3c_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-static void
-s3c_irq_unmask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq;
-        unsigned long mask;
-        if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
-                irqdbf2("s3c_irq_unmask %d\n", irqno);
-        irqno -= IRQ_EINT0;
-        mask = __raw_readl(S3C2410_INTMSK);
-        mask &= ~(1UL << irqno);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-struct irq_chip s3c_irq_level_chip = {
-        .name           = "s3c-level",
-        .irq_ack        = s3c_irq_maskack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-struct irq_chip s3c_irq_chip = {
-        .name           = "s3c",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-static void
-s3c_irqext_mask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - EXTINT_OFF;
-        unsigned long mask;
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        mask |= ( 1UL << irqno);
-        __raw_writel(mask, S3C24XX_EINTMASK);
-}
-static void
-s3c_irqext_ack(struct irq_data *data)
-{
-        unsigned long req;
-        unsigned long bit;
-        unsigned long mask;
-        bit = 1UL << (data->irq - EXTINT_OFF);
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        __raw_writel(bit, S3C24XX_EINTPEND);
-        req = __raw_readl(S3C24XX_EINTPEND);
-        req &= ~mask;
-        /* not sure if we should be acking the parent irq... */
-        if (data->irq <= IRQ_EINT7) {
-                if ((req & 0xf0) == 0)
-                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
-        } else {
-                if ((req >> 8) == 0)
-                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
-        }
-}
-static void
-s3c_irqext_unmask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - EXTINT_OFF;
-        unsigned long mask;
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        mask &= ~(1UL << irqno);
-        __raw_writel(mask, S3C24XX_EINTMASK);
-}
-int
-s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-        unsigned long newvalue = 0, value;
-        if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->irq - IRQ_EINT0) * 2;
-                extint_offset = (data->irq - IRQ_EINT0) * 4;
-        } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
-                extint_offset = (data->irq - (EXTINT_OFF)) * 4;
-        } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
-                extint_offset = (data->irq - IRQ_EINT8) * 4;
-        } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
-                extint_offset = (data->irq - IRQ_EINT16) * 4;
-        } else {
-                return -1;
-        }
-        /* Set the GPIO to external interrupt mode */
-        value = __raw_readl(gpcon_reg);
-        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-        __raw_writel(value, gpcon_reg);
-        /* Set the external interrupt to pointed trigger type */
-        switch (type)
-        {
-                case IRQ_TYPE_NONE:
-                        printk(KERN_WARNING "No edge setting!\n");
-                        break;
-                case IRQ_TYPE_EDGE_RISING:
-                        newvalue = S3C2410_EXTINT_RISEEDGE;
-                        break;
-                case IRQ_TYPE_EDGE_FALLING:
-                        newvalue = S3C2410_EXTINT_FALLEDGE;
-                        break;
-                case IRQ_TYPE_EDGE_BOTH:
-                        newvalue = S3C2410_EXTINT_BOTHEDGE;
-                        break;
-                case IRQ_TYPE_LEVEL_LOW:
-                        newvalue = S3C2410_EXTINT_LOWLEV;
-                        break;
-                case IRQ_TYPE_LEVEL_HIGH:
-                        newvalue = S3C2410_EXTINT_HILEV;
-                        break;
-                default:
-                        printk(KERN_ERR "No such irq type %d", type);
-                        return -1;
-        }
-        value = __raw_readl(extint_reg);
-        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-        __raw_writel(value, extint_reg);
-        return 0;
-}
-static struct irq_chip s3c_irqext_chip = {
-        .name           = "s3c-ext",
-        .irq_mask       = s3c_irqext_mask,
-        .irq_unmask     = s3c_irqext_unmask,
-        .irq_ack        = s3c_irqext_ack,
-        .irq_set_type   = s3c_irqext_type,
-        .irq_set_wake   = s3c_irqext_wake
-};
-static struct irq_chip s3c_irq_eint0t4 = {
-        .name           = "s3c-ext0",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-/* mask values for the parent registers for each of the interrupt types */
-#define INTMSK_UART0     (1UL << (IRQ_UART0 - IRQ_EINT0))
-#define INTMSK_UART1     (1UL << (IRQ_UART1 - IRQ_EINT0))
-#define INTMSK_UART2     (1UL << (IRQ_UART2 - IRQ_EINT0))
-#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
-/* UART0 */
-static void
-s3c_irq_uart0_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
-}
-static void
-s3c_irq_uart0_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART0);
-}
-static void
-s3c_irq_uart0_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
-}
-static struct irq_chip s3c_irq_uart0 = {
-        .name           = "s3c-uart0",
-        .irq_mask       = s3c_irq_uart0_mask,
-        .irq_unmask     = s3c_irq_uart0_unmask,
-        .irq_ack        = s3c_irq_uart0_ack,
-};
-/* UART1 */
-static void
-s3c_irq_uart1_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
-}
-static void
-s3c_irq_uart1_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART1);
-}
-static void
-s3c_irq_uart1_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
-}
-static struct irq_chip s3c_irq_uart1 = {
-        .name           = "s3c-uart1",
-        .irq_mask       = s3c_irq_uart1_mask,
-        .irq_unmask     = s3c_irq_uart1_unmask,
-        .irq_ack        = s3c_irq_uart1_ack,
-};
-/* UART2 */
-static void
-s3c_irq_uart2_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
-}
-static void
-s3c_irq_uart2_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART2);
-}
-static void
-s3c_irq_uart2_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
-}
-static struct irq_chip s3c_irq_uart2 = {
-        .name           = "s3c-uart2",
-        .irq_mask       = s3c_irq_uart2_mask,
-        .irq_unmask     = s3c_irq_uart2_unmask,
-        .irq_ack        = s3c_irq_uart2_ack,
-};
-/* ADC and Touchscreen */
-static void
-s3c_irq_adc_mask(struct irq_data *d)
-{
-        s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
-}
-static void
-s3c_irq_adc_unmask(struct irq_data *d)
-{
-        s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
-}
-static void
-s3c_irq_adc_ack(struct irq_data *d)
-{
-        s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
-}
-static struct irq_chip s3c_irq_adc = {
-        .name           = "s3c-adc",
-        .irq_mask       = s3c_irq_adc_mask,
-        .irq_unmask     = s3c_irq_adc_unmask,
-        .irq_ack        = s3c_irq_adc_ack,
-};
-/* irq demux for adc */
-static void s3c_irq_demux_adc(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-        unsigned int offset = 9;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc &= ~submsk;
-        subsrc >>= offset;
-        subsrc &= 3;
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_TC);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_ADC);
-                }
-        }
-}
-static void s3c_irq_demux_uart(unsigned int start)
-{
-        unsigned int subsrc, submsk;
-        unsigned int offset = start - IRQ_S3CUART_RX0;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
-                start, offset, subsrc, submsk);
-        subsrc &= ~submsk;
-        subsrc >>= offset;
-        subsrc &= 7;
-        if (subsrc != 0) {
-                if (subsrc & 1)
-                        generic_handle_irq(start);
-                if (subsrc & 2)
-                        generic_handle_irq(start+1);
-                if (subsrc & 4)
-                        generic_handle_irq(start+2);
-        }
-}
-/* uart demux entry points */
-static void
-s3c_irq_demux_uart0(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX0);
-}
-static void
-s3c_irq_demux_uart1(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX1);
-}
-static void
-s3c_irq_demux_uart2(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX2);
-}
-static void
-s3c_irq_demux_extint8(unsigned int irq,
-                      struct irq_desc *desc)
-{
-        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
-        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
-        eintpnd &= ~eintmsk;
-        eintpnd &= ~0xff;       /* ignore lower irqs */
-        /* we may as well handle all the pending IRQs here */
-        while (eintpnd) {
-                irq = __ffs(eintpnd);
-                eintpnd &= ~(1<<irq);
-                irq += (IRQ_EINT4 - 4);
-                generic_handle_irq(irq);
-        }
-}
-static void
-s3c_irq_demux_extint4t7(unsigned int irq,
-                        struct irq_desc *desc)
-{
-        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
-        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
-        eintpnd &= ~eintmsk;
-        eintpnd &= 0xff;        /* only lower irqs */
-        /* we may as well handle all the pending IRQs here */
-        while (eintpnd) {
-                irq = __ffs(eintpnd);
-                eintpnd &= ~(1<<irq);
-                irq += (IRQ_EINT4 - 4);
-                generic_handle_irq(irq);
-        }
-}
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- */
-int s3c24xx_set_fiq(unsigned int irq, bool on)
-{
-        u32 intmod;
-        unsigned offs;
-        if (on) {
-                offs = irq - FIQ_START;
-                if (offs > 31)
-                        return -EINVAL;
-                intmod = 1 << offs;
-        } else {
-                intmod = 0;
-        }
-        __raw_writel(intmod, S3C2410_INTMOD);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
-void __init s3c24xx_init_irq(void)
-{
-        unsigned long pend;
-        unsigned long last;
-        int irqno;
-        int i;
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-        irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
-        /* first, clear all interrupts pending... */
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C24XX_EINTPEND);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C24XX_EINTPEND);
-                printk("irq: clearing pending ext status %08x\n", (int)pend);
-                last = pend;
-        }
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2410_INTPND);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C2410_SRCPND);
-                __raw_writel(pend, S3C2410_INTPND);
-                printk("irq: clearing pending status %08x\n", (int)pend);
-                last = pend;
-        }
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2410_SUBSRCPND);
-                if (pend == 0 || pend == last)
-                        break;
-                printk("irq: clearing subpending status %08x\n", (int)pend);
-                __raw_writel(pend, S3C2410_SUBSRCPND);
-                last = pend;
-        }
-        /* register the main interrupts */
-        irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
-        for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
-                /* set all the s3c2410 internal irqs */
-                switch (irqno) {
-                        /* deal with the special IRQs (cascaded) */
-                case IRQ_EINT4t7:
-                case IRQ_EINT8t23:
-                case IRQ_UART0:
-                case IRQ_UART1:
-                case IRQ_UART2:
-                case IRQ_ADCPARENT:
-                        irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
-                                                 handle_level_irq);
-                        break;
-                case IRQ_RESERVED6:
-                case IRQ_RESERVED24:
-                        /* no IRQ here */
-                        break;
-                default:
-                        //irqdbf("registering irq %d (s3c irq)\n", irqno);
-                        irq_set_chip_and_handler(irqno, &s3c_irq_chip,
-                                                 handle_edge_irq);
-                        set_irq_flags(irqno, IRQF_VALID);
-                }
-        }
-        /* setup the cascade irq handlers */
-        irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
-        irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
-        irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
-        irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
-        irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
-        irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
-        /* external interrupts */
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irqdbf("registering irq %d (ext int)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
-                irqdbf("registering irq %d (extended s3c irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        /* register the uart interrupts */
-        irqdbf("s3c2410: registering external interrupts\n");
-        for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
-                irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
-                irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
-                irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
-                irqdbf("registering irq %d (s3c adc irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        irqdbf("s3c2410: registered interrupt handlers\n");
-}
-struct syscore_ops s3c24xx_irq_syscore_ops = {
-        .suspend        = s3c24xx_irq_suspend,
-        .resume         = s3c24xx_irq_resume,
-};
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 2d676ab50f73..ca07cb1b155a 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -386,11 +386,9 @@ static int s3c_adc_probe(struct platform_device *pdev)
                return -ENXIO;
        }
-        adc->regs = devm_request_and_ioremap(dev, regs);
+        adc->regs = devm_ioremap_resource(dev, regs);
-        if (!adc->regs) {
+        if (IS_ERR(adc->regs))
-                dev_err(dev, "failed to map registers\n");
+                return PTR_ERR(adc->regs);
-                return -ENXIO;
-        }
        ret = regulator_enable(adc->vdd);
        if (ret)
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index d088afa034e8..71d58ddea9c1 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -19,7 +19,8 @@
 #include <mach/dma.h>
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
-                                struct samsung_dma_req *param)
+                                struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name)
 {
        dma_cap_mask_t mask;
        void *filter_param;
@@ -33,7 +34,12 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
         */
        filter_param = (dma_ch == DMACH_DT_PROP) ?
                (void *)param->dt_dmach_prop : (void *)dma_ch;
-        return (unsigned)dma_request_channel(mask, pl330_filter, filter_param);
+        if (dev->of_node)
+                return (unsigned)dma_request_slave_channel(dev, ch_name);
+        else
+                return (unsigned)dma_request_channel(mask, pl330_filter,
+                                                        filter_param);
 }
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
index b258a08de591..2fc89315553f 100644
--- a/arch/arm/plat-samsung/include/plat/adc.h
+++ b/arch/arm/plat-samsung/include/plat/adc.h
@@ -15,6 +15,7 @@
 #define __ASM_PLAT_ADC_H __FILE__
 struct s3c_adc_client;
+struct platform_device;
 extern int s3c_adc_start(struct s3c_adc_client *client,
                         unsigned int channel, unsigned int nr_samples);
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
index 207e275362a8..f3a9cff6d5d4 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -14,12 +14,12 @@
 /* The S5PV210/S5PC110 implementations are as belows. */
        .macro fifo_level_s5pv210 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S5PV210_UFSTAT_TXMASK
        .endm
        .macro  fifo_full_s5pv210 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S5PV210_UFSTAT_TXFULL
        .endm
@@ -27,7 +27,7 @@
 * most widely re-used */
        .macro fifo_level_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
        .endm
@@ -36,7 +36,7 @@
 #endif
        .macro  fifo_full_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S3C2440_UFSTAT_TXFULL
        .endm
@@ -45,11 +45,11 @@
 #endif
        .macro  senduart,rd,rx
-                strb    \rd, [\rx, # S3C2410_UTXH ]
+                strb    \rd, [\rx, # S3C2410_UTXH]
        .endm
        .macro  busyuart, rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                ldr     \rd, [\rx, # S3C2410_UFCON]
                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
                beq     1001f                           @
                @ FIFO enabled...
@@ -60,7 +60,7 @@
 1001:
                @ busy waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UTRSTAT]
                tst     \rd, #S3C2410_UTRSTAT_TXFE
                beq     1001b
@@ -68,7 +68,7 @@
        .endm
        .macro  waituart,rd,rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                ldr     \rd, [\rx, # S3C2410_UFCON]
                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
                beq     1001f                           @
                @ FIFO enabled...
@@ -79,7 +79,7 @@
                b       1002f
 1001:
                @ idle waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UTRSTAT]
                tst     \rd, #S3C2410_UTRSTAT_TXFE
                beq     1001b
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index f5144cdd3001..114178268b75 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -39,7 +39,8 @@ struct samsung_dma_config {
 };
 struct samsung_dma_ops {
-        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param);
+        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name);
        int (*release)(unsigned ch, void *param);
        int (*config)(unsigned ch, struct samsung_dma_config *param);
        int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
index 945a99d59563..1d6cb2b8b094 100644
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ b/arch/arm/plat-samsung/include/plat/fimc-core.h
@@ -43,6 +43,8 @@ static inline void s3c_fimc_setname(int id, char *name)
                s5p_device_fimc3.name = name;
                break;
 #endif
+        default:
+                break;
        }
 }
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index f7a3ea2c498a..cf5aae5b0975 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -106,7 +106,18 @@ static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chi
 #else
 /* machine specific code should provide samsung_gpiolib_getchip */
-#include <mach/gpio-track.h>
+extern struct samsung_gpio_chip s3c24xx_gpios[];
+static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
+{
+        struct samsung_gpio_chip *chip;
+        if (pin > S3C_GPIO_END)
+                return NULL;
+        chip = &s3c24xx_gpios[pin/32];
+        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
+}
 static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
 #endif
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
deleted file mode 100644
index d1ecef0e38e0..000000000000
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <plat/gpio-cfg.h>
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 887a0c954379..f6fcadeee969 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -109,17 +109,11 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 #ifdef CONFIG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
-extern int s3c24xx_irq_suspend(void);
-extern void s3c24xx_irq_resume(void);
 #else
 #define s3c_irq_wake NULL
 #define s3c_irqext_wake NULL
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
 #endif
-extern struct syscore_ops s3c24xx_irq_syscore_ops;
 /* PM debug functions */
 #ifdef CONFIG_SAMSUNG_PM_DEBUG
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index 7178e338e25e..f27399a3c68d 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -25,6 +25,7 @@ extern  int s3c2416_baseclk_add(void);
 extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
 extern struct syscore_ops s3c2416_irq_syscore_ops;
 #else
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index a5b794ff838b..71b88ec48956 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -25,6 +25,8 @@ extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
 extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
 #define s3c2443_init_uarts NULL
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 151cc9195cf6..9b87f38fc4f4 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -374,6 +374,8 @@ static inline void s3c_sdhci_setname(int id, char *name)
                s3c_device_hsmmc3.name = name;
                break;
 #endif
+        default:
+                break;
        }
 }
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7e068d182c3d..438b24846e7f 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -97,33 +97,6 @@ static inline void flush(void)
                *((volatile unsigned int __force *)(ad)) = (d); \
        } while (0)
-/* CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-#define WDOG_COUNT (0xff00)
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
 static void arch_decomp_error(const char *x)
@@ -173,7 +146,6 @@ arch_decomp_setup(void)
         */
        arch_detect_cpu();
-        arch_decomp_wdog_start();
        /* Enable the UART FIFOs if they where not enabled and our
         * configuration says we should turn them on.
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 15070284343e..002b1472293b 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -51,7 +51,7 @@ void s3c_pm_dbg(const char *fmt, ...)
        char buff[256];
        va_start(va, fmt);
-        vsprintf(buff, fmt, va);
+        vsnprintf(buff, sizeof(buff), fmt, va);
        va_end(va);
        printascii(buff);
@@ -243,6 +243,7 @@ int (*pm_cpu_sleep)(unsigned long);
 static int s3c_pm_enter(suspend_state_t state)
 {
+        int ret;
        /* ensure the debug is initialised (if enabled) */
        s3c_pm_debug_init();
@@ -300,7 +301,9 @@ static int s3c_pm_enter(suspend_state_t state)
         * we resume as it saves its own register state and restores it
         * during the resume.  */
-        cpu_suspend(0, pm_cpu_sleep);
+        ret = cpu_suspend(0, pm_cpu_sleep);
+        if (ret)
+                return ret;
        /* restore the system state */
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
index f99448c48d30..0cc40aea3f5a 100644
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -36,7 +36,8 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
 }
 static unsigned s3c_dma_request(enum dma_ch dma_ch,
-                                        struct samsung_dma_req *param)
+                                struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name)
 {
        struct cb_data *data;
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 87dbd81bdf51..739d016eb273 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -10,6 +10,7 @@ choice
 config ARCH_SPEAR13XX
        bool "ST SPEAr13xx with Device Tree"
+        select ARCH_HAVE_CPUFREQ
        select ARM_GIC
        select CPU_V7
        select GPIO_SPEAR_SPICS
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 2ce6cb17a98b..51b2dc93e4da 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -38,6 +38,5 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif /* __PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 4f990115b1bd..7d4616d5df11 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,8 +11,8 @@
 * warranty of any kind, whether express or implied.
 */
 #include <linux/io.h>
+#include <linux/amba/sp810.h>
 #include <asm/system_misc.h>
-#include <asm/hardware/sp810.h>
 #include <mach/spear.h>
 #include <mach/generic.h>