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-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi1
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi87
-rw-r--r--arch/arm/boot/dts/am3517.dtsi2
-rw-r--r--arch/arm/boot/dts/am35xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am4372.dtsi89
-rw-r--r--arch/arm/boot/dts/am437x-idk-evm.dts25
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts84
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts53
-rw-r--r--arch/arm/boot/dts/dm8168-evm.dts25
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi34
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts8
-rw-r--r--arch/arm/boot/dts/dra7.dtsi183
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts8
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi5
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi5
-rw-r--r--arch/arm/boot/dts/omap2.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi80
-rw-r--r--arch/arm/boot/dts/omap2430-clocks.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi107
-rw-r--r--arch/arm/boot/dts/omap24xx-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts9
-rw-r--r--arch/arm/boot/dts/omap3.dtsi100
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi13
-rw-r--r--arch/arm/boot/dts/omap4-cpu-thermal.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi204
-rw-r--r--arch/arm/boot/dts/omap5.dtsi190
-rw-r--r--arch/arm/configs/multi_v7_defconfig82
-rw-r--r--arch/arm/configs/omap2plus_defconfig4
-rw-r--r--arch/arm/mach-asm9260/Kconfig2
-rw-r--r--arch/arm/mach-omap1/pm.c51
-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/clock.c111
-rw-r--r--arch/arm/mach-omap2/clock.h8
-rw-r--r--arch/arm/mach-omap2/cm.h2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm33xx.c2
-rw-r--r--arch/arm/mach-omap2/cm33xx.h3
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c3
-rw-r--r--arch/arm/mach-omap2/cm3xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm44xx.h3
-rw-r--r--arch/arm/mach-omap2/cm_common.c156
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c6
-rw-r--r--arch/arm/mach-omap2/common.c1
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/control.c201
-rw-r--r--arch/arm/mach-omap2/control.h10
-rw-r--r--arch/arm/mach-omap2/display.c15
-rw-r--r--arch/arm/mach-omap2/id.c5
-rw-r--r--arch/arm/mach-omap2/io.c114
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap-secure.h7
-rw-r--r--arch/arm/mach-omap2/omap4-common.c69
-rw-r--r--arch/arm/mach-omap2/pm24xx.c24
-rw-r--r--arch/arm/mach-omap2/pm34xx.c18
-rw-r--r--arch/arm/mach-omap2/prcm-common.h20
-rw-r--r--arch/arm/mach-omap2/prm.h27
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c6
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h4
-rw-r--r--arch/arm/mach-omap2/prm33xx.c2
-rw-r--r--arch/arm/mach-omap2/prm33xx.h2
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c20
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h7
-rw-r--r--arch/arm/mach-omap2/prm44xx.c70
-rw-r--r--arch/arm/mach-omap2/prm44xx.h1
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h8
-rw-r--r--arch/arm/mach-omap2/prm54xx.h1
-rw-r--r--arch/arm/mach-omap2/prm7xx.h2
-rw-r--r--arch/arm/mach-omap2/prm_common.c258
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c18
-rw-r--r--arch/arm/mach-omap2/prminst44xx.h1
-rw-r--r--arch/arm/mach-omap2/sleep44xx.S2
-rw-r--r--arch/arm/mach-omap2/vp.h9
-rw-r--r--arch/arm/mach-omap2/vp3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/vp44xx_data.c4
77 files changed, 1755 insertions, 981 deletions
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 6cc25ed912ee..2c6248d9a9ef 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -195,6 +195,7 @@
195 195
196&usb0 { 196&usb0 {
197 status = "okay"; 197 status = "okay";
198 dr_mode = "peripheral";
198}; 199};
199 200
200&usb1 { 201&usb1 {
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..236c78a3c6ca 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
83 }; 83 };
84 }; 84 };
85 85
86 am33xx_control_module: control_module@4a002000 {
87 compatible = "syscon";
88 reg = <0x44e10000 0x7fc>;
89 };
90
91 am33xx_pinmux: pinmux@44e10800 {
92 compatible = "pinctrl-single";
93 reg = <0x44e10800 0x0238>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 pinctrl-single,register-width = <32>;
97 pinctrl-single,function-mask = <0x7f>;
98 };
99
100 /* 86 /*
101 * XXX: Use a flat representation of the AM33XX interconnect. 87 * XXX: Use a flat representation of the AM33XX interconnect.
102 * The real AM33XX interconnect network is quite complex. Since 88 * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
111 ranges; 97 ranges;
112 ti,hwmods = "l3_main"; 98 ti,hwmods = "l3_main";
113 99
114 prcm: prcm@44e00000 { 100 l4_wkup: l4_wkup@44c00000 {
115 compatible = "ti,am3-prcm"; 101 compatible = "ti,am3-l4-wkup", "simple-bus";
116 reg = <0x44e00000 0x4000>; 102 #address-cells = <1>;
117 103 #size-cells = <1>;
118 prcm_clocks: clocks { 104 ranges = <0 0x44c00000 0x280000>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 };
122 105
123 prcm_clockdomains: clockdomains { 106 prcm: prcm@200000 {
124 }; 107 compatible = "ti,am3-prcm";
125 }; 108 reg = <0x200000 0x4000>;
126 109
127 scrm: scrm@44e10000 { 110 prcm_clocks: clocks {
128 compatible = "ti,am3-scrm"; 111 #address-cells = <1>;
129 reg = <0x44e10000 0x2000>; 112 #size-cells = <0>;
113 };
130 114
131 scrm_clocks: clocks { 115 prcm_clockdomains: clockdomains {
132 #address-cells = <1>; 116 };
133 #size-cells = <0>;
134 }; 117 };
135 118
136 scrm_clockdomains: clockdomains { 119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
137 }; 149 };
138 }; 150 };
139 151
140 cm: syscon@44e10000 {
141 compatible = "ti,am33xx-controlmodule", "syscon";
142 reg = <0x44e10000 0x800>;
143 };
144
145 intc: interrupt-controller@48200000 { 152 intc: interrupt-controller@48200000 {
146 compatible = "ti,am33xx-intc"; 153 compatible = "ti,am33xx-intc";
147 interrupt-controller; 154 interrupt-controller;
@@ -350,7 +357,7 @@
350 reg = <0x481cc000 0x2000>; 357 reg = <0x481cc000 0x2000>;
351 clocks = <&dcan0_fck>; 358 clocks = <&dcan0_fck>;
352 clock-names = "fck"; 359 clock-names = "fck";
353 syscon-raminit = <&am33xx_control_module 0x644 0>; 360 syscon-raminit = <&scm_conf 0x644 0>;
354 interrupts = <52>; 361 interrupts = <52>;
355 status = "disabled"; 362 status = "disabled";
356 }; 363 };
@@ -361,7 +368,7 @@
361 reg = <0x481d0000 0x2000>; 368 reg = <0x481d0000 0x2000>;
362 clocks = <&dcan1_fck>; 369 clocks = <&dcan1_fck>;
363 clock-names = "fck"; 370 clock-names = "fck";
364 syscon-raminit = <&am33xx_control_module 0x644 1>; 371 syscon-raminit = <&scm_conf 0x644 1>;
365 interrupts = <55>; 372 interrupts = <55>;
366 status = "disabled"; 373 status = "disabled";
367 }; 374 };
@@ -720,7 +727,7 @@
720 */ 727 */
721 interrupts = <40 41 42 43>; 728 interrupts = <40 41 42 43>;
722 ranges; 729 ranges;
723 syscon = <&cm>; 730 syscon = <&scm_conf>;
724 status = "disabled"; 731 status = "disabled";
725 732
726 davinci_mdio: mdio@4a101000 { 733 davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
31 status = "disabled"; 31 status = "disabled";
32 reg = <0x5c000000 0x30000>; 32 reg = <0x5c000000 0x30000>;
33 interrupts = <67 68 69 70>; 33 interrupts = <67 68 69 70>;
34 syscon = <&omap3_scm_general>; 34 syscon = <&scm_conf>;
35 ti,davinci-ctrl-reg-offset = <0x10000>; 35 ti,davinci-ctrl-reg-offset = <0x10000>;
36 ti,davinci-ctrl-mod-reg-offset = <0>; 36 ti,davinci-ctrl-mod-reg-offset = <0>;
37 ti,davinci-ctrl-ram-offset = <0x20000>; 37 ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 emac_ick: emac_ick { 11 emac_ick: emac_ick {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,am35xx-gate-clock"; 13 compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..2f6f0c2040db 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,22 +57,6 @@
57 cache-level = <2>; 57 cache-level = <2>;
58 }; 58 };
59 59
60 am43xx_control_module: control_module@4a002000 {
61 compatible = "syscon";
62 reg = <0x44e10000 0x7f4>;
63 };
64
65 am43xx_pinmux: pinmux@44e10800 {
66 compatible = "ti,am437-padconf", "pinctrl-single";
67 reg = <0x44e10800 0x31c>;
68 #address-cells = <1>;
69 #size-cells = <0>;
70 #interrupt-cells = <1>;
71 interrupt-controller;
72 pinctrl-single,register-width = <32>;
73 pinctrl-single,function-mask = <0xffffffff>;
74 };
75
76 ocp { 60 ocp {
77 compatible = "ti,am4372-l3-noc", "simple-bus"; 61 compatible = "ti,am4372-l3-noc", "simple-bus";
78 #address-cells = <1>; 62 #address-cells = <1>;
@@ -84,29 +68,58 @@
84 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 69 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
86 70
87 prcm: prcm@44df0000 { 71 l4_wkup: l4_wkup@44c00000 {
88 compatible = "ti,am4-prcm"; 72 compatible = "ti,am4-l4-wkup", "simple-bus";
89 reg = <0x44df0000 0x11000>; 73 #address-cells = <1>;
90 74 #size-cells = <1>;
91 prcm_clocks: clocks { 75 ranges = <0 0x44c00000 0x287000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 };
95 76
96 prcm_clockdomains: clockdomains { 77 prcm: prcm@1f0000 {
97 }; 78 compatible = "ti,am4-prcm";
98 }; 79 reg = <0x1f0000 0x11000>;
99 80
100 scrm: scrm@44e10000 { 81 prcm_clocks: clocks {
101 compatible = "ti,am4-scrm"; 82 #address-cells = <1>;
102 reg = <0x44e10000 0x2000>; 83 #size-cells = <0>;
84 };
103 85
104 scrm_clocks: clocks { 86 prcm_clockdomains: clockdomains {
105 #address-cells = <1>; 87 };
106 #size-cells = <0>;
107 }; 88 };
108 89
109 scrm_clockdomains: clockdomains { 90 scm: scm@210000 {
91 compatible = "ti,am4-scm", "simple-bus";
92 reg = <0x210000 0x4000>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x210000 0x4000>;
96
97 am43xx_pinmux: pinmux@800 {
98 compatible = "ti,am437-padconf",
99 "pinctrl-single";
100 reg = <0x800 0x31c>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 #interrupt-cells = <1>;
104 interrupt-controller;
105 pinctrl-single,register-width = <32>;
106 pinctrl-single,function-mask = <0xffffffff>;
107 };
108
109 scm_conf: scm_conf@0 {
110 compatible = "syscon";
111 reg = <0x0 0x800>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114
115 scm_clocks: clocks {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119 };
120
121 scm_clockdomains: clockdomains {
122 };
110 }; 123 };
111 }; 124 };
112 125
@@ -787,7 +800,7 @@
787 }; 800 };
788 801
789 ocp2scp0: ocp2scp@483a8000 { 802 ocp2scp0: ocp2scp@483a8000 {
790 compatible = "ti,omap-ocp2scp"; 803 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
791 #address-cells = <1>; 804 #address-cells = <1>;
792 #size-cells = <1>; 805 #size-cells = <1>;
793 ranges; 806 ranges;
@@ -806,7 +819,7 @@
806 }; 819 };
807 820
808 ocp2scp1: ocp2scp@483e8000 { 821 ocp2scp1: ocp2scp@483e8000 {
809 compatible = "ti,omap-ocp2scp"; 822 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
810 #address-cells = <1>; 823 #address-cells = <1>;
811 #size-cells = <1>; 824 #size-cells = <1>;
812 ranges; 825 ranges;
@@ -933,7 +946,7 @@
933 clocks = <&dcan0_fck>; 946 clocks = <&dcan0_fck>;
934 clock-names = "fck"; 947 clock-names = "fck";
935 reg = <0x481cc000 0x2000>; 948 reg = <0x481cc000 0x2000>;
936 syscon-raminit = <&am43xx_control_module 0x644 0>; 949 syscon-raminit = <&scm_conf 0x644 0>;
937 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
938 status = "disabled"; 951 status = "disabled";
939 }; 952 };
@@ -944,7 +957,7 @@
944 clocks = <&dcan1_fck>; 957 clocks = <&dcan1_fck>;
945 clock-names = "fck"; 958 clock-names = "fck";
946 reg = <0x481d0000 0x2000>; 959 reg = <0x481d0000 0x2000>;
947 syscon-raminit = <&am43xx_control_module 0x644 1>; 960 syscon-raminit = <&scm_conf 0x644 1>;
948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 961 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
949 status = "disabled"; 962 status = "disabled";
950 }; 963 };
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index f9a17e2ca8cb..0198f5a62b96 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -133,20 +133,6 @@
133 >; 133 >;
134 }; 134 };
135 135
136 i2c1_pins_default: i2c1_pins_default {
137 pinctrl-single,pins = <
138 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
139 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
140 >;
141 };
142
143 i2c1_pins_sleep: i2c1_pins_sleep {
144 pinctrl-single,pins = <
145 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
146 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
147 >;
148 };
149
150 mmc1_pins_default: pinmux_mmc1_pins_default { 136 mmc1_pins_default: pinmux_mmc1_pins_default {
151 pinctrl-single,pins = < 137 pinctrl-single,pins = <
152 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 138 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
@@ -254,7 +240,7 @@
254 status = "okay"; 240 status = "okay";
255 pinctrl-names = "default", "sleep"; 241 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&i2c0_pins_default>; 242 pinctrl-0 = <&i2c0_pins_default>;
257 pinctrl-1 = <&i2c0_pins_default>; 243 pinctrl-1 = <&i2c0_pins_sleep>;
258 clock-frequency = <400000>; 244 clock-frequency = <400000>;
259 245
260 at24@50 { 246 at24@50 {
@@ -262,17 +248,10 @@
262 pagesize = <64>; 248 pagesize = <64>;
263 reg = <0x50>; 249 reg = <0x50>;
264 }; 250 };
265};
266
267&i2c1 {
268 status = "okay";
269 pinctrl-names = "default", "sleep";
270 pinctrl-0 = <&i2c1_pins_default>;
271 pinctrl-1 = <&i2c1_pins_default>;
272 clock-frequency = <400000>;
273 251
274 tps: tps62362@60 { 252 tps: tps62362@60 {
275 compatible = "ti,tps62362"; 253 compatible = "ti,tps62362";
254 reg = <0x60>;
276 regulator-name = "VDD_MPU"; 255 regulator-name = "VDD_MPU";
277 regulator-min-microvolt = <950000>; 256 regulator-min-microvolt = <950000>;
278 regulator-max-microvolt = <1330000>; 257 regulator-max-microvolt = <1330000>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..72f01bb5d61c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
69 }; 69 };
70 }; 70 };
71 71
72 am43xx_pinmux: pinmux@44e10800 { 72 matrix_keypad: matrix_keypad@0 {
73 compatible = "gpio-matrix-keypad";
74 debounce-delay-ms = <5>;
75 col-scan-delay-us = <2>;
76
77 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
78 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
79 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
80 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
81
82 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
83 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
84 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
85 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
86
87 linux,keymap = <0x00000201 /* P1 */
88 0x01000204 /* P4 */
89 0x02000207 /* P7 */
90 0x0300020a /* NUMERIC_STAR */
91 0x00010202 /* P2 */
92 0x01010205 /* P5 */
93 0x02010208 /* P8 */
94 0x03010200 /* P0 */
95 0x00020203 /* P3 */
96 0x01020206 /* P6 */
97 0x02020209 /* P9 */
98 0x0302020b /* NUMERIC_POUND */
99 0x00030067 /* UP */
100 0x0103006a /* RIGHT */
101 0x0203006c /* DOWN */
102 0x03030069>; /* LEFT */
103 };
104
105 backlight {
106 compatible = "pwm-backlight";
107 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
108 brightness-levels = <0 51 53 56 62 75 101 152 255>;
109 default-brightness-level = <8>;
110 };
111};
112
113&am43xx_pinmux {
73 cpsw_default: cpsw_default { 114 cpsw_default: cpsw_default {
74 pinctrl-single,pins = < 115 pinctrl-single,pins = <
75 /* Slave 1 */ 116 /* Slave 1 */
@@ -279,47 +320,6 @@
279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 320 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
280 >; 321 >;
281 }; 322 };
282 };
283
284 matrix_keypad: matrix_keypad@0 {
285 compatible = "gpio-matrix-keypad";
286 debounce-delay-ms = <5>;
287 col-scan-delay-us = <2>;
288
289 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
290 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
291 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
292 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
293
294 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
295 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
296 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
297 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
298
299 linux,keymap = <0x00000201 /* P1 */
300 0x01000204 /* P4 */
301 0x02000207 /* P7 */
302 0x0300020a /* NUMERIC_STAR */
303 0x00010202 /* P2 */
304 0x01010205 /* P5 */
305 0x02010208 /* P8 */
306 0x03010200 /* P0 */
307 0x00020203 /* P3 */
308 0x01020206 /* P6 */
309 0x02020209 /* P9 */
310 0x0302020b /* NUMERIC_POUND */
311 0x00030067 /* UP */
312 0x0103006a /* RIGHT */
313 0x0203006c /* DOWN */
314 0x03030069>; /* LEFT */
315 };
316
317 backlight {
318 compatible = "pwm-backlight";
319 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
320 brightness-levels = <0 51 53 56 62 75 101 152 255>;
321 default-brightness-level = <8>;
322 };
323}; 323};
324 324
325&mmc1 { 325&mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..44869aa72642 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af3b49a..31497a45afb0 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -87,6 +87,7 @@
87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; 87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
88 gpio-fan,speed-map = <0 0>, 88 gpio-fan,speed-map = <0 0>,
89 <13000 1>; 89 <13000 1>;
90 #cooling-cells = <2>;
90 }; 91 };
91 92
92 extcon_usb1: extcon_usb1 { 93 extcon_usb1: extcon_usb1 {
@@ -442,6 +443,7 @@
442 pinctrl-0 = <&tmp102_pins_default>; 443 pinctrl-0 = <&tmp102_pins_default>;
443 interrupt-parent = <&gpio7>; 444 interrupt-parent = <&gpio7>;
444 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 445 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
446 #thermal-sensor-cells = <1>;
445 }; 447 };
446}; 448};
447 449
@@ -549,14 +551,53 @@
549 pinctrl-0 = <&usb1_pins>; 551 pinctrl-0 = <&usb1_pins>;
550}; 552};
551 553
552&omap_dwc3_1 { 554&usb2 {
553 extcon = <&extcon_usb1>; 555 dr_mode = "peripheral";
554}; 556};
555 557
556&omap_dwc3_2 { 558&cpu_trips {
557 extcon = <&extcon_usb2>; 559 cpu_alert1: cpu_alert1 {
560 temperature = <50000>; /* millicelsius */
561 hysteresis = <2000>; /* millicelsius */
562 type = "active";
563 };
558}; 564};
559 565
560&usb2 { 566&cpu_cooling_maps {
561 dr_mode = "peripheral"; 567 map1 {
568 trip = <&cpu_alert1>;
569 cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
570 };
571};
572
573&thermal_zones {
574 board_thermal: board_thermal {
575 polling-delay-passive = <1250>; /* milliseconds */
576 polling-delay = <1500>; /* milliseconds */
577
578 /* sensor ID */
579 thermal-sensors = <&tmp102 0>;
580
581 board_trips: trips {
582 board_alert0: board_alert {
583 temperature = <40000>; /* millicelsius */
584 hysteresis = <2000>; /* millicelsius */
585 type = "active";
586 };
587
588 board_crit: board_crit {
589 temperature = <105000>; /* millicelsius */
590 hysteresis = <0>; /* millicelsius */
591 type = "critical";
592 };
593 };
594
595 board_cooling_maps: cooling-maps {
596 map0 {
597 trip = <&board_alert0>;
598 cooling-device =
599 <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
600 };
601 };
602 };
562}; 603};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 857d0289ad4d..d3a29c1b8417 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -35,6 +35,18 @@
35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ 35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
36 >; 36 >;
37 }; 37 };
38
39 usb0_pins: pinmux_usb0_pins {
40 pinctrl-single,pins = <
41 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
42 >;
43 };
44
45 usb1_pins: pinmux_usb0_pins {
46 pinctrl-single,pins = <
47 DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */
48 >;
49 };
38}; 50};
39 51
40&i2c1 { 52&i2c1 {
@@ -127,3 +139,16 @@
127&mmc1 { 139&mmc1 {
128 vmmc-supply = <&vmmcsd_fixed>; 140 vmmc-supply = <&vmmcsd_fixed>;
129}; 141};
142
143/* At least dm8168-evm rev c won't support multipoint, later may */
144&usb0 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&usb0_pins>;
147 mentor,multipoint = <0>;
148};
149
150&usb1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&usb1_pins>;
153 mentor,multipoint = <0>;
154};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index d98d0f7de380..3c97b5f2addc 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -97,10 +97,31 @@
97 97
98 /* Device Configuration Registers */ 98 /* Device Configuration Registers */
99 scm_conf: syscon@600 { 99 scm_conf: syscon@600 {
100 compatible = "syscon"; 100 compatible = "syscon", "simple-bus";
101 reg = <0x600 0x110>; 101 reg = <0x600 0x110>;
102 #address-cells = <1>; 102 #address-cells = <1>;
103 #size-cells = <1>; 103 #size-cells = <1>;
104 ranges = <0 0x600 0x110>;
105
106 usb_phy0: usb-phy@20 {
107 compatible = "ti,dm8168-usb-phy";
108 reg = <0x20 0x8>;
109 reg-names = "phy";
110 clocks = <&main_fapll 6>;
111 clock-names = "refclk";
112 #phy-cells = <0>;
113 syscon = <&scm_conf>;
114 };
115
116 usb_phy1: usb-phy@28 {
117 compatible = "ti,dm8168-usb-phy";
118 reg = <0x28 0x8>;
119 reg-names = "phy";
120 clocks = <&main_fapll 6>;
121 clock-names = "refclk";
122 #phy-cells = <0>;
123 syscon = <&scm_conf>;
124 };
104 }; 125 };
105 126
106 scrm_clocks: clocks { 127 scrm_clocks: clocks {
@@ -357,7 +378,10 @@
357 reg-names = "mc", "control"; 378 reg-names = "mc", "control";
358 interrupts = <18>; 379 interrupts = <18>;
359 interrupt-names = "mc"; 380 interrupt-names = "mc";
360 dr_mode = "otg"; 381 dr_mode = "host";
382 interface-type = <0>;
383 phys = <&usb_phy0>;
384 phy-names = "usb2-phy";
361 mentor,multipoint = <1>; 385 mentor,multipoint = <1>;
362 mentor,num-eps = <16>; 386 mentor,num-eps = <16>;
363 mentor,ram-bits = <12>; 387 mentor,ram-bits = <12>;
@@ -366,13 +390,15 @@
366 390
367 usb1: usb@47401800 { 391 usb1: usb@47401800 {
368 compatible = "ti,musb-am33xx"; 392 compatible = "ti,musb-am33xx";
369 status = "disabled";
370 reg = <0x47401c00 0x400 393 reg = <0x47401c00 0x400
371 0x47401800 0x200>; 394 0x47401800 0x200>;
372 reg-names = "mc", "control"; 395 reg-names = "mc", "control";
373 interrupts = <19>; 396 interrupts = <19>;
374 interrupt-names = "mc"; 397 interrupt-names = "mc";
375 dr_mode = "otg"; 398 dr_mode = "host";
399 interface-type = <0>;
400 phys = <&usb_phy1>;
401 phy-names = "usb2-phy";
376 mentor,multipoint = <1>; 402 mentor,multipoint = <1>;
377 mentor,num-eps = <16>; 403 mentor,num-eps = <16>;
378 mentor,ram-bits = <12>; 404 mentor,ram-bits = <12>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 746cddb1b8f5..3290a96ba586 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -543,14 +543,6 @@
543 }; 543 };
544}; 544};
545 545
546&omap_dwc3_1 {
547 extcon = <&extcon_usb1>;
548};
549
550&omap_dwc3_2 {
551 extcon = <&extcon_usb2>;
552};
553
554&usb1 { 546&usb1 {
555 dr_mode = "peripheral"; 547 dr_mode = "peripheral";
556 pinctrl-names = "default"; 548 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..ce3eb311da1e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,17 +94,101 @@
94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
96 96
97 prm: prm@4ae06000 { 97 l4_cfg: l4@4a000000 {
98 compatible = "ti,dra7-prm"; 98 compatible = "ti,dra7-l4-cfg", "simple-bus";
99 reg = <0x4ae06000 0x3000>; 99 #address-cells = <1>;
100 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 100 #size-cells = <1>;
101 ranges = <0 0x4a000000 0x22c000>;
101 102
102 prm_clocks: clocks { 103 scm: scm@2000 {
104 compatible = "ti,dra7-scm-core", "simple-bus";
105 reg = <0x2000 0x2000>;
103 #address-cells = <1>; 106 #address-cells = <1>;
104 #size-cells = <0>; 107 #size-cells = <1>;
108 ranges = <0 0x2000 0x2000>;
109
110 scm_conf: scm_conf@0 {
111 compatible = "syscon";
112 reg = <0x0 0x1400>;
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 pbias_regulator: pbias_regulator {
117 compatible = "ti,pbias-omap";
118 reg = <0xe00 0x4>;
119 syscon = <&scm_conf>;
120 pbias_mmc_reg: pbias_mmc_omap5 {
121 regulator-name = "pbias_mmc_omap5";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <3000000>;
124 };
125 };
126 };
127
128 dra7_pmx_core: pinmux@1400 {
129 compatible = "ti,dra7-padconf",
130 "pinctrl-single";
131 reg = <0x1400 0x0464>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 #interrupt-cells = <1>;
135 interrupt-controller;
136 pinctrl-single,register-width = <32>;
137 pinctrl-single,function-mask = <0x3fffffff>;
138 };
139 };
140
141 cm_core_aon: cm_core_aon@5000 {
142 compatible = "ti,dra7-cm-core-aon";
143 reg = <0x5000 0x2000>;
144
145 cm_core_aon_clocks: clocks {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 };
149
150 cm_core_aon_clockdomains: clockdomains {
151 };
152 };
153
154 cm_core: cm_core@8000 {
155 compatible = "ti,dra7-cm-core";
156 reg = <0x8000 0x3000>;
157
158 cm_core_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 cm_core_clockdomains: clockdomains {
164 };
105 }; 165 };
166 };
106 167
107 prm_clockdomains: clockdomains { 168 l4_wkup: l4@4ae00000 {
169 compatible = "ti,dra7-l4-wkup", "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x4ae00000 0x3f000>;
173
174 counter32k: counter@4000 {
175 compatible = "ti,omap-counter32k";
176 reg = <0x4000 0x40>;
177 ti,hwmods = "counter_32k";
178 };
179
180 prm: prm@6000 {
181 compatible = "ti,dra7-prm";
182 reg = <0x6000 0x3000>;
183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
184
185 prm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 prm_clockdomains: clockdomains {
191 };
108 }; 192 };
109 }; 193 };
110 194
@@ -177,36 +261,16 @@
177 }; 261 };
178 }; 262 };
179 263
180 cm_core_aon: cm_core_aon@4a005000 { 264 bandgap: bandgap@4a0021e0 {
181 compatible = "ti,dra7-cm-core-aon"; 265 reg = <0x4a0021e0 0xc
182 reg = <0x4a005000 0x2000>; 266 0x4a00232c 0xc
183 267 0x4a002380 0x2c
184 cm_core_aon_clocks: clocks { 268 0x4a0023C0 0x3c
185 #address-cells = <1>; 269 0x4a002564 0x8
186 #size-cells = <0>; 270 0x4a002574 0x50>;
187 }; 271 compatible = "ti,dra752-bandgap";
188 272 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
189 cm_core_aon_clockdomains: clockdomains { 273 #thermal-sensor-cells = <1>;
190 };
191 };
192
193 cm_core: cm_core@4a008000 {
194 compatible = "ti,dra7-cm-core";
195 reg = <0x4a008000 0x3000>;
196
197 cm_core_clocks: clocks {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 cm_core_clockdomains: clockdomains {
203 };
204 };
205
206 counter32k: counter@4ae04000 {
207 compatible = "ti,omap-counter32k";
208 reg = <0x4ae04000 0x40>;
209 ti,hwmods = "counter_32k";
210 }; 274 };
211 275
212 dra7_ctrl_core: ctrl_core@4a002000 { 276 dra7_ctrl_core: ctrl_core@4a002000 {
@@ -219,28 +283,6 @@
219 reg = <0x4a002e00 0x7c>; 283 reg = <0x4a002e00 0x7c>;
220 }; 284 };
221 285
222 pbias_regulator: pbias_regulator {
223 compatible = "ti,pbias-omap";
224 reg = <0 0x4>;
225 syscon = <&dra7_ctrl_general>;
226 pbias_mmc_reg: pbias_mmc_omap5 {
227 regulator-name = "pbias_mmc_omap5";
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3000000>;
230 };
231 };
232
233 dra7_pmx_core: pinmux@4a003400 {
234 compatible = "ti,dra7-padconf", "pinctrl-single";
235 reg = <0x4a003400 0x0464>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 #interrupt-cells = <1>;
239 interrupt-controller;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0x3fffffff>;
242 };
243
244 sdma: dma-controller@4a056000 { 286 sdma: dma-controller@4a056000 {
245 compatible = "ti,omap4430-sdma"; 287 compatible = "ti,omap4430-sdma";
246 reg = <0x4a056000 0x1000>; 288 reg = <0x4a056000 0x1000>;
@@ -249,8 +291,8 @@
249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 292 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
251 #dma-cells = <1>; 293 #dma-cells = <1>;
252 #dma-channels = <32>; 294 dma-channels = <32>;
253 #dma-requests = <127>; 295 dma-requests = <127>;
254 }; 296 };
255 297
256 gpio1: gpio@4ae10000 { 298 gpio1: gpio@4ae10000 {
@@ -1090,8 +1132,8 @@
1090 <0x4A096800 0x40>; /* pll_ctrl */ 1132 <0x4A096800 0x40>; /* pll_ctrl */
1091 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1133 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1092 ctrl-module = <&omap_control_sata>; 1134 ctrl-module = <&omap_control_sata>;
1093 clocks = <&sys_clkin1>; 1135 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1094 clock-names = "sysclk"; 1136 clock-names = "sysclk", "refclk";
1095 #phy-cells = <0>; 1137 #phy-cells = <0>;
1096 }; 1138 };
1097 1139
@@ -1410,7 +1452,7 @@
1410 compatible = "ti,dra7-d_can"; 1452 compatible = "ti,dra7-d_can";
1411 ti,hwmods = "dcan1"; 1453 ti,hwmods = "dcan1";
1412 reg = <0x4ae3c000 0x2000>; 1454 reg = <0x4ae3c000 0x2000>;
1413 syscon-raminit = <&dra7_ctrl_core 0x558 0>; 1455 syscon-raminit = <&scm_conf 0x558 0>;
1414 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1456 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&dcan1_sys_clk_mux>; 1457 clocks = <&dcan1_sys_clk_mux>;
1416 status = "disabled"; 1458 status = "disabled";
@@ -1420,12 +1462,23 @@
1420 compatible = "ti,dra7-d_can"; 1462 compatible = "ti,dra7-d_can";
1421 ti,hwmods = "dcan2"; 1463 ti,hwmods = "dcan2";
1422 reg = <0x48480000 0x2000>; 1464 reg = <0x48480000 0x2000>;
1423 syscon-raminit = <&dra7_ctrl_core 0x558 1>; 1465 syscon-raminit = <&scm_conf 0x558 1>;
1424 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1466 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&sys_clkin1>; 1467 clocks = <&sys_clkin1>;
1426 status = "disabled"; 1468 status = "disabled";
1427 }; 1469 };
1428 }; 1470 };
1471
1472 thermal_zones: thermal-zones {
1473 #include "omap4-cpu-thermal.dtsi"
1474 #include "omap5-gpu-thermal.dtsi"
1475 #include "omap5-core-thermal.dtsi"
1476 };
1477
1478};
1479
1480&cpu_thermal {
1481 polling-delay = <500>; /* milliseconds */
1429}; 1482};
1430 1483
1431/include/ "dra7xx-clocks.dtsi" 1484/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 4d8711713610..e0264d0bf7b9 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -380,14 +380,6 @@
380 phy-supply = <&ldo4_reg>; 380 phy-supply = <&ldo4_reg>;
381}; 381};
382 382
383&omap_dwc3_1 {
384 extcon = <&extcon_usb1>;
385};
386
387&omap_dwc3_2 {
388 extcon = <&extcon_usb2>;
389};
390
391&usb1 { 383&usb1 {
392 dr_mode = "peripheral"; 384 dr_mode = "peripheral";
393 pinctrl-names = "default"; 385 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..6ac8e3601499 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
20 device_type = "cpu"; 20 device_type = "cpu";
21 compatible = "arm,cortex-a15"; 21 compatible = "arm,cortex-a15";
22 reg = <0>; 22 reg = <0>;
23
24 /* cooling options */
25 cooling-min-level = <0>;
26 cooling-max-level = <2>;
27 #cooling-cells = <2>; /* min followed by max */
23 }; 28 };
24 }; 29 };
25 30
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..eef981f4bcd5 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
31 clock-names = "cpu"; 31 clock-names = "cpu";
32 32
33 clock-latency = <300000>; /* From omap-cpufreq driver */ 33 clock-latency = <300000>; /* From omap-cpufreq driver */
34
35 /* cooling options */
36 cooling-min-level = <0>;
37 cooling-max-level = <2>;
38 #cooling-cells = <2>; /* min followed by max */
34 }; 39 };
35 cpu@1 { 40 cpu@1 {
36 device_type = "cpu"; 41 device_type = "cpu";
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 59d1c297bb30..578fa2a54dce 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -87,8 +87,8 @@
87 <14>, 87 <14>,
88 <15>; 88 <15>;
89 #dma-cells = <1>; 89 #dma-cells = <1>;
90 #dma-channels = <32>; 90 dma-channels = <32>;
91 #dma-requests = <64>; 91 dma-requests = <64>;
92 }; 92 };
93 93
94 i2c1: i2c@48070000 { 94 i2c1: i2c@48070000 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@48008000 { 17 l4: l4@48000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4", "simple-bus";
19 reg = <0x48008000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@8000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x8000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
30 };
29 31
30 scrm: scrm@48000000 { 32 prcm_clockdomains: clockdomains {
31 compatible = "ti,omap2-scrm"; 33 };
32 reg = <0x48000000 0x1000>; 34 };
33 35
34 scrm_clocks: clocks { 36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
35 #address-cells = <1>; 39 #address-cells = <1>;
36 #size-cells = <0>; 40 #size-cells = <1>;
41 ranges = <0 0x0 0x1000>;
42
43 omap2420_pmx: pinmux@30 {
44 compatible = "ti,omap2420-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0113>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x100>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63 };
64
65 scm_clockdomains: clockdomains {
66 };
37 }; 67 };
38 68
39 scrm_clockdomains: clockdomains { 69 counter32k: counter@4000 {
70 compatible = "ti,omap-counter32k";
71 reg = <0x4000 0x20>;
72 ti,hwmods = "counter_32k";
40 }; 73 };
41 }; 74 };
42 75
43 counter32k: counter@48004000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x48004000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2420_pmx: pinmux@48000030 {
50 compatible = "ti,omap2420-padconf", "pinctrl-single";
51 reg = <0x48000030 0x0113>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 gpio1: gpio@48018000 { 76 gpio1: gpio@48018000 {
59 compatible = "ti,omap2-gpio"; 77 compatible = "ti,omap2-gpio";
60 reg = <0x48018000 0x200>; 78 reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11&scrm_clocks { 11&scm_clocks {
12 mcbsp3_mux_fck: mcbsp3_mux_fck { 12 mcbsp3_mux_fck: mcbsp3_mux_fck {
13 #clock-cells = <0>; 13 #clock-cells = <0>;
14 compatible = "ti,composite-mux-clock"; 14 compatible = "ti,composite-mux-clock";
15 clocks = <&func_96m_ck>, <&mcbsp_clks>; 15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
16 reg = <0x02e8>; 16 reg = <0x78>;
17 }; 17 };
18 18
19 mcbsp3_fck: mcbsp3_fck { 19 mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <2>; 29 ti,bit-shift = <2>;
30 reg = <0x02e8>; 30 reg = <0x78>;
31 }; 31 };
32 32
33 mcbsp4_fck: mcbsp4_fck { 33 mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
41 compatible = "ti,composite-mux-clock"; 41 compatible = "ti,composite-mux-clock";
42 clocks = <&func_96m_ck>, <&mcbsp_clks>; 42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
43 ti,bit-shift = <4>; 43 ti,bit-shift = <4>;
44 reg = <0x02e8>; 44 reg = <0x78>;
45 }; 45 };
46 46
47 mcbsp5_fck: mcbsp5_fck { 47 mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@49006000 { 17 l4_wkup: l4_wkup@49000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4-wkup", "simple-bus";
19 reg = <0x49006000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x49000000 0x31000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@6000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x6000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
29 30 };
30 scrm: scrm@49002000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x49002000 0x1000>;
33 31
34 scrm_clocks: clocks { 32 prcm_clockdomains: clockdomains {
35 #address-cells = <1>; 33 };
36 #size-cells = <0>;
37 }; 34 };
38 35
39 scrm_clockdomains: clockdomains { 36 scm: scm@2000 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x2000 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges = <0 0x2000 0x1000>;
42
43 omap2430_pmx: pinmux@30 {
44 compatible = "ti,omap2430-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0154>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x240>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63
64 pbias_regulator: pbias_regulator {
65 compatible = "ti,pbias-omap";
66 reg = <0x230 0x4>;
67 syscon = <&scm_conf>;
68 pbias_mmc_reg: pbias_mmc_omap2430 {
69 regulator-name = "pbias_mmc_omap2430";
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3000000>;
72 };
73 };
74 };
75
76 scm_clockdomains: clockdomains {
77 };
40 }; 78 };
41 };
42
43 counter32k: counter@49020000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x49020000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2430_pmx: pinmux@49002030 {
50 compatible = "ti,omap2430-padconf", "pinctrl-single";
51 reg = <0x49002030 0x0154>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 omap2_scm_general: tisyscon@49002270 {
59 compatible = "syscon";
60 reg = <0x49002270 0x240>;
61 };
62 79
63 pbias_regulator: pbias_regulator { 80 counter32k: counter@20000 {
64 compatible = "ti,pbias-omap"; 81 compatible = "ti,omap-counter32k";
65 reg = <0x230 0x4>; 82 reg = <0x20000 0x20>;
66 syscon = <&omap2_scm_general>; 83 ti,hwmods = "counter_32k";
67 pbias_mmc_reg: pbias_mmc_omap2430 {
68 regulator-name = "pbias_mmc_omap2430";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3000000>;
71 }; 84 };
72 }; 85 };
73 86
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 mcbsp1_mux_fck: mcbsp1_mux_fck { 11 mcbsp1_mux_fck: mcbsp1_mux_fck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,composite-mux-clock"; 13 compatible = "ti,composite-mux-clock";
14 clocks = <&func_96m_ck>, <&mcbsp_clks>; 14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
15 ti,bit-shift = <2>; 15 ti,bit-shift = <2>;
16 reg = <0x0274>; 16 reg = <0x4>;
17 }; 17 };
18 18
19 mcbsp1_fck: mcbsp1_fck { 19 mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <6>; 29 ti,bit-shift = <6>;
30 reg = <0x0274>; 30 reg = <0x4>;
31 }; 31 };
32 32
33 mcbsp2_fck: mcbsp2_fck { 33 mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 60403273f83e..db80f9d376fa 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -16,6 +16,13 @@
16 model = "Nokia N900"; 16 model = "Nokia N900";
17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; 17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
18 18
19 aliases {
20 i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 };
25
19 cpus { 26 cpus {
20 cpu@0 { 27 cpu@0 {
21 cpu0-supply = <&vcc>; 28 cpu0-supply = <&vcc>;
@@ -704,7 +711,7 @@
704 compatible = "smsc,lan91c94"; 711 compatible = "smsc,lan91c94";
705 interrupt-parent = <&gpio2>; 712 interrupt-parent = <&gpio2>;
706 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 713 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
707 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 714 reg = <1 0 0xf>; /* 16 byte IO range */
708 bank-width = <2>; 715 bank-width = <2>;
709 pinctrl-names = "default"; 716 pinctrl-names = "default";
710 pinctrl-0 = <&ethernet_pins>; 717 pinctrl-0 = <&ethernet_pins>;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 01b71111bd55..02cd996d0b06 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
87 ranges; 87 ranges;
88 ti,hwmods = "l3_main"; 88 ti,hwmods = "l3_main";
89 89
90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
113 };
114
115 scm_conf: scm_conf@270 {
116 compatible = "syscon";
117 reg = <0x270 0x330>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120
121 scm_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 };
126
127 scm_clockdomains: clockdomains {
128 };
129
130 omap3_pmx_wkup: pinmux@a00 {
131 compatible = "ti,omap3-padconf",
132 "pinctrl-single";
133 reg = <0xa00 0x5c>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;
138 pinctrl-single,register-width = <16>;
139 pinctrl-single,function-mask = <0xff1f>;
140 };
141 };
142 };
143
90 aes: aes@480c5000 { 144 aes: aes@480c5000 {
91 compatible = "ti,omap3-aes"; 145 compatible = "ti,omap3-aes";
92 ti,hwmods = "aes"; 146 ti,hwmods = "aes";
@@ -121,19 +175,6 @@
121 }; 175 };
122 }; 176 };
123 177
124 scrm: scrm@48002000 {
125 compatible = "ti,omap3-scrm";
126 reg = <0x48002000 0x2000>;
127
128 scrm_clocks: clocks {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
133 scrm_clockdomains: clockdomains {
134 };
135 };
136
137 counter32k: counter@48320000 { 178 counter32k: counter@48320000 {
138 compatible = "ti,omap-counter32k"; 179 compatible = "ti,omap-counter32k";
139 reg = <0x48320000 0x20>; 180 reg = <0x48320000 0x20>;
@@ -155,41 +196,14 @@
155 <14>, 196 <14>,
156 <15>; 197 <15>;
157 #dma-cells = <1>; 198 #dma-cells = <1>;
158 #dma-channels = <32>; 199 dma-channels = <32>;
159 #dma-requests = <96>; 200 dma-requests = <96>;
160 };
161
162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
164 reg = <0x48002030 0x0238>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 #interrupt-cells = <1>;
168 interrupt-controller;
169 pinctrl-single,register-width = <16>;
170 pinctrl-single,function-mask = <0xff1f>;
171 };
172
173 omap3_pmx_wkup: pinmux@48002a00 {
174 compatible = "ti,omap3-padconf", "pinctrl-single";
175 reg = <0x48002a00 0x5c>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0xff1f>;
182 };
183
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
187 }; 201 };
188 202
189 pbias_regulator: pbias_regulator { 203 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap"; 204 compatible = "ti,pbias-omap";
191 reg = <0x2b0 0x4>; 205 reg = <0x2b0 0x4>;
192 syscon = <&omap3_scm_general>; 206 syscon = <&scm_conf>;
193 pbias_mmc_reg: pbias_mmc_omap2430 { 207 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430"; 208 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>; 209 regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
79 clock-div = <1>; 79 clock-div = <1>;
80 }; 80 };
81}; 81};
82&scrm_clocks { 82
83&scm_clocks {
83 mcbsp5_mux_fck: mcbsp5_mux_fck { 84 mcbsp5_mux_fck: mcbsp5_mux_fck {
84 #clock-cells = <0>; 85 #clock-cells = <0>;
85 compatible = "ti,composite-mux-clock"; 86 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>; 87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
87 ti,bit-shift = <4>; 88 ti,bit-shift = <4>;
88 reg = <0x02d8>; 89 reg = <0x68>;
89 }; 90 };
90 91
91 mcbsp5_fck: mcbsp5_fck { 92 mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
99 compatible = "ti,composite-mux-clock"; 100 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>; 101 clocks = <&core_96m_fck>, <&mcbsp_clks>;
101 ti,bit-shift = <2>; 102 ti,bit-shift = <2>;
102 reg = <0x0274>; 103 reg = <0x04>;
103 }; 104 };
104 105
105 mcbsp1_fck: mcbsp1_fck { 106 mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
113 compatible = "ti,composite-mux-clock"; 114 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>; 115 clocks = <&per_96m_fck>, <&mcbsp_clks>;
115 ti,bit-shift = <6>; 116 ti,bit-shift = <6>;
116 reg = <0x0274>; 117 reg = <0x04>;
117 }; 118 };
118 119
119 mcbsp2_fck: mcbsp2_fck { 120 mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
126 #clock-cells = <0>; 127 #clock-cells = <0>;
127 compatible = "ti,composite-mux-clock"; 128 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>; 129 clocks = <&per_96m_fck>, <&mcbsp_clks>;
129 reg = <0x02d8>; 130 reg = <0x68>;
130 }; 131 };
131 132
132 mcbsp3_fck: mcbsp3_fck { 133 mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
140 compatible = "ti,composite-mux-clock"; 141 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>; 142 clocks = <&per_96m_fck>, <&mcbsp_clks>;
142 ti,bit-shift = <2>; 143 ti,bit-shift = <2>;
143 reg = <0x02d8>; 144 reg = <0x68>;
144 }; 145 };
145 146
146 mcbsp4_fck: mcbsp4_fck { 147 mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index cb9458feb2e3..ab7f87ae96f0 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal {
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 0>; 19 thermal-sensors = <&bandgap 0>;
20 20
21 trips { 21 cpu_trips: trips {
22 cpu_alert0: cpu_alert { 22 cpu_alert0: cpu_alert {
23 temperature = <100000>; /* millicelsius */ 23 temperature = <100000>; /* millicelsius */
24 hysteresis = <2000>; /* millicelsius */ 24 hysteresis = <2000>; /* millicelsius */
@@ -31,7 +31,7 @@ cpu_thermal: cpu_thermal {
31 }; 31 };
32 }; 32 };
33 33
34 cooling-maps { 34 cpu_cooling_maps: cooling-maps {
35 map0 { 35 map0 {
36 trip = <&cpu_alert0>; 36 trip = <&cpu_alert0>;
37 cooling-device = 37 cooling-device =
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..cf2681b2d173 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -114,99 +114,141 @@
114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
116 116
117 cm1: cm1@4a004000 { 117 l4_cfg: l4@4a000000 {
118 compatible = "ti,omap4-cm1"; 118 compatible = "ti,omap4-l4-cfg", "simple-bus";
119 reg = <0x4a004000 0x2000>; 119 #address-cells = <1>;
120 120 #size-cells = <1>;
121 cm1_clocks: clocks { 121 ranges = <0 0x4a000000 0x1000000>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 122
126 cm1_clockdomains: clockdomains { 123 cm1: cm1@4000 {
127 }; 124 compatible = "ti,omap4-cm1";
128 }; 125 reg = <0x4000 0x2000>;
129 126
130 prm: prm@4a306000 { 127 cm1_clocks: clocks {
131 compatible = "ti,omap4-prm"; 128 #address-cells = <1>;
132 reg = <0x4a306000 0x3000>; 129 #size-cells = <0>;
133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 130 };
134 131
135 prm_clocks: clocks { 132 cm1_clockdomains: clockdomains {
136 #address-cells = <1>; 133 };
137 #size-cells = <0>;
138 }; 134 };
139 135
140 prm_clockdomains: clockdomains { 136 cm2: cm2@8000 {
141 }; 137 compatible = "ti,omap4-cm2";
142 }; 138 reg = <0x8000 0x3000>;
143 139
144 cm2: cm2@4a008000 { 140 cm2_clocks: clocks {
145 compatible = "ti,omap4-cm2"; 141 #address-cells = <1>;
146 reg = <0x4a008000 0x3000>; 142 #size-cells = <0>;
143 };
147 144
148 cm2_clocks: clocks { 145 cm2_clockdomains: clockdomains {
149 #address-cells = <1>; 146 };
150 #size-cells = <0>;
151 }; 147 };
152 148
153 cm2_clockdomains: clockdomains { 149 omap4_scm_core: scm@2000 {
150 compatible = "ti,omap4-scm-core", "simple-bus";
151 reg = <0x2000 0x1000>;
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0 0x2000 0x1000>;
155
156 scm_conf: scm_conf@0 {
157 compatible = "syscon";
158 reg = <0x0 0x800>;
159 #address-cells = <1>;
160 #size-cells = <1>;
161 };
154 }; 162 };
155 };
156
157 scrm: scrm@4a30a000 {
158 compatible = "ti,omap4-scrm";
159 reg = <0x4a30a000 0x2000>;
160 163
161 scrm_clocks: clocks { 164 omap4_padconf_core: scm@100000 {
165 compatible = "ti,omap4-scm-padconf-core",
166 "simple-bus";
162 #address-cells = <1>; 167 #address-cells = <1>;
163 #size-cells = <0>; 168 #size-cells = <1>;
169 ranges = <0 0x100000 0x1000>;
170
171 omap4_pmx_core: pinmux@40 {
172 compatible = "ti,omap4-padconf",
173 "pinctrl-single";
174 reg = <0x40 0x0196>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 #interrupt-cells = <1>;
178 interrupt-controller;
179 pinctrl-single,register-width = <16>;
180 pinctrl-single,function-mask = <0x7fff>;
181 };
182
183 omap4_padconf_global: omap4_padconf_global@5a0 {
184 compatible = "syscon";
185 reg = <0x5a0 0x170>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
191 reg = <0x60 0x4>;
192 syscon = <&omap4_padconf_global>;
193 pbias_mmc_reg: pbias_mmc_omap4 {
194 regulator-name = "pbias_mmc_omap4";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
197 };
198 };
199 };
164 }; 200 };
165 201
166 scrm_clockdomains: clockdomains { 202 l4_wkup: l4@300000 {
167 }; 203 compatible = "ti,omap4-l4-wkup", "simple-bus";
168 }; 204 #address-cells = <1>;
169 205 #size-cells = <1>;
170 counter32k: counter@4a304000 { 206 ranges = <0 0x300000 0x40000>;
171 compatible = "ti,omap-counter32k"; 207
172 reg = <0x4a304000 0x20>; 208 counter32k: counter@4000 {
173 ti,hwmods = "counter_32k"; 209 compatible = "ti,omap-counter32k";
174 }; 210 reg = <0x4000 0x20>;
175 211 ti,hwmods = "counter_32k";
176 omap4_pmx_core: pinmux@4a100040 { 212 };
177 compatible = "ti,omap4-padconf", "pinctrl-single"; 213
178 reg = <0x4a100040 0x0196>; 214 prm: prm@6000 {
179 #address-cells = <1>; 215 compatible = "ti,omap4-prm";
180 #size-cells = <0>; 216 reg = <0x6000 0x3000>;
181 #interrupt-cells = <1>; 217 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
182 interrupt-controller; 218
183 pinctrl-single,register-width = <16>; 219 prm_clocks: clocks {
184 pinctrl-single,function-mask = <0x7fff>; 220 #address-cells = <1>;
185 }; 221 #size-cells = <0>;
186 omap4_pmx_wkup: pinmux@4a31e040 { 222 };
187 compatible = "ti,omap4-padconf", "pinctrl-single"; 223
188 reg = <0x4a31e040 0x0038>; 224 prm_clockdomains: clockdomains {
189 #address-cells = <1>; 225 };
190 #size-cells = <0>; 226 };
191 #interrupt-cells = <1>; 227
192 interrupt-controller; 228 scrm: scrm@a000 {
193 pinctrl-single,register-width = <16>; 229 compatible = "ti,omap4-scrm";
194 pinctrl-single,function-mask = <0x7fff>; 230 reg = <0xa000 0x2000>;
195 }; 231
196 232 scrm_clocks: clocks {
197 omap4_padconf_global: tisyscon@4a1005a0 { 233 #address-cells = <1>;
198 compatible = "syscon"; 234 #size-cells = <0>;
199 reg = <0x4a1005a0 0x170>; 235 };
200 }; 236
201 237 scrm_clockdomains: clockdomains {
202 pbias_regulator: pbias_regulator { 238 };
203 compatible = "ti,pbias-omap"; 239 };
204 reg = <0x60 0x4>; 240
205 syscon = <&omap4_padconf_global>; 241 omap4_pmx_wkup: pinmux@1e040 {
206 pbias_mmc_reg: pbias_mmc_omap4 { 242 compatible = "ti,omap4-padconf",
207 regulator-name = "pbias_mmc_omap4"; 243 "pinctrl-single";
208 regulator-min-microvolt = <1800000>; 244 reg = <0x1e040 0x0038>;
209 regulator-max-microvolt = <3000000>; 245 #address-cells = <1>;
246 #size-cells = <0>;
247 #interrupt-cells = <1>;
248 interrupt-controller;
249 pinctrl-single,register-width = <16>;
250 pinctrl-single,function-mask = <0x7fff>;
251 };
210 }; 252 };
211 }; 253 };
212 254
@@ -223,8 +265,8 @@
223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 266 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
225 #dma-cells = <1>; 267 #dma-cells = <1>;
226 #dma-channels = <32>; 268 dma-channels = <32>;
227 #dma-requests = <127>; 269 dma-requests = <127>;
228 }; 270 };
229 271
230 gpio1: gpio@4a310000 { 272 gpio1: gpio@4a310000 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..3cdb5c22148d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -129,99 +129,141 @@
129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
131 131
132 prm: prm@4ae06000 { 132 l4_cfg: l4@4a000000 {
133 compatible = "ti,omap5-prm"; 133 compatible = "ti,omap5-l4-cfg", "simple-bus";
134 reg = <0x4ae06000 0x3000>; 134 #address-cells = <1>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 135 #size-cells = <1>;
136 ranges = <0 0x4a000000 0x22a000>;
136 137
137 prm_clocks: clocks { 138 scm_core: scm@2000 {
139 compatible = "ti,omap5-scm-core", "simple-bus";
140 reg = <0x2000 0x1000>;
138 #address-cells = <1>; 141 #address-cells = <1>;
139 #size-cells = <0>; 142 #size-cells = <1>;
143 ranges = <0 0x2000 0x800>;
144
145 scm_conf: scm_conf@0 {
146 compatible = "syscon";
147 reg = <0x0 0x800>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 };
140 }; 151 };
141 152
142 prm_clockdomains: clockdomains { 153 scm_padconf_core: scm@2800 {
154 compatible = "ti,omap5-scm-padconf-core",
155 "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0x2800 0x800>;
159
160 omap5_pmx_core: pinmux@40 {
161 compatible = "ti,omap5-padconf",
162 "pinctrl-single";
163 reg = <0x40 0x01b6>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 #interrupt-cells = <1>;
167 interrupt-controller;
168 pinctrl-single,register-width = <16>;
169 pinctrl-single,function-mask = <0x7fff>;
170 };
171
172 omap5_padconf_global: omap5_padconf_global@5a0 {
173 compatible = "syscon";
174 reg = <0x5a0 0xec>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177
178 pbias_regulator: pbias_regulator {
179 compatible = "ti,pbias-omap";
180 reg = <0x60 0x4>;
181 syscon = <&omap5_padconf_global>;
182 pbias_mmc_reg: pbias_mmc_omap5 {
183 regulator-name = "pbias_mmc_omap5";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <3000000>;
186 };
187 };
188 };
143 }; 189 };
144 };
145 190
146 cm_core_aon: cm_core_aon@4a004000 { 191 cm_core_aon: cm_core_aon@4000 {
147 compatible = "ti,omap5-cm-core-aon"; 192 compatible = "ti,omap5-cm-core-aon";
148 reg = <0x4a004000 0x2000>; 193 reg = <0x4000 0x2000>;
149 194
150 cm_core_aon_clocks: clocks { 195 cm_core_aon_clocks: clocks {
151 #address-cells = <1>; 196 #address-cells = <1>;
152 #size-cells = <0>; 197 #size-cells = <0>;
153 }; 198 };
154 199
155 cm_core_aon_clockdomains: clockdomains { 200 cm_core_aon_clockdomains: clockdomains {
201 };
156 }; 202 };
157 };
158 203
159 scrm: scrm@4ae0a000 { 204 cm_core: cm_core@8000 {
160 compatible = "ti,omap5-scrm"; 205 compatible = "ti,omap5-cm-core";
161 reg = <0x4ae0a000 0x2000>; 206 reg = <0x8000 0x3000>;
162 207
163 scrm_clocks: clocks { 208 cm_core_clocks: clocks {
164 #address-cells = <1>; 209 #address-cells = <1>;
165 #size-cells = <0>; 210 #size-cells = <0>;
166 }; 211 };
167 212
168 scrm_clockdomains: clockdomains { 213 cm_core_clockdomains: clockdomains {
214 };
169 }; 215 };
170 }; 216 };
171 217
172 cm_core: cm_core@4a008000 { 218 l4_wkup: l4@4ae00000 {
173 compatible = "ti,omap5-cm-core"; 219 compatible = "ti,omap5-l4-wkup", "simple-bus";
174 reg = <0x4a008000 0x3000>; 220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0x4ae00000 0x2b000>;
175 223
176 cm_core_clocks: clocks { 224 counter32k: counter@4000 {
177 #address-cells = <1>; 225 compatible = "ti,omap-counter32k";
178 #size-cells = <0>; 226 reg = <0x4000 0x40>;
227 ti,hwmods = "counter_32k";
179 }; 228 };
180 229
181 cm_core_clockdomains: clockdomains { 230 prm: prm@6000 {
231 compatible = "ti,omap5-prm";
232 reg = <0x6000 0x3000>;
233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
234
235 prm_clocks: clocks {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 prm_clockdomains: clockdomains {
241 };
182 }; 242 };
183 };
184 243
185 counter32k: counter@4ae04000 { 244 scrm: scrm@a000 {
186 compatible = "ti,omap-counter32k"; 245 compatible = "ti,omap5-scrm";
187 reg = <0x4ae04000 0x40>; 246 reg = <0xa000 0x2000>;
188 ti,hwmods = "counter_32k";
189 };
190 247
191 omap5_pmx_core: pinmux@4a002840 { 248 scrm_clocks: clocks {
192 compatible = "ti,omap5-padconf", "pinctrl-single"; 249 #address-cells = <1>;
193 reg = <0x4a002840 0x01b6>; 250 #size-cells = <0>;
194 #address-cells = <1>; 251 };
195 #size-cells = <0>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
198 pinctrl-single,register-width = <16>;
199 pinctrl-single,function-mask = <0x7fff>;
200 };
201 omap5_pmx_wkup: pinmux@4ae0c840 {
202 compatible = "ti,omap5-padconf", "pinctrl-single";
203 reg = <0x4ae0c840 0x0038>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
208 pinctrl-single,register-width = <16>;
209 pinctrl-single,function-mask = <0x7fff>;
210 };
211 252
212 omap5_padconf_global: tisyscon@4a002da0 { 253 scrm_clockdomains: clockdomains {
213 compatible = "syscon"; 254 };
214 reg = <0x4A002da0 0xec>; 255 };
215 };
216 256
217 pbias_regulator: pbias_regulator { 257 omap5_pmx_wkup: pinmux@c840 {
218 compatible = "ti,pbias-omap"; 258 compatible = "ti,omap5-padconf",
219 reg = <0x60 0x4>; 259 "pinctrl-single";
220 syscon = <&omap5_padconf_global>; 260 reg = <0xc840 0x0038>;
221 pbias_mmc_reg: pbias_mmc_omap5 { 261 #address-cells = <1>;
222 regulator-name = "pbias_mmc_omap5"; 262 #size-cells = <0>;
223 regulator-min-microvolt = <1800000>; 263 #interrupt-cells = <1>;
224 regulator-max-microvolt = <3000000>; 264 interrupt-controller;
265 pinctrl-single,register-width = <16>;
266 pinctrl-single,function-mask = <0x7fff>;
225 }; 267 };
226 }; 268 };
227 269
@@ -238,8 +280,8 @@
238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 281 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
240 #dma-cells = <1>; 282 #dma-cells = <1>;
241 #dma-channels = <32>; 283 dma-channels = <32>;
242 #dma-requests = <127>; 284 dma-requests = <127>;
243 }; 285 };
244 286
245 gpio1: gpio@4ae10000 { 287 gpio1: gpio@4ae10000 {
@@ -929,8 +971,8 @@
929 <0x4A096800 0x40>; /* pll_ctrl */ 971 <0x4A096800 0x40>; /* pll_ctrl */
930 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 972 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
931 ctrl-module = <&omap_control_sata>; 973 ctrl-module = <&omap_control_sata>;
932 clocks = <&sys_clkin>; 974 clocks = <&sys_clkin>, <&sata_ref_clk>;
933 clock-names = "sysclk"; 975 clock-names = "sysclk", "refclk";
934 #phy-cells = <0>; 976 #phy-cells = <0>;
935 }; 977 };
936 }; 978 };
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e8a4c955241b..b7e6b6fba5e0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -62,6 +62,17 @@ CONFIG_MACH_SPEAR1340=y
62CONFIG_ARCH_STI=y 62CONFIG_ARCH_STI=y
63CONFIG_ARCH_EXYNOS=y 63CONFIG_ARCH_EXYNOS=y
64CONFIG_EXYNOS5420_MCPM=y 64CONFIG_EXYNOS5420_MCPM=y
65CONFIG_ARCH_SHMOBILE_MULTI=y
66CONFIG_ARCH_EMEV2=y
67CONFIG_ARCH_R7S72100=y
68CONFIG_ARCH_R8A73A4=y
69CONFIG_ARCH_R8A7740=y
70CONFIG_ARCH_R8A7779=y
71CONFIG_ARCH_R8A7790=y
72CONFIG_ARCH_R8A7791=y
73CONFIG_ARCH_R8A7794=y
74CONFIG_ARCH_SH73A0=y
75CONFIG_MACH_MARZEN=y
65CONFIG_ARCH_SUNXI=y 76CONFIG_ARCH_SUNXI=y
66CONFIG_ARCH_SIRF=y 77CONFIG_ARCH_SIRF=y
67CONFIG_ARCH_TEGRA=y 78CONFIG_ARCH_TEGRA=y
@@ -84,6 +95,8 @@ CONFIG_PCI_KEYSTONE=y
84CONFIG_PCI_MSI=y 95CONFIG_PCI_MSI=y
85CONFIG_PCI_MVEBU=y 96CONFIG_PCI_MVEBU=y
86CONFIG_PCI_TEGRA=y 97CONFIG_PCI_TEGRA=y
98CONFIG_PCI_RCAR_GEN2=y
99CONFIG_PCI_RCAR_GEN2_PCIE=y
87CONFIG_PCIEPORTBUS=y 100CONFIG_PCIEPORTBUS=y
88CONFIG_SMP=y 101CONFIG_SMP=y
89CONFIG_NR_CPUS=8 102CONFIG_NR_CPUS=8
@@ -130,6 +143,7 @@ CONFIG_DEVTMPFS_MOUNT=y
130CONFIG_DMA_CMA=y 143CONFIG_DMA_CMA=y
131CONFIG_CMA_SIZE_MBYTES=64 144CONFIG_CMA_SIZE_MBYTES=64
132CONFIG_OMAP_OCP2SCP=y 145CONFIG_OMAP_OCP2SCP=y
146CONFIG_SIMPLE_PM_BUS=y
133CONFIG_MTD=y 147CONFIG_MTD=y
134CONFIG_MTD_CMDLINE_PARTS=y 148CONFIG_MTD_CMDLINE_PARTS=y
135CONFIG_MTD_BLOCK=y 149CONFIG_MTD_BLOCK=y
@@ -157,6 +171,7 @@ CONFIG_AHCI_SUNXI=y
157CONFIG_AHCI_TEGRA=y 171CONFIG_AHCI_TEGRA=y
158CONFIG_SATA_HIGHBANK=y 172CONFIG_SATA_HIGHBANK=y
159CONFIG_SATA_MV=y 173CONFIG_SATA_MV=y
174CONFIG_SATA_RCAR=y
160CONFIG_NETDEVICES=y 175CONFIG_NETDEVICES=y
161CONFIG_HIX5HD2_GMAC=y 176CONFIG_HIX5HD2_GMAC=y
162CONFIG_SUN4I_EMAC=y 177CONFIG_SUN4I_EMAC=y
@@ -167,14 +182,17 @@ CONFIG_MV643XX_ETH=y
167CONFIG_MVNETA=y 182CONFIG_MVNETA=y
168CONFIG_KS8851=y 183CONFIG_KS8851=y
169CONFIG_R8169=y 184CONFIG_R8169=y
185CONFIG_SH_ETH=y
170CONFIG_SMSC911X=y 186CONFIG_SMSC911X=y
171CONFIG_STMMAC_ETH=y 187CONFIG_STMMAC_ETH=y
172CONFIG_TI_CPSW=y 188CONFIG_TI_CPSW=y
173CONFIG_XILINX_EMACLITE=y 189CONFIG_XILINX_EMACLITE=y
174CONFIG_AT803X_PHY=y 190CONFIG_AT803X_PHY=y
175CONFIG_MARVELL_PHY=y 191CONFIG_MARVELL_PHY=y
192CONFIG_SMSC_PHY=y
176CONFIG_BROADCOM_PHY=y 193CONFIG_BROADCOM_PHY=y
177CONFIG_ICPLUS_PHY=y 194CONFIG_ICPLUS_PHY=y
195CONFIG_MICREL_PHY=y
178CONFIG_USB_PEGASUS=y 196CONFIG_USB_PEGASUS=y
179CONFIG_USB_USBNET=y 197CONFIG_USB_USBNET=y
180CONFIG_USB_NET_SMSC75XX=y 198CONFIG_USB_NET_SMSC75XX=y
@@ -192,15 +210,18 @@ CONFIG_KEYBOARD_CROS_EC=y
192CONFIG_MOUSE_PS2_ELANTECH=y 210CONFIG_MOUSE_PS2_ELANTECH=y
193CONFIG_INPUT_TOUCHSCREEN=y 211CONFIG_INPUT_TOUCHSCREEN=y
194CONFIG_TOUCHSCREEN_ATMEL_MXT=y 212CONFIG_TOUCHSCREEN_ATMEL_MXT=y
213CONFIG_TOUCHSCREEN_ST1232=m
195CONFIG_TOUCHSCREEN_STMPE=y 214CONFIG_TOUCHSCREEN_STMPE=y
196CONFIG_TOUCHSCREEN_SUN4I=y 215CONFIG_TOUCHSCREEN_SUN4I=y
197CONFIG_INPUT_MISC=y 216CONFIG_INPUT_MISC=y
198CONFIG_INPUT_MPU3050=y 217CONFIG_INPUT_MPU3050=y
199CONFIG_INPUT_AXP20X_PEK=y 218CONFIG_INPUT_AXP20X_PEK=y
219CONFIG_INPUT_ADXL34X=m
200CONFIG_SERIO_AMBAKMI=y 220CONFIG_SERIO_AMBAKMI=y
201CONFIG_SERIAL_8250=y 221CONFIG_SERIAL_8250=y
202CONFIG_SERIAL_8250_CONSOLE=y 222CONFIG_SERIAL_8250_CONSOLE=y
203CONFIG_SERIAL_8250_DW=y 223CONFIG_SERIAL_8250_DW=y
224CONFIG_SERIAL_8250_EM=y
204CONFIG_SERIAL_8250_MT6577=y 225CONFIG_SERIAL_8250_MT6577=y
205CONFIG_SERIAL_AMBA_PL011=y 226CONFIG_SERIAL_AMBA_PL011=y
206CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 227CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -213,6 +234,9 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
213CONFIG_SERIAL_TEGRA=y 234CONFIG_SERIAL_TEGRA=y
214CONFIG_SERIAL_IMX=y 235CONFIG_SERIAL_IMX=y
215CONFIG_SERIAL_IMX_CONSOLE=y 236CONFIG_SERIAL_IMX_CONSOLE=y
237CONFIG_SERIAL_SH_SCI=y
238CONFIG_SERIAL_SH_SCI_NR_UARTS=20
239CONFIG_SERIAL_SH_SCI_CONSOLE=y
216CONFIG_SERIAL_MSM=y 240CONFIG_SERIAL_MSM=y
217CONFIG_SERIAL_MSM_CONSOLE=y 241CONFIG_SERIAL_MSM_CONSOLE=y
218CONFIG_SERIAL_VT8500=y 242CONFIG_SERIAL_VT8500=y
@@ -233,19 +257,26 @@ CONFIG_I2C_MUX_PCA954x=y
233CONFIG_I2C_MUX_PINCTRL=y 257CONFIG_I2C_MUX_PINCTRL=y
234CONFIG_I2C_CADENCE=y 258CONFIG_I2C_CADENCE=y
235CONFIG_I2C_DESIGNWARE_PLATFORM=y 259CONFIG_I2C_DESIGNWARE_PLATFORM=y
260CONFIG_I2C_GPIO=m
236CONFIG_I2C_EXYNOS5=y 261CONFIG_I2C_EXYNOS5=y
237CONFIG_I2C_MV64XXX=y 262CONFIG_I2C_MV64XXX=y
263CONFIG_I2C_RIIC=y
238CONFIG_I2C_S3C2410=y 264CONFIG_I2C_S3C2410=y
265CONFIG_I2C_SH_MOBILE=y
239CONFIG_I2C_SIRF=y 266CONFIG_I2C_SIRF=y
240CONFIG_I2C_TEGRA=y
241CONFIG_I2C_ST=y 267CONFIG_I2C_ST=y
242CONFIG_SPI=y 268CONFIG_I2C_TEGRA=y
243CONFIG_I2C_XILINX=y 269CONFIG_I2C_XILINX=y
244CONFIG_SPI_DAVINCI=y 270CONFIG_I2C_RCAR=y
271CONFIG_SPI=y
245CONFIG_SPI_CADENCE=y 272CONFIG_SPI_CADENCE=y
273CONFIG_SPI_DAVINCI=y
246CONFIG_SPI_OMAP24XX=y 274CONFIG_SPI_OMAP24XX=y
247CONFIG_SPI_ORION=y 275CONFIG_SPI_ORION=y
248CONFIG_SPI_PL022=y 276CONFIG_SPI_PL022=y
277CONFIG_SPI_RSPI=y
278CONFIG_SPI_SH_MSIOF=m
279CONFIG_SPI_SH_HSPI=y
249CONFIG_SPI_SIRF=y 280CONFIG_SPI_SIRF=y
250CONFIG_SPI_SUN4I=y 281CONFIG_SPI_SUN4I=y
251CONFIG_SPI_SUN6I=y 282CONFIG_SPI_SUN6I=y
@@ -259,12 +290,15 @@ CONFIG_PINCTRL_PALMAS=y
259CONFIG_PINCTRL_APQ8084=y 290CONFIG_PINCTRL_APQ8084=y
260CONFIG_GPIO_SYSFS=y 291CONFIG_GPIO_SYSFS=y
261CONFIG_GPIO_GENERIC_PLATFORM=y 292CONFIG_GPIO_GENERIC_PLATFORM=y
262CONFIG_GPIO_DWAPB=y
263CONFIG_GPIO_DAVINCI=y 293CONFIG_GPIO_DAVINCI=y
294CONFIG_GPIO_DWAPB=y
295CONFIG_GPIO_EM=y
296CONFIG_GPIO_RCAR=y
264CONFIG_GPIO_XILINX=y 297CONFIG_GPIO_XILINX=y
265CONFIG_GPIO_ZYNQ=y 298CONFIG_GPIO_ZYNQ=y
266CONFIG_GPIO_PCA953X=y 299CONFIG_GPIO_PCA953X=y
267CONFIG_GPIO_PCA953X_IRQ=y 300CONFIG_GPIO_PCA953X_IRQ=y
301CONFIG_GPIO_PCF857X=y
268CONFIG_GPIO_TWL4030=y 302CONFIG_GPIO_TWL4030=y
269CONFIG_GPIO_PALMAS=y 303CONFIG_GPIO_PALMAS=y
270CONFIG_GPIO_SYSCON=y 304CONFIG_GPIO_SYSCON=y
@@ -276,10 +310,12 @@ CONFIG_POWER_RESET_AS3722=y
276CONFIG_POWER_RESET_GPIO=y 310CONFIG_POWER_RESET_GPIO=y
277CONFIG_POWER_RESET_KEYSTONE=y 311CONFIG_POWER_RESET_KEYSTONE=y
278CONFIG_POWER_RESET_SUN6I=y 312CONFIG_POWER_RESET_SUN6I=y
313CONFIG_POWER_RESET_RMOBILE=y
279CONFIG_SENSORS_LM90=y 314CONFIG_SENSORS_LM90=y
280CONFIG_SENSORS_LM95245=y 315CONFIG_SENSORS_LM95245=y
281CONFIG_THERMAL=y 316CONFIG_THERMAL=y
282CONFIG_CPU_THERMAL=y 317CONFIG_CPU_THERMAL=y
318CONFIG_RCAR_THERMAL=y
283CONFIG_ARMADA_THERMAL=y 319CONFIG_ARMADA_THERMAL=y
284CONFIG_DAVINCI_WATCHDOG 320CONFIG_DAVINCI_WATCHDOG
285CONFIG_ST_THERMAL_SYSCFG=y 321CONFIG_ST_THERMAL_SYSCFG=y
@@ -290,6 +326,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
290CONFIG_ORION_WATCHDOG=y 326CONFIG_ORION_WATCHDOG=y
291CONFIG_SUNXI_WATCHDOG=y 327CONFIG_SUNXI_WATCHDOG=y
292CONFIG_MESON_WATCHDOG=y 328CONFIG_MESON_WATCHDOG=y
329CONFIG_MFD_AS3711=y
293CONFIG_MFD_AS3722=y 330CONFIG_MFD_AS3722=y
294CONFIG_MFD_BCM590XX=y 331CONFIG_MFD_BCM590XX=y
295CONFIG_MFD_AXP20X=y 332CONFIG_MFD_AXP20X=y
@@ -304,13 +341,16 @@ CONFIG_MFD_TPS65090=y
304CONFIG_MFD_TPS6586X=y 341CONFIG_MFD_TPS6586X=y
305CONFIG_MFD_TPS65910=y 342CONFIG_MFD_TPS65910=y
306CONFIG_REGULATOR_AB8500=y 343CONFIG_REGULATOR_AB8500=y
344CONFIG_REGULATOR_AS3711=y
307CONFIG_REGULATOR_AS3722=y 345CONFIG_REGULATOR_AS3722=y
308CONFIG_REGULATOR_AXP20X=y 346CONFIG_REGULATOR_AXP20X=y
309CONFIG_REGULATOR_BCM590XX=y 347CONFIG_REGULATOR_BCM590XX=y
348CONFIG_REGULATOR_DA9210=y
310CONFIG_REGULATOR_GPIO=y 349CONFIG_REGULATOR_GPIO=y
311CONFIG_MFD_SYSCON=y 350CONFIG_MFD_SYSCON=y
312CONFIG_POWER_RESET_SYSCON=y 351CONFIG_POWER_RESET_SYSCON=y
313CONFIG_REGULATOR_MAX8907=y 352CONFIG_REGULATOR_MAX8907=y
353CONFIG_REGULATOR_MAX8973=y
314CONFIG_REGULATOR_MAX77686=y 354CONFIG_REGULATOR_MAX77686=y
315CONFIG_REGULATOR_PALMAS=y 355CONFIG_REGULATOR_PALMAS=y
316CONFIG_REGULATOR_S2MPS11=y 356CONFIG_REGULATOR_S2MPS11=y
@@ -324,18 +364,32 @@ CONFIG_REGULATOR_TWL4030=y
324CONFIG_REGULATOR_VEXPRESS=y 364CONFIG_REGULATOR_VEXPRESS=y
325CONFIG_MEDIA_SUPPORT=y 365CONFIG_MEDIA_SUPPORT=y
326CONFIG_MEDIA_CAMERA_SUPPORT=y 366CONFIG_MEDIA_CAMERA_SUPPORT=y
367CONFIG_MEDIA_CONTROLLER=y
368CONFIG_VIDEO_V4L2_SUBDEV_API=y
327CONFIG_MEDIA_USB_SUPPORT=y 369CONFIG_MEDIA_USB_SUPPORT=y
328CONFIG_USB_VIDEO_CLASS=y 370CONFIG_USB_VIDEO_CLASS=y
329CONFIG_USB_GSPCA=y 371CONFIG_USB_GSPCA=y
372CONFIG_V4L_PLATFORM_DRIVERS=y
373CONFIG_SOC_CAMERA=m
374CONFIG_SOC_CAMERA_PLATFORM=m
375CONFIG_VIDEO_RCAR_VIN=m
376CONFIG_V4L_MEM2MEM_DRIVERS=y
377CONFIG_VIDEO_RENESAS_VSP1=m
378# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
379CONFIG_VIDEO_ADV7180=m
330CONFIG_DRM=y 380CONFIG_DRM=y
381CONFIG_DRM_RCAR_DU=m
331CONFIG_DRM_TEGRA=y 382CONFIG_DRM_TEGRA=y
332CONFIG_DRM_PANEL_SIMPLE=y 383CONFIG_DRM_PANEL_SIMPLE=y
333CONFIG_FB_ARMCLCD=y 384CONFIG_FB_ARMCLCD=y
334CONFIG_FB_WM8505=y 385CONFIG_FB_WM8505=y
386CONFIG_FB_SH_MOBILE_LCDC=y
335CONFIG_FB_SIMPLE=y 387CONFIG_FB_SIMPLE=y
388CONFIG_FB_SH_MOBILE_MERAM=y
336CONFIG_BACKLIGHT_LCD_SUPPORT=y 389CONFIG_BACKLIGHT_LCD_SUPPORT=y
337CONFIG_BACKLIGHT_CLASS_DEVICE=y 390CONFIG_BACKLIGHT_CLASS_DEVICE=y
338CONFIG_BACKLIGHT_PWM=y 391CONFIG_BACKLIGHT_PWM=y
392CONFIG_BACKLIGHT_AS3711=y
339CONFIG_FRAMEBUFFER_CONSOLE=y 393CONFIG_FRAMEBUFFER_CONSOLE=y
340CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 394CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
341CONFIG_SOUND=y 395CONFIG_SOUND=y
@@ -343,6 +397,8 @@ CONFIG_SND=y
343CONFIG_SND_DYNAMIC_MINORS=y 397CONFIG_SND_DYNAMIC_MINORS=y
344CONFIG_SND_USB_AUDIO=y 398CONFIG_SND_USB_AUDIO=y
345CONFIG_SND_SOC=y 399CONFIG_SND_SOC=y
400CONFIG_SND_SOC_SH4_FSI=m
401CONFIG_SND_SOC_RCAR=m
346CONFIG_SND_SOC_TEGRA=y 402CONFIG_SND_SOC_TEGRA=y
347CONFIG_SND_SOC_TEGRA_RT5640=y 403CONFIG_SND_SOC_TEGRA_RT5640=y
348CONFIG_SND_SOC_TEGRA_WM8753=y 404CONFIG_SND_SOC_TEGRA_WM8753=y
@@ -350,6 +406,8 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
350CONFIG_SND_SOC_TEGRA_TRIMSLICE=y 406CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
351CONFIG_SND_SOC_TEGRA_ALC5632=y 407CONFIG_SND_SOC_TEGRA_ALC5632=y
352CONFIG_SND_SOC_TEGRA_MAX98090=y 408CONFIG_SND_SOC_TEGRA_MAX98090=y
409CONFIG_SND_SOC_AK4642=m
410CONFIG_SND_SOC_WM8978=m
353CONFIG_USB=y 411CONFIG_USB=y
354CONFIG_USB_XHCI_HCD=y 412CONFIG_USB_XHCI_HCD=y
355CONFIG_USB_XHCI_MVEBU=y 413CONFIG_USB_XHCI_MVEBU=y
@@ -362,6 +420,8 @@ CONFIG_USB_ISP1760_HCD=y
362CONFIG_USB_OHCI_HCD=y 420CONFIG_USB_OHCI_HCD=y
363CONFIG_USB_OHCI_HCD_STI=y 421CONFIG_USB_OHCI_HCD_STI=y
364CONFIG_USB_OHCI_HCD_PLATFORM=y 422CONFIG_USB_OHCI_HCD_PLATFORM=y
423CONFIG_USB_R8A66597_HCD=m
424CONFIG_USB_RENESAS_USBHS=m
365CONFIG_USB_STORAGE=y 425CONFIG_USB_STORAGE=y
366CONFIG_USB_DWC3=y 426CONFIG_USB_DWC3=y
367CONFIG_USB_CHIPIDEA=y 427CONFIG_USB_CHIPIDEA=y
@@ -374,6 +434,10 @@ CONFIG_SAMSUNG_USB3PHY=y
374CONFIG_USB_GPIO_VBUS=y 434CONFIG_USB_GPIO_VBUS=y
375CONFIG_USB_ISP1301=y 435CONFIG_USB_ISP1301=y
376CONFIG_USB_MXS_PHY=y 436CONFIG_USB_MXS_PHY=y
437CONFIG_USB_RCAR_PHY=m
438CONFIG_USB_RCAR_GEN2_PHY=m
439CONFIG_USB_GADGET=y
440CONFIG_USB_RENESAS_USBHS_UDC=m
377CONFIG_MMC=y 441CONFIG_MMC=y
378CONFIG_MMC_BLOCK_MINORS=16 442CONFIG_MMC_BLOCK_MINORS=16
379CONFIG_MMC_ARMMMCI=y 443CONFIG_MMC_ARMMMCI=y
@@ -392,12 +456,14 @@ CONFIG_MMC_SDHCI_ST=y
392CONFIG_MMC_OMAP=y 456CONFIG_MMC_OMAP=y
393CONFIG_MMC_OMAP_HS=y 457CONFIG_MMC_OMAP_HS=y
394CONFIG_MMC_MVSDIO=y 458CONFIG_MMC_MVSDIO=y
395CONFIG_MMC_SUNXI=y 459CONFIG_MMC_SDHI=y
396CONFIG_MMC_DW=y 460CONFIG_MMC_DW=y
397CONFIG_MMC_DW_IDMAC=y 461CONFIG_MMC_DW_IDMAC=y
398CONFIG_MMC_DW_PLTFM=y 462CONFIG_MMC_DW_PLTFM=y
399CONFIG_MMC_DW_EXYNOS=y 463CONFIG_MMC_DW_EXYNOS=y
400CONFIG_MMC_DW_ROCKCHIP=y 464CONFIG_MMC_DW_ROCKCHIP=y
465CONFIG_MMC_SH_MMCIF=y
466CONFIG_MMC_SUNXI=y
401CONFIG_NEW_LEDS=y 467CONFIG_NEW_LEDS=y
402CONFIG_LEDS_CLASS=y 468CONFIG_LEDS_CLASS=y
403CONFIG_LEDS_GPIO=y 469CONFIG_LEDS_GPIO=y
@@ -421,10 +487,12 @@ CONFIG_RTC_DRV_AS3722=y
421CONFIG_RTC_DRV_DS1307=y 487CONFIG_RTC_DRV_DS1307=y
422CONFIG_RTC_DRV_MAX8907=y 488CONFIG_RTC_DRV_MAX8907=y
423CONFIG_RTC_DRV_MAX77686=y 489CONFIG_RTC_DRV_MAX77686=y
490CONFIG_RTC_DRV_RS5C372=m
424CONFIG_RTC_DRV_PALMAS=y 491CONFIG_RTC_DRV_PALMAS=y
425CONFIG_RTC_DRV_TWL4030=y 492CONFIG_RTC_DRV_TWL4030=y
426CONFIG_RTC_DRV_TPS6586X=y 493CONFIG_RTC_DRV_TPS6586X=y
427CONFIG_RTC_DRV_TPS65910=y 494CONFIG_RTC_DRV_TPS65910=y
495CONFIG_RTC_DRV_S35390A=m
428CONFIG_RTC_DRV_EM3027=y 496CONFIG_RTC_DRV_EM3027=y
429CONFIG_RTC_DRV_PL031=y 497CONFIG_RTC_DRV_PL031=y
430CONFIG_RTC_DRV_VT8500=y 498CONFIG_RTC_DRV_VT8500=y
@@ -436,6 +504,9 @@ CONFIG_DMADEVICES=y
436CONFIG_DW_DMAC=y 504CONFIG_DW_DMAC=y
437CONFIG_MV_XOR=y 505CONFIG_MV_XOR=y
438CONFIG_TEGRA20_APB_DMA=y 506CONFIG_TEGRA20_APB_DMA=y
507CONFIG_SH_DMAE=y
508CONFIG_RCAR_AUDMAC_PP=m
509CONFIG_RCAR_DMAC=y
439CONFIG_STE_DMA40=y 510CONFIG_STE_DMA40=y
440CONFIG_SIRF_DMA=y 511CONFIG_SIRF_DMA=y
441CONFIG_TI_EDMA=y 512CONFIG_TI_EDMA=y
@@ -468,6 +539,7 @@ CONFIG_IIO=y
468CONFIG_XILINX_XADC=y 539CONFIG_XILINX_XADC=y
469CONFIG_AK8975=y 540CONFIG_AK8975=y
470CONFIG_PWM=y 541CONFIG_PWM=y
542CONFIG_PWM_RENESAS_TPU=y
471CONFIG_PWM_TEGRA=y 543CONFIG_PWM_TEGRA=y
472CONFIG_PWM_VT8500=y 544CONFIG_PWM_VT8500=y
473CONFIG_PHY_HIX5HD2_SATA=y 545CONFIG_PHY_HIX5HD2_SATA=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index b7386524c356..a097cffa1231 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -114,6 +114,7 @@ CONFIG_MTD_PHYSMAP_OF=y
114CONFIG_MTD_NAND=y 114CONFIG_MTD_NAND=y
115CONFIG_MTD_NAND_ECC_BCH=y 115CONFIG_MTD_NAND_ECC_BCH=y
116CONFIG_MTD_NAND_OMAP2=y 116CONFIG_MTD_NAND_OMAP2=y
117CONFIG_MTD_NAND_OMAP_BCH=y
117CONFIG_MTD_ONENAND=y 118CONFIG_MTD_ONENAND=y
118CONFIG_MTD_ONENAND_VERIFY_WRITE=y 119CONFIG_MTD_ONENAND_VERIFY_WRITE=y
119CONFIG_MTD_ONENAND_OMAP2=y 120CONFIG_MTD_ONENAND_OMAP2=y
@@ -248,6 +249,7 @@ CONFIG_TWL6040_CORE=y
248CONFIG_REGULATOR_PALMAS=y 249CONFIG_REGULATOR_PALMAS=y
249CONFIG_REGULATOR_PBIAS=y 250CONFIG_REGULATOR_PBIAS=y
250CONFIG_REGULATOR_TI_ABB=y 251CONFIG_REGULATOR_TI_ABB=y
252CONFIG_REGULATOR_TPS62360=m
251CONFIG_REGULATOR_TPS65023=y 253CONFIG_REGULATOR_TPS65023=y
252CONFIG_REGULATOR_TPS6507X=y 254CONFIG_REGULATOR_TPS6507X=y
253CONFIG_REGULATOR_TPS65217=y 255CONFIG_REGULATOR_TPS65217=y
@@ -374,7 +376,7 @@ CONFIG_PWM_TIEHRPWM=m
374CONFIG_PWM_TWL=m 376CONFIG_PWM_TWL=m
375CONFIG_PWM_TWL_LED=m 377CONFIG_PWM_TWL_LED=m
376CONFIG_OMAP_USB2=m 378CONFIG_OMAP_USB2=m
377CONFIG_TI_PIPE3=m 379CONFIG_TI_PIPE3=y
378CONFIG_EXT2_FS=y 380CONFIG_EXT2_FS=y
379CONFIG_EXT3_FS=y 381CONFIG_EXT3_FS=y
380# CONFIG_EXT3_FS_XATTR is not set 382# CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
index 8423be76080e..52241207a82a 100644
--- a/arch/arm/mach-asm9260/Kconfig
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -2,5 +2,7 @@ config MACH_ASM9260
2 bool "Alphascale ASM9260" 2 bool "Alphascale ASM9260"
3 depends on ARCH_MULTI_V5 3 depends on ARCH_MULTI_V5
4 select CPU_ARM926T 4 select CPU_ARM926T
5 select ASM9260_TIMER
6 select GENERIC_CLOCKEVENTS
5 help 7 help
6 Support for Alphascale ASM9260 based platform. 8 Support for Alphascale ASM9260 based platform.
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 34b4c0044961..dd94567c3628 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -71,13 +71,7 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
71static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 71static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
72static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 72static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
73 73
74#ifndef CONFIG_OMAP_32K_TIMER 74static unsigned short enable_dyn_sleep;
75
76static unsigned short enable_dyn_sleep = 0;
77
78#else
79
80static unsigned short enable_dyn_sleep = 1;
81 75
82static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, 76static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
83 char *buf) 77 char *buf)
@@ -90,8 +84,9 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
90{ 84{
91 unsigned short value; 85 unsigned short value;
92 if (sscanf(buf, "%hu", &value) != 1 || 86 if (sscanf(buf, "%hu", &value) != 1 ||
93 (value != 0 && value != 1)) { 87 (value != 0 && value != 1) ||
94 printk(KERN_ERR "idle_sleep_store: Invalid value\n"); 88 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
89 pr_err("idle_sleep_store: Invalid value\n");
95 return -EINVAL; 90 return -EINVAL;
96 } 91 }
97 enable_dyn_sleep = value; 92 enable_dyn_sleep = value;
@@ -101,7 +96,6 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
101static struct kobj_attribute sleep_while_idle_attr = 96static struct kobj_attribute sleep_while_idle_attr =
102 __ATTR(sleep_while_idle, 0644, idle_show, idle_store); 97 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
103 98
104#endif
105 99
106static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 100static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
107 101
@@ -115,16 +109,11 @@ void omap1_pm_idle(void)
115{ 109{
116 extern __u32 arm_idlect1_mask; 110 extern __u32 arm_idlect1_mask;
117 __u32 use_idlect1 = arm_idlect1_mask; 111 __u32 use_idlect1 = arm_idlect1_mask;
118 int do_sleep = 0;
119 112
120 local_fiq_disable(); 113 local_fiq_disable();
121 114
122#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) 115#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
123#warning Enable 32kHz OS timer in order to allow sleep states in idle
124 use_idlect1 = use_idlect1 & ~(1 << 9); 116 use_idlect1 = use_idlect1 & ~(1 << 9);
125#else
126 if (enable_dyn_sleep)
127 do_sleep = 1;
128#endif 117#endif
129 118
130#ifdef CONFIG_OMAP_DM_TIMER 119#ifdef CONFIG_OMAP_DM_TIMER
@@ -134,10 +123,12 @@ void omap1_pm_idle(void)
134 if (omap_dma_running()) 123 if (omap_dma_running())
135 use_idlect1 &= ~(1 << 6); 124 use_idlect1 &= ~(1 << 6);
136 125
137 /* We should be able to remove the do_sleep variable and multiple 126 /*
127 * We should be able to remove the do_sleep variable and multiple
138 * tests above as soon as drivers, timer and DMA code have been fixed. 128 * tests above as soon as drivers, timer and DMA code have been fixed.
139 * Even the sleep block count should become obsolete. */ 129 * Even the sleep block count should become obsolete.
140 if ((use_idlect1 != ~0) || !do_sleep) { 130 */
131 if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
141 132
142 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); 133 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
143 if (cpu_is_omap15xx()) 134 if (cpu_is_omap15xx())
@@ -635,15 +626,25 @@ static const struct platform_suspend_ops omap_pm_ops = {
635 626
636static int __init omap_pm_init(void) 627static int __init omap_pm_init(void)
637{ 628{
638 629 int error = 0;
639#ifdef CONFIG_OMAP_32K_TIMER
640 int error;
641#endif
642 630
643 if (!cpu_class_is_omap1()) 631 if (!cpu_class_is_omap1())
644 return -ENODEV; 632 return -ENODEV;
645 633
646 printk("Power Management for TI OMAP.\n"); 634 pr_info("Power Management for TI OMAP.\n");
635
636 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
637 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
638
639 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
640 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
641
642 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
643 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
644 /* OMAP16xx only */
645 pr_info("OMAP1 PM: sleep states in idle enabled\n");
646 enable_dyn_sleep = 1;
647 }
647 648
648 /* 649 /*
649 * We copy the assembler sleep/wakeup routines to SRAM. 650 * We copy the assembler sleep/wakeup routines to SRAM.
@@ -693,17 +694,15 @@ static int __init omap_pm_init(void)
693 omap_pm_init_debugfs(); 694 omap_pm_init_debugfs();
694#endif 695#endif
695 696
696#ifdef CONFIG_OMAP_32K_TIMER
697 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); 697 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
698 if (error) 698 if (error)
699 printk(KERN_ERR "sysfs_create_file failed: %d\n", error); 699 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
700#endif
701 700
702 if (cpu_is_omap16xx()) { 701 if (cpu_is_omap16xx()) {
703 /* configure LOW_PWR pin */ 702 /* configure LOW_PWR pin */
704 omap_cfg_reg(T20_1610_LOW_PWR); 703 omap_cfg_reg(T20_1610_LOW_PWR);
705 } 704 }
706 705
707 return 0; 706 return error;
708} 707}
709__initcall(omap_pm_init); 708__initcall(omap_pm_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2b8e47788062..1041b19485ab 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -69,6 +69,7 @@ config SOC_DRA7XX
69 select ARM_GIC 69 select ARM_GIC
70 select HAVE_ARM_ARCH_TIMER 70 select HAVE_ARM_ARCH_TIMER
71 select IRQ_CROSSBAR 71 select IRQ_CROSSBAR
72 select ARM_ERRATA_798181 if SMP
72 73
73config ARCH_OMAP2PLUS 74config ARCH_OMAP2PLUS
74 bool 75 bool
@@ -278,27 +279,6 @@ config OMAP3_SDRC_AC_TIMING
278 wish to say no. Selecting yes without understanding what is 279 wish to say no. Selecting yes without understanding what is
279 going on could result in system crashes; 280 going on could result in system crashes;
280 281
281config OMAP4_ERRATA_I688
282 bool "OMAP4 errata: Async Bridge Corruption"
283 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
284 select ARCH_HAS_BARRIERS
285 help
286 If a data is stalled inside asynchronous bridge because of back
287 pressure, it may be accepted multiple times, creating pointer
288 misalignment that will corrupt next transfers on that data path
289 until next reset of the system (No recovery procedure once the
290 issue is hit, the path remains consistently broken). Async bridge
291 can be found on path between MPU to EMIF and MPU to L3 interconnect.
292 This situation can happen only when the idle is initiated by a
293 Master Request Disconnection (which is trigged by software when
294 executing WFI on CPU).
295 The work-around for this errata needs all the initiators connected
296 through async bridge must ensure that data path is properly drained
297 before issuing WFI. This condition will be met if one Strongly ordered
298 access is performed to the target right before executing the WFI.
299 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
300 IO barrier ensure that there is no synchronisation loss on initiators
301 operating on both interconnect port simultaneously.
302endmenu 282endmenu
303 283
304endif 284endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5c37ae..a699d7169307 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,9 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26#include <linux/regmap.h>
27#include <linux/of_address.h>
28#include <linux/bootmem.h>
26#include <asm/cpu.h> 29#include <asm/cpu.h>
27 30
28#include <trace/events/power.h> 31#include <trace/events/power.h>
@@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
72static bool clkdm_control = true; 75static bool clkdm_control = true;
73 76
74static LIST_HEAD(clk_hw_omap_clocks); 77static LIST_HEAD(clk_hw_omap_clocks);
75void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 78
79struct clk_iomap {
80 struct regmap *regmap;
81 void __iomem *mem;
82};
83
84static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
85
86static void clk_memmap_writel(u32 val, void __iomem *reg)
87{
88 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
89 struct clk_iomap *io = clk_memmaps[r->index];
90
91 if (io->regmap)
92 regmap_write(io->regmap, r->offset, val);
93 else
94 writel_relaxed(val, io->mem + r->offset);
95}
96
97static u32 clk_memmap_readl(void __iomem *reg)
98{
99 u32 val;
100 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
101 struct clk_iomap *io = clk_memmaps[r->index];
102
103 if (io->regmap)
104 regmap_read(io->regmap, r->offset, &val);
105 else
106 val = readl_relaxed(io->mem + r->offset);
107
108 return val;
109}
76 110
77void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 111void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
78{ 112{
79 if (clk->flags & MEMMAP_ADDRESSING) { 113 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
80 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
81 writel_relaxed(val, clk_memmaps[r->index] + r->offset);
82 } else {
83 writel_relaxed(val, reg); 114 writel_relaxed(val, reg);
84 } 115 else
116 clk_memmap_writel(val, reg);
85} 117}
86 118
87u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 119u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
88{ 120{
89 u32 val; 121 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
122 return readl_relaxed(reg);
123 else
124 return clk_memmap_readl(reg);
125}
90 126
91 if (clk->flags & MEMMAP_ADDRESSING) { 127static struct ti_clk_ll_ops omap_clk_ll_ops = {
92 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg; 128 .clk_readl = clk_memmap_readl,
93 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 129 .clk_writel = clk_memmap_writel,
94 } else { 130};
95 val = readl_relaxed(reg);
96 }
97 131
98 return val; 132/**
133 * omap2_clk_provider_init - initialize a clock provider
134 * @match_table: DT device table to match for devices to init
135 * @np: device node pointer for the this clock provider
136 * @index: index for the clock provider
137 + @syscon: syscon regmap pointer
138 * @mem: iomem pointer for the clock provider memory area, only used if
139 * syscon is not provided
140 *
141 * Initializes a clock provider module (CM/PRM etc.), registering
142 * the memory mapping at specified index and initializing the
143 * low level driver infrastructure. Returns 0 in success.
144 */
145int __init omap2_clk_provider_init(struct device_node *np, int index,
146 struct regmap *syscon, void __iomem *mem)
147{
148 struct clk_iomap *io;
149
150 ti_clk_ll_ops = &omap_clk_ll_ops;
151
152 io = kzalloc(sizeof(*io), GFP_KERNEL);
153
154 io->regmap = syscon;
155 io->mem = mem;
156
157 clk_memmaps[index] = io;
158
159 ti_dt_clk_init_provider(np, index);
160
161 return 0;
162}
163
164/**
165 * omap2_clk_legacy_provider_init - initialize a legacy clock provider
166 * @index: index for the clock provider
167 * @mem: iomem pointer for the clock provider memory area
168 *
169 * Initializes a legacy clock provider memory mapping.
170 */
171void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
172{
173 struct clk_iomap *io;
174
175 ti_clk_ll_ops = &omap_clk_ll_ops;
176
177 io = memblock_virt_alloc(sizeof(*io), 0);
178
179 io->mem = mem;
180
181 clk_memmaps[index] = io;
99} 182}
100 183
101/* 184/*
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f96000..652ed0ab86ec 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
271extern const struct clksel_rate div_1_4_rates[]; 271extern const struct clksel_rate div_1_4_rates[];
272extern const struct clksel_rate div31_1to31_rates[]; 272extern const struct clksel_rate div31_1to31_rates[];
273 273
274extern void __iomem *clk_memmaps[];
275
276extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 274extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
277extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 275extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
278 276
277struct regmap;
278
279int __init omap2_clk_provider_init(struct device_node *np, int index,
280 struct regmap *syscon, void __iomem *mem);
281void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
282
279void __init ti_clk_init_features(void); 283void __init ti_clk_init_features(void);
280#endif 284#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87a79b6..1fe3e6b833d2 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
70int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); 70int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
71extern int cm_register(struct cm_ll_data *cld); 71extern int cm_register(struct cm_ll_data *cld);
72extern int cm_unregister(struct cm_ll_data *cld); 72extern int cm_unregister(struct cm_ll_data *cld);
73int omap_cm_init(void);
74int omap2_cm_base_init(void);
73 75
74# endif 76# endif
75 77
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9dcd05..3e5fd3587eb1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
393 .wait_module_ready = &omap2xxx_cm_wait_module_ready, 393 .wait_module_ready = &omap2xxx_cm_wait_module_ready,
394}; 394};
395 395
396int __init omap2xxx_cm_init(void) 396int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
397{ 397{
398 return cm_register(&omap2xxx_cm_ll_data); 398 return cm_register(&omap2xxx_cm_ll_data);
399} 399}
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c597b0e1..7b8c79c0ce27 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
63extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, 63extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
64 u32 mdm); 64 u32 mdm);
65 65
66extern int __init omap2xxx_cm_init(void); 66int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
67 67
68#endif 68#endif
69 69
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac784278..7b181f929525 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
352 .module_disable = &am33xx_cm_module_disable, 352 .module_disable = &am33xx_cm_module_disable,
353}; 353};
354 354
355int __init am33xx_cm_init(void) 355int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
356{ 356{
357 return cm_register(&am33xx_cm_ll_data); 357 return cm_register(&am33xx_cm_ll_data);
358} 358}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2bc9d9..a91f7d282455 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
19 19
20#include "cm.h" 20#include "cm.h"
21#include "cm-regbits-33xx.h" 21#include "cm-regbits-33xx.h"
22#include "prcm-common.h"
22 23
23/* CM base address */ 24/* CM base address */
24#define AM33XX_CM_BASE 0x44e00000 25#define AM33XX_CM_BASE 0x44e00000
@@ -374,6 +375,6 @@
374 375
375 376
376#ifndef __ASSEMBLER__ 377#ifndef __ASSEMBLER__
377int am33xx_cm_init(void); 378int am33xx_cm_init(const struct omap_prcm_init_data *data);
378#endif /* ASSEMBLER */ 379#endif /* ASSEMBLER */
379#endif 380#endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f035f9..187fa4386718 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
671 .wait_module_ready = &omap3xxx_cm_wait_module_ready, 671 .wait_module_ready = &omap3xxx_cm_wait_module_ready,
672}; 672};
673 673
674int __init omap3xxx_cm_init(void) 674int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
675{ 675{
676 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
676 return cm_register(&omap3xxx_cm_ll_data); 677 return cm_register(&omap3xxx_cm_ll_data);
677} 678}
678 679
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a8581c0c4..bc444e2080a1 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
72extern void omap3_cm_restore_context(void); 72extern void omap3_cm_restore_context(void);
73extern void omap3_cm_save_scratchpad_contents(u32 *ptr); 73extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
74 74
75extern int __init omap3xxx_cm_init(void); 75int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
76 76
77#endif 77#endif
78 78
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a4af19..309a4c913448 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004 24#define OMAP4_CM_STATICDEP 0x0004
25 25
26void omap_cm_base_init(void); 26int omap4_cm_init(const struct omap_prcm_init_data *data);
27int omap4_cm_init(void);
28 27
29#endif 28#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fcedc48..23e8bcec34e3 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,14 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/bug.h> 17#include <linux/bug.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
18 20
19#include "cm2xxx.h" 21#include "cm2xxx.h"
20#include "cm3xxx.h" 22#include "cm3xxx.h"
23#include "cm33xx.h"
21#include "cm44xx.h" 24#include "cm44xx.h"
25#include "clock.h"
22 26
23/* 27/*
24 * cm_ll_data: function pointers to SoC-specific implementations of 28 * cm_ll_data: function pointers to SoC-specific implementations of
@@ -33,6 +37,9 @@ void __iomem *cm_base;
33/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ 37/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
34void __iomem *cm2_base; 38void __iomem *cm2_base;
35 39
40#define CM_NO_CLOCKS 0x1
41#define CM_SINGLE_INSTANCE 0x2
42
36/** 43/**
37 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) 44 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
38 * @cm: CM base virtual address 45 * @cm: CM base virtual address
@@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
212 219
213 return 0; 220 return 0;
214} 221}
222
223#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
224 defined(CONFIG_SOC_DRA7XX)
225static struct omap_prcm_init_data cm_data __initdata = {
226 .index = TI_CLKM_CM,
227 .init = omap4_cm_init,
228};
229
230static struct omap_prcm_init_data cm2_data __initdata = {
231 .index = TI_CLKM_CM2,
232 .init = omap4_cm_init,
233};
234#endif
235
236#ifdef CONFIG_ARCH_OMAP2
237static struct omap_prcm_init_data omap2_prcm_data __initdata = {
238 .index = TI_CLKM_CM,
239 .init = omap2xxx_cm_init,
240 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
241};
242#endif
243
244#ifdef CONFIG_ARCH_OMAP3
245static struct omap_prcm_init_data omap3_cm_data __initdata = {
246 .index = TI_CLKM_CM,
247 .init = omap3xxx_cm_init,
248 .flags = CM_SINGLE_INSTANCE,
249
250 /*
251 * IVA2 offset is a negative value, must offset the cm_base address
252 * by this to get it to positive side on the iomap
253 */
254 .offset = -OMAP3430_IVA2_MOD,
255};
256#endif
257
258#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
259static struct omap_prcm_init_data am3_prcm_data __initdata = {
260 .index = TI_CLKM_CM,
261 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
262 .init = am33xx_cm_init,
263};
264#endif
265
266#ifdef CONFIG_SOC_AM43XX
267static struct omap_prcm_init_data am4_prcm_data __initdata = {
268 .index = TI_CLKM_CM,
269 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
270 .init = omap4_cm_init,
271};
272#endif
273
274static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
275#ifdef CONFIG_ARCH_OMAP2
276 { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
277#endif
278#ifdef CONFIG_ARCH_OMAP3
279 { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
280#endif
281#ifdef CONFIG_ARCH_OMAP4
282 { .compatible = "ti,omap4-cm1", .data = &cm_data },
283 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
284#endif
285#ifdef CONFIG_SOC_OMAP5
286 { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
287 { .compatible = "ti,omap5-cm-core", .data = &cm2_data },
288#endif
289#ifdef CONFIG_SOC_DRA7XX
290 { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
291 { .compatible = "ti,dra7-cm-core", .data = &cm2_data },
292#endif
293#ifdef CONFIG_SOC_AM33XX
294 { .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
295#endif
296#ifdef CONFIG_SOC_AM43XX
297 { .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
298#endif
299#ifdef CONFIG_SOC_TI81XX
300 { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
301 { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
302#endif
303 { }
304};
305
306/**
307 * omap2_cm_base_init - initialize iomappings for the CM drivers
308 *
309 * Detects and initializes the iomappings for the CM driver, based
310 * on the DT data. Returns 0 in success, negative error value
311 * otherwise.
312 */
313int __init omap2_cm_base_init(void)
314{
315 struct device_node *np;
316 const struct of_device_id *match;
317 struct omap_prcm_init_data *data;
318 void __iomem *mem;
319
320 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
321 data = (struct omap_prcm_init_data *)match->data;
322
323 mem = of_iomap(np, 0);
324 if (!mem)
325 return -ENOMEM;
326
327 if (data->index == TI_CLKM_CM)
328 cm_base = mem + data->offset;
329
330 if (data->index == TI_CLKM_CM2)
331 cm2_base = mem + data->offset;
332
333 data->mem = mem;
334
335 data->np = np;
336
337 if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
338 (cm_base && cm2_base)))
339 data->init(data);
340 }
341
342 return 0;
343}
344
345/**
346 * omap_cm_init - low level init for the CM drivers
347 *
348 * Initializes the low level clock infrastructure for CM drivers.
349 * Returns 0 in success, negative error value in failure.
350 */
351int __init omap_cm_init(void)
352{
353 struct device_node *np;
354 const struct of_device_id *match;
355 const struct omap_prcm_init_data *data;
356 int ret;
357
358 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
359 data = match->data;
360
361 if (data->flags & CM_NO_CLOCKS)
362 continue;
363
364 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
365 if (ret)
366 return ret;
367 }
368
369 return 0;
370}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff66aff..2c0e07ed6b99 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
63 * Populates the base addresses of the _cm_bases 63 * Populates the base addresses of the _cm_bases
64 * array used for read/write of cm module registers. 64 * array used for read/write of cm module registers.
65 */ 65 */
66void omap_cm_base_init(void) 66static void omap_cm_base_init(void)
67{ 67{
68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
514 .module_disable = &omap4_cminst_module_disable, 514 .module_disable = &omap4_cminst_module_disable,
515}; 515};
516 516
517int __init omap4_cm_init(void) 517int __init omap4_cm_init(const struct omap_prcm_init_data *data)
518{ 518{
519 omap_cm_base_init();
520
519 return cm_register(&omap4xxx_cm_ll_data); 521 return cm_register(&omap4xxx_cm_ll_data);
520} 522}
521 523
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 484cdadfb187..eae6a0e87c90 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -30,5 +30,4 @@ int __weak omap_secure_ram_reserve_memblock(void)
30void __init omap_reserve(void) 30void __init omap_reserve(void)
31{ 31{
32 omap_secure_ram_reserve_memblock(); 32 omap_secure_ram_reserve_memblock();
33 omap_barrier_reserve_memblock();
34} 33}
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 46e24581d624..cf3cf22ecd42 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -200,9 +200,6 @@ void __init omap4_map_io(void);
200void __init omap5_map_io(void); 200void __init omap5_map_io(void);
201void __init ti81xx_map_io(void); 201void __init ti81xx_map_io(void);
202 202
203/* omap_barriers_init() is OMAP4 only */
204void omap_barriers_init(void);
205
206/** 203/**
207 * omap_test_timeout - busy-loop, testing a condition 204 * omap_test_timeout - busy-loop, testing a condition
208 * @cond: condition to test until it evaluates to true 205 * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4ab29c..af95a624fe71 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,9 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of_address.h>
18#include <linux/regmap.h>
19#include <linux/mfd/syscon.h>
17 20
18#include "soc.h" 21#include "soc.h"
19#include "iomap.h" 22#include "iomap.h"
@@ -25,13 +28,15 @@
25#include "sdrc.h" 28#include "sdrc.h"
26#include "pm.h" 29#include "pm.h"
27#include "control.h" 30#include "control.h"
31#include "clock.h"
28 32
29/* Used by omap3_ctrl_save_padconf() */ 33/* Used by omap3_ctrl_save_padconf() */
30#define START_PADCONF_SAVE 0x2 34#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1 35#define PADCONF_SAVE_DONE 0x1
32 36
33static void __iomem *omap2_ctrl_base; 37static void __iomem *omap2_ctrl_base;
34static void __iomem *omap4_ctrl_pad_base; 38static s16 omap2_ctrl_offset;
39static struct regmap *omap2_ctrl_syscon;
35 40
36#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 41#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37struct omap3_scratchpad { 42struct omap3_scratchpad {
@@ -133,66 +138,79 @@ struct omap3_control_regs {
133static struct omap3_control_regs control_context; 138static struct omap3_control_regs control_context;
134#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 139#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
135 140
136#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 141void __init omap2_set_globals_control(void __iomem *ctrl)
137#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
138
139void __init omap2_set_globals_control(void __iomem *ctrl,
140 void __iomem *ctrl_pad)
141{ 142{
142 omap2_ctrl_base = ctrl; 143 omap2_ctrl_base = ctrl;
143 omap4_ctrl_pad_base = ctrl_pad;
144}
145
146void __iomem *omap_ctrl_base_get(void)
147{
148 return omap2_ctrl_base;
149} 144}
150 145
151u8 omap_ctrl_readb(u16 offset) 146u8 omap_ctrl_readb(u16 offset)
152{ 147{
153 return readb_relaxed(OMAP_CTRL_REGADDR(offset)); 148 u32 val;
149 u8 byte_offset = offset & 0x3;
150
151 val = omap_ctrl_readl(offset);
152
153 return (val >> (byte_offset * 8)) & 0xff;
154} 154}
155 155
156u16 omap_ctrl_readw(u16 offset) 156u16 omap_ctrl_readw(u16 offset)
157{ 157{
158 return readw_relaxed(OMAP_CTRL_REGADDR(offset)); 158 u32 val;
159 u16 byte_offset = offset & 0x2;
160
161 val = omap_ctrl_readl(offset);
162
163 return (val >> (byte_offset * 8)) & 0xffff;
159} 164}
160 165
161u32 omap_ctrl_readl(u16 offset) 166u32 omap_ctrl_readl(u16 offset)
162{ 167{
163 return readl_relaxed(OMAP_CTRL_REGADDR(offset)); 168 u32 val;
169
170 offset &= 0xfffc;
171 if (!omap2_ctrl_syscon)
172 val = readl_relaxed(omap2_ctrl_base + offset);
173 else
174 regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
175 &val);
176
177 return val;
164} 178}
165 179
166void omap_ctrl_writeb(u8 val, u16 offset) 180void omap_ctrl_writeb(u8 val, u16 offset)
167{ 181{
168 writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); 182 u32 tmp;
183 u8 byte_offset = offset & 0x3;
184
185 tmp = omap_ctrl_readl(offset);
186
187 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
188 tmp |= val << (byte_offset * 8);
189
190 omap_ctrl_writel(tmp, offset);
169} 191}
170 192
171void omap_ctrl_writew(u16 val, u16 offset) 193void omap_ctrl_writew(u16 val, u16 offset)
172{ 194{
173 writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); 195 u32 tmp;
174} 196 u8 byte_offset = offset & 0x2;
175 197
176void omap_ctrl_writel(u32 val, u16 offset) 198 tmp = omap_ctrl_readl(offset);
177{
178 writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
179}
180 199
181/* 200 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
182 * On OMAP4 control pad are not addressable from control 201 tmp |= val << (byte_offset * 8);
183 * core base. So the common omap_ctrl_read/write APIs breaks
184 * Hence export separate APIs to manage the omap4 pad control
185 * registers. This APIs will work only for OMAP4
186 */
187 202
188u32 omap4_ctrl_pad_readl(u16 offset) 203 omap_ctrl_writel(tmp, offset);
189{
190 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
191} 204}
192 205
193void omap4_ctrl_pad_writel(u32 val, u16 offset) 206void omap_ctrl_writel(u32 val, u16 offset)
194{ 207{
195 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); 208 offset &= 0xfffc;
209 if (!omap2_ctrl_syscon)
210 writel_relaxed(val, omap2_ctrl_base + offset);
211 else
212 regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
213 val);
196} 214}
197 215
198#ifdef CONFIG_ARCH_OMAP3 216#ifdef CONFIG_ARCH_OMAP3
@@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
611 omap3_ctrl_setup_d2d_padconf(); 629 omap3_ctrl_setup_d2d_padconf();
612} 630}
613#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 631#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
632
633struct control_init_data {
634 int index;
635 s16 offset;
636};
637
638static struct control_init_data ctrl_data = {
639 .index = TI_CLKM_CTRL,
640};
641
642static const struct control_init_data omap2_ctrl_data = {
643 .index = TI_CLKM_CTRL,
644 .offset = -OMAP2_CONTROL_GENERAL,
645};
646
647static const struct of_device_id omap_scrm_dt_match_table[] = {
648 { .compatible = "ti,am3-scm", .data = &ctrl_data },
649 { .compatible = "ti,am4-scm", .data = &ctrl_data },
650 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
651 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
652 { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
653 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
654 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
655 { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
656 { }
657};
658
659/**
660 * omap2_control_base_init - initialize iomappings for the control driver
661 *
662 * Detects and initializes the iomappings for the control driver, based
663 * on the DT data. Returns 0 in success, negative error value
664 * otherwise.
665 */
666int __init omap2_control_base_init(void)
667{
668 struct device_node *np;
669 const struct of_device_id *match;
670 struct control_init_data *data;
671
672 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
673 data = (struct control_init_data *)match->data;
674
675 omap2_ctrl_base = of_iomap(np, 0);
676 if (!omap2_ctrl_base)
677 return -ENOMEM;
678
679 omap2_ctrl_offset = data->offset;
680 }
681
682 return 0;
683}
684
685/**
686 * omap_control_init - low level init for the control driver
687 *
688 * Initializes the low level clock infrastructure for control driver.
689 * Returns 0 in success, negative error value in failure.
690 */
691int __init omap_control_init(void)
692{
693 struct device_node *np, *scm_conf;
694 const struct of_device_id *match;
695 const struct omap_prcm_init_data *data;
696 int ret;
697 struct regmap *syscon;
698
699 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
700 data = match->data;
701
702 /*
703 * Check if we have scm_conf node, if yes, use this to
704 * access clock registers.
705 */
706 scm_conf = of_get_child_by_name(np, "scm_conf");
707
708 if (scm_conf) {
709 syscon = syscon_node_to_regmap(scm_conf);
710
711 if (IS_ERR(syscon))
712 return PTR_ERR(syscon);
713
714 omap2_ctrl_syscon = syscon;
715
716 if (of_get_child_by_name(scm_conf, "clocks")) {
717 ret = omap2_clk_provider_init(scm_conf,
718 data->index,
719 syscon, NULL);
720 if (ret)
721 return ret;
722 }
723
724 iounmap(omap2_ctrl_base);
725 omap2_ctrl_base = NULL;
726 } else {
727 /* No scm_conf found, direct access */
728 ret = omap2_clk_provider_init(np, data->index, NULL,
729 omap2_ctrl_base);
730 if (ret)
731 return ret;
732 }
733 }
734
735 return 0;
736}
737
738/**
739 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
740 *
741 * Legacy iomap init for clock provider. Needed only by legacy boot mode,
742 * where the base addresses are not parsed from DT, but still required
743 * by the clock driver to be setup properly.
744 */
745void __init omap3_control_legacy_iomap_init(void)
746{
747 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
748}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8a487181210..80d2b7d8e36e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,15 +440,12 @@
440 440
441#ifndef __ASSEMBLY__ 441#ifndef __ASSEMBLY__
442#ifdef CONFIG_ARCH_OMAP2PLUS 442#ifdef CONFIG_ARCH_OMAP2PLUS
443extern void __iomem *omap_ctrl_base_get(void);
444extern u8 omap_ctrl_readb(u16 offset); 443extern u8 omap_ctrl_readb(u16 offset);
445extern u16 omap_ctrl_readw(u16 offset); 444extern u16 omap_ctrl_readw(u16 offset);
446extern u32 omap_ctrl_readl(u16 offset); 445extern u32 omap_ctrl_readl(u16 offset);
447extern u32 omap4_ctrl_pad_readl(u16 offset);
448extern void omap_ctrl_writeb(u8 val, u16 offset); 446extern void omap_ctrl_writeb(u8 val, u16 offset);
449extern void omap_ctrl_writew(u16 val, u16 offset); 447extern void omap_ctrl_writew(u16 val, u16 offset);
450extern void omap_ctrl_writel(u32 val, u16 offset); 448extern void omap_ctrl_writel(u32 val, u16 offset);
451extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
452 449
453extern void omap3_save_scratchpad_contents(void); 450extern void omap3_save_scratchpad_contents(void);
454extern void omap3_clear_scratchpad_contents(void); 451extern void omap3_clear_scratchpad_contents(void);
@@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
464extern void omap3630_ctrl_disable_rta(void); 461extern void omap3630_ctrl_disable_rta(void);
465extern int omap3_ctrl_save_padconf(void); 462extern int omap3_ctrl_save_padconf(void);
466void omap3_ctrl_init(void); 463void omap3_ctrl_init(void);
467extern void omap2_set_globals_control(void __iomem *ctrl, 464int omap2_control_base_init(void);
468 void __iomem *ctrl_pad); 465int omap_control_init(void);
466void omap2_set_globals_control(void __iomem *ctrl);
467void __init omap3_control_legacy_iomap_init(void);
469#else 468#else
470#define omap_ctrl_base_get() 0
471#define omap_ctrl_readb(x) 0 469#define omap_ctrl_readb(x) 0
472#define omap_ctrl_readw(x) 0 470#define omap_ctrl_readw(x) 0
473#define omap_ctrl_readl(x) 0 471#define omap_ctrl_readl(x) 0
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..f492ae147c6a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
26#include <linux/of.h> 26#include <linux/of.h>
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/mfd/syscon.h>
30#include <linux/regmap.h>
29 31
30#include <video/omapdss.h> 32#include <video/omapdss.h>
31#include "omap_hwmod.h" 33#include "omap_hwmod.h"
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
104 { "dss_hdmi", "omapdss_hdmi", -1 }, 106 { "dss_hdmi", "omapdss_hdmi", -1 },
105}; 107};
106 108
109#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
110
111static struct regmap *omap4_dsi_mux_syscon;
112
107static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 113static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
108{ 114{
109 u32 enable_mask, enable_shift; 115 u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
124 return -ENODEV; 130 return -ENODEV;
125 } 131 }
126 132
127 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 133 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
128 134
129 reg &= ~enable_mask; 135 reg &= ~enable_mask;
130 reg &= ~pipd_mask; 136 reg &= ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
132 reg |= (lanes << enable_shift) & enable_mask; 138 reg |= (lanes << enable_shift) & enable_mask;
133 reg |= (lanes << pipd_shift) & pipd_mask; 139 reg |= (lanes << pipd_shift) & pipd_mask;
134 140
135 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 141 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
136 142
137 return 0; 143 return 0;
138} 144}
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
665 return r; 671 return r;
666 } 672 }
667 673
674 /* add DSI info for omap4 */
675 node = of_find_node_by_name(NULL, "omap4_padconf_global");
676 if (node)
677 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
678
668 return 0; 679 return 0;
669} 680}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2a2f4d56e4c8..f8121dbc9d48 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
52 52
53int omap_type(void) 53int omap_type(void)
54{ 54{
55 u32 val = 0; 55 static u32 val = OMAP2_DEVICETYPE_MASK;
56
57 if (val < OMAP2_DEVICETYPE_MASK)
58 return val;
56 59
57 if (cpu_is_omap24xx()) { 60 if (cpu_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c4871c55bd8b..820dde8b5b04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -306,7 +306,6 @@ void __init am33xx_map_io(void)
306void __init omap4_map_io(void) 306void __init omap4_map_io(void)
307{ 307{
308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
309 omap_barriers_init();
310} 309}
311#endif 310#endif
312 311
@@ -314,7 +313,6 @@ void __init omap4_map_io(void)
314void __init omap5_map_io(void) 313void __init omap5_map_io(void)
315{ 314{
316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 315 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
317 omap_barriers_init();
318} 316}
319#endif 317#endif
320/* 318/*
@@ -384,13 +382,9 @@ void __init omap2420_init_early(void)
384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
387 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 385 omap2_control_base_init();
388 NULL);
389 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
390 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
391 omap2xxx_check_revision(); 386 omap2xxx_check_revision();
392 omap2xxx_prm_init(); 387 omap2_prcm_base_init();
393 omap2xxx_cm_init();
394 omap2xxx_voltagedomains_init(); 388 omap2xxx_voltagedomains_init();
395 omap242x_powerdomains_init(); 389 omap242x_powerdomains_init();
396 omap242x_clockdomains_init(); 390 omap242x_clockdomains_init();
@@ -414,13 +408,9 @@ void __init omap2430_init_early(void)
414 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 408 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
415 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 409 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
416 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 410 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
417 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 411 omap2_control_base_init();
418 NULL);
419 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
420 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
421 omap2xxx_check_revision(); 412 omap2xxx_check_revision();
422 omap2xxx_prm_init(); 413 omap2_prcm_base_init();
423 omap2xxx_cm_init();
424 omap2xxx_voltagedomains_init(); 414 omap2xxx_voltagedomains_init();
425 omap243x_powerdomains_init(); 415 omap243x_powerdomains_init();
426 omap243x_clockdomains_init(); 416 omap243x_clockdomains_init();
@@ -448,21 +438,30 @@ void __init omap3_init_early(void)
448 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 438 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
449 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 439 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
450 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 440 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
451 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 441 /* XXX: remove these once OMAP3 is DT only */
452 NULL); 442 if (!of_have_populated_dt()) {
453 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 443 omap2_set_globals_control(
454 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 444 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
445 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
446 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
447 NULL);
448 }
449 omap2_control_base_init();
455 omap3xxx_check_revision(); 450 omap3xxx_check_revision();
456 omap3xxx_check_features(); 451 omap3xxx_check_features();
457 omap3xxx_prm_init(); 452 omap2_prcm_base_init();
458 omap3xxx_cm_init(); 453 /* XXX: remove these once OMAP3 is DT only */
454 if (!of_have_populated_dt()) {
455 omap3xxx_prm_init(NULL);
456 omap3xxx_cm_init(NULL);
457 }
459 omap3xxx_voltagedomains_init(); 458 omap3xxx_voltagedomains_init();
460 omap3xxx_powerdomains_init(); 459 omap3xxx_powerdomains_init();
461 omap3xxx_clockdomains_init(); 460 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init(); 461 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup(); 462 omap_hwmod_init_postsetup();
464 if (!of_have_populated_dt()) { 463 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init(); 464 omap3_control_legacy_iomap_init();
466 if (soc_is_am35xx()) 465 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init; 466 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630()) 467 else if (cpu_is_omap3630())
@@ -549,14 +548,10 @@ void __init ti814x_init_early(void)
549{ 548{
550 omap2_set_globals_tap(TI814X_CLASS, 549 omap2_set_globals_tap(TI814X_CLASS,
551 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
552 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 551 omap2_control_base_init();
553 NULL);
554 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
555 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
556 omap3xxx_check_revision(); 552 omap3xxx_check_revision();
557 ti81xx_check_features(); 553 ti81xx_check_features();
558 am33xx_prm_init(); 554 omap2_prcm_base_init();
559 am33xx_cm_init();
560 omap3xxx_voltagedomains_init(); 555 omap3xxx_voltagedomains_init();
561 omap3xxx_powerdomains_init(); 556 omap3xxx_powerdomains_init();
562 ti81xx_clockdomains_init(); 557 ti81xx_clockdomains_init();
@@ -570,14 +565,10 @@ void __init ti816x_init_early(void)
570{ 565{
571 omap2_set_globals_tap(TI816X_CLASS, 566 omap2_set_globals_tap(TI816X_CLASS,
572 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 567 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
573 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 568 omap2_control_base_init();
574 NULL);
575 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
576 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
577 omap3xxx_check_revision(); 569 omap3xxx_check_revision();
578 ti81xx_check_features(); 570 ti81xx_check_features();
579 am33xx_prm_init(); 571 omap2_prcm_base_init();
580 am33xx_cm_init();
581 omap3xxx_voltagedomains_init(); 572 omap3xxx_voltagedomains_init();
582 omap3xxx_powerdomains_init(); 573 omap3xxx_powerdomains_init();
583 ti81xx_clockdomains_init(); 574 ti81xx_clockdomains_init();
@@ -593,14 +584,10 @@ void __init am33xx_init_early(void)
593{ 584{
594 omap2_set_globals_tap(AM335X_CLASS, 585 omap2_set_globals_tap(AM335X_CLASS,
595 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 586 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
596 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 587 omap2_control_base_init();
597 NULL);
598 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
599 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
600 omap3xxx_check_revision(); 588 omap3xxx_check_revision();
601 am33xx_check_features(); 589 am33xx_check_features();
602 am33xx_prm_init(); 590 omap2_prcm_base_init();
603 am33xx_cm_init();
604 am33xx_powerdomains_init(); 591 am33xx_powerdomains_init();
605 am33xx_clockdomains_init(); 592 am33xx_clockdomains_init();
606 am33xx_hwmod_init(); 593 am33xx_hwmod_init();
@@ -619,16 +606,10 @@ void __init am43xx_init_early(void)
619{ 606{
620 omap2_set_globals_tap(AM335X_CLASS, 607 omap2_set_globals_tap(AM335X_CLASS,
621 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 608 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
622 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 609 omap2_control_base_init();
623 NULL);
624 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
625 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
626 omap_prm_base_init();
627 omap_cm_base_init();
628 omap3xxx_check_revision(); 610 omap3xxx_check_revision();
629 am33xx_check_features(); 611 am33xx_check_features();
630 omap44xx_prm_init(); 612 omap2_prcm_base_init();
631 omap4_cm_init();
632 am43xx_powerdomains_init(); 613 am43xx_powerdomains_init();
633 am43xx_clockdomains_init(); 614 am43xx_clockdomains_init();
634 am43xx_hwmod_init(); 615 am43xx_hwmod_init();
@@ -648,19 +629,12 @@ void __init omap4430_init_early(void)
648{ 629{
649 omap2_set_globals_tap(OMAP443X_CLASS, 630 omap2_set_globals_tap(OMAP443X_CLASS,
650 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 631 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
651 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
652 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
653 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
654 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
655 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
656 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 632 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
657 omap_prm_base_init(); 633 omap2_control_base_init();
658 omap_cm_base_init();
659 omap4xxx_check_revision(); 634 omap4xxx_check_revision();
660 omap4xxx_check_features(); 635 omap4xxx_check_features();
661 omap4_cm_init(); 636 omap2_prcm_base_init();
662 omap4_pm_init_early(); 637 omap4_pm_init_early();
663 omap44xx_prm_init();
664 omap44xx_voltagedomains_init(); 638 omap44xx_voltagedomains_init();
665 omap44xx_powerdomains_init(); 639 omap44xx_powerdomains_init();
666 omap44xx_clockdomains_init(); 640 omap44xx_clockdomains_init();
@@ -683,18 +657,11 @@ void __init omap5_init_early(void)
683{ 657{
684 omap2_set_globals_tap(OMAP54XX_CLASS, 658 omap2_set_globals_tap(OMAP54XX_CLASS,
685 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 659 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
686 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
687 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
688 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
689 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
690 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
691 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 660 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
661 omap2_control_base_init();
692 omap4_pm_init_early(); 662 omap4_pm_init_early();
693 omap_prm_base_init(); 663 omap2_prcm_base_init();
694 omap_cm_base_init();
695 omap44xx_prm_init();
696 omap5xxx_check_revision(); 664 omap5xxx_check_revision();
697 omap4_cm_init();
698 omap54xx_voltagedomains_init(); 665 omap54xx_voltagedomains_init();
699 omap54xx_powerdomains_init(); 666 omap54xx_powerdomains_init();
700 omap54xx_clockdomains_init(); 667 omap54xx_clockdomains_init();
@@ -715,18 +682,11 @@ void __init omap5_init_late(void)
715void __init dra7xx_init_early(void) 682void __init dra7xx_init_early(void)
716{ 683{
717 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 684 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
718 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
719 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
720 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
721 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
722 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
723 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 685 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
686 omap2_control_base_init();
724 omap4_pm_init_early(); 687 omap4_pm_init_early();
725 omap_prm_base_init(); 688 omap2_prcm_base_init();
726 omap_cm_base_init();
727 omap44xx_prm_init();
728 dra7xxx_check_revision(); 689 dra7xxx_check_revision();
729 omap4_cm_init();
730 dra7xx_powerdomains_init(); 690 dra7xx_powerdomains_init();
731 dra7xx_clockdomains_init(); 691 dra7xx_clockdomains_init();
732 dra7xx_hwmod_init(); 692 dra7xx_hwmod_init();
@@ -764,7 +724,11 @@ int __init omap_clk_init(void)
764 ti_clk_init_features(); 724 ti_clk_init_features();
765 725
766 if (of_have_populated_dt()) { 726 if (of_have_populated_dt()) {
767 ret = of_prcm_init(); 727 ret = omap_control_init();
728 if (ret)
729 return ret;
730
731 ret = omap_prcm_init();
768 if (ret) 732 if (ret)
769 return ret; 733 return ret;
770 734
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 78064b0d4db5..176eef6ef338 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1053,7 +1053,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
1053 struct omap_mux *entry; 1053 struct omap_mux *entry;
1054 1054
1055#ifdef CONFIG_OMAP_MUX 1055#ifdef CONFIG_OMAP_MUX
1056 if (!superset->muxnames || !superset->muxnames[0]) { 1056 if (!superset->muxnames[0]) {
1057 superset++; 1057 superset++;
1058 continue; 1058 continue;
1059 } 1059 }
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index dec2b05d184b..af2851fbcdf0 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -70,13 +70,6 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
70extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); 70extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
71extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); 71extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
72 72
73#ifdef CONFIG_OMAP4_ERRATA_I688
74extern int omap_barrier_reserve_memblock(void);
75#else
76static inline void omap_barrier_reserve_memblock(void)
77{ }
78#endif
79
80#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 73#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
81void set_cntfreq(void); 74void set_cntfreq(void);
82#else 75#else
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index cee0fe1ee6ff..afaac9e25764 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -52,75 +52,6 @@ static void __iomem *twd_base;
52 52
53#define IRQ_LOCALTIMER 29 53#define IRQ_LOCALTIMER 29
54 54
55#ifdef CONFIG_OMAP4_ERRATA_I688
56/* Used to implement memory barrier on DRAM path */
57#define OMAP4_DRAM_BARRIER_VA 0xfe600000
58
59void __iomem *dram_sync, *sram_sync;
60
61static phys_addr_t paddr;
62static u32 size;
63
64void omap_bus_sync(void)
65{
66 if (dram_sync && sram_sync) {
67 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
68 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
69 isb();
70 }
71}
72EXPORT_SYMBOL(omap_bus_sync);
73
74static int __init omap4_sram_init(void)
75{
76 struct device_node *np;
77 struct gen_pool *sram_pool;
78
79 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
80 if (!np)
81 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
82 __func__);
83 sram_pool = of_get_named_gen_pool(np, "sram", 0);
84 if (!sram_pool)
85 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
86 __func__);
87 else
88 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
89
90 return 0;
91}
92omap_arch_initcall(omap4_sram_init);
93
94/* Steal one page physical memory for barrier implementation */
95int __init omap_barrier_reserve_memblock(void)
96{
97
98 size = ALIGN(PAGE_SIZE, SZ_1M);
99 paddr = arm_memblock_steal(size, SZ_1M);
100
101 return 0;
102}
103
104void __init omap_barriers_init(void)
105{
106 struct map_desc dram_io_desc[1];
107
108 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
109 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
110 dram_io_desc[0].length = size;
111 dram_io_desc[0].type = MT_MEMORY_RW_SO;
112 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
113 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
114
115 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
116 (long long) paddr, dram_io_desc[0].virtual);
117
118}
119#else
120void __init omap_barriers_init(void)
121{}
122#endif
123
124void gic_dist_disable(void) 55void gic_dist_disable(void)
125{ 56{
126 if (gic_dist_base_addr) 57 if (gic_dist_base_addr)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a03aa2..b1aad7e1426c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
75 75
76 /* Clear old wake-up events */ 76 /* Clear old wake-up events */
77 /* REVISIT: These write to reserved bits? */ 77 /* REVISIT: These write to reserved bits? */
78 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 78 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
79 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 79 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
80 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); 80 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
81 81
82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); 82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
104 clk_enable(osc_ck); 104 clk_enable(osc_ck);
105 105
106 /* clear CORE wake-up events */ 106 /* clear CORE wake-up events */
107 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 107 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
108 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 108 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
109 109
110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ 110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
111 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); 111 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
112 112
113 /* MPU domain wake events */ 113 /* MPU domain wake events */
114 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 114 omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
115 0x1);
116 115
117 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 116 omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
118 0x20);
119 117
120 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 118 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
121 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); 119 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
143 * it is in retention mode. */ 141 * it is in retention mode. */
144 if (omap2_allow_mpu_retention()) { 142 if (omap2_allow_mpu_retention()) {
145 /* REVISIT: These write to reserved bits? */ 143 /* REVISIT: These write to reserved bits? */
146 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 144 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
147 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 145 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
148 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); 146 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
149 147
150 /* Try to enter MPU retention */ 148 /* Try to enter MPU retention */
151 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 149 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df6001d..87b98bf92366 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
137{ 137{
138 int c; 138 int c;
139 139
140 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, 140 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
141 ~(OMAP3430_ST_IO_MASK | 141 OMAP3430_ST_IO_CHAIN_MASK);
142 OMAP3430_ST_IO_CHAIN_MASK));
143 142
144 return c ? IRQ_HANDLED : IRQ_NONE; 143 return c ? IRQ_HANDLED : IRQ_NONE;
145} 144}
@@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
153 * these are handled in a separate handler to avoid acking 152 * these are handled in a separate handler to avoid acking
154 * IO events before parsing in mux code 153 * IO events before parsing in mux code
155 */ 154 */
156 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, 155 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
157 OMAP3430_ST_IO_MASK | 156 OMAP3430_ST_IO_CHAIN_MASK));
158 OMAP3430_ST_IO_CHAIN_MASK); 157 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
159 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0); 158 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
160 c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
161 if (omap_rev() > OMAP3430_REV_ES1_0) { 159 if (omap_rev() > OMAP3430_REV_ES1_0) {
162 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0); 160 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
163 c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 161 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
164 } 162 }
165 163
166 return c ? IRQ_HANDLED : IRQ_NONE; 164 return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6163d66102a3..6ae0b3a1781e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
518 .priority = _priority \ 518 .priority = _priority \
519 } 519 }
520 520
521/**
522 * struct omap_prcm_init_data - PRCM driver init data
523 * @index: clock memory mapping index to be used
524 * @mem: IO mem pointer for this module
525 * @offset: module base address offset from the IO base
526 * @flags: PRCM module init flags
527 * @device_inst_offset: device instance offset within the module address space
528 * @init: low level PRCM init function for this module
529 * @np: device node for this PRCM module
530 */
531struct omap_prcm_init_data {
532 int index;
533 void __iomem *mem;
534 s16 offset;
535 u16 flags;
536 s32 device_inst_offset;
537 int (*init)(const struct omap_prcm_init_data *data);
538 struct device_node *np;
539};
540
521extern void omap_prcm_irq_cleanup(void); 541extern void omap_prcm_irq_cleanup(void);
522extern int omap_prcm_register_chain_handler( 542extern int omap_prcm_register_chain_handler(
523 struct omap_prcm_irq_setup *irq_setup); 543 struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6a2db8..233bc84fbc0e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,8 +19,9 @@
19extern void __iomem *prm_base; 19extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int omap_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void); 23int omap2_prm_base_init(void);
24int omap2_prcm_base_init(void);
24# endif 25# endif
25 26
26/* 27/*
@@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
28 * 29 *
29 * PRM_HAS_IO_WAKEUP: has IO wakeup capability 30 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
30 * PRM_HAS_VOLTAGE: has voltage domains 31 * PRM_HAS_VOLTAGE: has voltage domains
32 * PRM_IRQ_DEFAULT: use default irq number for PRM irq
31 */ 33 */
32#define PRM_HAS_IO_WAKEUP (1 << 0) 34#define PRM_HAS_IO_WAKEUP BIT(0)
33#define PRM_HAS_VOLTAGE (1 << 1) 35#define PRM_HAS_VOLTAGE BIT(1)
36#define PRM_IRQ_DEFAULT BIT(2)
34 37
35/* 38/*
36 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 39 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -146,6 +149,9 @@ struct prm_ll_data {
146 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, 149 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
147 u16 offset); 150 u16 offset);
148 void (*reset_system)(void); 151 void (*reset_system)(void);
152 int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
153 u32 (*vp_check_txdone)(u8 vp_id);
154 void (*vp_clear_txdone)(u8 vp_id);
149}; 155};
150 156
151extern int prm_register(struct prm_ll_data *pld); 157extern int prm_register(struct prm_ll_data *pld);
@@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
161void omap_prm_reset_system(void); 167void omap_prm_reset_system(void);
162 168
163void omap_prm_reconfigure_io_chain(void); 169void omap_prm_reconfigure_io_chain(void);
170int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
171
172/*
173 * Voltage Processor (VP) identifiers
174 */
175#define OMAP3_VP_VDD_MPU_ID 0
176#define OMAP3_VP_VDD_CORE_ID 1
177#define OMAP4_VP_VDD_CORE_ID 0
178#define OMAP4_VP_VDD_IVA_ID 1
179#define OMAP4_VP_VDD_MPU_ID 2
180
181u32 omap_prm_vp_check_txdone(u8 vp_id);
182void omap_prm_vp_clear_txdone(u8 vp_id);
164 183
165#endif 184#endif
166 185
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index af0f15278fc2..752018ce129c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
123 * Clears wakeup status bits for a given module, so that the device can 123 * Clears wakeup status bits for a given module, so that the device can
124 * re-enter idle. 124 * re-enter idle.
125 */ 125 */
126void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) 126static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
127{ 127{
128 u32 wkst; 128 u32 wkst;
129 129
130 wkst = omap2_prm_read_mod_reg(module, regs); 130 wkst = omap2_prm_read_mod_reg(module, regs);
131 wkst &= wkst_mask; 131 wkst &= wkst_mask;
132 omap2_prm_write_mod_reg(wkst, module, regs); 132 omap2_prm_write_mod_reg(wkst, module, regs);
133 return 0;
133} 134}
134 135
135int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) 136int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
216 .deassert_hardreset = &omap2_prm_deassert_hardreset, 217 .deassert_hardreset = &omap2_prm_deassert_hardreset,
217 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, 218 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
218 .reset_system = &omap2xxx_prm_dpll_reset, 219 .reset_system = &omap2xxx_prm_dpll_reset,
220 .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
219}; 221};
220 222
221int __init omap2xxx_prm_init(void) 223int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
222{ 224{
223 return prm_register(&omap2xxx_prm_ll_data); 225 return prm_register(&omap2xxx_prm_ll_data);
224} 226}
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 1d51643062f7..9008a9e55a1a 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,9 +124,7 @@
124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); 124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); 125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
126 126
127void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 127int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
128
129extern int __init omap2xxx_prm_init(void);
130 128
131#endif 129#endif
132 130
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 02f628601b09..dcb5001d77da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
378 .reset_system = am33xx_prm_global_warm_sw_reset, 378 .reset_system = am33xx_prm_global_warm_sw_reset,
379}; 379};
380 380
381int __init am33xx_prm_init(void) 381int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
382{ 382{
383 return prm_register(&am33xx_prm_ll_data); 383 return prm_register(&am33xx_prm_ll_data);
384} 384}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 98ac41f271da..2bc4ec52ba78 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,7 +118,7 @@
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119 119
120#ifndef __ASSEMBLER__ 120#ifndef __ASSEMBLER__
121int am33xx_prm_init(void); 121int am33xx_prm_init(const struct omap_prcm_init_data *data);
122 122
123#endif /* ASSEMBLER */ 123#endif /* ASSEMBLER */
124#endif 124#endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbdf83bc..62680aad2126 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -29,6 +29,7 @@
29#include "prm-regbits-34xx.h" 29#include "prm-regbits-34xx.h"
30#include "cm3xxx.h" 30#include "cm3xxx.h"
31#include "cm-regbits-34xx.h" 31#include "cm-regbits-34xx.h"
32#include "clock.h"
32 33
33static void omap3xxx_prm_read_pending_irqs(unsigned long *events); 34static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
34static void omap3xxx_prm_ocp_barrier(void); 35static void omap3xxx_prm_ocp_barrier(void);
@@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
96 97
97#define MAX_VP_ID ARRAY_SIZE(omap3_vp); 98#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
98 99
99u32 omap3_prm_vp_check_txdone(u8 vp_id) 100static u32 omap3_prm_vp_check_txdone(u8 vp_id)
100{ 101{
101 struct omap3_vp *vp = &omap3_vp[vp_id]; 102 struct omap3_vp *vp = &omap3_vp[vp_id];
102 u32 irqstatus; 103 u32 irqstatus;
@@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
106 return irqstatus & vp->tranxdone_status; 107 return irqstatus & vp->tranxdone_status;
107} 108}
108 109
109void omap3_prm_vp_clear_txdone(u8 vp_id) 110static void omap3_prm_vp_clear_txdone(u8 vp_id)
110{ 111{
111 struct omap3_vp *vp = &omap3_vp[vp_id]; 112 struct omap3_vp *vp = &omap3_vp[vp_id];
112 113
@@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
217 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt 218 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
218 * @module: PRM module to clear wakeups from 219 * @module: PRM module to clear wakeups from
219 * @regs: register set to clear, 1 or 3 220 * @regs: register set to clear, 1 or 3
220 * @ignore_bits: wakeup status bits to ignore 221 * @wkst_mask: wkst bits to clear
221 * 222 *
222 * The purpose of this function is to clear any wake-up events latched 223 * The purpose of this function is to clear any wake-up events latched
223 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 224 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
226 * that any peripheral wake-up events occurring while attempting to 227 * that any peripheral wake-up events occurring while attempting to
227 * clear the PM_WKST_x are detected and cleared. 228 * clear the PM_WKST_x are detected and cleared.
228 */ 229 */
229int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) 230static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
230{ 231{
231 u32 wkst, fclk, iclk, clken; 232 u32 wkst, fclk, iclk, clken;
232 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 233 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
238 239
239 wkst = omap2_prm_read_mod_reg(module, wkst_off); 240 wkst = omap2_prm_read_mod_reg(module, wkst_off);
240 wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 241 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
241 wkst &= ~ignore_bits; 242 wkst &= wkst_mask;
242 if (wkst) { 243 if (wkst) {
243 iclk = omap2_cm_read_mod_reg(module, iclk_off); 244 iclk = omap2_cm_read_mod_reg(module, iclk_off);
244 fclk = omap2_cm_read_mod_reg(module, fclk_off); 245 fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
254 omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 255 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
255 omap2_prm_write_mod_reg(wkst, module, wkst_off); 256 omap2_prm_write_mod_reg(wkst, module, wkst_off);
256 wkst = omap2_prm_read_mod_reg(module, wkst_off); 257 wkst = omap2_prm_read_mod_reg(module, wkst_off);
257 wkst &= ~ignore_bits; 258 wkst &= wkst_mask;
258 c++; 259 c++;
259 } 260 }
260 omap2_cm_write_mod_reg(iclk, module, iclk_off); 261 omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
664 .deassert_hardreset = &omap2_prm_deassert_hardreset, 665 .deassert_hardreset = &omap2_prm_deassert_hardreset,
665 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, 666 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
666 .reset_system = &omap3xxx_prm_dpll3_reset, 667 .reset_system = &omap3xxx_prm_dpll3_reset,
668 .clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
669 .vp_check_txdone = &omap3_prm_vp_check_txdone,
670 .vp_clear_txdone = &omap3_prm_vp_clear_txdone,
667}; 671};
668 672
669int __init omap3xxx_prm_init(void) 673int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
670{ 674{
675 omap2_clk_legacy_provider_init(TI_CLKM_PRM,
676 prm_base + OMAP3430_IVA2_MOD);
671 if (omap3_has_io_wakeup()) 677 if (omap3_has_io_wakeup())
672 prm_features |= PRM_HAS_IO_WAKEUP; 678 prm_features |= PRM_HAS_IO_WAKEUP;
673 679
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8b739a..5f095eec339c 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
132 132
133#ifndef __ASSEMBLER__ 133#ifndef __ASSEMBLER__
134 134
135/* OMAP3-specific VP functions */
136u32 omap3_prm_vp_check_txdone(u8 vp_id);
137void omap3_prm_vp_clear_txdone(u8 vp_id);
138
139/* 135/*
140 * OMAP3 access functions for voltage controller (VC) and 136 * OMAP3 access functions for voltage controller (VC) and
141 * voltage proccessor (VP) in the PRM. 137 * voltage proccessor (VP) in the PRM.
@@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
144extern void omap3_prm_vcvp_write(u32 val, u8 offset); 140extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 141extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146 142
147extern int __init omap3xxx_prm_init(void); 143int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
148int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
149void omap3xxx_prm_iva_idle(void); 144void omap3xxx_prm_iva_idle(void);
150void omap3_prm_reset_modem(void); 145void omap3_prm_reset_modem(void);
151int omap3xxx_prm_clear_global_cold_reset(void); 146int omap3xxx_prm_clear_global_cold_reset(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a08a617a6c11..c35ad0bedf81 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
138 }, 138 },
139}; 139};
140 140
141u32 omap4_prm_vp_check_txdone(u8 vp_id) 141static u32 omap4_prm_vp_check_txdone(u8 vp_id)
142{ 142{
143 struct omap4_vp *vp = &omap4_vp[vp_id]; 143 struct omap4_vp *vp = &omap4_vp[vp_id];
144 u32 irqstatus; 144 u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
149 return irqstatus & vp->tranxdone_status; 149 return irqstatus & vp->tranxdone_status;
150} 150}
151 151
152void omap4_prm_vp_clear_txdone(u8 vp_id) 152static void omap4_prm_vp_clear_txdone(u8 vp_id)
153{ 153{
154 struct omap4_vp *vp = &omap4_vp[vp_id]; 154 struct omap4_vp *vp = &omap4_vp[vp_id];
155 155
@@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
699 .deassert_hardreset = omap4_prminst_deassert_hardreset, 699 .deassert_hardreset = omap4_prminst_deassert_hardreset,
700 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, 700 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
701 .reset_system = omap4_prminst_global_warm_sw_reset, 701 .reset_system = omap4_prminst_global_warm_sw_reset,
702 .vp_check_txdone = omap4_prm_vp_check_txdone,
703 .vp_clear_txdone = omap4_prm_vp_clear_txdone,
702}; 704};
703 705
704int __init omap44xx_prm_init(void) 706static const struct omap_prcm_init_data *prm_init_data;
707
708int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
705{ 709{
706 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) 710 omap_prm_base_init();
711
712 prm_init_data = data;
713
714 if (data->flags & PRM_HAS_IO_WAKEUP)
707 prm_features |= PRM_HAS_IO_WAKEUP; 715 prm_features |= PRM_HAS_IO_WAKEUP;
708 716
709 if (!soc_is_dra7xx()) 717 if (data->flags & PRM_HAS_VOLTAGE)
710 prm_features |= PRM_HAS_VOLTAGE; 718 prm_features |= PRM_HAS_VOLTAGE;
711 719
720 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
721
712 return prm_register(&omap44xx_prm_ll_data); 722 return prm_register(&omap44xx_prm_ll_data);
713} 723}
714 724
715static const struct of_device_id omap_prm_dt_match_table[] = {
716 { .compatible = "ti,omap4-prm" },
717 { .compatible = "ti,omap5-prm" },
718 { .compatible = "ti,dra7-prm" },
719 { }
720};
721
722static int omap44xx_prm_late_init(void) 725static int omap44xx_prm_late_init(void)
723{ 726{
724 struct device_node *np;
725 int irq_num; 727 int irq_num;
726 728
727 if (!(prm_features & PRM_HAS_IO_WAKEUP)) 729 if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
731 if (!of_have_populated_dt()) 733 if (!of_have_populated_dt())
732 return 0; 734 return 0;
733 735
734 np = of_find_matching_node(NULL, omap_prm_dt_match_table); 736 irq_num = of_irq_get(prm_init_data->np, 0);
735 737 /*
736 if (!np) { 738 * Already have OMAP4 IRQ num. For all other platforms, we need
737 /* Default loaded up with OMAP4 values */ 739 * IRQ numbers from DT
738 if (!cpu_is_omap44xx()) 740 */
739 return 0; 741 if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
740 } else { 742 if (irq_num == -EPROBE_DEFER)
741 irq_num = of_irq_get(np, 0); 743 return irq_num;
742 /* 744
743 * Already have OMAP4 IRQ num. For all other platforms, we need 745 /* Have nothing to do */
744 * IRQ numbers from DT 746 return 0;
745 */ 747 }
746 if (irq_num < 0 && !cpu_is_omap44xx()) { 748
747 if (irq_num == -EPROBE_DEFER) 749 /* Once OMAP4 DT is filled as well */
748 return irq_num; 750 if (irq_num >= 0) {
749 751 omap4_prcm_irq_setup.irq = irq_num;
750 /* Have nothing to do */ 752 omap4_prcm_irq_setup.xlate_irq = NULL;
751 return 0;
752 }
753
754 /* Once OMAP4 DT is filled as well */
755 if (irq_num >= 0) {
756 omap4_prcm_irq_setup.irq = irq_num;
757 omap4_prcm_irq_setup.xlate_irq = NULL;
758 }
759 } 753 }
760 754
761 omap44xx_prm_enable_io_wakeup(); 755 omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422faa16..efd6035d0871 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,6 @@
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27 27
28#include "prm44xx_54xx.h" 28#include "prm44xx_54xx.h"
29#include "prcm-common.h"
30#include "prm.h" 29#include "prm.h"
31 30
32#define OMAP4430_PRM_BASE 0x4a306000 31#define OMAP4430_PRM_BASE 0x4a306000
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 714329565b90..3f139ebc8398 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -23,13 +23,11 @@
23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H 24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
25 25
26#include "prcm-common.h"
27
26/* Function prototypes */ 28/* Function prototypes */
27#ifndef __ASSEMBLER__ 29#ifndef __ASSEMBLER__
28 30
29/* OMAP4/OMAP5-specific VP functions */
30u32 omap4_prm_vp_check_txdone(u8 vp_id);
31void omap4_prm_vp_clear_txdone(u8 vp_id);
32
33/* 31/*
34 * OMAP4/OMAP5 access functions for voltage controller (VC) and 32 * OMAP4/OMAP5 access functions for voltage controller (VC) and
35 * voltage proccessor (VP) in the PRM. 33 * voltage proccessor (VP) in the PRM.
@@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
38extern void omap4_prm_vcvp_write(u32 val, u8 offset); 36extern void omap4_prm_vcvp_write(u32 val, u8 offset);
39extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 37extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
40 38
41extern int __init omap44xx_prm_init(void); 39int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
42 40
43#endif 41#endif
44 42
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e4411010309c..1eb22ff087dc 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,6 @@
22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H 22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
23 23
24#include "prm44xx_54xx.h" 24#include "prm44xx_54xx.h"
25#include "prcm-common.h"
26#include "prm.h" 25#include "prm.h"
27 26
28#define OMAP54XX_PRM_BASE 0x4ae06000 27#define OMAP54XX_PRM_BASE 0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 4bb50fbf29be..cc1e6a2b97f6 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,8 +22,8 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
24 24
25#include "prm44xx_54xx.h"
26#include "prcm-common.h" 25#include "prcm-common.h"
26#include "prm44xx_54xx.h"
27#include "prm.h" 27#include "prm.h"
28 28
29#define DRA7XX_PRM_BASE 0x4ae06000 29#define DRA7XX_PRM_BASE 0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba595cc..7add7994dbfc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,11 @@
32#include "prm2xxx_3xxx.h" 32#include "prm2xxx_3xxx.h"
33#include "prm2xxx.h" 33#include "prm2xxx.h"
34#include "prm3xxx.h" 34#include "prm3xxx.h"
35#include "prm33xx.h"
35#include "prm44xx.h" 36#include "prm44xx.h"
37#include "prm54xx.h"
38#include "prm7xx.h"
39#include "prcm43xx.h"
36#include "common.h" 40#include "common.h"
37#include "clock.h" 41#include "clock.h"
38#include "cm.h" 42#include "cm.h"
@@ -534,6 +538,61 @@ void omap_prm_reset_system(void)
534} 538}
535 539
536/** 540/**
541 * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
542 * @module: PRM module to clear wakeups from
543 * @regs: register to clear
544 * @wkst_mask: wkst bits to clear
545 *
546 * Clears any wakeup events for the module and register set defined.
547 * Uses SoC specific implementation to do the actual wakeup status
548 * clearing.
549 */
550int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
551{
552 if (!prm_ll_data->clear_mod_irqs) {
553 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
554 __func__);
555 return -EINVAL;
556 }
557
558 return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
559}
560
561/**
562 * omap_prm_vp_check_txdone - check voltage processor TX done status
563 *
564 * Checks if voltage processor transmission has been completed.
565 * Returns non-zero if a transmission has completed, 0 otherwise.
566 */
567u32 omap_prm_vp_check_txdone(u8 vp_id)
568{
569 if (!prm_ll_data->vp_check_txdone) {
570 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
571 __func__);
572 return 0;
573 }
574
575 return prm_ll_data->vp_check_txdone(vp_id);
576}
577
578/**
579 * omap_prm_vp_clear_txdone - clears voltage processor TX done status
580 *
581 * Clears the status bit for completed voltage processor transmission
582 * returned by prm_vp_check_txdone.
583 */
584void omap_prm_vp_clear_txdone(u8 vp_id)
585{
586 if (!prm_ll_data->vp_clear_txdone) {
587 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
588 __func__);
589 return;
590 }
591
592 prm_ll_data->vp_clear_txdone(vp_id);
593}
594
595/**
537 * prm_register - register per-SoC low-level data with the PRM 596 * prm_register - register per-SoC low-level data with the PRM
538 * @pld: low-level per-SoC OMAP PRM data & function pointers to register 597 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
539 * 598 *
@@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
578 return 0; 637 return 0;
579} 638}
580 639
581static const struct of_device_id omap_prcm_dt_match_table[] = { 640#ifdef CONFIG_ARCH_OMAP2
582 { .compatible = "ti,am3-prcm" }, 641static struct omap_prcm_init_data omap2_prm_data __initdata = {
583 { .compatible = "ti,am3-scrm" }, 642 .index = TI_CLKM_PRM,
584 { .compatible = "ti,am4-prcm" }, 643 .init = omap2xxx_prm_init,
585 { .compatible = "ti,am4-scrm" },
586 { .compatible = "ti,dm814-prcm" },
587 { .compatible = "ti,dm814-scrm" },
588 { .compatible = "ti,dm816-prcm" },
589 { .compatible = "ti,dm816-scrm" },
590 { .compatible = "ti,omap2-prcm" },
591 { .compatible = "ti,omap2-scrm" },
592 { .compatible = "ti,omap3-prm" },
593 { .compatible = "ti,omap3-cm" },
594 { .compatible = "ti,omap3-scrm" },
595 { .compatible = "ti,omap4-cm1" },
596 { .compatible = "ti,omap4-prm" },
597 { .compatible = "ti,omap4-cm2" },
598 { .compatible = "ti,omap4-scrm" },
599 { .compatible = "ti,omap5-prm" },
600 { .compatible = "ti,omap5-cm-core-aon" },
601 { .compatible = "ti,omap5-scrm" },
602 { .compatible = "ti,omap5-cm-core" },
603 { .compatible = "ti,dra7-prm" },
604 { .compatible = "ti,dra7-cm-core-aon" },
605 { .compatible = "ti,dra7-cm-core" },
606 { }
607}; 644};
645#endif
646
647#ifdef CONFIG_ARCH_OMAP3
648static struct omap_prcm_init_data omap3_prm_data __initdata = {
649 .index = TI_CLKM_PRM,
650 .init = omap3xxx_prm_init,
608 651
609static struct clk_hw_omap memmap_dummy_ck = { 652 /*
610 .flags = MEMMAP_ADDRESSING, 653 * IVA2 offset is a negative value, must offset the prm_base
654 * address by this to get it to positive
655 */
656 .offset = -OMAP3430_IVA2_MOD,
611}; 657};
658#endif
612 659
613static u32 prm_clk_readl(void __iomem *reg) 660#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
614{ 661static struct omap_prcm_init_data am3_prm_data __initdata = {
615 return omap2_clk_readl(&memmap_dummy_ck, reg); 662 .index = TI_CLKM_PRM,
616} 663 .init = am33xx_prm_init,
664};
665#endif
666
667#ifdef CONFIG_ARCH_OMAP4
668static struct omap_prcm_init_data omap4_prm_data __initdata = {
669 .index = TI_CLKM_PRM,
670 .init = omap44xx_prm_init,
671 .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
672 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
673};
674#endif
675
676#ifdef CONFIG_SOC_OMAP5
677static struct omap_prcm_init_data omap5_prm_data __initdata = {
678 .index = TI_CLKM_PRM,
679 .init = omap44xx_prm_init,
680 .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
681 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
682};
683#endif
684
685#ifdef CONFIG_SOC_DRA7XX
686static struct omap_prcm_init_data dra7_prm_data __initdata = {
687 .index = TI_CLKM_PRM,
688 .init = omap44xx_prm_init,
689 .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
690 .flags = PRM_HAS_IO_WAKEUP,
691};
692#endif
617 693
618static void prm_clk_writel(u32 val, void __iomem *reg) 694#ifdef CONFIG_SOC_AM43XX
619{ 695static struct omap_prcm_init_data am4_prm_data __initdata = {
620 omap2_clk_writel(val, &memmap_dummy_ck, reg); 696 .index = TI_CLKM_PRM,
621} 697 .init = omap44xx_prm_init,
698 .device_inst_offset = AM43XX_PRM_DEVICE_INST,
699};
700#endif
622 701
623static struct ti_clk_ll_ops omap_clk_ll_ops = { 702#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
624 .clk_readl = prm_clk_readl, 703static struct omap_prcm_init_data scrm_data __initdata = {
625 .clk_writel = prm_clk_writel, 704 .index = TI_CLKM_SCRM,
705};
706#endif
707
708static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
709#ifdef CONFIG_SOC_AM33XX
710 { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
711#endif
712#ifdef CONFIG_SOC_AM43XX
713 { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
714#endif
715#ifdef CONFIG_SOC_TI81XX
716 { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
717 { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
718#endif
719#ifdef CONFIG_ARCH_OMAP2
720 { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
721#endif
722#ifdef CONFIG_ARCH_OMAP3
723 { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
724#endif
725#ifdef CONFIG_ARCH_OMAP4
726 { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
727 { .compatible = "ti,omap4-scrm", .data = &scrm_data },
728#endif
729#ifdef CONFIG_SOC_OMAP5
730 { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
731 { .compatible = "ti,omap5-scrm", .data = &scrm_data },
732#endif
733#ifdef CONFIG_SOC_DRA7XX
734 { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
735#endif
736 { }
626}; 737};
627 738
628int __init of_prcm_init(void) 739/**
740 * omap2_prm_base_init - initialize iomappings for the PRM driver
741 *
742 * Detects and initializes the iomappings for the PRM driver, based
743 * on the DT data. Returns 0 in success, negative error value
744 * otherwise.
745 */
746int __init omap2_prm_base_init(void)
629{ 747{
630 struct device_node *np; 748 struct device_node *np;
749 const struct of_device_id *match;
750 struct omap_prcm_init_data *data;
631 void __iomem *mem; 751 void __iomem *mem;
632 int memmap_index = 0;
633 752
634 ti_clk_ll_ops = &omap_clk_ll_ops; 753 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
754 data = (struct omap_prcm_init_data *)match->data;
635 755
636 for_each_matching_node(np, omap_prcm_dt_match_table) {
637 mem = of_iomap(np, 0); 756 mem = of_iomap(np, 0);
638 clk_memmaps[memmap_index] = mem; 757 if (!mem)
639 ti_dt_clk_init_provider(np, memmap_index); 758 return -ENOMEM;
640 memmap_index++; 759
760 if (data->index == TI_CLKM_PRM)
761 prm_base = mem + data->offset;
762
763 data->mem = mem;
764
765 data->np = np;
766
767 if (data->init)
768 data->init(data);
641 } 769 }
642 770
643 return 0; 771 return 0;
644} 772}
645 773
646void __init omap3_prcm_legacy_iomaps_init(void) 774int __init omap2_prcm_base_init(void)
647{ 775{
648 ti_clk_ll_ops = &omap_clk_ll_ops; 776 int ret;
649 777
650 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD; 778 ret = omap2_prm_base_init();
651 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD; 779 if (ret)
652 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get(); 780 return ret;
781
782 return omap2_cm_base_init();
783}
784
785/**
786 * omap_prcm_init - low level init for the PRCM drivers
787 *
788 * Initializes the low level clock infrastructure for PRCM drivers.
789 * Returns 0 in success, negative error value in failure.
790 */
791int __init omap_prcm_init(void)
792{
793 struct device_node *np;
794 const struct of_device_id *match;
795 const struct omap_prcm_init_data *data;
796 int ret;
797
798 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
799 data = match->data;
800
801 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
802 if (ret)
803 return ret;
804 }
805
806 omap_cm_init();
807
808 return 0;
653} 809}
654 810
655static int __init prm_late_init(void) 811static int __init prm_late_init(void)
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1a1dce..c4859c4d3646 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
47 47
48s32 omap4_prmst_get_prm_dev_inst(void) 48s32 omap4_prmst_get_prm_dev_inst(void)
49{ 49{
50 if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
51 return prm_dev_inst;
52
53 /* This cannot be done way early at boot.. as things are not setup */
54 if (cpu_is_omap44xx())
55 prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
56 else if (soc_is_omap54xx())
57 prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
58 else if (soc_is_dra7xx())
59 prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
60 else if (soc_is_am43xx())
61 prm_dev_inst = AM43XX_PRM_DEVICE_INST;
62
63 return prm_dev_inst; 50 return prm_dev_inst;
64} 51}
65 52
53void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
54{
55 prm_dev_inst = dev_inst;
56}
57
66/* Read a register in a PRM instance */ 58/* Read a register in a PRM instance */
67u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 59u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
68{ 60{
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index fb1c9d7a2f9d..0c03d0731d7f 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -14,6 +14,7 @@
14 14
15#define PRM_INSTANCE_UNKNOWN -1 15#define PRM_INSTANCE_UNKNOWN -1
16extern s32 omap4_prmst_get_prm_dev_inst(void); 16extern s32 omap4_prmst_get_prm_dev_inst(void);
17void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
17 18
18/* 19/*
19 * In an ideal world, we would not export these low-level functions, 20 * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index b84a0122d823..ad1bb9431e94 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -333,11 +333,9 @@ ENDPROC(omap4_cpu_resume)
333 333
334#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */ 334#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
335 335
336#ifndef CONFIG_OMAP4_ERRATA_I688
337ENTRY(omap_bus_sync) 336ENTRY(omap_bus_sync)
338 ret lr 337 ret lr
339ENDPROC(omap_bus_sync) 338ENDPROC(omap_bus_sync)
340#endif
341 339
342ENTRY(omap_do_wfi) 340ENTRY(omap_do_wfi)
343 stmfd sp!, {lr} 341 stmfd sp!, {lr}
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080e4a6..7e0829682bd0 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
21 21
22struct voltagedomain; 22struct voltagedomain;
23 23
24/*
25 * Voltage Processor (VP) identifiers
26 */
27#define OMAP3_VP_VDD_MPU_ID 0
28#define OMAP3_VP_VDD_CORE_ID 1
29#define OMAP4_VP_VDD_CORE_ID 0
30#define OMAP4_VP_VDD_IVA_ID 1
31#define OMAP4_VP_VDD_MPU_ID 2
32
33/* XXX document */ 24/* XXX document */
34#define VP_IDLE_TIMEOUT 200 25#define VP_IDLE_TIMEOUT 200
35#define VP_TRANXDONE_TIMEOUT 300 26#define VP_TRANXDONE_TIMEOUT 300
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e026245e..b0590fe6ab01 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -28,8 +28,8 @@
28#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
29 29
30static const struct omap_vp_ops omap3_vp_ops = { 30static const struct omap_vp_ops omap3_vp_ops = {
31 .check_txdone = omap3_prm_vp_check_txdone, 31 .check_txdone = omap_prm_vp_check_txdone,
32 .clear_txdone = omap3_prm_vp_clear_txdone, 32 .clear_txdone = omap_prm_vp_clear_txdone,
33}; 33};
34 34
35/* 35/*
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index e62f6b018beb..2448bb9a8716 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -28,8 +28,8 @@
28#include "vp.h" 28#include "vp.h"
29 29
30static const struct omap_vp_ops omap4_vp_ops = { 30static const struct omap_vp_ops omap4_vp_ops = {
31 .check_txdone = omap4_prm_vp_check_txdone, 31 .check_txdone = omap_prm_vp_check_txdone,
32 .clear_txdone = omap4_prm_vp_clear_txdone, 32 .clear_txdone = omap_prm_vp_clear_txdone,
33}; 33};
34 34
35/* 35/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-05 18:01:14 -0400