284 files changed, 7578 insertions, 7032 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ade7e924bef5..041cf0774776 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -937,7 +937,6 @@ config ARCH_OMAP
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
-        select NEED_MACH_GPIO_H
         help
           Support for TI's OMAP platform (OMAP1/2/3/4).
 
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index cd169c386161..f0e69cbc5baa 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,8 @@
 #
 
 # Common support
-obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
+obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
+         serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index e255164ff087..a8fce3ccc707 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -625,7 +625,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         .atag_offset    = 0x100,
         .map_io         = ams_delta_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = ams_delta_init,
         .init_late      = ams_delta_init_late,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 4b6de70c47a6..e067f221f0f9 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -27,16 +27,16 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
 #include <mach/flash.h>
-#include <plat/fpga.h>
 #include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
+#include "fpga.h"
 
 /* fsample is pretty close to p2-sample */
 
@@ -123,9 +123,9 @@ static struct resource smc91x_resources[] = {
 
 static void __init fsample_init_smc91x(void)
 {
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
         mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+        __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
                    H2P2_DBG_FPGA_LAN_RESET);
         mdelay(50);
 }
@@ -362,7 +362,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
         .atag_offset    = 0x100,
         .map_io         = omap_fsample_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_fsample_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 4ec579fdd366..608e7d2a2778 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -81,7 +81,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
         .atag_offset    = 0x100,
         .map_io         = omap16xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index e1362ce48497..7119ef28e0ad 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -13,12 +13,11 @@
  */
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
-
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/i2c/tps65010.h>
 
-#include <plat/mmc.h>
-
 #include "board-h2.h"
+#include "mmc.h"
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 376f7f29ef77..9134b646f01b 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -39,8 +39,8 @@
 #include <asm/mach/map.h>
 
 #include <mach/mux.h>
-#include <plat/dma.h>
-#include <plat/tc.h>
+#include <plat-omap/dma-omap.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/flash.h>
@@ -50,6 +50,7 @@
 
 #include "common.h"
 #include "board-h2.h"
+#include "dma.h"
 
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
@@ -458,7 +459,6 @@ MACHINE_START(OMAP_H2, "TI-H2")
         .atag_offset    = 0x100,
         .map_io         = omap16xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = h2_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index c74daace8cd6..17d77914d769 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -16,9 +16,8 @@
 
 #include <linux/i2c/tps65010.h>
 
-#include <plat/mmc.h>
-
 #include "board-h3.h"
+#include "mmc.h"
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ededdb7ef28c..bf213d1d8075 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <linux/platform_data/keypad-omap.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 #include <mach/flash.h>
 
 #include <mach/hardware.h>
@@ -452,7 +452,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
         .atag_offset    = 0x100,
         .map_io         = omap16xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = h3_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 87ab2086ef96..356f816c84a6 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -43,7 +43,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/omap7xx.h>
-#include <plat/mmc.h>
+#include "mmc.h"
 
 #include <mach/irqs.h>
 #include <mach/usb.h>
@@ -600,7 +600,6 @@ MACHINE_START(HERALD, "HTC Herald")
         .atag_offset    = 0x100,
         .map_io         = htcherald_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = htcherald_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index db5f7d2976e7..f8033fab0f82 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -33,16 +33,15 @@
 
 #include <mach/mux.h>
 #include <mach/flash.h>
-#include <plat/fpga.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <linux/platform_data/keypad-omap.h>
-#include <plat/mmc.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "iomap.h"
 #include "common.h"
+#include "mmc.h"
 
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
@@ -215,7 +214,7 @@ static struct platform_device *innovator1510_devices[] __initdata = {
 
 static int innovator_get_pendown_state(void)
 {
-        return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
+        return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
 }
 
 static const struct ads7846_platform_data innovator1510_ts_info = {
@@ -279,7 +278,7 @@ static struct platform_device *innovator1610_devices[] __initdata = {
 static void __init innovator_init_smc91x(void)
 {
         if (cpu_is_omap1510()) {
-                fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1,
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1,
                            OMAP1510_FPGA_RST);
                 udelay(750);
         } else {
@@ -335,10 +334,10 @@ static int mmc_set_power(struct device *dev, int slot, int power_on,
                                 int vdd)
 {
         if (power_on)
-                fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3),
                                 OMAP1510_FPGA_POWER);
         else
-                fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3),
                                 OMAP1510_FPGA_POWER);
 
         return 0;
@@ -390,14 +389,14 @@ static void __init innovator_init(void)
                 omap_cfg_reg(UART3_TX);
                 omap_cfg_reg(UART3_RX);
 
-                reg = fpga_read(OMAP1510_FPGA_POWER);
+                reg = __raw_readb(OMAP1510_FPGA_POWER);
                 reg |= OMAP1510_FPGA_PCR_COM1_EN;
-                fpga_write(reg, OMAP1510_FPGA_POWER);
+                __raw_writeb(reg, OMAP1510_FPGA_POWER);
                 udelay(10);
 
-                reg = fpga_read(OMAP1510_FPGA_POWER);
+                reg = __raw_readb(OMAP1510_FPGA_POWER);
                 reg |= OMAP1510_FPGA_PCR_COM2_EN;
-                fpga_write(reg, OMAP1510_FPGA_POWER);
+                __raw_writeb(reg, OMAP1510_FPGA_POWER);
                 udelay(10);
 
                 platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
@@ -437,6 +436,7 @@ static void __init innovator_init(void)
  */
 static void __init innovator_map_io(void)
 {
+#ifdef CONFIG_ARCH_OMAP15XX
         omap15xx_map_io();
 
         iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
@@ -444,9 +444,10 @@ static void __init innovator_map_io(void)
 
         /* Dump the Innovator FPGA rev early - useful info for support. */
         pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
-                        fpga_read(OMAP1510_FPGA_REV_HIGH),
-                        fpga_read(OMAP1510_FPGA_REV_LOW),
-                        fpga_read(OMAP1510_FPGA_BOARD_REV));
+                        __raw_readb(OMAP1510_FPGA_REV_HIGH),
+                        __raw_readb(OMAP1510_FPGA_REV_LOW),
+                        __raw_readb(OMAP1510_FPGA_BOARD_REV));
+#endif
 }
 
 MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
@@ -454,7 +455,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
         .atag_offset    = 0x100,
         .map_io         = innovator_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = innovator_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7d5c06d6a52a..3e8ead67e459 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -29,13 +29,13 @@
 #include <asm/mach/map.h>
 
 #include <mach/mux.h>
-#include <plat/mmc.h>
-#include <plat/clock.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "common.h"
+#include "clock.h"
+#include "mmc.h"
 
 #define ADS7846_PENDOWN_GPIO    15
 
@@ -251,7 +251,6 @@ MACHINE_START(NOKIA770, "Nokia 770")
         .atag_offset    = 0x100,
         .map_io         = omap16xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_nokia770_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5973945a8741..872ea47cd28a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -48,7 +48,7 @@
 
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -606,7 +606,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
         .atag_offset    = 0x100,
         .map_io         = omap16xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = osk_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 1c578d58923a..584b6fab894b 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -36,8 +36,8 @@
 
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
-#include <plat/dma.h>
+#include <mach/tc.h>
+#include <plat-omap/dma-omap.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
@@ -45,6 +45,7 @@
 #include <mach/usb.h>
 
 #include "common.h"
+#include "dma.h"
 
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
@@ -264,7 +265,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
         .atag_offset    = 0x100,
         .map_io         = omap15xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_palmte_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 97158095083c..fbc986bfe69e 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -28,16 +28,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/platform_data/omap1_bl.h>
+#include <linux/platform_data/leds-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/led.h>
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
-#include <plat/tc.h>
+#include <plat-omap/dma-omap.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
@@ -45,6 +45,7 @@
 #include <mach/usb.h>
 
 #include "common.h"
+#include "dma.h"
 
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
@@ -310,7 +311,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
         .atag_offset    = 0x100,
         .map_io         = omap15xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_palmtt_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e311032e7eeb..60d917a93763 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -38,8 +38,8 @@
 
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
-#include <plat/tc.h>
+#include <plat-omap/dma-omap.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
@@ -47,6 +47,7 @@
 #include <mach/usb.h>
 
 #include "common.h"
+#include "dma.h"
 
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
@@ -326,7 +327,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
         .atag_offset    = 0x100,
         .map_io         = omap15xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_palmz71_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 198b05417bfc..9a7e483ed6fd 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -28,15 +28,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
-#include <plat/fpga.h>
 #include <mach/flash.h>
 
 #include <mach/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
+#include "fpga.h"
 
 static const unsigned int p2_keymap[] = {
         KEY(0, 0, KEY_UP),
@@ -231,9 +231,9 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = {
 
 static void __init perseus2_init_smc91x(void)
 {
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
         mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+        __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
                    H2P2_DBG_FPGA_LAN_RESET);
         mdelay(50);
 }
@@ -324,7 +324,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
         .atag_offset    = 0x100,
         .map_io         = omap_perseus2_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_perseus2_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 5932d56e17bf..4fcf19c78a08 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -16,9 +16,10 @@
 #include <linux/platform_device.h>
 
 #include <mach/hardware.h>
-#include <plat/mmc.h>
 #include <mach/board-sx1.h>
 
+#include "mmc.h"
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
 static int mmc_set_power(struct device *dev, int slot, int power_on,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 13bf2cc56814..1ebc7e08d6e5 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -36,15 +36,16 @@
 
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 #include <mach/irda.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/board-sx1.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "common.h"
+#include "dma.h"
 
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
@@ -403,7 +404,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
         .atag_offset    = 0x100,
         .map_io         = omap15xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = omap_sx1_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index ad75e3411d46..abf705f49b19 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -34,7 +34,7 @@
 #include <mach/board-voiceblue.h>
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -286,7 +286,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         .atag_offset    = 0x100,
         .map_io         = omap15xx_map_io,
         .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
         .init_irq       = omap1_init_irq,
         .init_machine   = voiceblue_init,
         .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 638f4070fc70..4f5fd4a084c0 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
@@ -21,21 +22,21 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/cpu.h>
-#include <plat/usb.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/clkdev_omap.h>
-
 #include <mach/hardware.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "opp.h"
+#include "sram.h"
 
 __u32 arm_idlect1_mask;
 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
 
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+static DEFINE_SPINLOCK(clockfw_lock);
+
 /*
  * Omap1 specific clock functions
  */
@@ -607,3 +608,497 @@ void omap1_clk_disable_unused(struct clk *clk)
 }
 
 #endif
+
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        int ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->usecount == 0) {
+                pr_err("Trying disable clock %s with 0 usecount\n",
+                       clk->name);
+                WARN_ON(1);
+                goto out;
+        }
+
+        omap1_clk_disable(clk);
+
+out:
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long flags;
+        unsigned long ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = clk->rate;
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/*
+ * Optional clock functions defined in include/linux/clk.h
+ */
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        long ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_round_rate(clk, rate);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_set_rate(clk, rate);
+        if (ret == 0)
+                propagate_rate(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n");
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+/*
+ * OMAP specific clock functions shared between omap1 and omap2
+ */
+
+int __initdata mpurate;
+
+/*
+ * By default we use the rate set by the bootloader.
+ * You can override this with mpurate= cmdline option.
+ */
+static int __init omap_clk_setup(char *str)
+{
+        get_option(&str, &mpurate);
+
+        if (!mpurate)
+                return 1;
+
+        if (mpurate < 1000)
+                mpurate *= 1000000;
+
+        return 1;
+}
+__setup("mpurate=", omap_clk_setup);
+
+/* Used for clocks that always have same value as the parent clock */
+unsigned long followparent_recalc(struct clk *clk)
+{
+        return clk->parent->rate;
+}
+
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+
+        return clk->parent->rate / clk->fixed_div;
+}
+
+void clk_reparent(struct clk *child, struct clk *parent)
+{
+        list_del_init(&child->sibling);
+        if (parent)
+                list_add(&child->sibling, &parent->children);
+        child->parent = parent;
+
+        /* now do the debugfs renaming to reattach the child
+           to the proper parent */
+}
+
+/* Propagate rate to children */
+void propagate_rate(struct clk *tclk)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &tclk->children, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+
+static LIST_HEAD(root_clks);
+
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &root_clks, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+
+/**
+ * clk_preinit - initialize any fields in the struct clk before clk init
+ * @clk: struct clk * to initialize
+ *
+ * Initialize any struct clk fields needed before normal clk initialization
+ * can run.  No return value.
+ */
+void clk_preinit(struct clk *clk)
+{
+        INIT_LIST_HEAD(&clk->children);
+}
+
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        /*
+         * trap out already registered clocks
+         */
+        if (clk->node.next || clk->node.prev)
+                return 0;
+
+        mutex_lock(&clocks_mutex);
+        if (clk->parent)
+                list_add(&clk->sibling, &clk->parent->children);
+        else
+                list_add(&clk->sibling, &root_clks);
+
+        list_add(&clk->node, &clocks);
+        if (clk->init)
+                clk->init(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->sibling);
+        list_del(&clk->node);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node)
+                if (clkp->flags & ENABLE_ON_INIT)
+                        clk_enable(clkp);
+}
+
+/**
+ * omap_clk_get_by_name - locate OMAP struct clk by its name
+ * @name: name of the struct clk to locate
+ *
+ * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ * names are unique.  Returns NULL if not found or a pointer to the
+ * struct clk if found.
+ */
+struct clk *omap_clk_get_by_name(const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+/*
+ * Low level helpers
+ */
+static int clkll_enable_null(struct clk *clk)
+{
+        return 0;
+}
+
+static void clkll_disable_null(struct clk *clk)
+{
+}
+
+const struct clkops clkops_null = {
+        .enable         = clkll_enable_null,
+        .disable        = clkll_disable_null,
+};
+
+/*
+ * Dummy clock
+ *
+ * Used for clock aliases that are needed on some OMAPs, but not others
+ */
+struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_null,
+};
+
+/*
+ *
+ */
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+/*
+ * Disable any unused clocks left on by the bootloader
+ */
+static int __init clk_disable_unused(void)
+{
+        struct clk *ck;
+        unsigned long flags;
+
+        pr_info("clock: disabling unused clocks to save power\n");
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(ck, &clocks, node) {
+                if (ck->ops == &clkops_null)
+                        continue;
+
+                if (ck->usecount > 0 || !ck->enable_reg)
+                        continue;
+
+                omap1_clk_disable_unused(ck);
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static struct dentry *clk_debugfs_root;
+
+static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+{
+        struct clk *c;
+        struct clk *pa;
+
+        mutex_lock(&clocks_mutex);
+        seq_printf(s, "%-30s %-30s %-10s %s\n",
+                   "clock-name", "parent-name", "rate", "use-count");
+
+        list_for_each_entry(c, &clocks, node) {
+                pa = c->parent;
+                seq_printf(s, "%-30s %-30s %-10lu %d\n",
+                           c->name, pa ? pa->name : "none", c->rate,
+                           c->usecount);
+        }
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+
+static int clk_dbg_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_dbg_show_summary, inode->i_private);
+}
+
+static const struct file_operations debug_clock_fops = {
+        .open           = clk_dbg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d;
+        struct clk *pa = c->parent;
+
+        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
+        if (!d)
+                return -ENOMEM;
+        c->dent = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        return 0;
+
+err_out:
+        debugfs_remove_recursive(c->dent);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clocks, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+
+        d = debugfs_create_file("summary", S_IRUGO,
+                d, NULL, &debug_clock_fops);
+        if (!d)
+                return -ENOMEM;
+
+        return 0;
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+late_initcall(clk_debugfs_init);
+
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 3d04f4f67676..1e4918a3a5ee 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -14,8 +14,184 @@
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 
 #include <linux/clk.h>
+#include <linux/list.h>
 
-#include <plat/clock.h>
+#include <linux/clkdev.h>
+
+struct module;
+struct clk;
+
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+/* Platform flags for the clkdev-OMAP integration code */
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)        /* 7xx, 850 */
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
+#define CK_1710         (1 << 4)        /* 1710 extra for rate selection */
+
+
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
+
+/**
+ * struct clkops - some clock function pointers
+ * @enable: fn ptr that enables the current clock in hardware
+ * @disable: fn ptr that enables the current clock in hardware
+ * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
+ *
+ * A "companion" clk is an accompanying clock to the one being queried
+ * that must be enabled for the IP module connected to the clock to
+ * become accessible by the hardware.  Neither @find_idlest nor
+ * @find_companion should be needed; that information is IP
+ * block-specific; the hwmod code has been created to handle this, but
+ * until hwmod data is ready and drivers have been converted to use PM
+ * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
+ * @find_companion must, unfortunately, remain.
+ */
+struct clkops {
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **,
+                                               u8 *, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **,
+                                                  u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
+};
+
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
+
+/**
+ * struct clk - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @ops: struct clkops * for this clock
+ * @name: the name of the clock in the hardware (used in hwmod data and debug)
+ * @parent: pointer to this clock's parent struct clk
+ * @children: list_head connecting to the child clks' @sibling list_heads
+ * @sibling: list_head connecting this clk to its parent clk's @children
+ * @rate: current clock rate
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @recalc: fn ptr that returns the clock's current rate
+ * @set_rate: fn ptr that can change the clock's current rate
+ * @round_rate: fn ptr that can round the clock's current rate
+ * @init: fn ptr to do clock-specific initialization
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @usecount: number of users that have requested this clock to be enabled
+ * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
+ * @flags: see "struct clk.flags possibilities" above
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ * XXX @usecount is poorly named.  It should be "enable_count" or
+ * something similar.  "users" in the description refers to kernel
+ * code (core code or drivers) that have called clk_enable() and not
+ * yet called clk_disable(); the usecount of parent clocks is also
+ * incremented by the clock code when clk_enable() is called on child
+ * clocks and decremented by the clock code when clk_disable() is
+ * called on child clocks.
+ *
+ * XXX @clkdm, @usecount, @children, @sibling should be marked for
+ * internal use only.
+ *
+ * @children and @sibling are used to optimize parent-to-child clock
+ * tree traversals.  (child-to-parent traversals use @parent.)
+ *
+ * XXX The notion of the clock's current rate probably needs to be
+ * separated from the clock's target rate.
+ */
+struct clk {
+        struct list_head        node;
+        const struct clkops     *ops;
+        const char              *name;
+        struct clk              *parent;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
+        unsigned long           rate;
+        void __iomem            *enable_reg;
+        unsigned long           (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        u8                      enable_bit;
+        s8                      usecount;
+        u8                      fixed_div;
+        u8                      flags;
+        u8                      rate_offset;
+        u8                      src_offset;
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
+};
+
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
+};
+
+extern int mpurate;
+
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_preinit(struct clk *clk);
+extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
+extern unsigned long followparent_recalc(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
+extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
+
+extern const struct clkops clkops_null;
+
+extern struct clk dummy_ck;
 
 int omap1_clk_init(void);
 void omap1_clk_late_init(void);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9b45f4b0ee22..cb7c6ae2e3fc 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -22,16 +22,14 @@
 
 #include <asm/mach-types.h>  /* for machine_is_* */
 
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/clkdev_omap.h>
-#include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
+#include "soc.h"
 
 #include <mach/hardware.h>
 #include <mach/usb.h>   /* for OTG_BASE */
 
 #include "iomap.h"
 #include "clock.h"
+#include "sram.h"
 
 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
 #define IDL_CLKOUT_ARM_SHIFT                    12
@@ -765,14 +763,6 @@ static struct omap_clk omap_clks[] = {
  * init
  */
 
-static struct clk_functions omap1_clk_functions = {
-        .clk_enable             = omap1_clk_enable,
-        .clk_disable            = omap1_clk_disable,
-        .clk_round_rate         = omap1_clk_round_rate,
-        .clk_set_rate           = omap1_clk_set_rate,
-        .clk_disable_unused     = omap1_clk_disable_unused,
-};
-
 static void __init omap1_show_rates(void)
 {
         pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
@@ -803,8 +793,6 @@ int __init omap1_clk_init(void)
         if (!cpu_is_omap15xx())
                 omap_writew(0, SOFT_REQ_REG2);
 
-        clk_init(&omap1_clk_functions);
-
         /* By default all idlect1 clocks are allowed to idle */
         arm_idlect1_mask = ~0;
 
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index c2552b24f9f2..dab2e102b9d7 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -26,8 +26,10 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
 #define __ARCH_ARM_MACH_OMAP1_COMMON_H
 
-#include <plat/common.h>
 #include <linux/mtd/mtd.h>
+#include <linux/i2c-omap.h>
+
+#include <plat/i2c.h>
 
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 void omap7xx_map_io(void);
@@ -38,6 +40,7 @@ static inline void omap7xx_map_io(void)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP15XX
+void omap1510_fpga_init_irq(void);
 void omap15xx_map_io(void);
 #else
 static inline void omap15xx_map_io(void)
@@ -90,4 +93,6 @@ extern int ocpi_enable(void);
 static inline int ocpi_enable(void) { return 0; }
 #endif
 
+extern int omap1_get_reset_sources(void);
+
 #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index d3fec92c54cb..7155ed8b97f8 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -19,10 +19,8 @@
 
 #include <asm/mach/map.h>
 
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
-#include <plat/mmc.h>
 
 #include <mach/omap7xx.h>
 #include <mach/camera.h>
@@ -30,6 +28,9 @@
 
 #include "common.h"
 #include "clock.h"
+#include "dma.h"
+#include "mmc.h"
+#include "sram.h"
 
 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
 
@@ -175,6 +176,13 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base,
         res[3].name = "tx";
         res[3].flags = IORESOURCE_DMA;
 
+        if (cpu_is_omap7xx())
+                data->slots[0].features = MMC_OMAP7XX;
+        if (cpu_is_omap15xx())
+                data->slots[0].features = MMC_OMAP15XX;
+        if (cpu_is_omap16xx())
+                data->slots[0].features = MMC_OMAP16XX;
+
         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
         if (ret == 0)
                 ret = platform_device_add_data(pdev, data, sizeof(*data));
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 29007fef84cd..978aed85d328 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -25,11 +25,13 @@
 #include <linux/device.h>
 #include <linux/io.h>
 
-#include <plat/dma.h>
-#include <plat/tc.h>
+#include <plat-omap/dma-omap.h>
+#include <mach/tc.h>
 
 #include <mach/irqs.h>
 
+#include "dma.h"
+
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 #define OMAP1_DMA_STRIDE                0x40
@@ -319,6 +321,9 @@ static int __init omap1_system_dma_init(void)
                 d->dev_caps = ENABLE_1510_MODE;
         enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
 
+        if (cpu_is_omap16xx())
+                d->dev_caps = ENABLE_16XX_MODE;
+
         d->dev_caps             |= SRC_PORT;
         d->dev_caps             |= DST_PORT;
         d->dev_caps             |= SRC_INDEX;
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
new file mode 100644
index 000000000000..da6345dab03f
--- /dev/null
+++ b/arch/arm/mach-omap1/dma.h
@@ -0,0 +1,83 @@
+/*
+ *  OMAP1 DMA channel definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __OMAP1_DMA_CHANNEL_H
+#define __OMAP1_DMA_CHANNEL_H
+
+/* DMA channels for omap1 */
+#define OMAP_DMA_NO_DEVICE              0
+#define OMAP_DMA_MCSI1_TX               1
+#define OMAP_DMA_MCSI1_RX               2
+#define OMAP_DMA_I2C_RX                 3
+#define OMAP_DMA_I2C_TX                 4
+#define OMAP_DMA_EXT_NDMA_REQ           5
+#define OMAP_DMA_EXT_NDMA_REQ2          6
+#define OMAP_DMA_UWIRE_TX               7
+#define OMAP_DMA_MCBSP1_TX              8
+#define OMAP_DMA_MCBSP1_RX              9
+#define OMAP_DMA_MCBSP3_TX              10
+#define OMAP_DMA_MCBSP3_RX              11
+#define OMAP_DMA_UART1_TX               12
+#define OMAP_DMA_UART1_RX               13
+#define OMAP_DMA_UART2_TX               14
+#define OMAP_DMA_UART2_RX               15
+#define OMAP_DMA_MCBSP2_TX              16
+#define OMAP_DMA_MCBSP2_RX              17
+#define OMAP_DMA_UART3_TX               18
+#define OMAP_DMA_UART3_RX               19
+#define OMAP_DMA_CAMERA_IF_RX           20
+#define OMAP_DMA_MMC_TX                 21
+#define OMAP_DMA_MMC_RX                 22
+#define OMAP_DMA_NAND                   23
+#define OMAP_DMA_IRQ_LCD_LINE           24
+#define OMAP_DMA_MEMORY_STICK           25
+#define OMAP_DMA_USB_W2FC_RX0           26
+#define OMAP_DMA_USB_W2FC_RX1           27
+#define OMAP_DMA_USB_W2FC_RX2           28
+#define OMAP_DMA_USB_W2FC_TX0           29
+#define OMAP_DMA_USB_W2FC_TX1           30
+#define OMAP_DMA_USB_W2FC_TX2           31
+
+/* These are only for 1610 */
+#define OMAP_DMA_CRYPTO_DES_IN          32
+#define OMAP_DMA_SPI_TX                 33
+#define OMAP_DMA_SPI_RX                 34
+#define OMAP_DMA_CRYPTO_HASH            35
+#define OMAP_DMA_CCP_ATTN               36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
+#define OMAP_DMA_MMC2_TX                54
+#define OMAP_DMA_MMC2_RX                55
+#define OMAP_DMA_CRYPTO_DES_OUT         56
+
+#endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 73ae6169aa4a..b3fb531af94e 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -10,7 +10,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/flash.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 29ec50fc688d..8bd71b2d0967 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -27,11 +27,11 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <plat/fpga.h>
-
 #include <mach/hardware.h>
 
 #include "iomap.h"
+#include "common.h"
+#include "fpga.h"
 
 static void fpga_mask_irq(struct irq_data *d)
 {
diff --git a/arch/arm/mach-omap1/fpga.h b/arch/arm/mach-omap1/fpga.h
new file mode 100644
index 000000000000..4b4307a80e48
--- /dev/null
+++ b/arch/arm/mach-omap1/fpga.h
@@ -0,0 +1,52 @@
+/*
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+
+/*
+ * ---------------------------------------------------------------------------
+ *  H2/P2 Debug board FPGA
+ * ---------------------------------------------------------------------------
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
+#define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
+#define H2P2_DBG_FPGA_START             0x04000000              /* PA */
+
+#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
+#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
+
+/* LEDs definition on debug board (16 LEDs, all physically green) */
+#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
+#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
+#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
+#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
+/*  cpu0 load-meter LEDs */
+#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+
+#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
+#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
+
+#endif
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 98e6f39224a4..02b3eb2e201c 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
+#include <mach/irqs.h>
+
 #define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE              0xFFFCE000
 
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 33f419236b17..b9952a258d82 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
+#include <mach/irqs.h>
+
 #define OMAP1610_GPIO1_BASE             0xfffbe400
 #define OMAP1610_GPIO2_BASE             0xfffbec00
 #define OMAP1610_GPIO3_BASE             0xfffbb400
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 958ce9acee95..f5819b2b7cbe 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
+#include <mach/irqs.h>
+
 #define OMAP7XX_GPIO1_BASE              0xfffbc000
 #define OMAP7XX_GPIO2_BASE              0xfffbc800
 #define OMAP7XX_GPIO3_BASE              0xfffbd000
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index a0551a6d7451..faca808cb3d9 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -19,11 +19,25 @@
  *
  */
 
-#include <plat/i2c.h>
+#include <linux/i2c-omap.h>
 #include <mach/mux.h>
-#include <plat/cpu.h>
+#include "soc.h"
+
+#include <plat/i2c.h>
+
+#define OMAP_I2C_SIZE           0x3f
+#define OMAP1_I2C_BASE          0xfffb3800
+#define OMAP1_INT_I2C           (32 + 4)
+
+static const char name[] = "omap_i2c";
 
-void __init omap1_i2c_mux_pins(int bus_id)
+static struct resource i2c_resources[2] = {
+};
+
+static struct platform_device omap_i2c_devices[1] = {
+};
+
+static void __init omap1_i2c_mux_pins(int bus_id)
 {
         if (cpu_is_omap7xx()) {
                 omap_cfg_reg(I2C_7XX_SDA);
@@ -33,3 +47,47 @@ void __init omap1_i2c_mux_pins(int bus_id)
                 omap_cfg_reg(I2C_SCL);
         }
 }
+
+int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
+                                int bus_id)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+
+        if (bus_id > 1)
+                return -EINVAL;
+
+        omap1_i2c_mux_pins(bus_id);
+
+        pdev = &omap_i2c_devices[bus_id - 1];
+        pdev->id = bus_id;
+        pdev->name = name;
+        pdev->num_resources = ARRAY_SIZE(i2c_resources);
+        res = i2c_resources;
+        res[0].start = OMAP1_I2C_BASE;
+        res[0].end = res[0].start + OMAP_I2C_SIZE;
+        res[0].flags = IORESOURCE_MEM;
+        res[1].start = OMAP1_INT_I2C;
+        res[1].flags = IORESOURCE_IRQ;
+        pdev->resource = res;
+
+        /* all OMAP1 have IP version 1 register set */
+        pdata->rev = OMAP_I2C_IP_VERSION_1;
+
+        /* all OMAP1 I2C are implemented like this */
+        pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
+                       OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                       OMAP_I2C_FLAG_16BIT_DATA_REG |
+                       OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
+
+        /* how the cpu bus is wired up differs for 7xx only */
+
+        if (cpu_is_omap7xx())
+                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
+        else
+                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
+
+        pdev->dev.platform_data = pdata;
+
+        return platform_device_register(pdev);
+}
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a1b846aacdaf..52de382fc804 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <asm/system_info.h>
 
-#include <plat/cpu.h>
+#include "soc.h"
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index 2b36a281dc84..5c1a26c9f490 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 
 #include <linux/serial_reg.h>
 
-#include <plat/serial.h>
+#include "serial.h"
 
                 .pushsection .data
 omap_uart_phys: .word   0x0
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index 88f08cab1717..78a8c6c24764 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -13,8 +13,6 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 
-#include "../../iomap.h"
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
deleted file mode 100644
index ebf86c0f4f46..000000000000
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/gpio.h
- */
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index 84248d250adb..5875a5098d35 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -39,7 +39,7 @@
 #include <asm/sizes.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
-#include <plat/cpu.h>
+#include <mach/soc.h>
 
 /*
  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
@@ -51,7 +51,7 @@ extern void omap_writeb(u8 v, u32 pa);
 extern void omap_writew(u16 v, u32 pa);
 extern void omap_writel(u32 v, u32 pa);
 
-#include <plat/tc.h>
+#include <mach/tc.h>
 
 /* Almost all documentation for chip and board memory maps assumes
  * BM is clear.  Most devel boards have a switch to control booting
@@ -72,7 +72,10 @@ static inline u32 omap_cs3_phys(void)
 
 #endif  /* ifndef __ASSEMBLER__ */
 
-#include <plat/serial.h>
+#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
+
+#include <mach/serial.h>
 
 /*
  * ---------------------------------------------------------------------------
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index 901082def9bd..3c2530523111 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -19,7 +19,7 @@
  * because of the strncmp().
  */
 #if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
-#include <plat/cpu.h>
+#include <mach/soc.h>
 
 /*
  * OMAP-1510 Local Bus address offset
diff --git a/arch/arm/mach-omap1/include/mach/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h
index 8fe05d6137c0..3d235244bf5c 100644
--- a/arch/arm/mach-omap1/include/mach/omap1510.h
+++ b/arch/arm/mach-omap1/include/mach/omap1510.h
@@ -45,5 +45,118 @@
 
 #define OMAP1510_DSP_MMU_BASE   (0xfffed200)
 
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
+#define OMAP1510_FPGA_SIZE              SZ_4K
+#define OMAP1510_FPGA_START             0x08000000              /* PA */
+
+/* Revision */
+#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
+#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
+
+#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510_FPGA_RESET_VALUE               0x42
+
+#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
+#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
+#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
+#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
+#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
+
 #endif /*  __ASM_ARCH_OMAP15XX_H */
 
diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/include/mach/serial.h
new file mode 100644
index 000000000000..2ce6a2db470b
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/serial.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <linux/init.h>
+
+/*
+ * Memory entry used for the DEBUG_LL UART configuration, relative to
+ * start of RAM. See also uncompress.h and debug-macro.S.
+ *
+ * Note that using a memory location for storing the UART configuration
+ * has at least two limitations:
+ *
+ * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
+ *    uncompress code could then partially overwrite itself
+ * 2. We assume printascii is called at least once before paging_init,
+ *    and addruart has a chance to read OMAP_UART_INFO
+ */
+#define OMAP_UART_INFO_OFS      0x3ffc
+
+/* OMAP1 serial ports */
+#define OMAP1_UART1_BASE        0xfffb0000
+#define OMAP1_UART2_BASE        0xfffb0800
+#define OMAP1_UART3_BASE        0xfffb9800
+
+#define OMAP_PORT_SHIFT         2
+#define OMAP7XX_PORT_SHIFT      0
+
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+
+/*
+ * DEBUG_LL port encoding stored into the UART1 scratchpad register by
+ * decomp_setup in uncompress.h
+ */
+#define OMAP1UART1              11
+#define OMAP1UART2              12
+#define OMAP1UART3              13
+
+#ifndef __ASSEMBLER__
+extern void omap_serial_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
new file mode 100644
index 000000000000..6cf9c1cc2bef
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -0,0 +1,229 @@
+/*
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+ * Copyright (C) 2009-11 Texas Instruments.
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_CPU_H
+#define __ASM_ARCH_OMAP_CPU_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bitops.h>
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP1
+#undef OMAP_NAME
+
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap850
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap16xx
+# endif
+#endif
+
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
+
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730, OMAP850
+ * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ */
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
+
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
+
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+IS_OMAP_CLASS(7xx, 0x07)
+IS_OMAP_CLASS(15xx, 0x15)
+IS_OMAP_CLASS(16xx, 0x16)
+
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             is_omap16xx()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             1
+# endif
+#endif
+
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap310():    True for OMAP310
+ * cpu_is_omap1510():   True for OMAP1510
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ */
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+IS_OMAP_TYPE(310, 0x0310)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+
+#define cpu_is_omap310()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+
+/* These are needed to compile common code */
+#ifdef CONFIG_ARCH_OMAP1
+#define cpu_is_omap242x()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap44xx()               0
+#define soc_is_omap54xx()               0
+#define soc_is_am33xx()                 0
+#define cpu_class_is_omap1()            1
+#define cpu_class_is_omap2()            0
+#endif
+
+/*
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ * between 310 vs. 1510 and 1611B/5912 vs. 1710.
+ */
+
+#if defined(CONFIG_ARCH_OMAP15XX)
+# undef  cpu_is_omap310
+# undef  cpu_is_omap1510
+# define cpu_is_omap310()               is_omap310()
+# define cpu_is_omap1510()              is_omap1510()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1610
+# undef  cpu_is_omap1611
+# undef  cpu_is_omap5912
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
+# define cpu_is_omap1710()              is_omap1710()
+#endif
+
+#endif  /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/mach-omap1/include/mach/tc.h
index 1b4b2da86203..1b4b2da86203 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/mach-omap1/include/mach/tc.h
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h
index 0ff22dc075c7..ad6fbe7d83f2 100644
--- a/arch/arm/mach-omap1/include/mach/uncompress.h
+++ b/arch/arm/mach-omap1/include/mach/uncompress.h
@@ -1,5 +1,122 @@
 /*
- * arch/arm/mach-omap1/include/mach/uncompress.h
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
  */
 
-#include <plat/uncompress.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+
+#include "serial.h"
+
+#define MDR1_MODE_MASK                  0x07
+
+volatile u8 *uart_base;
+int uart_shift;
+
+/*
+ * Store the DEBUG_LL uart number into memory.
+ * See also debug-macro.S, and serial.c for related code.
+ */
+static void set_omap_uart_info(unsigned char port)
+{
+        /*
+         * Get address of some.bss variable and round it down
+         * a la CONFIG_AUTO_ZRELADDR.
+         */
+        u32 ram_start = (u32)&uart_shift & 0xf8000000;
+        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
+        *uart_info = port;
+}
+
+static void putc(int c)
+{
+        if (!uart_base)
+                return;
+
+        /* Check for UART 16x mode */
+        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+                return;
+
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+                barrier();
+        uart_base[UART_TX << uart_shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
+        if (machine_is_##mach()) {                                      \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_omap_uart_info(port);                               \
+                break;                                                  \
+        }
+
+#define DEBUG_LL_OMAP7XX(p, mach)                                       \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
+                OMAP1UART##p)
+
+#define DEBUG_LL_OMAP1(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP1UART##p)
+
+static inline void arch_decomp_setup(void)
+{
+        int port = 0;
+
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap7xx/8xx based boards using UART1 with shift 0 */
+                DEBUG_LL_OMAP7XX(1, herald);
+                DEBUG_LL_OMAP7XX(1, omap_perseus2);
+
+                /* omap15xx/16xx based boards using UART1 */
+                DEBUG_LL_OMAP1(1, ams_delta);
+                DEBUG_LL_OMAP1(1, nokia770);
+                DEBUG_LL_OMAP1(1, omap_h2);
+                DEBUG_LL_OMAP1(1, omap_h3);
+                DEBUG_LL_OMAP1(1, omap_innovator);
+                DEBUG_LL_OMAP1(1, omap_osk);
+                DEBUG_LL_OMAP1(1, omap_palmte);
+                DEBUG_LL_OMAP1(1, omap_palmz71);
+
+                /* omap15xx/16xx based boards using UART2 */
+                DEBUG_LL_OMAP1(2, omap_palmtt);
+
+                /* omap15xx/16xx based boards using UART3 */
+                DEBUG_LL_OMAP1(3, sx1);
+        } while (0);
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 6a5baab1f4cb..5a3b80617a11 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -17,8 +17,8 @@
 #include <asm/mach/map.h>
 
 #include <mach/mux.h>
-#include <plat/tc.h>
-#include <plat/dma.h>
+#include <mach/tc.h>
+#include <plat-omap/dma-omap.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -134,7 +134,6 @@ void __init omap1_init_early(void)
          */
         omap1_clk_init();
         omap1_mux_init();
-        omap_init_consistent_dma_size();
 }
 
 void __init omap1_init_late(void)
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
index 330c4716b028..f4e2d7a21365 100644
--- a/arch/arm/mach-omap1/iomap.h
+++ b/arch/arm/mach-omap1/iomap.h
@@ -22,9 +22,6 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
-#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
-
 /*
  * ----------------------------------------------------------------------------
  * Omap1 specific IO mapping
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 6995fb6a3345..122ef67939a2 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -45,7 +45,7 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <plat/cpu.h>
+#include "soc.h"
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index ed42628611bc..7ed8c1857d56 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -27,11 +27,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
 
+#include "dma.h"
+
 int omap_lcd_dma_running(void)
 {
         /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index bdc2e7541adb..c6d8fdf92e9c 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,14 +19,15 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 #include <mach/mux.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include <mach/irqs.h>
 
 #include "iomap.h"
+#include "dma.h"
 
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
diff --git a/arch/arm/mach-omap1/mmc.h b/arch/arm/mach-omap1/mmc.h
new file mode 100644
index 000000000000..39c2b13de884
--- /dev/null
+++ b/arch/arm/mach-omap1/mmc.h
@@ -0,0 +1,18 @@
+#include <linux/mmc/host.h>
+#include <linux/platform_data/mmc-omap.h>
+
+#define OMAP15XX_NR_MMC         1
+#define OMAP16XX_NR_MMC         2
+#define OMAP1_MMC_SIZE          0x080
+#define OMAP1_MMC1_BASE         0xfffb7800
+#define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                                int nr_controllers);
+#else
+static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                                int nr_controllers)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 9cd4ddb51397..8dcebe6d8882 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,7 +10,7 @@
  * published by the Free Software Foundation.
  */
 
-#include <plat/clkdev_omap.h>
+#include "clock.h"
 #include "opp.h"
 
 /*-------------------------------------------------------------------------
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 47ec16155483..66d663a6ef3a 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -44,23 +44,23 @@
 #include <linux/io.h>
 #include <linux/atomic.h>
 
+#include <asm/fncpy.h>
 #include <asm/system_misc.h>
 #include <asm/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 #include <plat/dmtimer.h>
 
 #include <mach/irqs.h>
 
 #include "iomap.h"
+#include "clock.h"
 #include "pm.h"
+#include "sram.h"
 
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 7868e75ad077..3f2d39672393 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -19,8 +19,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <plat/omap_device.h>
-#include <plat/omap-pm.h>
+#include "soc.h"
 
 #ifdef CONFIG_PM_RUNTIME
 static int omap1_pm_runtime_suspend(struct device *dev)
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index b17709103866..a0a9f97772ea 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -10,6 +10,19 @@
 
 #include "common.h"
 
+/* ARM_SYSST bit shifts related to SoC reset sources */
+#define ARM_SYSST_POR_SHIFT                             5
+#define ARM_SYSST_EXT_RST_SHIFT                         4
+#define ARM_SYSST_ARM_WDRST_SHIFT                       2
+#define ARM_SYSST_GLOB_SWRST_SHIFT                      1
+
+/* Standardized reset source bits (across all OMAP SoCs) */
+#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT               0
+#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT               1
+#define OMAP_MPU_WD_RST_SRC_ID_SHIFT                    3
+#define OMAP_EXTWARM_RST_SRC_ID_SHIFT                   5
+
+
 void omap1_restart(char mode, const char *cmd)
 {
         /*
@@ -23,3 +36,28 @@ void omap1_restart(char mode, const char *cmd)
 
         omap_writew(1, ARM_RSTCT1);
 }
+
+/**
+ * omap1_get_reset_sources - return the source of the SoC's last reset
+ *
+ * Returns bits that represent the last reset source for the SoC.  The
+ * format is standardized across OMAPs for use by the OMAP watchdog.
+ */
+int omap1_get_reset_sources(void)
+{
+        int ret = 0;
+        u16 rs;
+
+        rs = __raw_readw(ARM_SYSST);
+
+        if (rs & (1 << ARM_SYSST_POR_SHIFT))
+                ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT))
+                ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT))
+                ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT))
+                ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT;
+
+        return ret;
+}
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index b9d6834af835..d1ac08016f0b 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -23,7 +23,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/mux.h>
-#include <plat/fpga.h>
 
 #include "pm.h"
 
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index 0e628743bd03..a908c51839a4 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -36,6 +36,8 @@
 
 #include <asm/assembler.h>
 
+#include <mach/hardware.h>
+
 #include "iomap.h"
 #include "pm.h"
 
diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h
new file mode 100644
index 000000000000..69daf0187b1d
--- /dev/null
+++ b/arch/arm/mach-omap1/soc.h
@@ -0,0 +1,4 @@
+/*
+ * We can move mach/soc.h here once the drivers are fixed
+ */
+#include <mach/soc.h>
diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c
new file mode 100644
index 000000000000..6431b0f862ce
--- /dev/null
+++ b/arch/arm/mach-omap1/sram-init.c
@@ -0,0 +1,76 @@
+/*
+ * OMAP SRAM detection and management
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/fncpy.h>
+#include <asm/tlb.h>
+#include <asm/cacheflush.h>
+
+#include <asm/mach/map.h>
+
+#include "soc.h"
+#include "sram.h"
+
+#define OMAP1_SRAM_PA           0x20000000
+#define SRAM_BOOTLOADER_SZ      0x80
+
+/*
+ * The amount of SRAM depends on the core type.
+ * Note that we cannot try to test for SRAM here because writes
+ * to secure SRAM will hang the system. Also the SRAM is not
+ * yet mapped at this point.
+ */
+static void __init omap_detect_and_map_sram(void)
+{
+        unsigned long omap_sram_skip = SRAM_BOOTLOADER_SZ;
+        unsigned long omap_sram_start = OMAP1_SRAM_PA;
+        unsigned long omap_sram_size;
+
+        if (cpu_is_omap7xx())
+                omap_sram_size = 0x32000;       /* 200K */
+        else if (cpu_is_omap15xx())
+                omap_sram_size = 0x30000;       /* 192K */
+        else if (cpu_is_omap1610() || cpu_is_omap1611() ||
+                        cpu_is_omap1621() || cpu_is_omap1710())
+                omap_sram_size = 0x4000;        /* 16K */
+        else {
+                pr_err("Could not detect SRAM size\n");
+                omap_sram_size = 0x4000;
+        }
+
+        omap_map_sram(omap_sram_start, omap_sram_size,
+                omap_sram_skip, 1);
+}
+
+static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
+
+void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
+{
+        BUG_ON(!_omap_sram_reprogram_clock);
+        /* On 730, bit 13 must always be 1 */
+        if (cpu_is_omap7xx())
+                ckctl |= 0x2000;
+        _omap_sram_reprogram_clock(dpllctl, ckctl);
+}
+
+int __init omap_sram_init(void)
+{
+        omap_detect_and_map_sram();
+        _omap_sram_reprogram_clock =
+                        omap_sram_push(omap1_sram_reprogram_clock,
+                                        omap1_sram_reprogram_clock_sz);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap1/sram.h b/arch/arm/mach-omap1/sram.h
new file mode 100644
index 000000000000..d5a6c8362301
--- /dev/null
+++ b/arch/arm/mach-omap1/sram.h
@@ -0,0 +1,7 @@
+#include <plat/sram.h>
+
+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+
+/* Do not use these */
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 74529549130c..89368195bf08 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -50,6 +50,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
+#include <plat/counter-32k.h>
 #include <plat/dmtimer.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 84267edd9421..104fed366b8f 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -301,7 +301,7 @@ static inline void otg_device_init(struct omap_usb_config *pdata)
 
 #endif
 
-u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
+static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
 {
         u32     syscon1 = 0;
 
@@ -409,7 +409,7 @@ u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
         return syscon1 << 16;
 }
 
-u32 __init omap1_usb1_init(unsigned nwires)
+static u32 __init omap1_usb1_init(unsigned nwires)
 {
         u32     syscon1 = 0;
 
@@ -475,7 +475,7 @@ bad:
         return syscon1 << 20;
 }
 
-u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
 {
         u32     syscon1 = 0;
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..c94d495b8d95 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,30 +4,37 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
-
-# INTCPS IP block support - XXX should be moved to drivers/
-obj-$(CONFIG_ARCH_OMAP2)                += irq.o
-obj-$(CONFIG_ARCH_OMAP3)                += irq.o
-obj-$(CONFIG_SOC_AM33XX)                += irq.o
-
-# Secure monitor API support
-obj-$(CONFIG_ARCH_OMAP3)                += omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap-smc.o omap-secure.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-smc.o omap-secure.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
+         omap_device.o sram.o
+
+omap-2-3-common                         = irq.o
+hwmod-common                            = omap_hwmod.o \
+                                          omap_hwmod_common_data.o
+clock-common                            = clock.o clock_common_data.o \
+                                          clkt_dpll.o clkt_clksel.o
+secure-common                           = omap-smc.o omap-secure.o
+
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
 
-obj-$(CONFIG_TWL4030_CORE)              += omap_twl.o
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 
 # SMP support ONLY available for OMAP4
 
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap4-common.o omap-wakeupgen.o
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -52,7 +59,6 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -63,15 +69,16 @@ endif
 
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
+obj-$(CONFIG_OMAP_PM_NOOP)              += omap-pm-noop.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)     += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -83,76 +90,82 @@ endif
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 
 # PRCM
-obj-y                                   += prcm.o prm_common.o
-obj-$(CONFIG_ARCH_OMAP2)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-y                                   += prcm.o prm_common.o cm_common.o
+obj-$(CONFIG_ARCH_OMAP2)                += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                            prcm_mpu44xx.o prminst44xx.o \
-                                           vc44xx_data.o vp44xx_data.o \
-                                           prm44xx.o
+                                           vc44xx_data.o vp44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
-obj-y                                   += voltage.o vc.o vp.o
+voltagedomain-common                    := voltage.o vc.o vp.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 
 # OMAP powerdomain framework
-obj-y                                   += powerdomain.o powerdomain-common.o
+powerdomain-common                      += powerdomain.o powerdomain-common.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 
 # PRCM clockdomain control
-obj-y                                   += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
+clockdomain-common                      += clockdomain.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 
 # Clock framework
-obj-y                                   += clock.o clock_common_data.o \
-                                           clkt_dpll.o clkt_clksel.o
-obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o clkt2xxx_sys.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)                += dpll3xxx.o clock33xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
+obj-$(CONFIG_SOC_AM33XX)                += clock33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
@@ -160,7 +173,6 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
-obj-y                                   += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
@@ -206,10 +218,10 @@ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index d0c54c573d34..af11dcdb7e2c 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 95b384d54f8a..d1c01625fe5a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -28,14 +28,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/gpmc.h>
-#include <plat/usb.h>
+#include "gpmc.h"
 #include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 96cd3693e1ae..79fd9048fd79 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -30,15 +30,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/usb.h>
 #include "common.h"
-#include <plat/dma.h>
-#include <plat/gpmc.h>
+#include <plat-omap/dma-omap.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "gpmc.h"
 #include "gpmc-smc91x.h"
 
+#include "soc.h"
 #include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index fc224ad86747..81871b1c735c 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -18,9 +18,8 @@
 
 #include "common.h"
 #include "gpmc-smc91x.h"
-#include <plat/usb.h>
 
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 
 #include "board-flash.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 3669c120c7e8..fd80d976872d 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -27,6 +27,7 @@
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
+#include <linux/usb/musb.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -34,8 +35,6 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
-#include <plat/mmc.h>
 #include "omap4-keypad.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
@@ -45,6 +44,7 @@
 
 #include "soc.h"
 #include "mux.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 318feadb1d6e..603503c587b7 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 
 #include "am35xx-emac.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index e16289755f2e..96d6c5ab5d4c 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,6 +25,7 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/musb.h>
 #include <linux/platform_data/gpio-omap.h>
 
 #include "am35xx.h"
@@ -33,7 +34,6 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index cea3abace815..64cf1bde0f3b 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -28,14 +28,14 @@
 #include <linux/clk.h>
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/leds-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <plat/led.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 376d26eb601c..a8cad2237a2a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -38,21 +38,19 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
-
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-nand.h"
 
 #define CM_T35_GPIO_PENDOWN             57
 #define SB_T35_USB_HUB_RESET_GPIO       167
@@ -181,7 +179,7 @@ static struct omap_nand_platform_data cm_t35_nand_data = {
 
 static void __init cm_t35_init_nand(void)
 {
-        if (gpmc_nand_init(&cm_t35_nand_data) < 0)
+        if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
                 pr_err("CM-T35: Unable to register NAND device\n");
 }
 #else
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 59c0a45f75b0..278664731d2c 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -39,9 +39,8 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 
 #include "am35xx.h"
 
@@ -49,6 +48,7 @@
 #include "control.h"
 #include "common-board-devices.h"
 #include "am35xx-emac.h"
+#include "gpmc-nand.h"
 
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
@@ -240,7 +240,7 @@ static struct omap_nand_platform_data cm_t3517_nand_data = {
 
 static void __init cm_t3517_init_nand(void)
 {
-        if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
+        if (gpmc_nand_init(&cm_t3517_nand_data, NULL) < 0)
                 pr_err("CM-T3517: NAND initialization failed\n");
 }
 #else
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 1fd161e934c7..933479e36737 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -39,9 +39,8 @@
 #include <asm/mach/flash.h>
 
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
@@ -55,8 +54,11 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define NAND_CS                 0
+
 #define OMAP_DM9000_GPIO_IRQ    25
 #define OMAP3_DEVKIT_TS_GPIO    27
 
@@ -621,8 +623,9 @@ static void __init devkit8000_init(void)
 
         usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
-                             ARRAY_SIZE(devkit8000_nand_partitions));
+        board_nand_init(devkit8000_nand_partitions,
+                        ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
         omap_twl4030_audio_init("omap3beagle");
 
         /* Ensure SDRC pins are mux'd for self-refresh */
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e642acf9cad0..c33adea0247c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -17,14 +17,14 @@
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
-#include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
-#include <plat/tc.h>
 
+#include "soc.h"
 #include "common.h"
 #include "board-flash.h"
+#include "gpmc-onenand.h"
+#include "gpmc-nand.h"
 
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
@@ -104,36 +104,35 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
                 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 /* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings[1] = {
+        {
+                .sync_clk = 0,
 
-        .sync_clk = 0,
+                .cs_on = 0,
+                .cs_rd_off = 36,
+                .cs_wr_off = 36,
 
-        .cs_on = 0,
-        .cs_rd_off = 36,
-        .cs_wr_off = 36,
+                .adv_on = 6,
+                .adv_rd_off = 24,
+                .adv_wr_off = 36,
 
-        .adv_on = 6,
-        .adv_rd_off = 24,
-        .adv_wr_off = 36,
+                .we_off = 30,
+                .oe_off = 48,
 
-        .we_off = 30,
-        .oe_off = 48,
+                .access = 54,
+                .rd_cycle = 72,
+                .wr_cycle = 72,
 
-        .access = 54,
-        .rd_cycle = 72,
-        .wr_cycle = 72,
-
-        .wr_access = 30,
-        .wr_data_mux_bus = 0,
+                .wr_access = 30,
+                .wr_data_mux_bus = 0,
+        },
 };
 
-static struct omap_nand_platform_data board_nand_data = {
-        .gpmc_t         = &nand_timings,
-};
+static struct omap_nand_platform_data board_nand_data;
 
 void
-__init board_nand_init(struct mtd_partition *nand_parts,
-                        u8 nr_parts, u8 cs, int nand_type)
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+                                int nand_type, struct gpmc_timings *gpmc_t)
 {
         board_nand_data.cs              = cs;
         board_nand_data.parts           = nand_parts;
@@ -141,7 +140,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
         board_nand_data.devsize         = nand_type;
 
         board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-        gpmc_nand_init(&board_nand_data);
+        gpmc_nand_init(&board_nand_data, gpmc_t);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 
@@ -238,5 +237,6 @@ void __init board_flash_init(struct flash_partitions partition_info[],
                 pr_err("NAND: Unable to find configuration in GPMC\n");
         else
                 board_nand_init(partition_info[2].parts,
-                        partition_info[2].nr_parts, nandcs, nand_type);
+                        partition_info[2].nr_parts, nandcs,
+                        nand_type, nand_default_timings);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c44b70d52021..2fb5d41a9fae 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,7 @@
  */
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 
 #define PDC_NOR         1
 #define PDC_NAND        2
@@ -40,12 +40,14 @@ static inline void board_flash_init(struct flash_partitions part[],
 #if defined(CONFIG_MTD_NAND_OMAP2) || \
                 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs, int nand_type);
+                u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
+extern struct gpmc_timings nand_default_timings[];
 #else
 static inline void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs, int nand_type)
+                u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
 {
 }
+#define nand_default_timings    NULL
 #endif
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8d04bf851af4..8668c72ee810 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -26,15 +26,14 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/mfd/menelaus.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/menelaus.h>
-#include <plat/dma.h>
-#include <plat/gpmc.h>
-#include "debug-devices.h"
+#include <plat-omap/dma-omap.h>
+#include <plat/debug-devices.h>
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -42,6 +41,7 @@
 #include "common.h"
 #include "mux.h"
 #include "control.h"
+#include "gpmc.h"
 
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 48d5e41dfbfa..dbc705ac4334 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -29,20 +29,19 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include "common.h"
-#include <plat/gpmc.h>
-#include <plat/usb.h>
-
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
+#include "common.h"
+#include "gpmc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
 #include "board-flash.h"
 #include "control.h"
+#include "gpmc-onenand.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -175,7 +174,7 @@ static void __init igep_flash_init(void)
                 pr_info("IGEP: initializing NAND memory device\n");
                 board_nand_init(igep_flash_partitions,
                                 ARRAY_SIZE(igep_flash_partitions),
-                                0, NAND_BUSWIDTH_16);
+                                0, NAND_BUSWIDTH_16, nand_default_timings);
         } else if (mux == IGEP_SYSBOOT_ONENAND) {
                 pr_info("IGEP: initializing OneNAND memory device\n");
                 board_onenand_init(igep_flash_partitions,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ee8c3cfb95b3..1164b1061038 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -35,9 +35,8 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/gpmc.h>
-#include <mach/board-zoom.h>
-#include <plat/usb.h>
+#include "board-zoom.h"
+#include "gpmc.h"
 #include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
@@ -420,8 +419,8 @@ static void __init omap_ldp_init(void)
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         usb_musb_init(NULL);
-        board_nand_init(ldp_nand_partitions,
-                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+        board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
+                        ZOOM_NAND_CS, 0, nand_default_timings);
 
         omap_hsmmc_init(mmc);
         ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index d95f727ca39a..e3efcb88cb3b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -22,16 +22,17 @@
 #include <linux/usb/musb.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/mfd/menelaus.h>
 #include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include "common.h"
-#include <plat/menelaus.h>
-#include <plat/mmc.h>
+#include "mmc.h"
 
 #include "mux.h"
+#include "gpmc-onenand.h"
 
 #define TUSB6010_ASYNC_CS       1
 #define TUSB6010_SYNC_CS        4
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d41ab98890ff..5a3800da903f 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -39,19 +39,22 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
-#include <plat/omap_device.h>
 
+#include "common.h"
+#include "omap_device.h"
+#include "gpmc.h"
+#include "soc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define NAND_CS 0
+
 /*
  * OMAP3 Beagle revision
  * Run time detection of Beagle revision is done by reading GPIO.
@@ -518,8 +521,9 @@ static void __init omap3_beagle_init(void)
 
         usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
-                             ARRAY_SIZE(omap3beagle_nand_partitions));
+        board_nand_init(omap3beagle_nand_partitions,
+                        ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
         omap_twl4030_audio_init("omap3beagle");
 
         /* Ensure msecure is mux'd to be able to set the RTC. */
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b9b776b6c954..3c0b9a90f3b3 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -32,6 +32,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/musb.h>
 #include <linux/usb/nop-usb-xceiv.h>
 #include <linux/smsc911x.h>
 
@@ -45,17 +46,20 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/usb.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "soc.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+
+#define NAND_CS                 0
 
 #define OMAP3_EVM_TS_GPIO       175
 #define OMAP3_EVM_EHCI_VBUS     22
@@ -731,8 +735,9 @@ static void __init omap3_evm_init(void)
         }
         usb_musb_init(&musb_board_data);
         usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
-                             ARRAY_SIZE(omap3evm_nand_partitions));
+        board_nand_init(omap3evm_nand_partitions,
+                        ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
 
         omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
         omap3evm_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7bd8253b5d1d..e84e2a875378 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -34,16 +34,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "gpmc-smsc911x.h"
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/usb.h>
-
 #include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-smsc911x.h"
 
 #define OMAP3LOGIC_SMSC911X_CS                  1
 
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 00a1f4ae6e44..ce31bd329f38 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -42,7 +42,6 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 
@@ -50,6 +49,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc-nand.h"
 
 #define PANDORA_WIFI_IRQ_GPIO           21
 #define PANDORA_WIFI_NRESET_GPIO        23
@@ -602,7 +602,7 @@ static void __init omap3pandora_init(void)
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
         usbhs_init(&usbhs_bdata);
         usb_musb_init(NULL);
-        gpmc_nand_init(&pandora_nand_data);
+        gpmc_nand_init(&pandora_nand_data, NULL);
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 731235eb319e..ba1124538b9c 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -40,9 +40,8 @@
 #include <asm/mach/flash.h>
 
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 944ffc436577..a225d819633f 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,12 +44,12 @@
 #include <asm/system_info.h>
 
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #include <asm/setup.h>
@@ -59,6 +59,8 @@
 #define TB_BL_PWM_TIMER         9
 #define TB_KILL_POWER_GPIO      168
 
+#define NAND_CS                 0
+
 static unsigned long touchbook_revision;
 
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
@@ -365,8 +367,9 @@ static void __init omap3_touchbook_init(void)
         omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
         usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
-                             ARRAY_SIZE(omap3touchbook_nand_partitions));
+        board_nand_init(omap3touchbook_nand_partitions,
+                        ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index bfcd397e233c..8c00b99cd2a3 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -29,6 +29,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/ti_wilink_st.h>
+#include <linux/usb/musb.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
@@ -38,12 +39,11 @@
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 
-#include "common.h"
-#include <plat/usb.h>
-#include <plat/mmc.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "common.h"
 #include "soc.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index b700685762b5..1cfb0374f5e2 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -49,14 +49,17 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
 
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
+#include "gpmc.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define NAND_CS                 0
+
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
 #define OVERO_GPIO_PENDOWN      114
@@ -495,8 +498,8 @@ static void __init overo_init(void)
         omap_serial_init();
         omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
-        omap_nand_flash_init(0, overo_nand_partitions,
-                             ARRAY_SIZE(overo_nand_partitions));
+        board_nand_init(overo_nand_partitions,
+                        ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
         usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 45997bfbcbd2..1997e0e722a1 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -22,17 +22,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <plat/i2c.h>
-#include <plat/mmc.h>
-#include <plat/usb.h>
-#include <plat/gpmc.h>
 #include "common.h"
-#include <plat/serial.h>
-
 #include "mux.h"
+#include "gpmc.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "sdram-nokia.h"
 #include "common-board-devices.h"
+#include "gpmc-onenand.h"
 
 static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 020e03c95bfe..07005fe40a2a 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -31,9 +31,7 @@
 #include <asm/system_info.h>
 
 #include "common.h"
-#include <plat/dma.h>
-#include <plat/gpmc.h>
-#include <plat/omap-pm.h>
+#include <plat-omap/dma-omap.h>
 #include "gpmc-smc91x.h"
 
 #include "board-rx51.h"
@@ -52,8 +50,11 @@
 #endif
 
 #include "mux.h"
+#include "omap-pm.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-onenand.h"
 
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
 #define SYSTEM_REV_S_USES_VAUX3 0x8
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 7bbb05d9689b..c388aec14799 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,18 +17,18 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/usb/musb.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-#include <plat/dma.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
+#include <plat-omap/dma-omap.h>
 
+#include "common.h"
 #include "mux.h"
+#include "gpmc.h"
 #include "pm.h"
 #include "sdram-nokia.h"
 
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index c4f8833b4c3c..5e672c2b6a43 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -14,13 +14,14 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/usb/musb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 
 static struct omap_musb_board_data musb_board_data = {
         .set_phy_power  = ti81xx_musb_phy_power,
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index afb2278a29f6..42e5f231a799 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -17,10 +17,10 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smsc911x.h"
 
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 
 #include "soc.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index b940ab2259fb..1c7c834a5b5f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,8 +16,9 @@
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 
+#include "soc.h"
 #include "common.h"
 
 #define LCD_PANEL_RESET_GPIO_PROD       96
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c166fe1fdff9..26e07addc9d7 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -26,9 +26,8 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
-#include <plat/usb.h>
 
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 
 #include "mux.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4994438e1f46..8feb4d99b96d 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -22,9 +22,8 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/usb.h>
 
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 
 #include "board-flash.h"
 #include "mux.h"
@@ -113,8 +112,9 @@ static void __init omap_zoom_init(void)
                 usbhs_init(&usbhs_bdata);
         }
 
-        board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
-                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+        board_nand_init(zoom_nand_partitions,
+                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+                        NAND_BUSWIDTH_16, nand_default_timings);
         zoom_debugboard_init();
         zoom_peripherals_init();
 
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/board-zoom.h
index 2e9486940ead..2e9486940ead 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/board-zoom.h
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index c2d15212d64d..e3f0c1e262a7 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -21,12 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
 #include <plat/prcm.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
index 1502a7bc20bb..399534c7843b 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -14,10 +14,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* Private functions */
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 4ae439222085..0d2f14c2dcce 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -25,15 +25,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "sram.h"
 
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index c3460928b5e0..e1777371bb5e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -23,8 +23,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 #include "clock2xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 8693cfdac49a..46683b3c2461 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -22,8 +22,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 #include "clock2xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3524f0e7b6d5..a38ebb209721 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,16 +33,14 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "sram.h"
 
 const struct prcm_config *curr_prcm_set;
 const struct prcm_config *rate_table;
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 7c6da2f731dc..6cf298e262f6 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -21,14 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-
 #include "clock.h"
 #include "clock3xxx.h"
 #include "clock34xx.h"
 #include "sdrc.h"
+#include "sram.h"
 
 #define CYCLES_PER_MHZ                  1000000
 
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 3ff22114d702..53646facda45 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -45,8 +45,6 @@
 #include <linux/io.h>
 #include <linux/bug.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 
 /* Private functions */
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 80411142f482..8463cc356245 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -21,8 +21,6 @@
 
 #include <asm/div64.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 3d43fba2542f..7c8d41e49834 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -14,7 +14,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
 #include <plat/prcm.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 961ac8f7e13d..9205ea7d8dde 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -15,6 +15,7 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
@@ -25,7 +26,6 @@
 
 #include <asm/cpu.h>
 
-#include <plat/clock.h>
 #include <plat/prcm.h>
 
 #include <trace/events/power.h>
@@ -33,7 +33,8 @@
 #include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
@@ -47,6 +48,10 @@ u16 cpu_mask;
  */
 static bool clkdm_control = true;
 
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+static DEFINE_SPINLOCK(clockfw_lock);
+
 /*
  * OMAP2+ specific clock functions
  */
@@ -512,12 +517,510 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 
 /* Common data */
 
-struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        int ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap2_clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->usecount == 0) {
+                pr_err("Trying disable clock %s with 0 usecount\n",
+                       clk->name);
+                WARN_ON(1);
+                goto out;
+        }
+
+        omap2_clk_disable(clk);
+
+out:
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long flags;
+        unsigned long ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = clk->rate;
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/*
+ * Optional clock functions defined in include/linux/clk.h
+ */
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        long ret;
+
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap2_clk_round_rate(clk, rate);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap2_clk_set_rate(clk, rate);
+        if (ret == 0)
+                propagate_rate(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
+                return ret;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->usecount == 0) {
+                ret = omap2_clk_set_parent(clk, parent);
+                if (ret == 0)
+                        propagate_rate(clk);
+        } else {
+                ret = -EBUSY;
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+/*
+ * OMAP specific clock functions shared between omap1 and omap2
+ */
+
+int __initdata mpurate;
+
+/*
+ * By default we use the rate set by the bootloader.
+ * You can override this with mpurate= cmdline option.
+ */
+static int __init omap_clk_setup(char *str)
+{
+        get_option(&str, &mpurate);
+
+        if (!mpurate)
+                return 1;
+
+        if (mpurate < 1000)
+                mpurate *= 1000000;
+
+        return 1;
+}
+__setup("mpurate=", omap_clk_setup);
+
+/* Used for clocks that always have same value as the parent clock */
+unsigned long followparent_recalc(struct clk *clk)
+{
+        return clk->parent->rate;
+}
+
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+
+        return clk->parent->rate / clk->fixed_div;
+}
+
+void clk_reparent(struct clk *child, struct clk *parent)
+{
+        list_del_init(&child->sibling);
+        if (parent)
+                list_add(&child->sibling, &parent->children);
+        child->parent = parent;
+
+        /* now do the debugfs renaming to reattach the child
+           to the proper parent */
+}
+
+/* Propagate rate to children */
+void propagate_rate(struct clk *tclk)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &tclk->children, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+
+static LIST_HEAD(root_clks);
+
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &root_clks, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+
+/**
+ * clk_preinit - initialize any fields in the struct clk before clk init
+ * @clk: struct clk * to initialize
+ *
+ * Initialize any struct clk fields needed before normal clk initialization
+ * can run.  No return value.
+ */
+void clk_preinit(struct clk *clk)
+{
+        INIT_LIST_HEAD(&clk->children);
+}
+
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        /*
+         * trap out already registered clocks
+         */
+        if (clk->node.next || clk->node.prev)
+                return 0;
+
+        mutex_lock(&clocks_mutex);
+        if (clk->parent)
+                list_add(&clk->sibling, &clk->parent->children);
+        else
+                list_add(&clk->sibling, &root_clks);
+
+        list_add(&clk->node, &clocks);
+        if (clk->init)
+                clk->init(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->sibling);
+        list_del(&clk->node);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+
+void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clocks, node)
+                if (clkp->flags & ENABLE_ON_INIT)
+                        clk_enable(clkp);
+}
+
+/**
+ * omap_clk_get_by_name - locate OMAP struct clk by its name
+ * @name: name of the struct clk to locate
+ *
+ * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ * names are unique.  Returns NULL if not found or a pointer to the
+ * struct clk if found.
+ */
+struct clk *omap_clk_get_by_name(const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+
+        mutex_lock(&clocks_mutex);
+
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+/*
+ * Low level helpers
+ */
+static int clkll_enable_null(struct clk *clk)
+{
+        return 0;
+}
+
+static void clkll_disable_null(struct clk *clk)
+{
+}
+
+const struct clkops clkops_null = {
+        .enable         = clkll_enable_null,
+        .disable        = clkll_disable_null,
+};
+
+/*
+ * Dummy clock
+ *
+ * Used for clock aliases that are needed on some OMAPs, but not others
+ */
+struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_null,
+};
+
+/*
+ *
+ */
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+/*
+ * Disable any unused clocks left on by the bootloader
+ */
+static int __init clk_disable_unused(void)
+{
+        struct clk *ck;
+        unsigned long flags;
+
+        pr_info("clock: disabling unused clocks to save power\n");
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(ck, &clocks, node) {
+                if (ck->ops == &clkops_null)
+                        continue;
+
+                if (ck->usecount > 0 || !ck->enable_reg)
+                        continue;
+
+                omap2_clk_disable_unused(ck);
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static struct dentry *clk_debugfs_root;
+
+static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+{
+        struct clk *c;
+        struct clk *pa;
+
+        mutex_lock(&clocks_mutex);
+        seq_printf(s, "%-30s %-30s %-10s %s\n",
+                   "clock-name", "parent-name", "rate", "use-count");
+
+        list_for_each_entry(c, &clocks, node) {
+                pa = c->parent;
+                seq_printf(s, "%-30s %-30s %-10lu %d\n",
+                           c->name, pa ? pa->name : "none", c->rate,
+                           c->usecount);
+        }
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+
+static int clk_dbg_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_dbg_show_summary, inode->i_private);
+}
+
+static const struct file_operations debug_clock_fops = {
+        .open           = clk_dbg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
 };
 
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d;
+        struct clk *pa = c->parent;
+
+        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
+        if (!d)
+                return -ENOMEM;
+        c->dent = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        return 0;
+
+err_out:
+        debugfs_remove_recursive(c->dent);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clocks, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+
+        d = debugfs_create_file("summary", S_IRUGO,
+                d, NULL, &debug_clock_fops);
+        if (!d)
+                return -ENOMEM;
+
+        return 0;
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+late_initcall(clk_debugfs_init);
+
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 35ec5f3d9a73..cfba1ffe5cc2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -17,8 +17,323 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
 #include <linux/kernel.h>
+#include <linux/list.h>
+
+#include <linux/clkdev.h>
+
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+/* Platform flags for the clkdev-OMAP integration code */
+#define CK_242X         (1 << 0)
+#define CK_243X         (1 << 1)        /* 243x, 253x */
+#define CK_3430ES1      (1 << 2)        /* 34xxES1 only */
+#define CK_3430ES2PLUS  (1 << 3)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_AM35XX       (1 << 4)        /* Sitara AM35xx */
+#define CK_36XX         (1 << 5)        /* 36xx/37xx-specific clocks */
+#define CK_443X         (1 << 6)
+#define CK_TI816X       (1 << 7)
+#define CK_446X         (1 << 8)
+#define CK_AM33XX       (1 << 9)        /* AM33xx specific clocks */
+
+
+#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
+#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
+
+struct module;
+struct clk;
+struct clockdomain;
+
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
+
+/**
+ * struct clkops - some clock function pointers
+ * @enable: fn ptr that enables the current clock in hardware
+ * @disable: fn ptr that enables the current clock in hardware
+ * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
+ *
+ * A "companion" clk is an accompanying clock to the one being queried
+ * that must be enabled for the IP module connected to the clock to
+ * become accessible by the hardware.  Neither @find_idlest nor
+ * @find_companion should be needed; that information is IP
+ * block-specific; the hwmod code has been created to handle this, but
+ * until hwmod data is ready and drivers have been converted to use PM
+ * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
+ * @find_companion must, unfortunately, remain.
+ */
+struct clkops {
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **,
+                                               u8 *, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **,
+                                                  u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
+};
+
+/* struct clksel_rate.flags possibilities */
+#define RATE_IN_242X            (1 << 0)
+#define RATE_IN_243X            (1 << 1)
+#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
+#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
+#define RATE_IN_36XX            (1 << 4)
+#define RATE_IN_4430            (1 << 5)
+#define RATE_IN_TI816X          (1 << 6)
+#define RATE_IN_4460            (1 << 7)
+#define RATE_IN_AM33XX          (1 << 8)
+#define RATE_IN_TI814X          (1 << 9)
+
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
+#define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
+
+/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
+
+
+/**
+ * struct clksel_rate - register bitfield values corresponding to clk divisors
+ * @val: register bitfield value (shifted to bit 0)
+ * @div: clock divisor corresponding to @val
+ * @flags: (see "struct clksel_rate.flags possibilities" above)
+ *
+ * @val should match the value of a read from struct clk.clksel_reg
+ * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
+ *
+ * @div is the divisor that should be applied to the parent clock's rate
+ * to produce the current clock's rate.
+ */
+struct clksel_rate {
+        u32                     val;
+        u8                      div;
+        u16                     flags;
+};
+
+/**
+ * struct clksel - available parent clocks, and a pointer to their divisors
+ * @parent: struct clk * to a possible parent clock
+ * @rates: available divisors for this parent clock
+ *
+ * A struct clksel is always associated with one or more struct clks
+ * and one or more struct clksel_rates.
+ */
+struct clksel {
+        struct clk               *parent;
+        const struct clksel_rate *rates;
+};
+
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+        void __iomem            *mult_div1_reg;
+        u32                     mult_mask;
+        u32                     div1_mask;
+        struct clk              *clk_bypass;
+        struct clk              *clk_ref;
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        unsigned long           last_rounded_rate;
+        u16                     last_rounded_m;
+        u16                     max_multiplier;
+        u8                      last_rounded_n;
+        u8                      min_divider;
+        u16                     max_divider;
+        u8                      modes;
+        void __iomem            *autoidle_reg;
+        void __iomem            *idlest_reg;
+        u32                     autoidle_mask;
+        u32                     freqsel_mask;
+        u32                     idlest_mask;
+        u32                     dco_mask;
+        u32                     sddiv_mask;
+        u8                      auto_recal_bit;
+        u8                      recal_en_bit;
+        u8                      recal_st_bit;
+        u8                      flags;
+};
+
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
+
+/**
+ * struct clk - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @ops: struct clkops * for this clock
+ * @name: the name of the clock in the hardware (used in hwmod data and debug)
+ * @parent: pointer to this clock's parent struct clk
+ * @children: list_head connecting to the child clks' @sibling list_heads
+ * @sibling: list_head connecting this clk to its parent clk's @children
+ * @rate: current clock rate
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @recalc: fn ptr that returns the clock's current rate
+ * @set_rate: fn ptr that can change the clock's current rate
+ * @round_rate: fn ptr that can round the clock's current rate
+ * @init: fn ptr to do clock-specific initialization
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @usecount: number of users that have requested this clock to be enabled
+ * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ * XXX @usecount is poorly named.  It should be "enable_count" or
+ * something similar.  "users" in the description refers to kernel
+ * code (core code or drivers) that have called clk_enable() and not
+ * yet called clk_disable(); the usecount of parent clocks is also
+ * incremented by the clock code when clk_enable() is called on child
+ * clocks and decremented by the clock code when clk_disable() is
+ * called on child clocks.
+ *
+ * XXX @clkdm, @usecount, @children, @sibling should be marked for
+ * internal use only.
+ *
+ * @children and @sibling are used to optimize parent-to-child clock
+ * tree traversals.  (child-to-parent traversals use @parent.)
+ *
+ * XXX The notion of the clock's current rate probably needs to be
+ * separated from the clock's target rate.
+ */
+struct clk {
+        struct list_head        node;
+        const struct clkops     *ops;
+        const char              *name;
+        struct clk              *parent;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
+        unsigned long           rate;
+        void __iomem            *enable_reg;
+        unsigned long           (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        u8                      enable_bit;
+        s8                      usecount;
+        u8                      fixed_div;
+        u8                      flags;
+        void __iomem            *clksel_reg;
+        u32                     clksel_mask;
+        const struct clksel     *clksel;
+        struct dpll_data        *dpll_data;
+        const char              *clkdm_name;
+        struct clockdomain      *clkdm;
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
+};
+
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
+};
+
+extern int mpurate;
+
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_preinit(struct clk *clk);
+extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
+extern unsigned long followparent_recalc(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
+extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
+
+extern const struct clkops clkops_null;
+
+extern struct clk dummy_ck;
 
-#include <plat/clock.h>
 
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
 #define CORE_CLK_SRC_32K                0x0
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index c3cde1a2b6de..da1e388f22f7 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -18,14 +18,12 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/clkdev_omap.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
@@ -1935,8 +1933,6 @@ int __init omap2420_clk_init(void)
         cpu_mask = RATE_IN_242X;
         rate_table = omap2420_rate_table;
 
-        clk_init(&omap2_clk_functions);
-
         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
              c++)
                 clk_preinit(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index a8e326177466..e37df538bcd3 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,13 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 
 /**
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 22404fe435e7..c97dafef894d 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,14 +17,12 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/clkdev_omap.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
@@ -2034,8 +2032,6 @@ int __init omap2430_clk_init(void)
         cpu_mask = RATE_IN_243X;
         rate_table = omap2430_rate_table;
 
-        clk_init(&omap2_clk_functions);
-
         for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
              c++)
                 clk_preinit(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index e92be1fc1a00..5feee16fee0e 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,8 +22,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 1a45d6bd2539..17e3de51bcba 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -17,9 +17,8 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
-#include <plat/clkdev_omap.h>
 
-#include "am33xx.h"
+#include "soc.h"
 #include "iomap.h"
 #include "control.h"
 #include "clock.h"
@@ -1087,8 +1086,6 @@ int __init am33xx_clk_init(void)
                 cpu_clkflg = CK_AM33XX;
         }
 
-        clk_init(&omap2_clk_functions);
-
         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
                 clk_preinit(c->lk.clk);
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 1fc96b9ee330..e41819ba7482 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -21,11 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 #include "clock34xx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /**
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 2e97d08f0e56..622ea0502610 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -21,11 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 #include "clock3517.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 0c5e25ed8879..0e1e9e4e2fa4 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -22,8 +22,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "clock.h"
 #include "clock36xx.h"
 
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 83bb01427d40..3e8aca2b1b61 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,8 +21,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1f42c9d5ecf3..6cca19953950 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -21,8 +21,6 @@
 #include <linux/list.h>
 #include <linux/io.h>
 
-#include <plat/clkdev_omap.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
@@ -30,7 +28,7 @@
 #include "clock34xx.h"
 #include "clock36xx.h"
 #include "clock3517.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
@@ -3573,8 +3571,6 @@ int __init omap3xxx_clk_init(void)
         else
                 dpll4_dd = dpll4_dd_34xx;
 
-        clk_init(&omap2_clk_functions);
-
         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
              c++)
                 clk_preinit(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 6efc30c961a5..2a450c9b9a7b 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -28,8 +28,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clkdev_omap.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
@@ -3366,8 +3364,6 @@ int __init omap4xxx_clk_init(void)
                 return 0;
         }
 
-        clk_init(&omap2_clk_functions);
-
         /*
          * Must stay commented until all OMAP SoC drivers are
          * converted to runtime PM, or drivers may start crashing
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 512e79a842cb..64e50465a4b5 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -27,7 +27,8 @@
 
 #include <linux/bitops.h>
 
-#include <plat/clock.h>
+#include "soc.h"
+#include "clock.h"
 #include "clockdomain.h"
 
 /* clkdm_list contains all registered struct clockdomains */
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 629576be7444..bc42446e23ab 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,9 +18,8 @@
 #include <linux/spinlock.h>
 
 #include "powerdomain.h"
-#include <plat/clock.h>
-#include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
+#include "clock.h"
+#include "omap_hwmod.h"
 
 /*
  * Clockdomain flags
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
deleted file mode 100644
index 70294f54e35a..000000000000
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * OMAP2 and OMAP3 clockdomain control
- *
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/types.h>
-#include <plat/prcm.h>
-#include "prm.h"
-#include "prm2xxx_3xxx.h"
-#include "cm.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
-#include "prm-regbits-24xx.h"
-#include "clockdomain.h"
-
-static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
-                                                struct clockdomain *clkdm2)
-{
-        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
-        return 0;
-}
-
-static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
-        return 0;
-}
-
-static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                PM_WKDEP, (1 << clkdm2->dep_bit));
-}
-
-static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-
-        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
-        }
-
-        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
-                                 PM_WKDEP);
-        return 0;
-}
-
-static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-
-static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-
-static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
-}
-
-static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-
-        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->sleepdep_usecount, 0);
-        }
-        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-
-static int omap2_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                                clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-
-static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                                clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-
-static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
-
-        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-}
-
-static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_del_autodeps(clkdm);
-}
-
-static void _enable_hwsup(struct clockdomain *clkdm)
-{
-        if (cpu_is_omap24xx())
-                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-        else if (cpu_is_omap34xx())
-                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-}
-
-static void _disable_hwsup(struct clockdomain *clkdm)
-{
-        if (cpu_is_omap24xx())
-                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-        else if (cpu_is_omap34xx())
-                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-}
-
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
-static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_add_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                        omap2_clkdm_wakeup(clkdm);
-        }
-
-        return 0;
-}
-
-static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_del_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                        omap2_clkdm_sleep(clkdm);
-        }
-
-        return 0;
-}
-
-static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
-
-        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-}
-
-static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_del_autodeps(clkdm);
-}
-
-static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
-            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-                omap3_clkdm_wakeup(clkdm);
-                return 0;
-        }
-
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_add_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                        omap3_clkdm_wakeup(clkdm);
-        }
-
-        return 0;
-}
-
-static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
-            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                _enable_hwsup(clkdm);
-                return 0;
-        }
-
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_del_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                        omap3_clkdm_sleep(clkdm);
-        }
-
-        return 0;
-}
-
-struct clkdm_ops omap2_clkdm_operations = {
-        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
-        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
-        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
-        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
-        .clkdm_sleep            = omap2_clkdm_sleep,
-        .clkdm_wakeup           = omap2_clkdm_wakeup,
-        .clkdm_allow_idle       = omap2_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap2_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
-};
-
-struct clkdm_ops omap3_clkdm_operations = {
-        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
-        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
-        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
-        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
-        .clkdm_add_sleepdep     = omap3_clkdm_add_sleepdep,
-        .clkdm_del_sleepdep     = omap3_clkdm_del_sleepdep,
-        .clkdm_read_sleepdep    = omap3_clkdm_read_sleepdep,
-        .clkdm_clear_all_sleepdeps      = omap3_clkdm_clear_all_sleepdeps,
-        .clkdm_sleep            = omap3_clkdm_sleep,
-        .clkdm_wakeup           = omap3_clkdm_wakeup,
-        .clkdm_allow_idle       = omap3_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap3_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
deleted file mode 100644
index aca6388fad76..000000000000
--- a/arch/arm/mach-omap2/clockdomain33xx.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * AM33XX clockdomain control
- *
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-
-#include "clockdomain.h"
-#include "cm33xx.h"
-
-
-static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-
-static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-
-static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-}
-
-static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-}
-
-static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                return am33xx_clkdm_wakeup(clkdm);
-
-        return 0;
-}
-
-static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-
-        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
-                am33xx_clkdm_sleep(clkdm);
-
-        return 0;
-}
-
-struct clkdm_ops am33xx_clkdm_operations = {
-        .clkdm_sleep            = am33xx_clkdm_sleep,
-        .clkdm_wakeup           = am33xx_clkdm_wakeup,
-        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
-        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
-        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
-        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
deleted file mode 100644
index 6fc6155625bc..000000000000
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * OMAP4 clockdomain control
- *
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include "clockdomain.h"
-#include "cminst44xx.h"
-#include "cm44xx.h"
-
-static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
-                                        clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-
-static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
-                                        clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-
-static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP,
-                                        (1 << clkdm2->dep_bit));
-}
-
-static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-
-        if (!clkdm->prcm_partition)
-                return 0;
-
-        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
-        }
-
-        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-
-static int omap4_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-
-static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-
-static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-}
-
-static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                omap4_clkdm_wakeup(clkdm);
-        else
-                omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
-                                                 clkdm->cm_inst,
-                                                 clkdm->clkdm_offs);
-}
-
-static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                return omap4_clkdm_wakeup(clkdm);
-
-        return 0;
-}
-
-static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-
-        if (!clkdm->prcm_partition)
-                return 0;
-
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
-            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                omap4_clkdm_allow_idle(clkdm);
-                return 0;
-        }
-
-        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-
-        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
-                omap4_clkdm_sleep(clkdm);
-
-        return 0;
-}
-
-struct clkdm_ops omap4_clkdm_operations = {
-        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
-        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
-        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
-        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
-        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
-        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
-        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
-        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
-        .clkdm_sleep            = omap4_clkdm_sleep,
-        .clkdm_wakeup           = omap4_clkdm_wakeup,
-        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 5c741852fac0..7e76becf3a4a 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -35,6 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index f09617555e15..b923007e45d0 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -35,6 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 933a35cd124a..e6b91e552d3d 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -33,6 +33,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index f24e3f7a2bbc..b3cee913dd67 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -33,4 +33,16 @@
  */
 #define MAX_MODULE_DISABLE_TIME         5000
 
+# ifndef __ASSEMBLER__
+
+/**
+ * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
+ */
+struct cm_ll_data {};
+
+extern int cm_register(struct cm_ll_data *cld);
+extern int cm_unregister(struct cm_ll_data *cld);
+
+# endif
+
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
new file mode 100644
index 000000000000..64165013daf9
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -0,0 +1,255 @@
+/*
+ * OMAP2xxx CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "common.h"
+#include "prm2xxx.h"
+#include "cm.h"
+#include "cm2xxx.h"
+#include "cm-regbits-24xx.h"
+#include "clockdomain.h"
+
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+#define DPLL_AUTOIDLE_DISABLE                           0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
+static const u8 omap2xxx_cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
+};
+
+/*
+ *
+ */
+
+static void _write_clktrctrl(u8 c, s16 module, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= ~mask;
+        v |= c << __ffs(mask);
+        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
+}
+
+bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+}
+
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+
+/*
+ * DPLL autoidle control
+ */
+
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
+
+/*
+ * APLL autoidle control
+ */
+
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~mask;
+        v |= m << __ffs(mask);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+
+/*
+ *
+ */
+
+/**
+ * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
+ * success or -EBUSY if the module doesn't enable in time.
+ */
+int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
+                return -EINVAL;
+
+        cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
+
+        mask = 1 << idlest_shift;
+        ena = mask;
+
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
+                            mask) == ena), MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/* Clockdomain low-level functions */
+
+static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+
+        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                       clkdm->clktrctrl_mask);
+}
+
+static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                        clkdm->clktrctrl_mask);
+
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+
+static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_add_autodeps(clkdm);
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2xxx_clkdm_wakeup(clkdm);
+        }
+
+        return 0;
+}
+
+static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_del_autodeps(clkdm);
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap2xxx_clkdm_sleep(clkdm);
+        }
+
+        return 0;
+}
+
+struct clkdm_ops omap2_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_sleep            = omap2xxx_clkdm_sleep,
+        .clkdm_wakeup           = omap2xxx_clkdm_wakeup,
+        .clkdm_allow_idle       = omap2xxx_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap2xxx_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2xxx_clkdm_clk_disable,
+};
+
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
new file mode 100644
index 000000000000..bce3c4be6d1f
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -0,0 +1,66 @@
+/*
+ * OMAP2xxx Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
+
+#include "prcm-common.h"
+#include "cm2xxx_3xxx.h"
+
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* OMAP2-specific register offsets */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP24XX_CM_IDLEST_VAL                          0
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+
+extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
+extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                         u8 idlest_shift);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 57b2f3c2fbf3..0e26bb1bf7e2 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -18,27 +18,6 @@
 
 #include "prcm-common.h"
 
-#define OMAP2420_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-#define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-
-
-/*
- * OMAP3-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
- * These registers appear once per CM module.
- */
-
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
-
-#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
-#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
 /*
  * Module specific CM register offsets from CM_BASE + domain offset
  * Use cm_{read,write}_mod_reg() with these registers.
@@ -57,6 +36,7 @@
 #define CM_IDLEST                                       0x0020
 #define CM_IDLEST1                                      CM_IDLEST
 #define CM_IDLEST2                                      0x0024
+#define OMAP2430_CM_IDLEST3                             0x0028
 #define CM_AUTOIDLE                                     0x0030
 #define CM_AUTOIDLE1                                    CM_AUTOIDLE
 #define CM_AUTOIDLE2                                    0x0034
@@ -66,70 +46,55 @@
 #define CM_CLKSEL2                                      0x0044
 #define OMAP2_CM_CLKSTCTRL                              0x0048
 
-/* OMAP2-specific register offsets */
-
-#define OMAP24XX_CM_FCLKEN2                             0x0004
-#define OMAP24XX_CM_ICLKEN4                             0x001c
-#define OMAP24XX_CM_AUTOIDLE4                           0x003c
-#define OMAP24XX_CM_IDLEST4                             0x002c
-
-#define OMAP2430_CM_IDLEST3                             0x0028
-
-/* OMAP3-specific register offsets */
-
-#define OMAP3430_CM_CLKEN_PLL                           0x0004
-#define OMAP3430ES2_CM_CLKEN2                           0x0004
-#define OMAP3430ES2_CM_FCLKEN3                          0x0008
-#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
-#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
-#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
-#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
-#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
-#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
-#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
-#define OMAP3430_CM_CLKSTST                             0x004c
-#define OMAP3430ES2_CM_CLKSEL4                          0x004c
-#define OMAP3430ES2_CM_CLKSEL5                          0x0050
-#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
-#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
-
+#ifndef __ASSEMBLER__
 
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+#include <linux/io.h>
 
-#define OMAP24XX_CM_IDLEST_VAL                          0
-#define OMAP34XX_CM_IDLEST_VAL                          1
+static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(cm_base + module + idx);
+}
 
+static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, cm_base + module + idx);
+}
 
-/* Clock management domain register get/set */
+/* Read-modify-write a register in a CM module. Caller must lock */
+static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
+                                            s16 idx)
+{
+        u32 v;
 
-#ifndef __ASSEMBLER__
+        v = omap2_cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_cm_write_mod_reg(v, module, idx);
 
-extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
-extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+        return v;
+}
 
-extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-                                      u8 idlest_shift);
-extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
-extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+/* Read a CM register, AND it, and shift the result down to bit 0 */
+static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
 
-extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
-extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+        v = omap2_cm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
 
-extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+        return v;
+}
 
-extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
-extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
 
-extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
-extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
 
 #endif
 
@@ -147,10 +112,4 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
 #define OMAP_ST_GFX_MASK                                (1 << 0)
 
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern void omap3_cm_save_context(void);
-extern void omap3_cm_restore_context(void);
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 13f56eafef03..058ce3c0873e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -22,8 +22,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/common.h>
-
+#include "clockdomain.h"
 #include "cm.h"
 #include "cm33xx.h"
 #include "cm-regbits-34xx.h"
@@ -311,3 +310,58 @@ void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
         v &= ~AM33XX_MODULEMODE_MASK;
         am33xx_cm_write_reg(v, inst, clkctrl_offs);
 }
+
+/*
+ * Clockdomain low-level functions
+ */
+
+static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return am33xx_clkdm_wakeup(clkdm);
+
+        return 0;
+}
+
+static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                am33xx_clkdm_sleep(clkdm);
+
+        return 0;
+}
+
+struct clkdm_ops am33xx_clkdm_operations = {
+        .clkdm_sleep            = am33xx_clkdm_sleep,
+        .clkdm_wakeup           = am33xx_clkdm_wakeup,
+        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
+        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
+        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
+        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 7f07ab02a5b3..8b03ec2f4394 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -1,8 +1,10 @@
 /*
- * OMAP2/3 CM module functions
+ * OMAP3xxx CM module functions
  *
  * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
  * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,8 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -21,56 +21,16 @@
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
+#include "prm2xxx_3xxx.h"
 #include "cm.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "clockdomain.h"
 
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
-#define DPLL_AUTOIDLE_DISABLE                           0x0
-#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
-
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
-#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
-#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
-
-static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
+static const u8 omap3xxx_cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
 };
 
-u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
-{
-        return __raw_readl(cm_base + module + idx);
-}
-
-void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __raw_writel(val, cm_base + module + idx);
-}
-
-/* Read-modify-write a register in a CM module. Caller must lock */
-u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = omap2_cm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        omap2_cm_write_mod_reg(v, module, idx);
-
-        return v;
-}
-
-u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
 /*
  *
  */
@@ -85,33 +45,15 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
 }
 
-bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
 {
         u32 v;
-        bool ret = 0;
-
-        BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
 
         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
         v &= mask;
         v >>= __ffs(mask);
 
-        if (cpu_is_omap24xx())
-                ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-        else
-                ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-
-        return ret;
-}
-
-void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
-{
-        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
-}
-
-void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
-{
-        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
 }
 
 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
@@ -135,109 +77,209 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 }
 
 /*
- * DPLL autoidle control
+ *
  */
 
-static void _omap2xxx_set_dpll_autoidle(u8 m)
+/**
+ * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
+ * success or -EBUSY if the module doesn't enable in time.
+ */
+int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 {
-        u32 v;
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
+                return -EINVAL;
+
+        cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
+
+        mask = 1 << idlest_shift;
+        ena = 0;
+
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
+                            mask) == ena), MAX_MODULE_READY_TIME, i);
 
-        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
-        v &= ~OMAP24XX_AUTO_DPLL_MASK;
-        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
-        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
 
-void omap2xxx_cm_set_dpll_disable_autoidle(void)
+/* Clockdomain low-level operations */
+
+static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
+                                       struct clockdomain *clkdm2)
 {
-        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                  clkdm1->pwrdm.ptr->prcm_offs,
+                                  OMAP3430_CM_SLEEPDEP);
+        return 0;
 }
 
-void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
+                                       struct clockdomain *clkdm2)
 {
-        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                    clkdm1->pwrdm.ptr->prcm_offs,
+                                    OMAP3430_CM_SLEEPDEP);
+        return 0;
 }
 
-/*
- * APLL autoidle control
- */
-
-static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
 {
-        u32 v;
-
-        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
-        v &= ~mask;
-        v |= m << __ffs(mask);
-        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+        return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                            OMAP3430_CM_SLEEPDEP,
+                                            (1 << clkdm2->dep_bit));
 }
 
-void omap2xxx_cm_set_apll54_disable_autoidle(void)
+static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
-                                    OMAP24XX_AUTO_54M_MASK);
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->sleepdep_usecount, 0);
+        }
+        omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                    OMAP3430_CM_SLEEPDEP);
+        return 0;
 }
 
-void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
-                                    OMAP24XX_AUTO_54M_MASK);
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                      clkdm->clktrctrl_mask);
+        return 0;
 }
 
-void omap2xxx_cm_set_apll96_disable_autoidle(void)
+static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
-                                    OMAP24XX_AUTO_96M_MASK);
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                       clkdm->clktrctrl_mask);
+        return 0;
 }
 
-void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
-                                    OMAP24XX_AUTO_96M_MASK);
-}
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
 
-/*
- *
- */
+        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                       clkdm->clktrctrl_mask);
+}
 
-/**
- * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
- * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
- *
- * XXX document
- */
-int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
 {
-        int ena = 0, i = 0;
-        u8 cm_idlest_reg;
-        u32 mask;
+        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                        clkdm->clktrctrl_mask);
 
-        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
-                return -EINVAL;
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
 
-        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
 
-        mask = 1 << idlest_shift;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
 
-        if (cpu_is_omap24xx())
-                ena = mask;
-        else if (cpu_is_omap34xx())
-                ena = 0;
-        else
-                BUG();
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3xxx_clkdm_wakeup(clkdm);
+                return 0;
+        }
+
+        hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_add_autodeps(clkdm);
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap3xxx_clkdm_wakeup(clkdm);
+        }
+
+        return 0;
+}
 
-        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
-                          MAX_MODULE_READY_TIME, i);
+static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
 
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+                return 0;
+        }
+
+        hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_del_autodeps(clkdm);
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap3xxx_clkdm_sleep(clkdm);
+        }
+
+        return 0;
 }
 
+struct clkdm_ops omap3_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_add_sleepdep     = omap3xxx_clkdm_add_sleepdep,
+        .clkdm_del_sleepdep     = omap3xxx_clkdm_del_sleepdep,
+        .clkdm_read_sleepdep    = omap3xxx_clkdm_read_sleepdep,
+        .clkdm_clear_all_sleepdeps      = omap3xxx_clkdm_clear_all_sleepdeps,
+        .clkdm_sleep            = omap3xxx_clkdm_sleep,
+        .clkdm_wakeup           = omap3xxx_clkdm_wakeup,
+        .clkdm_allow_idle       = omap3xxx_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap3xxx_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
+};
+
 /*
  * Context save/restore code - OMAP3 only
  */
-#ifdef CONFIG_ARCH_OMAP3
 struct omap3_cm_regs {
         u32 iva2_cm_clksel1;
         u32 iva2_cm_clksel2;
@@ -555,4 +597,3 @@ void omap3_cm_restore_context(void)
         omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
 }
-#endif
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
new file mode 100644
index 000000000000..4a6ac812edf4
--- /dev/null
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -0,0 +1,86 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
+
+#include "prcm-common.h"
+#include "cm2xxx_3xxx.h"
+
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP3-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* OMAP3-specific register offsets */
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP34XX_CM_IDLEST_VAL                          1
+
+
+#ifndef __ASSEMBLER__
+
+extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+
+extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                         u8 idlest_shift);
+
+extern void omap3_cm_save_context(void);
+extern void omap3_cm_restore_context(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
new file mode 100644
index 000000000000..3246cef151dc
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -0,0 +1,71 @@
+/*
+ * OMAP2+ common Clock Management (CM) IP block functions
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley <paul@pwsan.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This code should eventually be moved to a CM driver.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "cm2xxx.h"
+#include "cm3xxx.h"
+#include "cm44xx.h"
+
+/*
+ * cm_ll_data: function pointers to SoC-specific implementations of
+ * common CM functions
+ */
+static struct cm_ll_data null_cm_ll_data;
+static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
+
+/**
+ * cm_register - register per-SoC low-level data with the CM
+ * @cld: low-level per-SoC OMAP CM data & function pointers to register
+ *
+ * Register per-SoC low-level OMAP CM data and function pointers with
+ * the OMAP CM common interface.  The caller must keep the data
+ * pointed to by @cld valid until it calls cm_unregister() and
+ * it returns successfully.  Returns 0 upon success, -EINVAL if @cld
+ * is NULL, or -EEXIST if cm_register() has already been called
+ * without an intervening cm_unregister().
+ */
+int cm_register(struct cm_ll_data *cld)
+{
+        if (!cld)
+                return -EINVAL;
+
+        if (cm_ll_data != &null_cm_ll_data)
+                return -EEXIST;
+
+        cm_ll_data = cld;
+
+        return 0;
+}
+
+/**
+ * cm_unregister - unregister per-SoC low-level data & function pointers
+ * @cld: low-level per-SoC OMAP CM data & function pointers to unregister
+ *
+ * Unregister per-SoC low-level OMAP CM data and function pointers
+ * that were previously registered with cm_register().  The
+ * caller may not destroy any of the data pointed to by @cld until
+ * this function returns successfully.  Returns 0 upon success, or
+ * -EINVAL if @cld is NULL or if @cld does not match the struct
+ * cm_ll_data * previously registered by cm_register().
+ */
+int cm_unregister(struct cm_ll_data *cld)
+{
+        if (!cld || cm_ll_data != cld)
+                return -EINVAL;
+
+        cm_ll_data = &null_cm_ll_data;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 1894015ff04b..7f9a464f01e9 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -2,8 +2,9 @@
  * OMAP4 CM instance functions
  *
  * Copyright (C) 2009 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
  * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -22,6 +23,7 @@
 
 #include "iomap.h"
 #include "common.h"
+#include "clockdomain.h"
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
@@ -343,3 +345,141 @@ void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
         v &= ~OMAP4430_MODULEMODE_MASK;
         omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
 }
+
+/*
+ * Clockdomain low-level functions
+ */
+
+static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
+                                       clkdm1->prcm_partition,
+                                       clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                       OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
+                                         clkdm1->prcm_partition,
+                                         clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                         OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
+                                               clkdm1->cm_inst,
+                                               clkdm1->clkdm_offs +
+                                               OMAP4_CM_STATICDEP,
+                                               (1 << clkdm2->dep_bit));
+}
+
+static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        if (!clkdm->prcm_partition)
+                return 0;
+
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+
+        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
+                                         clkdm->cm_inst, clkdm->clkdm_offs +
+                                         OMAP4_CM_STATICDEP);
+        return 0;
+}
+
+static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                omap4_clkdm_wakeup(clkdm);
+        else
+                omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                                 clkdm->cm_inst,
+                                                 clkdm->clkdm_offs);
+}
+
+static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return omap4_clkdm_wakeup(clkdm);
+
+        return 0;
+}
+
+static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->prcm_partition)
+                return 0;
+
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
+
+        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                omap4_clkdm_sleep(clkdm);
+
+        return 0;
+}
+
+struct clkdm_ops omap4_clkdm_operations = {
+        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_sleep            = omap4_clkdm_sleep,
+        .clkdm_wakeup           = omap4_clkdm_wakeup,
+        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 48daac2581b4..ad856092c06a 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -25,7 +25,6 @@
 #include <linux/spi/ads7846.h>
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "common.h"
 #include "common-board-devices.h"
@@ -96,48 +95,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 {
 }
 #endif
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-                                 int nr_parts)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                pr_info("NAND: Unable to find configuration in GPMC\n");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                nand_data.cs = nandcs;
-                nand_data.parts = parts;
-                nand_data.nr_parts = nr_parts;
-                nand_data.devsize = options;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-                                 int nr_parts)
-{
-}
-#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a42836ab..72bb41b3fd25 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                        struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
 
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 17950c6e130b..34fb5b95859b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -16,14 +16,17 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/platform_data/dsp-omap.h>
 
-#include <plat/clock.h>
+#include <plat/vram.h>
 
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
+#include "clock.h"
 #include "sdrc.h"
 #include "control.h"
+#include "omap-secure.h"
 
 /* Global address base setup code */
 
@@ -200,3 +203,20 @@ void __init omap5_map_io(void)
         omap5_map_common_io();
 }
 #endif
+
+/*
+ * Stub function for OMAP2 so that common files
+ * continue to build when custom builds are used
+ */
+int __weak omap_secure_ram_reserve_memblock(void)
+{
+        return 0;
+}
+
+void __init omap_reserve(void)
+{
+        omap_vram_reserve_sdram_memblock();
+        omap_dsp_reserve_sdram_memblock();
+        omap_secure_ram_reserve_memblock();
+        omap_barrier_reserve_memblock();
+}
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7045e4d61ac3..426fcfcfd821 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -28,13 +28,16 @@
 
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/i2c.h>
 #include <linux/i2c/twl.h>
+#include <linux/i2c-omap.h>
 
 #include <asm/proc-fns.h>
 
-#include <plat/cpu.h>
-#include <plat/serial.h>
-#include <plat/common.h>
+#include "i2c.h"
+#include "serial.h"
+
+#include "usb.h"
 
 #define OMAP_INTC_START         NR_IRQS
 
@@ -338,6 +341,10 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1);
 struct omap2_hsmmc_info;
 extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
+extern void omap_reserve(void);
+
+struct omap_hwmod;
+extern int omap_dss_reset(struct omap_hwmod *);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index d1ff8399a222..06375ad20917 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3 System Control Module register access
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -15,15 +15,13 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <plat/sdrc.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "prm3xxx.h"
+#include "cm3xxx.h"
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index cba60e05e32e..2ad491d6910b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,10 +23,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
+#include <plat-omap/dma-omap.h>
+
 #include "iomap.h"
-#include <plat/dma.h>
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #include "omap4-keypad.h"
 
 #include "soc.h"
@@ -34,6 +35,7 @@
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
+#include "dma.h"
 
 #define L3_MODULES_MAX_LEN 12
 #define L3_MODULES 3
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 1011995f150a..89c57129357a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -25,11 +25,12 @@
 #include <linux/delay.h>
 
 #include <video/omapdss.h>
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/omap-pm.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include "omap-pm.h"
 #include "common.h"
 
+#include "soc.h"
 #include "iomap.h"
 #include "mux.h"
 #include "control.h"
@@ -284,6 +285,35 @@ err:
         return ERR_PTR(r);
 }
 
+static enum omapdss_version __init omap_display_get_version(void)
+{
+        if (cpu_is_omap24xx())
+                return OMAPDSS_VER_OMAP24xx;
+        else if (cpu_is_omap3630())
+                return OMAPDSS_VER_OMAP3630;
+        else if (cpu_is_omap34xx()) {
+                if (soc_is_am35xx()) {
+                        return OMAPDSS_VER_AM35xx;
+                } else {
+                        if (omap_rev() < OMAP3430_REV_ES3_0)
+                                return OMAPDSS_VER_OMAP34xx_ES1;
+                        else
+                                return OMAPDSS_VER_OMAP34xx_ES3;
+                }
+        } else if (omap_rev() == OMAP4430_REV_ES1_0)
+                return OMAPDSS_VER_OMAP4430_ES1;
+        else if (omap_rev() == OMAP4430_REV_ES2_0 ||
+                        omap_rev() == OMAP4430_REV_ES2_1 ||
+                        omap_rev() == OMAP4430_REV_ES2_2)
+                return OMAPDSS_VER_OMAP4430_ES2;
+        else if (cpu_is_omap44xx())
+                return OMAPDSS_VER_OMAP4;
+        else if (soc_is_omap54xx())
+                return OMAPDSS_VER_OMAP5;
+        else
+                return OMAPDSS_VER_UNKNOWN;
+}
+
 int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
         int r = 0;
@@ -291,9 +321,18 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
         int i, oh_count;
         const struct omap_dss_hwmod_data *curr_dss_hwmod;
         struct platform_device *dss_pdev;
+        enum omapdss_version ver;
 
         /* create omapdss device */
 
+        ver = omap_display_get_version();
+
+        if (ver == OMAPDSS_VER_UNKNOWN) {
+                pr_err("DSS not supported on this SoC\n");
+                return -ENODEV;
+        }
+
+        board_data->version = ver;
         board_data->dsi_enable_pads = omap_dsi_enable_pads;
         board_data->dsi_disable_pads = omap_dsi_disable_pads;
         board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index ff75abe60af2..e5aba58da5d2 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -28,9 +28,11 @@
 #include <linux/init.h>
 #include <linux/device.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
+
+#include "soc.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
 
 #define OMAP2_DMA_STRIDE        0x60
 
@@ -274,6 +276,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                 return -ENOMEM;
         }
 
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                d->dev_caps |= HS_CHANNELS_RESERVED;
+
         /* Check the capabilities register for descriptor loading feature */
         if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
                 dma_common_ch_end = CCDN;
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
new file mode 100644
index 000000000000..eba80dbc5218
--- /dev/null
+++ b/arch/arm/mach-omap2/dma.h
@@ -0,0 +1,131 @@
+/*
+ *  OMAP2PLUS DMA channel definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __OMAP2PLUS_DMA_CHANNEL_H
+#define __OMAP2PLUS_DMA_CHANNEL_H
+
+
+/* DMA channels for 24xx */
+#define OMAP24XX_DMA_NO_DEVICE          0
+#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
+#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
+#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
+#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
+#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
+#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
+#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
+#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
+#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
+#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
+#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
+
+#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
+#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
+
+/* Only for AM35xx */
+#define AM35XX_DMA_UART4_TX             54
+#define AM35XX_DMA_UART4_RX             55
+
+#endif /* __OMAP2PLUS_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 814e1808e158..eacf51f2bc27 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,8 +28,6 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 09d0ccccb861..5854da168a9c 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,8 +15,6 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include <plat/clock.h>
-
 #include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 72e0f01b715c..6282cc826613 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -24,8 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <plat/omap_device.h>
-#include <plat/omap_hwmod.h>
+#include "omap_device.h"
+#include "omap_hwmod.h"
 
 #if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE)
 
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 98388109f22a..b155500e84a8 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -27,7 +27,7 @@
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #ifdef CONFIG_BRIDGE_DVFS
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 #endif
 
 #include <linux/platform_data/dsp-omap.h>
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index d1058f16fb40..399acabc3d0b 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,9 +23,9 @@
 #include <linux/of.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/omap-pm.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include "omap-pm.h"
 
 #include "powerdomain.h"
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4acf497faeb3..8607735b3ab3 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -17,9 +17,12 @@
 
 #include <asm/mach/flash.h>
 
-#include <plat/gpmc.h>
-
+#include "gpmc.h"
 #include "soc.h"
+#include "gpmc-nand.h"
+
+/* minimum size for IO mapping */
+#define NAND_IO_SIZE    4
 
 static struct resource gpmc_nand_resource[] = {
         {
@@ -40,41 +43,36 @@ static struct platform_device gpmc_nand_device = {
         .resource       = gpmc_nand_resource,
 };
 
-static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
+static int omap2_nand_gpmc_retime(
+                                struct omap_nand_platform_data *gpmc_nand_data,
+                                struct gpmc_timings *gpmc_t)
 {
         struct gpmc_timings t;
         int err;
 
-        if (!gpmc_nand_data->gpmc_t)
-                return 0;
-
         memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
-        t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
-        t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
+        t.sync_clk = gpmc_t->sync_clk;
+        t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on);
+        t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on);
 
         /* Read */
-        t.adv_rd_off = gpmc_round_ns_to_ticks(
-                                gpmc_nand_data->gpmc_t->adv_rd_off);
+        t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off);
         t.oe_on  = t.adv_on;
-        t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access);
-        t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off);
-        t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off);
-        t.rd_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle);
+        t.access = gpmc_round_ns_to_ticks(gpmc_t->access);
+        t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off);
+        t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off);
+        t.rd_cycle  = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle);
 
         /* Write */
-        t.adv_wr_off = gpmc_round_ns_to_ticks(
-                                gpmc_nand_data->gpmc_t->adv_wr_off);
+        t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off);
         t.we_on  = t.oe_on;
         if (cpu_is_omap34xx()) {
-            t.wr_data_mux_bus = gpmc_round_ns_to_ticks(
-                                gpmc_nand_data->gpmc_t->wr_data_mux_bus);
-            t.wr_access = gpmc_round_ns_to_ticks(
-                                gpmc_nand_data->gpmc_t->wr_access);
+            t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus);
+            t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access);
         }
-        t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off);
-        t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
-        t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
+        t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off);
+        t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off);
+        t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle);
 
         /* Configure GPMC */
         if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
@@ -91,7 +89,29 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
         return 0;
 }
 
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+{
+        /* support only OMAP3 class */
+        if (!cpu_is_omap34xx()) {
+                pr_err("BCH ecc is not supported on this CPU\n");
+                return 0;
+        }
+
+        /*
+         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
+         * Other chips may be added if confirmed to work.
+         */
+        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+                pr_err("BCH 4-bit mode is not supported on this CPU\n");
+                return 0;
+        }
+
+        return 1;
+}
+
+int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
+                          struct gpmc_timings *gpmc_t)
 {
         int err = 0;
         struct device *dev = &gpmc_nand_device.dev;
@@ -112,11 +132,13 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                                 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
         gpmc_nand_resource[2].start =
                                 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
-         /* Set timings in GPMC */
-        err = omap2_nand_gpmc_retime(gpmc_nand_data);
-        if (err < 0) {
-                dev_err(dev, "Unable to set gpmc timings: %d\n", err);
-                return err;
+
+        if (gpmc_t) {
+                err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
+                if (err < 0) {
+                        dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+                        return err;
+                }
         }
 
         /* Enable RD PIN Monitoring Reg */
@@ -126,6 +148,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
+        if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
+                return -EINVAL;
+
         err = platform_device_register(&gpmc_nand_device);
         if (err < 0) {
                 dev_err(dev, "Unable to register NAND device\n");
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
new file mode 100644
index 000000000000..d59e1281e851
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-nand.h
@@ -0,0 +1,27 @@
+/*
+ *  arch/arm/mach-omap2/gpmc-nand.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __OMAP2_GPMC_NAND_H
+#define __OMAP2_GPMC_NAND_H
+
+#include "gpmc.h"
+#include <linux/platform_data/mtd-nand-omap2.h>
+
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
+extern int gpmc_nand_init(struct omap_nand_platform_data *d,
+                          struct gpmc_timings *gpmc_t);
+#else
+static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
+                                 struct gpmc_timings *gpmc_t)
+{
+        return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 916716e1da3b..d102183ed9a5 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -16,15 +16,25 @@
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/err.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/gpmc.h>
-
+#include "gpmc.h"
 #include "soc.h"
+#include "gpmc-onenand.h"
 
 #define ONENAND_IO_SIZE SZ_128K
 
+#define ONENAND_FLAG_SYNCREAD   (1 << 0)
+#define ONENAND_FLAG_SYNCWRITE  (1 << 1)
+#define ONENAND_FLAG_HF         (1 << 2)
+#define ONENAND_FLAG_VHF        (1 << 3)
+
+static unsigned onenand_flags;
+static unsigned latency;
+static int fclk_offset;
+
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 
 static struct resource gpmc_onenand_resource = {
@@ -38,11 +48,9 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 {
         struct gpmc_timings t;
-        u32 reg;
-        int err;
 
         const int t_cer = 15;
         const int t_avdp = 12;
@@ -55,11 +63,6 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
         const int t_wpl = 40;
         const int t_wph = 30;
 
-        /* Ensure sync read and sync write are disabled */
-        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
-        reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
-        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-
         memset(&t, 0, sizeof(t));
         t.sync_clk = 0;
         t.cs_on = 0;
@@ -86,25 +89,30 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
         t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
         t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
 
+        return t;
+}
+
+static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
+{
         /* Configure GPMC for asynchronous read */
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
                           GPMC_CONFIG1_DEVICESIZE_16 |
                           GPMC_CONFIG1_MUXADDDATA);
 
-        err = gpmc_cs_set_timings(cs, &t);
-        if (err)
-                return err;
+        return gpmc_cs_set_timings(cs, t);
+}
+
+static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
+{
+        u32 reg;
 
         /* Ensure sync read and sync write are disabled */
         reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
         reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-
-        return 0;
 }
 
-static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-                                int sync_read, int sync_write, int hf, int vhf)
+static void set_onenand_cfg(void __iomem *onenand_base)
 {
         u32 reg;
 
@@ -112,19 +120,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
         reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
         reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
                 ONENAND_SYS_CFG1_BL_16;
-        if (sync_read)
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
                 reg |= ONENAND_SYS_CFG1_SYNC_READ;
         else
                 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-        if (sync_write)
+        if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
                 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
         else
                 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
-        if (hf)
+        if (onenand_flags & ONENAND_FLAG_HF)
                 reg |= ONENAND_SYS_CFG1_HF;
         else
                 reg &= ~ONENAND_SYS_CFG1_HF;
-        if (vhf)
+        if (onenand_flags & ONENAND_FLAG_VHF)
                 reg |= ONENAND_SYS_CFG1_VHF;
         else
                 reg &= ~ONENAND_SYS_CFG1_VHF;
@@ -132,21 +140,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 }
 
 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
-                                  void __iomem *onenand_base, bool *clk_dep)
+                                  void __iomem *onenand_base)
 {
         u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
-        int freq = 0;
-
-        if (cfg->get_freq) {
-                struct onenand_freq_info fi;
-
-                fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
-                fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
-                fi.ver_id = ver;
-                freq = cfg->get_freq(&fi, clk_dep);
-                if (freq)
-                        return freq;
-        }
+        int freq;
 
         switch ((ver >> 4) & 0xf) {
         case 0:
@@ -172,9 +169,9 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
-                                        void __iomem *onenand_base,
-                                        int *freq_ptr)
+static struct gpmc_timings
+omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
+                                int freq)
 {
         struct gpmc_timings t;
         const int t_cer  = 15;
@@ -184,29 +181,15 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         const int t_wpl  = 40;
         const int t_wph  = 30;
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-        int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
-        int err, ticks_cez;
-        int cs = cfg->cs, freq = *freq_ptr;
         u32 reg;
-        bool clk_dep = false;
+        int div, fclk_offset_ns, gpmc_clk_ns;
+        int ticks_cez;
+        int cs = cfg->cs;
 
-        if (cfg->flags & ONENAND_SYNC_READ) {
-                sync_read = 1;
-        } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
-                sync_read = 1;
-                sync_write = 1;
-        } else
-                return omap2_onenand_set_async_mode(cs, onenand_base);
-
-        if (!freq) {
-                /* Very first call freq is not known */
-                err = omap2_onenand_set_async_mode(cs, onenand_base);
-                if (err)
-                        return err;
-                freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
-                first_time = 1;
-        }
+        if (cfg->flags & ONENAND_SYNC_READ)
+                onenand_flags = ONENAND_FLAG_SYNCREAD;
+        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+                onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
         case 104:
@@ -244,44 +227,31 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_ach   = 9;
                 t_aavdh = 7;
                 t_rdyo  = 15;
-                sync_write = 0;
+                onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
                 break;
         }
 
-        div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
+        div = gpmc_calc_divider(min_gpmc_clk_period);
         gpmc_clk_ns = gpmc_ticks_to_ns(div);
         if (gpmc_clk_ns < 15) /* >66Mhz */
-                hf = 1;
+                onenand_flags |= ONENAND_FLAG_HF;
+        else
+                onenand_flags &= ~ONENAND_FLAG_HF;
         if (gpmc_clk_ns < 12) /* >83Mhz */
-                vhf = 1;
-        if (vhf)
+                onenand_flags |= ONENAND_FLAG_VHF;
+        else
+                onenand_flags &= ~ONENAND_FLAG_VHF;
+        if (onenand_flags & ONENAND_FLAG_VHF)
                 latency = 8;
-        else if (hf)
+        else if (onenand_flags & ONENAND_FLAG_HF)
                 latency = 6;
         else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                 latency = 3;
         else
                 latency = 4;
 
-        if (clk_dep) {
-                if (gpmc_clk_ns < 12) { /* >83Mhz */
-                        t_ces   = 3;
-                        t_avds  = 4;
-                } else if (gpmc_clk_ns < 15) { /* >66Mhz */
-                        t_ces   = 5;
-                        t_avds  = 4;
-                } else if (gpmc_clk_ns < 25) { /* >40Mhz */
-                        t_ces   = 6;
-                        t_avds  = 5;
-                } else {
-                        t_ces   = 7;
-                        t_avds  = 7;
-                }
-        }
-
-        if (first_time)
-                set_onenand_cfg(onenand_base, latency,
-                                        sync_read, sync_write, hf, vhf);
+        /* Set synchronous read timings */
+        memset(&t, 0, sizeof(t));
 
         if (div == 1) {
                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -307,8 +277,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
         }
 
-        /* Set synchronous read timings */
-        memset(&t, 0, sizeof(t));
         t.sync_clk = min_gpmc_clk_period;
         t.cs_on = 0;
         t.adv_on = 0;
@@ -330,7 +298,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                      ticks_cez);
 
         /* Write */
-        if (sync_write) {
+        if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
                 t.adv_wr_off = t.adv_rd_off;
                 t.we_on  = 0;
                 t.we_off = t.cs_rd_off;
@@ -355,6 +323,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 }
         }
 
+        return t;
+}
+
+static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
+{
+        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
+        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
+
         /* Configure GPMC for synchronous read */
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
                           GPMC_CONFIG1_WRAPBURST_SUPP |
@@ -371,11 +347,45 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                           GPMC_CONFIG1_DEVICETYPE_NOR |
                           GPMC_CONFIG1_MUXADDDATA);
 
-        err = gpmc_cs_set_timings(cs, &t);
-        if (err)
-                return err;
+        return gpmc_cs_set_timings(cs, t);
+}
+
+static int omap2_onenand_setup_async(void __iomem *onenand_base)
+{
+        struct gpmc_timings t;
+        int ret;
+
+        omap2_onenand_set_async_mode(onenand_base);
 
-        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+        t = omap2_onenand_calc_async_timings();
+
+        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+
+        omap2_onenand_set_async_mode(onenand_base);
+
+        return 0;
+}
+
+static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
+{
+        int ret, freq = *freq_ptr;
+        struct gpmc_timings t;
+
+        if (!freq) {
+                /* Very first call freq is not known */
+                freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
+                set_onenand_cfg(onenand_base);
+        }
+
+        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+
+        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+
+        set_onenand_cfg(onenand_base);
 
         *freq_ptr = freq;
 
@@ -385,15 +395,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
         struct device *dev = &gpmc_onenand_device.dev;
+        unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
+        int ret;
 
-        /* Set sync timings in GPMC */
-        if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-                        freq_ptr) < 0) {
-                dev_err(dev, "Unable to set synchronous mode\n");
-                return -EINVAL;
+        ret = omap2_onenand_setup_async(onenand_base);
+        if (ret) {
+                dev_err(dev, "unable to set to async mode\n");
+                return ret;
         }
 
-        return 0;
+        if (!(gpmc_onenand_data->flags & l))
+                return 0;
+
+        ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
+        if (ret)
+                dev_err(dev, "unable to set to sync mode\n");
+        return ret;
 }
 
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
@@ -411,6 +428,11 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
 
+        if (cpu_is_omap34xx())
+                gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
+        else
+                gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
+
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
new file mode 100644
index 000000000000..216f23a8b45c
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-onenand.h
@@ -0,0 +1,24 @@
+/*
+ *  arch/arm/mach-omap2/gpmc-onenand.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __OMAP2_GPMC_ONENAND_H
+#define __OMAP2_GPMC_ONENAND_H
+
+#include <linux/platform_data/mtd-onenand-omap2.h>
+
+#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
+extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
+#else
+#define board_onenand_data      NULL
+static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
+{
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 565475310374..6eed907d594c 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smc91x.h"
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 249a0b440cd6..ef990118d32b 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,7 +20,7 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smsc911x.h"
 
 static struct resource gpmc_smsc911x_resources[] = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 92b5718fa722..bf6117c32f4b 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,16 +26,14 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 
-#include <asm/mach-types.h>
-#include <plat/gpmc.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
-#include <plat/cpu.h>
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/omap_device.h>
+#include <asm/mach-types.h>
 
 #include "soc.h"
 #include "common.h"
+#include "omap_device.h"
+#include "gpmc.h"
 
 #define DEVICE_NAME             "omap-gpmc"
 
@@ -59,6 +57,9 @@
 #define GPMC_ECC_SIZE_CONFIG    0x1fc
 #define GPMC_ECC1_RESULT        0x200
 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
 
 /* GPMC ECC control settings */
 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
@@ -75,6 +76,7 @@
 
 #define GPMC_CS0_OFFSET         0x60
 #define GPMC_CS_SIZE            0x30
+#define GPMC_BCH_SIZE           0x10
 
 #define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
@@ -137,7 +139,6 @@ static struct resource	gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
-static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -158,22 +159,6 @@ static u32 gpmc_read_reg(int idx)
         return __raw_readl(gpmc_base + idx);
 }
 
-static void gpmc_cs_write_byte(int cs, int idx, u8 val)
-{
-        void __iomem *reg_addr;
-
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        __raw_writeb(val, reg_addr);
-}
-
-static u8 gpmc_cs_read_byte(int cs, int idx)
-{
-        void __iomem *reg_addr;
-
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        return __raw_readb(reg_addr);
-}
-
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
         void __iomem *reg_addr;
@@ -288,7 +273,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
                 return -1
 #endif
 
-int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+int gpmc_calc_divider(unsigned int sync_clk)
 {
         int div;
         u32 l;
@@ -308,7 +293,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         int div;
         u32 l;
 
-        div = gpmc_cs_calc_divider(cs, t->sync_clk);
+        div = gpmc_calc_divider(t->sync_clk);
         if (div < 0)
                 return div;
 
@@ -509,44 +494,6 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_read_status - read access request to get the different gpmc status
- * @cmd: command type
- * @return status
- */
-int gpmc_read_status(int cmd)
-{
-        int     status = -EINVAL;
-        u32     regval = 0;
-
-        switch (cmd) {
-        case GPMC_GET_IRQ_STATUS:
-                status = gpmc_read_reg(GPMC_IRQSTATUS);
-                break;
-
-        case GPMC_PREFETCH_FIFO_CNT:
-                regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-                status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
-                break;
-
-        case GPMC_PREFETCH_COUNT:
-                regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-                status = GPMC_PREFETCH_STATUS_COUNT(regval);
-                break;
-
-        case GPMC_STATUS_BUFFER:
-                regval = gpmc_read_reg(GPMC_STATUS);
-                /* 1 : buffer is available to write */
-                status = regval & GPMC_STATUS_BUFF_EMPTY;
-                break;
-
-        default:
-                printk(KERN_ERR "gpmc_read_status: Not supported\n");
-        }
-        return status;
-}
-EXPORT_SYMBOL(gpmc_read_status);
-
-/**
  * gpmc_cs_configure - write request to configure gpmc
  * @cs: chip select number
  * @cmd: command type
@@ -614,121 +561,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 }
 EXPORT_SYMBOL(gpmc_cs_configure);
 
-/**
- * gpmc_nand_read - nand specific read access request
- * @cs: chip select number
- * @cmd: command type
- */
-int gpmc_nand_read(int cs, int cmd)
-{
-        int rval = -EINVAL;
-
-        switch (cmd) {
-        case GPMC_NAND_DATA:
-                rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
-                break;
-
-        default:
-                printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
-        }
-        return rval;
-}
-EXPORT_SYMBOL(gpmc_nand_read);
-
-/**
- * gpmc_nand_write - nand specific write request
- * @cs: chip select number
- * @cmd: command type
- * @wval: value to write
- */
-int gpmc_nand_write(int cs, int cmd, int wval)
-{
-        int err = 0;
-
-        switch (cmd) {
-        case GPMC_NAND_COMMAND:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
-                break;
-
-        case GPMC_NAND_ADDRESS:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
-                break;
-
-        case GPMC_NAND_DATA:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
-
-        default:
-                printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
-                err = -EINVAL;
-        }
-        return err;
-}
-EXPORT_SYMBOL(gpmc_nand_write);
-
-
-
-/**
- * gpmc_prefetch_enable - configures and starts prefetch transfer
- * @cs: cs (chip select) number
- * @fifo_th: fifo threshold to be used for read/ write
- * @dma_mode: dma mode enable (1) or disable (0)
- * @u32_count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- */
-int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-                                unsigned int u32_count, int is_write)
-{
-
-        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
-                pr_err("gpmc: fifo threshold is not supported\n");
-                return -1;
-        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
-                /* Set the amount of bytes to be prefetched */
-                gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
-
-                /* Set dma/mpu mode, the prefetch read / post write and
-                 * enable the engine. Set which cs is has requested for.
-                 */
-                gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
-                                        ENABLE_PREFETCH |
-                                        (dma_mode << DMA_MPU_MODE) |
-                                        (0x1 & is_write)));
-
-                /*  Start the prefetch engine */
-                gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
-        } else {
-                return -EBUSY;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(gpmc_prefetch_enable);
-
-/**
- * gpmc_prefetch_reset - disables and stops the prefetch engine
- */
-int gpmc_prefetch_reset(int cs)
-{
-        u32 config1;
-
-        /* check if the same module/cs is trying to reset */
-        config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
-        if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
-                return -EINVAL;
-
-        /* Stop the PFPW engine */
-        gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
-
-        /* Reset/disable the PFPW engine */
-        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
-
-        return 0;
-}
-EXPORT_SYMBOL(gpmc_prefetch_reset);
-
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
+        int i;
+
         reg->gpmc_status = gpmc_base + GPMC_STATUS;
         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
@@ -744,7 +580,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
-        reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+
+        for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
+                reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
+                                           GPMC_BCH_SIZE * i;
+        }
 }
 
 int gpmc_get_client_irq(unsigned irq_config)
@@ -1093,267 +939,3 @@ void omap3_gpmc_restore_context(void)
         }
 }
 #endif /* CONFIG_ARCH_OMAP3 */
-
-/**
- * gpmc_enable_hwecc - enable hardware ecc functionality
- * @cs: chip select number
- * @mode: read/write mode
- * @dev_width: device bus width(1 for x16, 0 for x8)
- * @ecc_size: bytes for which ECC will be generated
- */
-int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
-{
-        unsigned int val;
-
-        /* check if ecc module is in used */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-
-        gpmc_ecc_used = cs;
-
-        /* clear ecc and enable bits */
-        gpmc_write_reg(GPMC_ECC_CONTROL,
-                        GPMC_ECC_CTRL_ECCCLEAR |
-                        GPMC_ECC_CTRL_ECCREG1);
-
-        /* program ecc and result sizes */
-        val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
-        gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
-
-        switch (mode) {
-        case GPMC_ECC_READ:
-        case GPMC_ECC_WRITE:
-                gpmc_write_reg(GPMC_ECC_CONTROL,
-                                GPMC_ECC_CTRL_ECCCLEAR |
-                                GPMC_ECC_CTRL_ECCREG1);
-                break;
-        case GPMC_ECC_READSYN:
-                gpmc_write_reg(GPMC_ECC_CONTROL,
-                                GPMC_ECC_CTRL_ECCCLEAR |
-                                GPMC_ECC_CTRL_ECCDISABLE);
-                break;
-        default:
-                printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
-                break;
-        }
-
-        /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
-        val = (dev_width << 7) | (cs << 1) | (0x1);
-        gpmc_write_reg(GPMC_ECC_CONFIG, val);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
-
-/**
- * gpmc_calculate_ecc - generate non-inverted ecc bytes
- * @cs: chip select number
- * @dat: data pointer over which ecc is computed
- * @ecc_code: ecc code buffer
- *
- * Using non-inverted ECC is considered ugly since writing a blank
- * page (padding) will clear the ECC bytes. This is not a problem as long
- * no one is trying to write data on the seemingly unused page. Reading
- * an erased page will produce an ECC mismatch between generated and read
- * ECC bytes that has to be dealt with separately.
- */
-int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
-{
-        unsigned int val = 0x0;
-
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-
-        /* read ecc result */
-        val = gpmc_read_reg(GPMC_ECC1_RESULT);
-        *ecc_code++ = val;          /* P128e, ..., P1e */
-        *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
-        /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
-        *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
-
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
-
-#ifdef CONFIG_ARCH_OMAP3
-
-/**
- * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
- * @cs: chip select number
- * @nsectors: how many 512-byte sectors to process
- * @nerrors: how many errors to correct per sector (4 or 8)
- *
- * This function must be executed before any call to gpmc_enable_hwecc_bch.
- */
-int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
-{
-        /* check if ecc module is in use */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-
-        /* support only OMAP3 class */
-        if (!cpu_is_omap34xx()) {
-                printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
-                return -EINVAL;
-        }
-
-        /*
-         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
-         * Other chips may be added if confirmed to work.
-         */
-        if ((nerrors == 4) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
-                printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
-                return -EINVAL;
-        }
-
-        /* sanity check */
-        if (nsectors > 8) {
-                printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
-                       nsectors);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
-
-/**
- * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
- * @cs: chip select number
- * @mode: read/write mode
- * @dev_width: device bus width(1 for x16, 0 for x8)
- * @nsectors: how many 512-byte sectors to process
- * @nerrors: how many errors to correct per sector (4 or 8)
- */
-int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
-                          int nerrors)
-{
-        unsigned int val;
-
-        /* check if ecc module is in use */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-
-        gpmc_ecc_used = cs;
-
-        /* clear ecc and enable bits */
-        gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
-
-        /*
-         * When using BCH, sector size is hardcoded to 512 bytes.
-         * Here we are using wrapping mode 6 both for reading and writing, with:
-         *  size0 = 0  (no additional protected byte in spare area)
-         *  size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
-         */
-        gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
-
-        /* BCH configuration */
-        val = ((1                        << 16) | /* enable BCH */
-               (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
-               (0x06                     <<  8) | /* wrap mode = 6 */
-               (dev_width                <<  7) | /* bus width */
-               (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
-               (cs                       <<  1) | /* ECC CS */
-               (0x1));                            /* enable ECC */
-
-        gpmc_write_reg(GPMC_ECC_CONFIG, val);
-        gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
-
-/**
- * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
- * @cs:  chip select number
- * @dat: The pointer to data on which ecc is computed
- * @ecc: The ecc output buffer
- */
-int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
-{
-        int i;
-        unsigned long nsectors, reg, val1, val2;
-
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-
-        nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
-
-        for (i = 0; i < nsectors; i++) {
-
-                reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
-
-                /* Read hw-computed remainder */
-                val1 = gpmc_read_reg(reg + 0);
-                val2 = gpmc_read_reg(reg + 4);
-
-                /*
-                 * Add constant polynomial to remainder, in order to get an ecc
-                 * sequence of 0xFFs for a buffer filled with 0xFFs; and
-                 * left-justify the resulting polynomial.
-                 */
-                *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
-                *ecc++ = 0x13 ^ ((val2 >>  4) & 0xFF);
-                *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
-                *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
-                *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
-                *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
-                *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
-        }
-
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
-
-/**
- * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
- * @cs:  chip select number
- * @dat: The pointer to data on which ecc is computed
- * @ecc: The ecc output buffer
- */
-int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
-{
-        int i;
-        unsigned long nsectors, reg, val1, val2, val3, val4;
-
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-
-        nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
-
-        for (i = 0; i < nsectors; i++) {
-
-                reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
-
-                /* Read hw-computed remainder */
-                val1 = gpmc_read_reg(reg + 0);
-                val2 = gpmc_read_reg(reg + 4);
-                val3 = gpmc_read_reg(reg + 8);
-                val4 = gpmc_read_reg(reg + 12);
-
-                /*
-                 * Add constant polynomial to remainder, in order to get an ecc
-                 * sequence of 0xFFs for a buffer filled with 0xFFs.
-                 */
-                *ecc++ = 0xef ^ (val4 & 0xFF);
-                *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
-                *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
-                *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
-                *ecc++ = 0xed ^ (val3 & 0xFF);
-                *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
-                *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
-                *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
-                *ecc++ = 0x97 ^ (val2 & 0xFF);
-                *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
-                *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
-                *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
-                *ecc++ = 0xb5 ^ (val1 & 0xFF);
-        }
-
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
-
-#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 2e6e2597178c..79f4dfc2adb3 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -11,6 +11,8 @@
 #ifndef __OMAP2_GPMC_H
 #define __OMAP2_GPMC_H
 
+#include <linux/platform_data/mtd-nand-omap2.h>
+
 /* Maximum Number of Chip Selects */
 #define GPMC_CS_NUM             8
 
@@ -32,15 +34,6 @@
 #define GPMC_SET_IRQ_STATUS     0x00000004
 #define GPMC_CONFIG_WP          0x00000005
 
-#define GPMC_GET_IRQ_STATUS     0x00000006
-#define GPMC_PREFETCH_FIFO_CNT  0x00000007 /* bytes available in FIFO for r/w */
-#define GPMC_PREFETCH_COUNT     0x00000008 /* remaining bytes to be read/write*/
-#define GPMC_STATUS_BUFFER      0x00000009 /* 1: buffer is available to write */
-
-#define GPMC_NAND_COMMAND       0x0000000a
-#define GPMC_NAND_ADDRESS       0x0000000b
-#define GPMC_NAND_DATA          0x0000000c
-
 #define GPMC_ENABLE_IRQ         0x0000000d
 
 /* ECC commands */
@@ -76,25 +69,10 @@
 #define GPMC_DEVICETYPE_NOR             0
 #define GPMC_DEVICETYPE_NAND            2
 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
-#define GPMC_STATUS_BUFF_EMPTY          0x00000001
 #define WR_RD_PIN_MONITORING            0x00600000
-#define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
-#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
-#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
-#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
-
-enum omap_ecc {
-                /* 1-bit ecc: stored at end of spare area */
-        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
-        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
-                /* 1-bit ecc: stored at beginning of spare area as romcode */
-        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
-        OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
-        OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
-};
 
 /*
  * Note that all values in this struct are in nanoseconds except sync_clk
@@ -133,22 +111,6 @@ struct gpmc_timings {
         u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
 };
 
-struct gpmc_nand_regs {
-        void __iomem    *gpmc_status;
-        void __iomem    *gpmc_nand_command;
-        void __iomem    *gpmc_nand_address;
-        void __iomem    *gpmc_nand_data;
-        void __iomem    *gpmc_prefetch_config1;
-        void __iomem    *gpmc_prefetch_config2;
-        void __iomem    *gpmc_prefetch_control;
-        void __iomem    *gpmc_prefetch_status;
-        void __iomem    *gpmc_ecc_config;
-        void __iomem    *gpmc_ecc_control;
-        void __iomem    *gpmc_ecc_size_config;
-        void __iomem    *gpmc_ecc1_result;
-        void __iomem    *gpmc_bch_result0;
-};
-
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
@@ -160,31 +122,14 @@ extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 extern u32 gpmc_cs_read_reg(int cs, int idx);
-extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
+extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-                                        unsigned int u32_count, int is_write);
-extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
-extern int gpmc_nand_read(int cs, int cmd);
-extern int gpmc_nand_write(int cs, int cmd, int wval);
-
-int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
-int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
-
-#ifdef CONFIG_ARCH_OMAP3
-int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
-int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
-                          int nerrors);
-int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
-int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
-#endif /* CONFIG_ARCH_OMAP3 */
 
 #endif
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index e003f2bba30c..3da8900598c8 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -27,8 +27,8 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #include "hdq1w.h"
 
 #include "common.h"
diff --git a/arch/arm/mach-omap2/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h
index 0c1efc846d8d..c7e08d2a7a46 100644
--- a/arch/arm/mach-omap2/hdq1w.h
+++ b/arch/arm/mach-omap2/hdq1w.h
@@ -21,7 +21,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
 #define ARCH_ARM_MACH_OMAP2_HDQ1W_H
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 /*
  * XXX A future cleanup patch should modify
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 4d3a6324155f..4a964338992a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,14 +14,14 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <plat/mmc.h>
-#include <plat/omap-pm.h>
-#include <plat/omap_device.h>
+#include "soc.h"
+#include "omap_device.h"
+#include "omap-pm.h"
 
 #include "mux.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 8763c8520dc2..1df9b5feda16 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -21,8 +21,8 @@
 #include <linux/err.h>
 #include <linux/hwspinlock.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 
 static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
         .base_id = 0,
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index fc57e67b321f..4e63097e3cd8 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,11 +19,13 @@
  *
  */
 
-#include <plat/i2c.h>
+#include "soc.h"
 #include "common.h"
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 
 #include "mux.h"
+#include "i2c.h"
 
 /* In register I2C_CON, Bit 15 is the I2C enable bit */
 #define I2C_EN                                  BIT(15)
@@ -33,7 +35,9 @@
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT       10000
 
-void __init omap2_i2c_mux_pins(int bus_id)
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
+
+static void __init omap2_i2c_mux_pins(int bus_id)
 {
         char mux_name[sizeof("i2c2_scl.i2c2_scl")];
 
@@ -104,3 +108,62 @@ int omap_i2c_reset(struct omap_hwmod *oh)
 
         return 0;
 }
+
+static int __init omap_i2c_nr_ports(void)
+{
+        int ports = 0;
+
+        if (cpu_is_omap24xx())
+                ports = 2;
+        else if (cpu_is_omap34xx())
+                ports = 3;
+        else if (cpu_is_omap44xx())
+                ports = 4;
+        return ports;
+}
+
+static const char name[] = "omap_i2c";
+
+int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
+                                int bus_id)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+        struct omap_i2c_bus_platform_data *pdata;
+        struct omap_i2c_dev_attr *dev_attr;
+
+        if (bus_id > omap_i2c_nr_ports())
+                return -EINVAL;
+
+        omap2_i2c_mux_pins(bus_id);
+
+        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+                "String buffer overflow in I2C%d device setup\n", bus_id);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                        pr_err("Could not look up %s\n", oh_name);
+                        return -EEXIST;
+        }
+
+        pdata = i2c_pdata;
+        /*
+         * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
+         * use, and functionality implementation flags, up to the OMAP I2C
+         * driver via platform data
+         */
+        pdata->rev = oh->class->rev;
+
+        dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
+        pdata->flags = dev_attr->flags;
+
+        pdev = omap_device_build(name, bus_id, oh, pdata,
+                        sizeof(struct omap_i2c_bus_platform_data),
+                        NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
+
+        return PTR_RET(pdev);
+}
+
diff --git a/arch/arm/mach-omap2/i2c.h b/arch/arm/mach-omap2/i2c.h
new file mode 100644
index 000000000000..42b6f2e7d190
--- /dev/null
+++ b/arch/arm/mach-omap2/i2c.h
@@ -0,0 +1,42 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <plat/i2c.h>
+
+#ifndef __MACH_OMAP2_I2C_H
+#define __MACH_OMAP2_I2C_H
+
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+        u8      fifo_depth;
+        u32     flags;
+};
+
+int omap_i2c_reset(struct omap_hwmod *oh);
+
+#endif  /* __MACH_OMAP2_I2C_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 93d10de7129f..cfaed13d0040 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 
 #include <linux/serial_reg.h>
 
-#include <plat/serial.h>
+#include <mach/serial.h>
 
 #define UART_OFFSET(addr)       ((addr) & 0x00ffffff)
 
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
deleted file mode 100644
index 5621cc59c9f4..000000000000
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/gpio.h
- */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
index 65fce44dce34..70eda00db7a4 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/serial.h
- *
  * Copyright (C) 2009 Texas Instruments
  * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
@@ -10,11 +8,6 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <linux/init.h>
-
 /*
  * Memory entry used for the DEBUG_LL UART configuration, relative to
  * start of RAM. See also uncompress.h and debug-macro.S.
@@ -29,11 +22,6 @@
  */
 #define OMAP_UART_INFO_OFS      0x3ffc
 
-/* OMAP1 serial ports */
-#define OMAP1_UART1_BASE        0xfffb0000
-#define OMAP1_UART2_BASE        0xfffb0800
-#define OMAP1_UART3_BASE        0xfffb9800
-
 /* OMAP2 serial ports */
 #define OMAP2_UART1_BASE        0x4806a000
 #define OMAP2_UART2_BASE        0x4806c000
@@ -76,20 +64,14 @@
 #define ZOOM_UART_VIRT          0xfa400000
 
 #define OMAP_PORT_SHIFT         2
-#define OMAP7XX_PORT_SHIFT      0
 #define ZOOM_PORT_SHIFT         1
 
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
 #define OMAP24XX_BASE_BAUD      (48000000/16)
 
 /*
  * DEBUG_LL port encoding stored into the UART1 scratchpad register by
  * decomp_setup in uncompress.h
  */
-#define OMAP1UART1              11
-#define OMAP1UART2              12
-#define OMAP1UART3              13
 #define OMAP2UART1              21
 #define OMAP2UART2              22
 #define OMAP2UART3              23
@@ -109,15 +91,6 @@
 #define OMAP5UART4              OMAP4UART4
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
-/* This is only used by 8250.c for omap1510 */
-#define is_omap_port(pt)        ({int __ret = 0;                        \
-                        if ((pt)->port.mapbase == OMAP1_UART1_BASE ||   \
-                            (pt)->port.mapbase == OMAP1_UART2_BASE ||   \
-                            (pt)->port.mapbase == OMAP1_UART3_BASE)     \
-                                __ret = 1;                              \
-                        __ret;                                          \
-                        })
-
 #ifndef __ASSEMBLER__
 
 struct omap_board_data;
@@ -128,5 +101,3 @@ extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
 extern void omap_serial_init_port(struct omap_board_data *bdata,
                 struct omap_uart_port_info *platform_data);
 #endif
-
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
index 78e0557bfd4e..8e3546d3e041 100644
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -1,5 +1,176 @@
 /*
- * arch/arm/mach-omap2/include/mach/uncompress.h
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
  */
 
-#include <plat/uncompress.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+
+#include <mach/serial.h>
+
+#define MDR1_MODE_MASK                  0x07
+
+volatile u8 *uart_base;
+int uart_shift;
+
+/*
+ * Store the DEBUG_LL uart number into memory.
+ * See also debug-macro.S, and serial.c for related code.
+ */
+static void set_omap_uart_info(unsigned char port)
+{
+        /*
+         * Get address of some.bss variable and round it down
+         * a la CONFIG_AUTO_ZRELADDR.
+         */
+        u32 ram_start = (u32)&uart_shift & 0xf8000000;
+        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
+        *uart_info = port;
+}
+
+static void putc(int c)
+{
+        if (!uart_base)
+                return;
+
+        /* Check for UART 16x mode */
+        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+                return;
+
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+                barrier();
+        uart_base[UART_TX << uart_shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
+        if (machine_is_##mach()) {                                      \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_omap_uart_info(port);                               \
+                break;                                                  \
+        }
+
+#define DEBUG_LL_OMAP2(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP2UART##p)
+
+#define DEBUG_LL_OMAP3(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP3UART##p)
+
+#define DEBUG_LL_OMAP4(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP4UART##p)
+
+#define DEBUG_LL_OMAP5(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP5UART##p)
+/* Zoom2/3 shift is different for UART1 and external port */
+#define DEBUG_LL_ZOOM(mach)                                             \
+        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+
+#define DEBUG_LL_TI81XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI81XXUART##p)
+
+#define DEBUG_LL_AM33XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                AM33XXUART##p)
+
+static inline void arch_decomp_setup(void)
+{
+        int port = 0;
+
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap2 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap_2430sdp);
+                DEBUG_LL_OMAP2(1, omap_apollon);
+                DEBUG_LL_OMAP2(1, omap_h4);
+
+                /* omap2 based boards using UART3 */
+                DEBUG_LL_OMAP2(3, nokia_n800);
+                DEBUG_LL_OMAP2(3, nokia_n810);
+                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
+
+                /* omap3 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap3evm);
+                DEBUG_LL_OMAP3(1, omap_3430sdp);
+                DEBUG_LL_OMAP3(1, omap_3630sdp);
+                DEBUG_LL_OMAP3(1, omap3530_lv_som);
+                DEBUG_LL_OMAP3(1, omap3_torpedo);
+
+                /* omap3 based boards using UART3 */
+                DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, cm_t3517);
+                DEBUG_LL_OMAP3(3, cm_t3730);
+                DEBUG_LL_OMAP3(3, craneboard);
+                DEBUG_LL_OMAP3(3, devkit8000);
+                DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, igep0030);
+                DEBUG_LL_OMAP3(3, nokia_rm680);
+                DEBUG_LL_OMAP3(3, nokia_rm696);
+                DEBUG_LL_OMAP3(3, nokia_rx51);
+                DEBUG_LL_OMAP3(3, omap3517evm);
+                DEBUG_LL_OMAP3(3, omap3_beagle);
+                DEBUG_LL_OMAP3(3, omap3_pandora);
+                DEBUG_LL_OMAP3(3, omap_ldp);
+                DEBUG_LL_OMAP3(3, overo);
+                DEBUG_LL_OMAP3(3, touchbook);
+
+                /* omap4 based boards using UART3 */
+                DEBUG_LL_OMAP4(3, omap_4430sdp);
+                DEBUG_LL_OMAP4(3, omap4_panda);
+
+                /* omap5 based boards using UART3 */
+                DEBUG_LL_OMAP5(3, omap5_sevm);
+
+                /* zoom2/3 external uart */
+                DEBUG_LL_ZOOM(omap_zoom2);
+                DEBUG_LL_ZOOM(omap_zoom3);
+
+                /* TI8168 base boards using UART3 */
+                DEBUG_LL_TI81XX(3, ti8168evm);
+
+                /* TI8148 base boards using UART1 */
+                DEBUG_LL_TI81XX(1, ti8148evm);
+
+                /* AM33XX base boards using UART1 */
+                DEBUG_LL_AM33XX(1, am335xevm);
+        } while (0);
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4234d28dc171..807b8d919f81 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -25,14 +25,9 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-#include <plat/serial.h>
-#include <plat/omap-pm.h>
-#include <plat/omap_hwmod.h>
-#include <plat/multi.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 
+#include "omap_hwmod.h"
 #include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
@@ -43,6 +38,10 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "omap-pm.h"
+#include "sdrc.h"
+#include "serial.h"
+#include "sram.h"
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -354,11 +353,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
 
-static void __init omap_common_init_early(void)
-{
-        omap_init_consistent_dma_size();
-}
-
 static void __init omap_hwmod_init_postsetup(void)
 {
         u8 postsetup_state;
@@ -379,7 +373,6 @@ void __init omap2420_init_early(void)
 {
         omap2_set_globals_242x();
         omap2xxx_check_revision();
-        omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap242x_powerdomains_init();
         omap242x_clockdomains_init();
@@ -401,7 +394,6 @@ void __init omap2430_init_early(void)
 {
         omap2_set_globals_243x();
         omap2xxx_check_revision();
-        omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap243x_powerdomains_init();
         omap243x_clockdomains_init();
@@ -428,7 +420,6 @@ void __init omap3_init_early(void)
         omap2_set_globals_3xxx();
         omap3xxx_check_revision();
         omap3xxx_check_features();
-        omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
         omap3xxx_clockdomains_init();
@@ -462,7 +453,6 @@ void __init ti81xx_init_early(void)
         omap2_set_globals_ti81xx();
         omap3xxx_check_revision();
         ti81xx_check_features();
-        omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
         omap3xxx_clockdomains_init();
@@ -520,7 +510,6 @@ void __init am33xx_init_early(void)
         omap2_set_globals_am33xx();
         omap3xxx_check_revision();
         ti81xx_check_features();
-        omap_common_init_early();
         am33xx_voltagedomains_init();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
@@ -536,7 +525,6 @@ void __init omap4430_init_early(void)
         omap2_set_globals_443x();
         omap4xxx_check_revision();
         omap4xxx_check_features();
-        omap_common_init_early();
         omap44xx_voltagedomains_init();
         omap44xx_powerdomains_init();
         omap44xx_clockdomains_init();
@@ -558,7 +546,6 @@ void __init omap5_init_early(void)
 {
         omap2_set_globals_5xxx();
         omap5xxx_check_revision();
-        omap_common_init_early();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 37f8f948047b..a106c75c5338 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -19,11 +19,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
-
-#include <plat/dma.h>
-#include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
+#include <plat-omap/dma-omap.h>
+
+#include "omap_device.h"
+
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
new file mode 100644
index 000000000000..0cd4b089da9c
--- /dev/null
+++ b/arch/arm/mach-omap2/mmc.h
@@ -0,0 +1,23 @@
+#include <linux/mmc/host.h>
+#include <linux/platform_data/mmc-omap.h>
+
+#define OMAP24XX_NR_MMC         2
+#define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
+#define OMAP2_MMC1_BASE         0x4809c000
+
+#define OMAP4_MMC_REG_OFFSET    0x100
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
+#else
+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+{
+}
+#endif
+
+struct omap_hwmod;
+int omap_msdi_reset(struct omap_hwmod *oh);
+
+/* called from board-specific card detection service routine */
+extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+                                        int is_closed);
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 9e57b4aadb06..627e97e30743 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -25,13 +25,12 @@
 #include <linux/err.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/mmc.h>
-
 #include "common.h"
 #include "control.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #include "mux.h"
+#include "mmc.h"
 
 /*
  * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 701e17cba468..26126343d6ac 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -36,8 +36,9 @@
 #include <linux/interrupt.h>
 
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
+#include "soc.h"
 #include "control.h"
 #include "mux.h"
 #include "prm.h"
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ff4e6a0e9c7c..3f5fd7e3549d 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -50,6 +50,7 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "soc.h"
 #include "common.h"
 #include "omap44xx.h"
 #include "omap4-sar-layout.h"
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/mach-omap2/omap-pm-noop.c
index 9722f418ae1f..6a3be2bebddb 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/mach-omap2/omap-pm-noop.c
@@ -22,9 +22,8 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 
-/* Interface documentation is in mach/omap-pm.h */
-#include <plat/omap-pm.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
+#include "omap-pm.h"
 
 static bool off_mode_enabled;
 static int dummy_context_loss_counter;
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h
index 67faa7b8fe92..67faa7b8fe92 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/mach-omap2/omap-pm.h
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index e089e4d1ae38..b970440cffca 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/memblock.h>
 
-#include <plat/omap-secure.h>
 #include "omap-secure.h"
 
 static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index c90a43589abe..0e729170c46b 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -52,6 +52,13 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
                                 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
 extern phys_addr_t omap_secure_ram_mempool_base(void);
+extern int omap_secure_ram_reserve_memblock(void);
 
+#ifdef CONFIG_OMAP4_ERRATA_I688
+extern int omap_barrier_reserve_memblock(void);
+#else
+static inline void omap_barrier_reserve_memblock(void)
+{ }
+#endif
 #endif /* __ASSEMBLER__ */
 #endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index e1f289748c5d..3cfcd41bf8fa 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,16 +25,14 @@
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
 
-#include <plat/sram.h>
-#include <plat/omap-secure.h>
-#include <plat/mmc.h>
-
 #include "omap-wakeupgen.h"
-
 #include "soc.h"
 #include "common.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
+#include "omap-secure.h"
+#include "sram.h"
 
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 7a7d1f2a65e9..0ef934fec364 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -89,9 +89,8 @@
 #include <linux/of.h>
 #include <linux/notifier.h>
 
-#include <plat/omap_device.h>
-#include <plat/omap_hwmod.h>
-#include <plat/clock.h>
+#include "omap_device.h"
+#include "omap_hwmod.h"
 
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 106f50665804..0933c599bf89 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -34,7 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 extern struct dev_pm_domain omap_device_pm_domain;
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1d258b..37eeb45612f8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,18 +139,19 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
 
-#include <plat/clock.h>
-#include <plat/omap_hwmod.h>
+#include "clock.h"
+#include "omap_hwmod.h"
 #include <plat/prcm.h>
 
 #include "soc.h"
 #include "common.h"
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
+#include "cm3xxx.h"
 #include "cminst44xx.h"
 #include "cm33xx.h"
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
 #include "prm44xx.h"
 #include "prm33xx.h"
 #include "prminst44xx.h"
@@ -2668,7 +2669,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
 /* Static functions intended only for use in soc_ops field function pointers */
 
 /**
- * _omap2_wait_target_ready - wait for a module to leave slave idle
+ * _omap2xxx_wait_target_ready - wait for a module to leave slave idle
  * @oh: struct omap_hwmod *
  *
  * Wait for a module @oh to leave slave idle.  Returns 0 if the module
@@ -2676,7 +2677,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
  * slave idle; otherwise, pass along the return value of the
  * appropriate *_cm*_wait_module_ready() function.
  */
-static int _omap2_wait_target_ready(struct omap_hwmod *oh)
+static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
 {
         if (!oh)
                 return -EINVAL;
@@ -2689,9 +2690,36 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
 
         /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
 
-        return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-                                          oh->prcm.omap2.idlest_reg_id,
-                                          oh->prcm.omap2.idlest_idle_bit);
+        return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                             oh->prcm.omap2.idlest_reg_id,
+                                             oh->prcm.omap2.idlest_idle_bit);
+}
+
+/**
+ * _omap3xxx_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
+
+        return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                             oh->prcm.omap2.idlest_reg_id,
+                                             oh->prcm.omap2.idlest_idle_bit);
 }
 
 /**
@@ -3959,8 +3987,13 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
  */
 void __init omap_hwmod_init(void)
 {
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                soc_ops.wait_target_ready = _omap2_wait_target_ready;
+        if (cpu_is_omap24xx()) {
+                soc_ops.wait_target_ready = _omap2xxx_wait_target_ready;
+                soc_ops.assert_hardreset = _omap2_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+        } else if (cpu_is_omap34xx()) {
+                soc_ops.wait_target_ready = _omap3xxx_wait_target_ready;
                 soc_ops.assert_hardreset = _omap2_assert_hardreset;
                 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index b3349f7b1a2c..87b59b45c678 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -35,7 +35,6 @@
 #include <linux/list.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
-#include <plat/cpu.h>
 
 struct omap_device;
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5db6007c523..a8b3368dca3d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,21 +12,24 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+
+#include <linux/i2c-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/dma.h>
-#include <plat/serial.h>
-#include <plat/i2c.h>
+#include <plat-omap/dma-omap.h>
 #include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
 #include "l3_2xxx.h"
 #include "l4_2xxx.h"
-#include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "serial.h"
 #include "wd_timer.h"
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c455e41b0237..dc768c50e523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,21 +12,23 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+
+#include <linux/i2c-omap.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/dma.h>
-#include <plat/serial.h>
-#include <plat/i2c.h>
+#include <plat-omap/dma-omap.h>
 #include <plat/dmtimer.h>
-#include <plat/mmc.h>
+
+#include "omap_hwmod.h"
+#include "mmc.h"
 #include "l3_2xxx.h"
 
 #include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
+#include "i2c.h"
 #include "wd_timer.h"
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index cbb4ef6544ad..0413daba2dba 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -13,8 +13,7 @@
  */
 #include <asm/sizes.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
+#include "omap_hwmod.h"
 
 #include "omap_hwmod_common_data.h"
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 8851bbb6bb24..40d6c93d9853 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -9,13 +9,14 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
-#include <plat/dma.h>
-#include <plat/common.h>
+
+#include <plat-omap/dma-omap.h>
+
+#include "omap_hwmod.h"
 #include "hdq1w.h"
 
 #include "omap_hwmod_common_data.h"
+#include "dma.h"
 
 /* UART */
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 1a1287d62648..47901a5e76de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -13,10 +13,10 @@
  */
 #include <asm/sizes.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
+#include "omap_hwmod.h"
 #include "l3_2xxx.h"
 #include "l4_2xxx.h"
+#include "serial.h"
 
 #include "omap_hwmod_common_data.h"
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index bd9220ed5ab9..a0116d08cf45 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -8,13 +8,13 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
+
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 #include <plat/dmtimer.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1cd316d..ad8d43b33273 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -14,13 +14,11 @@
  * GNU General Public License for more details.
  */
 
-#include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
+#include <linux/i2c-omap.h>
+
+#include "omap_hwmod.h"
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dma.h>
-#include <plat/mmc.h>
-#include <plat/i2c.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -28,6 +26,8 @@
 #include "cm33xx.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
+#include "i2c.h"
+#include "mmc.h"
 
 /*
  * IP blocks
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee07dd4..abe66ced903f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -14,16 +14,14 @@
  *
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+
+#include <linux/i2c-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/dma.h>
-#include <plat/serial.h>
+#include <plat-omap/dma-omap.h>
 #include "l3_3xxx.h"
 #include "l4_3xxx.h"
-#include <plat/i2c.h>
-#include <plat/mmc.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
@@ -32,10 +30,16 @@
 #include "am35xx.h"
 
 #include "soc.h"
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
+
+#include "dma.h"
+#include "i2c.h"
+#include "mmc.h"
 #include "wd_timer.h"
+#include "serial.h"
 
 /*
  * OMAP3xxx hardware module integration data
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 652d0285bd6d..7a6132848f5d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,22 +21,23 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
+#include <linux/i2c-omap.h>
+
+#include <plat-omap/dma-omap.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/i2c.h>
-#include <plat/dma.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/mmc.h>
 #include <plat/dmtimer.h>
-#include <plat/common.h>
 #include <plat/iommu.h>
 
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "i2c.h"
+#include "mmc.h"
 #include "wd_timer.h"
 
 /* Base offset for all OMAP4 interrupts external to MPUSS */
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 9f1ccdc8cc8c..79d623b83e49 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -16,7 +16,7 @@
  * data and their integration with other OMAP modules and Linux.
  */
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 #include "omap_hwmod_common_data.h"
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 2bc8f1705d4a..cfcce299177c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -13,7 +13,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 #include "common.h"
 #include "display.h"
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index c784c12f98a1..7e437bf6024c 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -19,7 +19,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 #include "voltage.h"
 
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d992db8ff0b0..4d76a3ca5bf3 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -27,11 +27,11 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/usb.h>
-
-#include <plat/usb.h>
+#include <linux/usb/musb.h>
 
 #include "soc.h"
 #include "control.h"
+#include "usb.h"
 
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index f515a1a056d5..2bf35dc091be 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/i2c/twl.h>
 
+#include "soc.h"
 #include "voltage.h"
 
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 58e16aef40bb..bd41d59a7cab 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -20,7 +20,7 @@
 #include <linux/opp.h>
 #include <linux/cpu.h>
 
-#include <plat/omap_device.h>
+#include "omap_device.h"
 
 #include "omap_opp_data.h"
 
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 75cef5f67a8a..62772e0e0d69 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,6 +19,7 @@
  */
 #include <linux/module.h>
 
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 46092cd806fa..3cf4fdfd7ab0 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -27,12 +27,13 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
-#include <plat/clock.h>
+#include "clock.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/dmtimer.h>
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 
+#include "soc.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index ea61c32957bd..331478f9b864 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -20,10 +20,11 @@
 
 #include <asm/system_misc.h>
 
-#include <plat/omap-pm.h>
-#include <plat/omap_device.h>
+#include "omap-pm.h"
+#include "omap_device.h"
 #include "common.h"
 
+#include "soc.h"
 #include "prcm-common.h"
 #include "voltage.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8af6cd6ac331..13e1f4303989 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -31,21 +31,24 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
+#include <asm/fncpy.h>
+
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 #include <asm/system_misc.h>
 
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 
+#include "soc.h"
 #include "common.h"
-#include "prm2xxx_3xxx.h"
+#include "clock.h"
+#include "prm2xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "pm.h"
 #include "control.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a904de4313e..a8b43da0b6f4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -32,25 +32,25 @@
 
 #include <trace/events/power.h>
 
+#include <asm/fncpy.h>
 #include <asm/suspend.h>
 #include <asm/system_misc.h>
 
-#include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/sdrc.h>
 #include <plat/prcm.h>
-#include <plat/gpmc.h>
-#include <plat/dma.h>
+#include <plat-omap/dma-omap.h>
 
+#include "soc.h"
 #include "common.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "gpmc.h"
 #include "prm-regbits-34xx.h"
-
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
 #include "pm.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "control.h"
 
 /* pm34xx errata defined in pm.h */
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 04922d149068..7da75aed1514 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -18,6 +18,7 @@
 #include <linux/slab.h>
 #include <asm/system_misc.h>
 
+#include "soc.h"
 #include "common.h"
 #include "clockdomain.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 2a791766283d..3cf79b54ce61 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -15,8 +15,9 @@
 
 #include <asm/pmu.h>
 
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
+#include "soc.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
 
 static char *omap2_pmu_oh_names[] = {"mpu"};
 static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index baee90608d11..5277d56eb37f 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -22,8 +22,6 @@
 
 #include <linux/atomic.h>
 
-#include <plat/cpu.h>
-
 #include "voltage.h"
 
 /* Powerdomain basic power states */
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
deleted file mode 100644
index 3950ccfe5f4a..000000000000
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * OMAP2 and OMAP3 powerdomain control
- *
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/bug.h>
-
-#include <plat/prcm.h>
-
-#include "powerdomain.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "prm-regbits-34xx.h"
-
-
-/* Common functions across OMAP2 and OMAP3 */
-static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
-                                (pwrst << OMAP_POWERSTATE_SHIFT),
-                                pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-
-static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL,
-                                             OMAP_POWERSTATE_MASK);
-}
-
-static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTST,
-                                             OMAP_POWERSTATEST_MASK);
-}
-
-static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                                                                u8 pwrst)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
-
-        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                                   OMAP2_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                                                u8 pwrst)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-
-        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                                   OMAP2_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
-
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
-                                             m);
-}
-
-static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL, m);
-}
-
-static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 v;
-
-        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
-        omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
-                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-
-        /* XXX Is this udelay() value meaningful? */
-        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
-                OMAP_INTRANSITION_MASK) &&
-                (c++ < PWRDM_TRANSITION_BAILOUT))
-                        udelay(1);
-
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-
-        return 0;
-}
-
-/* Applicable only for OMAP3. Not supported on OMAP2 */
-static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP3430_PM_PREPWSTST,
-                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
-}
-
-static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTST,
-                                             OMAP3430_LOGICSTATEST_MASK);
-}
-
-static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL,
-                                             OMAP3430_LOGICSTATEST_MASK);
-}
-
-static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP3430_PM_PREPWSTST,
-                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
-}
-
-static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
-{
-        switch (bank) {
-        case 0:
-                return OMAP3430_LASTMEM1STATEENTERED_MASK;
-        case 1:
-                return OMAP3430_LASTMEM2STATEENTERED_MASK;
-        case 2:
-                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
-        case 3:
-                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
-        return 0;
-}
-
-static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-
-        m = omap3_get_mem_bank_lastmemst_mask(bank);
-
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                OMAP3430_PM_PREPWSTST, m);
-}
-
-static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
-        return 0;
-}
-
-static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
-{
-        return omap2_prm_rmw_mod_reg_bits(0,
-                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-}
-
-static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
-{
-        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                                          0, pwrdm->prcm_offs,
-                                          OMAP2_PM_PWSTCTRL);
-}
-
-struct pwrdm_ops omap2_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
-        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
-        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
-        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
-        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
-};
-
-struct pwrdm_ops omap3_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
-        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
-        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
-        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
-        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
-        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
-        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
-        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
-        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
-        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
deleted file mode 100644
index 67c5663899b6..000000000000
--- a/arch/arm/mach-omap2/powerdomain33xx.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * AM33XX Powerdomain control
- *
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
- * <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-
-#include <plat/prcm.h>
-
-#include "powerdomain.h"
-#include "prm33xx.h"
-#include "prm-regbits-33xx.h"
-
-
-static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
-                                (pwrst << OMAP_POWERSTATE_SHIFT),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-
-static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
-        v &= OMAP_POWERSTATE_MASK;
-        v >>= OMAP_POWERSTATE_SHIFT;
-
-        return v;
-}
-
-static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= OMAP_POWERSTATEST_MASK;
-        v >>= OMAP_POWERSTATEST_SHIFT;
-
-        return v;
-}
-
-static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
-        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
-
-        return v;
-}
-
-static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
-        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
-                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-
-static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
-                                AM33XX_LASTPOWERSTATEENTERED_MASK,
-                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        return 0;
-}
-
-static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 m;
-
-        m = pwrdm->logicretstate_mask;
-        if (!m)
-                return -EINVAL;
-
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-
-        return 0;
-}
-
-static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= AM33XX_LOGICSTATEST_MASK;
-        v >>= AM33XX_LOGICSTATEST_SHIFT;
-
-        return v;
-}
-
-static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        u32 v, m;
-
-        m = pwrdm->logicretstate_mask;
-        if (!m)
-                return -EINVAL;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        v &= m;
-        v >>= __ffs(m);
-
-        return v;
-}
-
-static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                u8 pwrst)
-{
-        u32 m;
-
-        m = pwrdm->mem_on_mask[bank];
-        if (!m)
-                return -EINVAL;
-
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-
-        return 0;
-}
-
-static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                        u8 pwrst)
-{
-        u32 m;
-
-        m = pwrdm->mem_ret_mask[bank];
-        if (!m)
-                return -EINVAL;
-
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-
-        return 0;
-}
-
-static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-
-        m = pwrdm->mem_pwrst_mask[bank];
-        if (!m)
-                return -EINVAL;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= m;
-        v >>= __ffs(m);
-
-        return v;
-}
-
-static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-
-        m = pwrdm->mem_retst_mask[bank];
-        if (!m)
-                return -EINVAL;
-
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        v &= m;
-        v >>= __ffs(m);
-
-        return v;
-}
-
-static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-
-        /* XXX Is this udelay() value meaningful? */
-        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
-                        & OMAP_INTRANSITION_MASK) &&
-                        (c++ < PWRDM_TRANSITION_BAILOUT))
-                udelay(1);
-
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-
-        return 0;
-}
-
-struct pwrdm_ops am33xx_pwrdm_operations = {
-        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
-        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
-        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
-        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
-        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
-        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
-        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
deleted file mode 100644
index aceb4f464c9b..000000000000
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * OMAP4 powerdomain control
- *
- * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/bug.h>
-
-#include "powerdomain.h"
-#include <plat/prcm.h>
-#include "prm2xxx_3xxx.h"
-#include "prm44xx.h"
-#include "prminst44xx.h"
-#include "prm-regbits-44xx.h"
-
-static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
-                                        (pwrst << OMAP_POWERSTATE_SHIFT),
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-
-static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= OMAP_POWERSTATE_MASK;
-        v >>= OMAP_POWERSTATE_SHIFT;
-
-        return v;
-}
-
-static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP_POWERSTATEST_MASK;
-        v >>= OMAP_POWERSTATEST_SHIFT;
-
-        return v;
-}
-
-static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
-        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
-
-        return v;
-}
-
-static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
-                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-
-static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
-                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
-        return 0;
-}
-
-static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 v;
-
-        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                                    u8 pwrst)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
-
-        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                     u8 pwrst)
-{
-        u32 m;
-
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-
-        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-
-        return 0;
-}
-
-static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP4430_LOGICSTATEST_MASK;
-        v >>= OMAP4430_LOGICSTATEST_SHIFT;
-
-        return v;
-}
-
-static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        u32 v;
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= OMAP4430_LOGICRETSTATE_MASK;
-        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
-
-        return v;
-}
-
-/**
- * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
- * @pwrdm: struct powerdomain * to read the state for
- *
- * Reads the previous logic powerstate for a powerdomain. This
- * function must determine the previous logic powerstate by first
- * checking the previous powerstate for the domain. If that was OFF,
- * then logic has been lost. If previous state was RETENTION, the
- * function reads the setting for the next retention logic state to
- * see the actual value.  In every other case, the logic is
- * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
- * depending whether the logic was retained or not.
- */
-static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
-{
-        int state;
-
-        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
-
-        if (state == PWRDM_POWER_OFF)
-                return PWRDM_POWER_OFF;
-
-        if (state != PWRDM_POWER_RET)
-                return PWRDM_POWER_RET;
-
-        return omap4_pwrdm_read_logic_retst(pwrdm);
-}
-
-static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-
-        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= m;
-        v >>= __ffs(m);
-
-        return v;
-}
-
-static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= m;
-        v >>= __ffs(m);
-
-        return v;
-}
-
-/**
- * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
- * @pwrdm: struct powerdomain * to read mem powerstate for
- * @bank: memory bank index
- *
- * Reads the previous memory powerstate for a powerdomain. This
- * function must determine the previous memory powerstate by first
- * checking the previous powerstate for the domain. If that was OFF,
- * then logic has been lost. If previous state was RETENTION, the
- * function reads the setting for the next memory retention state to
- * see the actual value.  In every other case, the logic is
- * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
- * depending whether logic was retained or not.
- */
-static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        int state;
-
-        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
-
-        if (state == PWRDM_POWER_OFF)
-                return PWRDM_POWER_OFF;
-
-        if (state != PWRDM_POWER_RET)
-                return PWRDM_POWER_RET;
-
-        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
-}
-
-static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-
-        /* XXX Is this udelay() value meaningful? */
-        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
-                                            pwrdm->prcm_offs,
-                                            OMAP4_PM_PWSTST) &
-                OMAP_INTRANSITION_MASK) &&
-               (c++ < PWRDM_TRANSITION_BAILOUT))
-                udelay(1);
-
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-
-        return 0;
-}
-
-struct pwrdm_ops omap4_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
-        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
-        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
-        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
-        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
-        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
-        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
-        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
-        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 2385c1f009ee..ba520d4f7c7b 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 0f51e034e0aa..cff270a178c5 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -28,6 +28,7 @@
 #include "common.h"
 #include <plat/prcm.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 6ac966103f34..638da6dd41c3 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
 
 /* Bits shared between registers */
 
@@ -209,9 +209,13 @@
 
 /* RM_RSTST_WKUP specific bits */
 /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST_SHIFT                      6
 #define OMAP24XX_EXTWMPU_RST_MASK                       (1 << 6)
+#define OMAP24XX_SECU_WD_RST_SHIFT                      5
 #define OMAP24XX_SECU_WD_RST_MASK                       (1 << 5)
+#define OMAP24XX_MPU_WD_RST_SHIFT                       4
 #define OMAP24XX_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST_SHIFT                    3
 #define OMAP24XX_SECU_VIOL_RST_MASK                     (1 << 3)
 
 /* PM_WKEN_WKUP specific bits */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 64c087af6a8b..838b594d4e13 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -14,7 +14,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
 
 
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
 
 /* Shared register bits */
 
@@ -509,15 +509,25 @@
 #define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
 
 /* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST_SHIFT                   10
 #define OMAP3430_ICECRUSHER_RST_MASK                    (1 << 10)
+#define OMAP3430_ICEPICK_RST_SHIFT                      9
 #define OMAP3430_ICEPICK_RST_MASK                       (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT         8
 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK          (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT         7
 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK          (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST_SHIFT                6
 #define OMAP3430_EXTERNAL_WARM_RST_MASK                 (1 << 6)
+#define OMAP3430_SECURE_WD_RST_SHIFT                    5
 #define OMAP3430_SECURE_WD_RST_MASK                     (1 << 5)
+#define OMAP3430_MPU_WD_RST_SHIFT                       4
 #define OMAP3430_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST_SHIFT                3
 #define OMAP3430_SECURITY_VIOL_RST_MASK                 (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST_SHIFT                    1
 #define OMAP3430_GLOBAL_SW_RST_MASK                     (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST_SHIFT                  0
 #define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
 
 /* PRM_VOLTCTRL */
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 39d562169d18..c30ab5de8d1d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -52,5 +52,58 @@
 #define OMAP_POWERSTATE_SHIFT                           0
 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 
+/*
+ * Standardized OMAP reset source bits
+ *
+ * To the extent these happen to match the hardware register bit
+ * shifts, it's purely coincidental.  Used by omap-wdt.c.
+ * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
+ * there are any bits remaining in the global PRM_RSTST register that
+ * haven't been identified, or when the PRM code for the current SoC
+ * doesn't know how to interpret the register.
+ */
+#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT                       0
+#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT                       1
+#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT                         2
+#define OMAP_MPU_WD_RST_SRC_ID_SHIFT                            3
+#define OMAP_SECU_WD_RST_SRC_ID_SHIFT                           4
+#define OMAP_EXTWARM_RST_SRC_ID_SHIFT                           5
+#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT                        6
+#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT                        7
+#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT                       8
+#define OMAP_ICEPICK_RST_SRC_ID_SHIFT                           9
+#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT                        10
+#define OMAP_C2C_RST_SRC_ID_SHIFT                               11
+#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT                           12
+
+#ifndef __ASSEMBLER__
+
+/**
+ * struct prm_reset_src_map - map register bitshifts to standard bitshifts
+ * @reg_shift: bitshift in the PRM reset source register
+ * @std_shift: bitshift equivalent in the standard reset source list
+ *
+ * The fields are signed because -1 is used as a terminator.
+ */
+struct prm_reset_src_map {
+        s8 reg_shift;
+        s8 std_shift;
+};
+
+/**
+ * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
+ * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl
+ */
+struct prm_ll_data {
+        u32 (*read_reset_sources)(void);
+};
+
+extern int prm_register(struct prm_ll_data *pld);
+extern int prm_unregister(struct prm_ll_data *pld);
+
+extern u32 prm_read_reset_sources(void);
+
+#endif
+
 
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
new file mode 100644
index 000000000000..e2860f9c111d
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -0,0 +1,126 @@
+/*
+ * OMAP2xxx PRM module functions
+ *
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include "common.h"
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "vp.h"
+#include "powerdomain.h"
+#include "clockdomain.h"
+#include "prm2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm-regbits-24xx.h"
+
+/*
+ * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
+ *   hardware register (which are specific to the OMAP2xxx SoCs) to
+ *   reset source ID bit shifts (which is an OMAP SoC-independent
+ *   enumeration)
+ */
+static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
+        { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
+        { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
+
+/**
+ * omap2xxx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap2xxx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
+
+        p = omap2xxx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+
+        return r;
+}
+
+int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                   clkdm->pwrdm.ptr->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                     clkdm->pwrdm.ptr->prcm_offs,
+                                     OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+struct pwrdm_ops omap2_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+
+/*
+ *
+ */
+
+static struct prm_ll_data omap2xxx_prm_ll_data = {
+        .read_reset_sources = &omap2xxx_prm_read_reset_sources,
+};
+
+static int __init omap2xxx_prm_init(void)
+{
+        if (!cpu_is_omap24xx())
+                return 0;
+
+        return prm_register(&omap2xxx_prm_ll_data);
+}
+subsys_initcall(omap2xxx_prm_init);
+
+static void __exit omap2xxx_prm_exit(void)
+{
+        if (!cpu_is_omap24xx())
+                return;
+
+        /* Should never happen */
+        WARN(prm_unregister(&omap2xxx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
new file mode 100644
index 000000000000..1d97112524f1
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -0,0 +1,132 @@
+/*
+ * OMAP2xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+
+/*
+ * OMAP2-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ *
+ */
+
+#define OMAP2_PRCM_REVISION_OFFSET      0x0000
+#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
+#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
+#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
+#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
+#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
+#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
+#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
+#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
+#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
+#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+
+/*
+ * Module specific PRM register offsets from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ */
+
+/* Register offsets appearing on both OMAP2 and OMAP3 */
+
+#define OMAP2_RM_RSTCTRL                                0x0050
+#define OMAP2_RM_RSTTIME                                0x0054
+#define OMAP2_RM_RSTST                                  0x0058
+#define OMAP2_PM_PWSTCTRL                               0x00e0
+#define OMAP2_PM_PWSTST                                 0x00e4
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+
+/* OMAP2xxx specific register offsets */
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+#ifndef __ASSEMBLER__
+/* Function prototypes */
+extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
+extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
+
+extern int __init prm2xxx_init(void);
+extern int __exit prm2xxx_exit(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9529984d8d2b..30517f5af707 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,82 +15,12 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <linux/irq.h>
 
-#include <plat/prcm.h>
-
-#include "soc.h"
 #include "common.h"
-#include "vp.h"
-
+#include "powerdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "prm-regbits-34xx.h"
-
-static const struct omap_prcm_irq omap3_prcm_irqs[] = {
-        OMAP_PRCM_IRQ("wkup",   0,      0),
-        OMAP_PRCM_IRQ("io",     9,      1),
-};
-
-static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
-        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
-        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
-        .nr_regs                = 1,
-        .irqs                   = omap3_prcm_irqs,
-        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
-        .irq                    = 11 + OMAP_INTC_START,
-        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
-        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
-        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
-        .restore_irqen          = &omap3xxx_prm_restore_irqen,
-};
-
-u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
-{
-        return __raw_readl(prm_base + module + idx);
-}
-
-void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __raw_writel(val, prm_base + module + idx);
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = omap2_prm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        omap2_prm_write_mod_reg(v, module, idx);
-
-        return v;
-}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        u32 v;
-
-        v = omap2_prm_read_mod_reg(domain, idx);
-        v &= mask;
-        v >>= __ffs(mask);
-
-        return v;
-}
-
-u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
+#include "clockdomain.h"
 
 /**
  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
@@ -104,9 +34,6 @@ u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  */
 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 {
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
-
         return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
                                        (1 << shift));
 }
@@ -127,9 +54,6 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 {
         u32 mask;
 
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
-
         mask = 1 << shift;
         omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
 
@@ -156,9 +80,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
         u32 rst, st;
         int c;
 
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
-
         rst = 1 << rst_shift;
         st = 1 << st_shift;
 
@@ -178,188 +99,155 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
 
-/* PRM VP */
-
-/*
- * struct omap3_vp - OMAP3 VP register access description.
- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
- */
-struct omap3_vp {
-        u32 tranxdone_status;
-};
-
-static struct omap3_vp omap3_vp[] = {
-        [OMAP3_VP_VDD_MPU_ID] = {
-                .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
-        },
-        [OMAP3_VP_VDD_CORE_ID] = {
-                .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
-        },
-};
-
-#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
-
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
-{
-        struct omap3_vp *vp = &omap3_vp[vp_id];
-        u32 irqstatus;
 
-        irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
-                                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        return irqstatus & vp->tranxdone_status;
-}
+/* Powerdomain low-level functions */
 
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+/* Common functions across OMAP2 and OMAP3 */
+int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 {
-        struct omap3_vp *vp = &omap3_vp[vp_id];
-
-        omap2_prm_write_mod_reg(vp->tranxdone_status,
-                                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+                                   (pwrst << OMAP_POWERSTATE_SHIFT),
+                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+        return 0;
 }
 
-u32 omap3_prm_vcvp_read(u8 offset)
+int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 {
-        return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP_POWERSTATE_MASK);
 }
 
-void omap3_prm_vcvp_write(u32 val, u8 offset)
+int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 {
-        omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP_POWERSTATEST_MASK);
 }
 
-u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
 {
-        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
 }
 
-/**
- * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
- * @events: ptr to a u32, preallocated by caller
- *
- * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
- * MPU IRQs, and store the result into the u32 pointed to by @events.
- * No return value.
- */
-void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
 {
-        u32 mask, st;
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 
-        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
-        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
 
-        events[0] = mask & st;
+        return 0;
 }
 
-/**
- * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
- *
- * Force any buffered writes to the PRM IP block to complete.  Needed
- * by the PRM IRQ handler, which reads and writes directly to the IP
- * block, to avoid race conditions after acknowledging or clearing IRQ
- * bits.  No return value.
- */
-void omap3xxx_prm_ocp_barrier(void)
+int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
-        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
+                                             m);
 }
 
-/**
- * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
- * @saved_mask: ptr to a u32 array to save IRQENABLE bits
- *
- * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
- * must be allocated by the caller.  Intended to be used in the PRM
- * interrupt handler suspend callback.  The OCP barrier is needed to
- * ensure the write to disable PRM interrupts reaches the PRM before
- * returning; otherwise, spurious interrupts might occur.  No return
- * value.
- */
-void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 {
-        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
-                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 
-        /* OCP barrier */
-        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL, m);
 }
 
-/**
- * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
- * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
- *
- * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
- * to be used in the PRM interrupt handler resume callback to restore
- * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
- * barrier should be needed here; any pending PRM interrupts will fire
- * once the writes reach the PRM.  No return value.
- */
-void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 {
-        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
-                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        u32 v;
+
+        v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
+        omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
 }
 
-/**
- * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
- *
- * Clear any previously-latched I/O wakeup events and ensure that the
- * I/O wakeup gates are aligned with the current mux settings.  Works
- * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
- * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
- * return value.
- */
-void omap3xxx_prm_reconfigure_io_chain(void)
+int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
-        int i = 0;
+        u32 c = 0;
 
-        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                   PM_WKEN);
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
 
-        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
-                          OMAP3430_ST_IO_CHAIN_MASK,
-                          MAX_IOPAD_LATCH_TIME, i);
-        if (i == MAX_IOPAD_LATCH_TIME)
-                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+                (c++ < PWRDM_TRANSITION_BAILOUT))
+                        udelay(1);
 
-        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                     PM_WKEN);
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
 
-        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
-                                   PM_WKST);
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
 
-        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+        return 0;
 }
 
-/**
- * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
- *
- * Activates the I/O wakeup event latches and allows events logged by
- * those latches to signal a wakeup event to the PRCM.  For I/O
- * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
- * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
- * No return value.
- */
-static void __init omap3xxx_prm_enable_io_wakeup(void)
+int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+                          struct clockdomain *clkdm2)
+{
+        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                   clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+
+int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
+                          struct clockdomain *clkdm2)
+{
+        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+
+int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+                           struct clockdomain *clkdm2)
 {
-        if (omap3_has_io_wakeup())
-                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-                                           PM_WKEN);
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                             PM_WKDEP, (1 << clkdm2->dep_bit));
 }
 
-static int __init omap3xxx_prcm_init(void)
+int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 {
-        int ret = 0;
-
-        if (cpu_is_omap34xx()) {
-                omap3xxx_prm_enable_io_wakeup();
-                ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
-                if (!ret)
-                        irq_set_status_flags(omap_prcm_event_to_irq("io"),
-                                             IRQ_NOAUTOEN);
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
         }
 
-        return ret;
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                     PM_WKDEP);
+        return 0;
 }
-subsys_initcall(omap3xxx_prcm_init);
+
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index c19d249b4816..3330b1bf789d 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
 /*
- * OMAP2/3 Power/Reset Management (PRM) register definitions
+ * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
  *
- * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  * Paul Walmsley
  *
@@ -19,160 +19,6 @@
 #include "prcm-common.h"
 #include "prm.h"
 
-#define OMAP2420_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-#define OMAP34XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
-
-
-/*
- * OMAP2-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- *
- */
-
-#define OMAP2_PRCM_REVISION_OFFSET      0x0000
-#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
-#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
-#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
-#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
-#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
-#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
-#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-
-/*
- * OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- */
-
-#define OMAP3_PRM_REVISION_OFFSET       0x0004
-#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
-#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
-
-#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
-
-
-#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
-#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
-#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
-#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
-#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
-#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
-#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
-#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
-#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
-#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
-#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
-#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
-#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
-#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
-#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
-#define OMAP3_PRM_RSTST_OFFSET  0x0058
-#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
-#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
-#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
-#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
-#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
-#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
-#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
-#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
-#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
-#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
-#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
-#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
-#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
-#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
-#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
-#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
-#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
-#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
-#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
-#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
-#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
-#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
-#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
-#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
-#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
-#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
-#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
-#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
-#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
-#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
-#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
-
-#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
-#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
-#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
 /*
  * Module specific PRM register offsets from PRM_BASE + domain offset
  *
@@ -200,66 +46,83 @@
 #define PM_EVGENONTIM                                   0x00d8
 #define PM_EVGENOFFTIM                                  0x00dc
 
-/* OMAP2xxx specific register offsets */
-#define OMAP24XX_PM_WKEN2                               0x00a4
-#define OMAP24XX_PM_WKST2                               0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
-
-/* OMAP3 specific register offsets */
-#define OMAP3430ES2_PM_WKEN3                            0x00f0
-#define OMAP3430ES2_PM_WKST3                            0x00b8
-
-#define OMAP3430_PM_MPUGRPSEL                           0x00a4
-#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
-#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
 
-#define OMAP3430_PM_IVAGRPSEL                           0x00a8
-#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
-#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
-
-#define OMAP3430_PM_PREPWSTST                           0x00e8
-
-#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
-#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+#ifndef __ASSEMBLER__
 
+#include <linux/io.h>
+#include "powerdomain.h"
 
-#ifndef __ASSEMBLER__
 /* Power/reset management domain register get/set */
-extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
-extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
-extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
-extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(prm_base + module + idx);
+}
+
+static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, prm_base + module + idx);
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
+                                             s16 idx)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_prm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
 
 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
 
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP3 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap3_prm_vcvp_read(u8 offset);
-extern void omap3_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-extern void omap3xxx_prm_reconfigure_io_chain(void);
-
-/* PRM interrupt-related functions */
-extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
-extern void omap3xxx_prm_ocp_barrier(void);
-extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
+extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst);
+extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst);
+extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
+
+extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+                                 struct clockdomain *clkdm2);
+extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
+                                 struct clockdomain *clkdm2);
+extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+                                  struct clockdomain *clkdm2);
+extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
 
 #endif /* __ASSEMBLER */
 
@@ -348,7 +211,9 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
  *
  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
  */
+#define OMAP_GLOBALWARM_RST_SHIFT                       1
 #define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
+#define OMAP_GLOBALCOLD_RST_SHIFT                       0
 #define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
 
 /*
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index e7dbb6cf1255..1ac73883f891 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,9 +19,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/common.h>
-
 #include "common.h"
+#include "powerdomain.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
 
@@ -133,3 +132,204 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
 
         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LOGICSTATEST_MASK;
+        v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v, m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_on_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                        u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_ret_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_pwrst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_retst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+                        & OMAP_INTRANSITION_MASK) &&
+                        (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
+        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
+        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
new file mode 100644
index 000000000000..1fea656b2ca8
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -0,0 +1,403 @@
+/*
+ * OMAP3xxx PRM module functions
+ *
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include "common.h"
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "vp.h"
+#include "powerdomain.h"
+#include "prm3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm-regbits-34xx.h"
+
+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+
+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 1,
+        .irqs                   = omap3_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
+        .irq                    = 11 + OMAP_INTC_START,
+        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+};
+
+/*
+ * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
+ *   register (which are specific to OMAP3xxx SoCs) to reset source ID
+ *   bit shifts (which is an OMAP SoC-independent enumeration)
+ */
+static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
+        { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
+          OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
+        { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
+          OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
+        { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
+        { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
+
+/* PRM VP */
+
+/*
+ * struct omap3_vp - OMAP3 VP register access description.
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+struct omap3_vp {
+        u32 tranxdone_status;
+};
+
+static struct omap3_vp omap3_vp[] = {
+        [OMAP3_VP_VDD_MPU_ID] = {
+                .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+        },
+        [OMAP3_VP_VDD_CORE_ID] = {
+                .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+        },
+};
+
+#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
+
+u32 omap3_prm_vp_check_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+        u32 irqstatus;
+
+        irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+                                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        return irqstatus & vp->tranxdone_status;
+}
+
+void omap3_prm_vp_clear_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+
+        omap2_prm_write_mod_reg(vp->tranxdone_status,
+                                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+}
+
+u32 omap3_prm_vcvp_read(u8 offset)
+{
+        return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+}
+
+void omap3_prm_vcvp_write(u32 val, u8 offset)
+{
+        omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+}
+
+u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+{
+        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+}
+
+/**
+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to a u32, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the u32 pointed to by @events.
+ * No return value.
+ */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+{
+        u32 mask, st;
+
+        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
+        events[0] = mask & st;
+}
+
+/**
+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap3xxx_prm_ocp_barrier(void)
+{
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+
+/**
+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ * must be allocated by the caller.  Intended to be used in the PRM
+ * interrupt handler suspend callback.  The OCP barrier is needed to
+ * ensure the write to disable PRM interrupts reaches the PRM before
+ * returning; otherwise, spurious interrupts might occur.  No return
+ * value.
+ */
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+
+/**
+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ * to be used in the PRM interrupt handler resume callback to restore
+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ * barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+}
+
+/**
+ * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
+ * return value.
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKEN);
+
+        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+                          OMAP3430_ST_IO_CHAIN_MASK,
+                          MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                     PM_WKEN);
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKST);
+
+        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+
+/**
+ * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O
+ * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+ * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+ * No return value.
+ */
+static void __init omap3xxx_prm_enable_io_wakeup(void)
+{
+        if (omap3_has_io_wakeup())
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                           PM_WKEN);
+}
+
+/**
+ * omap3xxx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap3xxx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
+
+        p = omap3xxx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+
+        return r;
+}
+
+/* Powerdomain low-level functions */
+
+/* Applicable only for OMAP3. Not supported on OMAP2 */
+static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
+}
+
+static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
+}
+
+static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP3430_LASTMEM1STATEENTERED_MASK;
+        case 1:
+                return OMAP3430_LASTMEM2STATEENTERED_MASK;
+        case 2:
+                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
+        case 3:
+                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap3_get_mem_bank_lastmemst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                OMAP3430_PM_PREPWSTST, m);
+}
+
+static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        return 0;
+}
+
+static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(0,
+                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+}
+
+static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          0, pwrdm->prcm_offs,
+                                          OMAP2_PM_PWSTCTRL);
+}
+
+struct pwrdm_ops omap3_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
+        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
+        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+
+/*
+ *
+ */
+
+static struct prm_ll_data omap3xxx_prm_ll_data = {
+        .read_reset_sources = &omap3xxx_prm_read_reset_sources,
+};
+
+static int __init omap3xxx_prm_init(void)
+{
+        int ret;
+
+        if (!cpu_is_omap34xx())
+                return 0;
+
+        ret = prm_register(&omap3xxx_prm_ll_data);
+        if (ret)
+                return ret;
+
+        omap3xxx_prm_enable_io_wakeup();
+        ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+        if (!ret)
+                irq_set_status_flags(omap_prcm_event_to_irq("io"),
+                                     IRQ_NOAUTOEN);
+
+
+        return ret;
+}
+subsys_initcall(omap3xxx_prm_init);
+
+static void __exit omap3xxx_prm_exit(void)
+{
+        if (!cpu_is_omap34xx())
+                return;
+
+        /* Should never happen */
+        WARN(prm_unregister(&omap3xxx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
new file mode 100644
index 000000000000..a3c28a875410
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -0,0 +1,160 @@
+/*
+ * OMAP3xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP3-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ */
+
+#define OMAP3_PRM_REVISION_OFFSET       0x0004
+#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
+#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
+#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
+#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
+#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET  0x0058
+#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
+#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
+#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
+#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
+#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
+#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
+#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
+#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
+#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
+#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
+#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/* OMAP3 specific register offsets */
+#define OMAP3430ES2_PM_WKEN3                            0x00f0
+#define OMAP3430ES2_PM_WKST3                            0x00b8
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+#ifndef __ASSEMBLER__
+
+/* OMAP3-specific VP functions */
+u32 omap3_prm_vp_check_txdone(u8 vp_id);
+void omap3_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP3 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap3_prm_vcvp_read(u8 offset);
+extern void omap3_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+extern void omap3xxx_prm_reconfigure_io_chain(void);
+
+/* PRM interrupt-related functions */
+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+extern void omap3xxx_prm_ocp_barrier(void);
+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+
+extern u32 omap3xxx_prm_get_reset_sources(void);
+
+#endif /* __ASSEMBLER */
+
+
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f0c4d5f4a174..a799e9552fbf 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -1,10 +1,11 @@
 /*
  * OMAP4 PRM module functions
  *
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
  * Copyright (C) 2010 Nokia Corporation
  * Benoît Cousson
  * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -27,6 +28,9 @@
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prminst44xx.h"
+#include "powerdomain.h"
+
+/* Static data */
 
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
         OMAP_PRCM_IRQ("wkup",   0,      0),
@@ -46,6 +50,33 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
         .restore_irqen          = &omap44xx_prm_restore_irqen,
 };
 
+/*
+ * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
+ *   hardware register (which are specific to OMAP44xx SoCs) to reset
+ *   source ID bit shifts (which is an OMAP SoC-independent
+ *   enumeration)
+ */
+static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
+        { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
+          OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
+          OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
+          OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
+        { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
+        { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
+
 /* PRM low-level functions */
 
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -291,12 +322,324 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 }
 
-static int __init omap4xxx_prcm_init(void)
+/**
+ * omap44xx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap44xx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
+                                    OMAP4_RM_RSTST);
+
+        p = omap44xx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+
+        return r;
+}
+
+/* Powerdomain low-level functions */
+
+static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+                                        (pwrst << OMAP_POWERSTATE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
+        return 0;
+}
+
+static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+
+        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LOGICSTATEST_MASK;
+        v >>= OMAP4430_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 {
-        if (cpu_is_omap44xx()) {
-                omap44xx_prm_enable_io_wakeup();
-                return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP4430_LOGICRETSTATE_MASK;
+        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+
+        return v;
+}
+
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
+
+static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
+
+static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+                                            pwrdm->prcm_offs,
+                                            OMAP4_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+               (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
         }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
         return 0;
 }
-subsys_initcall(omap4xxx_prcm_init);
+
+struct pwrdm_ops omap4_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
+        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
+        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+};
+
+/*
+ * XXX document
+ */
+static struct prm_ll_data omap44xx_prm_ll_data = {
+        .read_reset_sources = &omap44xx_prm_read_reset_sources,
+};
+
+static int __init omap44xx_prm_init(void)
+{
+        int ret;
+
+        if (!cpu_is_omap44xx())
+                return 0;
+
+        ret = prm_register(&omap44xx_prm_ll_data);
+        if (ret)
+                return ret;
+
+        omap44xx_prm_enable_io_wakeup();
+
+        return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+}
+subsys_initcall(omap44xx_prm_init);
+
+static void __exit omap44xx_prm_exit(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+
+        /* Should never happen */
+        WARN(prm_unregister(&omap44xx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap44xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index ee72ae6bd8c9..c8e1accdc90e 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -771,6 +771,8 @@ extern void omap44xx_prm_ocp_barrier(void);
 extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
 extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
 
+extern u32 omap44xx_prm_get_reset_sources(void);
+
 # endif
 
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 6b4d332be2f6..945b4ad6ab84 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,10 +24,11 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 
-#include <plat/common.h>
 #include <plat/prcm.h>
 
 #include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
+#include "prm3xxx.h"
 #include "prm44xx.h"
 
 /*
@@ -53,6 +54,13 @@ static struct irq_chip_generic **prcm_irq_chips;
  */
 static struct omap_prcm_irq_setup *prcm_irq_setup;
 
+/*
+ * prm_ll_data: function pointers to SoC-specific implementations of
+ * common PRM functions
+ */
+static struct prm_ll_data null_prm_ll_data;
+static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
+
 /* Private functions */
 
 /*
@@ -319,64 +327,71 @@ err:
         return -ENOMEM;
 }
 
-/*
- * Stubbed functions so that common files continue to build when
- * custom builds are used
- * XXX These are temporary and should be removed at the earliest possible
- * opportunity
+/**
+ * prm_read_reset_sources - return the sources of the SoC's last reset
+ *
+ * Return a u32 bitmask representing the reset sources that caused the
+ * SoC to reset.  The low-level per-SoC functions called by this
+ * function remap the SoC-specific reset source bits into an
+ * OMAP-common set of reset source bits, defined in
+ * arch/arm/mach-omap2/prm.h.  Returns the standardized reset source
+ * u32 bitmask from the hardware upon success, or returns (1 <<
+ * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
+ * function was registered.
  */
-u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
+u32 prm_read_reset_sources(void)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
-}
+        u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
 
-void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-}
+        if (prm_ll_data->read_reset_sources)
+                ret = prm_ll_data->read_reset_sources();
+        else
+                WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
 
-u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
-                s16 module, s16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
+        return ret;
 }
 
-u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+/**
+ * prm_register - register per-SoC low-level data with the PRM
+ * @pld: low-level per-SoC OMAP PRM data & function pointers to register
+ *
+ * Register per-SoC low-level OMAP PRM data and function pointers with
+ * the OMAP PRM common interface.  The caller must keep the data
+ * pointed to by @pld valid until it calls prm_unregister() and
+ * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
+ * is NULL, or -EEXIST if prm_register() has already been called
+ * without an intervening prm_unregister().
+ */
+int prm_register(struct prm_ll_data *pld)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
-}
+        if (!pld)
+                return -EINVAL;
 
-u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
-}
+        if (prm_ll_data != &null_prm_ll_data)
+                return -EEXIST;
 
-u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
-}
+        prm_ll_data = pld;
 
-int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
         return 0;
 }
 
-int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+/**
+ * prm_unregister - unregister per-SoC low-level data & function pointers
+ * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
+ *
+ * Unregister per-SoC low-level OMAP PRM data and function pointers
+ * that were previously registered with prm_register().  The
+ * caller may not destroy any of the data pointed to by @pld until
+ * this function returns successfully.  Returns 0 upon success, or
+ * -EINVAL if @pld is NULL or if @pld does not match the struct
+ * prm_ll_data * previously registered by prm_register().
+ */
+int prm_unregister(struct prm_ll_data *pld)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
-}
+        if (!pld || prm_ll_data != pld)
+                return -EINVAL;
+
+        prm_ll_data = &null_prm_ll_data;
 
-int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
-                                                u8 st_shift)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
         return 0;
 }
-
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
index 8bfaf342a028..1ee58c281a31 100644
--- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
+++ b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Hynix H8MBX00U0MER-0EM */
 static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index a391b4939f74..85cccc004c06 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
 #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Micron MT46H32M32LF-6 */
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 845c4fd2b125..0fa7ffa9b5ed 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -18,10 +18,8 @@
 #include <linux/io.h>
 
 #include "common.h"
-#include <plat/clock.h>
-#include <plat/sdrc.h>
-
 #include "sdram-nokia.h"
+#include "sdrc.h"
 
 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
 struct sdram_timings {
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
index cd4352917022..003f7bf4e2e3 100644
--- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
+++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Numonyx  M65KXXXXAM */
 static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 0e518a72831f..8dc3de5ebb5b 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
 #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Qimonda HYB18M512160AF-6 */
 static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index e3d345f46409..c64ee1904be8 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -24,10 +24,7 @@
 #include <linux/io.h>
 
 #include "common.h"
-#include <plat/clock.h>
-#include <plat/sram.h>
-
-#include <plat/sdrc.h>
+#include "clock.h"
 #include "sdrc.h"
 
 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
@@ -160,19 +157,3 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
         sdrc_write_reg(l, SDRC_POWER);
         omap2_sms_save_context();
 }
-
-void omap2_sms_write_rot_control(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_CONTROL(ctx));
-}
-
-void omap2_sms_write_rot_size(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_SIZE(ctx));
-}
-
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
-}
-
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index b3f83799e6cf..69c4b329452e 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -2,12 +2,14 @@
 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
 
 /*
- * OMAP2 SDRC register definitions
+ * OMAP2/3 SDRC/SMS macros and prototypes
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
+ * Tony Lindgren
+ * Richard Woodruff
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,8 +17,6 @@
  */
 #undef DEBUG
 
-#include <plat/sdrc.h>
-
 #ifndef __ASSEMBLER__
 
 #include <linux/io.h>
@@ -50,6 +50,58 @@ static inline u32 sms_read_reg(u16 reg)
 {
         return __raw_readl(OMAP_SMS_REGADDR(reg));
 }
+
+
+/**
+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ * @rate: SDRC clock rate (in Hz)
+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ * @mr: Value to program to SDRC_MR for this rate
+ *
+ * This structure holds a pre-computed set of register values for the
+ * SDRC for a given SDRC clock rate and SDRAM chip.  These are
+ * intended to be pre-computed and specified in an array in the board-*.c
+ * files.  The structure is keyed off the 'rate' field.
+ */
+struct omap_sdrc_params {
+        unsigned long rate;
+        u32 actim_ctrla;
+        u32 actim_ctrlb;
+        u32 rfr_ctrl;
+        u32 mr;
+};
+
+#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
+
+struct memory_timings {
+        u32 m_type;             /* ddr = 1, sdr = 0 */
+        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
+        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
+        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
+        u32 base_cs;            /* base chip select to use for calculations */
+};
+
+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+struct omap_sdrc_params *rx51_get_sdram_timings(void);
+
+u32 omap2xxx_sdrc_dll_is_unlocked(void);
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
+
+
 #else
 #define OMAP242X_SDRC_REGADDR(reg)                                      \
                         OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
@@ -57,6 +109,7 @@ static inline u32 sms_read_reg(u16 reg)
                         OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
 #define OMAP34XX_SDRC_REGADDR(reg)                                      \
                         OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+
 #endif  /* __ASSEMBLER__ */
 
 /* Minimum frequency that the SDRC DLL can lock at */
@@ -74,4 +127,85 @@ static inline u32 sms_read_reg(u16 reg)
  */
 #define SDRC_MPURATE_LOOPS              96
 
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_CS_CFG             0x040
+#define SDRC_SHARING            0x044
+#define SDRC_ERR_TYPE           0x04C
+#define SDRC_DLLA_CTRL          0x060
+#define SDRC_DLLA_STATUS        0x064
+#define SDRC_DLLB_CTRL          0x068
+#define SDRC_DLLB_STATUS        0x06C
+#define SDRC_POWER              0x070
+#define SDRC_MCFG_0             0x080
+#define SDRC_MR_0               0x084
+#define SDRC_EMR2_0             0x08c
+#define SDRC_ACTIM_CTRL_A_0     0x09c
+#define SDRC_ACTIM_CTRL_B_0     0x0a0
+#define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MANUAL_0           0x0a8
+#define SDRC_MCFG_1             0x0B0
+#define SDRC_MR_1               0x0B4
+#define SDRC_EMR2_1             0x0BC
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
+#define SDRC_MANUAL_1           0x0D8
+
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
+
+
+/*
+ * SMS register access
+ */
+
+#define OMAP242X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+
+#define SMS_SYSCONFIG                   0x010
+/* REVISIT: fill in other SMS registers here */
+
+
+
 #endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 73e55e485329..907291714643 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,16 +24,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
 #include "clock.h"
 #include "sdrc.h"
+#include "sram.h"
 
 /* Memory timing, DLL mode flags */
 #define M_DDR           1
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a507cd6cf4f1..aa30a3c20883 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -28,19 +28,20 @@
 #include <linux/console.h>
 
 #include <plat/omap-serial.h>
-#include "common.h"
-#include <plat/dma.h>
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/omap-pm.h>
-#include <plat/serial.h>
+#include <plat-omap/dma-omap.h>
 
+#include "common.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include "omap-pm.h"
+#include "soc.h"
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
 #include "control.h"
 #include "mux.h"
+#include "serial.h"
 
 /*
  * NOTE: By default the serial auto_suspend timeout is disabled as it causes
diff --git a/arch/arm/mach-omap2/serial.h b/arch/arm/mach-omap2/serial.h
new file mode 100644
index 000000000000..c4014f013df0
--- /dev/null
+++ b/arch/arm/mach-omap2/serial.h
@@ -0,0 +1 @@
+#include <mach/serial.h>
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 506987979c1c..d1dedc8195ed 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,13 +26,12 @@
 
 #include <asm/assembler.h>
 
-#include <plat/sram.h>
-
 #include "omap34xx.h"
 #include "iomap.h"
-#include "cm2xxx_3xxx.h"
-#include "prm2xxx_3xxx.h"
+#include "cm3xxx.h"
+#include "prm3xxx.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "control.h"
 
 /*
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index fc9b96daf851..070096496e20 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -1,7 +1,473 @@
-#include <plat/cpu.h>
+/*
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+ * Copyright (C) 2009-11 Texas Instruments.
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
 #include "omap24xx.h"
 #include "omap34xx.h"
 #include "omap44xx.h"
 #include "ti81xx.h"
 #include "am33xx.h"
 #include "omap54xx.h"
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bitops.h>
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+
+#ifdef CONFIG_SOC_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap4
+# endif
+#endif
+
+#ifdef CONFIG_SOC_OMAP5
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap5
+# endif
+#endif
+
+#ifdef CONFIG_SOC_AM33XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am33xx
+# endif
+#endif
+
+/*
+ * Omap device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define OMAP2_DEVICE_TYPE_TEST          0
+#define OMAP2_DEVICE_TYPE_EMU           1
+#define OMAP2_DEVICE_TYPE_SEC           2
+#define OMAP2_DEVICE_TYPE_GP            3
+#define OMAP2_DEVICE_TYPE_BAD           4
+
+int omap_type(void);
+
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
+
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
+ * cpu_is_omap243x():   True for OMAP2430
+ * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
+ * cpu_is_omap446x():   True for OMAP4460
+ * cpu_is_omap447x():   True for OMAP4470
+ * soc_is_omap543x():   True for OMAP5430, OMAP5432
+ */
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
+
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+
+#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_AM_CLASS(class, id)                          \
+static inline int is_am ##class (void)                  \
+{                                                       \
+        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
+}
+
+#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_TI_CLASS(class, id)                  \
+static inline int is_ti ##class (void)          \
+{                                                       \
+        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
+}
+
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
+
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+#define IS_AM_SUBCLASS(subclass, id)                    \
+static inline int is_am ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(35xx, 0x35)
+IS_OMAP_CLASS(54xx, 0x54)
+IS_AM_CLASS(33xx, 0x33)
+
+IS_TI_CLASS(81xx, 0x81)
+
+IS_OMAP_SUBCLASS(242x, 0x242)
+IS_OMAP_SUBCLASS(243x, 0x243)
+IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
+IS_OMAP_SUBCLASS(446x, 0x446)
+IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
+
+IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
+IS_AM_SUBCLASS(335x, 0x335)
+
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap242x()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap343x()               0
+#define cpu_is_ti81xx()                 0
+#define cpu_is_ti816x()                 0
+#define cpu_is_ti814x()                 0
+#define soc_is_am35xx()                 0
+#define soc_is_am33xx()                 0
+#define soc_is_am335x()                 0
+#define cpu_is_omap44xx()               0
+#define cpu_is_omap443x()               0
+#define cpu_is_omap446x()               0
+#define cpu_is_omap447x()               0
+#define soc_is_omap54xx()               0
+#define soc_is_omap543x()               0
+
+#if defined(MULTI_OMAP2)
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             is_omap24xx()
+# endif
+# if defined (CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             is_omap242x()
+# endif
+# if defined (CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             is_omap243x()
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap34xx()             is_omap34xx()
+#  define cpu_is_omap343x()             is_omap343x()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  define cpu_is_omap34xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP3430)
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap343x()             1
+# endif
+#endif
+
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap2420():   True for OMAP2420
+ * cpu_is_omap2422():   True for OMAP2422
+ * cpu_is_omap2423():   True for OMAP2423
+ * cpu_is_omap2430():   True for OMAP2430
+ * cpu_is_omap3430():   True for OMAP3430
+ */
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+IS_OMAP_TYPE(2420, 0x2420)
+IS_OMAP_TYPE(2422, 0x2422)
+IS_OMAP_TYPE(2423, 0x2423)
+IS_OMAP_TYPE(2430, 0x2430)
+IS_OMAP_TYPE(3430, 0x3430)
+
+#define cpu_is_omap2420()               0
+#define cpu_is_omap2422()               0
+#define cpu_is_omap2423()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap3430()               0
+#define cpu_is_omap3630()               0
+#define soc_is_omap5430()               0
+
+/* These are needed for the common code */
+#ifdef CONFIG_ARCH_OMAP2PLUS
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_class_is_omap1()            0
+#define cpu_class_is_omap2()            1
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2)
+# undef  cpu_is_omap2420
+# undef  cpu_is_omap2422
+# undef  cpu_is_omap2423
+# undef  cpu_is_omap2430
+# define cpu_is_omap2420()              is_omap2420()
+# define cpu_is_omap2422()              is_omap2422()
+# define cpu_is_omap2423()              is_omap2423()
+# define cpu_is_omap2430()              is_omap2430()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+# undef cpu_is_omap3430
+# undef cpu_is_ti81xx
+# undef cpu_is_ti816x
+# undef cpu_is_ti814x
+# undef soc_is_am35xx
+# define cpu_is_omap3430()              is_omap3430()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti81xx()                is_ti81xx()
+# define cpu_is_ti816x()                is_ti816x()
+# define cpu_is_ti814x()                is_ti814x()
+# define soc_is_am35xx()                is_am35xx()
+#endif
+
+# if defined(CONFIG_SOC_AM33XX)
+# undef soc_is_am33xx
+# undef soc_is_am335x
+# define soc_is_am33xx()                is_am33xx()
+# define soc_is_am335x()                is_am335x()
+#endif
+
+# if defined(CONFIG_ARCH_OMAP4)
+# undef cpu_is_omap44xx
+# undef cpu_is_omap443x
+# undef cpu_is_omap446x
+# undef cpu_is_omap447x
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
+# define cpu_is_omap446x()              is_omap446x()
+# define cpu_is_omap447x()              is_omap447x()
+# endif
+
+# if defined(CONFIG_SOC_OMAP5)
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx()              is_omap54xx()
+# define soc_is_omap543x()              is_omap543x()
+#endif
+
+/* Various silicon revisions for omap2 */
+#define OMAP242X_CLASS          0x24200024
+#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
+
+#define OMAP243X_CLASS          0x24300024
+#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
+
+#define OMAP343X_CLASS          0x34300034
+#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
+
+#define OMAP363X_CLASS          0x36300034
+#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
+
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+
+#define TI814X_CLASS            0x81400034
+#define TI8148_REV_ES1_0        TI814X_CLASS
+#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
+
+#define AM35XX_CLASS            0x35170034
+#define AM35XX_REV_ES1_0        AM35XX_CLASS
+#define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
+
+#define AM335X_CLASS            0x33500033
+#define AM335X_REV_ES1_0        AM335X_CLASS
+
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
+
+#define OMAP446X_CLASS          0x44600044
+#define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
+#define OMAP4460_REV_ES1_1      (OMAP446X_CLASS | (0x11 << 8))
+
+#define OMAP447X_CLASS          0x44700044
+#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
+
+#define OMAP54XX_CLASS          0x54000054
+#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
+void omap2xxx_check_revision(void);
+void omap3xxx_check_revision(void);
+void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
+void omap3xxx_check_features(void);
+void ti81xx_check_features(void);
+void omap4xxx_check_features(void);
+
+/*
+ * Runtime detection of OMAP3 features
+ *
+ * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
+ *    family have OS-level control over the I/O chain clock.  This is
+ *    to avoid a window during which wakeups could potentially be lost
+ *    during powerdomain transitions.  If this bit is set, it
+ *    indicates that the chip does support OS-level control of this
+ *    feature.
+ */
+extern u32 omap_features;
+
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
+#define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
+#define OMAP3_HAS_IO_CHAIN_CTRL         BIT(8)
+#define OMAP4_HAS_MPU_1GHZ              BIT(9)
+#define OMAP4_HAS_MPU_1_2GHZ            BIT(10)
+#define OMAP4_HAS_MPU_1_5GHZ            BIT(11)
+
+
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP3_HAS_ ##flag;       \
+}                                                       \
+
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
+OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
+
+/*
+ * Runtime detection of OMAP4 features
+ */
+#define OMAP4_HAS_FEATURE(feat, flag)                   \
+static inline unsigned int omap4_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP4_HAS_ ##flag;       \
+}                                                       \
+
+OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
+OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
+OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+
+#endif  /* __ASSEMBLY__ */
+
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index f8217a5a4a26..b0e77a407047 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -23,8 +23,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 
-#include <plat/omap_device.h>
-
+#include "soc.h"
+#include "omap_device.h"
 #include "voltage.h"
 #include "control.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
new file mode 100644
index 000000000000..0ff0f068bea8
--- /dev/null
+++ b/arch/arm/mach-omap2/sram.c
@@ -0,0 +1,305 @@
+/*
+ *
+ * OMAP SRAM detection and management
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/fncpy.h>
+#include <asm/tlb.h>
+#include <asm/cacheflush.h>
+
+#include <asm/mach/map.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "prm2xxx_3xxx.h"
+#include "sdrc.h"
+#include "sram.h"
+
+#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
+#else
+#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#endif
+#define OMAP5_SRAM_PA           0x40300000
+
+#define SRAM_BOOTLOADER_SZ      0x00
+
+#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
+
+#define GP_DEVICE               0x300
+
+#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
+
+static unsigned long omap_sram_start;
+static unsigned long omap_sram_skip;
+static unsigned long omap_sram_size;
+
+/*
+ * Depending on the target RAMFS firewall setup, the public usable amount of
+ * SRAM varies.  The default accessible size for all device types is 2k. A GP
+ * device allows ARM11 but not other initiators for full size. This
+ * functionality seems ok until some nice security API happens.
+ */
+static int is_sram_locked(void)
+{
+        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
+                /* RAMFW: R/W access to all initiators for all qualifier sets */
+                if (cpu_is_omap242x()) {
+                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                }
+                if (cpu_is_omap34xx()) {
+                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+                }
+                return 0;
+        } else
+                return 1; /* assume locked with no PPA or security driver */
+}
+
+/*
+ * The amount of SRAM depends on the core type.
+ * Note that we cannot try to test for SRAM here because writes
+ * to secure SRAM will hang the system. Also the SRAM is not
+ * yet mapped at this point.
+ */
+static void __init omap_detect_sram(void)
+{
+        omap_sram_skip = SRAM_BOOTLOADER_SZ;
+        if (is_sram_locked()) {
+                if (cpu_is_omap34xx()) {
+                        omap_sram_start = OMAP3_SRAM_PUB_PA;
+                        if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+                            (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+                                omap_sram_size = 0x7000; /* 28K */
+                                omap_sram_skip += SZ_16K;
+                        } else {
+                                omap_sram_size = 0x8000; /* 32K */
+                        }
+                } else if (cpu_is_omap44xx()) {
+                        omap_sram_start = OMAP4_SRAM_PUB_PA;
+                        omap_sram_size = 0xa000; /* 40K */
+                } else if (soc_is_omap54xx()) {
+                        omap_sram_start = OMAP5_SRAM_PA;
+                        omap_sram_size = SZ_128K; /* 128KB */
+                } else {
+                        omap_sram_start = OMAP2_SRAM_PUB_PA;
+                        omap_sram_size = 0x800; /* 2K */
+                }
+        } else {
+                if (soc_is_am33xx()) {
+                        omap_sram_start = AM33XX_SRAM_PA;
+                        omap_sram_size = 0x10000; /* 64K */
+                } else if (cpu_is_omap34xx()) {
+                        omap_sram_start = OMAP3_SRAM_PA;
+                        omap_sram_size = 0x10000; /* 64K */
+                } else if (cpu_is_omap44xx()) {
+                        omap_sram_start = OMAP4_SRAM_PA;
+                        omap_sram_size = 0xe000; /* 56K */
+                } else if (soc_is_omap54xx()) {
+                        omap_sram_start = OMAP5_SRAM_PA;
+                        omap_sram_size = SZ_128K; /* 128KB */
+                } else {
+                        omap_sram_start = OMAP2_SRAM_PA;
+                        if (cpu_is_omap242x())
+                                omap_sram_size = 0xa0000; /* 640K */
+                        else if (cpu_is_omap243x())
+                                omap_sram_size = 0x10000; /* 64K */
+                }
+        }
+}
+
+/*
+ * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
+ */
+static void __init omap2_map_sram(void)
+{
+        int cached = 1;
+
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        if (cpu_is_omap44xx()) {
+                omap_sram_start += PAGE_SIZE;
+                omap_sram_size -= SZ_16K;
+        }
+#endif
+        if (cpu_is_omap34xx()) {
+                /*
+                 * SRAM must be marked as non-cached on OMAP3 since the
+                 * CORE DPLL M2 divider change code (in SRAM) runs with the
+                 * SDRAM controller disabled, and if it is marked cached,
+                 * the ARM may attempt to write cache lines back to SDRAM
+                 * which will cause the system to hang.
+                 */
+                cached = 0;
+        }
+
+        omap_map_sram(omap_sram_start, omap_sram_size,
+                        omap_sram_skip, cached);
+}
+
+static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                              u32 base_cs, u32 force_unlock);
+
+void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                   u32 base_cs, u32 force_unlock)
+{
+        BUG_ON(!_omap2_sram_ddr_init);
+        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
+                             base_cs, force_unlock);
+}
+
+static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
+                                          u32 mem_type);
+
+void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
+{
+        BUG_ON(!_omap2_sram_reprogram_sdrc);
+        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
+}
+
+static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+
+u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
+{
+        BUG_ON(!_omap2_set_prcm);
+        return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
+}
+
+#ifdef CONFIG_SOC_OMAP2420
+static int __init omap242x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
+                                        omap242x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
+                                            omap242x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
+                                         omap242x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap242x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAP2430
+static int __init omap243x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
+                                        omap243x_sram_ddr_init_sz);
+
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
+                                            omap243x_sram_reprogram_sdrc_sz);
+
+        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
+                                         omap243x_sram_set_prcm_sz);
+
+        return 0;
+}
+#else
+static inline int omap243x_sram_init(void)
+{
+        return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+
+static u32 (*_omap3_sram_configure_core_dpll)(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+{
+        BUG_ON(!_omap3_sram_configure_core_dpll);
+        return _omap3_sram_configure_core_dpll(
+                        m2, unlock_dll, f, inc,
+                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
+                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
+}
+
+void omap3_sram_restore_context(void)
+{
+        omap_sram_reset();
+
+        _omap3_sram_configure_core_dpll =
+                omap_sram_push(omap3_sram_configure_core_dpll,
+                               omap3_sram_configure_core_dpll_sz);
+        omap_push_sram_idle();
+}
+
+static inline int omap34xx_sram_init(void)
+{
+        omap3_sram_restore_context();
+        return 0;
+}
+#else
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_ARCH_OMAP3 */
+
+static inline int am33xx_sram_init(void)
+{
+        return 0;
+}
+
+int __init omap_sram_init(void)
+{
+        omap_detect_sram();
+        omap2_map_sram();
+
+        if (cpu_is_omap242x())
+                omap242x_sram_init();
+        else if (cpu_is_omap2430())
+                omap243x_sram_init();
+        else if (soc_is_am33xx())
+                am33xx_sram_init();
+        else if (cpu_is_omap34xx())
+                omap34xx_sram_init();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
new file mode 100644
index 000000000000..ca7277c2a9ee
--- /dev/null
+++ b/arch/arm/mach-omap2/sram.h
@@ -0,0 +1,83 @@
+/*
+ * Interface for functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASSEMBLY__
+#include <plat/sram.h>
+
+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                u32 base_cs, u32 force_unlock);
+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                      u32 mem_type);
+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
+
+/* Do not use these */
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
+
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
+
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+
+
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
+
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern unsigned long omap3_sram_configure_core_dpll_sz;
+
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PA           0x40304000
+#define OMAP4_SRAM_VA           0xfe404000
+#else
+#define OMAP4_SRAM_PA           0x40300000
+#endif
+#define AM33XX_SRAM_PA          0x40300000
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 8f7326cd435b..680a7c56cc3e 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -34,8 +34,8 @@
 
 #include "soc.h"
 #include "iomap.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "prm2xxx.h"
+#include "cm2xxx.h"
 #include "sdrc.h"
 
         .text
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index b140d6578529..a1e9edd673f4 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -34,8 +34,8 @@
 
 #include "soc.h"
 #include "iomap.h"
-#include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "prm2xxx.h"
+#include "cm2xxx.h"
 #include "sdrc.h"
 
         .text
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 2d0ceaa23fb8..1446331b576a 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,7 @@
 #include "soc.h"
 #include "iomap.h"
 #include "sdrc.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 
 /*
  * This file needs be built unconditionally as ARM to interoperate correctly
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 69e46631a7cd..c5bc2cb4d8d3 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -43,10 +43,11 @@
 #include <asm/sched_clock.h>
 
 #include <asm/arch_timer.h>
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include <plat/counter-32k.h>
 #include <plat/dmtimer.h>
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 
 #include "soc.h"
 #include "common.h"
@@ -559,6 +560,8 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
         if (timer_dev_attr)
                 pdata->timer_capability = timer_dev_attr->timer_capability;
 
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+
         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
                                  NULL, 0, 0);
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 635e109f5ad3..827f54a1dd1d 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -26,9 +26,6 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 
-#include <plat/i2c.h>
-#include <plat/usb.h>
-
 #include "soc.h"
 #include "twl-common.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 3c434498e12e..d1dbe125b34f 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -25,10 +25,10 @@
 
 #include <asm/io.h>
 
-#include <plat/usb.h>
-#include <plat/omap_device.h>
-
+#include "soc.h"
+#include "omap_device.h"
 #include "mux.h"
+#include "usb.h"
 
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 51da21cb78f1..7b33b375fe77 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -25,12 +25,10 @@
 #include <linux/io.h>
 #include <linux/usb/musb.h>
 
-#include <plat/usb.h>
-#include <plat/omap_device.h>
-
-#include "am35xx.h"
-
+#include "omap_device.h"
+#include "soc.h"
 #include "mux.h"
+#include "usb.h"
 
 static struct musb_hdrc_config musb_config = {
         .multipoint     = 1,
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 805bea6edf17..a8795ff19e6d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -15,10 +15,11 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/export.h>
+#include <linux/platform_data/usb-omap.h>
 
 #include <linux/usb/musb.h>
 
-#include <plat/gpmc.h>
+#include "gpmc.h"
 
 #include "mux.h"
 
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
new file mode 100644
index 000000000000..9b986ead7c45
--- /dev/null
+++ b/arch/arm/mach-omap2/usb.h
@@ -0,0 +1,82 @@
+#include <linux/platform_data/usb-omap.h>
+
+/* AM35x */
+/* USB 2.0 PHY Control */
+#define CONF2_PHY_GPIOMODE      (1 << 23)
+#define CONF2_OTGMODE           (3 << 14)
+#define CONF2_NO_OVERRIDE       (0 << 14)
+#define CONF2_FORCE_HOST        (1 << 14)
+#define CONF2_FORCE_DEVICE      (2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN          (1 << 13)
+#define CONF2_VBDTCTEN          (1 << 12)
+#define CONF2_REFFREQ_24MHZ     (2 << 8)
+#define CONF2_REFFREQ_26MHZ     (7 << 8)
+#define CONF2_REFFREQ_13MHZ     (6 << 8)
+#define CONF2_REFFREQ           (0xf << 8)
+#define CONF2_PHYCLKGD          (1 << 7)
+#define CONF2_VBUSSENSE         (1 << 6)
+#define CONF2_PHY_PLLON         (1 << 5)
+#define CONF2_RESET             (1 << 4)
+#define CONF2_PHYPWRDN          (1 << 3)
+#define CONF2_OTGPWRDN          (1 << 2)
+#define CONF2_DATPOL            (1 << 1)
+
+/* TI81XX specific definitions */
+#define USBCTRL0        0x620
+#define USBSTAT0        0x624
+
+/* TI816X PHY controls bits */
+#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
+#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
+
+/* TI814X PHY controls bits */
+#define USBPHY_CM_PWRDN         (1 << 0)
+#define USBPHY_OTG_PWRDN        (1 << 1)
+#define USBPHY_CHGDET_DIS       (1 << 2)
+#define USBPHY_CHGDET_RSTRT     (1 << 3)
+#define USBPHY_SRCONDM          (1 << 4)
+#define USBPHY_SINKONDP         (1 << 5)
+#define USBPHY_CHGISINK_EN      (1 << 6)
+#define USBPHY_CHGVSRC_EN       (1 << 7)
+#define USBPHY_DMPULLUP         (1 << 8)
+#define USBPHY_DPPULLUP         (1 << 9)
+#define USBPHY_CDET_EXTCTL      (1 << 10)
+#define USBPHY_GPIO_MODE        (1 << 12)
+#define USBPHY_DPOPBUFCTL       (1 << 13)
+#define USBPHY_DMOPBUFCTL       (1 << 14)
+#define USBPHY_DPINPUT          (1 << 15)
+#define USBPHY_DMINPUT          (1 << 16)
+#define USBPHY_DPGPIO_PD        (1 << 17)
+#define USBPHY_DMGPIO_PD        (1 << 18)
+#define USBPHY_OTGVDET_EN       (1 << 19)
+#define USBPHY_OTGSESSEND_EN    (1 << 20)
+#define USBPHY_DATA_POLARITY    (1 << 23)
+
+struct usbhs_omap_board_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+
+        /* have to be valid if phy_reset is true and portx is in phy mode */
+        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+
+        /* Set this to true for ES2.x silicon */
+        unsigned                        es2_compatibility:1;
+
+        unsigned                        phy_reset:1;
+
+        /*
+         * Regulators for USB PHYs.
+         * Each PHY can have a separate regulator.
+         */
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
+};
+
+extern void usb_musb_init(struct omap_musb_board_data *board_data);
+extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+extern void am35x_set_mode(u8 musb_mode);
+extern void ti81xx_musb_phy_power(u8 on);
+
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index b2f1c67043a2..f6b6c37ac3f4 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -11,7 +11,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 #include "wd_timer.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index f6bbba73b535..a78f81034a9f 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -10,7 +10,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
 #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
 
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 
 extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
 extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index dacaee009a4e..8d885848600a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,13 +3,12 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
+obj-y := sram.o dma.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
 
 # omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
 
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
@@ -20,4 +19,3 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
 
-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
deleted file mode 100644
index 9d7ac20ef8f9..000000000000
--- a/arch/arm/plat-omap/clock.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- *  linux/arch/arm/plat-omap/clock.c
- *
- *  Copyright (C) 2004 - 2008 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *
- *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/cpufreq.h>
-#include <linux/io.h>
-
-#include <plat/clock.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
-
-static struct clk_functions *arch_clock;
-
-/*
- * Standard clock functions defined in include/linux/clk.h
- */
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        int ret;
-
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        if (!arch_clock || !arch_clock->clk_enable)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_enable(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        if (!arch_clock || !arch_clock->clk_disable)
-                return;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (clk->usecount == 0) {
-                pr_err("Trying disable clock %s with 0 usecount\n",
-                       clk->name);
-                WARN_ON(1);
-                goto out;
-        }
-
-        arch_clock->clk_disable(clk);
-
-out:
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long flags;
-        unsigned long ret;
-
-        if (clk == NULL || IS_ERR(clk))
-                return 0;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = clk->rate;
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*
- * Optional clock functions defined in include/linux/clk.h
- */
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        long ret;
-
-        if (clk == NULL || IS_ERR(clk))
-                return 0;
-
-        if (!arch_clock || !arch_clock->clk_round_rate)
-                return 0;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_round_rate(clk, rate);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-
-        if (!arch_clock || !arch_clock->clk_set_rate)
-                return ret;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_set_rate(clk, rate);
-        if (ret == 0)
-                propagate_rate(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
-                return ret;
-
-        if (!arch_clock || !arch_clock->clk_set_parent)
-                return ret;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (clk->usecount == 0) {
-                ret = arch_clock->clk_set_parent(clk, parent);
-                if (ret == 0)
-                        propagate_rate(clk);
-        } else
-                ret = -EBUSY;
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-/*
- * OMAP specific clock functions shared between omap1 and omap2
- */
-
-int __initdata mpurate;
-
-/*
- * By default we use the rate set by the bootloader.
- * You can override this with mpurate= cmdline option.
- */
-static int __init omap_clk_setup(char *str)
-{
-        get_option(&str, &mpurate);
-
-        if (!mpurate)
-                return 1;
-
-        if (mpurate < 1000)
-                mpurate *= 1000000;
-
-        return 1;
-}
-__setup("mpurate=", omap_clk_setup);
-
-/* Used for clocks that always have same value as the parent clock */
-unsigned long followparent_recalc(struct clk *clk)
-{
-        return clk->parent->rate;
-}
-
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap_fixed_divisor_recalc(struct clk *clk)
-{
-        WARN_ON(!clk->fixed_div);
-
-        return clk->parent->rate / clk->fixed_div;
-}
-
-void clk_reparent(struct clk *child, struct clk *parent)
-{
-        list_del_init(&child->sibling);
-        if (parent)
-                list_add(&child->sibling, &parent->children);
-        child->parent = parent;
-
-        /* now do the debugfs renaming to reattach the child
-           to the proper parent */
-}
-
-/* Propagate rate to children */
-void propagate_rate(struct clk *tclk)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &tclk->children, sibling) {
-                if (clkp->recalc)
-                        clkp->rate = clkp->recalc(clkp);
-                propagate_rate(clkp);
-        }
-}
-
-static LIST_HEAD(root_clks);
-
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-void recalculate_root_clocks(void)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &root_clks, sibling) {
-                if (clkp->recalc)
-                        clkp->rate = clkp->recalc(clkp);
-                propagate_rate(clkp);
-        }
-}
-
-/**
- * clk_preinit - initialize any fields in the struct clk before clk init
- * @clk: struct clk * to initialize
- *
- * Initialize any struct clk fields needed before normal clk initialization
- * can run.  No return value.
- */
-void clk_preinit(struct clk *clk)
-{
-        INIT_LIST_HEAD(&clk->children);
-}
-
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        /*
-         * trap out already registered clocks
-         */
-        if (clk->node.next || clk->node.prev)
-                return 0;
-
-        mutex_lock(&clocks_mutex);
-        if (clk->parent)
-                list_add(&clk->sibling, &clk->parent->children);
-        else
-                list_add(&clk->sibling, &root_clks);
-
-        list_add(&clk->node, &clocks);
-        if (clk->init)
-                clk->init(clk);
-        mutex_unlock(&clocks_mutex);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_register);
-
-void clk_unregister(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        mutex_lock(&clocks_mutex);
-        list_del(&clk->sibling);
-        list_del(&clk->node);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-
-void clk_enable_init_clocks(void)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &clocks, node) {
-                if (clkp->flags & ENABLE_ON_INIT)
-                        clk_enable(clkp);
-        }
-}
-
-int omap_clk_enable_autoidle_all(void)
-{
-        struct clk *c;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-
-        list_for_each_entry(c, &clocks, node)
-                if (c->ops->allow_idle)
-                        c->ops->allow_idle(c);
-
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return 0;
-}
-
-int omap_clk_disable_autoidle_all(void)
-{
-        struct clk *c;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-
-        list_for_each_entry(c, &clocks, node)
-                if (c->ops->deny_idle)
-                        c->ops->deny_idle(c);
-
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return 0;
-}
-
-/*
- * Low level helpers
- */
-static int clkll_enable_null(struct clk *clk)
-{
-        return 0;
-}
-
-static void clkll_disable_null(struct clk *clk)
-{
-}
-
-const struct clkops clkops_null = {
-        .enable         = clkll_enable_null,
-        .disable        = clkll_disable_null,
-};
-
-/*
- * Dummy clock
- *
- * Used for clock aliases that are needed on some OMAPs, but not others
- */
-struct clk dummy_ck = {
-        .name   = "dummy",
-        .ops    = &clkops_null,
-};
-
-/*
- *
- */
-
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-/*
- * Disable any unused clocks left on by the bootloader
- */
-static int __init clk_disable_unused(void)
-{
-        struct clk *ck;
-        unsigned long flags;
-
-        if (!arch_clock || !arch_clock->clk_disable_unused)
-                return 0;
-
-        pr_info("clock: disabling unused clocks to save power\n");
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(ck, &clocks, node) {
-                if (ck->ops == &clkops_null)
-                        continue;
-
-                if (ck->usecount > 0 || !ck->enable_reg)
-                        continue;
-
-                arch_clock->clk_disable_unused(ck);
-        }
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return 0;
-}
-late_initcall(clk_disable_unused);
-late_initcall(omap_clk_enable_autoidle_all);
-#endif
-
-int __init clk_init(struct clk_functions * custom_clocks)
-{
-        if (!custom_clocks) {
-                pr_err("No custom clock functions registered\n");
-                BUG();
-        }
-
-        arch_clock = custom_clocks;
-
-        return 0;
-}
-
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-/*
- *      debugfs support to trace clock tree hierarchy and attributes
- */
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static struct dentry *clk_debugfs_root;
-
-static int clk_dbg_show_summary(struct seq_file *s, void *unused)
-{
-        struct clk *c;
-        struct clk *pa;
-
-        mutex_lock(&clocks_mutex);
-        seq_printf(s, "%-30s %-30s %-10s %s\n",
-                "clock-name", "parent-name", "rate", "use-count");
-
-        list_for_each_entry(c, &clocks, node) {
-                pa = c->parent;
-                seq_printf(s, "%-30s %-30s %-10lu %d\n",
-                        c->name, pa ? pa->name : "none", c->rate, c->usecount);
-        }
-        mutex_unlock(&clocks_mutex);
-
-        return 0;
-}
-
-static int clk_dbg_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clk_dbg_show_summary, inode->i_private);
-}
-
-static const struct file_operations debug_clock_fops = {
-        .open           = clk_dbg_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d;
-        struct clk *pa = c->parent;
-
-        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-
-        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-
-        d = debugfs_create_file("summary", S_IRUGO,
-                d, NULL, &debug_clock_fops);
-        if (!d)
-                return -ENOMEM;
-
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-late_initcall(clk_debugfs_init);
-
-#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
deleted file mode 100644
index 111315a69354..000000000000
--- a/arch/arm/plat-omap/common.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/common.c
- *
- * Code common to all OMAP machines.
- * The file is created by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-
-#include <plat/common.h>
-#include <plat/vram.h>
-#include <linux/platform_data/dsp-omap.h>
-#include <plat/dma.h>
-
-#include <plat/omap-secure.h>
-
-void __init omap_reserve(void)
-{
-        omap_vram_reserve_sdram_memblock();
-        omap_dsp_reserve_sdram_memblock();
-        omap_secure_ram_reserve_memblock();
-        omap_barrier_reserve_memblock();
-}
-
-void __init omap_init_consistent_dma_size(void)
-{
-#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
-#endif
-}
-
-/*
- * Stub function for OMAP2 so that common files
- * continue to build when custom builds are used
- */
-int __weak omap_secure_ram_reserve_memblock(void)
-{
-        return 0;
-}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 87ba8dd0d791..f3771cdb9838 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,9 +22,6 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 
-#include <plat/common.h>
-#include <plat/clock.h>
-
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
 #define OMAP2_32KSYNCNT_REV_OFF         0x0
 #define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 5a4678edd65a..a609e2161817 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -15,8 +15,7 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <mach/hardware.h>
-#include "../mach-omap2/debug-devices.h"
+#include <plat/debug-devices.h>
 
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index ea29bbe8e5cf..c43ea21f33b4 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -17,16 +17,33 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
-#include <plat/fpga.h>
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
  * debug board (all green), accessed through FPGA registers.
  */
 
+/* NOTE:  most boards don't have a static mapping for the FPGA ... */
+struct h2p2_dbg_fpga {
+        /* offset 0x00 */
+        u16             smc91x[8];
+        /* offset 0x10 */
+        u16             fpga_rev;
+        u16             board_rev;
+        u16             gpio_outputs;
+        u16             leds;
+        /* offset 0x18 */
+        u16             misc_inputs;
+        u16             lan_status;
+        u16             lan_reset;
+        u16             reserved0;
+        /* offset 0x20 */
+        u16             ps2_data;
+        u16             ps2_ctrl;
+        /* plus also 4 rs232 ports ... */
+};
+
 static struct h2p2_dbg_fpga __iomem *fpga;
 
 static u16 fpga_led_state;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c76ed8bff838..c288b76f8e6c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 
-#include <plat/cpu.h>
-#include <plat/dma.h>
-#include <plat/tc.h>
+#include <plat-omap/dma-omap.h>
 
 /*
  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
@@ -175,12 +173,13 @@ static inline void set_gdma_dev(int req, int dev)
 #define omap_writel(val, reg)   do {} while (0)
 #endif
 
+#ifdef CONFIG_ARCH_OMAP1
 void omap_set_dma_priority(int lch, int dst_port, int priority)
 {
         unsigned long reg;
         u32 l;
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 switch (dst_port) {
                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
                         reg = OMAP_TC_OCPT1_PRIOR;
@@ -203,18 +202,22 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
                 l |= (priority & 0xf) << 8;
                 omap_writel(l, reg);
         }
+}
+#endif
 
-        if (cpu_class_is_omap2()) {
-                u32 ccr;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+void omap_set_dma_priority(int lch, int dst_port, int priority)
+{
+        u32 ccr;
 
-                ccr = p->dma_read(CCR, lch);
-                if (priority)
-                        ccr |= (1 << 6);
-                else
-                        ccr &= ~(1 << 6);
-                p->dma_write(ccr, CCR, lch);
-        }
+        ccr = p->dma_read(CCR, lch);
+        if (priority)
+                ccr |= (1 << 6);
+        else
+                ccr &= ~(1 << 6);
+        p->dma_write(ccr, CCR, lch);
 }
+#endif
 EXPORT_SYMBOL(omap_set_dma_priority);
 
 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
@@ -228,7 +231,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
         l |= data_type;
         p->dma_write(l, CSDP, lch);
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 u16 ccr;
 
                 ccr = p->dma_read(CCR, lch);
@@ -244,7 +247,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                 p->dma_write(ccr, CCR2, lch);
         }
 
-        if (cpu_class_is_omap2() && dma_trigger) {
+        if (dma_omap2plus() && dma_trigger) {
                 u32 val;
 
                 val = p->dma_read(CCR, lch);
@@ -284,7 +287,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 {
         BUG_ON(omap_dma_in_1510_mode());
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 u16 w;
 
                 w = p->dma_read(CCR2, lch);
@@ -314,7 +317,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                 p->dma_write(w, LCH_CTRL, lch);
         }
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 u32 val;
 
                 val = p->dma_read(CCR, lch);
@@ -342,7 +345,7 @@ EXPORT_SYMBOL(omap_set_dma_color_mode);
 
 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 {
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 u32 csdp;
 
                 csdp = p->dma_read(CSDP, lch);
@@ -355,7 +358,7 @@ EXPORT_SYMBOL(omap_set_dma_write_mode);
 
 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 {
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+        if (dma_omap1() && !dma_omap15xx()) {
                 u32 l;
 
                 l = p->dma_read(LCH_CTRL, lch);
@@ -373,7 +376,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 {
         u32 l;
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 u16 w;
 
                 w = p->dma_read(CSDP, lch);
@@ -415,7 +418,7 @@ EXPORT_SYMBOL(omap_set_dma_params);
 
 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 return;
 
         p->dma_write(eidx, CSEI, lch);
@@ -447,13 +450,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         case OMAP_DMA_DATA_BURST_DIS:
                 break;
         case OMAP_DMA_DATA_BURST_4:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                         burst = 0x1;
                 else
                         burst = 0x2;
                 break;
         case OMAP_DMA_DATA_BURST_8:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                         burst = 0x2;
                         break;
                 }
@@ -463,7 +466,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                  * fall through
                  */
         case OMAP_DMA_DATA_BURST_16:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                         burst = 0x3;
                         break;
                 }
@@ -487,7 +490,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 {
         u32 l;
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 l = p->dma_read(CSDP, lch);
                 l &= ~(0x1f << 9);
                 l |= dest_port << 9;
@@ -508,7 +511,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_params);
 
 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 return;
 
         p->dma_write(eidx, CDEI, lch);
@@ -540,19 +543,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         case OMAP_DMA_DATA_BURST_DIS:
                 break;
         case OMAP_DMA_DATA_BURST_4:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                         burst = 0x1;
                 else
                         burst = 0x2;
                 break;
         case OMAP_DMA_DATA_BURST_8:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                         burst = 0x2;
                 else
                         burst = 0x3;
                 break;
         case OMAP_DMA_DATA_BURST_16:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                         burst = 0x3;
                         break;
                 }
@@ -573,7 +576,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 static inline void omap_enable_channel_irq(int lch)
 {
         /* Clear CSR */
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 p->dma_read(CSR, lch);
         else
                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -587,7 +590,7 @@ static inline void omap_disable_channel_irq(int lch)
         /* disable channel interrupts */
         p->dma_write(0, CICR, lch);
         /* Clear CSR */
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 p->dma_read(CSR, lch);
         else
                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -611,7 +614,7 @@ static inline void enable_lnk(int lch)
 
         l = p->dma_read(CLNK_CTRL, lch);
 
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 l &= ~(1 << 14);
 
         /* Set the ENABLE_LNK bits */
@@ -619,7 +622,7 @@ static inline void enable_lnk(int lch)
                 l = dma_chan[lch].next_lch | (1 << 15);
 
 #ifndef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 if (dma_chan[lch].next_linked_ch != -1)
                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
@@ -636,12 +639,12 @@ static inline void disable_lnk(int lch)
         /* Disable interrupts */
         omap_disable_channel_irq(lch);
 
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                 /* Set the STOP_LNK bit */
                 l |= 1 << 14;
         }
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 /* Clear the ENABLE_LNK bit */
                 l &= ~(1 << 15);
         }
@@ -655,7 +658,7 @@ static inline void omap2_enable_irq_lch(int lch)
         u32 val;
         unsigned long flags;
 
-        if (!cpu_class_is_omap2())
+        if (dma_omap1())
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
@@ -673,7 +676,7 @@ static inline void omap2_disable_irq_lch(int lch)
         u32 val;
         unsigned long flags;
 
-        if (!cpu_class_is_omap2())
+        if (dma_omap1())
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
@@ -712,7 +715,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
         if (p->clear_lch_regs)
                 p->clear_lch_regs(free_ch);
 
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 omap_clear_dma(free_ch);
 
         spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -723,7 +726,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
         chan->flags = 0;
 
 #ifndef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 chan->chain_id = -1;
                 chan->next_linked_ch = -1;
         }
@@ -731,13 +734,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
 
         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
-        else if (cpu_class_is_omap2())
+        else if (dma_omap2plus())
                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
                         OMAP2_DMA_TRANS_ERR_IRQ;
 
-        if (cpu_is_omap16xx()) {
+        if (dma_omap16xx()) {
                 /* If the sync device is set, configure it dynamically. */
                 if (dev_id != 0) {
                         set_gdma_dev(free_ch + 1, dev_id);
@@ -748,11 +751,11 @@ int omap_request_dma(int dev_id, const char *dev_name,
                  * id.
                  */
                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
-        } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
+        } else if (dma_omap1()) {
                 p->dma_write(dev_id, CCR, free_ch);
         }
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 omap_enable_channel_irq(free_ch);
                 omap2_enable_irq_lch(free_ch);
         }
@@ -774,7 +777,7 @@ void omap_free_dma(int lch)
         }
 
         /* Disable interrupt for logical channel */
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 omap2_disable_irq_lch(lch);
 
         /* Disable all DMA interrupts for the channel. */
@@ -784,7 +787,7 @@ void omap_free_dma(int lch)
         p->dma_write(0, CCR, lch);
 
         /* Clear registers */
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                 omap_clear_dma(lch);
 
         spin_lock_irqsave(&dma_chan_lock, flags);
@@ -810,7 +813,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 {
         u32 reg;
 
-        if (!cpu_class_is_omap2()) {
+        if (dma_omap1()) {
                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
                 return;
         }
@@ -849,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
         }
         l = p->dma_read(CCR, lch);
         l &= ~((1 << 6) | (1 << 26));
-        if (cpu_class_is_omap2() && !cpu_is_omap242x())
+        if (d->dev_caps & IS_RW_PRIORITY)
                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
         else
                 l |= ((read_prio & 0x1) << 6);
@@ -882,7 +885,7 @@ void omap_start_dma(int lch)
          * The CPC/CDAC register needs to be initialized to zero
          * before starting dma transfer.
          */
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                 p->dma_write(0, CPC, lch);
         else
                 p->dma_write(0, CDAC, lch);
@@ -1045,7 +1048,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                 offset = p->dma_read(CPC, lch);
         else
                 offset = p->dma_read(CSAC, lch);
@@ -1053,7 +1056,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
                 offset = p->dma_read(CSAC, lch);
 
-        if (!cpu_is_omap15xx()) {
+        if (!dma_omap15xx()) {
                 /*
                  * CDAC == 0 indicates that the DMA transfer on the channel has
                  * not been started (no data has been transferred so far).
@@ -1065,7 +1068,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
                         offset = p->dma_read(CSSA, lch);
         }
 
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 
         return offset;
@@ -1084,7 +1087,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
 {
         dma_addr_t offset = 0;
 
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                 offset = p->dma_read(CPC, lch);
         else
                 offset = p->dma_read(CDAC, lch);
@@ -1093,7 +1096,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
          * read before the DMA controller finished disabling the channel.
          */
-        if (!cpu_is_omap15xx() && offset == 0) {
+        if (!dma_omap15xx() && offset == 0) {
                 offset = p->dma_read(CDAC, lch);
                 /*
                  * CDAC == 0 indicates that the DMA transfer on the channel has
@@ -1104,7 +1107,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
                         offset = p->dma_read(CDSA, lch);
         }
 
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
 
         return offset;
@@ -1121,7 +1124,7 @@ int omap_dma_running(void)
 {
         int lch;
 
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                 if (omap_lcd_dma_running())
                         return 1;
 
@@ -2024,7 +2027,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
         dma_chan                = d->chan;
         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                 dma_lch_count, GFP_KERNEL);
                 if (!dma_linked_lch) {
@@ -2036,7 +2039,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
         spin_lock_init(&dma_chan_lock);
         for (ch = 0; ch < dma_chan_count; ch++) {
                 omap_clear_dma(ch);
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                         omap2_disable_irq_lch(ch);
 
                 dma_chan[ch].dev_id = -1;
@@ -2045,7 +2048,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                 if (ch >= 6 && enable_1510_mode)
                         continue;
 
-                if (cpu_class_is_omap1()) {
+                if (dma_omap1()) {
                         /*
                          * request_irq() doesn't like dev_id (ie. ch) being
                          * zero, so we have to kludge around this.
@@ -2070,11 +2073,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                 }
         }
 
-        if (cpu_class_is_omap2() && !cpu_is_omap242x())
+        if (d->dev_caps & IS_RW_PRIORITY)
                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
                                 DMA_DEFAULT_FIFO_DEPTH, 0);
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 strcpy(irq_name, "0");
                 dma_irq = platform_get_irq_byname(pdev, irq_name);
                 if (dma_irq < 0) {
@@ -2089,9 +2092,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                 }
         }
 
-        /* reserve dma channels 0 and 1 in high security devices */
-        if (cpu_is_omap34xx() &&
-                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+        /* reserve dma channels 0 and 1 in high security devices on 34xx */
+        if (d->dev_caps & HS_CHANNELS_RESERVED) {
                 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
                 dma_chan[0].dev_id = 0;
                 dma_chan[1].dev_id = 1;
@@ -2118,7 +2120,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
 {
         int dma_irq;
 
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                 char irq_name[4];
                 strcpy(irq_name, "0");
                 dma_irq = platform_get_irq_byname(pdev, irq_name);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 938b50a33439..82231a75abd6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -42,9 +42,6 @@
 #include <linux/pm_runtime.h>
 
 #include <plat/dmtimer.h>
-#include <plat/omap-pm.h>
-
-#include <mach/hardware.h>
 
 static u32 omap_reserved_systimers;
 static LIST_HEAD(omap_timer_list);
@@ -271,7 +268,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 
 #if defined(CONFIG_ARCH_OMAP1)
-
+#include <mach/hardware.h>
 /**
  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
  * @inputmask: current value of idlect mask
@@ -348,7 +345,8 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
         omap_dm_timer_enable(timer);
 
         if (!(timer->capability & OMAP_TIMER_ALWON)) {
-                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                if (timer->get_context_loss_count &&
+                        timer->get_context_loss_count(&timer->pdev->dev) !=
                                 timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
@@ -377,9 +375,11 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
 
         __omap_dm_timer_stop(timer, timer->posted, rate);
 
-        if (!(timer->capability & OMAP_TIMER_ALWON))
-                timer->ctx_loss_count =
-                        omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
+                if (timer->get_context_loss_count)
+                        timer->ctx_loss_count =
+                                timer->get_context_loss_count(&timer->pdev->dev);
+        }
 
         /*
          * Since the register values are computed and written within
@@ -495,7 +495,8 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
         omap_dm_timer_enable(timer);
 
         if (!(timer->capability & OMAP_TIMER_ALWON)) {
-                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                if (timer->get_context_loss_count &&
+                        timer->get_context_loss_count(&timer->pdev->dev) !=
                                 timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
@@ -729,6 +730,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
         timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
         timer->pdev = pdev;
         timer->capability = pdata->timer_capability;
+        timer->get_context_loss_count = pdata->get_context_loss_count;
 
         /* Skip pm_runtime_enable for OMAP1 */
         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index bcbb9d5dc293..3a77b30f53d4 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -30,9 +30,69 @@
 #include <linux/io.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
 
+#include <plat/cpu.h>
+
+#ifdef CONFIG_OMAP2_VRFB
+
+/*
+ * The first memory resource is the register region for VRFB,
+ * the rest are VRFB virtual memory areas for each VRFB context.
+ */
+
+static const struct resource omap2_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+};
+
+static const struct resource omap3_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+        DEFINE_RES_MEM_NAMED(0xe0000000u, 0x4000000, "vrfb-area-4"),
+        DEFINE_RES_MEM_NAMED(0xe4000000u, 0x4000000, "vrfb-area-5"),
+        DEFINE_RES_MEM_NAMED(0xe8000000u, 0x4000000, "vrfb-area-6"),
+        DEFINE_RES_MEM_NAMED(0xec000000u, 0x4000000, "vrfb-area-7"),
+        DEFINE_RES_MEM_NAMED(0xf0000000u, 0x4000000, "vrfb-area-8"),
+        DEFINE_RES_MEM_NAMED(0xf4000000u, 0x4000000, "vrfb-area-9"),
+        DEFINE_RES_MEM_NAMED(0xf8000000u, 0x4000000, "vrfb-area-10"),
+        DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"),
+};
+
+static int __init omap_init_vrfb(void)
+{
+        struct platform_device *pdev;
+        const struct resource *res;
+        unsigned int num_res;
+
+        if (cpu_is_omap24xx()) {
+                res = omap2_vrfb_resources;
+                num_res = ARRAY_SIZE(omap2_vrfb_resources);
+        } else if (cpu_is_omap34xx()) {
+                res = omap3_vrfb_resources;
+                num_res = ARRAY_SIZE(omap3_vrfb_resources);
+        } else {
+                return 0;
+        }
+
+        pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
+                        res, num_res, NULL, 0);
+
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+        else
+                return 0;
+}
+
+arch_initcall(omap_init_vrfb);
+#endif
+
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
 static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5683a84c6ee..f9df624d108c 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,160 +26,18 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
+#include <linux/i2c-omap.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <mach/irqs.h>
 #include <plat/i2c.h>
-#include <plat/omap_device.h>
 
-#define OMAP_I2C_SIZE           0x3f
-#define OMAP1_I2C_BASE          0xfffb3800
-#define OMAP1_INT_I2C           (32 + 4)
-
-static const char name[] = "omap_i2c";
-
-#define I2C_RESOURCE_BUILDER(base, irq)                 \
-        {                                               \
-                .start  = (base),                       \
-                .end    = (base) + OMAP_I2C_SIZE,       \
-                .flags  = IORESOURCE_MEM,               \
-        },                                              \
-        {                                               \
-                .start  = (irq),                        \
-                .flags  = IORESOURCE_IRQ,               \
-        },
-
-static struct resource i2c_resources[][2] = {
-        { I2C_RESOURCE_BUILDER(0, 0) },
-};
-
-#define I2C_DEV_BUILDER(bus_id, res, data)              \
-        {                                               \
-                .id     = (bus_id),                     \
-                .name   = name,                         \
-                .num_resources  = ARRAY_SIZE(res),      \
-                .resource       = (res),                \
-                .dev            = {                     \
-                        .platform_data  = (data),       \
-                },                                      \
-        }
-
-#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
 #define OMAP_I2C_MAX_CONTROLLERS 4
 static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
-static struct platform_device omap_i2c_devices[] = {
-        I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-};
 
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
 
-static int __init omap_i2c_nr_ports(void)
-{
-        int ports = 0;
-
-        if (cpu_class_is_omap1())
-                ports = 1;
-        else if (cpu_is_omap24xx())
-                ports = 2;
-        else if (cpu_is_omap34xx())
-                ports = 3;
-        else if (cpu_is_omap44xx())
-                ports = 4;
-
-        return ports;
-}
-
-static inline int omap1_i2c_add_bus(int bus_id)
-{
-        struct platform_device *pdev;
-        struct omap_i2c_bus_platform_data *pdata;
-        struct resource *res;
-
-        omap1_i2c_mux_pins(bus_id);
-
-        pdev = &omap_i2c_devices[bus_id - 1];
-        res = pdev->resource;
-        res[0].start = OMAP1_I2C_BASE;
-        res[0].end = res[0].start + OMAP_I2C_SIZE;
-        res[1].start = OMAP1_INT_I2C;
-        pdata = &i2c_pdata[bus_id - 1];
-
-        /* all OMAP1 have IP version 1 register set */
-        pdata->rev = OMAP_I2C_IP_VERSION_1;
-
-        /* all OMAP1 I2C are implemented like this */
-        pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
-                       OMAP_I2C_FLAG_SIMPLE_CLOCK |
-                       OMAP_I2C_FLAG_16BIT_DATA_REG |
-                       OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
-
-        /* how the cpu bus is wired up differs for 7xx only */
-
-        if (cpu_is_omap7xx())
-                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
-        else
-                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
-
-        return platform_device_register(pdev);
-}
-
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline int omap2_i2c_add_bus(int bus_id)
-{
-        int l;
-        struct omap_hwmod *oh;
-        struct platform_device *pdev;
-        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
-        struct omap_i2c_bus_platform_data *pdata;
-        struct omap_i2c_dev_attr *dev_attr;
-
-        omap2_i2c_mux_pins(bus_id);
-
-        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
-        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
-                "String buffer overflow in I2C%d device setup\n", bus_id);
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                        pr_err("Could not look up %s\n", oh_name);
-                        return -EEXIST;
-        }
-
-        pdata = &i2c_pdata[bus_id - 1];
-        /*
-         * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
-         * use, and functionality implementation flags, up to the OMAP I2C
-         * driver via platform data
-         */
-        pdata->rev = oh->class->rev;
-
-        dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
-        pdata->flags = dev_attr->flags;
-
-        pdev = omap_device_build(name, bus_id, oh, pdata,
-                        sizeof(struct omap_i2c_bus_platform_data),
-                        NULL, 0, 0);
-        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
-
-        return PTR_RET(pdev);
-}
-#else
-static inline int omap2_i2c_add_bus(int bus_id)
-{
-        return 0;
-}
-#endif
-
-static int __init omap_i2c_add_bus(int bus_id)
-{
-        if (cpu_class_is_omap1())
-                return omap1_i2c_add_bus(bus_id);
-        else
-                return omap2_i2c_add_bus(bus_id);
-}
-
 /**
  * omap_i2c_bus_setup - Process command line options for the I2C bus speed
  * @str: String of options
@@ -193,12 +51,11 @@ static int __init omap_i2c_add_bus(int bus_id)
  */
 static int __init omap_i2c_bus_setup(char *str)
 {
-        int ports;
         int ints[3];
 
-        ports = omap_i2c_nr_ports();
         get_options(str, 3, ints);
-        if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
+        if (ints[0] < 2 || ints[1] < 1 ||
+                        ints[1] > OMAP_I2C_MAX_CONTROLLERS)
                 return 0;
         i2c_pdata[ints[1] - 1].clkrate = ints[2];
         i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
@@ -218,7 +75,7 @@ static int __init omap_register_i2c_bus_cmdline(void)
         for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
                 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
                         i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
-                        err = omap_i2c_add_bus(i + 1);
+                        err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
                         if (err)
                                 goto out;
                 }
@@ -243,7 +100,7 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
 {
         int err;
 
-        BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
+        BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
 
         if (info) {
                 err = i2c_register_board_info(bus_id, info, len);
@@ -256,5 +113,5 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
 
         i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
 
-        return omap_i2c_add_bus(bus_id);
+        return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
 }
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
index 0a87b052f8f7..6f506ba9e453 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
@@ -1,5 +1,5 @@
 /*
- *  arch/arm/plat-omap/include/mach/dma.h
+ *  OMAP DMA handling defines and function
  *
  *  Copyright (C) 2003 Nokia Corporation
  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
@@ -23,187 +23,8 @@
 
 #include <linux/platform_device.h>
 
-/*
- * TODO: These dma channel defines should go away once all
- * the omap drivers hwmod adapted.
- */
-
-/* Move omap4 specific defines to dma-44xx.h */
-#include "dma-44xx.h"
-
 #define INT_DMA_LCD                     25
 
-/* DMA channels for omap1 */
-#define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCSI1_TX               1
-#define OMAP_DMA_MCSI1_RX               2
-#define OMAP_DMA_I2C_RX                 3
-#define OMAP_DMA_I2C_TX                 4
-#define OMAP_DMA_EXT_NDMA_REQ           5
-#define OMAP_DMA_EXT_NDMA_REQ2          6
-#define OMAP_DMA_UWIRE_TX               7
-#define OMAP_DMA_MCBSP1_TX              8
-#define OMAP_DMA_MCBSP1_RX              9
-#define OMAP_DMA_MCBSP3_TX              10
-#define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_UART1_TX               12
-#define OMAP_DMA_UART1_RX               13
-#define OMAP_DMA_UART2_TX               14
-#define OMAP_DMA_UART2_RX               15
-#define OMAP_DMA_MCBSP2_TX              16
-#define OMAP_DMA_MCBSP2_RX              17
-#define OMAP_DMA_UART3_TX               18
-#define OMAP_DMA_UART3_RX               19
-#define OMAP_DMA_CAMERA_IF_RX           20
-#define OMAP_DMA_MMC_TX                 21
-#define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_NAND                   23
-#define OMAP_DMA_IRQ_LCD_LINE           24
-#define OMAP_DMA_MEMORY_STICK           25
-#define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_RX1           27
-#define OMAP_DMA_USB_W2FC_RX2           28
-#define OMAP_DMA_USB_W2FC_TX0           29
-#define OMAP_DMA_USB_W2FC_TX1           30
-#define OMAP_DMA_USB_W2FC_TX2           31
-
-/* These are only for 1610 */
-#define OMAP_DMA_CRYPTO_DES_IN          32
-#define OMAP_DMA_SPI_TX                 33
-#define OMAP_DMA_SPI_RX                 34
-#define OMAP_DMA_CRYPTO_HASH            35
-#define OMAP_DMA_CCP_ATTN               36
-#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
-#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
-#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
-#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
-#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
-#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
-#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
-#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
-#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
-#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
-#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
-#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
-#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
-#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
-#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
-#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
-#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
-#define OMAP_DMA_MMC2_TX                54
-#define OMAP_DMA_MMC2_RX                55
-#define OMAP_DMA_CRYPTO_DES_OUT         56
-
-/* DMA channels for 24xx */
-#define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
-#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
-#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
-#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
-#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
-#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
-#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
-#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
-#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
-#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
-#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
-#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
-#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
-#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
-#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
-#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
-#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
-#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
-#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
-#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
-#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
-#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
-#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
-#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
-#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
-
-#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
-#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
-
-/* Only for AM35xx */
-#define AM35XX_DMA_UART4_TX             54
-#define AM35XX_DMA_UART4_RX             55
-
-/*----------------------------------------------------------------------------*/
-
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
@@ -309,10 +130,12 @@
 #define SRC_PORT                        BIT(0x7)
 #define DST_PORT                        BIT(0x8)
 #define SRC_INDEX                       BIT(0x9)
-#define DST_INDEX                       BIT(0xA)
-#define IS_BURST_ONLY4                  BIT(0xB)
-#define CLEAR_CSR_ON_READ               BIT(0xC)
-#define IS_WORD_16                      BIT(0xD)
+#define DST_INDEX                       BIT(0xa)
+#define IS_BURST_ONLY4                  BIT(0xb)
+#define CLEAR_CSR_ON_READ               BIT(0xc)
+#define IS_WORD_16                      BIT(0xd)
+#define ENABLE_16XX_MODE                BIT(0xe)
+#define HS_CHANNELS_RESERVED            BIT(0xf)
 
 /* Defines for DMA Capabilities */
 #define DMA_HAS_TRANSPARENT_CAPS        (0x1 << 18)
@@ -449,7 +272,15 @@ struct omap_system_dma_plat_info {
         u32 (*dma_read)(int reg, int lch);
 };
 
-extern void __init omap_init_consistent_dma_size(void);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+#define dma_omap2plus() 1
+#else
+#define dma_omap2plus() 0
+#endif
+#define dma_omap1()     (!dma_omap2plus())
+#define dma_omap15xx()  ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
+#define dma_omap16xx()  ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
+
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
                         void (*callback)(int lch, u16 ch_status, void *data),
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
deleted file mode 100644
index 025d85a3ee86..000000000000
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * clkdev <-> OMAP integration
- *
- * Russell King <linux@arm.linux.org.uk>
- *
- */
-
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
-
-#include <linux/clkdev.h>
-
-struct omap_clk {
-        u16                             cpu;
-        struct clk_lookup               lk;
-};
-
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-/* Platform flags for the clkdev-OMAP integration code */
-#define CK_310          (1 << 0)
-#define CK_7XX          (1 << 1)        /* 7xx, 850 */
-#define CK_1510         (1 << 2)
-#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
-#define CK_242X         (1 << 4)
-#define CK_243X         (1 << 5)        /* 243x, 253x */
-#define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
-#define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_AM35XX       (1 << 9)        /* Sitara AM35xx */
-#define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
-#define CK_443X         (1 << 11)
-#define CK_TI816X       (1 << 12)
-#define CK_446X         (1 << 13)
-#define CK_AM33XX       (1 << 14)       /* AM33xx specific clocks */
-#define CK_1710         (1 << 15)       /* 1710 extra for rate selection */
-
-
-#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
-
-
-#endif
-
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
deleted file mode 100644
index e2e2d045e428..000000000000
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * OMAP clock: data structure definitions, function prototypes, shared macros
- *
- * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_CLOCK_H
-#define __ARCH_ARM_OMAP_CLOCK_H
-
-#include <linux/list.h>
-
-struct module;
-struct clk;
-struct clockdomain;
-
-/* Temporary, needed during the common clock framework conversion */
-#define __clk_get_name(clk)     (clk->name)
-#define __clk_get_parent(clk)   (clk->parent)
-#define __clk_get_rate(clk)     (clk->rate)
-
-/**
- * struct clkops - some clock function pointers
- * @enable: fn ptr that enables the current clock in hardware
- * @disable: fn ptr that enables the current clock in hardware
- * @find_idlest: function returning the IDLEST register for the clock's IP blk
- * @find_companion: function returning the "companion" clk reg for the clock
- * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
- * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
- *
- * A "companion" clk is an accompanying clock to the one being queried
- * that must be enabled for the IP module connected to the clock to
- * become accessible by the hardware.  Neither @find_idlest nor
- * @find_companion should be needed; that information is IP
- * block-specific; the hwmod code has been created to handle this, but
- * until hwmod data is ready and drivers have been converted to use PM
- * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
- * @find_companion must, unfortunately, remain.
- */
-struct clkops {
-        int                     (*enable)(struct clk *);
-        void                    (*disable)(struct clk *);
-        void                    (*find_idlest)(struct clk *, void __iomem **,
-                                               u8 *, u8 *);
-        void                    (*find_companion)(struct clk *, void __iomem **,
-                                                  u8 *);
-        void                    (*allow_idle)(struct clk *);
-        void                    (*deny_idle)(struct clk *);
-};
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-
-/* struct clksel_rate.flags possibilities */
-#define RATE_IN_242X            (1 << 0)
-#define RATE_IN_243X            (1 << 1)
-#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
-#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
-#define RATE_IN_36XX            (1 << 4)
-#define RATE_IN_4430            (1 << 5)
-#define RATE_IN_TI816X          (1 << 6)
-#define RATE_IN_4460            (1 << 7)
-#define RATE_IN_AM33XX          (1 << 8)
-#define RATE_IN_TI814X          (1 << 9)
-
-#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
-#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
-#define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
-
-/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
-#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
-
-
-/**
- * struct clksel_rate - register bitfield values corresponding to clk divisors
- * @val: register bitfield value (shifted to bit 0)
- * @div: clock divisor corresponding to @val
- * @flags: (see "struct clksel_rate.flags possibilities" above)
- *
- * @val should match the value of a read from struct clk.clksel_reg
- * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
- *
- * @div is the divisor that should be applied to the parent clock's rate
- * to produce the current clock's rate.
- */
-struct clksel_rate {
-        u32                     val;
-        u8                      div;
-        u16                     flags;
-};
-
-/**
- * struct clksel - available parent clocks, and a pointer to their divisors
- * @parent: struct clk * to a possible parent clock
- * @rates: available divisors for this parent clock
- *
- * A struct clksel is always associated with one or more struct clks
- * and one or more struct clksel_rates.
- */
-struct clksel {
-        struct clk               *parent;
-        const struct clksel_rate *rates;
-};
-
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        struct clk              *clk_bypass;
-        struct clk              *clk_ref;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        unsigned long           last_rounded_rate;
-        u16                     last_rounded_m;
-        u16                     max_multiplier;
-        u8                      last_rounded_n;
-        u8                      min_divider;
-        u16                     max_divider;
-        u8                      modes;
-        void __iomem            *autoidle_reg;
-        void __iomem            *idlest_reg;
-        u32                     autoidle_mask;
-        u32                     freqsel_mask;
-        u32                     idlest_mask;
-        u32                     dco_mask;
-        u32                     sddiv_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-        u8                      flags;
-};
-
-#endif
-
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- *     bits share the same register.  This flag allows the
- *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- *     should be used.  This is a temporary solution - a better approach
- *     would be to associate clock type-specific data with the clock,
- *     similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 1)
-#define CLOCK_NO_IDLE_PARENT    (1 << 2)
-#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2          (1 << 5)
-
-/**
- * struct clk - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @ops: struct clkops * for this clock
- * @name: the name of the clock in the hardware (used in hwmod data and debug)
- * @parent: pointer to this clock's parent struct clk
- * @children: list_head connecting to the child clks' @sibling list_heads
- * @sibling: list_head connecting this clk to its parent clk's @children
- * @rate: current clock rate
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @recalc: fn ptr that returns the clock's current rate
- * @set_rate: fn ptr that can change the clock's current rate
- * @round_rate: fn ptr that can round the clock's current rate
- * @init: fn ptr to do clock-specific initialization
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @usecount: number of users that have requested this clock to be enabled
- * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- * XXX @usecount is poorly named.  It should be "enable_count" or
- * something similar.  "users" in the description refers to kernel
- * code (core code or drivers) that have called clk_enable() and not
- * yet called clk_disable(); the usecount of parent clocks is also
- * incremented by the clock code when clk_enable() is called on child
- * clocks and decremented by the clock code when clk_disable() is
- * called on child clocks.
- *
- * XXX @clkdm, @usecount, @children, @sibling should be marked for
- * internal use only.
- *
- * @children and @sibling are used to optimize parent-to-child clock
- * tree traversals.  (child-to-parent traversals use @parent.)
- *
- * XXX The notion of the clock's current rate probably needs to be
- * separated from the clock's target rate.
- */
-struct clk {
-        struct list_head        node;
-        const struct clkops     *ops;
-        const char              *name;
-        struct clk              *parent;
-        struct list_head        children;
-        struct list_head        sibling;        /* node for children */
-        unsigned long           rate;
-        void __iomem            *enable_reg;
-        unsigned long           (*recalc)(struct clk *);
-        int                     (*set_rate)(struct clk *, unsigned long);
-        long                    (*round_rate)(struct clk *, unsigned long);
-        void                    (*init)(struct clk *);
-        u8                      enable_bit;
-        s8                      usecount;
-        u8                      fixed_div;
-        u8                      flags;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-        const char              *clkdm_name;
-        struct clockdomain      *clkdm;
-#else
-        u8                      rate_offset;
-        u8                      src_offset;
-#endif
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;  /* For visible tree hierarchy */
-#endif
-};
-
-struct clk_functions {
-        int             (*clk_enable)(struct clk *clk);
-        void            (*clk_disable)(struct clk *clk);
-        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-        void            (*clk_allow_idle)(struct clk *clk);
-        void            (*clk_deny_idle)(struct clk *clk);
-        void            (*clk_disable_unused)(struct clk *clk);
-};
-
-extern int mpurate;
-
-extern int clk_init(struct clk_functions *custom_clocks);
-extern void clk_preinit(struct clk *clk);
-extern int clk_register(struct clk *clk);
-extern void clk_reparent(struct clk *child, struct clk *parent);
-extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
-extern void recalculate_root_clocks(void);
-extern unsigned long followparent_recalc(struct clk *clk);
-extern void clk_enable_init_clocks(void);
-unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-extern struct clk *omap_clk_get_by_name(const char *name);
-extern int omap_clk_enable_autoidle_all(void);
-extern int omap_clk_disable_autoidle_all(void);
-
-extern const struct clkops clkops_null;
-
-extern struct clk dummy_ck;
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
deleted file mode 100644
index d1cb6f527b7e..000000000000
--- a/arch/arm/plat-omap/include/plat/common.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/common.h
- *
- * Header for code common to all OMAP machines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
-#define __ARCH_ARM_MACH_OMAP_COMMON_H
-
-#include <plat/i2c.h>
-#include <plat/omap_hwmod.h>
-
-extern int __init omap_init_clocksource_32k(void __iomem *vbase);
-
-extern void __init omap_check_revision(void);
-
-extern void omap_reserve(void);
-extern int omap_dss_reset(struct omap_hwmod *);
-
-void omap_sram_init(void);
-
-#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/counter-32k.h b/arch/arm/plat-omap/include/plat/counter-32k.h
new file mode 100644
index 000000000000..da000d482ff2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/counter-32k.h
@@ -0,0 +1 @@
+int omap_init_clocksource_32k(void __iomem *vbase);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67da857783ce..b4516aba67ed 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/cpu.h
- *
  * OMAP cpu type detection
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
@@ -30,470 +28,12 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
-#ifndef __ASSEMBLY__
-
-#include <linux/bitops.h>
-#include <plat/multi.h>
-
-/*
- * Omap device type i.e. EMU/HS/TST/GP/BAD
- */
-#define OMAP2_DEVICE_TYPE_TEST          0
-#define OMAP2_DEVICE_TYPE_EMU           1
-#define OMAP2_DEVICE_TYPE_SEC           2
-#define OMAP2_DEVICE_TYPE_GP            3
-#define OMAP2_DEVICE_TYPE_BAD           4
-
-int omap_type(void);
-
-/*
- * omap_rev bits:
- * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
- * CPU revision (See _REV_ defined in cpu.h)    [15:08]
- * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
- */
-unsigned int omap_rev(void);
-
-/*
- * Get the CPU revision for OMAP devices
- */
-#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
-
-/*
- * Macros to group OMAP into cpu classes.
- * These can be used in most places.
- * cpu_is_omap7xx():    True for OMAP730, OMAP850
- * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
- * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
- * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
- * cpu_is_omap243x():   True for OMAP2430
- * cpu_is_omap343x():   True for OMAP3430
- * cpu_is_omap443x():   True for OMAP4430
- * cpu_is_omap446x():   True for OMAP4460
- * cpu_is_omap447x():   True for OMAP4470
- * soc_is_omap543x():   True for OMAP5430, OMAP5432
- */
-#define GET_OMAP_CLASS  (omap_rev() & 0xff)
-
-#define IS_OMAP_CLASS(class, id)                        \
-static inline int is_omap ##class (void)                \
-{                                                       \
-        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
-}
-
-#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
-
-#define IS_AM_CLASS(class, id)                          \
-static inline int is_am ##class (void)                  \
-{                                                       \
-        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
-}
-
-#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
-
-#define IS_TI_CLASS(class, id)                  \
-static inline int is_ti ##class (void)          \
-{                                                       \
-        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
-}
-
-#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
-
-#define IS_OMAP_SUBCLASS(subclass, id)                  \
-static inline int is_omap ##subclass (void)             \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-
-#define IS_TI_SUBCLASS(subclass, id)                    \
-static inline int is_ti ##subclass (void)               \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-
-#define IS_AM_SUBCLASS(subclass, id)                    \
-static inline int is_am ##subclass (void)               \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-
-IS_OMAP_CLASS(7xx, 0x07)
-IS_OMAP_CLASS(15xx, 0x15)
-IS_OMAP_CLASS(16xx, 0x16)
-IS_OMAP_CLASS(24xx, 0x24)
-IS_OMAP_CLASS(34xx, 0x34)
-IS_OMAP_CLASS(44xx, 0x44)
-IS_AM_CLASS(35xx, 0x35)
-IS_OMAP_CLASS(54xx, 0x54)
-IS_AM_CLASS(33xx, 0x33)
-
-IS_TI_CLASS(81xx, 0x81)
-
-IS_OMAP_SUBCLASS(242x, 0x242)
-IS_OMAP_SUBCLASS(243x, 0x243)
-IS_OMAP_SUBCLASS(343x, 0x343)
-IS_OMAP_SUBCLASS(363x, 0x363)
-IS_OMAP_SUBCLASS(443x, 0x443)
-IS_OMAP_SUBCLASS(446x, 0x446)
-IS_OMAP_SUBCLASS(447x, 0x447)
-IS_OMAP_SUBCLASS(543x, 0x543)
-
-IS_TI_SUBCLASS(816x, 0x816)
-IS_TI_SUBCLASS(814x, 0x814)
-IS_AM_SUBCLASS(335x, 0x335)
-
-#define cpu_is_omap7xx()                0
-#define cpu_is_omap15xx()               0
-#define cpu_is_omap16xx()               0
-#define cpu_is_omap24xx()               0
-#define cpu_is_omap242x()               0
-#define cpu_is_omap243x()               0
-#define cpu_is_omap34xx()               0
-#define cpu_is_omap343x()               0
-#define cpu_is_ti81xx()                 0
-#define cpu_is_ti816x()                 0
-#define cpu_is_ti814x()                 0
-#define soc_is_am35xx()                 0
-#define soc_is_am33xx()                 0
-#define soc_is_am335x()                 0
-#define cpu_is_omap44xx()               0
-#define cpu_is_omap443x()               0
-#define cpu_is_omap446x()               0
-#define cpu_is_omap447x()               0
-#define soc_is_omap54xx()               0
-#define soc_is_omap543x()               0
-
-#if defined(MULTI_OMAP1)
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              is_omap7xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              is_omap7xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             is_omap15xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             is_omap16xx()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              1
-# endif
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              1
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             1
-# endif
-#endif
-
-#if defined(MULTI_OMAP2)
-# if defined(CONFIG_ARCH_OMAP2)
-#  undef  cpu_is_omap24xx
-#  define cpu_is_omap24xx()             is_omap24xx()
-# endif
-# if defined (CONFIG_SOC_OMAP2420)
-#  undef  cpu_is_omap242x
-#  define cpu_is_omap242x()             is_omap242x()
-# endif
-# if defined (CONFIG_SOC_OMAP2430)
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap243x()             is_omap243x()
-# endif
-# if defined(CONFIG_ARCH_OMAP3)
-#  undef  cpu_is_omap34xx
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap34xx()             is_omap34xx()
-#  define cpu_is_omap343x()             is_omap343x()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP2)
-#  undef  cpu_is_omap24xx
-#  define cpu_is_omap24xx()             1
-# endif
-# if defined(CONFIG_SOC_OMAP2420)
-#  undef  cpu_is_omap242x
-#  define cpu_is_omap242x()             1
-# endif
-# if defined(CONFIG_SOC_OMAP2430)
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap243x()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP3)
-#  undef  cpu_is_omap34xx
-#  define cpu_is_omap34xx()             1
-# endif
-# if defined(CONFIG_SOC_OMAP3430)
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap343x()             1
-# endif
-#endif
-
-/*
- * Macros to detect individual cpu types.
- * These are only rarely needed.
- * cpu_is_omap310():    True for OMAP310
- * cpu_is_omap1510():   True for OMAP1510
- * cpu_is_omap1610():   True for OMAP1610
- * cpu_is_omap1611():   True for OMAP1611
- * cpu_is_omap5912():   True for OMAP5912
- * cpu_is_omap1621():   True for OMAP1621
- * cpu_is_omap1710():   True for OMAP1710
- * cpu_is_omap2420():   True for OMAP2420
- * cpu_is_omap2422():   True for OMAP2422
- * cpu_is_omap2423():   True for OMAP2423
- * cpu_is_omap2430():   True for OMAP2430
- * cpu_is_omap3430():   True for OMAP3430
- */
-#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
-
-#define IS_OMAP_TYPE(type, id)                          \
-static inline int is_omap ##type (void)                 \
-{                                                       \
-        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
-}
-
-IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(1510, 0x1510)
-IS_OMAP_TYPE(1610, 0x1610)
-IS_OMAP_TYPE(1611, 0x1611)
-IS_OMAP_TYPE(5912, 0x1611)
-IS_OMAP_TYPE(1621, 0x1621)
-IS_OMAP_TYPE(1710, 0x1710)
-IS_OMAP_TYPE(2420, 0x2420)
-IS_OMAP_TYPE(2422, 0x2422)
-IS_OMAP_TYPE(2423, 0x2423)
-IS_OMAP_TYPE(2430, 0x2430)
-IS_OMAP_TYPE(3430, 0x3430)
-
-#define cpu_is_omap310()                0
-#define cpu_is_omap1510()               0
-#define cpu_is_omap1610()               0
-#define cpu_is_omap5912()               0
-#define cpu_is_omap1611()               0
-#define cpu_is_omap1621()               0
-#define cpu_is_omap1710()               0
-#define cpu_is_omap2420()               0
-#define cpu_is_omap2422()               0
-#define cpu_is_omap2423()               0
-#define cpu_is_omap2430()               0
-#define cpu_is_omap3430()               0
-#define cpu_is_omap3630()               0
-#define soc_is_omap5430()               0
-
-/*
- * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 310 vs. 1510 and 1611B/5912 vs. 1710.
- */
-
-#if defined(CONFIG_ARCH_OMAP15XX)
-# undef  cpu_is_omap310
-# undef  cpu_is_omap1510
-# define cpu_is_omap310()               is_omap310()
-# define cpu_is_omap1510()              is_omap1510()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-# undef  cpu_is_omap1610
-# undef  cpu_is_omap1611
-# undef  cpu_is_omap5912
-# undef  cpu_is_omap1621
-# undef  cpu_is_omap1710
-# define cpu_is_omap1610()              is_omap1610()
-# define cpu_is_omap1611()              is_omap1611()
-# define cpu_is_omap5912()              is_omap5912()
-# define cpu_is_omap1621()              is_omap1621()
-# define cpu_is_omap1710()              is_omap1710()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2)
-# undef  cpu_is_omap2420
-# undef  cpu_is_omap2422
-# undef  cpu_is_omap2423
-# undef  cpu_is_omap2430
-# define cpu_is_omap2420()              is_omap2420()
-# define cpu_is_omap2422()              is_omap2422()
-# define cpu_is_omap2423()              is_omap2423()
-# define cpu_is_omap2430()              is_omap2430()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3)
-# undef cpu_is_omap3430
-# undef cpu_is_ti81xx
-# undef cpu_is_ti816x
-# undef cpu_is_ti814x
-# undef soc_is_am35xx
-# define cpu_is_omap3430()              is_omap3430()
-# undef cpu_is_omap3630
-# define cpu_is_omap3630()              is_omap363x()
-# define cpu_is_ti81xx()                is_ti81xx()
-# define cpu_is_ti816x()                is_ti816x()
-# define cpu_is_ti814x()                is_ti814x()
-# define soc_is_am35xx()                is_am35xx()
+#ifdef CONFIG_ARCH_OMAP1
+#include <mach/soc.h>
 #endif
 
-# if defined(CONFIG_SOC_AM33XX)
-# undef soc_is_am33xx
-# undef soc_is_am335x
-# define soc_is_am33xx()                is_am33xx()
-# define soc_is_am335x()                is_am335x()
+#ifdef CONFIG_ARCH_OMAP2PLUS
+#include "../../mach-omap2/soc.h"
 #endif
 
-# if defined(CONFIG_ARCH_OMAP4)
-# undef cpu_is_omap44xx
-# undef cpu_is_omap443x
-# undef cpu_is_omap446x
-# undef cpu_is_omap447x
-# define cpu_is_omap44xx()              is_omap44xx()
-# define cpu_is_omap443x()              is_omap443x()
-# define cpu_is_omap446x()              is_omap446x()
-# define cpu_is_omap447x()              is_omap447x()
-# endif
-
-# if defined(CONFIG_SOC_OMAP5)
-# undef soc_is_omap54xx
-# undef soc_is_omap543x
-# define soc_is_omap54xx()              is_omap54xx()
-# define soc_is_omap543x()              is_omap543x()
-#endif
-
-/* Macros to detect if we have OMAP1 or OMAP2 */
-#define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
-                                cpu_is_omap16xx())
-#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
-                                cpu_is_omap44xx() || soc_is_omap54xx() || \
-                                soc_is_am33xx())
-
-/* Various silicon revisions for omap2 */
-#define OMAP242X_CLASS          0x24200024
-#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
-
-#define OMAP243X_CLASS          0x24300024
-#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
-
-#define OMAP343X_CLASS          0x34300034
-#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
-
-#define OMAP363X_CLASS          0x36300034
-#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
-
-#define TI816X_CLASS            0x81600034
-#define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
-
-#define TI814X_CLASS            0x81400034
-#define TI8148_REV_ES1_0        TI814X_CLASS
-#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
-#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
-
-#define AM35XX_CLASS            0x35170034
-#define AM35XX_REV_ES1_0        AM35XX_CLASS
-#define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
-
-#define AM335X_CLASS            0x33500033
-#define AM335X_REV_ES1_0        AM335X_CLASS
-
-#define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
-#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
-#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
-#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
-#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
-
-#define OMAP446X_CLASS          0x44600044
-#define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
-#define OMAP4460_REV_ES1_1      (OMAP446X_CLASS | (0x11 << 8))
-
-#define OMAP447X_CLASS          0x44700044
-#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
-
-#define OMAP54XX_CLASS          0x54000054
-#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
-#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
-
-void omap2xxx_check_revision(void);
-void omap3xxx_check_revision(void);
-void omap4xxx_check_revision(void);
-void omap5xxx_check_revision(void);
-void omap3xxx_check_features(void);
-void ti81xx_check_features(void);
-void omap4xxx_check_features(void);
-
-/*
- * Runtime detection of OMAP3 features
- *
- * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
- *    family have OS-level control over the I/O chain clock.  This is
- *    to avoid a window during which wakeups could potentially be lost
- *    during powerdomain transitions.  If this bit is set, it
- *    indicates that the chip does support OS-level control of this
- *    feature.
- */
-extern u32 omap_features;
-
-#define OMAP3_HAS_L2CACHE               BIT(0)
-#define OMAP3_HAS_IVA                   BIT(1)
-#define OMAP3_HAS_SGX                   BIT(2)
-#define OMAP3_HAS_NEON                  BIT(3)
-#define OMAP3_HAS_ISP                   BIT(4)
-#define OMAP3_HAS_192MHZ_CLK            BIT(5)
-#define OMAP3_HAS_IO_WAKEUP             BIT(6)
-#define OMAP3_HAS_SDRC                  BIT(7)
-#define OMAP3_HAS_IO_CHAIN_CTRL         BIT(8)
-#define OMAP4_HAS_MPU_1GHZ              BIT(9)
-#define OMAP4_HAS_MPU_1_2GHZ            BIT(10)
-#define OMAP4_HAS_MPU_1_5GHZ            BIT(11)
-
-
-#define OMAP3_HAS_FEATURE(feat,flag)                    \
-static inline unsigned int omap3_has_ ##feat(void)      \
-{                                                       \
-        return omap_features & OMAP3_HAS_ ##flag;       \
-}                                                       \
-
-OMAP3_HAS_FEATURE(l2cache, L2CACHE)
-OMAP3_HAS_FEATURE(sgx, SGX)
-OMAP3_HAS_FEATURE(iva, IVA)
-OMAP3_HAS_FEATURE(neon, NEON)
-OMAP3_HAS_FEATURE(isp, ISP)
-OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
-OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
-OMAP3_HAS_FEATURE(sdrc, SDRC)
-OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
-
-/*
- * Runtime detection of OMAP4 features
- */
-#define OMAP4_HAS_FEATURE(feat, flag)                   \
-static inline unsigned int omap4_has_ ##feat(void)      \
-{                                                       \
-        return omap_features & OMAP4_HAS_ ##flag;       \
-}                                                       \
-
-OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
-OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
-OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
-
-#endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
index a4edbd2f7484..8fc4287222dd 100644
--- a/arch/arm/mach-omap2/debug-devices.h
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -1,9 +1,2 @@
-#ifndef _OMAP_DEBUG_DEVICES_H
-#define _OMAP_DEBUG_DEVICES_H
-
-#include <linux/types.h>
-
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
deleted file mode 100644
index 1f767cb2f38a..000000000000
--- a/arch/arm/plat-omap/include/plat/dma-44xx.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * OMAP4 SDMA channel definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Paul Walmsley (paul@pwsan.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
-
-#define OMAP44XX_DMA_SYS_REQ0                   2
-#define OMAP44XX_DMA_SYS_REQ1                   3
-#define OMAP44XX_DMA_GPMC                       4
-#define OMAP44XX_DMA_DSS_DISPC_REQ              6
-#define OMAP44XX_DMA_SYS_REQ2                   7
-#define OMAP44XX_DMA_MCASP1_AXEVT               8
-#define OMAP44XX_DMA_ISS_REQ1                   9
-#define OMAP44XX_DMA_ISS_REQ2                   10
-#define OMAP44XX_DMA_MCASP1_AREVT               11
-#define OMAP44XX_DMA_ISS_REQ3                   12
-#define OMAP44XX_DMA_ISS_REQ4                   13
-#define OMAP44XX_DMA_DSS_RFBI_REQ               14
-#define OMAP44XX_DMA_SPI3_TX0                   15
-#define OMAP44XX_DMA_SPI3_RX0                   16
-#define OMAP44XX_DMA_MCBSP2_TX                  17
-#define OMAP44XX_DMA_MCBSP2_RX                  18
-#define OMAP44XX_DMA_MCBSP3_TX                  19
-#define OMAP44XX_DMA_MCBSP3_RX                  20
-#define OMAP44XX_DMA_C2C_SSCM_GPO0              21
-#define OMAP44XX_DMA_C2C_SSCM_GPO1              22
-#define OMAP44XX_DMA_SPI3_TX1                   23
-#define OMAP44XX_DMA_SPI3_RX1                   24
-#define OMAP44XX_DMA_I2C3_TX                    25
-#define OMAP44XX_DMA_I2C3_RX                    26
-#define OMAP44XX_DMA_I2C1_TX                    27
-#define OMAP44XX_DMA_I2C1_RX                    28
-#define OMAP44XX_DMA_I2C2_TX                    29
-#define OMAP44XX_DMA_I2C2_RX                    30
-#define OMAP44XX_DMA_MCBSP4_TX                  31
-#define OMAP44XX_DMA_MCBSP4_RX                  32
-#define OMAP44XX_DMA_MCBSP1_TX                  33
-#define OMAP44XX_DMA_MCBSP1_RX                  34
-#define OMAP44XX_DMA_SPI1_TX0                   35
-#define OMAP44XX_DMA_SPI1_RX0                   36
-#define OMAP44XX_DMA_SPI1_TX1                   37
-#define OMAP44XX_DMA_SPI1_RX1                   38
-#define OMAP44XX_DMA_SPI1_TX2                   39
-#define OMAP44XX_DMA_SPI1_RX2                   40
-#define OMAP44XX_DMA_SPI1_TX3                   41
-#define OMAP44XX_DMA_SPI1_RX3                   42
-#define OMAP44XX_DMA_SPI2_TX0                   43
-#define OMAP44XX_DMA_SPI2_RX0                   44
-#define OMAP44XX_DMA_SPI2_TX1                   45
-#define OMAP44XX_DMA_SPI2_RX1                   46
-#define OMAP44XX_DMA_MMC2_TX                    47
-#define OMAP44XX_DMA_MMC2_RX                    48
-#define OMAP44XX_DMA_UART1_TX                   49
-#define OMAP44XX_DMA_UART1_RX                   50
-#define OMAP44XX_DMA_UART2_TX                   51
-#define OMAP44XX_DMA_UART2_RX                   52
-#define OMAP44XX_DMA_UART3_TX                   53
-#define OMAP44XX_DMA_UART3_RX                   54
-#define OMAP44XX_DMA_UART4_TX                   55
-#define OMAP44XX_DMA_UART4_RX                   56
-#define OMAP44XX_DMA_MMC4_TX                    57
-#define OMAP44XX_DMA_MMC4_RX                    58
-#define OMAP44XX_DMA_MMC5_TX                    59
-#define OMAP44XX_DMA_MMC5_RX                    60
-#define OMAP44XX_DMA_MMC1_TX                    61
-#define OMAP44XX_DMA_MMC1_RX                    62
-#define OMAP44XX_DMA_SYS_REQ3                   64
-#define OMAP44XX_DMA_MCPDM_UP                   65
-#define OMAP44XX_DMA_MCPDM_DL                   66
-#define OMAP44XX_DMA_DMIC_REQ                   67
-#define OMAP44XX_DMA_C2C_SSCM_GPO2              68
-#define OMAP44XX_DMA_C2C_SSCM_GPO3              69
-#define OMAP44XX_DMA_SPI4_TX0                   70
-#define OMAP44XX_DMA_SPI4_RX0                   71
-#define OMAP44XX_DMA_DSS_DSI1_REQ0              72
-#define OMAP44XX_DMA_DSS_DSI1_REQ1              73
-#define OMAP44XX_DMA_DSS_DSI1_REQ2              74
-#define OMAP44XX_DMA_DSS_DSI1_REQ3              75
-#define OMAP44XX_DMA_DSS_HDMI_REQ               76
-#define OMAP44XX_DMA_MMC3_TX                    77
-#define OMAP44XX_DMA_MMC3_RX                    78
-#define OMAP44XX_DMA_USIM_TX                    79
-#define OMAP44XX_DMA_USIM_RX                    80
-#define OMAP44XX_DMA_DSS_DSI2_REQ0              81
-#define OMAP44XX_DMA_DSS_DSI2_REQ1              82
-#define OMAP44XX_DMA_DSS_DSI2_REQ2              83
-#define OMAP44XX_DMA_DSS_DSI2_REQ3              84
-#define OMAP44XX_DMA_SLIMBUS1_TX0               85
-#define OMAP44XX_DMA_SLIMBUS1_TX1               86
-#define OMAP44XX_DMA_SLIMBUS1_TX2               87
-#define OMAP44XX_DMA_SLIMBUS1_TX3               88
-#define OMAP44XX_DMA_SLIMBUS1_RX0               89
-#define OMAP44XX_DMA_SLIMBUS1_RX1               90
-#define OMAP44XX_DMA_SLIMBUS1_RX2               91
-#define OMAP44XX_DMA_SLIMBUS1_RX3               92
-#define OMAP44XX_DMA_SLIMBUS2_TX0               93
-#define OMAP44XX_DMA_SLIMBUS2_TX1               94
-#define OMAP44XX_DMA_SLIMBUS2_TX2               95
-#define OMAP44XX_DMA_SLIMBUS2_TX3               96
-#define OMAP44XX_DMA_SLIMBUS2_RX0               97
-#define OMAP44XX_DMA_SLIMBUS2_RX1               98
-#define OMAP44XX_DMA_SLIMBUS2_RX2               99
-#define OMAP44XX_DMA_SLIMBUS2_RX3               100
-#define OMAP44XX_DMA_ABE_REQ_0                  101
-#define OMAP44XX_DMA_ABE_REQ_1                  102
-#define OMAP44XX_DMA_ABE_REQ_2                  103
-#define OMAP44XX_DMA_ABE_REQ_3                  104
-#define OMAP44XX_DMA_ABE_REQ_4                  105
-#define OMAP44XX_DMA_ABE_REQ_5                  106
-#define OMAP44XX_DMA_ABE_REQ_6                  107
-#define OMAP44XX_DMA_ABE_REQ_7                  108
-#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ          109
-#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ         110
-#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ        111
-#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ          112
-#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ         113
-#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ        114
-#define OMAP44XX_DMA_DES_P_CTX_IN_REQ           115
-#define OMAP44XX_DMA_DES_P_DATA_IN_REQ          116
-#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ         117
-#define OMAP44XX_DMA_SHA2_CTXIN_P               118
-#define OMAP44XX_DMA_SHA2_DIN_P                 119
-#define OMAP44XX_DMA_SHA2_CTXOUT_P              120
-#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ     121
-#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ     122
-#define OMAP44XX_DMA_I2C4_TX                    124
-#define OMAP44XX_DMA_I2C4_RX                    125
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 85868e98c11c..3f5b9cfd9c0b 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -94,6 +94,7 @@ struct dmtimer_platform_data {
         /* set_timer_src - Only used for OMAP1 devices */
         int (*set_timer_src)(struct platform_device *pdev, int source);
         u32 timer_capability;
+        int (*get_context_loss_count)(struct device *);
 };
 
 int omap_dm_timer_reserve_systimer(int id);
@@ -263,6 +264,7 @@ struct omap_dm_timer {
         unsigned reserved:1;
         unsigned posted:1;
         struct timer_regs context;
+        int (*get_context_loss_count)(struct device *);
         int ctx_loss_count;
         int revision;
         u32 capability;
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
deleted file mode 100644
index bd3c6324ae1f..000000000000
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/fpga.h
- *
- * Interrupt handler for OMAP-1510 FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_FPGA_H
-#define __ASM_ARCH_OMAP_FPGA_H
-
-extern void omap1510_fpga_init_irq(void);
-
-#define fpga_read(reg)                  __raw_readb(reg)
-#define fpga_write(val, reg)            __raw_writeb(val, reg)
-
-/*
- * ---------------------------------------------------------------------------
- *  H2/P2 Debug board FPGA
- * ---------------------------------------------------------------------------
- */
-/* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
-#define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
-#define H2P2_DBG_FPGA_START             0x04000000              /* PA */
-
-#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
-
-/* NOTE:  most boards don't have a static mapping for the FPGA ... */
-struct h2p2_dbg_fpga {
-        /* offset 0x00 */
-        u16             smc91x[8];
-        /* offset 0x10 */
-        u16             fpga_rev;
-        u16             board_rev;
-        u16             gpio_outputs;
-        u16             leds;
-        /* offset 0x18 */
-        u16             misc_inputs;
-        u16             lan_status;
-        u16             lan_reset;
-        u16             reserved0;
-        /* offset 0x20 */
-        u16             ps2_data;
-        u16             ps2_ctrl;
-        /* plus also 4 rs232 ports ... */
-};
-
-/* LEDs definition on debug board (16 LEDs, all physically green) */
-#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
-#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
-#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
-#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
-/*  cpu0 load-meter LEDs */
-#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
-#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
-#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
-
-#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
-#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
-
-/*
- * ---------------------------------------------------------------------------
- *  OMAP-1510 FPGA
- * ---------------------------------------------------------------------------
- */
-#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
-#define OMAP1510_FPGA_SIZE              SZ_4K
-#define OMAP1510_FPGA_START             0x08000000              /* PA */
-
-/* Revision */
-#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
-
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
-
-/* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
-
-/* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
-
-/* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
-
-#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
-
-/*
- * Power up Giga UART driver, turn on HID clock.
- * Turn off BT power, since we're not using it and it
- * draws power.
- */
-#define OMAP1510_FPGA_RESET_VALUE               0x42
-
-#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
-#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
-#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
-#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
-#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
-#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
-#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
-#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
-
-/*
- * Innovator/OMAP1510 FPGA HID register bit definitions
- */
-#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
-#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
-#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
-#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
-#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
-#define OMAP1510_FPGA_HID_rsrvd (1<<6)
-#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
-
-/* The FPGA IRQ is cascaded through GPIO_13 */
-#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
-
-/* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
-#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
-#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
-#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
-#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
-#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
-#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
-#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
-#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
-#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
-#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
-#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
-#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
-#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
-#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
-#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
-#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
-#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
-#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
-#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7c22b9e10dc3..7a9028cb5a75 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,11 +18,15 @@
  * 02110-1301 USA
  *
  */
-#ifndef __ASM__ARCH_OMAP_I2C_H
-#define __ASM__ARCH_OMAP_I2C_H
 
-#include <linux/i2c.h>
-#include <linux/i2c-omap.h>
+#ifndef __PLAT_OMAP_I2C_H
+#define __PLAT_OMAP_I2C_H
+
+struct i2c_board_info;
+struct omap_i2c_bus_platform_data;
+
+int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
+                        int bus_id);
 
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -37,23 +41,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
-/**
- * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
- * @fifo_depth: total controller FIFO size (in bytes)
- * @flags: differences in hardware support capability
- *
- * @fifo_depth represents what exists on the hardware, not what is
- * actually configured at runtime by the device driver.
- */
-struct omap_i2c_dev_attr {
-        u8      fifo_depth;
-        u32     flags;
-};
-
-void __init omap1_i2c_mux_pins(int bus_id);
-void __init omap2_i2c_mux_pins(int bus_id);
-
 struct omap_hwmod;
 int omap_i2c_reset(struct omap_hwmod *oh);
 
-#endif /* __ASM__ARCH_OMAP_I2C_H */
+#endif /* __PLAT_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/led.h b/arch/arm/plat-omap/include/plat/led.h
deleted file mode 100644
index 25e451e7e2fd..000000000000
--- a/arch/arm/plat-omap/include/plat/led.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/led.h
- *
- *  Copyright (C) 2006 Samsung Electronics
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_LED_H
-#define ASMARM_ARCH_LED_H
-
-struct omap_led_config {
-        struct led_classdev     cdev;
-        s16                     gpio;
-};
-
-struct omap_led_platform_data {
-        s16                     nr_leds;
-        struct omap_led_config  *leds;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
deleted file mode 100644
index 4a970ec62dd1..000000000000
--- a/arch/arm/plat-omap/include/plat/menelaus.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/menelaus.h
- *
- * Functions to access Menelaus power management chip
- */
-
-#ifndef __ASM_ARCH_MENELAUS_H
-#define __ASM_ARCH_MENELAUS_H
-
-struct device;
-
-struct menelaus_platform_data {
-        int (* late_init)(struct device *dev);
-};
-
-extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                          void *data);
-extern void menelaus_unregister_mmc_callback(void);
-extern int menelaus_set_mmc_opendrain(int slot, int enable);
-extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
-
-extern int menelaus_set_vmem(unsigned int mV);
-extern int menelaus_set_vio(unsigned int mV);
-extern int menelaus_set_vmmc(unsigned int mV);
-extern int menelaus_set_vaux(unsigned int mV);
-extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
-extern int menelaus_set_slot_sel(int enable);
-extern int menelaus_get_slot_pin_states(void);
-extern int menelaus_set_vcore_sw(unsigned int mV);
-extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
-
-#define EN_VPLL_SLEEP   (1 << 7)
-#define EN_VMMC_SLEEP   (1 << 6)
-#define EN_VAUX_SLEEP   (1 << 5)
-#define EN_VIO_SLEEP    (1 << 4)
-#define EN_VMEM_SLEEP   (1 << 3)
-#define EN_DC3_SLEEP    (1 << 2)
-#define EN_DC2_SLEEP    (1 << 1)
-#define EN_VC_SLEEP     (1 << 0)
-
-extern int menelaus_set_regulator_sleep(int enable, u32 val);
-
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
-#define omap_has_menelaus()     1
-#else
-#define omap_has_menelaus()     0
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
deleted file mode 100644
index 8b4e4f2da2f5..000000000000
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * MMC definitions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP2_MMC_H
-#define __OMAP2_MMC_H
-
-#include <linux/types.h>
-#include <linux/device.h>
-#include <linux/mmc/host.h>
-
-#include <plat/omap_hwmod.h>
-
-#define OMAP15XX_NR_MMC         1
-#define OMAP16XX_NR_MMC         2
-#define OMAP1_MMC_SIZE          0x080
-#define OMAP1_MMC1_BASE         0xfffb7800
-#define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
-
-#define OMAP24XX_NR_MMC         2
-#define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
-#define OMAP2_MMC1_BASE         0x4809c000
-
-#define OMAP4_MMC_REG_OFFSET    0x100
-
-#define OMAP_MMC_MAX_SLOTS      2
-
-/*
- * struct omap_mmc_dev_attr.flags possibilities
- *
- * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
- *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
- *    should be set if this is the case.  See for example Section 22.5.3
- *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
- *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
- *
- * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
- *    don't work correctly on some MMC controller instances on some
- *    OMAP3 SoCs; this flag should be set if this is the case.  See
- *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
- *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
- *    Revision F (October 2010) (SPRZ278F).
- */
-#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
-#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ       BIT(1)
-
-struct omap_mmc_dev_attr {
-        u8 flags;
-};
-
-struct omap_mmc_platform_data {
-        /* back-link to device */
-        struct device *dev;
-
-        /* number of slots per controller */
-        unsigned nr_slots:2;
-
-        /* set if your board has components or wiring that limits the
-         * maximum frequency on the MMC bus */
-        unsigned int max_freq;
-
-        /* switch the bus to a new slot */
-        int (*switch_slot)(struct device *dev, int slot);
-        /* initialize board-specific MMC functionality, can be NULL if
-         * not supported */
-        int (*init)(struct device *dev);
-        void (*cleanup)(struct device *dev);
-        void (*shutdown)(struct device *dev);
-
-        /* To handle board related suspend/resume functionality for MMC */
-        int (*suspend)(struct device *dev, int slot);
-        int (*resume)(struct device *dev, int slot);
-
-        /* Return context loss count due to PM states changing */
-        int (*get_context_loss_count)(struct device *dev);
-
-        /* Integrating attributes from the omap_hwmod layer */
-        u8 controller_flags;
-
-        /* Register offset deviation */
-        u16 reg_offset;
-
-        struct omap_mmc_slot_data {
-
-                /*
-                 * 4/8 wires and any additional host capabilities
-                 * need to OR'd all capabilities (ref. linux/mmc/host.h)
-                 */
-                u8  wires;      /* Used for the MMC driver on omap1 and 2420 */
-                u32 caps;       /* Used for the MMC driver on 2430 and later */
-                u32 pm_caps;    /* PM capabilities of the mmc */
-
-                /*
-                 * nomux means "standard" muxing is wrong on this board, and
-                 * that board-specific code handled it before common init logic.
-                 */
-                unsigned nomux:1;
-
-                /* switch pin can be for card detect (default) or card cover */
-                unsigned cover:1;
-
-                /* use the internal clock */
-                unsigned internal_clock:1;
-
-                /* nonremovable e.g. eMMC */
-                unsigned nonremovable:1;
-
-                /* Try to sleep or power off when possible */
-                unsigned power_saving:1;
-
-                /* If using power_saving and the MMC power is not to go off */
-                unsigned no_off:1;
-
-                /* eMMC does not handle power off when not in sleep state */
-                unsigned no_regulator_off_init:1;
-
-                /* Regulator off remapped to sleep */
-                unsigned vcc_aux_disable_is_sleep:1;
-
-                /* we can put the features above into this variable */
-#define HSMMC_HAS_PBIAS         (1 << 0)
-#define HSMMC_HAS_UPDATED_RESET (1 << 1)
-                unsigned features;
-
-                int switch_pin;                 /* gpio (card detect) */
-                int gpio_wp;                    /* gpio (write protect) */
-
-                int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
-                int (*set_power)(struct device *dev, int slot,
-                                 int power_on, int vdd);
-                int (*get_ro)(struct device *dev, int slot);
-                void (*remux)(struct device *dev, int slot, int power_on);
-                /* Call back before enabling / disabling regulators */
-                void (*before_set_reg)(struct device *dev, int slot,
-                                       int power_on, int vdd);
-                /* Call back after enabling / disabling regulators */
-                void (*after_set_reg)(struct device *dev, int slot,
-                                      int power_on, int vdd);
-                /* if we have special card, init it using this callback */
-                void (*init_card)(struct mmc_card *card);
-
-                /* return MMC cover switch state, can be NULL if not supported.
-                 *
-                 * possible return values:
-                 *   0 - closed
-                 *   1 - open
-                 */
-                int (*get_cover_state)(struct device *dev, int slot);
-
-                const char *name;
-                u32 ocr_mask;
-
-                /* Card detection IRQs */
-                int card_detect_irq;
-                int (*card_detect)(struct device *dev, int slot);
-
-                unsigned int ban_openended:1;
-
-        } slots[OMAP_MMC_MAX_SLOTS];
-};
-
-/* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
-                                        int is_closed);
-
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
-void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers);
-void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
-#else
-static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers)
-{
-}
-static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-{
-}
-#endif
-
-extern int omap_msdi_reset(struct omap_hwmod *oh);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
deleted file mode 100644
index 324d31b14852..000000000000
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Support for compiling in multiple OMAP processors
- *
- * Copyright (C) 2010 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __PLAT_OMAP_MULTI_H
-#define __PLAT_OMAP_MULTI_H
-
-/*
- * Test if multicore OMAP support is needed
- */
-#undef MULTI_OMAP1
-#undef MULTI_OMAP2
-#undef OMAP_NAME
-
-#ifdef CONFIG_ARCH_OMAP730
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap730
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap850
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap1510
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap16xx
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
-# endif
-#endif
-#ifdef CONFIG_SOC_OMAP2420
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2420
-# endif
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2430
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap3
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap4
-# endif
-#endif
-
-#ifdef CONFIG_SOC_OMAP5
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap5
-# endif
-#endif
-
-#ifdef CONFIG_SOC_AM33XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME am33xx
-# endif
-#endif
-
-#endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
deleted file mode 100644
index 0e4acd2d2deb..000000000000
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __OMAP_SECURE_H__
-#define __OMAP_SECURE_H__
-
-#include <linux/types.h>
-
-extern int omap_secure_ram_reserve_memblock(void);
-
-#ifdef CONFIG_OMAP4_ERRATA_I688
-extern int omap_barrier_reserve_memblock(void);
-#else
-static inline void omap_barrier_reserve_memblock(void)
-{ }
-#endif
-#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
deleted file mode 100644
index 36d6a7666216..000000000000
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef ____ASM_ARCH_SDRC_H
-#define ____ASM_ARCH_SDRC_H
-
-/*
- * OMAP2/3 SDRC/SMS register definitions
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Tony Lindgren
- * Paul Walmsley
- * Richard Woodruff
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
-
-#define SDRC_SYSCONFIG          0x010
-#define SDRC_CS_CFG             0x040
-#define SDRC_SHARING            0x044
-#define SDRC_ERR_TYPE           0x04C
-#define SDRC_DLLA_CTRL          0x060
-#define SDRC_DLLA_STATUS        0x064
-#define SDRC_DLLB_CTRL          0x068
-#define SDRC_DLLB_STATUS        0x06C
-#define SDRC_POWER              0x070
-#define SDRC_MCFG_0             0x080
-#define SDRC_MR_0               0x084
-#define SDRC_EMR2_0             0x08c
-#define SDRC_ACTIM_CTRL_A_0     0x09c
-#define SDRC_ACTIM_CTRL_B_0     0x0a0
-#define SDRC_RFR_CTRL_0         0x0a4
-#define SDRC_MANUAL_0           0x0a8
-#define SDRC_MCFG_1             0x0B0
-#define SDRC_MR_1               0x0B4
-#define SDRC_EMR2_1             0x0BC
-#define SDRC_ACTIM_CTRL_A_1     0x0C4
-#define SDRC_ACTIM_CTRL_B_1     0x0C8
-#define SDRC_RFR_CTRL_1         0x0D4
-#define SDRC_MANUAL_1           0x0D8
-
-#define SDRC_POWER_AUTOCOUNT_SHIFT      8
-#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
-#define SDRC_POWER_CLKCTRL_SHIFT        4
-#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
-#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
-
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
-
-
-/*
- * SMS register access
- */
-
-#define OMAP242X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-
-/* SMS register offsets - read/write with sms_{read,write}_reg() */
-
-#define SMS_SYSCONFIG                   0x010
-#define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
-#define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
-#define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
-/* REVISIT: fill in other SMS registers here */
-
-
-#ifndef __ASSEMBLER__
-
-/**
- * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
- * @rate: SDRC clock rate (in Hz)
- * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- * @mr: Value to program to SDRC_MR for this rate
- *
- * This structure holds a pre-computed set of register values for the
- * SDRC for a given SDRC clock rate and SDRAM chip.  These are
- * intended to be pre-computed and specified in an array in the board-*.c
- * files.  The structure is keyed off the 'rate' field.
- */
-struct omap_sdrc_params {
-        unsigned long rate;
-        u32 actim_ctrla;
-        u32 actim_ctrlb;
-        u32 rfr_ctrl;
-        u32 mr;
-};
-
-#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
-void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                            struct omap_sdrc_params *sdrc_cs1);
-#else
-static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                                          struct omap_sdrc_params *sdrc_cs1) {};
-#endif
-
-int omap2_sdrc_get_params(unsigned long r,
-                          struct omap_sdrc_params **sdrc_cs0,
-                          struct omap_sdrc_params **sdrc_cs1);
-void omap2_sms_save_context(void);
-void omap2_sms_restore_context(void);
-
-void omap2_sms_write_rot_control(u32 val, unsigned ctx);
-void omap2_sms_write_rot_size(u32 val, unsigned ctx);
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
-
-#ifdef CONFIG_ARCH_OMAP2
-
-struct memory_timings {
-        u32 m_type;             /* ddr = 1, sdr = 0 */
-        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
-        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
-        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
-        u32 base_cs;            /* base chip select to use for calculations */
-};
-
-extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
-
-u32 omap2xxx_sdrc_dll_is_unlocked(void);
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
-
-#endif  /* CONFIG_ARCH_OMAP2 */
-
-#endif  /* __ASSEMBLER__ */
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 227ae2657554..ba4525059a99 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -1,18 +1,8 @@
-/*
- * arch/arm/plat-omap/include/mach/sram.h
- *
- * Interface for functions that need to be run in internal SRAM
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+int omap_sram_init(void);
 
-#ifndef __ARCH_ARM_OMAP_SRAM_H
-#define __ARCH_ARM_OMAP_SRAM_H
-
-#ifndef __ASSEMBLY__
-#include <asm/fncpy.h>
+void omap_map_sram(unsigned long start, unsigned long size,
+                        unsigned long skip, int cached);
+void omap_sram_reset(void);
 
 extern void *omap_sram_push_address(unsigned long size);
 
@@ -24,82 +14,3 @@ extern void *omap_sram_push_address(unsigned long size);
                 _res = fncpy(_sram_address, &(funcp), size);    \
         _res;                                                   \
 })
-
-extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
-
-extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                u32 base_cs, u32 force_unlock);
-extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                      u32 mem_type);
-extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
-extern u32 omap3_configure_core_dpll(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-extern void omap3_sram_restore_context(void);
-
-/* Do not use these */
-extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap1_sram_reprogram_clock_sz;
-
-extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap24xx_sram_reprogram_clock_sz;
-
-extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap242x_sram_ddr_init_sz;
-
-extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap242x_sram_set_prcm_sz;
-
-extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap242x_sram_reprogram_sdrc_sz;
-
-
-extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap243x_sram_ddr_init_sz;
-
-extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap243x_sram_set_prcm_sz;
-
-extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-
-extern u32 omap3_sram_configure_core_dpll(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-extern unsigned long omap3_sram_configure_core_dpll_sz;
-
-#ifdef CONFIG_PM
-extern void omap_push_sram_idle(void);
-#else
-static inline void omap_push_sram_idle(void) {}
-#endif /* CONFIG_PM */
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * OMAP2+: define the SRAM PA addresses.
- * Used by the SRAM management code and the idle sleep code.
- */
-#define OMAP2_SRAM_PA           0x40200000
-#define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA           0x40304000
-#define OMAP4_SRAM_VA           0xfe404000
-#else
-#define OMAP4_SRAM_PA           0x40300000
-#endif
-#define AM33XX_SRAM_PA          0x40300000
-#endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
deleted file mode 100644
index 7f7b112acccb..000000000000
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-
-#include <plat/serial.h>
-
-#define MDR1_MODE_MASK                  0x07
-
-volatile u8 *uart_base;
-int uart_shift;
-
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
-        /*
-         * Get address of some.bss variable and round it down
-         * a la CONFIG_AUTO_ZRELADDR.
-         */
-        u32 ram_start = (u32)&uart_shift & 0xf8000000;
-        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
-        *uart_info = port;
-}
-
-static void putc(int c)
-{
-        if (!uart_base)
-                return;
-
-        /* Check for UART 16x mode */
-        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
-                return;
-
-        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
-                barrier();
-        uart_base[UART_TX << uart_shift] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
-        if (machine_is_##mach()) {                                      \
-                uart_base = (volatile u8 *)(dbg_uart);                  \
-                uart_shift = (dbg_shft);                                \
-                port = (dbg_id);                                        \
-                set_omap_uart_info(port);                               \
-                break;                                                  \
-        }
-
-#define DEBUG_LL_OMAP7XX(p, mach)                                       \
-        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
-                OMAP1UART##p)
-
-#define DEBUG_LL_OMAP1(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP1UART##p)
-
-#define DEBUG_LL_OMAP2(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP2UART##p)
-
-#define DEBUG_LL_OMAP3(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP3UART##p)
-
-#define DEBUG_LL_OMAP4(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP4UART##p)
-
-#define DEBUG_LL_OMAP5(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP5UART##p)
-/* Zoom2/3 shift is different for UART1 and external port */
-#define DEBUG_LL_ZOOM(mach)                                             \
-        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-
-#define DEBUG_LL_TI81XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI81XXUART##p)
-
-#define DEBUG_LL_AM33XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                AM33XXUART##p)
-
-static inline void arch_decomp_setup(void)
-{
-        int port = 0;
-
-        /*
-         * Initialize the port based on the machine ID from the bootloader.
-         * Note that we're using macros here instead of switch statement
-         * as machine_is functions are optimized out for the boards that
-         * are not selected.
-         */
-        do {
-                /* omap7xx/8xx based boards using UART1 with shift 0 */
-                DEBUG_LL_OMAP7XX(1, herald);
-                DEBUG_LL_OMAP7XX(1, omap_perseus2);
-
-                /* omap15xx/16xx based boards using UART1 */
-                DEBUG_LL_OMAP1(1, ams_delta);
-                DEBUG_LL_OMAP1(1, nokia770);
-                DEBUG_LL_OMAP1(1, omap_h2);
-                DEBUG_LL_OMAP1(1, omap_h3);
-                DEBUG_LL_OMAP1(1, omap_innovator);
-                DEBUG_LL_OMAP1(1, omap_osk);
-                DEBUG_LL_OMAP1(1, omap_palmte);
-                DEBUG_LL_OMAP1(1, omap_palmz71);
-
-                /* omap15xx/16xx based boards using UART2 */
-                DEBUG_LL_OMAP1(2, omap_palmtt);
-
-                /* omap15xx/16xx based boards using UART3 */
-                DEBUG_LL_OMAP1(3, sx1);
-
-                /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap_2430sdp);
-                DEBUG_LL_OMAP2(1, omap_apollon);
-                DEBUG_LL_OMAP2(1, omap_h4);
-
-                /* omap2 based boards using UART3 */
-                DEBUG_LL_OMAP2(3, nokia_n800);
-                DEBUG_LL_OMAP2(3, nokia_n810);
-                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
-
-                /* omap3 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap3evm);
-                DEBUG_LL_OMAP3(1, omap_3430sdp);
-                DEBUG_LL_OMAP3(1, omap_3630sdp);
-                DEBUG_LL_OMAP3(1, omap3530_lv_som);
-                DEBUG_LL_OMAP3(1, omap3_torpedo);
-
-                /* omap3 based boards using UART3 */
-                DEBUG_LL_OMAP3(3, cm_t35);
-                DEBUG_LL_OMAP3(3, cm_t3517);
-                DEBUG_LL_OMAP3(3, cm_t3730);
-                DEBUG_LL_OMAP3(3, craneboard);
-                DEBUG_LL_OMAP3(3, devkit8000);
-                DEBUG_LL_OMAP3(3, igep0020);
-                DEBUG_LL_OMAP3(3, igep0030);
-                DEBUG_LL_OMAP3(3, nokia_rm680);
-                DEBUG_LL_OMAP3(3, nokia_rm696);
-                DEBUG_LL_OMAP3(3, nokia_rx51);
-                DEBUG_LL_OMAP3(3, omap3517evm);
-                DEBUG_LL_OMAP3(3, omap3_beagle);
-                DEBUG_LL_OMAP3(3, omap3_pandora);
-                DEBUG_LL_OMAP3(3, omap_ldp);
-                DEBUG_LL_OMAP3(3, overo);
-                DEBUG_LL_OMAP3(3, touchbook);
-
-                /* omap4 based boards using UART3 */
-                DEBUG_LL_OMAP4(3, omap_4430sdp);
-                DEBUG_LL_OMAP4(3, omap4_panda);
-
-                /* omap5 based boards using UART3 */
-                DEBUG_LL_OMAP5(3, omap5_sevm);
-
-                /* zoom2/3 external uart */
-                DEBUG_LL_ZOOM(omap_zoom2);
-                DEBUG_LL_ZOOM(omap_zoom3);
-
-                /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI81XX(3, ti8168evm);
-
-                /* TI8148 base boards using UART1 */
-                DEBUG_LL_TI81XX(1, ti8148evm);
-
-                /* AM33XX base boards using UART1 */
-                DEBUG_LL_AM33XX(1, am335xevm);
-        } while (0);
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
deleted file mode 100644
index 87ee140fefaa..000000000000
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ /dev/null
@@ -1,179 +0,0 @@
-// include/asm-arm/mach-omap/usb.h
-
-#ifndef __ASM_ARCH_OMAP_USB_H
-#define __ASM_ARCH_OMAP_USB_H
-
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-
-#define OMAP3_HS_USB_PORTS      3
-
-enum usbhs_omap_port_mode {
-        OMAP_USBHS_PORT_MODE_UNUSED,
-        OMAP_EHCI_PORT_MODE_PHY,
-        OMAP_EHCI_PORT_MODE_TLL,
-        OMAP_EHCI_PORT_MODE_HSIC,
-        OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
-};
-
-struct usbhs_omap_board_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-
-        /* have to be valid if phy_reset is true and portx is in phy mode */
-        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
-
-        /* Set this to true for ES2.x silicon */
-        unsigned                        es2_compatibility:1;
-
-        unsigned                        phy_reset:1;
-
-        /*
-         * Regulators for USB PHYs.
-         * Each PHY can have a separate regulator.
-         */
-        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
-};
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-
-struct ehci_hcd_omap_platform_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
-        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
-};
-
-struct ohci_hcd_omap_platform_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        es2_compatibility:1;
-};
-
-struct usbhs_omap_platform_data {
-        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
-
-        struct ehci_hcd_omap_platform_data      *ehci_data;
-        struct ohci_hcd_omap_platform_data      *ohci_data;
-};
-
-struct usbtll_omap_platform_data {
-        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
-};
-/*-------------------------------------------------------------------------*/
-
-struct omap_musb_board_data {
-        u8      interface_type;
-        u8      mode;
-        u16     power;
-        unsigned extvbus:1;
-        void    (*set_phy_power)(u8 on);
-        void    (*clear_irq)(void);
-        void    (*set_mode)(u8 mode);
-        void    (*reset)(void);
-};
-
-enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
-
-extern void usb_musb_init(struct omap_musb_board_data *board_data);
-
-extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
-extern int omap_tll_enable(void);
-extern int omap_tll_disable(void);
-
-extern int omap4430_phy_power(struct device *dev, int ID, int on);
-extern int omap4430_phy_set_clk(struct device *dev, int on);
-extern int omap4430_phy_init(struct device *dev);
-extern int omap4430_phy_exit(struct device *dev);
-extern int omap4430_phy_suspend(struct device *dev, int suspend);
-
-#endif
-
-extern void am35x_musb_reset(void);
-extern void am35x_musb_phy_power(u8 on);
-extern void am35x_musb_clear_irq(void);
-extern void am35x_set_mode(u8 musb_mode);
-extern void ti81xx_musb_phy_power(u8 on);
-
-/* AM35x */
-/* USB 2.0 PHY Control */
-#define CONF2_PHY_GPIOMODE      (1 << 23)
-#define CONF2_OTGMODE           (3 << 14)
-#define CONF2_NO_OVERRIDE       (0 << 14)
-#define CONF2_FORCE_HOST        (1 << 14)
-#define CONF2_FORCE_DEVICE      (2 << 14)
-#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
-#define CONF2_SESENDEN          (1 << 13)
-#define CONF2_VBDTCTEN          (1 << 12)
-#define CONF2_REFFREQ_24MHZ     (2 << 8)
-#define CONF2_REFFREQ_26MHZ     (7 << 8)
-#define CONF2_REFFREQ_13MHZ     (6 << 8)
-#define CONF2_REFFREQ           (0xf << 8)
-#define CONF2_PHYCLKGD          (1 << 7)
-#define CONF2_VBUSSENSE         (1 << 6)
-#define CONF2_PHY_PLLON         (1 << 5)
-#define CONF2_RESET             (1 << 4)
-#define CONF2_PHYPWRDN          (1 << 3)
-#define CONF2_OTGPWRDN          (1 << 2)
-#define CONF2_DATPOL            (1 << 1)
-
-/* TI81XX specific definitions */
-#define USBCTRL0        0x620
-#define USBSTAT0        0x624
-
-/* TI816X PHY controls bits */
-#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
-#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
-
-/* TI814X PHY controls bits */
-#define USBPHY_CM_PWRDN         (1 << 0)
-#define USBPHY_OTG_PWRDN        (1 << 1)
-#define USBPHY_CHGDET_DIS       (1 << 2)
-#define USBPHY_CHGDET_RSTRT     (1 << 3)
-#define USBPHY_SRCONDM          (1 << 4)
-#define USBPHY_SINKONDP         (1 << 5)
-#define USBPHY_CHGISINK_EN      (1 << 6)
-#define USBPHY_CHGVSRC_EN       (1 << 7)
-#define USBPHY_DMPULLUP         (1 << 8)
-#define USBPHY_DPPULLUP         (1 << 9)
-#define USBPHY_CDET_EXTCTL      (1 << 10)
-#define USBPHY_GPIO_MODE        (1 << 12)
-#define USBPHY_DPOPBUFCTL       (1 << 13)
-#define USBPHY_DMOPBUFCTL       (1 << 14)
-#define USBPHY_DPINPUT          (1 << 15)
-#define USBPHY_DMINPUT          (1 << 16)
-#define USBPHY_DPGPIO_PD        (1 << 17)
-#define USBPHY_DMGPIO_PD        (1 << 18)
-#define USBPHY_OTGVDET_EN       (1 << 19)
-#define USBPHY_OTGSESSEND_EN    (1 << 20)
-#define USBPHY_DATA_POLARITY    (1 << 23)
-
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
-u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
-u32 omap1_usb1_init(unsigned nwires);
-u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
-#else
-static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
-{
-        return 0;
-}
-static inline u32 omap1_usb1_init(unsigned nwires)
-{
-        return 0;
-
-}
-static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-        return 0;
-}
-#endif
-
-#endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
deleted file mode 100644
index 3792bdea2f6d..000000000000
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * VRFB Rotation Engine
- *
- * Copyright (C) 2009 Nokia Corporation
- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __OMAP_VRFB_H__
-#define __OMAP_VRFB_H__
-
-#define OMAP_VRFB_LINE_LEN 2048
-
-struct vrfb {
-        u8 context;
-        void __iomem *vaddr[4];
-        unsigned long paddr[4];
-        u16 xres;
-        u16 yres;
-        u16 xoffset;
-        u16 yoffset;
-        u8 bytespp;
-        bool yuv_mode;
-};
-
-#ifdef CONFIG_OMAP2_VRFB
-extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
-extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
-extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
-                u8 bytespp);
-extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
-extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
-extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-                u16 width, u16 height,
-                unsigned bytespp, bool yuv_mode);
-extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
-extern void omap_vrfb_restore_context(void);
-
-#else
-static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
-static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
-static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
-                u8 bytespp) {}
-static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
-                { return 0; }
-static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
-                { return 0; }
-static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-                u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
-static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
-                { return 0; }
-static inline void omap_vrfb_restore_context(void) {}
-#endif
-#endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 28acb383e7df..743fc2836f7a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -20,198 +20,20 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <asm/fncpy.h>
 #include <asm/tlb.h>
 #include <asm/cacheflush.h>
 
 #include <asm/mach/map.h>
 
-#include <plat/sram.h>
-#include <plat/cpu.h>
-
-#include "sram.h"
-
-/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
-#include "../mach-omap2/iomap.h"
-#include "../mach-omap2/prm2xxx_3xxx.h"
-#include "../mach-omap2/sdrc.h"
-
-#define OMAP1_SRAM_PA           0x20000000
-#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
-#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA           0x40300000
-
-#if defined(CONFIG_ARCH_OMAP2PLUS)
-#define SRAM_BOOTLOADER_SZ      0x00
-#else
-#define SRAM_BOOTLOADER_SZ      0x80
-#endif
-
-#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
-
-#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
-
-#define GP_DEVICE               0x300
-
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
 
-static unsigned long omap_sram_start;
 static void __iomem *omap_sram_base;
 static unsigned long omap_sram_skip;
 static unsigned long omap_sram_size;
 static void __iomem *omap_sram_ceil;
 
 /*
- * Depending on the target RAMFS firewall setup, the public usable amount of
- * SRAM varies.  The default accessible size for all device types is 2k. A GP
- * device allows ARM11 but not other initiators for full size. This
- * functionality seems ok until some nice security API happens.
- */
-static int is_sram_locked(void)
-{
-        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
-                /* RAMFW: R/W access to all initiators for all qualifier sets */
-                if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
-                }
-                if (cpu_is_omap34xx()) {
-                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
-                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
-                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
-                }
-                return 0;
-        } else
-                return 1; /* assume locked with no PPA or security driver */
-}
-
-/*
- * The amount of SRAM depends on the core type.
- * Note that we cannot try to test for SRAM here because writes
- * to secure SRAM will hang the system. Also the SRAM is not
- * yet mapped at this point.
- */
-static void __init omap_detect_sram(void)
-{
-        omap_sram_skip = SRAM_BOOTLOADER_SZ;
-        if (cpu_class_is_omap2()) {
-                if (is_sram_locked()) {
-                        if (cpu_is_omap34xx()) {
-                                omap_sram_start = OMAP3_SRAM_PUB_PA;
-                                if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
-                                    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
-                                        omap_sram_size = 0x7000; /* 28K */
-                                        omap_sram_skip += SZ_16K;
-                                } else {
-                                        omap_sram_size = 0x8000; /* 32K */
-                                }
-                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_start = OMAP4_SRAM_PUB_PA;
-                                omap_sram_size = 0xa000; /* 40K */
-                        } else if (soc_is_omap54xx()) {
-                                omap_sram_start = OMAP5_SRAM_PA;
-                                omap_sram_size = SZ_128K; /* 128KB */
-                        } else {
-                                omap_sram_start = OMAP2_SRAM_PUB_PA;
-                                omap_sram_size = 0x800; /* 2K */
-                        }
-                } else {
-                        if (soc_is_am33xx()) {
-                                omap_sram_start = AM33XX_SRAM_PA;
-                                omap_sram_size = 0x10000; /* 64K */
-                        } else if (cpu_is_omap34xx()) {
-                                omap_sram_start = OMAP3_SRAM_PA;
-                                omap_sram_size = 0x10000; /* 64K */
-                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_start = OMAP4_SRAM_PA;
-                                omap_sram_size = 0xe000; /* 56K */
-                        } else if (soc_is_omap54xx()) {
-                                omap_sram_start = OMAP5_SRAM_PA;
-                                omap_sram_size = SZ_128K; /* 128KB */
-                        } else {
-                                omap_sram_start = OMAP2_SRAM_PA;
-                                if (cpu_is_omap242x())
-                                        omap_sram_size = 0xa0000; /* 640K */
-                                else if (cpu_is_omap243x())
-                                        omap_sram_size = 0x10000; /* 64K */
-                        }
-                }
-        } else {
-                omap_sram_start = OMAP1_SRAM_PA;
-
-                if (cpu_is_omap7xx())
-                        omap_sram_size = 0x32000;       /* 200K */
-                else if (cpu_is_omap15xx())
-                        omap_sram_size = 0x30000;       /* 192K */
-                else if (cpu_is_omap1610() || cpu_is_omap1611() ||
-                                cpu_is_omap1621() || cpu_is_omap1710())
-                        omap_sram_size = 0x4000;        /* 16K */
-                else {
-                        pr_err("Could not detect SRAM size\n");
-                        omap_sram_size = 0x4000;
-                }
-        }
-}
-
-/*
- * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
- */
-static void __init omap_map_sram(void)
-{
-        int cached = 1;
-
-        if (omap_sram_size == 0)
-                return;
-
-#ifdef CONFIG_OMAP4_ERRATA_I688
-        if (cpu_is_omap44xx()) {
-                omap_sram_start += PAGE_SIZE;
-                omap_sram_size -= SZ_16K;
-        }
-#endif
-        if (cpu_is_omap34xx()) {
-                /*
-                 * SRAM must be marked as non-cached on OMAP3 since the
-                 * CORE DPLL M2 divider change code (in SRAM) runs with the
-                 * SDRAM controller disabled, and if it is marked cached,
-                 * the ARM may attempt to write cache lines back to SDRAM
-                 * which will cause the system to hang.
-                 */
-                cached = 0;
-        }
-
-        omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
-        omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
-                                                cached);
-        if (!omap_sram_base) {
-                pr_err("SRAM: Could not map\n");
-                return;
-        }
-
-        omap_sram_ceil = omap_sram_base + omap_sram_size;
-
-        /*
-         * Looks like we need to preserve some bootloader code at the
-         * beginning of SRAM for jumping to flash for reboot to work...
-         */
-        memset_io(omap_sram_base + omap_sram_skip, 0,
-                  omap_sram_size - omap_sram_skip);
-}
-
-/*
  * Memory allocator for SRAM: calculates the new ceiling address
  * for pushing a function using the fncpy API.
  *
@@ -236,171 +58,39 @@ void *omap_sram_push_address(unsigned long size)
         return (void *)omap_sram_ceil;
 }
 
-#ifdef CONFIG_ARCH_OMAP1
-
-static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
-
-void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
-{
-        BUG_ON(!_omap_sram_reprogram_clock);
-        /* On 730, bit 13 must always be 1 */
-        if (cpu_is_omap7xx())
-                ckctl |= 0x2000;
-        _omap_sram_reprogram_clock(dpllctl, ckctl);
-}
-
-static int __init omap1_sram_init(void)
-{
-        _omap_sram_reprogram_clock =
-                        omap_sram_push(omap1_sram_reprogram_clock,
-                                        omap1_sram_reprogram_clock_sz);
-
-        return 0;
-}
-
-#else
-#define omap1_sram_init()       do {} while (0)
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2)
-
-static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                              u32 base_cs, u32 force_unlock);
-
-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                   u32 base_cs, u32 force_unlock)
-{
-        BUG_ON(!_omap2_sram_ddr_init);
-        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
-                             base_cs, force_unlock);
-}
-
-static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
-                                          u32 mem_type);
-
-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
-{
-        BUG_ON(!_omap2_sram_reprogram_sdrc);
-        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
-}
-
-static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
-u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
-{
-        BUG_ON(!_omap2_set_prcm);
-        return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2420
-static int __init omap242x_sram_init(void)
-{
-        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
-                                        omap242x_sram_ddr_init_sz);
-
-        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
-                                            omap242x_sram_reprogram_sdrc_sz);
-
-        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
-                                         omap242x_sram_set_prcm_sz);
-
-        return 0;
-}
-#else
-static inline int omap242x_sram_init(void)
-{
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static int __init omap243x_sram_init(void)
-{
-        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
-                                        omap243x_sram_ddr_init_sz);
-
-        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
-                                            omap243x_sram_reprogram_sdrc_sz);
-
-        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
-                                         omap243x_sram_set_prcm_sz);
-
-        return 0;
-}
-#else
-static inline int omap243x_sram_init(void)
-{
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-
-static u32 (*_omap3_sram_configure_core_dpll)(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-
-u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
-{
-        BUG_ON(!_omap3_sram_configure_core_dpll);
-        return _omap3_sram_configure_core_dpll(
-                        m2, unlock_dll, f, inc,
-                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
-                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
-                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
-                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
-}
-
-void omap3_sram_restore_context(void)
+/*
+ * The SRAM context is lost during off-idle and stack
+ * needs to be reset.
+ */
+void omap_sram_reset(void)
 {
         omap_sram_ceil = omap_sram_base + omap_sram_size;
-
-        _omap3_sram_configure_core_dpll =
-                omap_sram_push(omap3_sram_configure_core_dpll,
-                               omap3_sram_configure_core_dpll_sz);
-        omap_push_sram_idle();
 }
 
-static inline int omap34xx_sram_init(void)
-{
-        omap3_sram_restore_context();
-        return 0;
-}
-#else
-static inline int omap34xx_sram_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_ARCH_OMAP3 */
-
-static inline int am33xx_sram_init(void)
+/*
+ * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
+ */
+void __init omap_map_sram(unsigned long start, unsigned long size,
+                                 unsigned long skip, int cached)
 {
-        return 0;
-}
+        if (size == 0)
+                return;
 
-int __init omap_sram_init(void)
-{
-        omap_detect_sram();
-        omap_map_sram();
+        start = ROUND_DOWN(start, PAGE_SIZE);
+        omap_sram_size = size;
+        omap_sram_skip = skip;
+        omap_sram_base = __arm_ioremap_exec(start, size, cached);
+        if (!omap_sram_base) {
+                pr_err("SRAM: Could not map\n");
+                return;
+        }
 
-        if (!(cpu_class_is_omap2()))
-                omap1_sram_init();
-        else if (cpu_is_omap242x())
-                omap242x_sram_init();
-        else if (cpu_is_omap2430())
-                omap243x_sram_init();
-        else if (soc_is_am33xx())
-                am33xx_sram_init();
-        else if (cpu_is_omap34xx())
-                omap34xx_sram_init();
+        omap_sram_reset();
 
-        return 0;
+        /*
+         * Looks like we need to preserve some bootloader code at the
+         * beginning of SRAM for jumping to flash for reboot to work...
+         */
+        memset_io(omap_sram_base + omap_sram_skip, 0,
+                  omap_sram_size - omap_sram_skip);
 }
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
deleted file mode 100644
index 29b43ef97f20..000000000000
--- a/arch/arm/plat-omap/sram.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PLAT_OMAP_SRAM_H__
-#define __PLAT_OMAP_SRAM_H__
-
-extern int __init omap_sram_init(void);
-
-#endif /* __PLAT_OMAP_SRAM_H__ */