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-rw-r--r--arch/arm/boot/dts/spear1310.dtsi18
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi6
-rw-r--r--arch/arm/include/asm/io.h1
-rw-r--r--arch/arm/mach-integrator/pci_v3.c23
4 files changed, 25 insertions, 23 deletions
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index fa5f2bb5f106..9d342920695a 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -85,7 +85,8 @@
85 85
86 pcie0: pcie@b1000000 { 86 pcie0: pcie@b1000000 {
87 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 87 compatible = "st,spear1340-pcie", "snps,dw-pcie";
88 reg = <0xb1000000 0x4000>; 88 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
89 reg-names = "dbi", "config";
89 interrupts = <0 68 0x4>; 90 interrupts = <0 68 0x4>;
90 interrupt-map-mask = <0 0 0 0>; 91 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0x0 0 &gic 0 68 0x4>; 92 interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -95,15 +96,15 @@
95 #address-cells = <3>; 96 #address-cells = <3>;
96 #size-cells = <2>; 97 #size-cells = <2>;
97 device_type = "pci"; 98 device_type = "pci";
98 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ 99 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
99 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
101 status = "disabled"; 101 status = "disabled";
102 }; 102 };
103 103
104 pcie1: pcie@b1800000 { 104 pcie1: pcie@b1800000 {
105 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 105 compatible = "st,spear1340-pcie", "snps,dw-pcie";
106 reg = <0xb1800000 0x4000>; 106 reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
107 reg-names = "dbi", "config";
107 interrupts = <0 69 0x4>; 108 interrupts = <0 69 0x4>;
108 interrupt-map-mask = <0 0 0 0>; 109 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0x0 0 &gic 0 69 0x4>; 110 interrupt-map = <0x0 0 &gic 0 69 0x4>;
@@ -113,15 +114,15 @@
113 #address-cells = <3>; 114 #address-cells = <3>;
114 #size-cells = <2>; 115 #size-cells = <2>;
115 device_type = "pci"; 116 device_type = "pci";
116 ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ 117 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
117 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
118 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ 118 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
119 status = "disabled"; 119 status = "disabled";
120 }; 120 };
121 121
122 pcie2: pcie@b4000000 { 122 pcie2: pcie@b4000000 {
123 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 123 compatible = "st,spear1340-pcie", "snps,dw-pcie";
124 reg = <0xb4000000 0x4000>; 124 reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
125 reg-names = "dbi", "config";
125 interrupts = <0 70 0x4>; 126 interrupts = <0 70 0x4>;
126 interrupt-map-mask = <0 0 0 0>; 127 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0x0 0 &gic 0 70 0x4>; 128 interrupt-map = <0x0 0 &gic 0 70 0x4>;
@@ -131,8 +132,7 @@
131 #address-cells = <3>; 132 #address-cells = <3>;
132 #size-cells = <2>; 133 #size-cells = <2>;
133 device_type = "pci"; 134 device_type = "pci";
134 ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ 135 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
135 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
136 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 136 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index e71df0f2cb52..13e1aa33daa2 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -50,7 +50,8 @@
50 50
51 pcie0: pcie@b1000000 { 51 pcie0: pcie@b1000000 {
52 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 52 compatible = "st,spear1340-pcie", "snps,dw-pcie";
53 reg = <0xb1000000 0x4000>; 53 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
54 reg-names = "dbi", "config";
54 interrupts = <0 68 0x4>; 55 interrupts = <0 68 0x4>;
55 interrupt-map-mask = <0 0 0 0>; 56 interrupt-map-mask = <0 0 0 0>;
56 interrupt-map = <0x0 0 &gic 0 68 0x4>; 57 interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -60,8 +61,7 @@
60 #address-cells = <3>; 61 #address-cells = <3>;
61 #size-cells = <2>; 62 #size-cells = <2>;
62 device_type = "pci"; 63 device_type = "pci";
63 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ 64 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
64 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
66 status = "disabled"; 66 status = "disabled";
67 }; 67 };
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 3d23418cbddd..180567408ee8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
178 178
179/* PCI fixed i/o mapping */ 179/* PCI fixed i/o mapping */
180#define PCI_IO_VIRT_BASE 0xfee00000 180#define PCI_IO_VIRT_BASE 0xfee00000
181#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
181 182
182#if defined(CONFIG_PCI) 183#if defined(CONFIG_PCI)
183void pci_ioremap_set_mem_type(int mem_type); 184void pci_ioremap_set_mem_type(int mem_type);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 05e1f73a1e8d..c186a17c2cff 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void)
660{ 660{
661 unsigned long flags; 661 unsigned long flags;
662 unsigned int temp; 662 unsigned int temp;
663 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
663 664
664 pcibios_min_mem = 0x00100000; 665 pcibios_min_mem = 0x00100000;
665 666
@@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void)
701 /* 702 /*
702 * Setup window 2 - PCI IO 703 * Setup window 2 - PCI IO
703 */ 704 */
704 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | 705 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
705 V3_LB_BASE_ENABLE); 706 V3_LB_BASE_ENABLE);
706 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); 707 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
707 708
@@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void)
742static void __init pci_v3_postinit(void) 743static void __init pci_v3_postinit(void)
743{ 744{
744 unsigned int pci_cmd; 745 unsigned int pci_cmd;
746 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
745 747
746 pci_cmd = PCI_COMMAND_MEMORY | 748 pci_cmd = PCI_COMMAND_MEMORY |
747 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; 749 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void)
758 "interrupt: %d\n", ret); 760 "interrupt: %d\n", ret);
759#endif 761#endif
760 762
761 register_isa_ports(non_mem.start, io_mem.start, 0); 763 register_isa_ports(non_mem.start, io_address, 0);
762} 764}
763 765
764/* 766/*
@@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev)
867 869
868 for_each_of_pci_range(&parser, &range) { 870 for_each_of_pci_range(&parser, &range) {
869 if (!range.flags) { 871 if (!range.flags) {
870 of_pci_range_to_resource(&range, np, &conf_mem); 872 ret = of_pci_range_to_resource(&range, np, &conf_mem);
871 conf_mem.name = "PCIv3 config"; 873 conf_mem.name = "PCIv3 config";
872 } 874 }
873 if (range.flags & IORESOURCE_IO) { 875 if (range.flags & IORESOURCE_IO) {
874 of_pci_range_to_resource(&range, np, &io_mem); 876 ret = of_pci_range_to_resource(&range, np, &io_mem);
875 io_mem.name = "PCIv3 I/O"; 877 io_mem.name = "PCIv3 I/O";
876 } 878 }
877 if ((range.flags & IORESOURCE_MEM) && 879 if ((range.flags & IORESOURCE_MEM) &&
878 !(range.flags & IORESOURCE_PREFETCH)) { 880 !(range.flags & IORESOURCE_PREFETCH)) {
879 non_mem_pci = range.pci_addr; 881 non_mem_pci = range.pci_addr;
880 non_mem_pci_sz = range.size; 882 non_mem_pci_sz = range.size;
881 of_pci_range_to_resource(&range, np, &non_mem); 883 ret = of_pci_range_to_resource(&range, np, &non_mem);
882 non_mem.name = "PCIv3 non-prefetched mem"; 884 non_mem.name = "PCIv3 non-prefetched mem";
883 } 885 }
884 if ((range.flags & IORESOURCE_MEM) && 886 if ((range.flags & IORESOURCE_MEM) &&
885 (range.flags & IORESOURCE_PREFETCH)) { 887 (range.flags & IORESOURCE_PREFETCH)) {
886 pre_mem_pci = range.pci_addr; 888 pre_mem_pci = range.pci_addr;
887 pre_mem_pci_sz = range.size; 889 pre_mem_pci_sz = range.size;
888 of_pci_range_to_resource(&range, np, &pre_mem); 890 ret = of_pci_range_to_resource(&range, np, &pre_mem);
889 pre_mem.name = "PCIv3 prefetched mem"; 891 pre_mem.name = "PCIv3 prefetched mem";
890 } 892 }
891 }
892 893
893 if (!conf_mem.start || !io_mem.start || 894 if (ret < 0) {
894 !non_mem.start || !pre_mem.start) { 895 dev_err(&pdev->dev, "missing ranges in device node\n");
895 dev_err(&pdev->dev, "missing ranges in device node\n"); 896 return ret;
896 return -EINVAL; 897 }
897 } 898 }
898 899
899 pci_v3.map_irq = of_irq_parse_and_map_pci; 900 pci_v3.map_irq = of_irq_parse_and_map_pci;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 07:23:36 -0500