570 files changed, 26208 insertions, 28613 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 392e7ae69452..45df48ba0b12 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -362,19 +362,6 @@ config ARCH_VERSATILE
        help
          This enables support for ARM Ltd Versatile board.
-config ARCH_AT91
-        bool "Atmel AT91"
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select IRQ_DOMAIN
-        select NEED_MACH_IO_H if PCCARD
-        select PINCTRL
-        select PINCTRL_AT91
-        select USE_OF
-        help
-          This enables support for systems based on Atmel
-          AT91RM9200, AT91SAM9 and SAMA5 processors.
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
        select ARCH_REQUIRE_GPIOLIB
@@ -632,18 +619,6 @@ config ARCH_PXA
        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-config ARCH_MSM
-        bool "Qualcomm MSM (non-multiplatform)"
-        select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Qualcomm MSM/QSD based systems.  This runs on the
-          apps processor of the MSM/QSD and depends on a shared memory
-          interface to the modem processor which runs the baseband
-          stack and controls some vital subsystems
-          (clock and power control, etc).
 config ARCH_SHMOBILE_LEGACY
        bool "Renesas ARM SoCs (non-multiplatform)"
        select ARCH_SHMOBILE
@@ -653,7 +628,6 @@ config ARCH_SHMOBILE_LEGACY
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_MACH_CLKDEV
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select MULTI_IRQ_HANDLER
@@ -851,6 +825,8 @@ config ARCH_VIRT
 #
 source "arch/arm/mach-mvebu/Kconfig"
+source "arch/arm/mach-alpine/Kconfig"
 source "arch/arm/mach-asm9260/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
@@ -897,8 +873,6 @@ source "arch/arm/mach-ks8695/Kconfig"
 source "arch/arm/mach-meson/Kconfig"
-source "arch/arm/mach-msm/Kconfig"
 source "arch/arm/mach-moxart/Kconfig"
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1523,7 +1497,7 @@ config HZ_FIXED
        int
        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
                ARCH_S5PV210 || ARCH_EXYNOS4
-        default AT91_TIMER_HZ if ARCH_AT91
+        default 128 if SOC_AT91RM9200
        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
        default 0
@@ -1856,35 +1830,6 @@ config ZBOOT_ROM
          Say Y here if you intend to execute your compressed kernel image
          (zImage) directly from ROM or flash.  If unsure, say N.
-choice
-        prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
-        depends on ZBOOT_ROM && ARCH_SH7372
-        default ZBOOT_ROM_NONE
-        help
-          Include experimental SD/MMC loading code in the ROM-able zImage.
-          With this enabled it is possible to write the ROM-able zImage
-          kernel image to an MMC or SD card and boot the kernel straight
-          from the reset vector. At reset the processor Mask ROM will load
-          the first part of the ROM-able zImage which in turn loads the
-          rest the kernel image to RAM.
-config ZBOOT_ROM_NONE
-        bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
-        help
-          Do not load image from SD or MMC
-config ZBOOT_ROM_MMCIF
-        bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
-        help
-          Load image from MMCIF hardware block.
-config ZBOOT_ROM_SH_MOBILE_SDHI
-        bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
-        help
-          Load image from SDHI hardware block
-endchoice
 config ARM_APPENDED_DTB
        bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
        depends on OF
@@ -2158,6 +2103,8 @@ source "net/Kconfig"
 source "drivers/Kconfig"
+source "drivers/firmware/Kconfig"
 source "fs/Kconfig"
 source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8b0183a9a300..0c12ffb155a2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -93,6 +93,14 @@ choice
        prompt "Kernel low-level debugging port"
        depends on DEBUG_LL
+        config DEBUG_ALPINE_UART0
+                bool "Kernel low-level debugging messages via Alpine UART0"
+                depends on ARCH_ALPINE
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Alpine based platforms.
        config DEBUG_ASM9260_UART
                bool "Kernel low-level debugging via asm9260 UART"
                depends on MACH_ASM9260
@@ -448,25 +456,6 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on MMP UART3.
-        config DEBUG_MSM_UART
-                bool "Kernel low-level debugging messages via MSM UART"
-                depends on ARCH_MSM
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM devices.
-                  ARCH                DEBUG_UART_PHYS   DEBUG_UART_VIRT   #
-                  MSM7X00A, QSD8X50   0xa9a00000        0xe1000000        UART1
-                  MSM7X00A, QSD8X50   0xa9b00000        0xe1000000        UART2
-                  MSM7X00A, QSD8X50   0xa9c00000        0xe1000000        UART3
-                  MSM7X30             0xaca00000        0xe1000000        UART1
-                  MSM7X30             0xacb00000        0xe1000000        UART2
-                  MSM7X30             0xacc00000        0xe1000000        UART3
-                  Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
-                  options based on your needs.
        config DEBUG_QCOM_UARTDM
                bool "Kernel low-level debugging messages via QCOM UARTDM"
                depends on ARCH_QCOM
@@ -806,7 +795,7 @@ choice
                  via SCIF2 on Renesas R-Car H1 (R8A7779).
        config DEBUG_RCAR_GEN2_SCIF0
-                bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793)"
+                bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793"
                depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7793
                help
                  Say Y here if you want kernel low-level debugging support
@@ -821,12 +810,11 @@ choice
                  via SCIF2 on Renesas R-Car E2 (R8A7794).
        config DEBUG_RMOBILE_SCIFA0
-                bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372"
+                bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
-                depends on ARCH_R8A73A4 || ARCH_SH7372
+                depends on ARCH_R8A73A4
                help
                  Say Y here if you want kernel low-level debugging support
-                  via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile
+                  via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4).
-                  AP4 (SH7372).
        config DEBUG_RMOBILE_SCIFA1
                bool "Kernel low-level debugging messages via SCIFA1 on R8A7740"
@@ -1295,7 +1283,7 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX6SL_UART || \
                                 DEBUG_IMX6SX_UART
        default "debug/ks8695.S" if DEBUG_KS8695_UART
-        default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
+        default "debug/msm.S" if DEBUG_QCOM_UARTDM
        default "debug/netx.S" if DEBUG_NETX_UART
        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
        default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
@@ -1388,7 +1376,6 @@ config DEBUG_UART_PHYS
        default 0x80230000 if DEBUG_PICOXCELL_UART
        default 0x808c0000 if ARCH_EP93XX
        default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
-        default 0xa9a00000 if DEBUG_MSM_UART
        default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
        default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
        default 0xc0013000 if DEBUG_U300_UART
@@ -1417,6 +1404,7 @@ config DEBUG_UART_PHYS
        default 0xf8b00000 if DEBUG_HIX5HD2_UART
        default 0xf991e000 if DEBUG_QCOM_UARTDM
        default 0xfcb00000 if DEBUG_HI3620_UART
+        default 0xfd883000 if DEBUG_ALPINE_UART0
        default 0xfe800000 if ARCH_IOP32X
        default 0xff690000 if DEBUG_RK32_UART2
        default 0xffc02000 if DEBUG_SOCFPGA_UART
@@ -1433,7 +1421,7 @@ config DEBUG_UART_PHYS
                DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_LL_UART_EFM32 || \
                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
-                DEBUG_MSM_UART || DEBUG_NETX_UART || \
+                DEBUG_NETX_UART || \
                DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
                DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
                DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
@@ -1446,7 +1434,6 @@ config DEBUG_UART_VIRT
        hex "Virtual base address of debug UART"
        default 0xe0000a00 if DEBUG_NETX_UART
        default 0xe0010fe0 if ARCH_RPC
-        default 0xe1000000 if DEBUG_MSM_UART
        default 0xf0000be0 if ARCH_EBSA110
        default 0xf0010000 if DEBUG_ASM9260_UART
        default 0xf01fb000 if DEBUG_NOMADIK_UART
@@ -1483,6 +1470,7 @@ config DEBUG_UART_VIRT
        default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
        default 0xfd000000 if ARCH_SPEAR13XX
        default 0xfd012000 if ARCH_MV78XX0
+        default 0xfd883000 if DEBUG_ALPINE_UART0
        default 0xfde12000 if ARCH_DOVE
        default 0xfe012000 if ARCH_ORION5X
        default 0xf31004c0 if DEBUG_MESON_UARTAO
@@ -1526,7 +1514,7 @@ config DEBUG_UART_VIRT
        default DEBUG_UART_PHYS if !MMU
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
-                DEBUG_MSM_UART || DEBUG_NETX_UART || \
+                DEBUG_NETX_UART || \
                DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
                DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
                DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
@@ -1543,7 +1531,7 @@ config DEBUG_UART_8250_WORD
        depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
        depends on DEBUG_UART_8250_SHIFT >= 2
        default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
-                ARCH_KEYSTONE || \
+                ARCH_KEYSTONE || DEBUG_ALPINE_UART0 || \
                DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
                DEBUG_DAVINCI_DA8XX_UART2 || \
                DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
@@ -1556,7 +1544,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
 config DEBUG_UNCOMPRESS
        bool
-        depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG
+        depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG
        default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
                     (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
        help
@@ -1573,7 +1561,8 @@ config DEBUG_UNCOMPRESS
 config UNCOMPRESS_INCLUDE
        string
        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
-                                        PLAT_SAMSUNG || ARCH_EFM32
+                                        PLAT_SAMSUNG || ARCH_EFM32 || \
+                                        ARCH_SHMOBILE_LEGACY
        default "mach/uncompress.h"
 config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5575d9fa8806..985227cbbd1b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,13 +136,13 @@ textofs-$(CONFIG_PM_H1940)      := 0x00108000
 ifeq ($(CONFIG_ARCH_SA1100),y)
 textofs-$(CONFIG_SA1111) := 0x00208000
 endif
-textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ALPINE)           += alpine
 machine-$(CONFIG_ARCH_AT91)             += at91
 machine-$(CONFIG_ARCH_AXXIA)            += axxia
 machine-$(CONFIG_ARCH_BCM)              += bcm
@@ -171,7 +171,6 @@ machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
 machine-$(CONFIG_ARCH_MESON)            += meson
 machine-$(CONFIG_ARCH_MMP)              += mmp
 machine-$(CONFIG_ARCH_MOXART)           += moxart
-machine-$(CONFIG_ARCH_MSM)              += msm
 machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_MXC)              += imx
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3ea230aa94b7..6e1fb2b2ecc7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -6,21 +6,6 @@
 OBJS            =
-# Ensure that MMCIF loader code appears early in the image
-# to minimise that number of bocks that have to be read in
-# order to load it.
-ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y)
-OBJS            += mmcif-sh7372.o
-endif
-# Ensure that SDHI loader code appears early in the image
-# to minimise that number of bocks that have to be read in
-# order to load it.
-ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y)
-OBJS            += sdhi-shmobile.o
-OBJS            += sdhi-sh7372.o
-endif
 AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD    = head.o
 OBJS    += misc.o decompress.o
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index e7f80928949c..22a75259faa3 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -25,36 +25,6 @@
        /* load board-specific initialization code */
 #include <mach/zboot.h>
-#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
-        /* Load image from MMC/SD */
-        adr     sp, __tmp_stack + 256
-        ldr     r0, __image_start
-        ldr     r1, __image_end
-        subs    r1, r1, r0
-        ldr     r0, __load_base
-        bl      mmc_loader
-        /* Jump to loaded code */
-        ldr     r0, __loaded
-        ldr     r1, __image_start
-        sub     r0, r0, r1
-        ldr     r1, __load_base
-        add     pc, r0, r1
-__image_start:
-        .long   _start
-__image_end:
-        .long   _got_end
-__load_base:
-        .long   MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
-__loaded:
-        .long   __continue
-        .align
-__tmp_stack:
-        .space  256
-__continue:
-#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
        adr     r0, dtb_info
        ldmia   r0, {r1, r3, r4, r5, r7}
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
deleted file mode 100644
index 672ae95db5c3..000000000000
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * sh7372 MMCIF loader
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2010 Simon Horman
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/mmc/boot.h>
-#include <mach/mmc.h>
-#define MMCIF_BASE      (void __iomem *)0xe6bd0000
-#define PORT84CR        (void __iomem *)0xe6050054
-#define PORT85CR        (void __iomem *)0xe6050055
-#define PORT86CR        (void __iomem *)0xe6050056
-#define PORT87CR        (void __iomem *)0xe6050057
-#define PORT88CR        (void __iomem *)0xe6050058
-#define PORT89CR        (void __iomem *)0xe6050059
-#define PORT90CR        (void __iomem *)0xe605005a
-#define PORT91CR        (void __iomem *)0xe605005b
-#define PORT92CR        (void __iomem *)0xe605005c
-#define PORT99CR        (void __iomem *)0xe6050063
-#define SMSTPCR3        (void __iomem *)0xe615013c
-/* SH7372 specific MMCIF loader
- *
- * loads the zImage from an MMC card starting from block 1.
- *
- * The image must be start with a vrl4 header and
- * the zImage must start at offset 512 of the image. That is,
- * at block 2 (=byte 1024) on the media
- *
- * Use the following line to write the vrl4 formated zImage
- * to an MMC card
- * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
- */
-asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
-{
-        mmc_init_progress();
-        mmc_update_progress(MMC_PROGRESS_ENTER);
-        /* Initialise MMC
-         * registers: PORT84CR-PORT92CR
-         *            (MMCD0_0-MMCD0_7,MMCCMD0 Control)
-         * value: 0x04 - select function 4
-         */
-         __raw_writeb(0x04, PORT84CR);
-         __raw_writeb(0x04, PORT85CR);
-         __raw_writeb(0x04, PORT86CR);
-         __raw_writeb(0x04, PORT87CR);
-         __raw_writeb(0x04, PORT88CR);
-         __raw_writeb(0x04, PORT89CR);
-         __raw_writeb(0x04, PORT90CR);
-         __raw_writeb(0x04, PORT91CR);
-         __raw_writeb(0x04, PORT92CR);
-        /* Initialise MMC
-         * registers: PORT99CR (MMCCLK0 Control)
-         * value: 0x10 | 0x04 - enable output | select function 4
-         */
-        __raw_writeb(0x14, PORT99CR);
-        /* Enable clock to MMC hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
-        mmc_update_progress(MMC_PROGRESS_INIT);
-        /* setup MMCIF hardware */
-        sh_mmcif_boot_init(MMCIF_BASE);
-        mmc_update_progress(MMC_PROGRESS_LOAD);
-        /* load kernel via MMCIF interface */
-        sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
-                              (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
-        /* Disable clock to MMC hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
-        mmc_update_progress(MMC_PROGRESS_DONE);
-}
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
deleted file mode 100644
index d279294f2381..000000000000
--- a/arch/arm/boot/compressed/sdhi-sh7372.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * SuperH Mobile SDHI
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2010 Kuninori Morimoto
- * Copyright (C) 2010 Simon Horman
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Parts inspired by u-boot
- */
-#include <linux/io.h>
-#include <mach/mmc.h>
-#include <linux/mmc/boot.h>
-#include <linux/mmc/tmio.h>
-#include "sdhi-shmobile.h"
-#define PORT179CR       0xe60520b3
-#define PORT180CR       0xe60520b4
-#define PORT181CR       0xe60520b5
-#define PORT182CR       0xe60520b6
-#define PORT183CR       0xe60520b7
-#define PORT184CR       0xe60520b8
-#define SMSTPCR3        0xe615013c
-#define CR_INPUT_ENABLE 0x10
-#define CR_FUNCTION1    0x01
-#define SDHI1_BASE      (void __iomem *)0xe6860000
-#define SDHI_BASE       SDHI1_BASE
-/*  SuperH Mobile SDHI loader
- *
- * loads the zImage from an SD card starting from block 0
- * on physical partition 1
- *
- * The image must be start with a vrl4 header and
- * the zImage must start at offset 512 of the image. That is,
- * at block 1 (=byte 512) of physical partition 1
- *
- * Use the following line to write the vrl4 formated zImage
- * to an SD card
- * # dd if=vrl4.out of=/dev/sdx bs=512
- */
-asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
-{
-        int high_capacity;
-        mmc_init_progress();
-        mmc_update_progress(MMC_PROGRESS_ENTER);
-        /* Initialise SDHI1 */
-        /* PORT184CR: GPIO_FN_SDHICMD1 Control */
-        __raw_writeb(CR_FUNCTION1, PORT184CR);
-        /* PORT179CR: GPIO_FN_SDHICLK1 Control */
-        __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
-        /* PORT181CR: GPIO_FN_SDHID1_3 Control */
-        __raw_writeb(CR_FUNCTION1, PORT183CR);
-        /* PORT182CR: GPIO_FN_SDHID1_2 Control */
-        __raw_writeb(CR_FUNCTION1, PORT182CR);
-        /* PORT183CR: GPIO_FN_SDHID1_1 Control */
-        __raw_writeb(CR_FUNCTION1, PORT181CR);
-        /* PORT180CR: GPIO_FN_SDHID1_0 Control */
-        __raw_writeb(CR_FUNCTION1, PORT180CR);
-        /* Enable clock to SDHI1 hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
-        /* setup SDHI hardware */
-        mmc_update_progress(MMC_PROGRESS_INIT);
-        high_capacity = sdhi_boot_init(SDHI_BASE);
-        if (high_capacity < 0)
-                goto err;
-        mmc_update_progress(MMC_PROGRESS_LOAD);
-        /* load kernel */
-        if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
-                              0, /* Kernel is at block 1 */
-                              (len + TMIO_BBS - 1) / TMIO_BBS, buf))
-                goto err;
-        /* Disable clock to SDHI1 hardware block */
-        __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
-        mmc_update_progress(MMC_PROGRESS_DONE);
-        return;
-err:
-        for(;;);
-}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
deleted file mode 100644
index bd3d46980955..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/*
- * SuperH Mobile SDHI
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2010 Kuninori Morimoto
- * Copyright (C) 2010 Simon Horman
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Parts inspired by u-boot
- */
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/core.h>
-#include <linux/mmc/mmc.h>
-#include <linux/mmc/sd.h>
-#include <linux/mmc/tmio.h>
-#include <mach/sdhi.h>
-#define OCR_FASTBOOT            (1<<29)
-#define OCR_HCS                 (1<<30)
-#define OCR_BUSY                (1<<31)
-#define RESP_CMD12              0x00000030
-static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
-{
-        return __raw_readw(base + addr);
-}
-static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
-{
-        return __raw_readw(base + addr) |
-               __raw_readw(base + addr + 2) << 16;
-}
-static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
-{
-        __raw_writew(val, base + addr);
-}
-static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
-{
-        __raw_writew(val, base + addr);
-        __raw_writew(val >> 16, base + addr + 2);
-}
-#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL |          \
-                   TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT |      \
-                   TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN |        \
-                   TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS |        \
-                   TMIO_STAT_ILL_FUNC)
-static int sdhi_intr(void __iomem *base)
-{
-        unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
-        if (state & ALL_ERROR) {
-                sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
-                sd_ctrl_write32(base, CTL_IRQ_MASK,
-                                ALL_ERROR |
-                                sd_ctrl_read32(base, CTL_IRQ_MASK));
-                return -EINVAL;
-        }
-        if (state & TMIO_STAT_CMDRESPEND) {
-                sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
-                sd_ctrl_write32(base, CTL_IRQ_MASK,
-                                TMIO_STAT_CMDRESPEND |
-                                sd_ctrl_read32(base, CTL_IRQ_MASK));
-                return 0;
-        }
-        if (state & TMIO_STAT_RXRDY) {
-                sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
-                sd_ctrl_write32(base, CTL_IRQ_MASK,
-                                TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
-                                sd_ctrl_read32(base, CTL_IRQ_MASK));
-                return 0;
-        }
-        if (state & TMIO_STAT_DATAEND) {
-                sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
-                sd_ctrl_write32(base, CTL_IRQ_MASK,
-                                TMIO_STAT_DATAEND |
-                                sd_ctrl_read32(base, CTL_IRQ_MASK));
-                return 0;
-        }
-        return -EAGAIN;
-}
-static int sdhi_boot_wait_resp_end(void __iomem *base)
-{
-        int err = -EAGAIN, timeout = 10000000;
-        while (timeout--) {
-                err = sdhi_intr(base);
-                if (err != -EAGAIN)
-                        break;
-                udelay(1);
-        }
-        return err;
-}
-/* SDHI_CLK_CTRL */
-#define CLK_MMC_ENABLE                 (1 << 8)
-#define CLK_MMC_INIT                   (1 << 6)        /* clk / 256 */
-static void sdhi_boot_mmc_clk_stop(void __iomem *base)
-{
-        sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
-        msleep(10);
-        sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
-                sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
-        msleep(10);
-}
-static void sdhi_boot_mmc_clk_start(void __iomem *base)
-{
-        sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
-                sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
-        msleep(10);
-        sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
-        msleep(10);
-}
-static void sdhi_boot_reset(void __iomem *base)
-{
-        sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
-        msleep(10);
-        sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
-        msleep(10);
-}
-/* Set MMC clock / power.
- * Note: This controller uses a simple divider scheme therefore it cannot
- * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
- * MMC wont run that fast, it has to be clocked at 12MHz which is the next
- * slowest setting.
- */
-static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
-{
-        if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
-                return -EBUSY;
-        if (ios->clock)
-                sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
-                                ios->clock | CLK_MMC_ENABLE);
-        /* Power sequence - OFF -> ON -> UP */
-        switch (ios->power_mode) {
-        case MMC_POWER_OFF: /* power down SD bus */
-                sdhi_boot_mmc_clk_stop(base);
-                break;
-        case MMC_POWER_ON: /* power up SD bus */
-                break;
-        case MMC_POWER_UP: /* start bus clock */
-                sdhi_boot_mmc_clk_start(base);
-                break;
-        }
-        switch (ios->bus_width) {
-        case MMC_BUS_WIDTH_1:
-                sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
-        break;
-        case MMC_BUS_WIDTH_4:
-                sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
-        break;
-        }
-        /* Let things settle. delay taken from winCE driver */
-        udelay(140);
-        return 0;
-}
-/* These are the bitmasks the tmio chip requires to implement the MMC response
- * types. Note that R1 and R6 are the same in this scheme. */
-#define RESP_NONE      0x0300
-#define RESP_R1        0x0400
-#define RESP_R1B       0x0500
-#define RESP_R2        0x0600
-#define RESP_R3        0x0700
-#define DATA_PRESENT   0x0800
-#define TRANSFER_READ  0x1000
-static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
-{
-        int err, c = cmd->opcode;
-        switch (mmc_resp_type(cmd)) {
-        case MMC_RSP_NONE: c |= RESP_NONE; break;
-        case MMC_RSP_R1:   c |= RESP_R1;   break;
-        case MMC_RSP_R1B:  c |= RESP_R1B;  break;
-        case MMC_RSP_R2:   c |= RESP_R2;   break;
-        case MMC_RSP_R3:   c |= RESP_R3;   break;
-        default:
-                return -EINVAL;
-        }
-        /* No interrupts so this may not be cleared */
-        sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
-        sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
-                        sd_ctrl_read32(base, CTL_IRQ_MASK));
-        sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
-        sd_ctrl_write16(base, CTL_SD_CMD, c);
-        sd_ctrl_write32(base, CTL_IRQ_MASK,
-                        ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
-                        sd_ctrl_read32(base, CTL_IRQ_MASK));
-        err = sdhi_boot_wait_resp_end(base);
-        if (err)
-                return err;
-        cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
-        return 0;
-}
-static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
-                                    unsigned long block, unsigned short *buf)
-{
-        int err, i;
-        /* CMD17 - Read */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_READ_SINGLE_BLOCK | \
-                             TRANSFER_READ | DATA_PRESENT;
-                if (high_capacity)
-                        cmd.arg = block;
-                else
-                        cmd.arg = block * TMIO_BBS;
-                cmd.flags = MMC_RSP_R1;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-        }
-        sd_ctrl_write32(base, CTL_IRQ_MASK,
-                        ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
-                          TMIO_STAT_TXUNDERRUN) &
-                        sd_ctrl_read32(base, CTL_IRQ_MASK));
-        err = sdhi_boot_wait_resp_end(base);
-        if (err)
-                return err;
-        sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
-        for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
-                *buf++ = sd_ctrl_read16(base, RESP_CMD12);
-        err = sdhi_boot_wait_resp_end(base);
-        if (err)
-                return err;
-        return 0;
-}
-int sdhi_boot_do_read(void __iomem *base, int high_capacity,
-                      unsigned long offset, unsigned short count,
-                      unsigned short *buf)
-{
-        unsigned long i;
-        int err = 0;
-        for (i = 0; i < count; i++) {
-                err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
-                                               buf + (i * TMIO_BBS /
-                                                      sizeof(*buf)));
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
-int sdhi_boot_init(void __iomem *base)
-{
-        bool sd_v2 = false, sd_v1_0 = false;
-        unsigned short cid;
-        int err, high_capacity = 0;
-        sdhi_boot_mmc_clk_stop(base);
-        sdhi_boot_reset(base);
-        /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
-        {
-                struct mmc_ios ios;
-                ios.power_mode = MMC_POWER_ON;
-                ios.bus_width = MMC_BUS_WIDTH_1;
-                ios.clock = CLK_MMC_INIT;
-                err = sdhi_boot_mmc_set_ios(base, &ios);
-                if (err)
-                        return err;
-        }
-        /* CMD0 */
-        {
-                struct mmc_command cmd;
-                msleep(1);
-                cmd.opcode = MMC_GO_IDLE_STATE;
-                cmd.arg = 0;
-                cmd.flags = MMC_RSP_NONE;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-                msleep(2);
-        }
-        /* CMD8 - Test for SD version 2 */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = SD_SEND_IF_COND;
-                cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
-                cmd.flags = MMC_RSP_R1;
-                err = sdhi_boot_request(base, &cmd); /* Ignore error */
-                if ((cmd.resp[0] & 0xff) == 0xaa)
-                        sd_v2 = true;
-        }
-        /* CMD55 - Get OCR (SD) */
-        {
-                int timeout = 1000;
-                struct mmc_command cmd;
-                cmd.arg = 0;
-                do {
-                        cmd.opcode = MMC_APP_CMD;
-                        cmd.flags = MMC_RSP_R1;
-                        cmd.arg = 0;
-                        err = sdhi_boot_request(base, &cmd);
-                        if (err)
-                                break;
-                        cmd.opcode = SD_APP_OP_COND;
-                        cmd.flags = MMC_RSP_R3;
-                        cmd.arg = (VOLTAGES & 0xff8000);
-                        if (sd_v2)
-                                cmd.arg |= OCR_HCS;
-                        cmd.arg |= OCR_FASTBOOT;
-                        err = sdhi_boot_request(base, &cmd);
-                        if (err)
-                                break;
-                        msleep(1);
-                } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
-                if (!err && timeout) {
-                        if (!sd_v2)
-                                sd_v1_0 = true;
-                        high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
-                }
-        }
-        /* CMD1 - Get OCR (MMC) */
-        if (!sd_v2 && !sd_v1_0) {
-                int timeout = 1000;
-                struct mmc_command cmd;
-                do {
-                        cmd.opcode = MMC_SEND_OP_COND;
-                        cmd.arg = VOLTAGES | OCR_HCS;
-                        cmd.flags = MMC_RSP_R3;
-                        err = sdhi_boot_request(base, &cmd);
-                        if (err)
-                                return err;
-                        msleep(1);
-                } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
-                if (!timeout)
-                        return -EAGAIN;
-                high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
-        }
-        /* CMD2 - Get CID */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_ALL_SEND_CID;
-                cmd.arg = 0;
-                cmd.flags = MMC_RSP_R2;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-        }
-        /* CMD3
-         * MMC: Set the relative address
-         * SD:  Get the relative address
-         * Also puts the card into the standby state
-         */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_SET_RELATIVE_ADDR;
-                cmd.arg = 0;
-                cmd.flags = MMC_RSP_R1;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-                cid = cmd.resp[0] >> 16;
-        }
-        /* CMD9 - Get CSD */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_SEND_CSD;
-                cmd.arg = cid << 16;
-                cmd.flags = MMC_RSP_R2;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-        }
-        /* CMD7 - Select the card */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_SELECT_CARD;
-                //cmd.arg = rca << 16;
-                cmd.arg = cid << 16;
-                //cmd.flags = MMC_RSP_R1B;
-                cmd.flags = MMC_RSP_R1;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-        }
-        /* CMD16 - Set the block size */
-        {
-                struct mmc_command cmd;
-                cmd.opcode = MMC_SET_BLOCKLEN;
-                cmd.arg = TMIO_BBS;
-                cmd.flags = MMC_RSP_R1;
-                err = sdhi_boot_request(base, &cmd);
-                if (err)
-                        return err;
-        }
-        return high_capacity;
-}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h
deleted file mode 100644
index 92eaa09f985e..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef SDHI_MOBILE_H
-#define SDHI_MOBILE_H
-#include <linux/compiler.h>
-int sdhi_boot_do_read(void __iomem *base, int high_capacity,
-                      unsigned long offset, unsigned short count,
-                      unsigned short *buf);
-int sdhi_boot_init(void __iomem *base);
-#endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..86217db2937a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,5 +1,7 @@
 ifeq ($(CONFIG_OF),y)
+dtb-$(CONFIG_ARCH_ALPINE) += \
+        alpine-db.dtb
 dtb-$(CONFIG_MACH_ASM9260) += \
        alphascale-asm9260-devkit.dtb
 # Keep at91 dtb files sorted alphabetically for each SoC
@@ -42,6 +44,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
        sama5d34ek.dtb \
        sama5d35ek.dtb \
        sama5d36ek.dtb \
+        at91-sama5d4_xplained.dtb \
        at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += \
        atlas6-evb.dtb
@@ -59,13 +62,15 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
        bcm4708-netgear-r6300-v2.dtb \
        bcm47081-asus-rt-n18u.dtb \
        bcm47081-buffalo-wzr-600dhp2.dtb \
-        bcm47081-buffalo-wzr-900dhp.dtb
+        bcm47081-buffalo-wzr-900dhp.dtb \
+        bcm4709-netgear-r8000.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += \
        bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
        bcm911360_entphn.dtb \
        bcm911360k.dtb \
-        bcm958300k.dtb
+        bcm958300k.dtb \
+        bcm958305k.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
        bcm28155-ap.dtb \
        bcm21664-garnet.dtb
@@ -165,6 +170,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
        kirkwood-lsxhl.dtb \
        kirkwood-mplcec4.dtb \
        kirkwood-mv88f6281gtw-ge.dtb \
+        kirkwood-nas2big.dtb \
        kirkwood-net2big.dtb \
        kirkwood-net5big.dtb \
        kirkwood-netgear_readynas_duo_v2.dtb \
@@ -199,6 +205,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
        ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_MACH_MESON6) += \
        meson6-atv1200.dtb
+dtb-$(CONFIG_MACH_MESON8) += \
+        meson8-minix-neo-x8.dtb
 dtb-$(CONFIG_ARCH_MMP) += \
        pxa168-aspenite.dtb \
        pxa910-dkb.dtb \
@@ -299,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6q-wandboard.dtb \
        imx6q-wandboard-revb1.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
-        imx6sl-evk.dtb
+        imx6sl-evk.dtb \
+        imx6sl-warp.dtb
 dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-sabreauto.dtb \
+        imx6sx-sdb-reva.dtb \
        imx6sx-sdb.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-qds.dtb \
@@ -386,6 +396,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
        omap3-overo-storm-tobi.dtb \
        omap3-overo-summit.dtb \
        omap3-overo-tobi.dtb \
+        omap3-pandora-600mhz.dtb \
+        omap3-pandora-1ghz.dtb \
        omap3-sbc-t3517.dtb \
        omap3-sbc-t3530.dtb \
        omap3-sbc-t3730.dtb \
@@ -401,7 +413,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \
        am335x-evmsk.dtb \
        am335x-nano.dtb \
        am335x-pepper.dtb \
-        am335x-lxm.dtb
+        am335x-lxm.dtb \
+        am335x-chiliboard.dtb
 dtb-$(CONFIG_ARCH_OMAP4) += \
        omap4-duovero-parlor.dtb \
        omap4-panda.dtb \
@@ -464,25 +477,23 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
        s5pv210-smdkv210.dtb \
        s5pv210-torbreck.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
-        r8a73a4-ape6evm.dtb \
-        r8a73a4-ape6evm-reference.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7778-bockw.dtb \
        r8a7778-bockw-reference.dtb \
        r8a7779-marzen.dtb \
-        sh7372-mackerel.dtb \
+        sh73a0-kzm9g.dtb
-        sh73a0-kzm9g.dtb \
-        sh73a0-kzm9g-reference.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
        emev2-kzm9d.dtb \
        r7s72100-genmai.dtb \
        r8a73a4-ape6evm.dtb \
        r8a7740-armadillo800eva.dtb \
+        r8a7778-bockw.dtb \
        r8a7779-marzen.dtb \
        r8a7790-lager.dtb \
        r8a7791-henninger.dtb \
        r8a7791-koelsch.dtb \
-        r8a7794-alt.dtb
+        r8a7794-alt.dtb \
+        sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += \
        socfpga_arria5_socdk.dtb \
        socfpga_arria10_socdk.dtb \
@@ -577,6 +588,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
 dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
        tegra124-jetson-tk1.dtb \
        tegra124-nyan-big.dtb \
+        tegra124-nyan-blaze.dtb \
        tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_U300) += \
        ste-u300.dtb
@@ -624,11 +636,14 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
        armada-388-db.dtb \
        armada-388-gp.dtb \
        armada-388-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_39X) += \
+        armada-398-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
        armada-xp-axpwifiap.dtb \
        armada-xp-db.dtb \
        armada-xp-gp.dtb \
        armada-xp-lenovo-ix4-300d.dtb \
+        armada-xp-linksys-mamba.dtb \
        armada-xp-matrix.dtb \
        armada-xp-netgear-rn2120.dtb \
        armada-xp-openblocks-ax3-4.dtb \
diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts
new file mode 100644
index 000000000000..dfb5a0802273
--- /dev/null
+++ b/arch/arm/boot/dts/alpine-db.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Alternatively, redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   *   Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *   *   Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+/dts-v1/;
+#include "alpine.dtsi"
+/ {
+        model = "Annapurna Labs Alpine Dev Board";
+        /* no need for anything outside SOC */
+};
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
new file mode 100644
index 000000000000..9af2d60e9a7f
--- /dev/null
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Alternatively, redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   *   Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *   *   Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+/ {
+        /* SOC compatibility */
+        compatible = "al,alpine";
+        /* CPU Configuration */
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "al,alpine-smp";
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+        };
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+                arch-timer {
+                        compatible = "arm,cortex-a15-timer",
+                                     "arm,armv7-timer";
+                        interrupts =
+                                <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                        clock-frequency = <0>; /* Filled by loader */
+                };
+                /* Interrupt Controller */
+                gic: gic@fb001000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        #size-cells = <0>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xfb001000 0x0 0x1000>,
+                              <0x0 0xfb002000 0x0 0x2000>,
+                              <0x0 0xfb004000 0x0 0x1000>,
+                              <0x0 0xfb006000 0x0 0x2000>;
+                        interrupts =
+                                <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+                /* CPU Resume registers */
+                cpu-resume@fbff5ec0 {
+                        compatible = "al,alpine-cpu-resume";
+                        reg = <0x0 0xfbff5ec0 0x0 0x30>;
+                };
+                /* North Bridge Service Registers */
+                sysfabric-service@fb070000 {
+                        compatible = "al,alpine-sysfabric-service", "syscon";
+                        reg = <0x0 0xfb070000 0x0 0x10000>;
+                };
+                /* Performance Monitor Unit */
+                pmu {
+                        compatible = "arm,cortex-a15-pmu";
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                uart0:uart@fd883000 {
+                        compatible = "ns16550a";
+                        reg = <0x0 0xfd883000 0x0 0x1000>;
+                        clock-frequency = <0>; /* Filled by loader */
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+                uart1:uart@0xfd884000 {
+                        compatible = "ns16550a";
+                        reg = <0x0 0xfd884000 0x0 0x1000>;
+                        clock-frequency = <0>; /* Filled by loader */
+                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+                /* Internal PCIe Controller */
+                pcie-internal@0xfbc00000 {
+                        compatible = "pci-host-ecam-generic";
+                        device_type = "pci";
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        #interrupt-cells = <1>;
+                        reg = <0x0 0xfbc00000 0x0 0x100000>;
+                        interrupt-map-mask = <0xf800 0 0 7>;
+                        /* Add legacy interrupts for SATA devices only */
+                        interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
+                                        <0x4800 0 0 1 &gic 0 44 4>;
+                        /* 32 bit non prefetchable memory space */
+                        ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
+                        bus-range = <0x00 0x00>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
new file mode 100644
index 000000000000..310da20a8aa7
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "am335x-chilisom.dtsi"
+/ {
+        model = "AM335x Chiliboard";
+        compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
+                     "ti,am33xx";
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_gpio_pins>;
+                led0 {
+                        label = "led0";
+                        gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+        };
+};
+&am33xx_pinmux {
+        usb1_drvvbus: usb1_drvvbus {
+                pinctrl-single,pins = <
+                        0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
+                >;
+        };
+        sd_pins: pinmux_sd_card {
+                pinctrl-single,pins = <
+                        0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+                        0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+                        0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+                        0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+                        0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+                        0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
+        led_gpio_pins: led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
+                        0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+                >;
+        };
+};
+&ldo4_reg {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+};
+/* Ethernet */
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rmii";
+};
+&phy_sel {
+        rmii-clock-ext;
+};
+/* USB */
+&usb {
+        status = "okay";
+};
+&usb_ctrl_mod {
+        status = "okay";
+};
+&usb1_phy {
+        status = "okay";
+};
+&usb1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_drvvbus>;
+        status = "okay";
+        dr_mode = "host";
+};
+&cppi41dma  {
+        status = "okay";
+};
+/* microSD */
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd_pins>;
+        vmmc-supply = <&ldo4_reg>;
+        bus-width = <0x4>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi
new file mode 100644
index 000000000000..7e9a34dffe21
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy <lisovy@jablotron.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "am33xx.dtsi"
+/ {
+        model = "Grinn AM335x ChiliSOM";
+        compatible = "grinn,am335x-chilisom", "ti,am33xx";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&dcdc2_reg>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+};
+&am33xx_pinmux {
+        pinctrl-names = "default";
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                >;
+        };
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                >;
+        };
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
+                        0x110 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxerr.rmii1_rxerr */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+                        0x13c (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd1.rmii1_rxd1 */
+                        0x140 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd0.rmii1_rxd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_ref_clk.rmii_ref_clk */
+                >;
+        };
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* mdio_data.mdio_data */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+                        /* mdio_clk.mdio_clk */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                >;
+        };
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+        nandflash_pins: nandflash_pins {
+                pinctrl-single,pins = <
+                        0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                        0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                        0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                        0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                        0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                        0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                        0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                        0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+                        0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                        0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_csn0.gpmc_csn0 */
+                        0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_advn_ale.gpmc_advn_ale */
+                        0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_oen_ren.gpmc_oen_ren */
+                        0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_wen.gpmc_wen */
+                        0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0)    /* gpmc_be0n_cle.gpmc_be0n_cle */
+                >;
+        };
+};
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        status = "okay";
+        clock-frequency = <400000>;
+        tps: tps@24 {
+                reg = <0x24>;
+        };
+};
+/include/ "tps65217.dtsi"
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-name = "vdds_dpr";
+                        regulator-always-on;
+                };
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                ldo1_reg: regulator@3 {
+                        regulator-name = "vio,vrtc,vdds";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                ldo2_reg: regulator@4 {
+                        regulator-name = "vdd_3v3aux";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                ldo3_reg: regulator@5 {
+                        regulator-name = "vdd_1v8";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                ldo4_reg: regulator@6 {
+                        regulator-name = "vdd_3v3d";
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
+/* Ethernet MAC */
+&mac {
+        slaves = <1>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+/* NAND Flash */
+&elm {
+        status = "okay";
+};
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nandflash_pins>;
+        ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
+        nand@0,0 {
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wait-on-read = "true";
+                gpmc,wait-on-write = "true";
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index df5fee6b6b4b..87fc7a35e802 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -15,6 +15,7 @@
 #include "am33xx.dtsi"
 #include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
        model = "TI AM335x EVM-SK";
@@ -647,6 +648,16 @@
        cap-power-off-card;
        pinctrl-names = "default";
        pinctrl-0 = <&mmc2_pins>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 &mcasp1 {
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index a3466455b171..5ed4ca6eaf55 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -213,7 +213,9 @@
        pinctrl-0 = <&i2c0_pins>;
        gpio@20 {
-                compatible = "mcp,mcp23017";
+                compatible = "microchip,mcp23017";
+                gpio-controller;
+                #gpio-cells = <2>;
                reg = <0x20>;
        };
@@ -222,7 +224,7 @@
        };
        eeprom@53 {
-                compatible = "mcp,24c02";
+                compatible = "microchip,24c02";
                reg = <0x53>;
                pagesize = <8>;
        };
@@ -297,8 +299,8 @@
                |            |-->0x004FFFFF-> Kernel end
                |            |-->0x00500000-> File system start
                |            |
-                |            |-->0x014FFFFF-> File system end
+                |            |-->0x01FFFFFF-> File system end
-                |            |-->0x01500000-> User data start
+                |            |-->0x02000000-> User data start
                |            |
                |            |-->0x03FFFFFF-> User data end
                |            |-->0x04000000-> Data storage start
@@ -327,12 +329,12 @@
                partition@4 {
                        label = "rootfs";
-                        reg = <0x00500000 0x01000000>; /* 16MB */
+                        reg = <0x00500000 0x01b00000>; /* 27MB */
                };
                partition@5 {
                        label = "user";
-                        reg = <0x01500000 0x02b00000>; /* 43MB */
+                        reg = <0x02000000 0x02000000>; /* 32MB */
                };
                partition@6 {
@@ -343,7 +345,7 @@
 };
 &mac {
-        dual_emac = <1>;
+        dual_emac;
        status = "okay";
 };
@@ -353,11 +355,13 @@
 &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "mii";
        dual_emac_res_vlan = <1>;
 };
 &cpsw_emac1 {
        phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "mii";
        dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 071b56aa0c7e..afb4b3a7bab4 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        sys_clkin_ck: sys_clkin_ck {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
                };
        };
-        am33xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7fc>;
-        };
-        am33xx_pinmux: pinmux@44e10800 {
-                compatible = "pinctrl-single";
-                reg = <0x44e10800 0x0238>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0x7f>;
-        };
        /*
         * XXX: Use a flat representation of the AM33XX interconnect.
         * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
                ranges;
                ti,hwmods = "l3_main";
-                prcm: prcm@44e00000 {
+                l4_wkup: l4_wkup@44c00000 {
-                        compatible = "ti,am3-prcm";
+                        compatible = "ti,am3-l4-wkup", "simple-bus";
-                        reg = <0x44e00000 0x4000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        prcm_clocks: clocks {
+                        ranges = <0 0x44c00000 0x280000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                        prcm: prcm@200000 {
-                        };
+                                compatible = "ti,am3-prcm";
-                };
+                                reg = <0x200000 0x4000>;
-                scrm: scrm@44e10000 {
+                                prcm_clocks: clocks {
-                        compatible = "ti,am3-scrm";
+                                        #address-cells = <1>;
-                        reg = <0x44e10000 0x2000>;
+                                        #size-cells = <0>;
+                                };
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am3-scm", "simple-bus";
+                                reg = <0x210000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x2000>;
+                                am33xx_pinmux: pinmux@800 {
+                                        compatible = "pinctrl-single";
+                                        reg = <0x800 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x7f>;
+                                };
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
                };
-                cm: syscon@44e10000 {
-                        compatible = "ti,am33xx-controlmodule", "syscon";
-                        reg = <0x44e10000 0x800>;
-                };
                intc: interrupt-controller@48200000 {
                        compatible = "ti,am33xx-intc";
                        interrupt-controller;
@@ -350,7 +357,7 @@
                        reg = <0x481cc000 0x2000>;
                        clocks = <&dcan0_fck>;
                        clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                        interrupts = <52>;
                        status = "disabled";
                };
@@ -361,7 +368,7 @@
                        reg = <0x481d0000 0x2000>;
                        clocks = <&dcan1_fck>;
                        clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                        interrupts = <55>;
                        status = "disabled";
                };
@@ -720,7 +727,7 @@
                         */
                        interrupts = <40 41 42 43>;
                        ranges;
-                        syscon = <&cm>;
+                        syscon = <&scm_conf>;
                        status = "disabled";
                        davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
                        status = "disabled";
                        reg = <0x5c000000 0x30000>;
                        interrupts = <67 68 69 70>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                        ti,davinci-ctrl-reg-offset = <0x10000>;
                        ti,davinci-ctrl-mod-reg-offset = <0>;
                        ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        emac_ick: emac_ick {
                #clock-cells = <0>;
                compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 8a099bc10c1e..c80a3e233792 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -66,22 +66,6 @@
                cache-level = <2>;
        };
-        am43xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7f4>;
-        };
-        am43xx_pinmux: pinmux@44e10800 {
-                compatible = "ti,am437-padconf", "pinctrl-single";
-                reg = <0x44e10800 0x31c>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                #interrupt-cells = <1>;
-                interrupt-controller;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0xffffffff>;
-        };
        ocp {
                compatible = "ti,am4372-l3-noc", "simple-bus";
                #address-cells = <1>;
@@ -93,29 +77,58 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prcm: prcm@44df0000 {
+                l4_wkup: l4_wkup@44c00000 {
-                        compatible = "ti,am4-prcm";
+                        compatible = "ti,am4-l4-wkup", "simple-bus";
-                        reg = <0x44df0000 0x11000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        prcm_clocks: clocks {
+                        ranges = <0 0x44c00000 0x287000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                        prcm: prcm@1f0000 {
-                        };
+                                compatible = "ti,am4-prcm";
-                };
+                                reg = <0x1f0000 0x11000>;
-                scrm: scrm@44e10000 {
+                                prcm_clocks: clocks {
-                        compatible = "ti,am4-scrm";
+                                        #address-cells = <1>;
-                        reg = <0x44e10000 0x2000>;
+                                        #size-cells = <0>;
+                                };
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am4-scm", "simple-bus";
+                                reg = <0x210000 0x4000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x4000>;
+                                am43xx_pinmux: pinmux@800 {
+                                        compatible = "ti,am437-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x800 0x31c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0xffffffff>;
+                                };
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
                };
@@ -796,7 +809,7 @@
                };
                ocp2scp0: ocp2scp@483a8000 {
-                        compatible = "ti,omap-ocp2scp";
+                        compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
@@ -815,7 +828,7 @@
                };
                ocp2scp1: ocp2scp@483e8000 {
-                        compatible = "ti,omap-ocp2scp";
+                        compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
@@ -893,7 +906,7 @@
                };
                hdq: hdq@48347000 {
-                        compatible = "ti,am43xx-hdq";
+                        compatible = "ti,am4372-hdq";
                        reg = <0x48347000 0x1000>;
                        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&func_12m_clk>;
@@ -942,7 +955,7 @@
                        clocks = <&dcan0_fck>;
                        clock-names = "fck";
                        reg = <0x481cc000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
@@ -953,7 +966,7 @@
                        clocks = <&dcan1_fck>;
                        clock-names = "fck";
                        reg = <0x481d0000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 0198f5a62b96..378344271746 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -133,6 +133,20 @@
                >;
        };
+        i2c2_pins_default: i2c2_pins_default {
+                pinctrl-single,pins = <
+                        0x1e8 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+                        0x1ec (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+                >;
+        };
+        i2c2_pins_sleep: i2c2_pins_sleep {
+                pinctrl-single,pins = <
+                        0x1e8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x1ec (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
        mmc1_pins_default: pinmux_mmc1_pins_default {
                pinctrl-single,pins = <
                        0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
@@ -263,6 +277,14 @@
        };
 };
+&i2c2 {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&i2c2_pins_default>;
+        pinctrl-1 = <&i2c2_pins_sleep>;
+        clock-frequency = <100000>;
+};
 &epwmss0 {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 1d7109196872..795d68af6df9 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
                };
        };
-        am43xx_pinmux: pinmux@44e10800 {
+        matrix_keypad: matrix_keypad@0 {
+                compatible = "gpio-matrix-keypad";
+                debounce-delay-ms = <5>;
+                col-scan-delay-us = <2>;
+                row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
+                             &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
+                             &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
+                             &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
+                col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
+                             &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
+                             &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
+                             &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
+                linux,keymap = <0x00000201      /* P1 */
+                        0x01000204      /* P4 */
+                        0x02000207      /* P7 */
+                        0x0300020a      /* NUMERIC_STAR */
+                        0x00010202      /* P2 */
+                        0x01010205      /* P5 */
+                        0x02010208      /* P8 */
+                        0x03010200      /* P0 */
+                        0x00020203      /* P3 */
+                        0x01020206      /* P6 */
+                        0x02020209      /* P9 */
+                        0x0302020b      /* NUMERIC_POUND */
+                        0x00030067      /* UP */
+                        0x0103006a      /* RIGHT */
+                        0x0203006c      /* DOWN */
+                        0x03030069>;    /* LEFT */
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
+};
+&am43xx_pinmux {
                cpsw_default: cpsw_default {
                        pinctrl-single,pins = <
                                /* Slave 1 */
@@ -279,47 +320,6 @@
                                0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
                        >;
                };
-        };
-        matrix_keypad: matrix_keypad@0 {
-                        compatible = "gpio-matrix-keypad";
-                        debounce-delay-ms = <5>;
-                        col-scan-delay-us = <2>;
-                        row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
-                                     &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
-                                     &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
-                                     &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
-                        col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
-                                     &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
-                                     &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
-                                     &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
-                        linux,keymap = <0x00000201      /* P1 */
-                                0x01000204      /* P4 */
-                                0x02000207      /* P7 */
-                                0x0300020a      /* NUMERIC_STAR */
-                                0x00010202      /* P2 */
-                                0x01010205      /* P5 */
-                                0x02010208      /* P8 */
-                                0x03010200      /* P0 */
-                                0x00020203      /* P3 */
-                                0x01020206      /* P6 */
-                                0x02020209      /* P9 */
-                                0x0302020b      /* NUMERIC_POUND */
-                                0x00030067      /* UP */
-                                0x0103006a      /* RIGHT */
-                                0x0203006c      /* DOWN */
-                                0x03030069>;    /* LEFT */
-                };
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 51 53 56 62 75 101 152 255>;
-                default-brightness-level = <8>;
-        };
 };
 &mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index cfb49686ab6a..d0c0dfa4ec48 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        sys_clkin_ck: sys_clkin_ck {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index bd48dba16748..15f198e4864d 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -8,7 +8,6 @@
 /dts-v1/;
 #include "dra74x.dtsi"
-#include <dt-bindings/clk/ti-dra7-atl.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -87,6 +86,7 @@
                gpios =  <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
                gpio-fan,speed-map = <0     0>,
                                     <13000 1>;
+                #cooling-cells = <2>;
        };
        extcon_usb1: extcon_usb1 {
@@ -442,6 +442,7 @@
                pinctrl-0 = <&tmp102_pins_default>;
                interrupt-parent = <&gpio7>;
                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+                #thermal-sensor-cells = <1>;
        };
 };
@@ -548,6 +549,61 @@
        pinctrl-0 = <&usb1_pins>;
 };
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
 &usb2 {
        dr_mode = "peripheral";
 };
+&cpu_trips {
+        cpu_alert1: cpu_alert1 {
+                temperature = <50000>; /* millicelsius */
+                hysteresis = <2000>; /* millicelsius */
+                type = "active";
+        };
+};
+&cpu_cooling_maps {
+        map1 {
+                trip = <&cpu_alert1>;
+                cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+        };
+};
+&thermal_zones {
+        board_thermal: board_thermal {
+                polling-delay-passive = <1250>; /* milliseconds */
+                polling-delay = <1500>; /* milliseconds */
+                                /* sensor       ID */
+                thermal-sensors = <&tmp102     0>;
+                board_trips: trips {
+                        board_alert0: board_alert {
+                                temperature = <40000>; /* millicelsius */
+                                hysteresis = <2000>; /* millicelsius */
+                                type = "active";
+                        };
+                        board_crit: board_crit {
+                                temperature = <105000>; /* millicelsius */
+                                hysteresis = <0>; /* millicelsius */
+                                type = "critical";
+                        };
+                };
+                board_cooling_maps: cooling-maps {
+                        map0 {
+                                trip = <&board_alert0>;
+                                cooling-device =
+                                  <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                        };
+                };
+       };
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e993c46bd472..19f3bf271915 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -45,6 +45,15 @@
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
 */
 /dts-v1/;
@@ -55,7 +64,7 @@
        compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
@@ -64,7 +73,7 @@
        };
        soc {
-                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
                internal-regs {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index b10ceb488efe..0f40d5da28c3 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -51,7 +51,7 @@
        compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3f8cc3845a5e..a31207860f34 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -53,7 +53,7 @@
        compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 99eb8a014ac6..00540f292979 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -53,7 +53,7 @@
        compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 6ae36a38beb2..19475e68b8e9 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,7 +64,7 @@
        compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 59f74e66963f..b42b767763aa 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -67,8 +67,7 @@
                     "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
-                stdout-path = &uart0;
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 8a322ad57e5f..ec96f0b36346 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -59,8 +59,8 @@
        compatible = "marvell,armada-370-xp";
        aliases {
-                eth0 = &eth0;
+                serial0 = &uart0;
-                eth1 = &eth1;
+                serial1 = &uart1;
        };
        cpus {
@@ -73,6 +73,11 @@
                };
        };
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
+        };
        soc {
                #address-cells = <2>;
                #size-cells = <1>;
@@ -223,7 +228,7 @@
                                      <0x20250 0x8>;
                        };
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                compatible = "marvell,mpic";
                                #interrupt-cells = <1>;
                                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 27397f151def..00b50db57c9c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
                                compatible = "marvell,aurora-outer-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                                cache-level = <2>;
                                cache-unified;
                                wt-override;
                        };
@@ -232,7 +233,7 @@
                                reg = <0x18330 0x4>;
                        };
-                        interrupt-controller@20000 {
+                        interrupt-controller@20a00 {
                                reg = <0x20a00 0x1d0>, <0x21870 0x58>;
                        };
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 0440891425c0..4eabc9c21f8d 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -55,7 +55,7 @@
        compatible = "marvell,a375-db", "marvell,armada375";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index ba3c57e0af72..c675257f2377 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -60,8 +60,8 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
-                ethernet0 = &eth0;
+                serial0 = &uart0;
-                ethernet1 = &eth1;
+                serial1 = &uart1;
        };
        clocks {
@@ -96,6 +96,11 @@
                };
        };
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
+        };
        soc {
                compatible = "marvell,armada375-mbus", "simple-bus";
                #address-cells = <2>;
@@ -276,7 +281,7 @@
                                status = "disabled";
                        };
-                        serial@12000 {
+                        uart0: serial@12000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12000 0x100>;
                                reg-shift = <2>;
@@ -286,7 +291,7 @@
                                status = "disabled";
                        };
-                        serial@12100 {
+                        uart1: serial@12100 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12100 0x100>;
                                reg-shift = <2>;
@@ -394,7 +399,7 @@
                                reg = <0x20000 0x100>, <0x20180 0x20>;
                        };
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                compatible = "marvell,mpic";
                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                                #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
index 57b9119fb3e0..7219ac3a3d90 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -49,8 +49,7 @@
        compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
        chosen {
-                bootargs = "console=ttyS0,115200";
+                stdout-path = "serial1:115200n8";
-                stdout-path = &uart1;
        };
        memory {
@@ -126,6 +125,13 @@
                                status = "okay";
                        };
+                        pinctrl@18000 {
+                                xhci0_vbus_pins: xhci0-vbus-pins {
+                                        marvell,pins = "mpp44";
+                                        marvell,function = "gpio";
+                                };
+                        };
                        ethernet@30000 {
                                status = "okay";
                                phy = <&phy2>;
@@ -150,6 +156,24 @@
                                phy = <&phy0>;
                                phy-mode = "rgmii-id";
                        };
+                        nfc: flash@d0000 {
+                                status = "okay";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                num-cs = <1>;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                        };
+                        usb3@f0000 {
+                                status = "okay";
+                                usb-phy = <&usb3_phy>;
+                        };
                };
                pcie-controller {
@@ -175,4 +199,20 @@
                        };
                };
        };
+        usb3_phy: usb3_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&reg_xhci0_vbus>;
+        };
+        reg_xhci0_vbus: xhci0-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&xhci0_vbus_pins>;
+                regulator-name = "xhci0-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+        };
 };
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 16512efcd32c..51d1623de53e 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -54,7 +54,7 @@
                "marvell,armada385", "marvell,armada380";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
@@ -99,7 +99,7 @@
                                phy-mode = "rgmii-id";
                        };
-                        usb@50000 {
+                        usb@58000 {
                                status = "ok";
                        };
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 590b383db323..78514ab0b47a 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -48,8 +48,7 @@
        compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
        chosen {
-                bootargs = "console=ttyS0,115200";
+                stdout-path = "serial0:115200n8";
-                stdout-path = &uart0;
        };
        memory {
@@ -135,7 +134,7 @@
                        };
                        /* CON4 */
-                        usb@50000 {
+                        usb@58000 {
                                vcc-supply = <&reg_usb2_0_vbus>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index d99baac72081..1dc6e2341cc2 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -55,7 +55,7 @@
                "marvell,armada385","marvell,armada380";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
@@ -85,6 +85,16 @@
                                clock-frequency = <100000>;
                        };
+                        sdhci@d8000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sdhci_pins>;
+                                broken-cd;
+                                no-1-8-v;
+                                wp-inverted;
+                                bus-width = <8>;
+                                status = "okay";
+                        };
                        serial@12000 {
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 1dff30a81e24..ed2dd8ba4080 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -59,9 +59,13 @@
        aliases {
                gpio0 = &gpio0;
                gpio1 = &gpio1;
-                ethernet0 = &eth0;
+                serial0 = &uart0;
-                ethernet1 = &eth1;
+                serial1 = &uart1;
-                ethernet2 = &eth2;
+        };
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts-extended = <&mpic 3>;
        };
        soc {
@@ -216,7 +220,7 @@
                                status = "disabled";
                        };
-                        serial@12100 {
+                        uart1: serial@12100 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12100 0x100>;
                                reg-shift = <2>;
@@ -368,7 +372,7 @@
                                reg = <0x20000 0x100>, <0x20180 0x20>;
                        };
-                        mpic: interrupt-controller@20000 {
+                        mpic: interrupt-controller@20a00 {
                                compatible = "marvell,mpic";
                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                                #interrupt-cells = <1>;
@@ -435,7 +439,7 @@
                                status = "disabled";
                        };
-                        usb@50000 {
+                        usb@58000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x58000 0x500>;
                                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -548,8 +552,11 @@
                        sdhci@d8000 {
                                compatible = "marvell,armada-380-sdhci";
-                                reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+                                reg-names = "sdhci", "mbus", "conf-sdio3";
-                                interrupts = <0 25 0x4>;
+                                reg = <0xd8000 0x1000>,
+                                        <0xdc000 0x100>,
+                                        <0x18454 0x4>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gateclk 17>;
                                mrvl,clk-delay-cycles = <0x1F>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
new file mode 100644
index 000000000000..094e39c66039
--- /dev/null
+++ b/arch/arm/boot/dts/armada-390.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada 390 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "armada-39x.dtsi"
+/ {
+        soc {
+                internal-regs {
+                        pinctrl@18000 {
+                                compatible = "marvell,mv88f6920-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+};
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
new file mode 100644
index 000000000000..bbf83756c43c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -0,0 +1,153 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 Development Board
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "armada-398.dtsi"
+/ {
+        model = "Marvell Armada 398 Development Board";
+        compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2 GB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+                internal-regs {
+                        spi@10680 {
+                                status = "okay";
+                                pinctrl-0 = <&spi1_pins>;
+                                pinctrl-names = "default";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>;
+                                        spi-max-frequency = <108000000>;
+                                        partition@0 {
+                                                label = "U-Boot";
+                                                reg = <0 0x400000>;
+                                        };
+                                        partition@400000 {
+                                                label = "Filesystem";
+                                                reg = <0x400000 0x1000000>;
+                                        };
+                                };
+                        };
+                        i2c@11000 {
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+                        serial@12000 {
+                                pinctrl-0 = <&uart0_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                        };
+                        serial@12100 {
+                                pinctrl-0 = <&uart1_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                        };
+                        flash@d0000 {
+                                status = "okay";
+                                pinctrl-0 = <&nand_pins>;
+                                pinctrl-names = "default";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                nand-ecc-strength = <8>;
+                                nand-ecc-step-size = <512>;
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
+                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
new file mode 100644
index 000000000000..fdc25914e3a3
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "armada-39x.dtsi"
+/ {
+        compatible = "marvell,armada398", "marvell,armada390";
+        soc {
+                internal-regs {
+                        pinctrl@18000 {
+                                compatible = "marvell,mv88f6928-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
new file mode 100644
index 000000000000..0e85fc15ceda
--- /dev/null
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -0,0 +1,508 @@
+/*
+ * Device Tree Include file for Marvell Armada 39x family of SoCs.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+/ {
+        model = "Marvell Armada 39x family SoC";
+        compatible = "marvell,armada390";
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "marvell,armada-390-smp";
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        soc {
+                compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
+                             "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                interrupt-parent = <&gic>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+                };
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+                        L2: cache-controller@8000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x8000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                        };
+                        scu@c000 {
+                                compatible = "arm,cortex-a9-scu";
+                                reg = <0xc000 0x100>;
+                        };
+                        timer@c600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xc600 0x20>;
+                                interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+                                clocks = <&coreclk 2>;
+                        };
+                        gic: interrupt-controller@d000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #size-cells = <0>;
+                                interrupt-controller;
+                                reg = <0xd000 0x1000>,
+                                      <0xc100 0x100>;
+                        };
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c2: i2c@11200 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11200 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c3: i2c@11300 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11300 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        uart0: serial@12000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        uart1: serial@12100 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        uart2: serial@12200 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12200 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        uart3: serial@12300 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12300 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        pinctrl@18000 {
+                                i2c0_pins: i2c0-pins {
+                                        marvell,pins = "mpp2", "mpp3";
+                                        marvell,function = "i2c0";
+                                };
+                                uart0_pins: uart0-pins {
+                                        marvell,pins = "mpp0", "mpp1";
+                                        marvell,function = "ua0";
+                                };
+                                uart1_pins: uart1-pins {
+                                        marvell,pins = "mpp19", "mpp20";
+                                        marvell,function = "ua1";
+                                };
+                                spi1_pins: spi1-pins {
+                                        marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
+                                        marvell,function = "spi1";
+                                };
+                                nand_pins: nand-pins {
+                                        marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+                                                       "mpp38", "mpp28", "mpp40", "mpp42",
+                                                       "mpp35", "mpp36", "mpp25", "mpp30",
+                                                       "mpp32";
+                                        marvell,function = "dev";
+                                };
+                        };
+                        system-controller@18200 {
+                                compatible = "marvell,armada-390-system-controller",
+                                             "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-390-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
+                        };
+                        coreclk: mvebu-sar@18600 {
+                                compatible = "marvell,armada-390-core-clock";
+                                reg = <0x18600 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
+                        };
+                        mpic: interrupt-controller@20a00 {
+                                compatible = "marvell,mpic";
+                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                                interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        timer@20300 {
+                                compatible = "marvell,armada-380-timer",
+                                             "marvell,armada-xp-timer";
+                                reg = <0x20300 0x30>, <0x21040 0x30>;
+                                interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&mpic 5>,
+                                                      <&mpic 6>;
+                                clocks = <&coreclk 2>, <&coreclk 5>;
+                                clock-names = "nbclk", "fixed";
+                        };
+                        cpurst@20800 {
+                                compatible = "marvell,armada-370-cpu-reset";
+                                reg = <0x20800 0x10>;
+                        };
+                        pmsu@22000 {
+                                compatible = "marvell,armada-390-pmsu",
+                                             "marvell,armada-380-pmsu";
+                                reg = <0x22000 0x1000>;
+                        };
+                        xor@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60a00 0x100>;
+                                clocks = <&gateclk 22>;
+                                status = "okay";
+                                xor00 {
+                                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor01 {
+                                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        xor@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gateclk 28>;
+                                status = "okay";
+                                xor10 {
+                                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor11 {
+                                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        flash@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coredivclk 0>;
+                                status = "disabled";
+                        };
+                        sdhci@d8000 {
+                                compatible = "marvell,armada-380-sdhci";
+                                reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 17>;
+                                mrvl,clk-delay-cycles = <0x1F>;
+                                status = "disabled";
+                        };
+                        coredivclk: clock@e4250 {
+                                compatible = "marvell,armada-390-corediv-clock",
+                                             "marvell,armada-380-corediv-clock";
+                                reg = <0xe4250 0xc>;
+                                #clock-cells = <1>;
+                                clocks = <&mainpll>;
+                                clock-output-names = "nand";
+                        };
+                };
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        msi-parent = <&mpic>;
+                        bus-range = <0x00 0xff>;
+                        ranges =
+                               <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+                        /*
+                         * This port can be either x4 or x1. When
+                         * configured in x4 by the bootloader, then
+                         * pcie@4,0 is not available.
+                         */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+                        /*
+                         * x1 port only available when pcie@1,0 is
+                         * configured as a x1 port
+                         */
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+                };
+        };
+        clocks {
+                /* 2 GHz fixed main PLL */
+                mainpll: mainpll {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <2000000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c1fbab243609..dfd782b44e50 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -59,7 +59,7 @@
        compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 48bdafe17526..103782407618 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -64,7 +64,7 @@
        compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 206aebba01be..565227eacf06 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -65,7 +65,7 @@
        compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 5fb3c8b687cf..06a6a6c1fdf7 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -54,8 +54,7 @@
                     "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
-                stdout-path = &uart0;
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
new file mode 100644
index 000000000000..a2cf2154dcdb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -0,0 +1,393 @@
+/*
+ * Device Tree file for the Linksys WRT1900AC (Mamba).
+ *
+ * Note: this board is shipped with a new generation boot loader that
+ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
+ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be
+ * used.
+ *
+ * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on armada-xp-axpwifiap.dts:
+ *
+ *     Copyright (C) 2013 Marvell
+ *
+ *     Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-xp-mv78230.dtsi"
+/ {
+        model = "Linksys WRT1900AC";
+        compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
+                     "marvell,armadaxp", "marvell,armada-370-xp";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+                        /* Etron EJ168 USB 3.0 controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        /* First mini-PCIe port */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+                        /* Second mini-PCIe port */
+                        pcie@3,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                };
+                internal-regs {
+                        /* J10: VCC, NC, RX, NC, TX, GND  */
+                        serial@12000 {
+                                status = "okay";
+                        };
+                        sata@a0000 {
+                                nr-ports = <1>;
+                                status = "okay";
+                        };
+                        ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy-mode = "rgmii-id";
+                                fixed-link {
+                                        speed = <1000>;
+                                        full-duplex;
+                                };
+                        };
+                        ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy-mode = "rgmii-id";
+                                fixed-link {
+                                        speed = <1000>;
+                                        full-duplex;
+                                };
+                        };
+                        /* USB part of the eSATA/USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                                tmp421@4c {
+                                        compatible = "ti,tmp421";
+                                        reg = <0x4c>;
+                                };
+                                tlc59116@68 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #gpio-cells = <2>;
+                                        compatible = "ti,tlc59116";
+                                        reg = <0x68>;
+                                        wan_amber@0 {
+                                                label = "mamba:amber:wan";
+                                                reg = <0x0>;
+                                        };
+                                        wan_white@1 {
+                                                label = "mamba:white:wan";
+                                                reg = <0x1>;
+                                        };
+                                        wlan_2g@2 {
+                                                label = "mamba:white:wlan_2g";
+                                                reg = <0x2>;
+                                        };
+                                        wlan_5g@3 {
+                                                label = "mamba:white:wlan_5g";
+                                                reg = <0x3>;
+                                        };
+                                        esata@4 {
+                                                label = "mamba:white:esata";
+                                                reg = <0x4>;
+                                        };
+                                        usb2@5 {
+                                                label = "mamba:white:usb2";
+                                                reg = <0x5>;
+                                        };
+                                        usb3_1@6 {
+                                                label = "mamba:white:usb3_1";
+                                                reg = <0x6>;
+                                        };
+                                        usb3_2@7 {
+                                                label = "mamba:white:usb3_2";
+                                                reg = <0x7>;
+                                        };
+                                        wps_white@8 {
+                                                label = "mamba:white:wps";
+                                                reg = <0x8>;
+                                        };
+                                        wps_amber@9 {
+                                                label = "mamba:amber:wps";
+                                                reg = <0x9>;
+                                        };
+                                };
+                        };
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x100000>;  /* 1MB */
+                                        read-only;
+                                };
+                                partition@100000 {
+                                        label = "u_env";
+                                        reg = <0x100000 0x40000>;    /* 256KB */
+                                };
+                                partition@140000 {
+                                        label = "s_env";
+                                        reg = <0x140000 0x40000>;    /* 256KB */
+                                };
+                                partition@900000 {
+                                        label = "devinfo";
+                                        reg = <0x900000 0x100000>;   /* 1MB */
+                                        read-only;
+                                };
+                                /* kernel1 overlaps with rootfs1 by design */
+                                partition@a00000 {
+                                        label = "kernel1";
+                                        reg = <0xa00000 0x2800000>;  /* 40MB */
+                                };
+                                partition@d00000 {
+                                        label = "rootfs1";
+                                        reg = <0xd00000 0x2500000>;  /* 37MB */
+                                };
+                                /* kernel2 overlaps with rootfs2 by design */
+                                partition@3200000 {
+                                        label = "kernel2";
+                                        reg = <0x3200000 0x2800000>; /* 40MB */
+                                };
+                                partition@3500000 {
+                                        label = "rootfs2";
+                                        reg = <0x3500000 0x2500000>; /* 37MB */
+                                };
+                                /*
+                                 * 38MB, last MB is for the BBT, not writable
+                                 */
+                                partition@5a00000 {
+                                        label = "syscfg";
+                                        reg = <0x5a00000 0x2600000>;
+                                };
+                                /*
+                                 * Unused area between "s_env" and "devinfo".
+                                 * Moved here because otherwise the renumbered
+                                 * partitions would break the bootloader
+                                 * supplied bootargs
+                                 */
+                                partition@180000 {
+                                        label = "unused_area";
+                                        reg = <0x180000 0x780000>;   /* 7.5MB */
+                                };
+                        };
+                        spi0: spi@10600 {
+                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "everspin,mr25h256";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <40000000>;
+                                };
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&keys_pin>;
+                pinctrl-names = "default";
+                button@1 {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+                };
+                button@2 {
+                        label = "Factory Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&power_led_pin>;
+                pinctrl-names = "default";
+                power {
+                        label = "mamba:white:power";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+        gpio_fan {
+                /* SUNON HA4010V4-0000-C99 */
+                compatible = "gpio-fan";
+                gpios = <&gpio0 24 0>;
+                gpio-fan,speed-map = <0    0
+                                      4500 1>;
+        };
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+                dsa,ethernet = <&eth0>;
+                dsa,mii-bus = <&mdio>;
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0>;  /* MDIO address 0, switch 0 in tree */
+                        port@0 {
+                                reg = <0>;
+                                label = "lan4";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                label = "lan3";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                label = "lan2";
+                        };
+                        port@3 {
+                                reg = <3>;
+                                label = "lan1";
+                        };
+                        port@4 {
+                                reg = <4>;
+                                label = "internet";
+                        };
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                        };
+                };
+        };
+};
+&pinctrl {
+        keys_pin: keys-pin {
+                marvell,pins = "mpp32", "mpp33";
+                marvell,function = "gpio";
+        };
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+        gpio_fan_pin: gpio-fan-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 56f958eb1ede..f894bc83e957 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -52,7 +52,7 @@
        compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 4a7cbed79b07..8479fdc9e9c2 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -57,7 +57,6 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
-                eth3 = &eth3;
        };
        cpus {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 36ce63a96cc9..661d54c81580 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -57,7 +57,6 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
-                eth3 = &eth3;
        };
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 99cb9a8401b4..1516fc2627f9 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -53,7 +53,7 @@
        compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 0c76d9f05fd0..e3b08fb959e5 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -54,7 +54,7 @@
        compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index e9fb225169aa..6063428fa6a0 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -67,8 +67,7 @@
                     "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
-                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
-                stdout-path = &uart0;
        };
        memory {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 82917236a2fb..013d63f69e36 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -57,7 +57,8 @@
        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
        aliases {
-                eth2 = &eth2;
+                serial2 = &uart2;
+                serial3 = &uart3;
        };
        soc {
@@ -78,6 +79,7 @@
                                compatible = "marvell,aurora-system-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                                cache-level = <2>;
                                cache-unified;
                                wt-override;
                        };
@@ -149,11 +151,11 @@
                        cpuclk: clock-complex@18700 {
                                #clock-cells = <1>;
                                compatible = "marvell,armada-xp-cpu-clock";
-                                reg = <0x18700 0xA0>, <0x1c054 0x10>;
+                                reg = <0x18700 0x24>, <0x1c054 0x10>;
                                clocks = <&coreclk 1>;
                        };
-                        interrupt-controller@20000 {
+                        interrupt-controller@20a00 {
                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                        };
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index fec1fca2ad66..9991240b7438 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -167,7 +167,13 @@
                        macb1: ethernet@f802c000 {
                                phy-mode = "rmii";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                status = "okay";
+                                ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
                        };
                        dbgu: serial@ffffee00 {
@@ -188,6 +194,11 @@
                                                        <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
                                        };
+                                        pinctrl_key_gpio: key_gpio_0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
                                        pinctrl_mmc0_cd: mmc0_cd {
                                                atmel,pins =
                                                        <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
@@ -276,6 +287,9 @@
        gpio_keys {
                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_key_gpio>;
                bp3 {
                        label = "PB_USER";
                        gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
new file mode 100644
index 000000000000..c740e1a2a3a5
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -0,0 +1,241 @@
+/*
+ * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
+ *
+ *  Copyright (C) 2015 Atmel,
+ *                2015 Josh Wu <josh.wu@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+/ {
+        model = "Atmel SAMA5D4 Xplained";
+        compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
+        chosen {
+                bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
+        };
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+                main_xtal {
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        spi0: spi@f8010000 {
+                                cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+                                status = "okay";
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+                        i2c0: i2c@f8014000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@f8020000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                                phy0: ethernet-phy@1 {
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                                        reg = <1>;
+                                };
+                        };
+                        mmc1: mmc@fc000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 3 0>;
+                                };
+                        };
+                        usart3: serial@fc00c000 {
+                                status = "okay";
+                        };
+                        usart4: serial@fc010000 {
+                                status = "okay";
+                        };
+                        adc0: adc@fc034000 {
+                                atmel,adc-vref = <3300>;
+                                status = "okay";
+                        };
+                        watchdog@fc068640 {
+                                status = "okay";
+                        };
+                        pinctrl@fc06a000 {
+                                board {
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+                                        };
+                                        pinctrl_key_gpio: key_gpio_0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                };
+                        };
+                };
+                usb0: gadget@00400000 {
+                        atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+                usb1: ohci@00500000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0
+                                           &pioE 11 GPIO_ACTIVE_HIGH
+                                           &pioE 14 GPIO_ACTIVE_HIGH
+                                          >;
+                        status = "okay";
+                };
+                usb2: ehci@00600000 {
+                        status = "okay";
+                };
+                nand0: nand@80000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        nand-on-flash-bbt;
+                        atmel,has-pmecc;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_key_gpio>;
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                status = "okay";
+                d8 {
+                        label = "d8";
+                        gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
+                        status = "disabled";
+                };
+                d10 {
+                        label = "d10";
+                        gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 9198b719d0ef..89ef4a540db5 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -115,6 +115,10 @@
                                };
                        };
+                        ssc0: ssc@f8008000 {
+                                status = "okay";
+                        };
                        spi0: spi@f8010000 {
                                cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
                                status = "okay";
@@ -127,6 +131,13 @@
                        i2c0: i2c@f8014000 {
                                status = "okay";
+                                wm8904: codec@1a {
+                                        compatible = "wlf,wm8904";
+                                        reg = <0x1a>;
+                                        clocks = <&pck2>;
+                                        clock-names = "mclk";
+                                };
                        };
                        macb0: ethernet@f8020000 {
@@ -171,6 +182,10 @@
                                                atmel,pins =
                                                        <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
                                        };
+                                        pinctrl_pck2_as_audio_mck: pck2_as_audio_mck {
+                                                atmel,pins =
+                                                        <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
                                        pinctrl_usba_vbus: usba_vbus {
                                                atmel,pins =
                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
@@ -244,8 +259,6 @@
        gpio_keys {
                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_key_gpio>;
@@ -257,4 +270,42 @@
                        gpio-key,wakeup;
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                status = "okay";
+                d8 {
+                        label = "d8";
+                        /* PE28, conflicts with usart4 rts pin */
+                        gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
+                };
+                d9 {
+                        label = "d9";
+                        gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
+                };
+                d10 {
+                        label = "d10";
+                        gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        sound {
+                compatible = "atmel,asoc-wm8904";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
+                atmel,model = "wm8904 @ SAMA5D4EK";
+                atmel,audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "IN1L", "Line In Jack",
+                        "IN1R", "Line In Jack";
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8904>;
+        };
 };
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 21c2b504f977..4fb333bd1f85 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -356,9 +356,13 @@
                        };
                        st: timer@fffffd00 {
-                                compatible = "atmel,at91rm9200-st";
+                                compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
                                reg = <0xfffffd00 0x100>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                watchdog {
+                                        compatible = "atmel,at91rm9200-wdt";
+                                };
                        };
                        rtc: rtc@fffffe00 {
@@ -830,7 +834,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91rm9200-usart";
+                                compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 62d25b14deb8..d88fe62a2b2e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -753,7 +753,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index d55fdf2487ef..bf8d1856a55a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -276,7 +276,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index e4f61a979a57..111889b556cf 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -762,7 +762,7 @@
                        };
                        dbgu: serial@ffffee00 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 17b879990914..a7da0dd0c98f 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,7 @@
 */
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_isi.dtsi"
 #include "at91sam9x5_usart3.dtsi"
 #include "at91sam9x5_macb0.dtsi"
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 1e4c49c584d3..707fd4ea58f5 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -16,10 +16,28 @@
        ahb {
                apb {
+                        spi0: spi@f0000000 {
+                                status = "disabled";
+                        };
+                        mmc1: mmc@f000c000 {
+                                status = "disabled";
+                        };
+                        i2c0: i2c@f8010000 {
+                                ov2640: camera@0x30 {
+                                        status = "okay";
+                                };
+                        };
                        macb0: ethernet@f802c000 {
                                phy-mode = "rmii";
                                status = "okay";
                        };
+                        isi: isi@f8048000 {
+                                status = "okay";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 8ec05b11298a..70e59c5ceb2f 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -893,7 +893,7 @@
                        };
                        dbgu: serial@ffffee00 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 0c53a375ba99..a9e35dfc12d9 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -757,7 +757,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
@@ -912,6 +912,15 @@
                                clocks = <&pwm_clk>;
                                status = "disabled";
                        };
+                        usb1: gadget@f803c000 {
+                                compatible = "atmel,at91sam9260-udc";
+                                reg = <0xf803c000 0x4000>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+                                clocks = <&udphs_clk>, <&udpck>;
+                                clock-names = "pclk", "hclk";
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 9575c0d895c9..6e067c8a3502 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -108,6 +108,13 @@
                                                        <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                        };
                                };
+                                usb1 {
+                                        pinctrl_usb1_vbus_sense: usb1_vbus_sense {
+                                                atmel,pins =
+                                                        <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;  /* PB16 gpio usb vbus sense, no pull up and deglitch */
+                                        };
+                                };
                        };
                        spi0: spi@f0000000 {
@@ -120,9 +127,20 @@
                                };
                        };
+                        usb1: gadget@f803c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
                        watchdog@fffffe40 {
                                status = "okay";
                        };
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 40f645b8fe25..ebfd5ce9cb38 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -377,7 +377,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index d221179d0f1a..3aa56ae3410a 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,7 +860,7 @@
                        };
                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
index 98bc877a68ef..8fc45ca4dcb5 100644
--- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -13,6 +13,37 @@
 / {
        ahb {
                apb {
+                        pinctrl@fffff400 {
+                                isi {
+                                        pinctrl_isi_data_0_7: isi-0-data-0-7 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_D0, conflicts with LCDDAT0 */
+                                                        AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D1, conflicts with LCDDAT1 */
+                                                        AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D2, conflicts with LCDDAT2 */
+                                                        AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D3, conflicts with LCDDAT3 */
+                                                        AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D4, conflicts with LCDDAT4 */
+                                                        AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D5, conflicts with LCDDAT5 */
+                                                        AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D6, conflicts with LCDDAT6 */
+                                                        AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE     /* ISI_D7, conflicts with LCDDAT7 */
+                                                        AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_PCK, conflicts with LCDDAT12 */
+                                                        AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_HSYNC, conflicts with LCDDAT14 */
+                                                        AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* ISI_VSYNC, conflicts with LCDDAT13 */
+                                        };
+                                        pinctrl_isi_data_8_9: isi-0-data-8-9 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE    /* ISI_D8, conflicts with LCDDAT8 */
+                                                        AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;   /* ISI_D9, conflicts with LCDDAT9 */
+                                        };
+                                        pinctrl_isi_data_10_11: isi-0-data-10-11 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* ISI_D10, conflicts with LCDDAT10 */
+                                                        AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with LCDDAT11 */
+                                        };
+                                };
+                        };
                        pmc: pmc@fffffc00 {
                                periphck {
                                        isi_clk: isi_clk {
@@ -21,6 +52,21 @@
                                        };
                                };
                        };
+                        isi: isi@f8048000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf8048000 0x4000>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi_data_0_7>;
+                                clocks = <&isi_clk>;
+                                clock-names = "isi_clk";
+                                status = "disabled";
+                                port {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 229d6c24a9c4..26112ebd15fc 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -42,6 +42,10 @@
                                        };
                                };
                        };
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index bd16bd360272..cc83a37a7311 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -59,6 +59,16 @@
                                status = "okay";
                        };
+                        isi: isi@f8048000 {
+                                status = "disabled";
+                                port {
+                                        isi_0: endpoint@0 {
+                                                remote-endpoint = <&ov2640_0>;
+                                                bus-width = <8>;
+                                        };
+                                };
+                        };
                        i2c0: i2c@f8010000 {
                                status = "okay";
@@ -66,9 +76,47 @@
                                        compatible = "wm8731";
                                        reg = <0x1a>;
                                };
+                                ov2640: camera@0x30 {
+                                        compatible = "ovti,ov2640";
+                                        reg = <0x30>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
+                                        resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
+                                        pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
+                                        clocks = <&pck0>;
+                                        clock-names = "xvclk";
+                                        assigned-clocks = <&pck0>;
+                                        assigned-clock-rates = <25000000>;
+                                        status = "disabled";
+                                        port {
+                                                ov2640_0: endpoint {
+                                                        remote-endpoint = <&isi_0>;
+                                                        bus-width = <8>;
+                                                };
+                                        };
+                                };
                        };
                        pinctrl@fffff400 {
+                                camera_sensor {
+                                        pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */
+                                        };
+                                        pinctrl_sensor_power: sensor_power-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_sensor_reset: sensor_reset-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                mmc0 {
                                        pinctrl_board_mmc0: mmc0-board {
                                                atmel,pins =
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index ff5fb6ab0b97..7b52c33ea69a 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -54,6 +54,42 @@
        /include/ "bcm-cygnus-clock.dtsi"
+        pinctrl: pinctrl@0x0301d0c8 {
+                compatible = "brcm,cygnus-pinmux";
+                reg = <0x0301d0c8 0x30>,
+                      <0x0301d24c 0x2c>;
+        };
+        gpio_crmu: gpio@03024800 {
+                compatible = "brcm,cygnus-crmu-gpio";
+                reg = <0x03024800 0x50>,
+                      <0x03024008 0x18>;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+        gpio_ccm: gpio@1800a000 {
+                compatible = "brcm,cygnus-ccm-gpio";
+                reg = <0x1800a000 0x50>,
+                      <0x0301d164 0x20>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+        };
+        gpio_asiu: gpio@180a5000 {
+                compatible = "brcm,cygnus-asiu-gpio";
+                reg = <0x180a5000 0x668>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                pinmux = <&pinctrl>;
+                interrupt-controller;
+                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+        };
        amba {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -90,6 +126,48 @@
                status = "disabled";
        };
+        pcie0: pcie@18012000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18012000 0x1000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+                linux,pci-domain = <0>;
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x28000000 0 0x00010000
+                          0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
+                status = "disabled";
+        };
+        pcie1: pcie@18013000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18013000 0x1000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+                linux,pci-domain = <1>;
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x48000000 0 0x00010000
+                          0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
+                status = "disabled";
+        };
        uart0: serial@18020000 {
                compatible = "snps,dw-apb-uart";
                reg = <0x18020000 0x100>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index f18c9d9b2f2c..2ed9e5794785 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -45,13 +45,13 @@
                power0 {
                        label = "bcm53xx:green:power";
                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
+                        linux,default-trigger = "default-on";
                };
                power1 {
                        label = "bcm53xx:amber:power";
                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-on";
+                        linux,default-trigger = "default-off";
                };
                usb {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
new file mode 100644
index 000000000000..ea26dd3ec03a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -0,0 +1,77 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Netgear R8000
+ *
+ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm4708.dtsi"
+/ {
+        compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708";
+        model = "Netgear R8000 (BCM4709)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                power0 {
+                        label = "bcm53xx:white:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                5ghz-1 {
+                        label = "bcm53xx:white:5ghz-1";
+                        gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                2ghz {
+                        label = "bcm53xx:white:2ghz";
+                        gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index 0ca0f4e523d0..39ac7840d7ee 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -76,7 +76,7 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                        clock-frequency = <0x4d3f640>;
+                        clock-frequency = <81000000>;
                };
                sun_top_ctrl: syscon@404000 {
@@ -96,6 +96,18 @@
                                     "syscon";
                        reg = <0x452000 0x100>;
                };
+                irq0_intc: interrupt-controller@40a780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        interrupt-parent = <&gic>;
+                        #interrupt-cells = <1>;
+                        reg = <0x40a780 0x8>;
+                        interrupt-controller;
+                        interrupts = <GIC_SPI 0x45 0x0>,
+                                     <GIC_SPI 0x43 0x0>;
+                        brcm,int-map-mask = <0x25c>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+                };
        };
        smpboot {
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index d2ee95280548..7db484323fd6 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -33,6 +33,7 @@
 /dts-v1/;
 #include "bcm-cygnus.dtsi"
+#include "dt-bindings/input/input.h"
 / {
        model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
@@ -50,4 +51,16 @@
        uart3: serial@18023000 {
                status = "okay";
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                hook {
+                        label = "HOOK";
+                        linux,code = <KEY_O>;
+                        gpios = <&gpio_asiu 48 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
index f1bb36f3975c..c9eb8565eac5 100644
--- a/arch/arm/boot/dts/bcm958300k.dts
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -47,6 +47,14 @@
                bootargs = "console=ttyS0,115200";
        };
+        pcie0: pcie@18012000 {
+                status = "okay";
+        };
+        pcie1: pcie@18013000 {
+                status = "okay";
+        };
        uart3: serial@18023000 {
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts
new file mode 100644
index 000000000000..56b429abbedb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958305k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+#include "bcm-cygnus.dtsi"
+/ {
+        model = "Cygnus Wireless Audio (BCM958305K)";
+        compatible = "brcm,bcm58305", "brcm,cygnus";
+        aliases {
+                serial0 = &uart3;
+        };
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index afe678f6d2e9..169a85578fc9 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -29,10 +29,10 @@
 &dm816x_pinmux {
        mcspi1_pins: pinmux_mcspi1_pins {
                pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0)     /* SPI_SCLK */
+                        DM816X_IOPAD(0x0a94, MUX_MODE0)                 /* SPI_SCLK */
-                        DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0)    /* SPI_SCS0 */
+                        DM816X_IOPAD(0x0a98, MUX_MODE0)                 /* SPI_SCS0 */
-                        DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0)     /* SPI_D0 */
+                        DM816X_IOPAD(0x0aa8, MUX_MODE0)                 /* SPI_D0 */
-                        DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0)     /* SPI_D1 */
+                        DM816X_IOPAD(0x0aac, MUX_MODE0)                 /* SPI_D1 */
                >;
        };
@@ -52,13 +52,13 @@
        usb0_pins: pinmux_usb0_pins {
                pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0d00, MUX_MODE0)                 /* USB0_DRVVBUS */
+                        DM816X_IOPAD(0x0d04, MUX_MODE0)                 /* USB0_DRVVBUS */
                >;
        };
-        usb1_pins: pinmux_usb0_pins {
+        usb1_pins: pinmux_usb1_pins {
                pinctrl-single,pins = <
-                        DM816X_IOPAD(0x0d04, MUX_MODE0)                 /* USB1_DRVVBUS */
+                        DM816X_IOPAD(0x0d08, MUX_MODE0)                 /* USB1_DRVVBUS */
                >;
        };
 };
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index f35715bc6992..de8427be830a 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -396,6 +396,29 @@
                                mentor,num-eps = <16>;
                                mentor,ram-bits = <12>;
                                mentor,power = <500>;
+                                dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                                        &cppi41dma  2 0 &cppi41dma  3 0
+                                        &cppi41dma  4 0 &cppi41dma  5 0
+                                        &cppi41dma  6 0 &cppi41dma  7 0
+                                        &cppi41dma  8 0 &cppi41dma  9 0
+                                        &cppi41dma 10 0 &cppi41dma 11 0
+                                        &cppi41dma 12 0 &cppi41dma 13 0
+                                        &cppi41dma 14 0 &cppi41dma  0 1
+                                        &cppi41dma  1 1 &cppi41dma  2 1
+                                        &cppi41dma  3 1 &cppi41dma  4 1
+                                        &cppi41dma  5 1 &cppi41dma  6 1
+                                        &cppi41dma  7 1 &cppi41dma  8 1
+                                        &cppi41dma  9 1 &cppi41dma 10 1
+                                        &cppi41dma 11 1 &cppi41dma 12 1
+                                        &cppi41dma 13 1 &cppi41dma 14 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
                        };
                        usb1: usb@47401800 {
@@ -413,6 +436,43 @@
                                mentor,num-eps = <16>;
                                mentor,ram-bits = <12>;
                                mentor,power = <500>;
+                                dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                                        &cppi41dma 17 0 &cppi41dma 18 0
+                                        &cppi41dma 19 0 &cppi41dma 20 0
+                                        &cppi41dma 21 0 &cppi41dma 22 0
+                                        &cppi41dma 23 0 &cppi41dma 24 0
+                                        &cppi41dma 25 0 &cppi41dma 26 0
+                                        &cppi41dma 27 0 &cppi41dma 28 0
+                                        &cppi41dma 29 0 &cppi41dma 15 1
+                                        &cppi41dma 16 1 &cppi41dma 17 1
+                                        &cppi41dma 18 1 &cppi41dma 19 1
+                                        &cppi41dma 20 1 &cppi41dma 21 1
+                                        &cppi41dma 22 1 &cppi41dma 23 1
+                                        &cppi41dma 24 1 &cppi41dma 25 1
+                                        &cppi41dma 26 1 &cppi41dma 27 1
+                                        &cppi41dma 28 1 &cppi41dma 29 1>;
+                                dma-names =
+                                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                                        "rx14", "rx15",
+                                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                                        "tx14", "tx15";
+                        };
+                        cppi41dma: dma-controller@47402000 {
+                                compatible = "ti,am3359-cppi41";
+                                reg =  <0x47400000 0x1000
+                                        0x47402000 0x1000
+                                        0x47403000 0x1000
+                                        0x47404000 0x4000>;
+                                reg-names = "glue", "controller", "scheduler", "queuemgr";
+                                interrupts = <17>;
+                                interrupt-names = "glue";
+                                #dma-cells = <2>;
+                                #dma-channels = <30>;
+                                #dma-requests = <256>;
                        };
                };
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index a5441d5482a6..9ad829523a13 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -1,5 +1,8 @@
 /include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 / {
@@ -61,7 +64,7 @@
                                  0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0   /* Port 1.0 Mem */
                                  0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
-                        pcie-port@0 {
+                        pcie0: pcie-port@0 {
                                device_type = "pci";
                                status = "disabled";
                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@@ -79,7 +82,7 @@
                                interrupt-map = <0 0 0 0 &intc 16>;
                        };
-                        pcie-port@1 {
+                        pcie1: pcie-port@1 {
                                device_type = "pci";
                                status = "disabled";
                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@@ -154,7 +157,7 @@
                        uart2: serial@12200 {
                                compatible = "ns16550a";
-                                reg = <0x12000 0x100>;
+                                reg = <0x12200 0x100>;
                                reg-shift = <2>;
                                interrupts = <9>;
                                clocks = <&core_clk 0>;
@@ -163,7 +166,7 @@
                        uart3: serial@12300 {
                                compatible = "ns16550a";
-                                reg = <0x12100 0x100>;
+                                reg = <0x12300 0x100>;
                                reg-shift = <2>;
                                interrupts = <10>;
                                clocks = <&core_clk 0>;
@@ -448,6 +451,11 @@
                                        marvell,function = "gpio";
                                };
+                                pmx_pcie1_clkreq: pmx-pcie1-clkreq {
+                                        marvell,pins = "mpp9";
+                                        marvell,function = "pex1";
+                                };
                                pmx_gpio_10: pmx-gpio-10 {
                                        marvell,pins = "mpp10";
                                        marvell,function = "gpio";
@@ -458,6 +466,11 @@
                                        marvell,function = "gpio";
                                };
+                                pmx_pcie0_clkreq: pmx-pcie0-clkreq {
+                                        marvell,pins = "mpp11";
+                                        marvell,function = "pex0";
+                                };
                                pmx_gpio_12: pmx-gpio-12 {
                                        marvell,pins = "mpp12";
                                        marvell,function = "gpio";
@@ -563,6 +576,18 @@
                                        marvell,function = "gpio";
                                };
+                                pmx_spi1_4_7: pmx-spi1-4-7 {
+                                        marvell,pins = "mpp4", "mpp5",
+                                                "mpp6", "mpp7";
+                                        marvell,function = "spi1";
+                                };
+                                pmx_spi1_20_23: pmx-spi1-20-23 {
+                                        marvell,pins = "mpp20", "mpp21",
+                                                "mpp22", "mpp23";
+                                        marvell,function = "spi1";
+                                };
                                pmx_uart1: pmx-uart1 {
                                        marvell,pins = "mpp_uart1";
                                        marvell,function = "uart1";
@@ -582,6 +607,36 @@
                                        marvell,pins = "mpp_nand";
                                        marvell,function = "gpo";
                                };
+                                pmx_i2c1: pmx-i2c1 {
+                                        marvell,pins = "mpp17", "mpp19";
+                                        marvell,function = "twsi";
+                                };
+                                pmx_i2c2: pmx-i2c2 {
+                                        marvell,pins = "mpp_audio1";
+                                        marvell,function = "twsi";
+                                };
+                                pmx_ssp_i2c2: pmx-ssp-i2c2 {
+                                        marvell,pins = "mpp_audio1";
+                                        marvell,function = "ssp/twsi";
+                                };
+                                pmx_i2cmux_0: pmx-i2cmux-0 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt1";
+                                };
+                                pmx_i2cmux_1: pmx-i2cmux-1 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt2";
+                                };
+                                pmx_i2cmux_2: pmx-i2cmux-2 {
+                                        marvell,pins = "twsi";
+                                        marvell,function = "twsi-opt3";
+                                };
                        };
                        core_clk: core-clocks@d0214 {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index b1bd06c6c2a8..aa465904f6cc 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -541,6 +541,14 @@
        };
 };
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
 &usb1 {
        dr_mode = "peripheral";
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a0afce7ad482..5332b57b4950 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -102,17 +102,101 @@
                interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                                      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prm: prm@4ae06000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,dra7-prm";
+                        compatible = "ti,dra7-l4-cfg", "simple-bus";
-                        reg = <0x4ae06000 0x3000>;
+                        #address-cells = <1>;
-                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22c000>;
-                        prm_clocks: clocks {
+                        scm: scm@2000 {
+                                compatible = "ti,dra7-scm-core", "simple-bus";
+                                reg = <0x2000 0x2000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x1400>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0xe00 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+                                dra7_pmx_core: pinmux@1400 {
+                                        compatible = "ti,dra7-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x1400 0x0464>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x3fffffff>;
+                                };
+                        };
+                        cm_core_aon: cm_core_aon@5000 {
+                                compatible = "ti,dra7-cm-core-aon";
+                                reg = <0x5000 0x2000>;
+                                cm_core_aon_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
+                        };
+                        cm_core: cm_core@8000 {
+                                compatible = "ti,dra7-cm-core";
+                                reg = <0x8000 0x3000>;
+                                cm_core_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                cm_core_clockdomains: clockdomains {
+                                };
                        };
+                };
-                        prm_clockdomains: clockdomains {
+                l4_wkup: l4@4ae00000 {
+                        compatible = "ti,dra7-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x3f000>;
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
+                        };
+                        prm: prm@6000 {
+                                compatible = "ti,dra7-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                prm_clockdomains: clockdomains {
+                                };
                        };
                };
@@ -185,36 +269,16 @@
                        };
                };
-                cm_core_aon: cm_core_aon@4a005000 {
+                bandgap: bandgap@4a0021e0 {
-                        compatible = "ti,dra7-cm-core-aon";
+                        reg = <0x4a0021e0 0xc
-                        reg = <0x4a005000 0x2000>;
+                                0x4a00232c 0xc
+                                0x4a002380 0x2c
-                        cm_core_aon_clocks: clocks {
+                                0x4a0023C0 0x3c
-                                #address-cells = <1>;
+                                0x4a002564 0x8
-                                #size-cells = <0>;
+                                0x4a002574 0x50>;
-                        };
+                                compatible = "ti,dra752-bandgap";
+                                interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-                        cm_core_aon_clockdomains: clockdomains {
+                                #thermal-sensor-cells = <1>;
-                        };
-                };
-                cm_core: cm_core@4a008000 {
-                        compatible = "ti,dra7-cm-core";
-                        reg = <0x4a008000 0x3000>;
-                        cm_core_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        cm_core_clockdomains: clockdomains {
-                        };
-                };
-                counter32k: counter@4ae04000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4ae04000 0x40>;
-                        ti,hwmods = "counter_32k";
                };
                dra7_ctrl_core: ctrl_core@4a002000 {
@@ -227,28 +291,6 @@
                        reg = <0x4a002e00 0x7c>;
                };
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0 0x4>;
-                        syscon = <&dra7_ctrl_general>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
-                                regulator-name = "pbias_mmc_omap5";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-                dra7_pmx_core: pinmux@4a003400 {
-                        compatible = "ti,dra7-padconf", "pinctrl-single";
-                        reg = <0x4a003400 0x0464>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <32>;
-                        pinctrl-single,function-mask = <0x3fffffff>;
-                };
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
@@ -666,7 +708,6 @@
                        reg = <0x48820000 0x80>;
                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer5";
-                        ti,timer-dsp;
                };
                timer6: timer@48822000 {
@@ -674,8 +715,6 @@
                        reg = <0x48822000 0x80>;
                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer6";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                };
                timer7: timer@48824000 {
@@ -683,7 +722,6 @@
                        reg = <0x48824000 0x80>;
                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer7";
-                        ti,timer-dsp;
                };
                timer8: timer@48826000 {
@@ -691,8 +729,6 @@
                        reg = <0x48826000 0x80>;
                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer8";
-                        ti,timer-dsp;
-                        ti,timer-pwm;
                };
                timer9: timer@4803e000 {
@@ -714,7 +750,6 @@
                        reg = <0x48088000 0x80>;
                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer11";
-                        ti,timer-pwm;
                };
                timer13: timer@48828000 {
@@ -1419,7 +1454,7 @@
                        compatible = "ti,dra7-d_can";
                        ti,hwmods = "dcan1";
                        reg = <0x4ae3c000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+                        syscon-raminit = <&scm_conf 0x558 0>;
                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&dcan1_sys_clk_mux>;
                        status = "disabled";
@@ -1429,12 +1464,23 @@
                        compatible = "ti,dra7-d_can";
                        ti,hwmods = "dcan2";
                        reg = <0x48480000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+                        syscon-raminit = <&scm_conf 0x558 1>;
                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&sys_clkin1>;
                        status = "disabled";
                };
        };
+        thermal_zones: thermal-zones {
+                #include "omap4-cpu-thermal.dtsi"
+                #include "omap5-gpu-thermal.dtsi"
+                #include "omap5-core-thermal.dtsi"
+        };
+};
+&cpu_thermal {
+        polling-delay = <500>; /* milliseconds */
 };
 /include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index daf28110d487..ce0390f081d9 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -377,6 +377,14 @@
        phy-supply = <&ldo4_reg>;
 };
+&omap_dwc3_1 {
+        extcon = <&extcon_usb1>;
+};
+&omap_dwc3_2 {
+        extcon = <&extcon_usb2>;
+};
 &usb1 {
        dr_mode = "peripheral";
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f7fb0d0ef25a..03d742f8d572 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                };
        };
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 00eeed789b4b..cc560a70926f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
                        clock-names = "cpu";
                        clock-latency = <300000>; /* From omap-cpufreq driver */
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                };
                cpu@1 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 99b09a44e269..3b933f74d000 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1493,6 +1493,14 @@
                ti,dividers = <1>, <8>;
        };
+        clkout2_clk: clkout2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkoutmux2_clk_mux>;
+                ti,bit-shift = <8>;
+                reg = <0x06b0>;
+        };
        l3init_960m_gfclk: l3init_960m_gfclk {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 667d323e80a3..19446273e4a7 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -94,3 +94,16 @@
                vdd33a-supply = <&reg_3p3v>;
        };
 };
+&pfc {
+        uart1_pins: uart@e1030000 {
+                renesas,groups = "uart1_ctrl", "uart1_data";
+                renesas,function = "uart1";
+        };
+};
+&uart1 {
+        pinctrl-0 = <&uart1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index cc7bfe0ba40a..bb45694d91bc 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -169,12 +169,18 @@
                clock-names = "sclk";
        };
+        pfc: pfc@e0140200 {
+                compatible = "renesas,pfc-emev2";
+                reg = <0xe0140200 0x100>;
+        };
        gpio0: gpio@e0050000 {
                compatible = "renesas,em-gio";
                reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
                             <0 68 IRQ_TYPE_LEVEL_HIGH>;
                gpio-controller;
+                gpio-ranges = <&pfc 0 0 32>;
                #gpio-cells = <2>;
                ngpios = <32>;
                interrupt-controller;
@@ -186,6 +192,7 @@
                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
                             <0 70 IRQ_TYPE_LEVEL_HIGH>;
                gpio-controller;
+                gpio-ranges = <&pfc 0 32 32>;
                #gpio-cells = <2>;
                ngpios = <32>;
                interrupt-controller;
@@ -197,6 +204,7 @@
                interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
                             <0 72 IRQ_TYPE_LEVEL_HIGH>;
                gpio-controller;
+                gpio-ranges = <&pfc 0 64 32>;
                #gpio-cells = <2>;
                ngpios = <32>;
                interrupt-controller;
@@ -208,6 +216,7 @@
                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
                             <0 74 IRQ_TYPE_LEVEL_HIGH>;
                gpio-controller;
+                gpio-ranges = <&pfc 0 96 32>;
                #gpio-cells = <2>;
                ngpios = <32>;
                interrupt-controller;
@@ -219,6 +228,7 @@
                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
                             <0 76 IRQ_TYPE_LEVEL_HIGH>;
                gpio-controller;
+                gpio-ranges = <&pfc 0 128 31>;
                #gpio-cells = <2>;
                ngpios = <31>;
                interrupt-controller;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 14ab515aa83c..e3bfb11c6ef8 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -176,6 +176,10 @@
                        compatible = "samsung,exynos3250-cmu";
                        reg = <0x10030000 0x20000>;
                        #clock-cells = <1>;
+                        assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
+                                          <&cmu CLK_MOUT_ACLK_266_SUB>;
+                        assigned-clock-parents = <&cmu CLK_FIN_PLL>,
+                                                 <&cmu CLK_FIN_PLL>;
                };
                cmu_dmc: clock-controller@105C0000 {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index adb4f6a97a1d..8de12af7c276 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -75,10 +75,18 @@
                };
        };
+        emmc_pwrseq: pwrseq {
+                pinctrl-0 = <&sd1_cd>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpk1 2 1>;
+        };
        mmc@12550000 {
                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                pinctrl-names = "default";
                vmmc-supply = <&ldo20_reg &buck8_reg>;
+                mmc-pwrseq = <&emmc_pwrseq>;
                status = "okay";
                num-slots = <1>;
@@ -472,6 +480,12 @@
        };
 };
+/* RSTN signal for eMMC */
+&sd1_cd {
+        samsung,pin-pud = <0>;
+        samsung,pin-drv = <0>;
+};
 &pinctrl_1 {
        gpio_power_key: power_key {
                samsung,pins = "gpx1-3";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index b9aeec430527..2657e842e5a5 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -29,6 +29,7 @@
        chosen {
                bootargs = "console=tty1";
+                stdout-path = "serial3:115200n8";
        };
        gpio-keys {
@@ -183,7 +184,20 @@
                        powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
                        reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
                        edid-emulation = <5>;
-                        panel = <&panel>;
+                        ports {
+                                port@0 {
+                                        bridge_out: endpoint {
+                                                remote-endpoint = <&panel_in>;
+                                        };
+                                };
+                                port@1 {
+                                        bridge_in: endpoint {
+                                                remote-endpoint = <&dp_out>;
+                                        };
+                                };
+                        };
                };
        };
@@ -228,6 +242,20 @@
                compatible = "auo,b116xw03";
                power-supply = <&fet6>;
                backlight = <&backlight>;
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&bridge_out>;
+                        };
+                };
+        };
+        mmc3_pwrseq: mmc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */
+                              <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77686 MAX77686_CLK_PMIC>;
+                clock-names = "ext_clock";
        };
 };
@@ -242,7 +270,14 @@
        samsung,link-rate = <0x0a>;
        samsung,lane-count = <2>;
        samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
-        bridge = <&ptn3460>;
+        ports {
+                port@0 {
+                        dp_out: endpoint {
+                                remote-endpoint = <&bridge_in>;
+                        };
+                };
+        };
 };
 &ehci {
@@ -531,17 +566,33 @@
        status = "okay";
        num-slots = <1>;
        broken-cd;
+        cap-sdio-irq;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <2 3>;
        samsung,dw-mshc-ddr-timing = <1 2>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>;
        bus-width = <4>;
        cap-sd-highspeed;
+        mmc-pwrseq = <&mmc3_pwrseq>;
 };
 &pinctrl_0 {
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-1";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        wifi_rst: wifi-rst {
+                samsung,pins = "gpx0-2";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
        power_key_irq: power-key-irq {
                samsung,pins = "gpx1-3";
                samsung,pin-function = <0xf>;
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index f02775487cd4..d03f9b8d376d 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=tty1";
+                stdout-path = "serial3:115200n8";
        };
        gpio-keys {
@@ -429,7 +430,6 @@
 &mmc_0 {
        status = "okay";
        num-slots = <1>;
-        supports-highspeed;
        broken-cd;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
@@ -437,11 +437,8 @@
        samsung,dw-mshc-ddr-timing = <1 2>;
        pinctrl-names = "default";
        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
-        slot@0 {
+        cap-mmc-highspeed;
-                reg = <0>;
-                bus-width = <8>;
-        };
 };
 /*
@@ -451,7 +448,6 @@
 &mmc_1 {
        status = "okay";
        num-slots = <1>;
-        supports-highspeed;
        broken-cd;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
@@ -459,11 +455,8 @@
        samsung,dw-mshc-ddr-timing = <1 2>;
        pinctrl-names = "default";
        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
+        bus-width = <4>;
-        slot@0 {
+        cap-sd-highspeed;
-                reg = <0>;
-                bus-width = <4>;
-        };
 };
 &pinctrl_0 {
@@ -490,7 +483,7 @@
        power_key_irq: power-key-irq {
                samsung,pins = "gpx1-3";
-                samsung,pin-function = <0>;
+                samsung,pin-function = <0xf>;
                samsung,pin-pud = <0>;
                samsung,pin-drv = <0>;
        };
@@ -518,7 +511,7 @@
        lid_irq: lid-irq {
                samsung,pins = "gpx3-5";
-                samsung,pin-function = <0>;
+                samsung,pin-function = <0xf>;
                samsung,pin-pud = <0>;
                samsung,pin-drv = <0>;
        };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 77f656eb8e6b..257e2f10525d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -143,7 +143,7 @@
                compatible = "samsung,exynos4210-mct";
                reg = <0x101C0000 0x800>;
                interrupt-controller;
-                #interrups-cells = <2>;
+                #interrupt-cells = <2>;
                interrupt-parent = <&mct_map>;
                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                             <4 0>, <5 0>;
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index db2c1c4cd900..b82b6fa15f48 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -55,7 +55,7 @@
                samsung,dw-mshc-sdr-timing = <0 4>;
                samsung,dw-mshc-ddr-timing = <0 2>;
                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
                vmmc-supply = <&ldo10_reg>;
                bus-width = <8>;
                cap-mmc-highspeed;
@@ -68,7 +68,7 @@
                samsung,dw-mshc-sdr-timing = <2 3>;
                samsung,dw-mshc-ddr-timing = <1 2>;
                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
                vmmc-supply = <&ldo19_reg>;
                vqmmc-supply = <&ldo13_reg>;
                bus-width = <4>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index c47bb70665c1..0788d08fb43e 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -43,6 +43,10 @@
                pinctrl-names = "default";
        };
+        chosen {
+                stdout-path = "serial3:115200n8";
+        };
        fixed-rate-clocks {
                oscclk {
                        compatible = "samsung,exynos5420-oscclk";
@@ -118,6 +122,19 @@
                compatible = "auo,b116xw03";
                power-supply = <&tps65090_fet6>;
                backlight = <&backlight>;
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&bridge_out>;
+                        };
+                };
+        };
+        mmc1_pwrseq: mmc1_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77802 MAX77802_CLK_32K_CP>;
+                clock-names = "ext_clock";
        };
 };
@@ -137,7 +154,14 @@
        samsung,link-rate = <0x06>;
        samsung,lane-count = <2>;
        samsung,hpd-gpio = <&gpx2 6 0>;
-        bridge = <&ps8625>;
+        ports {
+                port@0 {
+                        dp_out: endpoint {
+                                remote-endpoint = <&bridge_in>;
+                        };
+                };
+        };
 };
 &fimd {
@@ -581,6 +605,8 @@
                interrupt-parent = <&gpx0>;
                pinctrl-names = "default";
                pinctrl-0 = <&max98090_irq>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
        };
        light-sensor@44 {
@@ -595,8 +621,22 @@
                sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
                reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
                lane-count = <2>;
-                panel = <&panel>;
                use-external-pwm;
+                ports {
+                        port@0 {
+                                bridge_out: endpoint {
+                                        remote-endpoint = <&panel_in>;
+                                };
+                        };
+                        port@1 {
+                                bridge_in: endpoint {
+                                        remote-endpoint = <&dp_out>;
+                                };
+                        };
+                };
        };
 };
@@ -659,11 +699,32 @@
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <0 4>;
        samsung,dw-mshc-ddr-timing = <0 2>;
+        samsung,dw-mshc-hs400-timing = <0 2>;
+        samsung,read-strobe-delay = <90>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
        bus-width = <8>;
 };
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        cap-sdio-irq;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+                    <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        mmc-pwrseq = <&mmc1_pwrseq>;
+        vqmmc-supply = <&buck10_reg>;
+};
 &mmc_2 {
        status = "okay";
        num-slots = <1>;
@@ -674,7 +735,7 @@
        samsung,dw-mshc-sdr-timing = <2 3>;
        samsung,dw-mshc-ddr-timing = <1 2>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
        bus-width = <4>;
 };
@@ -683,6 +744,13 @@
        pinctrl-names = "default";
        pinctrl-0 = <&mask_tpm_reset>;
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
        max98090_irq: max98090-irq {
                samsung,pins = "gpx0-2";
                samsung,pin-function = <0>;
@@ -770,6 +838,29 @@
        };
 };
+&pinctrl_1 {
+        /* Adjust WiFi drive strengths lower for EMI */
+        sd1_clk: sd1-clk {
+                samsung,pin-drv = <2>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus8: sd1-bus-width8 {
+                samsung,pin-drv = <2>;
+        };
+};
 &pinctrl_2 {
        pmic_dvs_2: pmic-dvs-2 {
                samsung,pins = "gpj4-2";
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index ba686e40eac7..8b153166ebdb 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -201,6 +201,13 @@
                        samsung,pin-drv = <3>;
                };
+                sd0_rclk: sd0-rclk {
+                        samsung,pins = "gpc0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <1>;
+                        samsung,pin-drv = <3>;
+                };
                sd1_cmd: sd1-cmd {
                        samsung,pins = "gpc1-1";
                        samsung,pin-function = <2>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 8be3d7b489ff..9103f2381a6d 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -80,8 +80,11 @@
                samsung,dw-mshc-ciu-div = <3>;
                samsung,dw-mshc-sdr-timing = <0 4>;
                samsung,dw-mshc-ddr-timing = <0 2>;
+                samsung,dw-mshc-hs400-timing = <0 2>;
+                samsung,read-strobe-delay = <90>;
                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8
+                             &sd0_rclk>;
                bus-width = <8>;
                cap-mmc-highspeed;
        };
@@ -93,7 +96,7 @@
                samsung,dw-mshc-sdr-timing = <2 3>;
                samsung,dw-mshc-ddr-timing = <1 2>;
                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
                bus-width = <4>;
                cap-sd-highspeed;
        };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index b3d2d53820e3..f67b23f303c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -221,7 +221,7 @@
                compatible = "samsung,exynos4210-mct";
                reg = <0x101C0000 0x800>;
                interrupt-controller;
-                #interrups-cells = <1>;
+                #interrupt-cells = <1>;
                interrupt-parent = <&mct_map>;
                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
                                <8>, <9>, <10>, <11>;
@@ -251,6 +251,8 @@
                compatible = "samsung,exynos4210-pd";
                reg = <0x10044000 0x20>;
                #power-domain-cells = <0>;
+                clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
+                clock-names = "asb0", "asb1";
        };
        isp_pd: power-domain@10044020 {
@@ -283,9 +285,11 @@
                         <&clock CLK_MOUT_SW_ACLK300>,
                         <&clock CLK_MOUT_USER_ACLK300_DISP1>,
                         <&clock CLK_MOUT_SW_ACLK400>,
-                         <&clock CLK_MOUT_USER_ACLK400_DISP1>;
+                         <&clock CLK_MOUT_USER_ACLK400_DISP1>,
+                         <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
                clock-names = "oscclk", "pclk0", "clk0",
-                              "pclk1", "clk1", "pclk2", "clk2";
+                              "pclk1", "clk1", "pclk2", "clk2",
+                              "asb0", "asb1";
        };
        pinctrl_0: pinctrl@13400000 {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index a519c863248d..edc25cf1d717 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -264,6 +264,13 @@
                };
        };
+        emmc_pwrseq: pwrseq {
+                pinctrl-0 = <&emmc_nrst_pin>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpd1 0 1>;
+        };
        i2c_2: i2c@12C80000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <66000>;
@@ -298,13 +305,14 @@
 &mmc_0 {
        status = "okay";
+        mmc-pwrseq = <&emmc_pwrseq>;
        broken-cd;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <0 4>;
        samsung,dw-mshc-ddr-timing = <0 2>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
        bus-width = <8>;
        cap-mmc-highspeed;
 };
@@ -316,7 +324,7 @@
        samsung,dw-mshc-sdr-timing = <0 4>;
        samsung,dw-mshc-ddr-timing = <0 2>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
        bus-width = <4>;
        cap-sd-highspeed;
 };
@@ -330,6 +338,15 @@
        };
 };
+&pinctrl_1 {
+        emmc_nrst_pin: emmc-nrst {
+                samsung,pins = "gpd1-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
 &usbdrd_dwc3_0 {
        dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 06737c60d333..412f41d62686 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -42,6 +42,10 @@
                pinctrl-names = "default";
        };
+        chosen {
+                stdout-path = "serial3:115200n8";
+        };
        fixed-rate-clocks {
                oscclk {
                        compatible = "samsung,exynos5420-oscclk";
@@ -119,6 +123,13 @@
                power-supply = <&tps65090_fet6>;
                backlight = <&backlight>;
        };
+        mmc1_pwrseq: mmc1_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+                clocks = <&max77802 MAX77802_CLK_32K_CP>;
+                clock-names = "ext_clock";
+        };
 };
 &adc {
@@ -581,6 +592,8 @@
                interrupt-parent = <&gpx0>;
                pinctrl-names = "default";
                pinctrl-0 = <&max98091_irq>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
        };
        light-sensor@44 {
@@ -641,18 +654,40 @@
        num-slots = <1>;
        broken-cd;
        mmc-hs200-1_8v;
+        mmc-hs400-1_8v;
        cap-mmc-highspeed;
        non-removable;
        card-detect-delay = <200>;
-        clock-frequency = <400000000>;
+        clock-frequency = <800000000>;
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <0 4>;
        samsung,dw-mshc-ddr-timing = <0 2>;
+        samsung,dw-mshc-hs400-timing = <0 2>;
+        samsung,read-strobe-delay = <90>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
        bus-width = <8>;
 };
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        cap-sdio-irq;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+                    <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        mmc-pwrseq = <&mmc1_pwrseq>;
+        vqmmc-supply = <&buck10_reg>;
+};
 &mmc_2 {
        status = "okay";
        num-slots = <1>;
@@ -663,7 +698,7 @@
        samsung,dw-mshc-sdr-timing = <2 3>;
        samsung,dw-mshc-ddr-timing = <1 2>;
        pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
        bus-width = <4>;
 };
@@ -672,6 +707,13 @@
        pinctrl-names = "default";
        pinctrl-0 = <&mask_tpm_reset>;
+        wifi_en: wifi-en {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
        max98091_irq: max98091-irq {
                samsung,pins = "gpx0-2";
                samsung,pin-function = <0>;
@@ -759,6 +801,29 @@
        };
 };
+&pinctrl_1 {
+        /* Adjust WiFi drive strengths lower for EMI */
+        sd1_clk: sd1-clk {
+                samsung,pin-drv = <2>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pin-drv = <2>;
+        };
+        sd1_bus8: sd1-bus-width8 {
+                samsung,pin-drv = <2>;
+        };
+};
 &pinctrl_2 {
        pmic_dvs_2: pmic-dvs-2 {
                samsung,pins = "gpj4-2";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9c21b1583762..dd45e6971bc3 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -75,6 +75,27 @@
                mux-int-port = <1>;
                mux-ext-port = <4>;
        };
+        wvga: display {
+                model = "CLAA057VC01CW";
+                bits-per-pixel = <16>;
+                fsl,pcr = <0xfa208b80>;
+                bus-width = <18>;
+                native-mode = <&wvga_timings>;
+                display-timings {
+                        wvga_timings: 640x480 {
+                                hactive = <640>;
+                                vactive = <480>;
+                                hback-porch = <45>;
+                                hfront-porch = <114>;
+                                hsync-len = <1>;
+                                vback-porch = <33>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock-frequency = <25200000>;
+                        };
+                };
+        };
 };
 &audmux {
@@ -190,6 +211,33 @@
                        >;
                };
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX25_PAD_LD0__LD0               0xe0
+                                MX25_PAD_LD1__LD1               0xe0
+                                MX25_PAD_LD2__LD2               0xe0
+                                MX25_PAD_LD3__LD3               0xe0
+                                MX25_PAD_LD4__LD4               0xe0
+                                MX25_PAD_LD5__LD5               0xe0
+                                MX25_PAD_LD6__LD6               0xe0
+                                MX25_PAD_LD7__LD7               0xe0
+                                MX25_PAD_LD8__LD8               0xe0
+                                MX25_PAD_LD9__LD9               0xe0
+                                MX25_PAD_LD10__LD10             0xe0
+                                MX25_PAD_LD11__LD11             0xe0
+                                MX25_PAD_LD12__LD12             0xe0
+                                MX25_PAD_LD13__LD13             0xe0
+                                MX25_PAD_LD14__LD14             0xe0
+                                MX25_PAD_LD15__LD15             0xe0
+                                MX25_PAD_GPIO_E__LD16           0xe0
+                                MX25_PAD_GPIO_F__LD17           0xe0
+                                MX25_PAD_HSYNC__HSYNC           0xe0
+                                MX25_PAD_VSYNC__VSYNC           0xe0
+                                MX25_PAD_LSCLK__LSCLK           0xe0
+                                MX25_PAD_OE_ACD__OE_ACD         0xe0
+                                MX25_PAD_CONTRAST__CONTRAST     0xe0
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
@@ -202,6 +250,16 @@
        };
 };
+&lcdc {
+        display = <&wvga>;
+        fsl,lpccr = <0x00a903ff>;
+        fsl,lscr1 = <0x00120300>;
+        fsl,dmacr = <0x00020010>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        status = "okay";
+};
 &nfc {
        nand-on-flash-bbt;
        status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 88eebb15da6a..7c4b9f2f9aad 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,48 +17,69 @@
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
+#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
 #define MX25_PAD_A10__A10                       0x008 0x000 0x000 0x00 0x000
 #define MX25_PAD_A10__GPIO_4_0                  0x008 0x000 0x000 0x05 0x000
 #define MX25_PAD_A13__A13                       0x00c 0x22C 0x000 0x00 0x000
 #define MX25_PAD_A13__GPIO_4_1                  0x00c 0x22C 0x000 0x05 0x000
+#define MX25_PAD_A13__LCDC_CLS                  0x00c 0x22C 0x000 0x07 0x000
 #define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x10 0x000
 #define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x15 0x000
+#define MX25_PAD_A14__SIM1_CLK1                 0x010 0x230 0x000 0x16 0x000
+#define MX25_PAD_A14__LCDC_SPL                  0x010 0x230 0x000 0x17 0x000
 #define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x10 0x000
 #define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x15 0x000
+#define MX25_PAD_A15__SIM1_RST1                 0x014 0x234 0x000 0x16 0x000
+#define MX25_PAD_A15__LCDC_PS                   0x014 0x234 0x000 0x17 0x000
 #define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x10 0x000
 #define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x15 0x000
+#define MX25_PAD_A16__SIM1_VEN1                 0x018 0x000 0x000 0x16 0x000
+#define MX25_PAD_A16__LCDC_REV                  0x018 0x000 0x000 0x17 0x000
 #define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x10 0x000
 #define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x15 0x000
+#define MX25_PAD_A17__SIM1_TX                   0x01c 0x238 0x554 0x16 0x000
+#define MX25_PAD_A17__FEC_TX_ERR                0x01c 0x238 0x000 0x17 0x000
 #define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x10 0x000
 #define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x15 0x000
+#define MX25_PAD_A18__SIM1_PD1                  0x020 0x23c 0x550 0x16 0x000
 #define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x17 0x000
 #define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x10 0x000
-#define MX25_PAD_A19__FEC_RX_ER                 0x024 0x240 0x518 0x17 0x000
 #define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x15 0x000
+#define MX25_PAD_A19__SIM1_RX1                  0x024 0x240 0x54c 0x16 0x000
+#define MX25_PAD_A19__FEC_RX_ERR                0x024 0x240 0x518 0x17 0x000
 #define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x10 0x000
 #define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x15 0x000
+#define MX25_PAD_A20__SIM2_CLK1                 0x028 0x244 0x000 0x16 0x000
 #define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x17 0x000
 #define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x10 0x000
 #define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x15 0x000
+#define MX25_PAD_A21__SIM2_RST1                 0x02c 0x248 0x000 0x16 0x000
 #define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x17 0x000
 #define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x10 0x000
 #define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x15 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
+#define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x16 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
 #define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x10 0x000
 #define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x15 0x000
+#define MX25_PAD_A23__SIM2_TX1                  0x034 0x24c 0x560 0x16 0x000
+#define MX25_PAD_A23__FEC_TDATA3                0x034 0x24c 0x000 0x17 0x000
 #define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x10 0x000
 #define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x15 0x000
+#define MX25_PAD_A24__SIM2_PD1                  0x038 0x250 0x55c 0x16 0x000
 #define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x17 0x000
 #define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x10 0x000
@@ -133,20 +154,25 @@
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
 #define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
+#define MX25_PAD_D15__SDHC1_DAT7                0x088 0x280 0x4d8 0x06 0x000
 #define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
 #define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
 #define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
+#define MX25_PAD_D14__SDHC1_DAT6                0x08c 0x284 0x4d4 0x06 0x000
 #define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
 #define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
 #define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
+#define MX25_PAD_D13__SDHC1_DAT5                0x090 0x288 0x4d0 0x06 0x000
 #define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
 #define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
+#define MX25_PAD_D12__SDHC1_DAT4                0x094 0x28c 0x4cc 0x06 0x000
 #define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
 #define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
+#define MX25_PAD_D11__USBOTG_PWR                0x098 0x290 0x000 0x06 0x000
 #define MX25_PAD_D10__D10                       0x09c 0x294 0x000 0x00 0x000
 #define MX25_PAD_D10__GPIO_4_10                 0x09c 0x294 0x000 0x05 0x000
@@ -212,26 +238,33 @@
 #define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x10 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x15 0x000
+#define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
 #define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x10 0x000
 #define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x15 0x001
+#define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x10 0x000
-#define MX25_PAD_LD10__FEC_RX_ER                0x0f0 0x2e8 0x518 0x15 0x001
+#define MX25_PAD_LD10__FEC_RX_ERR               0x0f0 0x2e8 0x518 0x15 0x001
 #define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x10 0x000
 #define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x15 0x001
+#define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
 #define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
 #define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x15 0x001
 #define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__CSPI2_MISO               0x0fc 0x2f4 0x49c 0x02 0x000
 #define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x15 0x000
 #define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__CSPI2_SCLK               0x100 0x2f8 0x494 0x02 0x000
 #define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x15 0x000
 #define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__CSPI2_RDY                0x104 0x2fc 0x498 0x02 0x000
 #define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x15 0x001
 #define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x10 0x000
@@ -244,6 +277,7 @@
 #define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x15 0x000
 #define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__CSPI2_SS0              0x114 0x30c 0x4a4 0x02 0x000
 #define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
 #define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
@@ -257,26 +291,31 @@
 #define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x10 0x000
 #define MX25_PAD_CSI_D2__UART5_RXD_MUX          0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__SIM1_CLK0              0x120 0x318 0x000 0x04 0x000
 #define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x15 0x000
 #define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
 #define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
 #define MX25_PAD_CSI_D3__UART5_TXD_MUX          0x124 0x31c 0x000 0x11 0x000
+#define MX25_PAD_CSI_D3__SIM1_RST0              0x124 0x31c 0x000 0x04 0x000
 #define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
 #define MX25_PAD_CSI_D4__CSI_D4                 0x128 0x320 0x000 0x10 0x000
 #define MX25_PAD_CSI_D4__UART5_RTS              0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__SIM1_VEN0              0x128 0x320 0x000 0x04 0x000
 #define MX25_PAD_CSI_D4__GPIO_1_29              0x128 0x320 0x000 0x15 0x000
 #define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x17 0x000
 #define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
-#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x001
+#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x000
+#define MX25_PAD_CSI_D5__SIM1_TX0               0x12c 0x324 0x000 0x04 0x000
 #define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
 #define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x12 0x001
+#define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
@@ -284,32 +323,32 @@
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
-#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x001
+#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x000
 #define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
 #define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x17 0x000
 #define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
-#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x001
+#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x000
 #define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
 #define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x17 0x000
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
-#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x001
+#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x000
 #define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x12 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
-#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x001
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x000
 #define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x12 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
-#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x001
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x000
 #define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x12 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x001
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x000
 #define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x12 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
@@ -369,8 +408,8 @@
 #define MX25_PAD_UART2_RTS__CC1                 0x188 0x380 0x000 0x13 0x000
 #define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x15 0x000
-#define MX25_PAD_UART2_CTS__FEC_RX_ER           0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x10 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ERR          0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
 #define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
@@ -392,11 +431,11 @@
 #define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x15 0x000
 #define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x15 0x002
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x12 0x002
 #define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x15 0x000
 #define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x10 0x002
+#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x12 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x15 0x000
 #define MX25_PAD_KPP_ROW0__KPP_ROW0             0x1a8 0x3a0 0x000 0x10 0x000
@@ -410,7 +449,7 @@
 #define MX25_PAD_KPP_ROW2__GPIO_2_31            0x1b0 0x3a8 0x000 0x15 0x000
 #define MX25_PAD_KPP_ROW3__KPP_ROW3             0x1b4 0x3ac 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW3__CSI_LD1              0x1b4 0x3ac 0x48c 0x13 0x002
+#define MX25_PAD_KPP_ROW3__CSI_D1               0x1b4 0x3ac 0x48c 0x13 0x002
 #define MX25_PAD_KPP_ROW3__GPIO_3_0             0x1b4 0x3ac 0x000 0x15 0x000
 #define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x10 0x000
@@ -455,9 +494,18 @@
 #define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x15 0x000
 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_TX but that's wrong.
+ */
+#define MX25_PAD_FEC_RDATA1__CAN2_TX            0x1e0 0x3d8 0x000 0x14 0x000
 #define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x15 0x000
 #define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_RX but that's wrong.
+ */
 #define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x14 0x000
 #define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x15 0x000
@@ -471,30 +519,34 @@
 #define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x10 0x000
 #define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x15 0x000
-#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
 #define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x10 0x000
 #define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x16 0x000
 #define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x12 0x000
 #define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x10 0x000
-#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 #define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x12 0x001
+#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 #define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x10 0x000
+#define MX25_PAD_GPIO_C__PWM4_PWMO              0x1fc 0x3f8 0x000 0x11 0x000
+#define MX25_PAD_GPIO_C__I2C2_SCL               0x1fc 0x3f8 0x51c 0x12 0x001
+#define MX25_PAD_GPIO_C__KPP_COL4               0x1fc 0x3f8 0x52c 0x13 0x001
 #define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
 #define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
+#define MX25_PAD_GPIO_D__I2C2_SDA               0x200 0x3fc 0x520 0x12 0x001
 #define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
 #define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
 #define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x11 0x002
 #define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x12 0x000
 #define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
+#define MX25_PAD_GPIO_E__UART4_RXD              0x204 0x400 0x570 0x16 0x002
 #define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
 #define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x12 0x000
 #define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
+#define MX25_PAD_GPIO_F__UART4_TXD              0x208 0x404 0x000 0x16 0x000
 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
 #define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x15 0x000
@@ -505,6 +557,7 @@
 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ           0x214 0x408 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS           0x214 0x408 0x000 0x14 0x000
 #define MX25_PAD_VSTBY_REQ__GPIO_3_17           0x214 0x408 0x000 0x15 0x000
 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x15 0x000
@@ -517,6 +570,7 @@
 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0         0x224 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE0__GPIO_4_30          0x224 0x000 0x000 0x05 0x000
 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 4b063b68db44..6951b66d1ab7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -488,6 +488,7 @@
                                interrupts = <54>;
                                clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -497,6 +498,7 @@
                                interrupts = <55>;
                                clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7198fe3798c6..070e59cbdd8b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -78,7 +78,7 @@
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1f38a052ad4b..7ac4f1af16ac 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -110,6 +110,13 @@
                                        };
                                };
                        };
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                xceiver-supply = <&reg_can0_vcc>;
+                                status = "okay";
+                        };
                };
                apbx@80040000 {
@@ -130,6 +137,13 @@
                                status = "okay";
                        };
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
                        usbphy0: usbphy@8007c000 {
                                status = "okay";
                        };
@@ -143,7 +157,8 @@
        ahb@80080000 {
                usb0: usb@80080000 {
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usb0_otg_apf28dev>;
+                        pinctrl-0 = <&usb0_otg_apf28dev
+                                        &usb0_id_pins_b>;
                        vbus-supply = <&reg_usb0_vbus>;
                        status = "okay";
                };
@@ -156,7 +171,7 @@
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac1_pins_a>;
-                        phy-reset-gpios = <&gpio0 23 0>;
+                        phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
@@ -175,6 +190,14 @@
                        gpio = <&gpio1 23 1>;
                        enable-active-high;
                };
+                reg_can0_vcc: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "can0_vcc";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
        };
        leds {
@@ -200,8 +223,9 @@
                user-button {
                        label = "User button";
-                        gpios = <&gpio0 17 0>;
+                        gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
                        linux,code = <0x100>;
+                        gpio-key,wakeup;
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 47f68ac868d4..25e25f82fbae 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -829,6 +829,19 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
+                                spi3_pins_b: spi3@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP3_SCK__SSP3_SCK
+                                                MX28_PAD_SSP3_MOSI__SSP3_CMD
+                                                MX28_PAD_SSP3_MISO__SSP3_D0
+                                                MX28_PAD_SSP3_SS0__SSP3_D3
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
                                usb0_pins_a: usb0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -1197,6 +1210,7 @@
                        interrupts = <92>;
                        clocks = <&clks 61>;
                        fsl,usbphy = <&usbphy1>;
+                        dr_mode = "host";
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6932928f3b45..b6478e97d6a7 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -318,6 +318,7 @@
                                clocks = <&clks 73>;
                                fsl,usbmisc = <&usbmisc 1>;
                                fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 620b0f030591..e2457138311f 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -197,6 +197,7 @@
                                reg = <0x53f80200 0x0200>;
                                interrupts = <14>;
                                clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -205,6 +206,7 @@
                                reg = <0x53f80400 0x0200>;
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -213,6 +215,7 @@
                                reg = <0x53f80600 0x0200>;
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index c0116cffc513..f46fe9bf0bcb 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -265,6 +265,7 @@
                                interrupts = <14>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -274,6 +275,7 @@
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -283,6 +285,7 @@
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ff4fa7ecacd8..c3e3ca9362fb 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -309,6 +309,7 @@
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
                                fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -318,6 +319,7 @@
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -327,6 +329,7 @@
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 9cd06e5e59f0..d4c4a22db488 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -83,3 +83,7 @@
 &ipu1_di0_disp0 {
        remote-endpoint = <&display0_in>;
 };
+&pwm1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index b413e24288dc..15203f0e9725 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -72,3 +72,7 @@
 &ipu1_di0_disp0 {
        remote-endpoint = <&display0_in>;
 };
+&pwm3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
index 58aa8f2b0f26..e0b7fe8e18f8 100644
--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 44a0e6736bb1..7369d2d7da3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
 * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index 9efd8b0c8011..670bd8c4c847 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
index c2bf8476ce45..0f6044553a24 100644
--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
 * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 93ec79bb6b35..399103b8e2c9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,19 +294,21 @@
 };
 &mipi_dsi {
-        port@2 {
+        ports {
-                reg = <2>;
+                port@2 {
+                        reg = <2>;
-                mipi_mux_2: endpoint {
+                        mipi_mux_2: endpoint {
-                        remote-endpoint = <&ipu2_di0_mipi>;
+                                remote-endpoint = <&ipu2_di0_mipi>;
+                        };
                };
-        };
-        port@3 {
+                port@3 {
-                reg = <3>;
+                        reg = <3>;
-                mipi_mux_3: endpoint {
+                        mipi_mux_3: endpoint {
-                        remote-endpoint = <&ipu2_di1_mipi>;
+                                remote-endpoint = <&ipu2_di1_mipi>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 6a524ca011e7..d033bb182060 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -1,8 +1,48 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        ir_recv: ir-receiver {
@@ -66,6 +106,18 @@
                spdif-controller = <&spdif>;
                spdif-out;
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pinctrl_gpio_key>;
+                pinctrl-names = "default";
+                button_0 {
+                        label = "Button 0";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_0>;
+                };
+        };
 };
 &hdmi {
@@ -170,9 +222,19 @@
                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
                        >;
                };
+                pinctrl_gpio_key: gpio-key {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA8__GPIO3_IO08  0x17059
+                        >;
+                };
        };
 };
+&pwm1 {
+        status = "okay";
+};
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_cubox_i_spdif>;
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 62841e85a91e..151a3db2aea9 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
@@ -50,6 +88,19 @@
                };
        };
+        sound-sgtl5000 {
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "On-board Codec";
+                mux-ext-port = <5>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
        sound-spdif {
                compatible = "fsl,imx-audio-spdif";
                model = "On-board SPDIF";
@@ -59,6 +110,10 @@
        };
 };
+&audmux {
+        status = "okay";
+};
 &can1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@@ -75,16 +130,24 @@
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-        /*
-         * Not fitted on Carrier-1 board... yet
        status = "okay";
+        /* Pro baseboard model */
        rtc: pcf8523@68 {
                compatible = "nxp,pcf8523";
                reg = <0x68>;
        };
-         */
+        /* Pro baseboard model */
+        sgtl5000: sgtl5000@0a {
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
 };
 &i2c2 {
@@ -129,6 +192,20 @@
                        >;
                };
+                pinctrl_hummingboard_pwm1: pwm1grp {
+                        fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
+                };
+                pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+                                MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+                                MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
+                                MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+                                MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+                        >;
+                };
                pinctrl_hummingboard_spdif: hummingboard-spdif {
                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                };
@@ -168,12 +245,28 @@
        };
 };
+&pwm1 {
+         pinctrl-names = "default";
+         pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
+         status = "okay";
+};
+&pwm2 {
+         pinctrl-names = "default";
+         status = "okay";
+};
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
        status = "okay";
 };
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &usbh1 {
        disable-over-current;
        vbus-supply = <&reg_usbh1_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index db9f45b2c573..4a1820309cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -3,6 +3,44 @@
 *
 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
 * MicroSOM.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 &fec {
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 79eac6849d4c..349f82be816e 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd69385d..46b2fed7c319 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,34 @@
        };
 };
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+        max7310_a: gpio@30 {
+                compatible = "maxim,max7310";
+                reg = <0x30>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        max7310_b: gpio@32 {
+                compatible = "maxim,max7310";
+                reg = <0x32>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        max7310_c: gpio@34 {
+                compatible = "maxim,max7310";
+                reg = <0x34>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +293,13 @@
                        >;
                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                        >;
+                };
                pinctrl_pwm3: pwm1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec44314..f74a8ded515f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -82,7 +83,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                dma_apbh: dma-apbh@00110000 {
@@ -122,6 +123,7 @@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0x00a00600 0x20>;
                        interrupts = <1 13 0xf01>;
+                        interrupt-parent = <&intc>;
                        clocks = <&clks IMX6QDL_CLK_TWD>;
                };
@@ -357,6 +359,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM1>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm2: pwm@02084000 {
@@ -367,6 +370,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM2>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm3: pwm@02088000 {
@@ -377,6 +381,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM3>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm4: pwm@0208c000 {
@@ -387,6 +392,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM4>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        can1: flexcan@02090000 {
@@ -598,7 +604,7 @@
                                        regulator-name = "vddpu";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
+                                        regulator-enable-ramp-delay = <150>;
                                        anatop-reg-offset = <0x140>;
                                        anatop-vol-bit-shift = <9>;
                                        anatop-vol-bit-width = <5>;
@@ -658,7 +664,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,8 +699,19 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                         <&clks IMX6QDL_CLK_VPU_AXI>;
+                                #power-domain-cells = <1>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -845,6 +862,7 @@
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbphy = <&usbphy2>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -854,6 +872,7 @@
                                interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -863,6 +882,7 @@
                                interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -1022,19 +1042,24 @@
                                reg = <0x021e0000 0x4000>;
                                status = "disabled";
-                                port@0 {
+                                ports {
-                                        reg = <0>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        port@0 {
+                                                reg = <0>;
-                                        mipi_mux_0: endpoint {
+                                                mipi_mux_0: endpoint {
-                                                remote-endpoint = <&ipu1_di0_mipi>;
+                                                        remote-endpoint = <&ipu1_di0_mipi>;
+                                                };
                                        };
-                                };
-                                port@1 {
+                                        port@1 {
-                                        reg = <1>;
+                                                reg = <1>;
-                                        mipi_mux_1: endpoint {
+                                                mipi_mux_1: endpoint {
-                                                remote-endpoint = <&ipu1_di1_mipi>;
+                                                        remote-endpoint = <&ipu1_di1_mipi>;
+                                                };
                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
new file mode 100644
index 000000000000..64f7decf1fdc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2014, 2015 O.S. Systems Software LTDA.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+/ {
+        model = "WaRP Board";
+        compatible = "warp,imx6sl-warp", "fsl,imx6sl";
+        memory {
+                reg = <0x80000000 0x20000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usb_otg1_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 0 0>;
+                        enable-active-high;
+                };
+                reg_usb_otg2_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 2 0>;
+                        enable-active-high;
+                };
+                reg_1p8v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "1P8V";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+        };
+        usdhc3_pwrseq: usdhc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>,       /* WL_REG_ON */
+                              <&gpio3 25 GPIO_ACTIVE_LOW>,      /* BT_REG_ON */
+                              <&gpio4 4 GPIO_ACTIVE_LOW>,       /* BT_WAKE */
+                              <&gpio4 6 GPIO_ACTIVE_LOW>;       /* BT_RST_N */
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <4>;
+        non-removable;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        mmc-pwrseq = <&usdhc3_pwrseq>;
+        status = "okay";
+};
+&iomuxc {
+        imx6sl-warp {
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x41b0b1
+                                MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x41b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_D12__UART2_RX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D13__UART2_TX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D14__UART2_RTS_B         0x4130B1
+                                MX6SL_PAD_EPDC_D15__UART2_CTS_B         0x4130B1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_AUD_RXC__UART3_RX_DATA        0x41b0b1
+                                MX6SL_PAD_AUD_RXC__UART3_TX_DATA        0x41b0b1
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x417059
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x410059
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x417059
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x417059
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x417059
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x417059
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x417059
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x417059
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x417059
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x417059
+                        >;
+                };
+                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170b9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100b9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170b9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170b9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170b9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170b9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170b9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170b9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170b9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170b9
+                        >;
+                };
+                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170f9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100f9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170f9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170f9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170f9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170f9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170f9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170f9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170f9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170f9
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x417059
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x410059
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x417059
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x417059
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x417059
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x417059
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170b9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100b9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170b9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170b9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170b9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170f9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100f9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170f9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170f9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170f9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170f9
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e054cee..a78e715e3982 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -95,7 +96,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                ocram: sram@00900000 {
@@ -568,7 +569,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -603,7 +604,14 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+                                         <&clks IMX6SL_CLK_GPU2D_PODF>;
+                                #power-domain-cells = <1>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -699,6 +707,7 @@
                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
new file mode 100644
index 000000000000..c76b87cba275
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "imx6sx-sdb.dtsi"
+/ {
+        model = "Freescale i.MX6 SoloX SDB RevA Board";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&qspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_qspi2>;
+        status = "okay";
+        flash0: s25fl128s@0 {
+                reg = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+        flash1: s25fl128s@1 {
+                reg = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 32f07d6b4042..0bfc4e7865b2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -1,197 +1,40 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/dts-v1/;
+#include "imx6sx-sdb.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "imx6sx.dtsi"
 / {
-        model = "Freescale i.MX6 SoloX SDB Board";
+        model = "Freescale i.MX6 SoloX SDB RevB Board";
-        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
-        chosen {
-                stdout-path = &uart1;
-        };
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm3 0 5000000>;
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-        };
-        gpio-keys {
-                compatible = "gpio-keys";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_gpio_keys>;
-                volume-up {
-                        label = "Volume Up";
-                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEUP>;
-                };
-                volume-down {
-                        label = "Volume Down";
-                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEDOWN>;
-                };
-        };
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                vcc_sd3: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_vcc_sd3>;
-                        regulator-name = "VCC_SD3";
-                        regulator-min-microvolt = <3000000>;
-                        regulator-max-microvolt = <3000000>;
-                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_usb_otg1_vbus: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg1>;
-                        regulator-name = "usb_otg1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_usb_otg2_vbus: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg2>;
-                        regulator-name = "usb_otg2_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_psu_5v: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "PSU-5V0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                };
-                reg_lcd_3v3: regulator@4 {
-                        compatible = "regulator-fixed";
-                        reg = <4>;
-                        regulator-name = "lcd-3v3";
-                        gpio = <&gpio3 27 0>;
-                        enable-active-high;
-                };
-                reg_peri_3v3: regulator@5 {
-                        compatible = "regulator-fixed";
-                        reg = <5>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_peri_3v3>;
-                        regulator-name = "peri_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        regulator-always-on;
-                };
-                reg_enet_3v3: regulator@6 {
-                        compatible = "regulator-fixed";
-                        reg = <6>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_enet_3v3>;
-                        regulator-name = "enet_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
-                };
-        };
-        sound {
-                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
-                model = "wm8962-audio";
-                ssi-controller = <&ssi2>;
-                audio-codec = <&codec>;
-                audio-routing =
-                        "Headphone Jack", "HPOUTL",
-                        "Headphone Jack", "HPOUTR",
-                        "Ext Spk", "SPKOUTL",
-                        "Ext Spk", "SPKOUTR",
-                        "AMIC", "MICBIAS",
-                        "IN3R", "AMIC";
-                mux-int-port = <2>;
-                mux-ext-port = <6>;
-        };
-};
-&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux>;
-        status = "okay";
 };
-&fec1 {
+&cpu0 {
-        pinctrl-names = "default";
+        operating-points = <
-        pinctrl-0 = <&pinctrl_enet1>;
+                /* kHz    uV */
-        phy-supply = <&reg_enet_3v3>;
+                996000  1250000
-        phy-mode = "rgmii";
+                792000  1175000
-        phy-handle = <&ethphy1>;
+                396000  1175000
-        status = "okay";
+                >;
+        fsl,soc-operating-points = <
-        mdio {
+                /* ARM kHz      SOC uV */
-                #address-cells = <1>;
+                996000  1250000
-                #size-cells = <0>;
+                792000  1175000
+                396000  1175000
-                ethphy1: ethernet-phy@1 {
+        >;
-                        reg = <1>;
-                };
-                ethphy2: ethernet-phy@2 {
-                        reg = <2>;
-                };
-        };
 };
-&fec2 {
+&i2c1 {
+        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
-        phy-mode = "rgmii";
-        phy-handle = <&ethphy2>;
        status = "okay";
-};
-&i2c1 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1>;
-        status = "okay";
        pmic: pfuze100@08 {
-                compatible = "fsl,pfuze100";
+                compatible = "fsl,pfuze200";
                reg = <0x08>;
                regulators {
@@ -203,14 +46,6 @@
                                regulator-ramp-delay = <6250>;
                        };
-                        sw1c_reg: sw1c {
-                                regulator-min-microvolt = <300000>;
-                                regulator-max-microvolt = <1875000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                                regulator-ramp-delay = <6250>;
-                        };
                        sw2_reg: sw2 {
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <3300000>;
@@ -232,11 +67,6 @@
                                regulator-always-on;
                        };
-                        sw4_reg: sw4 {
-                                regulator-min-microvolt = <800000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
                        swbst_reg: swbst {
                                regulator-min-microvolt = <5000000>;
                                regulator-max-microvolt = <5150000>;
@@ -292,401 +122,24 @@
        };
 };
-&i2c4 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c4>;
-        status = "okay";
-        codec: wm8962@1a {
-                compatible = "wlf,wm8962";
-                reg = <0x1a>;
-                clocks = <&clks IMX6SX_CLK_AUDIO>;
-                DCVDD-supply = <&vgen4_reg>;
-                DBVDD-supply = <&vgen4_reg>;
-                AVDD-supply = <&vgen4_reg>;
-                CPVDD-supply = <&vgen4_reg>;
-                MICVDD-supply = <&vgen3_reg>;
-                PLLVDD-supply = <&vgen4_reg>;
-                SPKVDD1-supply = <&reg_psu_5v>;
-                SPKVDD2-supply = <&reg_psu_5v>;
-        };
-};
-&lcdif1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_lcd>;
-        lcd-supply = <&reg_lcd_3v3>;
-        display = <&display0>;
-        status = "okay";
-        display0: display0 {
-                bits-per-pixel = <16>;
-                bus-width = <24>;
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: timing0 {
-                                clock-frequency = <33500000>;
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <89>;
-                                hfront-porch = <164>;
-                                vback-porch = <23>;
-                                vfront-porch = <10>;
-                                hsync-len = <10>;
-                                vsync-len = <10>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                de-active = <1>;
-                                pixelclk-active = <0>;
-                        };
-                };
-        };
-};
-&pwm3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm3>;
-        status = "okay";
-};
-&snvs_poweroff {
-        status = "okay";
-};
 &qspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_qspi2>;
        status = "okay";
-        flash0: s25fl128s@0 {
+        flash0: n25q256a@0 {
-                reg = <0>;
                #address-cells = <1>;
                #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
+                compatible = "micron,n25q256a";
-                spi-max-frequency = <66000000>;
+                spi-max-frequency = <29000000>;
+                reg = <0>;
        };
-        flash1: s25fl128s@1 {
+        flash1: n25q256a@1 {
-                reg = <1>;
                #address-cells = <1>;
                #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
+                compatible = "micron,n25q256a";
-                spi-max-frequency = <66000000>;
+                spi-max-frequency = <29000000>;
-        };
+                reg = <1>;
-};
-&ssi2 {
-        status = "okay";
-};
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-&uart5 { /* for bluetooth */
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
-        status = "okay";
-};
-&usbotg1 {
-        vbus-supply = <&reg_usb_otg1_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usb_otg1_id>;
-        status = "okay";
-};
-&usbotg2 {
-        vbus-supply = <&reg_usb_otg2_vbus>;
-        dr_mode = "host";
-        status = "okay";
-};
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        non-removable;
-        no-1-8-v;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        status = "okay";
-};
-&usdhc3 {
-        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-        bus-width = <8>;
-        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        vmmc-supply = <&vcc_sd3>;
-        status = "okay";
-};
-&usdhc4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4>;
-        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
-        status = "okay";
-};
-&iomuxc {
-        imx6x-sdb {
-                pinctrl_audmux: audmuxgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
-                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
-                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
-                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
-                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
-                        >;
-                };
-                pinctrl_enet1: enet1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
-                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
-                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
-                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
-                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
-                        >;
-                };
-                pinctrl_enet_3v3: enet3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
-                        >;
-                };
-                pinctrl_enet2: enet2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
-                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
-                        >;
-                };
-                pinctrl_gpio_keys: gpio_keysgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
-                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
-                        >;
-                };
-                pinctrl_i2c1: i2c1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
-                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
-                        >;
-                };
-                pinctrl_i2c4: i2c4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
-                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
-                        >;
-                };
-                pinctrl_lcd: lcdgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
-                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
-                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
-                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
-                        >;
-                };
-                pinctrl_peri_3v3: peri3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
-                        >;
-                };
-                pinctrl_pwm3: pwm3grp-1 {
-                        fsl,pins = <
-                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
-                        >;
-                };
-                pinctrl_qspi2: qspi2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
-                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
-                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
-                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
-                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
-                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
-                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
-                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
-                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
-                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
-                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
-                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
-                        >;
-                };
-                pinctrl_vcc_sd3: vccsd3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
-                        >;
-                };
-                pinctrl_uart1: uart1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
-                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
-                        >;
-                };
-                pinctrl_uart5: uart5grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
-                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
-                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
-                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
-                        >;
-                };
-                pinctrl_usb_otg1: usbotg1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
-                        >;
-                };
-                pinctrl_usb_otg1_id: usbotg1idgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
-                        >;
-                };
-                pinctrl_usb_otg2: usbot2ggrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
-                        >;
-                };
-                pinctrl_usdhc2: usdhc2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
-                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
-                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
-                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
-                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
-                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
-                        >;
-                };
-                pinctrl_usdhc3: usdhc3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
-                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
-                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
-                        >;
-                };
-                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
-                        >;
-                };
-                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
-                        >;
-                };
-                pinctrl_usdhc4: usdhc4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
-                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
-                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
-                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
-                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
-                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
-                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
-                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
-                        >;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
new file mode 100644
index 000000000000..cef04cef3a80
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -0,0 +1,562 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sx.dtsi"
+/ {
+        model = "Freescale i.MX6 SoloX SDB Board";
+        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+        chosen {
+                stdout-path = &uart1;
+        };
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vcc_sd3: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_vcc_sd3>;
+                        regulator-name = "VCC_SD3";
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb_otg1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg1>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb_otg2_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg2>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_psu_5v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "PSU-5V0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+                reg_lcd_3v3: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "lcd-3v3";
+                        gpio = <&gpio3 27 0>;
+                        enable-active-high;
+                };
+                reg_peri_3v3: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_peri_3v3>;
+                        regulator-name = "peri_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+                reg_enet_3v3: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_enet_3v3>;
+                        regulator-name = "enet_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "AMIC", "MICBIAS",
+                        "IN3R", "AMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <6>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-supply = <&reg_enet_3v3>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ethphy1: ethernet-phy@1 {
+                        reg = <1>;
+                };
+                ethphy2: ethernet-phy@2 {
+                        reg = <2>;
+                };
+        };
+};
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy2>;
+        status = "okay";
+};
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        status = "okay";
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks IMX6SX_CLK_AUDIO>;
+                DCVDD-supply = <&vgen4_reg>;
+                DBVDD-supply = <&vgen4_reg>;
+                AVDD-supply = <&vgen4_reg>;
+                CPVDD-supply = <&vgen4_reg>;
+                MICVDD-supply = <&vgen3_reg>;
+                PLLVDD-supply = <&vgen4_reg>;
+                SPKVDD1-supply = <&reg_psu_5v>;
+                SPKVDD2-supply = <&reg_psu_5v>;
+        };
+};
+&lcdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+        display0: display0 {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&snvs_poweroff {
+        status = "okay";
+};
+&ssi2 {
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart5 { /* for bluetooth */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb_otg1_id>;
+        status = "okay";
+};
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        dr_mode = "host";
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        non-removable;
+        no-1-8-v;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <8>;
+        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        vmmc-supply = <&vcc_sd3>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&iomuxc {
+        imx6x-sdb {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
+                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
+                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
+                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
+                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
+                        >;
+                };
+                pinctrl_enet1: enet1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
+                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
+                        >;
+                };
+                pinctrl_enet_3v3: enet3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
+                        >;
+                };
+                pinctrl_enet2: enet2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+                        >;
+                };
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
+                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c4: i2c4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
+                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+                        >;
+                };
+                pinctrl_peri_3v3: peri3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
+                        >;
+                };
+                pinctrl_pwm3: pwm3grp-1 {
+                        fsl,pins = <
+                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+                        >;
+                };
+                pinctrl_qspi2: qspi2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
+                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
+                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
+                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
+                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
+                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
+                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
+                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
+                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
+                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
+                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
+                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
+                        >;
+                };
+                pinctrl_vcc_sd3: vccsd3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
+                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
+                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
+                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
+                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
+                        >;
+                };
+                pinctrl_usb_otg1: usbotg1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
+                        >;
+                };
+                pinctrl_usb_otg1_id: usbotg1idgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
+                        >;
+                };
+                pinctrl_usb_otg2: usbot2ggrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
+                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
+                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
+                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
+                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
+                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
+                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
+                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
+                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
+                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
+                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
+                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
+                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
+                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
+                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee1e7ae..708175d59b9c 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -131,7 +132,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                pmu {
@@ -666,7 +667,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -700,7 +701,10 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                        };
                        iomuxc: iomuxc@020e0000 {
@@ -763,6 +767,7 @@
                                fsl,usbmisc = <&usbmisc 2>;
                                phy_type = "hsic";
                                fsl,anatop = <&anatop>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts
new file mode 100644
index 000000000000..7427ec50b829
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nas2big.dts
@@ -0,0 +1,143 @@
+/*
+ * Device Tree file for LaCie 2Big NAS
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+/dts-v1/;
+#include "kirkwood-netxbig.dtsi"
+/ {
+        model = "LaCie 2Big NAS";
+        compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                rtc@10300 {
+                        /* The on-chip RTC is not powered (no supercap). */
+                        status = "disabled";
+                };
+                spi@10600 {
+                        /*
+                         * A NAND flash is used instead of an SPI flash for
+                         * the other netxbig-compatible boards.
+                         */
+                        status = "disabled";
+                };
+        };
+        fan {
+                /*
+                 * An I2C fan controller (GMT G762) is used but alarm is
+                 * wired to a separate GPIO.
+                 */
+                compatible = "gpio-fan";
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+        };
+        regulators: regulators {
+                status = "okay";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                };
+                clocks {
+                        g762_clk: g762-oscillator {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <32768>;
+                        };
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+&i2c0 {
+        status = "okay";
+        /*
+         * An external I2C RTC (Dallas DS1337S+) is used. This allows
+         * to power-up the board on an RTC alarm. The external RTC can
+         * be kept powered, even when the SoC is off.
+         */
+        rtc@68 {
+                compatible = "dallas,ds1307";
+                reg = <0x68>;
+                interrupts = <43>;
+        };
+        g762@3e {
+                compatible = "gmt,g762";
+                reg = <0x3e>;
+                clocks = <&g762_clk>;
+        };
+};
+&nand {
+        chip-delay = <50>;
+        status = "okay";
+        partition@0 {
+                label = "U-Boot";
+                reg = <0x0 0x100000>;
+        };
+        partition@100000 {
+                label = "uImage";
+                reg = <0x100000 0x1000000>;
+        };
+        partition@1100000 {
+                label = "root";
+                reg = <0x1100000 0x8000000>;
+        };
+        partition@9100000 {
+                label = "unused";
+                reg = <0x9100000 0x6f00000>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts
index 53dc37a3b687..13a44773b6df 100644
--- a/arch/arm/boot/dts/kirkwood-net2big.dts
+++ b/arch/arm/boot/dts/kirkwood-net2big.dts
@@ -27,6 +27,11 @@
                device_type = "memory";
                reg = <0x00000000 0x10000000>;
        };
+        fan {
+                compatible = "gpio-fan";
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+        };
 };
 &regulators {
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index b67ede515bcd..548441384d2a 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -150,5 +150,25 @@
                        interrupts = <0 15 1>;
                        status = "disabled";
                };
+                spifc: spi@c1108c80 {
+                        compatible = "amlogic,meson6-spifc";
+                        reg = <0xc1108c80 0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clk81>;
+                        status = "disabled";
+                };
+                ethmac: ethernet@c9410000 {
+                        compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+                        reg = <0xc9410000 0x10000
+                               0xc1108108 0x4>;
+                        interrupts = <0 8 1>;
+                        interrupt-names = "macirq";
+                        clocks = <&clk81>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
+                };
        };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index d7d351a68944..1237faa63ce6 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -64,3 +64,7 @@
 &uart_AO {
        status = "okay";
 };
+&ethmac {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
new file mode 100644
index 000000000000..4f536bb1f002
--- /dev/null
+++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2014 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "meson8.dtsi"
+/ {
+        model = "MINIX NEO-X8";
+        compatible = "minix,neo-x8", "amlogic,meson8";
+        aliases {
+                serial0 = &uart_AO;
+        };
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                blue {
+                        label = "x8:blue:power";
+                        gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&uart_AO {
+        status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
+};
+&i2c_AO {
+        status = "okay";
+        pinctrl-0 = <&i2c_ao_pins>;
+        pinctrl-names = "default";
+        pmic@32 {
+                compatible = "ricoh,rn5t618";
+                reg = <0x32>;
+                regulators {
+                };
+        };
+        rtc@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+&spifc {
+        status = "okay";
+        pinctrl-0 = <&spi_nor_pins>;
+        pinctrl-names = "default";
+        spi-flash@0 {
+                compatible = "mxicy,mx25l1606e";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+                partition@0 {
+                        label = "boot";
+                        reg = <0x0 0x100000>;
+                };
+                partition@100000 {
+                        label = "env";
+                        reg = <0x100000 0x10000>;
+                };
+        };
+};
+&ir_receiver {
+        status = "okay";
+        pinctrl-0 = <&ir_recv_pins>;
+        pinctrl-names = "default";
+};
+&ethmac {
+        status = "okay";
+        pinctrl-0 = <&eth_pins>;
+        pnictrl-names = "default";
+};
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 1f442a7fe03b..a2ddcb8c545a 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -43,6 +43,7 @@
 *     OTHER DEALINGS IN THE SOFTWARE.
 */
+#include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 / {
@@ -89,4 +90,71 @@
                compatible = "fixed-clock";
                clock-frequency = <141666666>;
        };
+        pinctrl: pinctrl@c1109880 {
+                compatible = "amlogic,meson8-pinctrl";
+                reg = <0xc1109880 0x10>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                gpio: banks@c11080b0 {
+                        reg = <0xc11080b0 0x28>,
+                              <0xc11080e8 0x18>,
+                              <0xc1108120 0x18>,
+                              <0xc1108030 0x30>;
+                        reg-names = "mux", "pull", "pull-enable", "gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpio_ao: ao-bank@c1108030 {
+                        reg = <0xc8100014 0x4>,
+                              <0xc810002c 0x4>,
+                              <0xc8100024 0x8>;
+                        reg-names = "mux", "pull", "gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                uart_ao_a_pins: uart_ao_a {
+                        mux {
+                                groups = "uart_tx_ao_a", "uart_rx_ao_a";
+                                function = "uart_ao";
+                        };
+                };
+                i2c_ao_pins: i2c_mst_ao {
+                        mux {
+                                groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
+                                function = "i2c_mst_ao";
+                        };
+                };
+                spi_nor_pins: nor {
+                        mux {
+                                groups = "nor_d", "nor_q", "nor_c", "nor_cs";
+                                function = "nor";
+                        };
+                };
+                ir_recv_pins: remote {
+                        mux {
+                                groups = "remote_input";
+                                function = "remote";
+                        };
+                };
+                eth_pins: ethernet {
+                        mux {
+                                groups = "eth_tx_clk_50m", "eth_tx_en",
+                                         "eth_txd1", "eth_txd0",
+                                         "eth_rx_clk_in", "eth_rx_dv",
+                                         "eth_rxd1", "eth_rxd0", "eth_mdio",
+                                         "eth_mdc";
+                                function = "ethernet";
+                        };
+                };
+        };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index 106b61b10030..88b3cb128698 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -138,5 +138,10 @@
                        clocks = <&uart_clk>;
                        status = "disabled";
                };
+                wdt: watchdog@010000000 {
+                        compatible = "mediatek,mt6589-wdt";
+                        reg = <0x10000000 0x44>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
index 9565199bce7a..4907c5085d4b 100644
--- a/arch/arm/boot/dts/nspire-classic.dtsi
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -51,6 +51,11 @@
        compatible = "lsi,nspire-classic-ahb-divider";
 };
+&vbus_reg {
+        gpio = <&gpio 5 0>;
+};
 / {
        memory {
                device_type = "memory";
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
index 375b924f60d8..08e0b81b3385 100644
--- a/arch/arm/boot/dts/nspire-cx.dts
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -69,6 +69,10 @@
        0x0709001d      0x070a0033      >;
 };
+&vbus_reg {
+        gpio = <&gpio 2 0>;
+};
 / {
        model = "TI-NSPIRE CX";
        compatible = "ti,nspire-cx";
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index a22ffe633b49..390c91aea16d 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -54,6 +54,20 @@
                clocks = <&ahb_clk>;
        };
+        usb_phy: usb_phy {
+                compatible = "usb-nop-xceiv";
+        };
+        vbus_reg: vbus_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "USB VBUS output";
+                regulator-type = "voltage";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
        ahb {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -65,8 +79,12 @@
                };
                usb0: usb@B0000000 {
+                        compatible = "lsi,zevio-usb";
                        reg = <0xB0000000 0x1000>;
                        interrupts = <8>;
+                        usb-phy = <&usb_phy>;
+                        vbus-supply = <&vbus_reg>;
                };
                usb1: usb@B4000000 {
@@ -105,8 +123,11 @@
                        ranges;
                        gpio: gpio@90000000 {
+                                compatible = "lsi,zevio-gpio";
                                reg = <0x90000000 0x1000>;
                                interrupts = <7>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                        };
                        fast_timer: timer@90010000 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
        compatible = "ti,omap2420", "ti,omap2";
        ocp {
-                prcm: prcm@48008000 {
+                l4: l4@48000000 {
-                        compatible = "ti,omap2-prcm";
+                        compatible = "ti,omap2-l4", "simple-bus";
-                        reg = <0x48008000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x100000>;
-                        prcm_clocks: clocks {
+                        prcm: prcm@8000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap2-prcm";
-                                #size-cells = <0>;
+                                reg = <0x8000 0x1000>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                                prcm_clocks: clocks {
-                        };
+                                        #address-cells = <1>;
-                };
+                                        #size-cells = <0>;
+                                };
-                scrm: scrm@48000000 {
+                                prcm_clockdomains: clockdomains {
-                        compatible = "ti,omap2-scrm";
+                                };
-                        reg = <0x48000000 0x1000>;
+                        };
-                        scrm_clocks: clocks {
+                        scm: scm@0 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x0 0x1000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x0 0x1000>;
+                                omap2420_pmx: pinmux@30 {
+                                        compatible = "ti,omap2420-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0113>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x100>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
-                        scrm_clockdomains: clockdomains {
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x20>;
+                                ti,hwmods = "counter_32k";
                        };
                };
-                counter32k: counter@48004000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x48004000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap2420_pmx: pinmux@48000030 {
-                        compatible = "ti,omap2420-padconf", "pinctrl-single";
-                        reg = <0x48000030 0x0113>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
                gpio1: gpio@48018000 {
                        compatible = "ti,omap2-gpio";
                        reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        mcbsp3_mux_fck: mcbsp3_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <4>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
        compatible = "ti,omap2430", "ti,omap2";
        ocp {
-                prcm: prcm@49006000 {
+                l4_wkup: l4_wkup@49000000 {
-                        compatible = "ti,omap2-prcm";
+                        compatible = "ti,omap2-l4-wkup", "simple-bus";
-                        reg = <0x49006000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x49000000 0x31000>;
-                        prcm_clocks: clocks {
+                        prcm: prcm@6000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap2-prcm";
-                                #size-cells = <0>;
+                                reg = <0x6000 0x1000>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                                prcm_clocks: clocks {
-                        };
+                                        #address-cells = <1>;
-                };
+                                        #size-cells = <0>;
+                                };
-                scrm: scrm@49002000 {
-                        compatible = "ti,omap2-scrm";
-                        reg = <0x49002000 0x1000>;
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@2000 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+                                omap2430_pmx: pinmux@30 {
+                                        compatible = "ti,omap2430-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0154>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x240>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x230 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap2430 {
+                                                        regulator-name = "pbias_mmc_omap2430";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
-                };
-                counter32k: counter@49020000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x49020000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap2430_pmx: pinmux@49002030 {
-                        compatible = "ti,omap2430-padconf", "pinctrl-single";
-                        reg = <0x49002030 0x0154>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
-                omap2_scm_general: tisyscon@49002270 {
-                        compatible = "syscon";
-                        reg = <0x49002270 0x240>;
-                };
-                pbias_regulator: pbias_regulator {
+                        counter32k: counter@20000 {
-                        compatible = "ti,pbias-omap";
+                                compatible = "ti,omap-counter32k";
-                        reg = <0x230 0x4>;
+                                reg = <0x20000 0x20>;
-                        syscon = <&omap2_scm_general>;
+                                ti,hwmods = "counter_32k";
-                        pbias_mmc_reg: pbias_mmc_omap2430 {
-                                regulator-name = "pbias_mmc_omap2430";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
                        };
                };
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        mcbsp1_mux_fck: mcbsp1_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x4>;
        };
        mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x4>;
        };
        mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 8cdca51b6984..7c4dca122a91 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -60,7 +60,6 @@
                ti,model = "omap3beagle";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        gpio_keys {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6d4c46be8c39..a5474113cd50 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -71,7 +71,6 @@
                ti,model = "omap3beagle";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        gpio_keys {
@@ -378,3 +377,55 @@
                };
        };
 };
+&gpmc {
+        status = "ok";
+        ranges = <0 0 0x30000000 0x1000000>;    /* CS0 space, 16MB */
+        /* Chip select 0 */
+        nand@0,0 {
+                reg = <0 0 4>;          /* NAND I/O window, 4 bytes */
+                interrupts = <20>;
+                ti,nand-ecc-opt = "ham1";
+                nand-bus-width = <16>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                gpmc,device-width = <2>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <36>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <24>;
+                gpmc,adv-wr-off-ns = <36>;
+                gpmc,oe-on-ns = <6>;
+                gpmc,oe-off-ns = <48>;
+                gpmc,we-on-ns = <6>;
+                gpmc,we-off-ns = <30>;
+                gpmc,rd-cycle-ns = <72>;
+                gpmc,wr-cycle-ns = <72>;
+                gpmc,access-ns = <54>;
+                gpmc,wr-access-ns = <30>;
+                partition@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+                partition@1c0000 {
+                        label = "U-Boot Env";
+                        reg = <0x260000 0x20000>;
+                };
+                partition@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x400000>;
+                };
+                partition@780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0xf980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index 0ab748cf7749..f5b5a1d96cd7 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -133,6 +133,16 @@
        non-removable;
        bus-width = <4>;
        cap-power-off-card;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 &dss {
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 46eadb21b5ef..2294f5b0aa10 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -73,6 +73,16 @@
        non-removable;
        bus-width = <4>;
        cap-power-off-card;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 &dss {
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index d9e92b654f85..046cd7733c4f 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -16,7 +16,6 @@
                ti,model = "cm-t35";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 169037e5ff53..134d3f27a8ec 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -48,7 +48,6 @@
                ti,model = "devkit8000";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
                ti,audio-routing =
                        "Ext Spk", "PREDRIVEL",
                        "Ext Spk", "PREDRIVER",
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
index 127f3e7c10c4..346552b94d9f 100644
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -106,6 +106,16 @@
        non-removable;
        bus-width = <4>;
        cap-power-off-card;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 &twl_gpio {
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fb3a69604ed5..b9f68817bd6e 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -46,7 +46,6 @@
                ti,model = "gta04";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        spi_lcd {
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 8a63ad2286aa..d5e5cd449b16 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -22,7 +22,6 @@
                compatible = "ti,omap-twl4030";
                ti,model = "igep2";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        vdd33: regulator-vdd33 {
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
index cc8bd0cd8cf8..72f7cdc091fb 100644
--- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -42,4 +42,13 @@
        vmmc-supply = <&lbep5clwmc_wlen>;
        bus-width = <4>;
        non-removable;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
index 9326b282c94a..b899e341874a 100644
--- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -64,4 +64,13 @@
        vmmc-supply = <&lbep5clwmc_wlen>;
        bus-width = <4>;
        non-removable;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index e81fb651d5d0..e63133304a34 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -38,7 +38,6 @@
                ti,model = "lilly-a83x";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        reg_vcc3: vcc3 {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 9938b5dc1909..f2e213931e09 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -16,3 +16,40 @@
        model = "Nokia N9";
        compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
 };
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <1 3>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 2cab149b191c..a29315833ecd 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -9,9 +9,23 @@
 /dts-v1/;
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
 #include <dt-bindings/input/input.h>
+/*
+ * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
+ * for omap AES HW crypto support. When linux kernel try to access memory of AES
+ * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
+ * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
+ * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
+ * There is "unofficial" version of bootloader which enables AES in L3 firewall
+ * but it is not widely used and to prevent kernel crash rather AES is disabled.
+ * There is also no runtime detection code if AES is disabled in L3 firewall...
+ */
+&aes {
+        status = "disabled";
+};
 / {
        model = "Nokia N900";
        compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index c41db94ee9c2..800b379d368d 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -8,7 +8,7 @@
 * published by the Free Software Foundation.
 */
-#include "omap36xx-hs.dtsi"
+#include "omap36xx.dtsi"
 / {
        cpus {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index 261c5589bfa3..0885b34d5d7d 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -16,3 +16,40 @@
        model = "Nokia N950";
        compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
 };
+&i2c2 {
+        smia_1: camera@10 {
+                compatible = "nokia,smia";
+                reg = <0x10>;
+                /* No reset gpio */
+                vana-supply = <&vaux3>;
+                clocks = <&isp 0>;
+                clock-frequency = <9600000>;
+                nokia,nvm-size = <(16 * 64)>;
+                port {
+                        smia_1_1: endpoint {
+                                link-frequencies = /bits/ 64 <210000000 333600000 398400000>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi2a_ep>;
+                        };
+                };
+        };
+};
+&isp {
+        vdd-csiphy1-supply = <&vaux2>;
+        vdd-csiphy2-supply = <&vaux2>;
+        ports {
+                port@2 {
+                        reg = <2>;
+                        csi2a_ep: endpoint {
+                                remote-endpoint = <&smia_1_1>;
+                                clock-lanes = <2>;
+                                data-lanes = <3 1>;
+                                crc = <1>;
+                                lane-polarities = <1 1 1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
index d36bf0250a05..18e1649681c1 100644
--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -27,7 +27,6 @@
                ti,model = "overo";
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        /* HS USB Port 2 Power */
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
new file mode 100644
index 000000000000..9619a28dfd7d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * device tree for OpenPandora 1GHz with DM3730
+ */
+/dts-v1/;
+#include "omap36xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+/ {
+        model = "Pandora Handheld Console 1GHz";
+        compatible = "ti,omap36xx", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                        OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_127 = MMC2_WP */
+                        OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4)                 /* reserved.gpio_126 = MMC1_WP */
+                        OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_128 = LED_MMC1 */
+                        OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4)                /* reserved.gpio_129 = LED_MMC2 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
new file mode 100644
index 000000000000..fb803a70a2bb
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * device tree for OpenPandora with OMAP3530
+ */
+/dts-v1/;
+#include "omap34xx.dtsi"
+#include "omap3-pandora-common.dtsi"
+/ {
+        model = "Pandora Handheld Console";
+        compatible = "ti,omap3";
+};
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusb2_2_pins
+                &control_pins
+        >;
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_ctl.sdmmc3_cmd */
+                        OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                        OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d5.sdmmc3_dat1 */
+                        OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                >;
+        };
+        control_pins: pinmux_control_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4)    /* etk_d0.gpio_14 =  HP_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4)            /* etk_d1.gpio_15 =  BT_SHUTDOWN */
+                        OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 =  RESET_USB_HOST */
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4)             /* etk_d7.gpio_21 =  WIFI IRQ */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)            /* etk_d8.gpio_22 =  MSECURE */
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4)            /* etk_d9.gpio_23 =  WIFI_POWER */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
new file mode 100644
index 000000000000..782ab1ff1d08
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) 2015
+ *   Nikolaus Schaller <hns@goldelico.com>
+ *
+ * Common device tree include for OpenPandora devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/input/input.h>
+/ {
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+        aliases {
+                display0 = &lcd;
+        };
+        tv: connector@1 {
+                compatible = "connector-analog-tv";
+                label = "tv";
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                led@1 {
+                        label = "pandora::sd1";
+                        gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;    /* GPIO_128 */
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+                led@2 {
+                        label = "pandora::sd2";
+                        gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;    /* GPIO_129 */
+                        linux,default-trigger = "mmc1";
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "pandora::bluetooth";
+                        gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;   /* GPIO_158 */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+                led@4 {
+                        label = "pandora::wifi";
+                        gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;   /* GPIO_159 */
+                        linux,default-trigger = "mmc2";
+                        default-state = "off";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+                up-button {
+                        label = "up";
+                        linux,code = <KEY_UP>;
+                        gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;    /* GPIO_110 */
+                        gpio-key,wakeup;
+                };
+                down-button {
+                        label = "down";
+                        linux,code = <KEY_DOWN>;
+                        gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;     /* GPIO_103 */
+                        gpio-key,wakeup;
+                };
+                left-button {
+                        label = "left";
+                        linux,code = <KEY_LEFT>;
+                        gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;     /* GPIO_96 */
+                        gpio-key,wakeup;
+                };
+                right-button {
+                        label = "right";
+                        linux,code = <KEY_RIGHT>;
+                        gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;     /* GPIO_98 */
+                        gpio-key,wakeup;
+                };
+                pageup-button {
+                        label = "game 1";
+                        linux,code = <KEY_PAGEUP>;
+                        gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;    /* GPIO_109 */
+                        gpio-key,wakeup;
+                };
+                pagedown-button {
+                        label = "game 3";
+                        linux,code = <KEY_PAGEDOWN>;
+                        gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;    /* GPIO_106 */
+                        gpio-key,wakeup;
+                };
+                home-button {
+                        label = "game 4";
+                        linux,code = <KEY_HOME>;
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;     /* GPIO_101 */
+                        gpio-key,wakeup;
+                };
+                end-button {
+                        label = "game 2";
+                        linux,code = <KEY_END>;
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;    /* GPIO_111 */
+                        gpio-key,wakeup;
+                };
+                right-shift {
+                        label = "l";
+                        linux,code = <KEY_RIGHTSHIFT>;
+                        gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;     /* GPIO_102 */
+                        gpio-key,wakeup;
+                };
+                kp-plus {
+                        label = "l2";
+                        linux,code = <KEY_KPPLUS>;
+                        gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;     /* GPIO_97 */
+                        gpio-key,wakeup;
+                };
+                right-ctrl {
+                        label = "r";
+                        linux,code = <KEY_RIGHTCTRL>;
+                        gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;     /* GPIO_105 */
+                        gpio-key,wakeup;
+                };
+                kp-minus {
+                        label = "r2";
+                        linux,code = <KEY_KPMINUS>;
+                        gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;    /* GPIO_107 */
+                        gpio-key,wakeup;
+                };
+                left-ctrl {
+                        label = "ctrl";
+                        linux,code = <KEY_LEFTCTRL>;
+                        gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;     /* GPIO_104 */
+                        gpio-key,wakeup;
+                };
+                menu {
+                        label = "menu";
+                        linux,code = <KEY_MENU>;
+                        gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;     /* GPIO_99 */
+                        gpio-key,wakeup;
+                };
+                hold {
+                        label = "hold";
+                        linux,code = <KEY_COFFEE>;
+                        gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;    /* GPIO_176 */
+                        gpio-key,wakeup;
+                };
+                left-alt {
+                        label = "alt";
+                        linux,code = <KEY_LEFTALT>;
+                        gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;    /* GPIO_100 */
+                        gpio-key,wakeup;
+                };
+                lid {
+                        label = "lid";
+                        linux,code = <0x00>;    /* SW_LID lid shut */
+                        linux,input-type = <0x05>;    /* EV_SW */
+                        gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;   /* GPIO_108 */
+                };
+        };
+};
+&omap3_pmx_core {
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat4.sdmmc2_dirdat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat5.sdmmc2_dirdat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1)        /* sdmmc2_dat6.sdmmc2_dircmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1)         /* sdmmc2_dat7.sdmmc2_clkin */
+                >;
+        };
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                        OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4)       /* GPIO_157 = lcd reset */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+        led_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4)       /* GPIO_128 */
+                        OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)       /* GPIO_129 */
+                        OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4)       /* GPIO_158 */
+                        OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4)       /* GPIO_159 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4)        /* GPIO_96 */
+                        OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4)        /* GPIO_97 */
+                        OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4)        /* GPIO_98 */
+                        OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4)        /* GPIO_99 */
+                        OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4)        /* GPIO_100 */
+                        OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4)        /* GPIO_101 */
+                        OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4)        /* GPIO_102 */
+                        OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4)        /* GPIO_103 */
+                        OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4)        /* GPIO_104 */
+                        OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4)        /* GPIO_105 */
+                        OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4)        /* GPIO_106 */
+                        OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4)        /* GPIO_107 */
+                        OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4)        /* GPIO_108 */
+                        OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4)        /* GPIO_109 */
+                        OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4)        /* GPIO_110 */
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4)        /* GPIO_111 */
+                        OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)        /* GPIO_176 */
+                >;
+        };
+        penirq_pins: pinmux_penirq_pins {
+                pinctrl-single,pins = <
+                        /* here we could enable to wakeup the cpu from suspend by a pen touch */
+                        OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4)        /* GPIO_94 */
+                >;
+        };
+};
+&omap3_pmx_core2 {
+        /* define in CPU specific file that includes this one
+         * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD()
+         */
+};
+&i2c1 {
+        clock-frequency = <2600000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+                twl_power: power {
+                        compatible = "ti,twl4030-power-reset";
+                        ti,use_poweroff;
+                };
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                                ti,ramp_delay_value = <3>;
+                        };
+                };
+        };
+};
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+&twl_keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <6>;
+        linux,keymap = <
+                MATRIX_KEY(0, 0, KEY_9)
+                MATRIX_KEY(0, 1, KEY_8)
+                MATRIX_KEY(0, 2, KEY_I)
+                MATRIX_KEY(0, 3, KEY_J)
+                MATRIX_KEY(0, 4, KEY_N)
+                MATRIX_KEY(0, 5, KEY_M)
+                MATRIX_KEY(1, 0, KEY_0)
+                MATRIX_KEY(1, 1, KEY_7)
+                MATRIX_KEY(1, 2, KEY_U)
+                MATRIX_KEY(1, 3, KEY_H)
+                MATRIX_KEY(1, 4, KEY_B)
+                MATRIX_KEY(1, 5, KEY_SPACE)
+                MATRIX_KEY(2, 0, KEY_BACKSPACE)
+                MATRIX_KEY(2, 1, KEY_6)
+                MATRIX_KEY(2, 2, KEY_Y)
+                MATRIX_KEY(2, 3, KEY_G)
+                MATRIX_KEY(2, 4, KEY_V)
+                MATRIX_KEY(2, 5, KEY_FN)
+                MATRIX_KEY(3, 0, KEY_O)
+                MATRIX_KEY(3, 1, KEY_5)
+                MATRIX_KEY(3, 2, KEY_T)
+                MATRIX_KEY(3, 3, KEY_F)
+                MATRIX_KEY(3, 4, KEY_C)
+                MATRIX_KEY(4, 0, KEY_P)
+                MATRIX_KEY(4, 1, KEY_4)
+                MATRIX_KEY(4, 2, KEY_R)
+                MATRIX_KEY(4, 3, KEY_D)
+                MATRIX_KEY(4, 4, KEY_X)
+                MATRIX_KEY(5, 0, KEY_K)
+                MATRIX_KEY(5, 1, KEY_3)
+                MATRIX_KEY(5, 2, KEY_E)
+                MATRIX_KEY(5, 3, KEY_S)
+                MATRIX_KEY(5, 4, KEY_Z)
+                MATRIX_KEY(6, 0, KEY_L)
+                MATRIX_KEY(6, 1, KEY_2)
+                MATRIX_KEY(6, 2, KEY_W)
+                MATRIX_KEY(6, 3, KEY_A)
+                MATRIX_KEY(6, 4, KEY_RIGHTBRACE)
+                MATRIX_KEY(7, 0, KEY_ENTER)
+                MATRIX_KEY(7, 1, KEY_1)
+                MATRIX_KEY(7, 2, KEY_Q)
+                MATRIX_KEY(7, 3, KEY_LEFTSHIFT)
+                MATRIX_KEY(7, 4, KEY_LEFTBRACE )
+         >;
+};
+/* backup battery charger */
+&charger {
+        ti,bb-uvolt = <3200000>;
+        ti,bb-uamp = <150>;
+};
+/* MMC2 */
+&vmmc2 {
+        regulator-min-microvolt = <1850000>;
+        regulator-max-microvolt = <3150000>;
+};
+/* LCD */
+&vaux1 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+};
+/* USB Host PHY */
+&vaux2 {
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+};
+/* available on expansion connector */
+&vaux3 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+/* ADS7846 and nubs */
+&vaux4 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+/* power audio DAC and LID sensor */
+&vsim {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+        regulator-always-on;
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        /* no clients so we should disable clock */
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        bq27500@55 {
+                compatible = "ti,bq27500";
+                reg = <0x55>;
+        };
+};
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; /* GPIO_126 */
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&vmmc2>;
+        bus-width = <4>;
+        cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* GPIO_127 */
+};
+/* bluetooth*/
+&uart1 {
+};
+/* spare (expansion connector) */
+&uart2 {
+};
+/* console (expansion connector) */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+&gpmc {
+        ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
+        nand@0,0 {
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "sw";
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,device-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */
+                x-loader@0 {
+                        label = "xloader";
+                        reg = <0 0x80000>;
+                };
+                bootloaders@80000 {
+                        label = "uboot";
+                        reg = <0x80000 0x1e0000>;
+                };
+                bootloaders_env@260000 {
+                        label = "uboot-env";
+                        reg = <0x260000 0x20000>;
+                };
+                kernel@280000 {
+                        label = "boot";
+                        reg = <0x280000 0xa00000>;
+                };
+                filesystem@680000 {
+                        label = "rootfs";
+                        reg = <0xc80000 0>;     /* 0 = MTDPART_SIZ_FULL */
+                };
+        };
+};
+&mcspi1 {
+        tsc2046@0 {
+                reg = <0>;      /* CS0 */
+                compatible = "ti,tsc2046";
+                spi-max-frequency = <1000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&penirq_pins>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <30 0>;    /* GPIO_94 */
+                pendown-gpio = <&gpio3 30 0>;
+                vcc-supply = <&vaux4>;
+                ti,x-min = /bits/ 16 <0>;
+                ti,x-max = /bits/ 16 <8000>;
+                ti,y-min = /bits/ 16 <0>;
+                ti,y-max = /bits/ 16 <4800>;
+                ti,x-plate-ohms = /bits/ 16 <40>;
+                ti,pressure-max = /bits/ 16 <255>;
+                linux,wakeup;
+        };
+        lcd: lcd@1 {
+                reg = <1>;      /* CS1 */
+                compatible =    "omapdss,tpo,td043mtea1";
+                spi-max-frequency = <100000>;
+                spi-cpol;
+                spi-cpha;
+                label = "lcd";
+                reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;      /* GPIO_157 */
+                vcc-supply = <&vaux1>;
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+        };
+};
+/* n/a - used as GPIOs */
+&mcbsp1 {
+};
+/* audio DAC */
+&mcbsp2 {
+};
+/* bluetooth */
+&mcbsp3 {
+};
+/* to twl4030*/
+&mcbsp4 {
+};
+&venc {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
+&dss {
+        pinctrl-names = "default";
+        pinctrl-0 = < &dss_dpi_pins >;
+        status = "ok";
+        vdds_dsi-supply = <&vpll2>;
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index e89820a6776e..7bd8d9a4f67f 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -8,7 +8,16 @@
 */
 /dts-v1/;
-#include "omap34xx-hs.dtsi"
+#include "omap34xx.dtsi"
+/* Secure omaps have some devices inaccessible depending on the firmware */
+&aes {
+        status = "disabled";
+};
+&sham {
+        status = "disabled";
+};
 / {
        cpus {
@@ -45,7 +54,6 @@
                /* McBSP2 is used for onboard sound, same as on beagle */
                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
        };
        /* Regulator to enable/switch the vcc of the Wifi module */
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index 6644f516a42b..131448d86e67 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -195,6 +195,16 @@
        cap-power-off-card;
        pinctrl-names = "default";
        pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */
+                ref-clock-frequency = <26000000>;
+        };
 };
 &uart1 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 3fdc84fddb70..d18a90f5eca3 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
                ranges;
                ti,hwmods = "l3_main";
+                l4_core: l4@48000000 {
+                        compatible = "ti,omap3-l4-core", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x1000000>;
+                        scm: scm@2000 {
+                                compatible = "ti,omap3-scm", "simple-bus";
+                                reg = <0x2000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+                                omap3_pmx_core: pinmux@30 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x330>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
+                                omap3_pmx_wkup: pinmux@a00 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0xa00 0x5c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+                        };
+                };
                aes: aes@480c5000 {
                        compatible = "ti,omap3-aes";
                        ti,hwmods = "aes";
@@ -123,19 +177,6 @@
                        };
                };
-                scrm: scrm@48002000 {
-                        compatible = "ti,omap3-scrm";
-                        reg = <0x48002000 0x2000>;
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        scrm_clockdomains: clockdomains {
-                        };
-                };
                counter32k: counter@48320000 {
                        compatible = "ti,omap-counter32k";
                        reg = <0x48320000 0x20>;
@@ -161,37 +202,10 @@
                        dma-requests = <96>;
                };
-                omap3_pmx_core: pinmux@48002030 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002030 0x0238>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-                omap3_pmx_wkup: pinmux@48002a00 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002a00 0x5c>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-                omap3_scm_general: tisyscon@48002270 {
-                        compatible = "syscon";
-                        reg = <0x48002270 0x2f0>;
-                };
                pbias_regulator: pbias_regulator {
                        compatible = "ti,pbias-omap";
                        reg = <0x2b0 0x4>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                        pbias_mmc_reg: pbias_mmc_omap2430 {
                                regulator-name = "pbias_mmc_omap2430";
                                regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap34xx-hs.dtsi b/arch/arm/boot/dts/omap34xx-hs.dtsi
deleted file mode 100644
index 1ff626489546..000000000000
--- a/arch/arm/boot/dts/omap34xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-#include "omap34xx.dtsi"
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-&sham {
-        status = "disabled";
-};
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 3819c1e91591..4f6b2d5b1902 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,6 +8,8 @@
 * kind, whether express or implied.
 */
+#include <dt-bindings/media/omap3-isp.h>
 #include "omap3.dtsi"
 / {
@@ -37,6 +39,21 @@
                        pinctrl-single,register-width = <16>;
                        pinctrl-single,function-mask = <0xff1f>;
                };
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x017c>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0xdc>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap36xx-hs.dtsi b/arch/arm/boot/dts/omap36xx-hs.dtsi
deleted file mode 100644
index 2c7febb0e016..000000000000
--- a/arch/arm/boot/dts/omap36xx-hs.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Disabled modules for secure omaps */
-#include "omap36xx.dtsi"
-/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
-        status = "disabled";
-};
-&sham {
-        status = "disabled";
-};
-&timer12 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 541704a59a5a..86253de5a97a 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,6 +8,8 @@
 * kind, whether express or implied.
 */
+#include <dt-bindings/media/omap3-isp.h>
 #include "omap3.dtsi"
 / {
@@ -69,6 +71,21 @@
                        pinctrl-single,register-width = <16>;
                        pinctrl-single,function-mask = <0xff1f>;
                };
+                isp: isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x0600>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0x2f0>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
                clock-div = <1>;
        };
 };
-&scrm_clocks {
+&scm_clocks {
        mcbsp5_mux_fck: mcbsp5_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&core_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <4>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&core_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x04>;
        };
        mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x04>;
        };
        mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index cb9458feb2e3..ab7f87ae96f0 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal {
                        /* sensor       ID */
        thermal-sensors = <&bandgap     0>;
-        trips {
+        cpu_trips: trips {
                cpu_alert0: cpu_alert {
                        temperature = <100000>; /* millicelsius */
                        hysteresis = <2000>; /* millicelsius */
@@ -31,7 +31,7 @@ cpu_thermal: cpu_thermal {
                };
        };
-        cooling-maps {
+        cpu_cooling_maps: cooling-maps {
                map0 {
                        trip = <&cpu_alert0>;
                        cooling-device =
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 7c15fb2e2fe4..f1507bc8737e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -448,6 +448,16 @@
        non-removable;
        bus-width = <4>;
        cap-power-off-card;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+                ref-clock-frequency = <38400000>;
+        };
 };
 &emif1 {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 8aca8dae968a..dac86ed7481f 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -485,6 +485,17 @@
        non-removable;
        bus-width = <4>;
        cap-power-off-card;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1281";
+                reg = <2>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+                ref-clock-frequency = <26000000>;
+                tcxo-clock-frequency = <26000000>;
+        };
 };
 &emif1 {
diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
index cc66af419236..9bceeb7e1f03 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
@@ -65,4 +65,14 @@
        bus-width = <4>;
        cap-power-off-card;
        status = "okay";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1271";
+                reg = <2>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
+                ref-clock-frequency = <38400000>;
+        };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f2091d1c9c36..f884d6adb71e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -124,99 +124,141 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                cm1: cm1@4a004000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,omap4-cm1";
+                        compatible = "ti,omap4-l4-cfg", "simple-bus";
-                        reg = <0x4a004000 0x2000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        cm1_clocks: clocks {
+                        ranges = <0 0x4a000000 0x1000000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        cm1_clockdomains: clockdomains {
+                        cm1: cm1@4000 {
-                        };
+                                compatible = "ti,omap4-cm1";
-                };
+                                reg = <0x4000 0x2000>;
-                prm: prm@4a306000 {
+                                cm1_clocks: clocks {
-                        compatible = "ti,omap4-prm";
+                                        #address-cells = <1>;
-                        reg = <0x4a306000 0x3000>;
+                                        #size-cells = <0>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                };
-                        prm_clocks: clocks {
+                                cm1_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        prm_clockdomains: clockdomains {
+                        cm2: cm2@8000 {
-                        };
+                                compatible = "ti,omap4-cm2";
-                };
+                                reg = <0x8000 0x3000>;
-                cm2: cm2@4a008000 {
+                                cm2_clocks: clocks {
-                        compatible = "ti,omap4-cm2";
+                                        #address-cells = <1>;
-                        reg = <0x4a008000 0x3000>;
+                                        #size-cells = <0>;
+                                };
-                        cm2_clocks: clocks {
+                                cm2_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        cm2_clockdomains: clockdomains {
+                        omap4_scm_core: scm@2000 {
+                                compatible = "ti,omap4-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                        };
-                };
-                scrm: scrm@4a30a000 {
-                        compatible = "ti,omap4-scrm";
-                        reg = <0x4a30a000 0x2000>;
-                        scrm_clocks: clocks {
+                        omap4_padconf_core: scm@100000 {
+                                compatible = "ti,omap4-scm-padconf-core",
+                                             "simple-bus";
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x100000 0x1000>;
+                                omap4_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap4-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x0196>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+                                omap4_padconf_global: omap4_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0x170>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap4_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap4 {
+                                                        regulator-name = "pbias_mmc_omap4";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                        };
-                        scrm_clockdomains: clockdomains {
+                        l4_wkup: l4@300000 {
-                        };
+                                compatible = "ti,omap4-l4-wkup", "simple-bus";
-                };
+                                #address-cells = <1>;
+                                #size-cells = <1>;
-                counter32k: counter@4a304000 {
+                                ranges = <0 0x300000 0x40000>;
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4a304000 0x20>;
+                                counter32k: counter@4000 {
-                        ti,hwmods = "counter_32k";
+                                        compatible = "ti,omap-counter32k";
-                };
+                                        reg = <0x4000 0x20>;
+                                        ti,hwmods = "counter_32k";
-                omap4_pmx_core: pinmux@4a100040 {
+                                };
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a100040 0x0196>;
+                                prm: prm@6000 {
-                        #address-cells = <1>;
+                                        compatible = "ti,omap4-prm";
-                        #size-cells = <0>;
+                                        reg = <0x6000 0x3000>;
-                        #interrupt-cells = <1>;
+                                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
+                                        prm_clocks: clocks {
-                        pinctrl-single,function-mask = <0x7fff>;
+                                                #address-cells = <1>;
-                };
+                                                #size-cells = <0>;
-                omap4_pmx_wkup: pinmux@4a31e040 {
+                                        };
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a31e040 0x0038>;
+                                        prm_clockdomains: clockdomains {
-                        #address-cells = <1>;
+                                        };
-                        #size-cells = <0>;
+                                };
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
+                                scrm: scrm@a000 {
-                        pinctrl-single,register-width = <16>;
+                                        compatible = "ti,omap4-scrm";
-                        pinctrl-single,function-mask = <0x7fff>;
+                                        reg = <0xa000 0x2000>;
-                };
+                                        scrm_clocks: clocks {
-                omap4_padconf_global: tisyscon@4a1005a0 {
+                                                #address-cells = <1>;
-                        compatible = "syscon";
+                                                #size-cells = <0>;
-                        reg = <0x4a1005a0 0x170>;
+                                        };
-                };
+                                        scrm_clockdomains: clockdomains {
-                pbias_regulator: pbias_regulator {
+                                        };
-                        compatible = "ti,pbias-omap";
+                                };
-                        reg = <0x60 0x4>;
-                        syscon = <&omap4_padconf_global>;
+                                omap4_pmx_wkup: pinmux@1e040 {
-                        pbias_mmc_reg: pbias_mmc_omap4 {
+                                        compatible = "ti,omap4-padconf",
-                                regulator-name = "pbias_mmc_omap4";
+                                                     "pinctrl-single";
-                                regulator-min-microvolt = <1800000>;
+                                        reg = <0x1e040 0x0038>;
-                                regulator-max-microvolt = <3000000>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
                        };
                };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 77b5f70d0ebc..efe5f737f39b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -139,99 +139,141 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prm: prm@4ae06000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,omap5-prm";
+                        compatible = "ti,omap5-l4-cfg", "simple-bus";
-                        reg = <0x4ae06000 0x3000>;
+                        #address-cells = <1>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22a000>;
-                        prm_clocks: clocks {
+                        scm_core: scm@2000 {
+                                compatible = "ti,omap5-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x800>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                        };
-                        prm_clockdomains: clockdomains {
+                        scm_padconf_core: scm@2800 {
+                                compatible = "ti,omap5-scm-padconf-core",
+                                             "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2800 0x800>;
+                                omap5_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap5-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x01b6>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+                                omap5_padconf_global: omap5_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0xec>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap5_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                        };
-                };
-                cm_core_aon: cm_core_aon@4a004000 {
+                        cm_core_aon: cm_core_aon@4000 {
-                        compatible = "ti,omap5-cm-core-aon";
+                                compatible = "ti,omap5-cm-core-aon";
-                        reg = <0x4a004000 0x2000>;
+                                reg = <0x4000 0x2000>;
-                        cm_core_aon_clocks: clocks {
+                                cm_core_aon_clocks: clocks {
-                                #address-cells = <1>;
+                                        #address-cells = <1>;
-                                #size-cells = <0>;
+                                        #size-cells = <0>;
-                        };
+                                };
-                        cm_core_aon_clockdomains: clockdomains {
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
                        };
-                };
-                scrm: scrm@4ae0a000 {
+                        cm_core: cm_core@8000 {
-                        compatible = "ti,omap5-scrm";
+                                compatible = "ti,omap5-cm-core";
-                        reg = <0x4ae0a000 0x2000>;
+                                reg = <0x8000 0x3000>;
-                        scrm_clocks: clocks {
+                                cm_core_clocks: clocks {
-                                #address-cells = <1>;
+                                        #address-cells = <1>;
-                                #size-cells = <0>;
+                                        #size-cells = <0>;
-                        };
+                                };
-                        scrm_clockdomains: clockdomains {
+                                cm_core_clockdomains: clockdomains {
+                                };
                        };
                };
-                cm_core: cm_core@4a008000 {
+                l4_wkup: l4@4ae00000 {
-                        compatible = "ti,omap5-cm-core";
+                        compatible = "ti,omap5-l4-wkup", "simple-bus";
-                        reg = <0x4a008000 0x3000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x2b000>;
-                        cm_core_clocks: clocks {
+                        counter32k: counter@4000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap-counter32k";
-                                #size-cells = <0>;
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
                        };
-                        cm_core_clockdomains: clockdomains {
+                        prm: prm@6000 {
+                                compatible = "ti,omap5-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                prm_clockdomains: clockdomains {
+                                };
                        };
-                };
-                counter32k: counter@4ae04000 {
+                        scrm: scrm@a000 {
-                        compatible = "ti,omap-counter32k";
+                                compatible = "ti,omap5-scrm";
-                        reg = <0x4ae04000 0x40>;
+                                reg = <0xa000 0x2000>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap5_pmx_core: pinmux@4a002840 {
+                                scrm_clocks: clocks {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
+                                        #address-cells = <1>;
-                        reg = <0x4a002840 0x01b6>;
+                                        #size-cells = <0>;
-                        #address-cells = <1>;
+                                };
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap5_pmx_wkup: pinmux@4ae0c840 {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
-                        reg = <0x4ae0c840 0x0038>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap5_padconf_global: tisyscon@4a002da0 {
+                                scrm_clockdomains: clockdomains {
-                        compatible = "syscon";
+                                };
-                        reg = <0x4A002da0 0xec>;
+                        };
-                };
-                pbias_regulator: pbias_regulator {
+                        omap5_pmx_wkup: pinmux@c840 {
-                        compatible = "ti,pbias-omap";
+                                compatible = "ti,omap5-padconf",
-                        reg = <0x60 0x4>;
+                                             "pinctrl-single";
-                        syscon = <&omap5_padconf_global>;
+                                reg = <0xc840 0x0038>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
+                                #address-cells = <1>;
-                                regulator-name = "pbias_mmc_omap5";
+                                #size-cells = <0>;
-                                regulator-min-microvolt = <1800000>;
+                                #interrupt-cells = <1>;
-                                regulator-max-microvolt = <3000000>;
+                                interrupt-controller;
+                                pinctrl-single,register-width = <16>;
+                                pinctrl-single,function-mask = <0x7fff>;
                        };
                };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c071652..6c1511263a55 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@1 {
@@ -33,6 +34,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@2 {
@@ -43,6 +45,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@3 {
@@ -53,12 +56,23 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                L2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                };
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <400>;
+                                exit-latency-us = <900>;
+                                min-residency-us = <3000>;
+                        };
+                };
        };
        cpu-pmu {
@@ -139,26 +153,26 @@
                        reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
                };
-                saw0: regulator@2089000 {
+                saw0: power-controller@2089000 {
-                        compatible = "qcom,saw2";
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
-                saw1: regulator@2099000 {
+                saw1: power-controller@2099000 {
-                        compatible = "qcom,saw2";
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
-                saw2: regulator@20a9000 {
+                saw2: power-controller@20a9000 {
-                        compatible = "qcom,saw2";
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
-                saw3: regulator@20b9000 {
+                saw3: power-controller@20b9000 {
-                        compatible = "qcom,saw2";
+                        compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
@@ -166,6 +180,7 @@
                gsbi1: gsbi@12440000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <1>;
                        reg = <0x12440000 0x100>;
                        clocks = <&gcc GSBI1_H_CLK>;
                        clock-names = "iface";
@@ -173,6 +188,8 @@
                        #size-cells = <1>;
                        ranges;
+                        syscon-tcsr = <&tcsr>;
                        i2c1: i2c@12460000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x12460000 0x1000>;
@@ -187,6 +204,7 @@
                gsbi2: gsbi@12480000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <2>;
                        reg = <0x12480000 0x100>;
                        clocks = <&gcc GSBI2_H_CLK>;
                        clock-names = "iface";
@@ -194,6 +212,8 @@
                        #size-cells = <1>;
                        ranges;
+                        syscon-tcsr = <&tcsr>;
                        i2c2: i2c@124a0000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x124a0000 0x1000>;
@@ -208,6 +228,7 @@
                gsbi7: gsbi@16600000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <7>;
                        reg = <0x16600000 0x100>;
                        clocks = <&gcc GSBI7_H_CLK>;
                        clock-names = "iface";
@@ -215,6 +236,8 @@
                        #size-cells = <1>;
                        ranges;
+                        syscon-tcsr = <&tcsr>;
                        serial@16640000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16640000 0x1000>,
@@ -239,6 +262,13 @@
                        #reset-cells = <1>;
                };
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-apq8064";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
                mmcc: clock-controller@4000000 {
                        compatible = "qcom,mmcc-apq8064";
                        reg = <0x4000000 0x1000>;
@@ -349,5 +379,10 @@
                                pinctrl-0 = <&sdc4_gpios>;
                        };
                };
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-apq8064", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 47370494d0f8..d484d08163e9 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
 / {
        model = "Qualcomm APQ8074 Dragonboard";
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index c9ff10821ad9..f7725b96612c 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"
 / {
        model = "Qualcomm APQ8084/IFC6540";
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 8ecec58a9ff6..cb43acfc5d1d 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -1,4 +1,5 @@
 #include "qcom-apq8084.dtsi"
+#include "qcom-pma8084.dtsi"
 / {
        model = "Qualcomm APQ 8084-MTP";
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc16858..7084010ee61b 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -21,6 +21,8 @@
                        enable-method = "qcom,kpss-acc-v2";
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@1 {
@@ -30,6 +32,8 @@
                        enable-method = "qcom,kpss-acc-v2";
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@2 {
@@ -39,6 +43,8 @@
                        enable-method = "qcom,kpss-acc-v2";
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@3 {
@@ -48,6 +54,8 @@
                        enable-method = "qcom,kpss-acc-v2";
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                L2: l2-cache {
@@ -55,6 +63,16 @@
                        cache-level = <2>;
                        qcom,saw = <&saw_l2>;
                };
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <150>;
+                                exit-latency-us = <200>;
+                                min-residency-us = <2000>;
+                        };
+                };
        };
        cpu-pmu {
@@ -144,7 +162,27 @@
                        };
                };
-                saw_l2: regulator@f9012000 {
+                saw0: power-controller@f9089000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw1: power-controller@f9099000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw2: power-controller@f90a9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw3: power-controller@f90b9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw_l2: power-controller@f9012000 {
                        compatible = "qcom,saw2";
                        reg = <0xf9012000 0x1000>;
                        regulator;
@@ -226,5 +264,21 @@
                        clock-names = "core", "iface";
                        status = "disabled";
                };
+                spmi_bus: spmi@fc4cf000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg-names = "core", "intr", "cnfg";
+                        reg = <0xfc4cf000 0x1000>,
+                              <0xfc4cb000 0x1000>,
+                              <0xfc4ca000 0x1000>;
+                        interrupt-names = "periph_irq";
+                        interrupts = <0 190 0>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index d01f618df5f7..9f727d8eadf6 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 / {
@@ -74,6 +75,21 @@
                ranges;
                compatible = "simple-bus";
+                lpass@28100000 {
+                        compatible = "qcom,lpass-cpu";
+                        status = "disabled";
+                        clocks = <&lcc AHBIX_CLK>,
+                                        <&lcc MI2S_OSR_CLK>,
+                                        <&lcc MI2S_BIT_CLK>;
+                        clock-names = "ahbix-clk",
+                                        "mi2s-osr-clk",
+                                        "mi2s-bit-clk";
+                        interrupts = <0 85 1>;
+                        interrupt-names = "lpass-irq-lpaif";
+                        reg = <0x28100000 0x10000>;
+                        reg-names = "lpass-lpaif";
+                };
                qcom_pinmux: pinmux@800000 {
                        compatible = "qcom,ipq8064-pinctrl";
                        reg = <0x800000 0x4000>;
@@ -132,6 +148,7 @@
                gsbi2: gsbi@12480000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <2>;
                        reg = <0x12480000 0x100>;
                        clocks = <&gcc GSBI2_H_CLK>;
                        clock-names = "iface";
@@ -140,6 +157,8 @@
                        ranges;
                        status = "disabled";
+                        syscon-tcsr = <&tcsr>;
                        serial@12490000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x12490000 0x1000>,
@@ -167,6 +186,7 @@
                gsbi4: gsbi@16300000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <4>;
                        reg = <0x16300000 0x100>;
                        clocks = <&gcc GSBI4_H_CLK>;
                        clock-names = "iface";
@@ -175,6 +195,8 @@
                        ranges;
                        status = "disabled";
+                        syscon-tcsr = <&tcsr>;
                        serial@16340000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16340000 0x1000>,
@@ -201,6 +223,7 @@
                gsbi5: gsbi@1a200000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <5>;
                        reg = <0x1a200000 0x100>;
                        clocks = <&gcc GSBI5_H_CLK>;
                        clock-names = "iface";
@@ -209,6 +232,8 @@
                        ranges;
                        status = "disabled";
+                        syscon-tcsr = <&tcsr>;
                        serial@1a240000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x1a240000 0x1000>,
@@ -291,5 +316,18 @@
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-ipq8064", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-ipq8064";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd6193f56..20bbd19b996e 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -82,6 +82,7 @@
                gsbi12: gsbi@19c00000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <12>;
                        reg = <0x19c00000 0x100>;
                        clocks = <&gcc GSBI12_H_CLK>;
                        clock-names = "iface";
@@ -89,6 +90,8 @@
                        #size-cells = <1>;
                        ranges;
+                        syscon-tcsr = <&tcsr>;
                        serial@19c40000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x19c40000 0x1000>,
@@ -196,6 +199,11 @@
                                vmmc-supply = <&vsdcc_fixed>;
                        };
                };
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-msm8660", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5cd9e3c..a02b984cc68d 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -91,6 +91,13 @@
                        reg = <0x900000 0x4000>;
                };
+                lcc: clock-controller@28000000 {
+                        compatible = "qcom,lcc-msm8960";
+                        reg = <0x28000000 0x1000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
                clock-controller@4000000 {
                        compatible = "qcom,mmcc-msm8960";
                        reg = <0x4000000 0x1000>;
@@ -122,6 +129,7 @@
                gsbi5: gsbi@16400000 {
                        compatible = "qcom,gsbi-v1.0.0";
+                        cell-index = <5>;
                        reg = <0x16400000 0x100>;
                        clocks = <&gcc GSBI5_H_CLK>;
                        clock-names = "iface";
@@ -129,6 +137,8 @@
                        #size-cells = <1>;
                        ranges;
+                        syscon-tcsr = <&tcsr>;
                        serial@16440000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16440000 0x1000>,
@@ -238,5 +248,10 @@
                                vmmc-supply = <&vsdcc_fixed>;
                        };
                };
+                tcsr: syscon@1a400000 {
+                        compatible = "qcom,tcsr-msm8960", "syscon";
+                        reg = <0x1a400000 0x100>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index cccc21b7c8fd..bd35b0674ff6 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -1,4 +1,6 @@
 #include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
 / {
        model = "Sony Xperia Z1";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec16a787..37b47b5538b8 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -21,6 +21,8 @@
                        reg = <0>;
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@1 {
@@ -30,6 +32,8 @@
                        reg = <1>;
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@2 {
@@ -39,6 +43,8 @@
                        reg = <2>;
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                cpu@3 {
@@ -48,6 +54,8 @@
                        reg = <3>;
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                };
                L2: l2-cache {
@@ -55,6 +63,16 @@
                        cache-level = <2>;
                        qcom,saw = <&saw_l2>;
                };
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <150>;
+                                exit-latency-us = <200>;
+                                min-residency-us = <2000>;
+                        };
+                };
        };
        cpu-pmu {
@@ -144,7 +162,27 @@
                        };
                };
-                saw_l2: regulator@f9012000 {
+                saw0: power-controller@f9089000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw1: power-controller@f9099000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw2: power-controller@f90a9000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw3: power-controller@f90b9000 {
+                        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+                };
+                saw_l2: power-controller@f9012000 {
                        compatible = "qcom,saw2";
                        reg = <0xf9012000 0x1000>;
                        regulator;
@@ -247,5 +285,21 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
+                spmi_bus: spmi@fc4cf000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg-names = "core", "intr", "cnfg";
+                        reg = <0xfc4cf000 0x1000>,
+                              <0xfc4cb000 0x1000>,
+                              <0xfc4ca000 0x1000>;
+                        interrupt-names = "periph_irq";
+                        interrupts = <0 190 0>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi
new file mode 100644
index 000000000000..73813cc118f9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+&spmi_bus {
+        usid4: pm8841@4 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x4 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        usid5: pm8841@5 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x5 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
new file mode 100644
index 000000000000..24c5088acea2
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+&spmi_bus {
+        usid0: pm8941@0 {
+                compatible ="qcom,spmi-pmic";
+                reg = <0x0 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        usid1: pm8941@1 {
+                compatible ="qcom,spmi-pmic";
+                reg = <0x1 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
new file mode 100644
index 000000000000..a5a4fe695a46
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -0,0 +1,18 @@
+#include <dt-bindings/spmi/spmi.h>
+&spmi_bus {
+        usid0: pma8084@0 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x0 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        usid1: pma8084@1 {
+                compatible = "qcom,spmi-pmic";
+                reg = <0x1 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
deleted file mode 100644
index b3d8f844b57a..000000000000
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Device Tree Source for the APE6EVM board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/dts-v1/;
-#include "r8a73a4.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
-        model = "APE6EVM";
-        compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
-        aliases {
-                serial0 = &scifa0;
-        };
-        chosen {
-                bootargs = "ignore_loglevel rw";
-                stdout-path = &scifa0;
-        };
-        memory@40000000 {
-                device_type = "memory";
-                reg = <0 0x40000000 0 0x40000000>;
-        };
-        memory@200000000 {
-                device_type = "memory";
-                reg = <2 0x00000000 0 0x40000000>;
-        };
-        vcc_mmc0: regulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "MMC0 Vcc";
-                regulator-min-microvolt = <2800000>;
-                regulator-max-microvolt = <2800000>;
-                regulator-always-on;
-        };
-        vcc_sdhi0: regulator@1 {
-                compatible = "regulator-fixed";
-                regulator-name = "SDHI0 Vcc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-        /* Common 3.3V rail, used by several devices on APE6EVM */
-        ape6evm_fixed_3v3: regulator@2 {
-                compatible = "regulator-fixed";
-                regulator-name = "3V3";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-always-on;
-        };
-        lbsc {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0 0x20000000>;
-        };
-};
-&i2c5 {
-        status = "okay";
-        vdd_dvfs: max8973@1b {
-                compatible = "maxim,max8973";
-                reg = <0x1b>;
-                regulator-min-microvolt = <935000>;
-                regulator-max-microvolt = <1200000>;
-                regulator-boot-on;
-                regulator-always-on;
-        };
-};
-&cpu0 {
-        cpu0-supply = <&vdd_dvfs>;
-        operating-points = <
-                /* kHz  uV */
-                1950000 1115000
-                1462500  995000
-        >;
-        voltage-tolerance = <1>; /* 1% */
-};
-&cmt1 {
-        status = "okay";
-};
-&pfc {
-        scifa0_pins: serial0 {
-                renesas,groups = "scifa0_data";
-                renesas,function = "scifa0";
-        };
-        mmc0_pins: mmc {
-                renesas,groups = "mmc0_data8", "mmc0_ctrl";
-                renesas,function = "mmc0";
-        };
-        sdhi0_pins: sd0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-                renesas,function = "sdhi0";
-        };
-        sdhi1_pins: sd1 {
-                renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
-                renesas,function = "sdhi1";
-        };
-};
-&mmcif0 {
-        vmmc-supply = <&vcc_mmc0>;
-        bus-width = <8>;
-        non-removable;
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins>;
-        status = "okay";
-};
-&scifa0 {
-        pinctrl-0 = <&scifa0_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-};
-&sdhi0 {
-        vmmc-supply = <&vcc_sdhi0>;
-        bus-width = <4>;
-        toshiba,mmc-wrprotect-disable;
-        pinctrl-names = "default";
-        pinctrl-0 = <&sdhi0_pins>;
-        status = "okay";
-};
-&sdhi1 {
-        vmmc-supply = <&ape6evm_fixed_3v3>;
-        bus-width = <4>;
-        broken-cd;
-        toshiba,mmc-wrprotect-disable;
-        pinctrl-names = "default";
-        pinctrl-0 = <&sdhi1_pins>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 0d50bef01234..81a38ceee098 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -22,7 +22,7 @@
        };
        chosen {
-                bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
+                bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
                stdout-path = &scifa0;
        };
@@ -72,50 +72,30 @@
                regulator-always-on;
        };
-        lbsc {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0 0x20000000>;
-                ethernet@8000000 {
-                        compatible = "smsc,lan9220", "smsc,lan9115";
-                        reg = <0x08000000 0x1000>;
-                        interrupt-parent = <&irqc1>;
-                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
-                        phy-mode = "mii";
-                        reg-io-width = <4>;
-                        smsc,irq-active-high;
-                        smsc,irq-push-pull;
-                        vdd33a-supply = <&ape6evm_fixed_3v3>;
-                        vddvario-supply = <&ape6evm_fixed_1v8>;
-                };
-        };
        leds {
                compatible = "gpio-leds";
                led1 {
-                        gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
                        label = "GNSS_EN";
                };
                led2 {
-                        gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
                        label = "NFC_NRST";
                };
                led3 {
-                        gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
                        label = "GNSS_NRST";
                };
                led4 {
-                        gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 232 GPIO_ACTIVE_HIGH>;
                        label = "BT_WAKEUP";
                };
                led5 {
-                        gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 250 GPIO_ACTIVE_HIGH>;
                        label = "STROBE";
                };
                led6 {
-                        gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
+                        gpios = <&pfc 288 GPIO_ACTIVE_HIGH>;
                        label = "BBRESETOUT";
                };
        };
@@ -123,10 +103,14 @@
        keyboard {
                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&keyboard_pins>;
                zero-key {
                        gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_0>;
                        label = "S16";
+                        gpio-key,wakeup;
                };
                menu-key {
@@ -184,6 +168,21 @@
        voltage-tolerance = <1>; /* 1% */
 };
+&bsc {
+        ethernet@8000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x08000000 0x1000>;
+                interrupt-parent = <&irqc1>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                phy-mode = "mii";
+                reg-io-width = <4>;
+                smsc,irq-active-high;
+                smsc,irq-push-pull;
+                vdd33a-supply = <&ape6evm_fixed_3v3>;
+                vddvario-supply = <&ape6evm_fixed_1v8>;
+        };
+};
 &cmt1 {
        status = "okay";
 };
@@ -208,6 +207,12 @@
                renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
                renesas,function = "sdhi1";
        };
+        keyboard_pins: keyboard {
+                renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
+                               "PORT328", "PORT329";
+                bias-pull-up;
+        };
 };
 &mmcif0 {
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 38136d9f6d95..0fd889f88109 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,7 @@
 * kind, whether express or implied.
 */
+#include <dt-bindings/clock/r8a73a4-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -27,9 +28,15 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
+                        power-domains = <&pd_a2sl>;
                };
        };
+        ptm {
+                compatible = "arm,coresight-etm3x";
+                power-domains = <&pd_d4>;
+        };
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -41,11 +48,13 @@
        dbsc1: memory-controller@e6790000 {
                compatible = "renesas,dbsc-r8a73a4";
                reg = <0 0xe6790000 0 0x10000>;
+                power-domains = <&pd_a3bc>;
        };
        dbsc2: memory-controller@e67a0000 {
                compatible = "renesas,dbsc-r8a73a4";
                reg = <0 0xe67a0000 0 0x10000>;
+                power-domains = <&pd_a3bc>;
        };
        dmac: dma-multiplexer {
@@ -87,38 +96,19 @@
                                        "ch8", "ch9", "ch10", "ch11",
                                        "ch12", "ch13", "ch14", "ch15",
                                        "ch16", "ch17", "ch18", "ch19";
+                        clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
+                        power-domains = <&pd_a3sp>;
                };
        };
-        pfc: pfc@e6050000 {
-                compatible = "renesas,pfc-r8a73a4";
-                reg = <0 0xe6050000 0 0x9000>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupts-extended =
-                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
-                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
-                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
-                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
-                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
-                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
-                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
-                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
-                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
-                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
-                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
-                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
-                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
-                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
-                        <&irqc1 24 0>, <&irqc1 25 0>;
-        };
        i2c5: i2c@e60b0000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe60b0000 0 0x428>;
                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -127,6 +117,9 @@
                compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
                reg = <0 0xe6130000 0 0x1004>;
                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
+                clock-names = "fck";
+                power-domains = <&pd_c5>;
                renesas,channels-mask = <0xff>;
@@ -170,6 +163,7 @@
                             <0 29 IRQ_TYPE_LEVEL_HIGH>,
                             <0 30 IRQ_TYPE_LEVEL_HIGH>,
                             <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&pd_c4>;
        };
        irqc1: interrupt-controller@e61c0200 {
@@ -203,6 +197,31 @@
                             <0 55 IRQ_TYPE_LEVEL_HIGH>,
                             <0 56 IRQ_TYPE_LEVEL_HIGH>,
                             <0 57 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&pd_c4>;
+        };
+        pfc: pfc@e6050000 {
+                compatible = "renesas,pfc-r8a73a4";
+                reg = <0 0xe6050000 0 0x9000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
+                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
+                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
+                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
+                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
+                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
+                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
+                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
+                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
+                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
+                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
+                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
+                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
+                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
+                        <&irqc1 24 0>, <&irqc1 25 0>;
+                power-domains = <&pd_c5>;
        };
        thermal@e61f0000 {
@@ -210,6 +229,8 @@
                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
                         <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
+                power-domains = <&pd_c5>;
        };
        i2c0: i2c@e6500000 {
@@ -218,6 +239,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6500000 0 0x428>;
                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -227,6 +250,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6510000 0 0x428>;
                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -236,6 +261,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6520000 0 0x428>;
                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -245,6 +272,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6530000 0 0x428>;
                interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -254,6 +283,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6540000 0 0x428>;
                interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -263,6 +294,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6550000 0 0x428>;
                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -272,6 +305,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6560000 0 0x428>;
                interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -281,6 +316,8 @@
                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6570000 0 0x428>;
                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -288,6 +325,9 @@
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6c20000 0 0x100>;
                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -295,6 +335,9 @@
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6c30000 0 0x100>;
                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -302,6 +345,9 @@
                compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
                reg = <0 0xe6c40000 0 0x100>;
                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -309,6 +355,9 @@
                compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
                reg = <0 0xe6c50000 0 0x100>;
                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -316,6 +365,9 @@
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6ce0000 0 0x100>;
                interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -323,6 +375,9 @@
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6cf0000 0 0x100>;
                interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
+                clock-names = "sci_ick";
+                power-domains = <&pd_c4>;
                status = "disabled";
        };
@@ -330,6 +385,8 @@
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee100000 0 0x100>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
+                power-domains = <&pd_a3sp>;
                cap-sd-highspeed;
                status = "disabled";
        };
@@ -338,6 +395,8 @@
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee120000 0 0x100>;
                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
+                power-domains = <&pd_a3sp>;
                cap-sd-highspeed;
                status = "disabled";
        };
@@ -346,6 +405,8 @@
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee140000 0 0x100>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
+                power-domains = <&pd_a3sp>;
                cap-sd-highspeed;
                status = "disabled";
        };
@@ -354,6 +415,8 @@
                compatible = "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;
                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
+                power-domains = <&pd_a3sp>;
                reg-io-width = <4>;
                status = "disabled";
        };
@@ -362,6 +425,8 @@
                compatible = "renesas,sh-mmcif";
                reg = <0 0xee220000 0 0x80>;
                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
+                power-domains = <&pd_a3sp>;
                reg-io-width = <4>;
                status = "disabled";
        };
@@ -377,4 +442,450 @@
                        <0 0xf1006000 0 0x2000>;
                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
+        bsc: bus@fec10000 {
+                compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
+                             "simple-pm-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0 0x20000000>;
+                reg = <0 0xfec10000 0 0x400>;
+                clocks = <&zb_clk>;
+                power-domains = <&pd_c4>;
+        };
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                /* External root clocks */
+                extalr_clk: extalr_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "extalr";
+                };
+                extal1_clk: extal1_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                        clock-output-names = "extal1";
+                };
+                extal2_clk: extal2_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <48000000>;
+                        clock-output-names = "extal2";
+                };
+                fsiack_clk: fsiack_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "fsiack";
+                };
+                fsibck_clk: fsibck_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "fsibck";
+                };
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a73a4-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x10000>;
+                        clocks = <&extal1_clk>, <&extal2_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll2",
+                                             "pll2s", "pll2h", "z", "z2",
+                                             "i", "m3", "b", "m1", "m2",
+                                             "zx", "zs", "hp";
+                };
+                /* Variable factor clocks (DIV6) */
+                zb_clk: zb_clk@e6150010 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150010 0 4>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "zb";
+                };
+                sdhi0_clk: sdhi0_clk@e6150074 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150074 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi0ck";
+                };
+                sdhi1_clk: sdhi1_clk@e6150078 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi1ck";
+                };
+                sdhi2_clk: sdhi2_clk@e615007c {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sdhi2ck";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                mmc1_clk: mmc1_clk@e6150244 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150244 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc1";
+                };
+                vclk1_clk: vclk1_clk@e6150008 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150008 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk1";
+                };
+                vclk2_clk: vclk2_clk@e615000c {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615000c 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk2";
+                };
+                vclk3_clk: vclk3_clk@e615001c {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615001c 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk3";
+                };
+                vclk4_clk: vclk4_clk@e6150014 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150014 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk4";
+                };
+                vclk5_clk: vclk5_clk@e6150034 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150034 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <0>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk5";
+                };
+                fsia_clk: fsia_clk@e6150018 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150018 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <&fsiack_clk>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsia";
+                };
+                fsib_clk: fsib_clk@e6150090 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150090 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <&fsibck_clk>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsib";
+                };
+                mp_clk: mp_clk@e6150080 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150080 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <&extal2_clk>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mp";
+                };
+                m4_clk: m4_clk@e6150098 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150098 0 4>;
+                        clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
+                        #clock-cells = <0>;
+                        clock-output-names = "m4";
+                };
+                hsi_clk: hsi_clk@e615026c {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615026c 0 4>;
+                        clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
+                                 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "hsi";
+                };
+                spuv_clk: spuv_clk@e6150094 {
+                        compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150094 0 4>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                                 <&extal2_clk>, <&extal2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "spuv";
+                };
+                /* Fixed factor clocks */
+                main_div2_clk: main_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "main_div2";
+                };
+                pll0_div2_clk: pll0_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll0_div2";
+                };
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                extal1_div2_clk: extal1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal1_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "extal1_div2";
+                };
+                /* Gate clocks */
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
+                                R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
+                                R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
+                                R8A73A4_CLK_DMAC
+                        >;
+                        clock-output-names =
+                                "scifa0", "scifa1", "scifb0", "scifb1",
+                                "scifb2", "scifb3", "dmac";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
+                                 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
+                                 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
+                                 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
+                                 R8A73A4_CLK_HP>, <&cpg_clocks
+                                 R8A73A4_CLK_HP>, <&extalr_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
+                                R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
+                                R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
+                                R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
+                                R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
+                                R8A73A4_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
+                                "mmcif0", "iic6", "iic7", "iic0", "iic1",
+                                "cmt1";
+                };
+                mstp4_clks: mstp4_clks@e6150140 {
+                        compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+                        clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
+                                 <&cpg_clocks R8A73A4_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
+                                R8A73A4_CLK_IIC3
+                        >;
+                        clock-output-names =
+                                "iic5", "iic4", "iic3";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
+                        >;
+                        clock-output-names =
+                                "thermal", "iic8";
+                };
+        };
+        sysc: system-controller@e6180000 {
+                compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
+                reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
+                pm-domains {
+                        pd_c5: c5 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #power-domain-cells = <0>;
+                                pd_c4: c4@0 {
+                                        reg = <0>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3sg: a3sg@16 {
+                                                reg = <16>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3ex: a3ex@17 {
+                                                reg = <17>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3sp: a3sp@18 {
+                                                reg = <18>;
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #power-domain-cells = <0>;
+                                                pd_a2us: a2us@19 {
+                                                        reg = <19>;
+                                                        #power-domain-cells = <0>;
+                                                };
+                                        };
+                                        pd_a3sm: a3sm@20 {
+                                                reg = <20>;
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #power-domain-cells = <0>;
+                                                pd_a2sl: a2sl@21 {
+                                                        reg = <21>;
+                                                        #power-domain-cells = <0>;
+                                                };
+                                        };
+                                        pd_a3km: a3km@22 {
+                                                reg = <22>;
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #power-domain-cells = <0>;
+                                                pd_a2kl: a2kl@23 {
+                                                        reg = <23>;
+                                                        #power-domain-cells = <0>;
+                                                };
+                                        };
+                                };
+                                pd_c4ma: c4ma@1 {
+                                        reg = <1>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_c4cl: c4cl@2 {
+                                        reg = <2>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_d4: d4@3 {
+                                        reg = <3>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4bc: a4bc@4 {
+                                        reg = <4>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3bc: a3bc@5 {
+                                                reg = <5>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                };
+                                pd_a4l: a4l@6 {
+                                        reg = <6>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4lc: a4lc@7 {
+                                        reg = <7>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4mp: a4mp@8 {
+                                        reg = <8>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3mp: a3mp@9 {
+                                                reg = <9>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3vc: a3vc@10 {
+                                                reg = <10>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                };
+                                pd_a4sf: a4sf@11 {
+                                        reg = <11>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a3r: a3r@12 {
+                                        reg = <12>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a2rv: a2rv@13 {
+                                                reg = <13>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a2is: a2is@14 {
+                                                reg = <14>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 8a092605d641..83c1c3ca1b8f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -431,6 +431,18 @@
                        clock-frequency = <27000000>;
                        clock-output-names = "dv";
                };
+                fmsick_clk: fmsick_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fmsick";
+                };
+                fmsock_clk: fmsock_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "fmsock";
+                };
                fsiack_clk: fsiack_clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -459,13 +471,78 @@
                };
                /* Variable factor clocks (DIV6) */
+                vclk1_clk: vclk1_clk@e6150008 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150008 4>;
+                        clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>,
+                                 <&extal1_div2_clk>, <&extalr_clk>, <0>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk1";
+                };
+                vclk2_clk: vclk2_clk@e615000c {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615000c 4>;
+                        clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>,
+                                 <&extal1_div2_clk>, <&extalr_clk>, <0>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vclk2";
+                };
+                fmsi_clk: fmsi_clk@e6150010 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150010 4>;
+                        clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fmsi";
+                };
+                fmso_clk: fmso_clk@e6150014 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150014 4>;
+                        clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fmso";
+                };
+                fsia_clk: fsia_clk@e6150018 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150018 4>;
+                        clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "fsia";
+                };
                sub_clk: sub_clk@e6150080 {
                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150080 4>;
-                        clocks = <&pllc1_div2_clk>;
+                        clocks = <&pllc1_div2_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "sub";
                };
+                spu_clk: spu_clk@e6150084 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150084 4>;
+                        clocks = <&pllc1_div2_clk>,
+                                 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "spu";
+                };
+                vou_clk: vou_clk@e6150088 {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe6150088 4>;
+                        clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
+                                 <0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "vou";
+                };
+                stpro_clk: stpro_clk@e615009c {
+                        compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0xe615009c 4>;
+                        clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
+                        #clock-cells = <0>;
+                        clock-output-names = "stpro";
+                };
                /* Fixed factor clocks */
                pllc1_div2_clk: pllc1_div2_clk {
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 46a884d45175..787fa6f9f46d 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -16,17 +16,191 @@
 /dts-v1/;
 #include "r8a7778.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "bockw";
        compatible = "renesas,bockw", "renesas,r8a7778";
+        aliases {
+                serial0 = &scif0;
+        };
        chosen {
                bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
+                stdout-path = &scif0;
        };
        memory {
                device_type = "memory";
                reg = <0x60000000 0x10000000>;
        };
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,bitclock-master = <&sndcodec>;
+                simple-audio-card,frame-master = <&sndcodec>;
+                sndcpu: simple-audio-card,cpu {
+                        sound-dai = <&rcar_sound>;
+                };
+                sndcodec: simple-audio-card,codec {
+                        sound-dai = <&ak4643>;
+                        system-clock-frequency = <11289600>;
+                };
+        };
+};
+&bsc {
+        ethernet@18300000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x18300000 0x1000>;
+                phy-mode = "mii";
+                interrupt-parent = <&irqpin>;
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+                reg-io-width = <4>;
+                vddvario-supply = <&fixedregulator3v3>;
+                vdd33a-supply = <&fixedregulator3v3>;
+        };
+};
+&extal_clk {
+        clock-frequency = <33333333>;
+};
+&i2c0 {
+        status = "okay";
+        ak4643: sound-codec@12 {
+                compatible = "asahi-kasei,ak4643";
+                #sound-dai-cells = <0>;
+                reg = <0x12>;
+        };
+        camera@41 {
+                compatible = "oki,ml86v7667";
+                reg = <0x41>;
+        };
+        camera@43 {
+                compatible = "oki,ml86v7667";
+                reg = <0x43>;
+        };
+        rx8581: rtc@51 {
+                compatible = "epson,rx8581";
+                reg = <0x51>;
+        };
+};
+&mmcif {
+        pinctrl-0 = <&mmc_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <8>;
+        broken-cd;
+        status = "okay";
+};
+&irqpin {
+        status = "okay";
+};
+&tmu0 {
+        status = "okay";
+};
+&pfc {
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_a", "scif0_ctrl";
+                renesas,function = "scif0";
+        };
+        mmc_pins: mmc {
+                renesas,groups = "mmc_data8", "mmc_ctrl";
+                renesas,function = "mmc";
+        };
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
+                                  "sdhi0_cd";
+                renesas,function = "sdhi0";
+        };
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0_a";
+                renesas,function = "hspi0";
+        };
+        usb0_pins: usb0 {
+                renesas,groups = "usb0";
+                renesas,function = "usb0";
+        };
+        usb1_pins: usb1 {
+                renesas,groups = "usb1";
+                renesas,function = "usb1";
+        };
+        vin0_pins: vin0 {
+                renesas,groups = "vin0_data8", "vin0_clk";
+                renesas,function = "vin0";
+        };
+        vin1_pins: vin1 {
+                renesas,groups = "vin1_data8", "vin1_clk";
+                renesas,function = "vin1";
+        };
+};
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+        wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+};
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        flash: flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl008k";
+                reg = <0>;
+                spi-max-frequency = <104000000>;
+                m25p,fast-read;
+                partition@0 {
+                        label = "data(spi)";
+                        reg = <0x00000000 0x00100000>;
+                };
+        };
+};
+&scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ef8533910029..868f97309533 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,7 @@
 /include/ "skeleton.dtsi"
+#include <dt-bindings/clock/r8a7778-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 / {
@@ -40,6 +41,24 @@
                spi2 = &hspi2;
        };
+        bsc: bus@1c000000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0x1c000000>;
+        };
+        ether: ethernet@fde00000 {
+                compatible = "renesas,ether-r8a7778";
+                reg = <0xfde00000 0x400>;
+                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+                phy-mode = "rmii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
        gic: interrupt-controller@fe438000 {
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
@@ -132,6 +151,7 @@
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc70000 0x1000>;
                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
                status = "disabled";
        };
@@ -141,6 +161,7 @@
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc71000 0x1000>;
                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
                status = "disabled";
        };
@@ -150,6 +171,7 @@
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc72000 0x1000>;
                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
                status = "disabled";
        };
@@ -159,6 +181,7 @@
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc73000 0x1000>;
                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
                status = "disabled";
        };
@@ -168,6 +191,8 @@
                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
                             <0 34 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
+                clock-names = "fck";
                #renesas,channels = <3>;
@@ -180,6 +205,8 @@
                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
                             <0 38 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
+                clock-names = "fck";
                #renesas,channels = <3>;
@@ -192,16 +219,75 @@
                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
                             <0 42 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
+                clock-names = "fck";
                #renesas,channels = <3>;
                status = "disabled";
        };
+        rcar_sound: sound@ffd90000 {
+                #sound-dai-cells = <1>;
+                compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
+                reg =   <0xffd90000 0x1000>,    /* SRU */
+                        <0xffd91000 0x1240>,    /* SSI */
+                        <0xfffe0000 0x24>;      /* ADG */
+                clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
+                        <&mstp3_clks R8A7778_CLK_SSI7>,
+                        <&mstp3_clks R8A7778_CLK_SSI6>,
+                        <&mstp3_clks R8A7778_CLK_SSI5>,
+                        <&mstp3_clks R8A7778_CLK_SSI4>,
+                        <&mstp0_clks R8A7778_CLK_SSI3>,
+                        <&mstp0_clks R8A7778_CLK_SSI2>,
+                        <&mstp0_clks R8A7778_CLK_SSI1>,
+                        <&mstp0_clks R8A7778_CLK_SSI0>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
+                        <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
+                        <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                        <&cpg_clocks R8A7778_CLK_S1>;
+                clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
+                        "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+                        "src.8", "src.7", "src.6", "src.5", "src.4",
+                        "src.3", "src.2", "src.1", "src.0",
+                        "clk_a", "clk_b", "clk_c", "clk_i";
+                status = "disabled";
+                rcar_sound,src {
+                        src3: src@3 { };
+                        src4: src@4 { };
+                        src5: src@5 { };
+                        src6: src@6 { };
+                        src7: src@7 { };
+                        src8: src@8 { };
+                        src9: src@9 { };
+                };
+                rcar_sound,ssi {
+                        ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                };
+        };
        scif0: serial@ffe40000 {
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe40000 0x100>;
                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -209,6 +295,8 @@
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe41000 0x100>;
                interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -216,6 +304,8 @@
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe42000 0x100>;
                interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -223,6 +313,8 @@
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe43000 0x100>;
                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -230,6 +322,8 @@
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe44000 0x100>;
                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -237,6 +331,8 @@
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe45000 0x100>;
                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
+                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -244,6 +340,7 @@
                compatible = "renesas,sh-mmcif";
                reg = <0xffe4e000 0x100>;
                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7778_CLK_MMC>;
                status = "disabled";
        };
@@ -251,6 +348,7 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4c000 0x100>;
                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
                status = "disabled";
        };
@@ -258,6 +356,7 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4d000 0x100>;
                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
                status = "disabled";
        };
@@ -265,6 +364,7 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4f000 0x100>;
                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
                status = "disabled";
        };
@@ -272,6 +372,7 @@
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc7000 0x18>;
                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -281,6 +382,7 @@
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc8000 0x18>;
                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
@@ -290,8 +392,199 @@
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc6000 0x18>;
                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                /* External input clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@ffc80000 {
+                        compatible = "renesas,r8a7778-cpg-clocks";
+                        reg = <0xffc80000 0x80>;
+                        #clock-cells = <1>;
+                        clocks = <&extal_clk>;
+                        clock-output-names = "plla", "pllb", "b",
+                                             "out", "p", "s", "s1";
+                };
+                /* Audio clocks; frequencies are set by boards if applicable. */
+                audio_clk_a: audio_clk_a {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-output-names = "audio_clk_a";
+                };
+                audio_clk_b: audio_clk_b {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-output-names = "audio_clk_b";
+                };
+                audio_clk_c: audio_clk_c {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-output-names = "audio_clk_c";
+                };
+                /* Fixed ratio clocks */
+                g_clk: g_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "g";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                s3_clk: s3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "s3";
+                };
+                s4_clk: s4_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "s4";
+                };
+                z_clk: z_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clock-output-names = "z";
+                };
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@ffc80030 {
+                        compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80030 4>;
+                        clocks = <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_S>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
+                                R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
+                                R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
+                                R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
+                                R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
+                                R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
+                                R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
+                                R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
+                                R8A7778_CLK_SSI3 R8A7778_CLK_SRU
+                                R8A7778_CLK_HSPI
+                        >;
+                        clock-output-names =
+                                "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
+                                "scif1", "scif2", "scif3", "scif4", "scif5",
+                                "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
+                                "ssi2", "ssi3", "sru", "hspi";
+                };
+                mstp1_clks: mstp1_clks@ffc80034 {
+                        compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80034 4>, <0xffc80044 4>;
+                        clocks = <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_S>,
+                                 <&cpg_clocks R8A7778_CLK_S>,
+                                 <&cpg_clocks R8A7778_CLK_P>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7778_CLK_ETHER R8A7778_CLK_VIN0
+                                R8A7778_CLK_VIN1 R8A7778_CLK_USB
+                        >;
+                        clock-output-names =
+                                "ether", "vin0", "vin1", "usb";
+                };
+                mstp3_clks: mstp3_clks@ffc8003c {
+                        compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xffc8003c 4>;
+                        clocks = <&s4_clk>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7778_CLK_MMC R8A7778_CLK_SDHI0
+                                R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
+                                R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
+                                R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
+                                R8A7778_CLK_SSI8
+                        >;
+                        clock-output-names =
+                                "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
+                                "ssi5", "ssi6", "ssi7", "ssi8";
+                };
+                mstp5_clks: mstp5_clks@ffc80054 {
+                        compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80054 4>;
+                        clocks = <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_P>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
+                                R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
+                                R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
+                                R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
+                                R8A7778_CLK_SRU_SRC8
+                        >;
+                        clock-output-names =
+                                "sru-src0", "sru-src1", "sru-src2",
+                                "sru-src3", "sru-src4", "sru-src5",
+                                "sru-src6", "sru-src7", "sru-src8";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index e83d40e24bcd..540756cdf391 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -122,6 +122,12 @@
                        };
                };
        };
+        x3_clk: x3-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <65000000>;
+        };
 };
 &du {
@@ -129,6 +135,9 @@
        pinctrl-names = "default";
        status = "okay";
+        clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
+        clock-names = "du", "dclkin.0";
        ports {
                port@0 {
                        endpoint {
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 0c3b6783b72a..aaa4f258e279 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -222,6 +222,29 @@
                        };
                };
        };
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+        x2_clk: x2-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+        x13_clk: x13-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
 };
 &du {
@@ -229,12 +252,26 @@
        pinctrl-names = "default";
        status = "okay";
+        clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+                 <&mstp7_clks R8A7790_CLK_DU1>,
+                 <&mstp7_clks R8A7790_CLK_DU2>,
+                 <&mstp7_clks R8A7790_CLK_LVDS0>,
+                 <&mstp7_clks R8A7790_CLK_LVDS1>,
+                 <&x13_clk>, <&x2_clk>;
+        clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+                      "dclkin.0", "dclkin.1";
        ports {
                port@0 {
                        endpoint {
                                remote-endpoint = <&adv7123_in>;
                        };
                };
+                port@1 {
+                        endpoint {
+                                remote-endpoint = <&adv7511_in>;
+                        };
+                };
                port@2 {
                        lvds_connector: endpoint {
                        };
@@ -506,6 +543,38 @@
                        };
                };
        };
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&du_out_lvds0>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
 };
 &iic3 {
@@ -513,9 +582,27 @@
        pinctrl-0 = <&iic3_pins>;
        status = "okay";
+        pmic@58 {
+                compatible = "dlg,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                rtc {
+                        compatible = "dlg,da9063-rtc";
+                };
+                wdt {
+                        compatible = "dlg,da9063-watchdog";
+                };
+        };
        vdd_dvfs: regulator@68 {
                compatible = "dlg,da9210";
                reg = <0x68>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                regulator-min-microvolt = <1000000>;
                regulator-max-microvolt = <1000000>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4b38fc920114..4bb2f4c17321 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,6 +1,7 @@
 /*
 * Device Tree Source for the r8a7790 SoC
 *
+ * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded Inc.
 *
@@ -369,13 +370,6 @@
                dma-channels = <13>;
        };
-        audmapp: dma-controller@ec740000 {
-                compatible = "renesas,rcar-audmapp";
-                #dma-cells = <1>;
-                reg = <0 0xec740000 0 0x200>;
-        };
        i2c0: i2c@e6508000 {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -493,17 +487,21 @@
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a7790";
-                reg = <0 0xee100000 0 0x200>;
+                reg = <0 0xee100000 0 0x328>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
+                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
        sdhi1: sd@ee120000 {
                compatible = "renesas,sdhi-r8a7790";
-                reg = <0 0xee120000 0 0x200>;
+                reg = <0 0xee120000 0 0x328>;
                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
+                dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -512,6 +510,8 @@
                reg = <0 0xee140000 0 0x100>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
+                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -520,6 +520,8 @@
                reg = <0 0xee160000 0 0x100>;
                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
+                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -792,6 +794,26 @@
                };
        };
+        can0: can@e6e80000 {
+                compatible = "renesas,can-r8a7790";
+                reg = <0 0xe6e80000 0 0x1000>;
+                interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
+                         <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+        can1: can@e6e88000 {
+                compatible = "renesas,can-r8a7790";
+                reg = <0 0xe6e88000 0 0x1000>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
+                         <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -838,16 +860,34 @@
                        clock-output-names = "audio_clk_c";
                };
+                /* External USB clock - can be overridden by the board */
+                usb_extal_clk: usb_extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <48000000>;
+                        clock-output-names = "usb_extal";
+                };
+                /* External CAN clock */
+                can_clk: can_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "can_clk";
+                        status = "disabled";
+                };
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7790-cpg-clocks",
                                     "renesas,rcar-gen2-cpg-clocks";
                        reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>;
+                        clocks = <&extal_clk &usb_extal_clk>;
                        #clock-cells = <1>;
                        clock-output-names = "main", "pll0", "pll1", "pll3",
                                             "lb", "qspi", "sdh", "sd0", "sd1",
-                                             "z";
+                                             "z", "rcan", "adsp";
                };
                /* Variable factor clocks */
@@ -1121,18 +1161,21 @@
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
+                                 <&extal_clk>, <&p_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
-                                R8A7790_CLK_THERMAL R8A7790_CLK_PWM
+                                R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
+                                R8A7790_CLK_PWM
                        >;
-                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
+                        clock-output-names = "audmac0", "audmac1", "adsp_mod",
+                                             "thermal", "pwm";
                };
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                        clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                        clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
                                 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
                                 <&zx_clk>;
                        #clock-cells = <1>;
@@ -1410,7 +1453,10 @@
                reg =   <0 0xec500000 0 0x1000>, /* SCU */
                        <0 0xec5a0000 0 0x100>,  /* ADG */
                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x1280>; /* SSI */
+                        <0 0xec541000 0 0x1280>, /* SSI */
+                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
                clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
                        <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
                        <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
@@ -1435,34 +1481,171 @@
                status = "disabled";
                rcar_sound,dvc {
-                        dvc0: dvc@0 { };
+                        dvc0: dvc@0 {
-                        dvc1: dvc@1 { };
+                                dmas = <&audma0 0xbc>;
+                                dma-names = "tx";
+                        };
+                        dvc1: dvc@1 {
+                                dmas = <&audma0 0xbe>;
+                                dma-names = "tx";
+                        };
                };
                rcar_sound,src {
-                        src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
+                        src0: src@0 {
-                        src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
-                        src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
-                        src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx";
-                        src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
-                        src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
+                        src1: src@1 {
-                        src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
-                        src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
-                        src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx";
-                        src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
+                        src2: src@2 {
+                                interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                dma-names = "rx", "tx";
+                        };
+                        src3: src@3 {
+                                interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src4: src@4 {
+                                interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src5: src@5 {
+                                interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                dma-names = "rx", "tx";
+                        };
+                        src6: src@6 {
+                                interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                dma-names = "rx", "tx";
+                        };
+                        src7: src@7 {
+                                interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                dma-names = "rx", "tx";
+                        };
+                        src8: src@8 {
+                                interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                dma-names = "rx", "tx";
+                        };
+                        src9: src@9 {
+                                interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                dma-names = "rx", "tx";
+                        };
                };
                rcar_sound,ssi {
-                        ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi0: ssi@0 {
-                        ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
-                        ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                        ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx", "rxu", "txu";
-                        ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
-                        ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi1: ssi@1 {
-                        ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
+                                 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
-                        ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                        ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx", "rxu", "txu";
-                        ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
+                        ssi2: ssi@2 {
+                                interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi3: ssi@3 {
+                                interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi4: ssi@4 {
+                                interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi5: ssi@5 {
+                                interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi6: ssi@6 {
+                                interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi7: ssi@7 {
+                                interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi8: ssi@8 {
+                                interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi9: ssi@9 {
+                                interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
                };
        };
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_rt: mmu@ffc80000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xffc80000 0 0x1000>;
+                interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index d2ebf11f9881..e33e4047b0b0 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -141,6 +141,11 @@
                renesas,groups = "vin0_data8", "vin0_clk";
                renesas,function = "vin0";
        };
+        can0_pins: can0 {
+                renesas,groups = "can0_data";
+                renesas,function = "can0";
+        };
 };
 &scif0 {
@@ -307,3 +312,9 @@
                };
        };
 };
+&can0 {
+        pinctrl-0 = <&can0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a3c27807f6c5..74c3212f1f11 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -258,6 +258,29 @@
                        system-clock-frequency = <11289600>;
                };
        };
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+        x2_clk: x2-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+        x13_clk: x13-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
 };
 &du {
@@ -265,7 +288,19 @@
        pinctrl-names = "default";
        status = "okay";
+        clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+                 <&mstp7_clks R8A7791_CLK_DU1>,
+                 <&mstp7_clks R8A7791_CLK_LVDS0>,
+                 <&x13_clk>, <&x2_clk>;
+        clock-names = "du.0", "du.1", "lvds.0",
+                      "dclkin.0", "dclkin.1";
        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7511_in>;
+                        };
+                };
                port@1 {
                        lvds_connector: endpoint {
                        };
@@ -284,7 +319,7 @@
        };
        du_pins: du {
-                renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
+                renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0";
                renesas,function = "du";
        };
@@ -506,6 +541,38 @@
                };
        };
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
        eeprom@50 {
                compatible = "renesas,24c02";
                reg = <0x50>;
@@ -517,9 +584,27 @@
        status = "okay";
        clock-frequency = <100000>;
+        pmic@58 {
+                compatible = "dlg,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                rtc {
+                        compatible = "dlg,da9063-rtc";
+                };
+                wdt {
+                        compatible = "dlg,da9063-watchdog";
+                };
+        };
        vdd_dvfs: regulator@68 {
                compatible = "dlg,da9210";
                reg = <0x68>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                regulator-min-microvolt = <1000000>;
                regulator-max-microvolt = <1000000>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e35812a0d8d4..4696062f6dde 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
 /*
 * Device Tree Source for the r8a7791 SoC
 *
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2015 Renesas Electronics Corporation
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded Inc.
 *
@@ -357,13 +357,6 @@
                dma-channels = <13>;
        };
-        audmapp: dma-controller@ec740000 {
-                compatible = "renesas,rcar-audmapp";
-                #dma-cells = <1>;
-                reg = <0 0xec740000 0 0x200>;
-        };
        /* The memory map in the User's Manual maps the cores to bus numbers */
        i2c0: i2c@e6508000 {
                #address-cells = <1>;
@@ -482,9 +475,11 @@
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a7791";
-                reg = <0 0xee100000 0 0x200>;
+                reg = <0 0xee100000 0 0x328>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
+                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -493,6 +488,8 @@
                reg = <0 0xee140000 0 0x100>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
+                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -501,6 +498,8 @@
                reg = <0 0xee160000 0 0x100>;
                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
+                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -816,6 +815,26 @@
                };
        };
+        can0: can@e6e80000 {
+                compatible = "renesas,can-r8a7791";
+                reg = <0 0xe6e80000 0 0x1000>;
+                interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
+                         <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+        can1: can@e6e88000 {
+                compatible = "renesas,can-r8a7791";
+                reg = <0 0xe6e88000 0 0x1000>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
+                         <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -862,31 +881,50 @@
                        status = "disabled";
                };
+                /* External USB clock - can be overridden by the board */
+                usb_extal_clk: usb_extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <48000000>;
+                        clock-output-names = "usb_extal";
+                };
+                /* External CAN clock */
+                can_clk: can_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overridden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "can_clk";
+                        status = "disabled";
+                };
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7791-cpg-clocks",
                                     "renesas,rcar-gen2-cpg-clocks";
                        reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>;
+                        clocks = <&extal_clk &usb_extal_clk>;
                        #clock-cells = <1>;
                        clock-output-names = "main", "pll0", "pll1", "pll3",
-                                             "lb", "qspi", "sdh", "sd0", "z";
+                                             "lb", "qspi", "sdh", "sd0", "z",
+                                             "rcan", "adsp";
                };
                /* Variable factor clocks */
-                sd1_clk: sd2_clk@e6150078 {
+                sd2_clk: sd2_clk@e6150078 {
                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe6150078 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                        clock-output-names = "sd1";
+                        clock-output-names = "sd2";
                };
-                sd2_clk: sd3_clk@e615026c {
+                sd3_clk: sd3_clk@e615026c {
                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe615026c 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                        clock-output-names = "sd2";
+                        clock-output-names = "sd3";
                };
                mmc0_clk: mmc0_clk@e6150240 {
                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
@@ -1107,7 +1145,7 @@
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
+                        clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
                                 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
                                 <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
@@ -1125,18 +1163,21 @@
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
+                                 <&extal_clk>, <&p_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
-                                R8A7791_CLK_THERMAL R8A7791_CLK_PWM
+                                R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
+                                R8A7791_CLK_PWM
                        >;
-                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
+                        clock-output-names = "audmac0", "audmac1", "adsp_mod",
+                                             "thermal", "pwm";
                };
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                        clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                        clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
                                 <&zx_clk>, <&zx_clk>, <&zx_clk>;
                        #clock-cells = <1>;
@@ -1154,7 +1195,7 @@
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
+                        clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
                                 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
@@ -1384,6 +1425,66 @@
                status = "disabled";
        };
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_rt: mmu@ffc80000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xffc80000 0 0x1000>;
+                interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_gp: mmu@e62a0000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe62a0000 0 0x1000>;
+                interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 261 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
        rcar_sound: rcar_sound@ec500000 {
                /*
                 * #sound-dai-cells is required
@@ -1395,7 +1496,10 @@
                reg =   <0 0xec500000 0 0x1000>, /* SCU */
                        <0 0xec5a0000 0 0x100>,  /* ADG */
                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x1280>; /* SSI */
+                        <0 0xec541000 0 0x1280>, /* SSI */
+                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
                clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
                        <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
                        <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
@@ -1420,34 +1524,120 @@
                status = "disabled";
                rcar_sound,dvc {
-                        dvc0: dvc@0 { };
+                        dvc0: dvc@0 {
-                        dvc1: dvc@1 { };
+                                dmas = <&audma0 0xbc>;
+                                dma-names = "tx";
+                        };
+                        dvc1: dvc@1 {
+                                dmas = <&audma0 0xbe>;
+                                dma-names = "tx";
+                        };
                };
                rcar_sound,src {
-                        src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
+                        src0: src@0 {
-                        src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
-                        src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
-                        src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx";
-                        src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
-                        src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
+                        src1: src@1 {
-                        src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
-                        src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
-                        src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx";
-                        src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
+                        src2: src@2 {
+                                interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                dma-names = "rx", "tx";
+                        };
+                        src3: src@3 {
+                                interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src4: src@4 {
+                                interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                dma-names = "rx", "tx";
+                        };
+                        src5: src@5 {
+                                interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                dma-names = "rx", "tx";
+                        };
+                        src6: src@6 {
+                                interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                dma-names = "rx", "tx";
+                        };
+                        src7: src@7 {
+                                interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                dma-names = "rx", "tx";
+                        };
+                        src8: src@8 {
+                                interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                dma-names = "rx", "tx";
+                        };
+                        src9: src@9 {
+                                interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                dma-names = "rx", "tx";
+                        };
                };
                rcar_sound,ssi {
-                        ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi0: ssi@0 {
-                        ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
+                                interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
-                        ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                        ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx", "rxu", "txu";
-                        ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
-                        ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi1: ssi@1 {
-                        ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
+                                 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
-                        ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
+                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                        ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
+                                dma-names = "rx", "tx", "rxu", "txu";
-                        ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
+                        };
+                        ssi2: ssi@2 {
+                                interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi3: ssi@3 {
+                                interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi4: ssi@4 {
+                                interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi5: ssi@5 {
+                                interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi6: ssi@6 {
+                                interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi7: ssi@7 {
+                                interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi8: ssi@8 {
+                                interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
+                        ssi9: ssi@9 {
+                                interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                dma-names = "rx", "tx", "rxu", "txu";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 0d848e605071..928cfa641475 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -43,6 +43,19 @@
        status = "okay";
 };
+&ether {
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "okay";
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
+        };
+};
 &scif2 {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8f78da5ef10b..7a3ffa51a8bf 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -107,6 +107,66 @@
                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
        };
+        dmac0: dma-controller@e6700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6700000 0 0x20000>;
+                interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+                              0 200 IRQ_TYPE_LEVEL_HIGH
+                              0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH
+                              0 205 IRQ_TYPE_LEVEL_HIGH
+                              0 206 IRQ_TYPE_LEVEL_HIGH
+                              0 207 IRQ_TYPE_LEVEL_HIGH
+                              0 208 IRQ_TYPE_LEVEL_HIGH
+                              0 209 IRQ_TYPE_LEVEL_HIGH
+                              0 210 IRQ_TYPE_LEVEL_HIGH
+                              0 211 IRQ_TYPE_LEVEL_HIGH
+                              0 212 IRQ_TYPE_LEVEL_HIGH
+                              0 213 IRQ_TYPE_LEVEL_HIGH
+                              0 214 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
+        dmac1: dma-controller@e6720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xe6720000 0 0x20000>;
+                interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                              0 216 IRQ_TYPE_LEVEL_HIGH
+                              0 217 IRQ_TYPE_LEVEL_HIGH
+                              0 218 IRQ_TYPE_LEVEL_HIGH
+                              0 219 IRQ_TYPE_LEVEL_HIGH
+                              0 308 IRQ_TYPE_LEVEL_HIGH
+                              0 309 IRQ_TYPE_LEVEL_HIGH
+                              0 310 IRQ_TYPE_LEVEL_HIGH
+                              0 311 IRQ_TYPE_LEVEL_HIGH
+                              0 312 IRQ_TYPE_LEVEL_HIGH
+                              0 313 IRQ_TYPE_LEVEL_HIGH
+                              0 314 IRQ_TYPE_LEVEL_HIGH
+                              0 315 IRQ_TYPE_LEVEL_HIGH
+                              0 316 IRQ_TYPE_LEVEL_HIGH
+                              0 317 IRQ_TYPE_LEVEL_HIGH
+                              0 318 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12", "ch13", "ch14";
+                clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <15>;
+        };
        scifa0: serial@e6c40000 {
                compatible = "renesas,scifa-r8a7794", "renesas,scifa";
                reg = <0 0xe6c40000 0 64>;
@@ -269,6 +329,41 @@
                status = "disabled";
        };
+        ether: ethernet@ee700000 {
+                compatible = "renesas,ether-r8a7794";
+                reg = <0 0xee700000 0 0x400>;
+                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+                phy-mode = "rmii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        sdhi0: sd@ee100000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee100000 0 0x200>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+                status = "disabled";
+        };
+        sdhi1: sd@ee140000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee140000 0 0x100>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+                status = "disabled";
+        };
+        sdhi2: sd@ee160000 {
+                compatible = "renesas,sdhi-r8a7794";
+                reg = <0 0xee160000 0 0x100>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+                status = "disabled";
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -294,19 +389,19 @@
                                             "lb", "qspi", "sdh", "sd0", "z";
                };
                /* Variable factor clocks */
-                sd1_clk: sd2_clk@e6150078 {
+                sd2_clk: sd2_clk@e6150078 {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe6150078 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                        clock-output-names = "sd1";
+                        clock-output-names = "sd2";
                };
-                sd2_clk: sd3_clk@e615007c {
+                sd3_clk: sd3_clk@e615026c {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
-                        reg = <0 0xe615007c 0 4>;
+                        reg = <0 0xe615026c 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                        clock-output-names = "sd2";
+                        clock-output-names = "sd3";
                };
                mmc0_clk: mmc0_clk@e6150240 {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
@@ -518,7 +613,7 @@
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
+                        clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
                                 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
@@ -585,4 +680,54 @@
                        clock-output-names = "scifa3", "scifa4", "scifa5";
                };
        };
+        ipmmu_sy0: mmu@e6280000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6280000 0 0x1000>;
+                interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 224 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_sy1: mmu@e6290000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6290000 0 0x1000>;
+                interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_ds: mmu@e6740000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe6740000 0 0x1000>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+        };
+        ipmmu_mp: mmu@ec680000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xec680000 0 0x1000>;
+                interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
+        ipmmu_mx: mmu@fe951000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xfe951000 0 0x1000>;
+                interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 221 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+        };
+        ipmmu_gp: mmu@e62a0000 {
+                compatible = "renesas,ipmmu-vmsa";
+                reg = <0 0xe62a0000 0 0x1000>;
+                interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 261 IRQ_TYPE_LEVEL_HIGH>;
+                #iommu-cells = <1>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 9a09579b8309..bdf85701987d 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -103,6 +103,14 @@
                regulator-always-on;
                regulator-boot-on;
        };
+        vsys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vsys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
 };
 &emac {
@@ -148,6 +156,14 @@
                pinctrl-names = "default";
                pinctrl-0 = <&act8846_dvs0_ctl>;
+                vp1-supply = <&vsys>;
+                vp2-supply = <&vsys>;
+                vp3-supply = <&vsys>;
+                vp4-supply = <&vsys>;
+                inl1-supply = <&vcc_io>;
+                inl2-supply = <&vsys>;
+                inl3-supply = <&vsys>;
                regulators {
                        vcc_ddr: REG1 {
                                regulator-name = "VCC_DDR";
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index d7b8bbc0c25f..1687e8336994 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -33,6 +33,7 @@
                regulator-max-microvolt = <1350000>;
                regulator-always-on;
                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
        };
        vdd_gpu: syr828@41 {
@@ -43,6 +44,7 @@
                regulator-min-microvolt = <850000>;
                regulator-max-microvolt = <1350000>;
                regulator-always-on;
+                vin-supply = <&vcc_sys>;
        };
        hym8563@51 {
@@ -64,6 +66,14 @@
                reg = <0x5a>;
                status = "okay";
+                vp1-supply = <&vcc_sys>;
+                vp2-supply = <&vcc_sys>;
+                vp3-supply = <&vcc_sys>;
+                vp4-supply = <&vcc_sys>;
+                inl1-supply = <&vcc_io>;
+                inl2-supply = <&vcc_sys>;
+                inl3-supply = <&vcc_20>;
                regulators {
                        vcc_ddr: REG1 {
                                regulator-name = "VCC_DDR";
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index a1c294bf7fed..f62ea78754a9 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -43,9 +43,16 @@
                #clock-cells = <1>;
                clock-output-names = "xin32k", "rk808-clkout2";
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
                vcc8-supply = <&vcc_18>;
                vcc9-supply = <&vcc_io>;
                vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
                vcc12-supply = <&vcc_io>;
                vddio-supply = <&vccio_pmu>;
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 5e895a514a0b..4a457518d861 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -103,6 +103,15 @@
                regulator-always-on;
                regulator-boot-on;
        };
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
 };
 &emmc {
@@ -238,6 +247,10 @@
        };
 };
+&usbphy {
+        status = "okay";
+};
 &usb_host0_ehci {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index e6f873abbe0d..b54dd78580c1 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -179,6 +179,22 @@
        status = "okay";
 };
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        clock_in_out = "input";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
 &hdmi {
        ddc-i2c-bus = <&i2c5>;
        status = "okay";
@@ -459,6 +475,10 @@
        status = "okay";
 };
+&usbphy {
+        status = "okay";
+};
 &usb_host1 {
        pinctrl-names = "default";
        pinctrl-0 = <&usbhub_rst>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
new file mode 100644
index 000000000000..d081f0e0da36
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2014, 2015 Andy Yan <andy.yan@rock-chips.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "rk3288.dtsi"
+/ {
+        model = "PopMetal-RK3288";
+        compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+        memory{
+                reg = <0 0x80000000>;
+        };
+        ext_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+                #clock-cells = <0>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwrbtn>;
+                button@0 {
+                        gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <116>;
+                        label = "GPIO Key Power";
+                        linux,input-type = <1>;
+                        gpio-key,wakeup = <1>;
+                        debounce-interval = <100>;
+                };
+        };
+        ir: ir-receiver {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ir_int>;
+        };
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
+&emmc {
+        broken-cd;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        non-removable;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+        status = "okay";
+};
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;                     /* wp not hooked up */
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+};
+&gmac {
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio4 7 0>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
+&hdmi {
+        ddc-i2c-bus = <&i2c5>;
+        status = "okay";
+};
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int &global_pwroff>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc_18>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vcc_io>;
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "vdd_arm";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+                        vcc_lan: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_lan";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+                        vccio_sd: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+                        vcc18_lcd: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+                        ldo5: LDO_REG5 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "ldo5";
+                        };
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+                        vcca_codec: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcca_codec";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+                        vcc_wl: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_wl";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                        vcc_lcd: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+        ak8963: ak8963@0d {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0d>;
+                interrupt-parent = <&gpio8>;
+                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&comp_int>;
+        };
+        l3g4200d: l3g4200d@68 {
+                compatible = "st,l3g4200d-gyro";
+                st,drdy-int-pin = <2>;
+                reg = <0x6b>;
+        };
+        mma8452: mma8452@1d {
+                compatible = "fsl,mma8452";
+                reg = <0x1d>;
+                interrupt-parent = <&gpio8>;
+                interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&gsensor_int>;
+        };
+};
+&i2c2 {
+        status = "okay";
+};
+&i2c3 {
+        status = "okay";
+};
+&i2c4 {
+        status = "okay";
+};
+&i2c5 {
+        status = "okay";
+};
+&pinctrl {
+        ak8963 {
+                comp_int: comp-int {
+                        rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+        buttons {
+                pwrbtn: pwrbtn {
+                        rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+        ir {
+                ir_int: ir-int {
+                        rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+        mma8452 {
+                gsensor_int: gsensor-int {
+                        rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+};
+&vopb {
+        status = "okay";
+};
+&vopb_mmu {
+        status = "okay";
+};
+&vopl {
+        status = "okay";
+};
+&vopl_mmu {
+        status = "okay";
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
+&uart2 {
+        status = "okay";
+};
+&uart3 {
+        status = "okay";
+};
+&uart4 {
+        status = "okay";
+};
+&usbphy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index eccc78d3220b..165968d51d8f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -420,6 +420,8 @@
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_USBHOST0>;
                clock-names = "usbhost";
+                phys = <&usbphy1>;
+                phy-names = "usb";
                status = "disabled";
        };
@@ -432,6 +434,8 @@
                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_USBHOST1>;
                clock-names = "otg";
+                phys = <&usbphy2>;
+                phy-names = "usb2-phy";
                status = "disabled";
        };
@@ -442,6 +446,8 @@
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_OTG0>;
                clock-names = "otg";
+                phys = <&usbphy0>;
+                phy-names = "usb2-phy";
                status = "disabled";
        };
@@ -698,6 +704,35 @@
                interrupts = <GIC_PPI 9 0xf04>;
        };
+        usbphy: phy {
+                compatible = "rockchip,rk3288-usb-phy";
+                rockchip,grf = <&grf>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+                usbphy0: usb-phy0 {
+                        #phy-cells = <0>;
+                        reg = <0x320>;
+                        clocks = <&cru SCLK_OTGPHY0>;
+                        clock-names = "phyclk";
+                };
+                usbphy1: usb-phy1 {
+                        #phy-cells = <0>;
+                        reg = <0x334>;
+                        clocks = <&cru SCLK_OTGPHY1>;
+                        clock-names = "phyclk";
+                };
+                usbphy2: usb-phy2 {
+                        #phy-cells = <0>;
+                        reg = <0x348>;
+                        clocks = <&cru SCLK_OTGPHY2>;
+                        clock-names = "phyclk";
+                };
+        };
        pinctrl: pinctrl {
                compatible = "rockchip,rk3288-pinctrl";
                rockchip,grf = <&grf>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 367af53c1b84..57ab8587f7b9 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -26,6 +26,7 @@
                serial2 = &usart1;
                serial3 = &usart2;
                serial4 = &usart3;
+                serial5 = &uart0;
                gpio0 = &pioA;
                gpio1 = &pioB;
                gpio2 = &pioC;
@@ -206,6 +207,17 @@
                                status = "disabled";
                        };
+                        uart0: serial@f0024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf0024000 0x100>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                clocks = <&uart0_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
                        pwm0: pwm@f002c000 {
                                compatible = "atmel,sama5d3-pwm";
                                reg = <0xf002c000 0x300>;
@@ -439,7 +451,7 @@
                        };
                        dbgu: serial@ffffee00 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
@@ -764,6 +776,22 @@
                                        };
                                };
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* conflicts with PWMFI2, ISI_D8 */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* conflicts with ISI_PCK */
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* conflicts with TWD0, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* conflicts with TWCK0, ISI_HSYNC */
+                                        };
+                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
@@ -1098,6 +1126,12 @@
                                                atmel,clk-output-range = <0 66000000>;
                                        };
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
                                        twi0_clk: twi0_clk {
                                                reg = <18>;
                                                #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 9089c7c6cea8..d9a9aca1ccfd 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -44,8 +44,6 @@
        gpio_keys {
                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
                pb_user1 {
                        label = "pb_user1";
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index eaf41451ad0c..c5a3772741bf 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * CAN support
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index b4544cf11bad..7cb235ef0fb6 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * Ethernet.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index de5ed59fb446..23f225fbb756 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * Gigabit Ethernet.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 85d302701565..be7cfefc6c31 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * LCD support
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -13,40 +13,183 @@
 / {
        ahb {
                apb {
+                        hlcdc: hlcdc@f0030000 {
+                                compatible = "atmel,sama5d3-hlcdc";
+                                reg = <0xf0030000 0x2000>;
+                                interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+                                clock-names = "periph_clk","sys_clk", "slow_clk";
+                                status = "disabled";
+                                hlcdc-display-controller {
+                                        compatible = "atmel,hlcdc-display-controller";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        port@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                reg = <0>;
+                                        };
+                                };
+                                hlcdc_pwm: hlcdc-pwm {
+                                        compatible = "atmel,hlcdc-pwm";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_lcd_pwm>;
+                                        #pwm-cells = <3>;
+                                };
+                        };
                        pinctrl@fffff200 {
                                lcd {
-                                        pinctrl_lcd: lcd-0 {
+                                        pinctrl_lcd_base: lcd-base-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDISP */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+                                        };
+                                        pinctrl_lcd_pwm: lcd-pwm-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
+                                        };
+                                        pinctrl_lcd_rgb444: lcd-rgb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
+                                        };
+                                        pinctrl_lcd_rgb565: lcd-rgb-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
+                                        };
+                                        pinctrl_lcd_rgb666: lcd-rgb-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
+                                        };
+                                        pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD17 pin */
+                                        };
+                                        pinctrl_lcd_rgb888: lcd-rgb-3 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                        pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt {
                                                atmel,pins =
-                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA24 periph A LCDPWM */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
-                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA26 periph A LCDVSYNC */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
-                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA27 periph A LCDHSYNC */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
-                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA25 periph A LCDDISP */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
-                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA29 periph A LCDDEN */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
-                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA28 periph A LCDPCK */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
-                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A LCDD0 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
-                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A LCDD1 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
-                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA2 periph A LCDD2 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
-                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA3 periph A LCDD3 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
-                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA4 periph A LCDD4 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
-                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA5 periph A LCDD5 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
-                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA6 periph A LCDD6 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
-                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A LCDD7 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
-                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A LCDD8 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
-                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A LCDD9 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
-                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A LCDD10 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD16 pin */
-                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A LCDD11 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD17 pin */
-                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A LCDD12 pin */
+                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD18 pin */
-                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A LCDD13 pin */
+                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD19 pin */
-                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A LCDD14 pin */
+                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD20 pin */
-                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A LCDD15 pin */
+                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD21 pin */
-                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC14 periph C LCDD16 pin */
+                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* LCDD22 pin */
-                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC13 periph C LCDD17 pin */
+                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD23 pin */
-                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC12 periph C LCDD18 pin */
-                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC11 periph C LCDD19 pin */
-                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC10 periph C LCDD20 pin */
-                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC15 periph C LCDD21 pin */
-                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PE27 periph C LCDD22 pin */
-                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 1b02208ea6ff..026b252f09b3 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * 3 MMC ports
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 02848453ca0c..f7fa58fe09f1 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * 2 TC blocks.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 7a8d4c6115f7..2511d748867b 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
 * UART support
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 4303874889c6..6b1bb58f9c0b 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -64,9 +64,13 @@
                gpio2 = &pioC;
                gpio3 = &pioD;
                gpio4 = &pioE;
+                pwm0 = &pwm0;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
                i2c0 = &i2c0;
+                i2c1 = &i2c1;
                i2c2 = &i2c2;
        };
        cpus {
@@ -310,6 +314,34 @@
                        #size-cells = <1>;
                        ranges;
+                        hlcdc: hlcdc@f0000000 {
+                                compatible = "atmel,sama5d4-hlcdc";
+                                reg = <0xf0000000 0x4000>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+                                clock-names = "periph_clk","sys_clk", "slow_clk";
+                                status = "disabled";
+                                hlcdc-display-controller {
+                                        compatible = "atmel,hlcdc-display-controller";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        port@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                reg = <0>;
+                                        };
+                                };
+                                hlcdc_pwm: hlcdc-pwm {
+                                        compatible = "atmel,hlcdc-pwm";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_lcd_pwm>;
+                                        #pwm-cells = <3>;
+                                };
+                        };
                        dma1: dma-controller@f0004000 {
                                compatible = "atmel,sama5d4-dma";
                                reg = <0xf0004000 0x200>;
@@ -319,6 +351,21 @@
                                clock-names = "dma_clk";
                        };
+                        isi: isi@f0008000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf0008000 0x4000>;
+                                interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi_data_0_7>;
+                                clocks = <&isi_clk>;
+                                clock-names = "isi_clk";
+                                status = "disabled";
+                                port {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                        };
                        ramc0: ramc@f0010000 {
                                compatible = "atmel,sama5d3-ddramc";
                                reg = <0xf0010000 0x200>;
@@ -800,6 +847,33 @@
                                clock-names = "mci_clk";
                        };
+                        ssc0: ssc@f8008000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf8008000 0x4000>;
+                                interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(26))>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(27))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
+                                status = "disabled";
+                        };
+                        pwm0: pwm@f800c000 {
+                                compatible = "atmel,sama5d3-pwm";
+                                reg = <0xf800c000 0x300>;
+                                interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
+                                status = "disabled";
+                        };
                        spi0: spi@f8010000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -839,6 +913,25 @@
                                status = "disabled";
                        };
+                        i2c1: i2c@f8018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8018000 0x4000>;
+                                interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(4)>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(5)>;
+                                dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi1_clk>;
+                                status = "disabled";
+                        };
                        tcb0: timer@f801c000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf801c000 0x100>;
@@ -853,6 +946,8 @@
                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb0_rmii>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                clocks = <&macb0_clk>, <&macb0_clk>;
                                clock-names = "hclk", "pclk";
                                status = "disabled";
@@ -953,6 +1048,24 @@
                                status = "disabled";
                        };
+                        ssc1: ssc@fc014000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xfc014000 0x4000>;
+                                interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                dmas = <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(28))>,
+                                       <&dma1
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+                                        | AT91_XDMAC_DT_PERID(29))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&ssc1_clk>;
+                                clock-names = "pclk";
+                                status = "disabled";
+                        };
                        tcb1: timer@fc020000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xfc020000 0x100>;
@@ -1008,6 +1121,46 @@
                                };
                        };
+                        aes@fc044000 {
+                                compatible = "atmel,at91sam9g46-aes";
+                                reg = <0xfc044000 0x100>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(41)>,
+                                       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(40)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&aes_clk>;
+                                clock-names = "aes_clk";
+                                status = "disabled";
+                        };
+                        tdes@fc04c000 {
+                                compatible = "atmel,at91sam9g46-tdes";
+                                reg = <0xfc04c000 0x100>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(42)>,
+                                       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(43)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&tdes_clk>;
+                                clock-names = "tdes_clk";
+                                status = "disabled";
+                        };
+                        sha@fc050000 {
+                                compatible = "atmel,at91sam9g46-sha";
+                                reg = <0xfc050000 0x100>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
+                                        AT91_XDMAC_DT_PERID(44)>;
+                                dma-names = "tx";
+                                clocks = <&sha_clk>;
+                                clock-names = "sha_clk";
+                                status = "disabled";
+                        };
                        rstc@fc068600 {
                                compatible = "atmel,at91sam9g45-rstc";
                                reg = <0xfc068600 0x10>;
@@ -1064,7 +1217,7 @@
                        };
                        dbgu: serial@fc069000 {
-                                compatible = "atmel,at91sam9260-usart";
+                                compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
                                reg = <0xfc069000 0x200>;
                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
@@ -1190,6 +1343,14 @@
                                        };
                                };
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
+                                                         AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
+                                        };
+                                };
                                i2c2 {
                                        pinctrl_i2c2: i2c2-0 {
                                                atmel,pins =
@@ -1198,6 +1359,155 @@
                                        };
                                };
+                                isi {
+                                        pinctrl_isi_data_0_7: isi-0-data-0-7 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
+                                                         AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
+                                                         AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
+                                                         AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
+                                                         AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
+                                                         AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
+                                                         AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
+                                                         AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
+                                                         AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
+                                        };
+                                        pinctrl_isi_data_8_9: isi-0-data-8-9 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
+                                                         AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
+                                        };
+                                        pinctrl_isi_data_10_11: isi-0-data-10-11 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
+                                                         AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
+                                        };
+                                };
+                                lcd {
+                                        pinctrl_lcd_base: lcd-base-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+                                        };
+                                        pinctrl_lcd_pwm: lcd-pwm-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
+                                        };
+                                        pinctrl_lcd_rgb444: lcd-rgb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
+                                        };
+                                        pinctrl_lcd_rgb565: lcd-rgb-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
+                                        };
+                                        pinctrl_lcd_rgb666: lcd-rgb-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                        pinctrl_lcd_rgb777: lcd-rgb-3 {
+                                                atmel,pins =
+                                                         /* LCDDAT0 conflicts with TMS */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         /* LCDDAT8 conflicts with TCK */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         /* LCDDAT16 conflicts with NTRST */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                        pinctrl_lcd_rgb888: lcd-rgb-4 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+                                        };
+                                };
                                macb0 {
                                        pinctrl_macb0_rmii: macb0_rmii-0 {
                                                atmel,pins =
@@ -1281,6 +1591,38 @@
                                        };
                                };
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
+                                                         AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
+                                                         AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
+                                        };
+                                        pinctrl_ssc0_rx: ssc0_rx {
+                                                atmel,pins =
+                                                        <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
+                                                         AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
+                                                         AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
+                                        };
+                                };
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
+                                                         AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
+                                        };
+                                        pinctrl_ssc1_rx: ssc1_rx {
+                                                atmel,pins =
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
+                                        };
+                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
deleted file mode 100644
index a759a276c9a9..000000000000
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Device Tree Source for the mackerel board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/dts-v1/;
-#include "sh7372.dtsi"
-/ {
-        model = "Mackerel (AP4 EVM 2nd)";
-        compatible = "renesas,mackerel";
-        chosen {
-                bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
-        };
-        memory {
-                device_type = "memory";
-                reg = <0x40000000 0x10000000>;
-        };
-};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
deleted file mode 100644
index f863a10cb1b2..000000000000
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Device Tree Source for the sh7372 SoC
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/include/ "skeleton.dtsi"
-/ {
-        compatible = "renesas,sh7372";
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu@0 {
-                        compatible = "arm,cortex-a8";
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        clock-frequency = <800000000>;
-                };
-        };
-        pfc: pfc@e6050000 {
-                compatible = "renesas,pfc-sh7372";
-                reg = <0xe6050000 0x8000>,
-                      <0xe605801c 0x1c>;
-                gpio-controller;
-                #gpio-cells = <2>;
-        };
-};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
deleted file mode 100644
index 6d32c87632d4..000000000000
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Device Tree Source for the KZM-A9-GT board
- *
- * Copyright (C) 2012 Horms Solutions Ltd.
- *
- * Based on sh73a0-kzm9g.dts
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/dts-v1/;
-#include "sh73a0.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-/ {
-        model = "KZM-A9-GT";
-        compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
-        aliases {
-                serial4 = &scifa4;
-        };
-        cpus {
-                cpu@0 {
-                        cpu0-supply = <&vdd_dvfs>;
-                        operating-points = <
-                                /* kHz  uV */
-                                1196000 1315000
-                                 598000 1175000
-                                 398667 1065000
-                        >;
-                        voltage-tolerance = <1>; /* 1% */
-                };
-        };
-        chosen {
-                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
-                stdout-path = &scifa4;
-        };
-        memory {
-                device_type = "memory";
-                reg = <0x41000000 0x1e800000>;
-        };
-        reg_1p8v: regulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-1.8V";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-        reg_3p3v: regulator@1 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-3.3V";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-        vmmc_sdhi0: regulator@2 {
-                compatible = "regulator-fixed";
-                regulator-name = "SDHI0 Vcc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-        vmmc_sdhi2: regulator@3 {
-                compatible = "regulator-fixed";
-                regulator-name = "SDHI2 Vcc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-        lan9220@10000000 {
-                compatible = "smsc,lan9220", "smsc,lan9115";
-                reg = <0x10000000 0x100>;
-                phy-mode = "mii";
-                interrupt-parent = <&irqpin0>;
-                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-                reg-io-width = <4>;
-                smsc,irq-push-pull;
-                smsc,save-mac-address;
-                vddvario-supply = <&reg_1p8v>;
-                vdd33a-supply = <&reg_3p3v>;
-        };
-        leds {
-                compatible = "gpio-leds";
-                led1 {
-                        gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
-                        label = "LED1";
-                };
-                led2 {
-                        gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
-                        label = "LED2";
-                };
-                led3 {
-                        gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
-                        label = "LED3";
-                };
-                led4 {
-                        gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
-                        label = "LED4";
-                };
-        };
-        keyboard {
-                compatible = "gpio-keys";
-                back-key {
-                        gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_BACK>;
-                        label = "SW3";
-                };
-                right-key {
-                        gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_RIGHT>;
-                        label = "SW2-R";
-                };
-                left-key {
-                        gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_LEFT>;
-                        label = "SW2-L";
-                };
-                enter-key {
-                        gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_ENTER>;
-                        label = "SW2-P";
-                };
-                up-key {
-                        gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_UP>;
-                        label = "SW2-U";
-                };
-                down-key {
-                        gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_DOWN>;
-                        label = "SW2-D";
-                };
-                home-key {
-                        gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_HOME>;
-                        label = "SW1";
-                };
-        };
-        sound {
-                compatible = "simple-audio-card";
-                simple-audio-card,format = "left_j";
-                simple-audio-card,cpu {
-                        sound-dai = <&sh_fsi2 0>;
-                };
-                simple-audio-card,codec {
-                        sound-dai = <&ak4648>;
-                        bitclock-master;
-                        frame-master;
-                        system-clock-frequency = <11289600>;
-                };
-        };
-};
-&cmt1 {
-        status = "okay";
-};
-&extal2_clk {
-        clock-frequency = <48000000>;
-};
-&i2c0 {
-        status = "okay";
-        as3711@40 {
-                compatible = "ams,as3711";
-                reg = <0x40>;
-                regulators {
-                        vdd_dvfs: sd1 {
-                                regulator-name = "1.315V CPU";
-                                regulator-min-microvolt = <1050000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        sd2 {
-                                regulator-name = "1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        sd4 {
-                                regulator-name = "1.215V";
-                                regulator-min-microvolt = <1215000>;
-                                regulator-max-microvolt = <1235000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo2 {
-                                regulator-name = "2.8V CPU";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo3 {
-                                regulator-name = "3.0V CPU";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo4 {
-                                regulator-name = "2.8V";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo5 {
-                                regulator-name = "2.8V #2";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo7 {
-                                regulator-name = "1.15V CPU";
-                                regulator-min-microvolt = <1150000>;
-                                regulator-max-microvolt = <1150000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                        ldo8 {
-                                regulator-name = "1.15V CPU #2";
-                                regulator-min-microvolt = <1150000>;
-                                regulator-max-microvolt = <1150000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-                };
-        };
-        ak4648: ak4648@12 {
-                #sound-dai-cells = <0>;
-                compatible = "asahi-kasei,ak4648";
-                reg = <0x12>;
-        };
-};
-&i2c3 {
-        pinctrl-0 = <&i2c3_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-        pcf8575: gpio@20 {
-                compatible = "nxp,pcf8575";
-                reg = <0x20>;
-                interrupt-parent = <&irqpin2>;
-                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-};
-&mmcif {
-        pinctrl-0 = <&mmcif_pins>;
-        pinctrl-names = "default";
-        bus-width = <8>;
-        vmmc-supply = <&reg_1p8v>;
-        status = "okay";
-};
-&pfc {
-        i2c3_pins: i2c3 {
-                renesas,groups = "i2c3_1";
-                renesas,function = "i2c3";
-        };
-        mmcif_pins: mmc {
-                mux {
-                        renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
-                        renesas,function = "mmc0";
-                };
-                cfg {
-                        renesas,groups = "mmc0_data8_0";
-                        renesas,pins = "PORT279";
-                        bias-pull-up;
-                };
-        };
-        scifa4_pins: serial4 {
-                renesas,groups = "scifa4_data", "scifa4_ctrl";
-                renesas,function = "scifa4";
-        };
-        sdhi0_pins: sd0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
-                renesas,function = "sdhi0";
-        };
-        sdhi2_pins: sd2 {
-                renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
-                renesas,function = "sdhi2";
-        };
-        fsia_pins: sounda {
-                renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
-                                 "fsia_data_in", "fsia_data_out";
-                renesas,function = "fsia";
-        };
-};
-&scifa4 {
-        pinctrl-0 = <&scifa4_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-};
-&sdhi0 {
-        pinctrl-0 = <&sdhi0_pins>;
-        pinctrl-names = "default";
-        vmmc-supply = <&vmmc_sdhi0>;
-        bus-width = <4>;
-        status = "okay";
-};
-&sdhi2 {
-        pinctrl-0 = <&sdhi2_pins>;
-        pinctrl-names = "default";
-        vmmc-supply = <&vmmc_sdhi2>;
-        bus-width = <4>;
-        broken-cd;
-        status = "okay";
-};
-&sh_fsi2 {
-        pinctrl-0 = <&fsia_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 27c5f426d172..022ba505f573 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -1,6 +1,9 @@
 /*
 * Device Tree Source for the KZM-A9-GT board
 *
+ * Copyright (C) 2012 Horms Solutions Ltd.
+ *
+ * Based on sh73a0-kzm9g.dts
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
@@ -10,17 +13,388 @@
 /dts-v1/;
 #include "sh73a0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
        model = "KZM-A9-GT";
        compatible = "renesas,kzm9g", "renesas,sh73a0";
+        aliases {
+                serial4 = &scifa4;
+        };
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd_dvfs>;
+                        operating-points = <
+                                /* kHz  uV */
+                                1196000 1315000
+                                 598000 1175000
+                                 398667 1065000
+                        >;
+                        voltage-tolerance = <1>; /* 1% */
+                };
+        };
        chosen {
-                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw";
+                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
+                stdout-path = &scifa4;
        };
        memory {
                device_type = "memory";
-                reg = <0x41000000 0x1e800000>;
+                reg = <0x40000000 0x20000000>;
+        };
+        reg_1p8v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+        reg_3p3v: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+        vmmc_sdhi0: regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vmmc_sdhi2: regulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI2 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
+                        label = "LED1";
+                };
+                led2 {
+                        gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
+                        label = "LED2";
+                };
+                led3 {
+                        gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
+                        label = "LED3";
+                };
+                led4 {
+                        gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
+                        label = "LED4";
+                };
+        };
+        keyboard {
+                compatible = "gpio-keys";
+                back-key {
+                        gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                        label = "SW3";
+                };
+                right-key {
+                        gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_RIGHT>;
+                        label = "SW2-R";
+                };
+                left-key {
+                        gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_LEFT>;
+                        label = "SW2-L";
+                };
+                enter-key {
+                        gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_ENTER>;
+                        label = "SW2-P";
+                };
+                up-key {
+                        gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_UP>;
+                        label = "SW2-U";
+                };
+                down-key {
+                        gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_DOWN>;
+                        label = "SW2-D";
+                };
+                home-key {
+                        gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                        label = "SW1";
+                };
+        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&ak4648>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <11289600>;
+                };
+        };
+};
+&bsc {
+        ethernet@10000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x10000000 0x100>;
+                phy-mode = "mii";
+                interrupt-parent = <&irqpin0>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                reg-io-width = <4>;
+                smsc,irq-push-pull;
+                smsc,save-mac-address;
+                vddvario-supply = <&reg_1p8v>;
+                vdd33a-supply = <&reg_3p3v>;
+        };
+};
+&cmt1 {
+        status = "okay";
+};
+&extal2_clk {
+        clock-frequency = <48000000>;
+};
+&i2c0 {
+        status = "okay";
+        compass@c {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0c>;
+                interrupt-parent = <&irqpin3>;
+                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+        };
+        ak4648: codec@12 {
+                compatible = "asahi-kasei,ak4648";
+                reg = <0x12>;
+                #sound-dai-cells = <0>;
+        };
+        accelerometer@1d {
+                compatible = "adi,adxl34x";
+                reg = <0x1d>;
+                interrupt-parent = <&irqpin3>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
+                             <3 IRQ_TYPE_LEVEL_HIGH>;
        };
+        rtc@32 {
+                compatible = "ricoh,r2025sd";
+                reg = <0x32>;
+        };
+        as3711@40 {
+                compatible = "ams,as3711";
+                reg = <0x40>;
+                regulators {
+                        vdd_dvfs: sd1 {
+                                regulator-name = "1.315V CPU";
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd2 {
+                                regulator-name = "1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd4 {
+                                regulator-name = "1.215V";
+                                regulator-min-microvolt = <1215000>;
+                                regulator-max-microvolt = <1235000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo2 {
+                                regulator-name = "2.8V CPU";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo3 {
+                                regulator-name = "3.0V CPU";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo4 {
+                                regulator-name = "2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo5 {
+                                regulator-name = "2.8V #2";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo7 {
+                                regulator-name = "1.15V CPU";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo8 {
+                                regulator-name = "1.15V CPU #2";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
+};
+&i2c1 {
+        status = "okay";
+        touchscreen@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+        };
+};
+&i2c3 {
+        pinctrl-0 = <&i2c3_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        pcf8575: gpio@20 {
+                compatible = "nxp,pcf8575";
+                reg = <0x20>;
+                interrupt-parent = <&irqpin2>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+};
+&mmcif {
+        pinctrl-0 = <&mmcif_pins>;
+        pinctrl-names = "default";
+        bus-width = <8>;
+        vmmc-supply = <&reg_1p8v>;
+        status = "okay";
+};
+&pfc {
+        i2c3_pins: i2c3 {
+                renesas,groups = "i2c3_1";
+                renesas,function = "i2c3";
+        };
+        mmcif_pins: mmc {
+                mux {
+                        renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+                        renesas,function = "mmc0";
+                };
+                cfg {
+                        renesas,groups = "mmc0_data8_0";
+                        renesas,pins = "PORT279";
+                        bias-pull-up;
+                };
+        };
+        scifa4_pins: serial4 {
+                renesas,groups = "scifa4_data", "scifa4_ctrl";
+                renesas,function = "scifa4";
+        };
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
+                renesas,function = "sdhi0";
+        };
+        sdhi2_pins: sd2 {
+                renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+                renesas,function = "sdhi2";
+        };
+        fsia_pins: sounda {
+                renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
+                                 "fsia_data_in", "fsia_data_out";
+                renesas,function = "fsia";
+        };
+};
+&scifa4 {
+        pinctrl-0 = <&scifa4_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vmmc_sdhi0>;
+        bus-width = <4>;
+        status = "okay";
+};
+&sdhi2 {
+        pinctrl-0 = <&sdhi2_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vmmc_sdhi2>;
+        bus-width = <4>;
+        broken-cd;
+        status = "okay";
+};
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 2dfd5b44255d..45b539ce4d35 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -11,6 +11,7 @@
 /include/ "skeleton.dtsi"
 #include <dt-bindings/clock/sh73a0-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 / {
@@ -26,15 +27,24 @@
                        compatible = "arm,cortex-a9";
                        reg = <0>;
                        clock-frequency = <1196000000>;
+                        power-domains = <&pd_a2sl>;
                };
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
                        clock-frequency = <1196000000>;
+                        power-domains = <&pd_a2sl>;
                };
        };
+        timer@f0000600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0xf0000600 0x20>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&twd_clk>;
+        };
        gic: interrupt-controller@f0001000 {
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
@@ -49,6 +59,7 @@
                interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
                             <0 38 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "sec", "temp";
+                power-domains = <&pd_a4bc1>;
        };
        sbsc1: memory-controller@fe400000 {
@@ -57,6 +68,7 @@
                interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
                             <0 36 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "sec", "temp";
+                power-domains = <&pd_a4bc0>;
        };
        pmu {
@@ -69,11 +81,12 @@
                compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
                reg = <0xe6138000 0x200>;
                interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
+                clock-names = "fck";
+                power-domains = <&pd_c5>;
                renesas,channels-mask = <0x3f>;
-                clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
-                clock-names = "fck";
                status = "disabled";
        };
@@ -94,6 +107,9 @@
                              0 6 IRQ_TYPE_LEVEL_HIGH
                              0 7 IRQ_TYPE_LEVEL_HIGH
                              0 8 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                power-domains = <&pd_a4s>;
+                control-parent;
        };
        irqpin1: irqpin@e6900004 {
@@ -113,6 +129,8 @@
                              0 14 IRQ_TYPE_LEVEL_HIGH
                              0 15 IRQ_TYPE_LEVEL_HIGH
                              0 16 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                power-domains = <&pd_a4s>;
                control-parent;
        };
@@ -133,6 +151,9 @@
                              0 22 IRQ_TYPE_LEVEL_HIGH
                              0 23 IRQ_TYPE_LEVEL_HIGH
                              0 24 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                power-domains = <&pd_a4s>;
+                control-parent;
        };
        irqpin3: irqpin@e690000c {
@@ -152,6 +173,9 @@
                              0 30 IRQ_TYPE_LEVEL_HIGH
                              0 31 IRQ_TYPE_LEVEL_HIGH
                              0 32 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+                power-domains = <&pd_a4s>;
+                control-parent;
        };
        i2c0: i2c@e6820000 {
@@ -164,6 +188,7 @@
                              0 169 IRQ_TYPE_LEVEL_HIGH
                              0 170 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -177,6 +202,7 @@
                              0 53 IRQ_TYPE_LEVEL_HIGH
                              0 54 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -190,6 +216,7 @@
                              0 173 IRQ_TYPE_LEVEL_HIGH
                              0 174 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -203,6 +230,7 @@
                              0 185 IRQ_TYPE_LEVEL_HIGH
                              0 186 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -216,6 +244,7 @@
                              0 189 IRQ_TYPE_LEVEL_HIGH
                              0 190 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
+                power-domains = <&pd_c5>;
                status = "disabled";
        };
@@ -225,6 +254,7 @@
                interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
                              0 141 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
+                power-domains = <&pd_a3sp>;
                reg-io-width = <4>;
                status = "disabled";
        };
@@ -236,6 +266,7 @@
                              0 84 IRQ_TYPE_LEVEL_HIGH
                              0 85 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
+                power-domains = <&pd_a3sp>;
                cap-sd-highspeed;
                status = "disabled";
        };
@@ -247,6 +278,7 @@
                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
                              0 89 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
+                power-domains = <&pd_a3sp>;
                toshiba,mmc-wrprotect-disable;
                cap-sd-highspeed;
                status = "disabled";
@@ -258,6 +290,7 @@
                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
                              0 105 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
+                power-domains = <&pd_a3sp>;
                toshiba,mmc-wrprotect-disable;
                cap-sd-highspeed;
                status = "disabled";
@@ -269,6 +302,7 @@
                interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -278,6 +312,7 @@
                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -287,6 +322,7 @@
                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -296,6 +332,7 @@
                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -305,6 +342,7 @@
                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -314,6 +352,7 @@
                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -323,6 +362,7 @@
                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -332,6 +372,7 @@
                interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -341,6 +382,7 @@
                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
                clock-names = "sci_ick";
+                power-domains = <&pd_a3sp>;
                status = "disabled";
        };
@@ -359,6 +401,117 @@
                        <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
                        <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
                        <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
+                power-domains = <&pd_c5>;
+        };
+        sysc: system-controller@e6180000 {
+                compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
+                reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
+                pm-domains {
+                        pd_c5: c5 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #power-domain-cells = <0>;
+                                pd_c4: c4@0 {
+                                        reg = <0>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_d4: d4@1 {
+                                        reg = <1>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4bc0: a4bc0@4 {
+                                        reg = <4>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4bc1: a4bc1@5 {
+                                        reg = <5>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4lc0: a4lc0@6 {
+                                        reg = <6>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4lc1: a4lc1@7 {
+                                        reg = <7>;
+                                        #power-domain-cells = <0>;
+                                };
+                                pd_a4mp: a4mp@8 {
+                                        reg = <8>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3mp: a3mp@9 {
+                                                reg = <9>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3vc: a3vc@10 {
+                                                reg = <10>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                };
+                                pd_a4rm: a4rm@12 {
+                                        reg = <12>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3r: a3r@13 {
+                                                reg = <13>;
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #power-domain-cells = <0>;
+                                                pd_a2rv: a2rv@14 {
+                                                        reg = <14>;
+                                                        #address-cells = <1>;
+                                                        #size-cells = <0>;
+                                                        #power-domain-cells = <0>;
+                                                };
+                                        };
+                                };
+                                pd_a4s: a4s@16 {
+                                        reg = <16>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #power-domain-cells = <0>;
+                                        pd_a3sp: a3sp@17 {
+                                                reg = <17>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3sg: a3sg@18 {
+                                                reg = <18>;
+                                                #power-domain-cells = <0>;
+                                        };
+                                        pd_a3sm: a3sm@19 {
+                                                reg = <19>;
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #power-domain-cells = <0>;
+                                                pd_a2sl: a2sl@20 {
+                                                        reg = <20>;
+                                                        #power-domain-cells = <0>;
+                                                };
+                                        };
+                                };
+                        };
+                };
        };
        sh_fsi2: sound@ec230000 {
@@ -366,9 +519,22 @@
                compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
                reg = <0xec230000 0x400>;
                interrupts = <0 146 0x4>;
+                power-domains = <&pd_a4mp>;
                status = "disabled";
        };
+        bsc: bus@fec10000 {
+                compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+                             "simple-pm-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0x20000000>;
+                reg = <0xfec10000 0x400>;
+                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&zb_clk>;
+                power-domains = <&pd_a4s>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -426,133 +592,159 @@
                vclk1_clk: vclk1_clk@e6150008 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150008 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                        #clock-cells = <0>;
                        clock-output-names = "vclk1";
                };
                vclk2_clk: vclk2_clk@e615000c {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe615000c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                        #clock-cells = <0>;
                        clock-output-names = "vclk2";
                };
                vclk3_clk: vclk3_clk@e615001c {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe615001c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
+                                 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
+                                 <0>;
                        #clock-cells = <0>;
                        clock-output-names = "vclk3";
                };
                zb_clk: zb_clk@e6150010 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150010 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "zb";
                };
                flctl_clk: flctl_clk@e6150014 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150014 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "flctlck";
                };
                sdhi0_clk: sdhi0_clk@e6150074 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150074 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "sdhi0ck";
                };
                sdhi1_clk: sdhi1_clk@e6150078 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150078 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "sdhi1ck";
                };
                sdhi2_clk: sdhi2_clk@e615007c {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe615007c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div13_clk>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "sdhi2ck";
                };
                fsia_clk: fsia_clk@e6150018 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150018 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&fsiack_clk>, <&fsiack_clk>;
                        #clock-cells = <0>;
                        clock-output-names = "fsia";
                };
                fsib_clk: fsib_clk@e6150090 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150090 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&fsibck_clk>, <&fsibck_clk>;
                        #clock-cells = <0>;
                        clock-output-names = "fsib";
                };
                sub_clk: sub_clk@e6150080 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150080 4>;
-                        clocks = <&extal2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                        #clock-cells = <0>;
                        clock-output-names = "sub";
                };
                spua_clk: spua_clk@e6150084 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150084 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                        #clock-cells = <0>;
                        clock-output-names = "spua";
                };
                spuv_clk: spuv_clk@e6150094 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150094 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&extal2_clk>, <&extal2_clk>;
                        #clock-cells = <0>;
                        clock-output-names = "spuv";
                };
                msu_clk: msu_clk@e6150088 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150088 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "msu";
                };
                hsi_clk: hsi_clk@e615008c {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe615008c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&pll1_div7_clk>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "hsi";
                };
                mfg1_clk: mfg1_clk@e6150098 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150098 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "mfg1";
                };
                mfg2_clk: mfg2_clk@e615009c {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe615009c 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "mfg2";
                };
                dsit_clk: dsit_clk@e6150060 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150060 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <0>,
+                                 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "dsit";
                };
                dsi0p_clk: dsi0p_clk@e6150064 {
                        compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0xe6150064 4>;
-                        clocks = <&pll1_div2_clk>;
+                        clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
+                                 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
+                                 <&extcki_clk>, <0>, <0>, <0>;
                        #clock-cells = <0>;
                        clock-output-names = "dsi0pck";
                };
@@ -695,5 +887,16 @@
                        clock-output-names =
                                "iic3", "iic4", "keysc";
                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xe6150144 4>, <0xe615003c 4>;
+                        clocks = <&cpg_clocks SH73A0_CLK_HP>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                SH73A0_CLK_INTCA0
+                        >;
+                        clock-output-names =
+                                "intca0";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
new file mode 100644
index 000000000000..2c5cede686dc
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -0,0 +1,2421 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,parent-clock-frequency = <528000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+                                nvidia,parent-clock-frequency = <924000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+        emc@0,7001b000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000e0e
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008cd>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000006
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000005
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x00000006
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000006
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00080000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00008000
+                                        0x00000000
+                                        0x00000000
+                                        0x00008000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000707
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000e000e
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0173000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004d
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004b
+                                        0x0000000e
+                                        0x00000052
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000008
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00050000
+                                        0x00050000
+                                        0x00050000
+                                        0x00050000
+                                        0x00005000
+                                        0x00005000
+                                        0x00005000
+                                        0x00005000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0173000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000011
+                                        0x00000066
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006c
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00038000
+                                        0x00038000
+                                        0x00038000
+                                        0x00038000
+                                        0x00003800
+                                        0x00003800
+                                        0x00003800
+                                        0x00003800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000941>;
+                                nvidia,emc-mrs-wait-cnt = <0x0139000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000018
+                                        0x00000088
+                                        0x00000000
+                                        0x00000010
+                                        0x00000006
+                                        0x00000006
+                                        0x00000009
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000009
+                                        0x00030000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000010
+                                        0x00000012
+                                        0x00000014
+                                        0x00000fd6
+                                        0x00000000
+                                        0x000003f5
+                                        0x00000002
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000000
+                                        0x00000085
+                                        0x00000012
+                                        0x00000090
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000010
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001017
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe01200b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00054000
+                                        0x00054000
+                                        0x00000000
+                                        0x00054000
+                                        0x00054000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x0000000c
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0139000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000042a0
+                                        0x80002062
+                                        0x0000000a
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0127000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000001b
+                                        0x0000009b
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000097
+                                        0x00000015
+                                        0x000000a3
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000013
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001248
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x0000000d
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0127000e
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024aa
+                                        0x0000000e
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200018>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f7000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000024
+                                        0x000000cd
+                                        0x00000000
+                                        0x00000019
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c7
+                                        0x00000018
+                                        0x000000d7
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x00000019
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00700b1
+                                        0x00008000
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x007fc008
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000000
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00514514
+                                        0x00514514
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f7000e
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430303>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200020>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000f15>;
+                                nvidia,emc-mrs-wait-cnt = <0x00cd000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x0000004c>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000002b
+                                        0x000000f0
+                                        0x00000000
+                                        0x0000001e
+                                        0x0000000b
+                                        0x00000009
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000016
+                                        0x0000000b
+                                        0x0000000b
+                                        0x00000004
+                                        0x00000002
+                                        0x00000000
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000d
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000f
+                                        0x000a0000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000016
+                                        0x0000001a
+                                        0x0000001c
+                                        0x00001be7
+                                        0x00000000
+                                        0x000006f9
+                                        0x00000004
+                                        0x00000015
+                                        0x00000001
+                                        0x00000000
+                                        0x000000e7
+                                        0x0000001b
+                                        0x000000fb
+                                        0x00000200
+                                        0x00000006
+                                        0x00000007
+                                        0x00000006
+                                        0x0000001e
+                                        0x00000000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00001c28
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab898
+                                        0xe00400b1
+                                        0x00008000
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x007f800a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000004
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000000
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x5d75d720
+                                        0x00514514
+                                        0x00514514
+                                        0x5d75d700
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000128
+                                        0x00cd000e
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x800037ea
+                                        0x00000011
+                                >;
+                        };
+                };
+        };
+        memory-controller@0,70019000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0502
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0503
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000004
+                                        0x00000002
+                                        0x00000003
+                                        0x00000001
+                                        0x00000003
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0504
+                                        0x73840a05
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000006
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,emem-configuration = <
+                                        0x0f000007
+                                        0x80000040
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000007
+                                        0x00000008
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x06050202
+                                        0x0010090c
+                                        0x7428180d
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000a
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000d
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00170e13
+                                        0x736c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+                                nvidia,emem-configuration = <
+                                        0x0e00000d
+                                        0x80000040
+                                        0x00000005
+                                        0x00000006
+                                        0x00000016
+                                        0x0000000e
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000009
+                                        0x09060202
+                                        0x001a1016
+                                        0x734e2a17
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index dbfaba09703a..ed8a8acd3d34 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -3,6 +3,8 @@
 #include <dt-bindings/input/input.h>
 #include "tegra124.dtsi"
+#include "tegra124-jetson-tk1-emc.dtsi"
 / {
        model = "NVIDIA Tegra124 Jetson TK1";
        compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
@@ -60,35 +62,35 @@
                                nvidia,pins = "clk_32k_out_pa0";
                                nvidia,function = "soc";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        uart3_cts_n_pa1 {
                                nvidia,pins = "uart3_cts_n_pa1";
-                                nvidia,function = "uartc";
+                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap2_fs_pa2 {
                                nvidia,pins = "dap2_fs_pa2";
                                nvidia,function = "i2s1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap2_sclk_pa3 {
                                nvidia,pins = "dap2_sclk_pa3";
                                nvidia,function = "i2s1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap2_din_pa4 {
                                nvidia,pins = "dap2_din_pa4";
                                nvidia,function = "i2s1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        dap2_dout_pa5 {
@@ -96,14 +98,14 @@
                                nvidia,function = "i2s1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc3_clk_pa6 {
                                nvidia,pins = "sdmmc3_clk_pa6";
                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc3_cmd_pa7 {
                                nvidia,pins = "sdmmc3_cmd_pa7";
@@ -116,14 +118,14 @@
                                nvidia,pins = "pb0";
                                nvidia,function = "uartd";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pb1 {
                                nvidia,pins = "pb1";
                                nvidia,function = "uartd";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc3_dat3_pb4 {
@@ -156,9 +158,9 @@
                        };
                        uart3_rts_n_pc0 {
                                nvidia,pins = "uart3_rts_n_pc0";
-                                nvidia,function = "uartc";
+                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        uart2_txd_pc2 {
@@ -172,7 +174,7 @@
                                nvidia,pins = "uart2_rxd_pc3";
                                nvidia,function = "irda";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        gen1_i2c_scl_pc4 {
@@ -194,44 +196,39 @@
                        pc7 {
                                nvidia,pins = "pc7";
                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pg0 {
                                nvidia,pins = "pg0";
-                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pg1 {
                                nvidia,pins = "pg1";
-                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pg2 {
                                nvidia,pins = "pg2";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pg3 {
                                nvidia,pins = "pg3";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pg4 {
                                nvidia,pins = "pg4";
-                                nvidia,function = "spi4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pg5 {
                                nvidia,pins = "pg5";
@@ -251,7 +248,7 @@
                                nvidia,pins = "pg7";
                                nvidia,function = "spi4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        ph0 {
@@ -270,7 +267,6 @@
                        };
                        ph2 {
                                nvidia,pins = "ph2";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -278,57 +274,53 @@
                        ph3 {
                                nvidia,pins = "ph3";
                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ph4 {
                                nvidia,pins = "ph4";
-                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        ph5 {
                                nvidia,pins = "ph5";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ph6 {
                                nvidia,pins = "ph6";
                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ph7 {
                                nvidia,pins = "ph7";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pi0 {
                                nvidia,pins = "pi0";
-                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pi1 {
                                nvidia,pins = "pi1";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pi2 {
                                nvidia,pins = "pi2";
                                nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pi3 {
@@ -341,22 +333,21 @@
                        pi4 {
                                nvidia,pins = "pi4";
                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pi5 {
                                nvidia,pins = "pi5";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pi6 {
                                nvidia,pins = "pi6";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pi7 {
@@ -368,23 +359,22 @@
                        };
                        pj0 {
                                nvidia,pins = "pj0";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pj2 {
                                nvidia,pins = "pj2";
                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        uart2_cts_n_pj5 {
                                nvidia,pins = "uart2_cts_n_pj5";
                                nvidia,function = "uartb";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        uart2_rts_n_pj6 {
@@ -403,35 +393,32 @@
                        };
                        pk0 {
                                nvidia,pins = "pk0";
-                                nvidia,function = "soc";
+                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pk1 {
                                nvidia,pins = "pk1";
-                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pk2 {
                                nvidia,pins = "pk2";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pk3 {
                                nvidia,pins = "pk3";
                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pk4 {
                                nvidia,pins = "pk4";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -439,13 +426,12 @@
                        spdif_out_pk5 {
                                nvidia,pins = "spdif_out_pk5";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        spdif_in_pk6 {
                                nvidia,pins = "spdif_in_pk6";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -459,17 +445,17 @@
                        };
                        dap1_fs_pn0 {
                                nvidia,pins = "dap1_fs_pn0";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap1_din_pn1 {
                                nvidia,pins = "dap1_din_pn1";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap1_dout_pn2 {
                                nvidia,pins = "dap1_dout_pn2";
@@ -480,108 +466,104 @@
                        };
                        dap1_sclk_pn3 {
                                nvidia,pins = "dap1_sclk_pn3";
-                                nvidia,function = "i2s0";
+                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        usb_vbus_en0_pn4 {
                                nvidia,pins = "usb_vbus_en0_pn4";
                                nvidia,function = "usb";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
                        usb_vbus_en1_pn5 {
                                nvidia,pins = "usb_vbus_en1_pn5";
                                nvidia,function = "usb";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
                        hdmi_int_pn7 {
                                nvidia,pins = "hdmi_int_pn7";
-                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data7_po0 {
                                nvidia,pins = "ulpi_data7_po0";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data0_po1 {
                                nvidia,pins = "ulpi_data0_po1";
-                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        ulpi_data1_po2 {
                                nvidia,pins = "ulpi_data1_po2";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data2_po3 {
                                nvidia,pins = "ulpi_data2_po3";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data3_po4 {
                                nvidia,pins = "ulpi_data3_po4";
-                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        ulpi_data4_po5 {
                                nvidia,pins = "ulpi_data4_po5";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data5_po6 {
                                nvidia,pins = "ulpi_data5_po6";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ulpi_data6_po7 {
                                nvidia,pins = "ulpi_data6_po7";
                                nvidia,function = "ulpi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap3_fs_pp0 {
                                nvidia,pins = "dap3_fs_pp0";
                                nvidia,function = "i2s2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap3_din_pp1 {
                                nvidia,pins = "dap3_din_pp1";
                                nvidia,function = "i2s2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap3_dout_pp2 {
                                nvidia,pins = "dap3_dout_pp2";
-                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -595,91 +577,87 @@
                        };
                        dap4_fs_pp4 {
                                nvidia,pins = "dap4_fs_pp4";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap4_din_pp5 {
                                nvidia,pins = "dap4_din_pp5";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd3";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap4_dout_pp6 {
                                nvidia,pins = "dap4_dout_pp6";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap4_sclk_pp7 {
                                nvidia,pins = "dap4_sclk_pp7";
-                                nvidia,function = "i2s3";
+                                nvidia,function = "rsvd3";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_col0_pq0 {
                                nvidia,pins = "kb_col0_pq0";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_col1_pq1 {
                                nvidia,pins = "kb_col1_pq1";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_col2_pq2 {
                                nvidia,pins = "kb_col2_pq2";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_col3_pq3 {
                                nvidia,pins = "kb_col3_pq3";
-                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_col4_pq4 {
                                nvidia,pins = "kb_col4_pq4";
                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_col5_pq5 {
                                nvidia,pins = "kb_col5_pq5";
-                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_col6_pq6 {
                                nvidia,pins = "kb_col6_pq6";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_col7_pq7 {
                                nvidia,pins = "kb_col7_pq7";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row0_pr0 {
                                nvidia,pins = "kb_row0_pr0";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -687,121 +665,115 @@
                        kb_row1_pr1 {
                                nvidia,pins = "kb_row1_pr1";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row2_pr2 {
                                nvidia,pins = "kb_row2_pr2";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row3_pr3 {
                                nvidia,pins = "kb_row3_pr3";
-                                nvidia,function = "sys";
+                                nvidia,function = "kbc";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row4_pr4 {
                                nvidia,pins = "kb_row4_pr4";
-                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_row5_pr5 {
                                nvidia,pins = "kb_row5_pr5";
                                nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row6_pr6 {
                                nvidia,pins = "kb_row6_pr6";
                                nvidia,function = "displaya_alt";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_row7_pr7 {
                                nvidia,pins = "kb_row7_pr7";
-                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_row8_ps0 {
                                nvidia,pins = "kb_row8_ps0";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row9_ps1 {
                                nvidia,pins = "kb_row9_ps1";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "uarta";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row10_ps2 {
                                nvidia,pins = "kb_row10_ps2";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "uarta";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_row11_ps3 {
                                nvidia,pins = "kb_row11_ps3";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row12_ps4 {
                                nvidia,pins = "kb_row12_ps4";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row13_ps5 {
                                nvidia,pins = "kb_row13_ps5";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row14_ps6 {
                                nvidia,pins = "kb_row14_ps6";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row15_ps7 {
                                nvidia,pins = "kb_row15_ps7";
-                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        kb_row16_pt0 {
                                nvidia,pins = "kb_row16_pt0";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        kb_row17_pt1 {
                                nvidia,pins = "kb_row17_pt1";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        gen2_i2c_scl_pt5 {
                                nvidia,pins = "gen2_i2c_scl_pt5";
@@ -828,72 +800,63 @@
                        };
                        pu0 {
                                nvidia,pins = "pu0";
-                                nvidia,function = "rsvd4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu1 {
                                nvidia,pins = "pu1";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu2 {
                                nvidia,pins = "pu2";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu3 {
                                nvidia,pins = "pu3";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu4 {
                                nvidia,pins = "pu4";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu5 {
                                nvidia,pins = "pu5";
-                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pu6 {
                                nvidia,pins = "pu6";
-                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pv0 {
                                nvidia,pins = "pv0";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pv1 {
                                nvidia,pins = "pv1";
-                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc3_cd_n_pv2 {
                                nvidia,pins = "sdmmc3_cd_n_pv2";
                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc1_wp_n_pv3 {
@@ -922,16 +885,16 @@
                        gpio_w2_aud_pw2 {
                                nvidia,pins = "gpio_w2_aud_pw2";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        gpio_w3_aud_pw3 {
                                nvidia,pins = "gpio_w3_aud_pw3";
                                nvidia,function = "spi6";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap_mclk1_pw4 {
                                nvidia,pins = "dap_mclk1_pw4";
@@ -949,17 +912,17 @@
                        };
                        uart3_txd_pw6 {
                                nvidia,pins = "uart3_txd_pw6";
-                                nvidia,function = "uartc";
+                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        uart3_rxd_pw7 {
                                nvidia,pins = "uart3_rxd_pw7";
-                                nvidia,function = "uartc";
+                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dvfs_pwm_px0 {
                                nvidia,pins = "dvfs_pwm_px0";
@@ -970,10 +933,9 @@
                        };
                        gpio_x1_aud_px1 {
                                nvidia,pins = "gpio_x1_aud_px1";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        dvfs_clk_px2 {
                                nvidia,pins = "dvfs_clk_px2";
@@ -985,34 +947,32 @@
                        gpio_x3_aud_px3 {
                                nvidia,pins = "gpio_x3_aud_px3";
                                nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        gpio_x4_aud_px4 {
                                nvidia,pins = "gpio_x4_aud_px4";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        gpio_x5_aud_px5 {
                                nvidia,pins = "gpio_x5_aud_px5";
                                nvidia,function = "rsvd4";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        gpio_x6_aud_px6 {
                                nvidia,pins = "gpio_x6_aud_px6";
                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        gpio_x7_aud_px7 {
                                nvidia,pins = "gpio_x7_aud_px7";
-                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1027,8 +987,8 @@
                        ulpi_dir_py1 {
                                nvidia,pins = "ulpi_dir_py1";
                                nvidia,function = "spi1";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        ulpi_nxt_py2 {
@@ -1048,44 +1008,44 @@
                        sdmmc1_dat3_py4 {
                                nvidia,pins = "sdmmc1_dat3_py4";
                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc1_dat2_py5 {
                                nvidia,pins = "sdmmc1_dat2_py5";
                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc1_dat1_py6 {
                                nvidia,pins = "sdmmc1_dat1_py6";
                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc1_dat0_py7 {
                                nvidia,pins = "sdmmc1_dat0_py7";
-                                nvidia,function = "sdmmc1";
+                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc1_clk_pz0 {
                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
+                                nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc1_cmd_pz1 {
                                nvidia,pins = "sdmmc1_cmd_pz1";
                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pwr_i2c_scl_pz6 {
                                nvidia,pins = "pwr_i2c_scl_pz6";
@@ -1184,7 +1144,6 @@
                        };
                        pbb3 {
                                nvidia,pins = "pbb3";
-                                nvidia,function = "vgp3";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1198,21 +1157,18 @@
                        };
                        pbb5 {
                                nvidia,pins = "pbb5";
-                                nvidia,function = "rsvd3";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pbb6 {
                                nvidia,pins = "pbb6";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pbb7 {
                                nvidia,pins = "pbb7";
-                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1226,15 +1182,13 @@
                        };
                        pcc1 {
                                nvidia,pins = "pcc1";
-                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pcc2 {
                                nvidia,pins = "pcc2";
-                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
@@ -1248,8 +1202,8 @@
                        clk2_req_pcc5 {
                                nvidia,pins = "clk2_req_pcc5";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pex_l0_rst_n_pdd1 {
@@ -1262,15 +1216,15 @@
                        pex_l0_clkreq_n_pdd2 {
                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
                                nvidia,function = "pe0";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pex_wake_n_pdd3 {
                                nvidia,pins = "pex_wake_n_pdd3";
                                nvidia,function = "pe";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pex_l1_rst_n_pdd5 {
@@ -1283,8 +1237,8 @@
                        pex_l1_clkreq_n_pdd6 {
                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
                                nvidia,function = "pe1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        clk3_out_pee0 {
@@ -1297,13 +1251,12 @@
                        clk3_req_pee1 {
                                nvidia,pins = "clk3_req_pee1";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        dap_mclk1_req_pee2 {
                                nvidia,pins = "dap_mclk1_req_pee2";
-                                nvidia,function = "sata";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1314,7 +1267,7 @@
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
                        sdmmc3_clk_lb_out_pee4 {
                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
@@ -1333,24 +1286,24 @@
                        dp_hpd_pff0 {
                                nvidia,pins = "dp_hpd_pff0";
                                nvidia,function = "dp";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        usb_vbus_en2_pff1 {
                                nvidia,pins = "usb_vbus_en2_pff1";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
                        pff2 {
                                nvidia,pins = "pff2";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
                        core_pwr_req {
@@ -1362,7 +1315,7 @@
                        };
                        cpu_pwr_req {
                                nvidia,pins = "cpu_pwr_req";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "cpu";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1371,7 +1324,7 @@
                                nvidia,pins = "pwr_int_n";
                                nvidia,function = "pmi";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        reset_out_n {
@@ -1379,7 +1332,7 @@
                                nvidia,function = "reset_out_n";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        owr {
                                nvidia,pins = "owr";
@@ -1391,9 +1344,9 @@
                        };
                        clk_32k_in {
                                nvidia,pins = "clk_32k_in";
-                                nvidia,function = "rsvd2";
+                                nvidia,function = "clk";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        jtag_rtck {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
new file mode 100644
index 000000000000..1a5748d05dda
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -0,0 +1,2023 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        /* TODO: Add 528MHz frequency */
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+        emc@0,7001b000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
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+                                        0x00004000
+                                        0x00000000
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+                                        0x00004000
+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x0000088d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000007
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x00000006
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000007
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00004000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00094000
+                                        0x00094000
+                                        0x00009400
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000303
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0174000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004c
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004a
+                                        0x0000000e
+                                        0x00000051
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000009
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00098000
+                                        0x00098000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0174000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000012
+                                        0x00000065
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006b
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000d
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00070000
+                                        0x00070000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00048000
+                                        0x00048000
+                                        0x00004800
+                                        0x00004800
+                                        0x00004800
+                                        0x00004800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0128000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000001c
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000096
+                                        0x00000015
+                                        0x000000a2
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000015
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001249
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00048000
+                                        0x00048000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x00000003
+                                        0x00000006
+                                        0x00000005
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x00000003
+                                        0x00000006
+                                        0x00000005
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0128000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024aa
+                                        0x0000000e
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0080089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200418>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f8000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000025
+                                        0x000000cc
+                                        0x00000000
+                                        0x0000001a
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x00000009
+                                        0x00000009
+                                        0x00000003
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c6
+                                        0x00000018
+                                        0x000000d6
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x0000001d
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x80000005
+                                        0x00000000
+                                        0x104ab198
+                                        0xe00700b1
+                                        0x00008000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00034000
+                                        0x00034000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000009
+                                        0x00000009
+                                        0x00000007
+                                        0x00000009
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000009
+                                        0x00000009
+                                        0x00000007
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000101
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00514514
+                                        0x00514514
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f8000c
+                                        0x00000007
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+                };
+        };
+        memory-controller@0,70019000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0403
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000005
+                                        0x00000002
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0405
+                                        0x73840a06
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000005
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000007
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00160d13
+                                        0x734c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 004e8e4e1c04..2d21253ea4e3 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -1,46 +1,29 @@
 /dts-v1/;
-#include <dt-bindings/input/input.h>
+#include "tegra124-nyan.dtsi"
-#include "tegra124.dtsi"
+#include "tegra124-nyan-big-emc.dtsi"
 / {
        model = "Acer Chromebook 13 CB5-311";
        compatible = "google,nyan-big", "nvidia,tegra124";
-        aliases {
+        panel: panel {
-                rtc0 = "/i2c@0,7000d000/pmic@40";
+                compatible = "auo,b133xtn01";
-                rtc1 = "/rtc@0,7000e000";
-                serial0 = &uarta;
-        };
-        memory {
+                backlight = <&backlight>;
-                reg = <0x0 0x80000000 0x0 0x80000000>;
+                ddc-i2c-bus = <&dpaux>;
        };
-        host1x@0,50000000 {
+        sdhci@0,700b0400 { /* SD Card on this bus */
-                hdmi@0,54280000 {
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
-                        status = "okay";
+        };
-                        vdd-supply = <&vdd_3v3_hdmi>;
-                        pll-supply = <&vdd_hdmi_pll>;
-                        hdmi-supply = <&vdd_5v0_hdmi>;
-                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio =
-                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-                };
-                sor@0,54540000 {
-                        status = "okay";
-                        nvidia,dpaux = <&dpaux>;
-                        nvidia,panel = <&panel>;
-                };
-                dpaux@0,545c0000 {
+        sound {
-                        vdd-supply = <&vdd_3v3_panel>;
+                compatible = "nvidia,tegra-audio-max98090-nyan-big",
-                        status = "okay";
+                             "nvidia,tegra-audio-max98090-nyan",
-                };
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "GoogleNyanBig";
        };
        pinmux@0,70000868 {
@@ -48,1092 +31,1308 @@
                pinctrl-0 = <&pinmux_default>;
                pinmux_default: common {
-                        dap_mclk1_pw4 {
+                        clk_32k_out_pa0 {
-                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,pins = "clk_32k_out_pa0";
-                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        dap2_din_pa4 {
                                nvidia,pins = "dap2_din_pa4";
                                nvidia,function = "i2s1";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        dap2_dout_pa5 {
-                                nvidia,pins = "dap2_dout_pa5",
+                                nvidia,pins = "dap2_dout_pa5";
-                                              "dap2_fs_pa2",
-                                              "dap2_sclk_pa3";
                                nvidia,function = "i2s1";
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        dvfs_pwm_px0 {
+                        sdmmc3_clk_pa6 {
-                                nvidia,pins = "dvfs_pwm_px0",
+                                nvidia,pins = "sdmmc3_clk_pa6";
-                                              "dvfs_clk_px2";
+                                nvidia,function = "sdmmc3";
-                                nvidia,function = "cldvfs";
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        ulpi_clk_py0 {
+                        sdmmc3_cmd_pa7 {
-                                nvidia,pins = "ulpi_clk_py0",
+                                nvidia,pins = "sdmmc3_cmd_pa7";
-                                              "ulpi_nxt_py2",
+                                nvidia,function = "sdmmc3";
-                                              "ulpi_stp_py3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                nvidia,function = "spi1";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb1 {
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        ulpi_dir_py1 {
+                        gen1_i2c_sda_pc5 {
-                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,pins = "gen1_i2c_sda_pc5";
-                                nvidia,function = "spi1";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pc7 {
+                                nvidia,pins = "pc7";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        cam_i2c_scl_pbb1 {
+                        pg0 {
-                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                nvidia,pins = "pg0";
-                                              "cam_i2c_sda_pbb2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,function = "i2c3";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg1 {
+                                nvidia,pins = "pg1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        gen2_i2c_scl_pt5 {
+                        pg2 {
-                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                nvidia,pins = "pg2";
-                                              "gen2_i2c_sda_pt6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,function = "i2c2";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg3 {
+                                nvidia,pins = "pg3";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
                        pg4 {
-                                nvidia,pins = "pg4",
+                                nvidia,pins = "pg4";
-                                              "pg5",
+                                nvidia,function = "spi4";
-                                              "pg6",
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                              "pi3";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg5 {
+                                nvidia,pins = "pg5";
                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        pg7 {
                                nvidia,pins = "pg7";
                                nvidia,function = "spi4";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ph1 {
                                nvidia,pins = "ph1";
                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        pk0 {
+                        ph3 {
-                                nvidia,pins = "pk0",
+                                nvidia,pins = "ph3";
-                                              "kb_row15_ps7",
+                                nvidia,function = "gmi";
-                                              "clk_32k_out_pa0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,function = "soc";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 {
+                                nvidia,pins = "ph4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sdmmc1_clk_pz0 {
+                        ph5 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,pins = "ph5";
-                                nvidia,function = "sdmmc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 {
+                                nvidia,pins = "ph6";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sdmmc1_cmd_pz1 {
+                        ph7 {
-                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                nvidia,pins = "ph7";
-                                              "sdmmc1_dat0_py7",
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                              "sdmmc1_dat1_py6",
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                              "sdmmc1_dat2_py5",
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                              "sdmmc1_dat3_py4";
+                        };
-                                nvidia,function = "sdmmc1";
+                        pi0 {
+                                nvidia,pins = "pi0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi1 {
+                                nvidia,pins = "pi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi2 {
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 {
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi5 {
+                                nvidia,pins = "pi5";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        sdmmc3_clk_pa6 {
+                        pi6 {
-                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,pins = "pi6";
-                                nvidia,function = "sdmmc3";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sdmmc3_cmd_pa7 {
+                        pi7 {
-                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                nvidia,pins = "pi7";
-                                              "sdmmc3_dat0_pb7",
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                              "sdmmc3_dat1_pb6",
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                              "sdmmc3_dat2_pb5",
-                                              "sdmmc3_dat3_pb4",
-                                              "kb_col4_pq4",
-                                              "sdmmc3_clk_lb_out_pee4",
-                                              "sdmmc3_clk_lb_in_pee5",
-                                              "sdmmc3_cd_n_pv2";
-                                nvidia,function = "sdmmc3";
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj0 {
+                                nvidia,pins = "pj0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sdmmc4_clk_pcc4 {
+                        pj2 {
-                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,pins = "pj2";
-                                nvidia,function = "sdmmc4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 {
+                                nvidia,pins = "pk1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        sdmmc4_cmd_pt7 {
+                        pk2 {
-                                nvidia,pins = "sdmmc4_cmd_pt7",
+                                nvidia,pins = "pk2";
-                                              "sdmmc4_dat0_paa0",
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                              "sdmmc4_dat1_paa1",
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                              "sdmmc4_dat2_paa2",
-                                              "sdmmc4_dat3_paa3",
-                                              "sdmmc4_dat4_paa4",
-                                              "sdmmc4_dat5_paa5",
-                                              "sdmmc4_dat6_paa6",
-                                              "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk3 {
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 {
+                                nvidia,pins = "pk4";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        pwr_i2c_scl_pz6 {
+                        spdif_out_pk5 {
-                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                nvidia,pins = "spdif_out_pk5";
-                                              "pwr_i2c_sda_pz7";
+                                nvidia,function = "rsvd2";
-                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk7 {
+                                nvidia,pins = "pk7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        jtag_rtck {
+                        usb_vbus_en1_pn5 {
-                                nvidia,pins = "jtag_rtck";
+                                nvidia,pins = "usb_vbus_en1_pn5";
-                                nvidia,function = "rtck";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        clk_32k_in {
+                        kb_col5_pq5 {
-                                nvidia,pins = "clk_32k_in";
+                                nvidia,pins = "kb_col5_pq5";
-                                nvidia,function = "clk";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        core_pwr_req {
+                        kb_row0_pr0 {
-                                nvidia,pins = "core_pwr_req";
+                                nvidia,pins = "kb_row0_pr0";
-                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        cpu_pwr_req {
+                        kb_row2_pr2 {
-                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,pins = "kb_row2_pr2";
-                                nvidia,function = "cpu";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        pwr_int_n {
+                        kb_row5_pr5 {
-                                nvidia,pins = "pwr_int_n";
+                                nvidia,pins = "kb_row5_pr5";
-                                nvidia,function = "pmi";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        reset_out_n {
+                        kb_row10_ps2 {
-                                nvidia,pins = "reset_out_n";
+                                nvidia,pins = "kb_row10_ps2";
-                                nvidia,function = "reset_out_n";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        clk3_out_pee0 {
+                        kb_row13_ps5 {
-                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,pins = "kb_row13_ps5";
-                                nvidia,function = "extperiph3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        gen1_i2c_sda_pc5 {
+                        kb_row16_pt0 {
-                                nvidia,pins = "gen1_i2c_sda_pc5",
+                                nvidia,pins = "kb_row16_pt0";
-                                              "gen1_i2c_scl_pc4";
+                                nvidia,function = "rsvd2";
-                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 {
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        hdmi_cec_pee3 {
+                        gen2_i2c_sda_pt6 {
-                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,pins = "gen2_i2c_sda_pt6";
-                                nvidia,function = "cec";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                        };
-                        hdmi_int_pn7 {
+                        pu0 {
-                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 {
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
                        ddc_scl_pv4 {
-                                nvidia,pins = "ddc_scl_pv4",
+                                nvidia,pins = "ddc_scl_pv4";
-                                              "ddc_sda_pv5";
                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
                        };
-                        kb_row10_ps2 {
+                        gpio_w2_aud_pw2 {
-                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,pins = "gpio_w2_aud_pw2";
-                                nvidia,function = "uarta";
+                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        kb_row9_ps1 {
+                        dap_mclk1_pw4 {
-                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,pins = "dap_mclk1_pw4";
-                                nvidia,function = "uarta";
+                                nvidia,function = "extperiph1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        usb_vbus_en0_pn4 {
+                        clk2_out_pw5 {
-                                nvidia,pins = "usb_vbus_en0_pn4",
+                                nvidia,pins = "clk2_out_pw5";
-                                              "usb_vbus_en1_pn5";
+                                nvidia,function = "rsvd2";
-                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        drive_sdio1 {
+                        gpio_x3_aud_px3 {
-                                nvidia,pins = "drive_sdio1";
+                                nvidia,pins = "gpio_x3_aud_px3";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "rsvd4";
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,pull-down-strength = <36>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull-up-strength = <20>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                        };
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                        gpio_x4_aud_px4 {
-                        };
+                                nvidia,pins = "gpio_x4_aud_px4";
-                        drive_sdio3 {
-                                nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,pull-down-strength = <22>;
-                                nvidia,pull-up-strength = <36>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                        };
-                        drive_gma {
-                                nvidia,pins = "drive_gma";
-                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
-                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,pull-down-strength = <2>;
-                                nvidia,pull-up-strength = <1>;
-                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,drive-type = <1>;
-                        };
-                        codec_irq_l {
-                                nvidia,pins = "ph4";
-                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        lcd_bl_en {
+                        gpio_x5_aud_px5 {
-                                nvidia,pins = "ph2";
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
                                nvidia,function = "gmi";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        touch_irq_l {
+                        ulpi_clk_py0 {
-                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,pins = "ulpi_clk_py0";
-                                nvidia,function = "spi6";
+                                nvidia,function = "spi1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        tpm_davint_l {
+                        ulpi_dir_py1 {
-                                nvidia,pins = "ph6";
+                                nvidia,pins = "ulpi_dir_py1";
-                                nvidia,function = "gmi";
+                                nvidia,function = "spi1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        ts_irq_l {
+                        ulpi_nxt_py2 {
-                                nvidia,pins = "pk2";
+                                nvidia,pins = "ulpi_nxt_py2";
-                                nvidia,function = "gmi";
+                                nvidia,function = "spi1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        ts_reset_l {
+                        ulpi_stp_py3 {
-                                nvidia,pins = "pk4";
+                                nvidia,pins = "ulpi_stp_py3";
-                                nvidia,function = "gmi";
+                                nvidia,function = "spi1";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        ts_shdn_l {
+                        sdmmc1_dat3_py4 {
-                                nvidia,pins = "pk1";
+                                nvidia,pins = "sdmmc1_dat3_py4";
-                                nvidia,function = "gmi";
+                                nvidia,function = "sdmmc1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        ph7 {
+                        sdmmc1_dat2_py5 {
-                                nvidia,pins = "ph7";
+                                nvidia,pins = "sdmmc1_dat2_py5";
-                                nvidia,function = "gmi";
+                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        kb_col0_ap {
+                        sdmmc1_dat1_py6 {
-                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,pins = "sdmmc1_dat1_py6";
-                                nvidia,function = "rsvd4";
+                                nvidia,function = "sdmmc1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        lid_open {
+                        sdmmc1_dat0_py7 {
-                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,pins = "sdmmc1_dat0_py7";
-                                nvidia,function = "rsvd3";
+                                nvidia,function = "sdmmc1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        en_vdd_sd {
+                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "rsvd4";
+                                nvidia,function = "sdmmc1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        ac_ok {
+                        sdmmc1_cmd_pz1 {
-                                nvidia,pins = "pj0";
+                                nvidia,pins = "sdmmc1_cmd_pz1";
-                                nvidia,function = "gmi";
+                                nvidia,function = "sdmmc1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sensor_irq_l {
+                        pwr_i2c_scl_pz6 {
-                                nvidia,pins = "pi6";
+                                nvidia,pins = "pwr_i2c_scl_pz6";
-                                nvidia,function = "gmi";
+                                nvidia,function = "i2cpwr";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
-                        wifi_en {
+                        pwr_i2c_sda_pz7 {
-                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,pins = "pwr_i2c_sda_pz7";
-                                nvidia,function = "rsvd4";
+                                nvidia,function = "i2cpwr";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        en_vdd_bl {
+                        cam_i2c_scl_pbb1 {
-                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,pins = "cam_i2c_scl_pbb1";
-                                nvidia,function = "i2s2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        en_vdd_hdmi {
+                        pex_l0_rst_n_pdd1 {
-                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
-                                nvidia,function = "spdif";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 {
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_out_pee4 {
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        soc_warm_reset_l {
+                        sdmmc3_clk_lb_in_pee5 {
-                                nvidia,pins = "pi5";
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
-                                nvidia,function = "gmi";
+                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        hp_det_l {
+                        dp_hpd_pff0 {
-                                nvidia,pins = "pi7";
+                                nvidia,pins = "dp_hpd_pff0";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "dp";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        mic_det_l {
+                        usb_vbus_en2_pff1 {
-                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,pins = "usb_vbus_en2_pff1";
                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                };
+                        reset_out_n {
-        };
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
-        serial@0,70006000 {
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                /* Debug connector on the bottom of the board near SD card. */
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                status = "okay";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-        };
-        pwm@0,7000a000 {
-                status = "okay";
-        };
-        i2c@0,7000c000 {
-                status = "okay";
-                clock-frequency = <100000>;
-                acodec: audio-codec@10 {
-                        compatible = "maxim,max98090";
-                        reg = <0x10>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
-                };
-                temperature-sensor@4c {
-                        compatible = "ti,tmp451";
-                        reg = <0x4c>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
-                        #thermal-sensor-cells = <1>;
-                };
-        };
-        i2c@0,7000c400 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-        i2c@0,7000c500 {
-                status = "okay";
-                clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
-                };
-        };
-        hdmi_ddc: i2c@0,7000c700 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-        i2c@0,7000d000 {
-                status = "okay";
-                clock-frequency = <400000>;
-                pmic: pmic@40 {
-                        compatible = "ams,as3722";
-                        reg = <0x40>;
-                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                        ams,system-power-controller;
-                        #interrupt-cells = <2>;
-                        interrupt-controller;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&as3722_default>;
-                        as3722_default: pinmux {
-                                gpio0 {
-                                        pins = "gpio0";
-                                        function = "gpio";
-                                        bias-pull-down;
-                                };
-                                gpio1 {
-                                        pins = "gpio1";
-                                        function = "gpio";
-                                        bias-pull-up;
-                                };
-                                gpio2_4_7 {
-                                        pins = "gpio2", "gpio4", "gpio7";
-                                        function = "gpio";
-                                        bias-pull-up;
-                                };
-                                gpio3_6 {
-                                        pins = "gpio3", "gpio6";
-                                        bias-high-impedance;
-                                };
-                                gpio5 {
-                                        pins = "gpio5";
-                                        function = "clk32k-out";
-                                        bias-pull-down;
-                                };
                        };
+                        owr {
-                        regulators {
+                                nvidia,pins = "owr";
-                                vsup-sd2-supply = <&vdd_5v0_sys>;
+                                nvidia,function = "rsvd2";
-                                vsup-sd3-supply = <&vdd_5v0_sys>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                vsup-sd4-supply = <&vdd_5v0_sys>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                vsup-sd5-supply = <&vdd_5v0_sys>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                vin-ldo0-supply = <&vdd_1v35_lp0>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
-                                vin-ldo1-6-supply = <&vdd_3v3_run>;
-                                vin-ldo2-5-7-supply = <&vddio_1v8>;
-                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
-                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
-                                vin-ldo11-supply = <&vdd_3v3_run>;
-                                sd0 {
-                                        regulator-name = "+VDD_CPU_AP";
-                                        regulator-min-microvolt = <700000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-min-microamp = <3500000>;
-                                        regulator-max-microamp = <3500000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        ams,ext-control = <2>;
-                                };
-                                sd1 {
-                                        regulator-name = "+VDD_CORE";
-                                        regulator-min-microvolt = <700000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-min-microamp = <2500000>;
-                                        regulator-max-microamp = <4000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        ams,ext-control = <1>;
-                                };
-                                vdd_1v35_lp0: sd2 {
-                                        regulator-name = "+1.35V_LP0(sd2)";
-                                        regulator-min-microvolt = <1350000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                sd3 {
-                                        regulator-name = "+1.35V_LP0(sd3)";
-                                        regulator-min-microvolt = <1350000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                vdd_1v05_run: sd4 {
-                                        regulator-name = "+1.05V_RUN";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                };
-                                vddio_1v8: sd5 {
-                                        regulator-name = "+1.8V_VDDIO";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-                                sd6 {
-                                        regulator-name = "+VDD_GPU_AP";
-                                        regulator-min-microvolt = <650000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-min-microamp = <3500000>;
-                                        regulator-max-microamp = <3500000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-                                ldo0 {
-                                        regulator-name = "+1.05V_RUN_AVDD";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                        ams,ext-control = <1>;
-                                };
-                                ldo1 {
-                                        regulator-name = "+1.8V_RUN_CAM";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo2 {
-                                        regulator-name = "+1.2V_GEN_AVDD";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                };
-                                ldo3 {
-                                        regulator-name = "+1.00V_LP0_VDD_RTC";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
-                                        ams,enable-tracking;
-                                };
-                                vdd_run_cam: ldo4 {
-                                        regulator-name = "+3.3V_RUN_CAM";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-                                ldo5 {
-                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                };
-                                vddio_sdmmc3: ldo6 {
-                                        regulator-name = "+VDDIO_SDMMC3";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <3300000>;
-                                };
-                                ldo7 {
-                                        regulator-name = "+1.05V_RUN_CAM_REAR";
-                                        regulator-min-microvolt = <1050000>;
-                                        regulator-max-microvolt = <1050000>;
-                                };
-                                ldo9 {
-                                        regulator-name = "+2.8V_RUN_TOUCH";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-                                ldo10 {
-                                        regulator-name = "+2.8V_RUN_CAM_AF";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-                                ldo11 {
-                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
                        };
-                };
+                        clk_32k_in {
-        };
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
-        spi@0,7000d400 {
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                status = "okay";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                cros_ec: cros-ec@0 {
+                        };
-                        compatible = "google,cros-ec-spi";
+                        jtag_rtck {
-                        spi-max-frequency = <3000000>;
+                                nvidia,pins = "jtag_rtck";
-                        interrupt-parent = <&gpio>;
+                                nvidia,function = "rtck";
-                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                        reg = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                        google,cros-ec-spi-msg-delay = <2000>;
-                        i2c-tunnel {
-                                compatible = "google,cros-ec-i2c-tunnel";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                google,remote-bus = <0>;
-                                charger: bq24735@9 {
-                                        compatible = "ti,bq24735";
-                                        reg = <0x9>;
-                                        interrupt-parent = <&gpio>;
-                                        interrupts = <TEGRA_GPIO(J, 0)
-                                                        GPIO_ACTIVE_HIGH>;
-                                        ti,ac-detect-gpios = <&gpio
-                                                        TEGRA_GPIO(J, 0)
-                                                        GPIO_ACTIVE_HIGH>;
-                                };
-                                battery: sbs-battery@b {
-                                        compatible = "sbs,sbs-battery";
-                                        reg = <0xb>;
-                                        sbs,i2c-retry-count = <2>;
-                                        sbs,poll-retry-count = <10>;
-                                        power-supplies = <&charger>;
-                                };
                        };
                };
        };
-        spi@0,7000da00 {
-                status = "okay";
-                spi-max-frequency = <25000000>;
-                flash@0 {
-                        compatible = "winbond,w25q32dw";
-                        reg = <0>;
-                };
-        };
-        pmc@0,7000e400 {
-                nvidia,invert-interrupt;
-                nvidia,suspend-mode = <0>;
-                nvidia,cpu-pwr-good-time = <500>;
-                nvidia,cpu-pwr-off-time = <300>;
-                nvidia,core-pwr-good-time = <641 3845>;
-                nvidia,core-pwr-off-time = <61036>;
-                nvidia,core-power-req-active-high;
-                nvidia,sys-clock-req-active-high;
-        };
-        hda@0,70030000 {
-                status = "okay";
-        };
-        sdhci@0,700b0000 { /* WiFi/BT on this bus */
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                no-1-8-v;
-                non-removable;
-        };
-        sdhci@0,700b0400 { /* SD Card on this bus */
-                status = "okay";
-                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
-                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
-                no-1-8-v;
-                vqmmc-supply = <&vddio_sdmmc3>;
-        };
-        sdhci@0,700b0600 { /* eMMC on this bus */
-                status = "okay";
-                bus-width = <8>;
-                no-1-8-v;
-                non-removable;
-        };
-        ahub@0,70300000 {
-                i2s@0,70301100 {
-                        status = "okay";
-                };
-        };
-        usb@0,7d000000 { /* Rear external USB port. */
-                status = "okay";
-        };
-        usb-phy@0,7d000000 {
-                status = "okay";
-                vbus-supply = <&vdd_usb1_vbus>;
-        };
-        usb@0,7d004000 { /* Internal webcam. */
-                status = "okay";
-        };
-        usb-phy@0,7d004000 {
-                status = "okay";
-                vbus-supply = <&vdd_run_cam>;
-        };
-        usb@0,7d008000 { /* Left external USB port. */
-                status = "okay";
-        };
-        usb-phy@0,7d008000 {
-                status = "okay";
-                vbus-supply = <&vdd_usb3_vbus>;
-        };
-        backlight: backlight {
-                compatible = "pwm-backlight";
-                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
-                power-supply = <&vdd_led>;
-                pwms = <&pwm 1 1000000>;
-                default-brightness-level = <224>;
-                brightness-levels =
-                        <  0   1   2   3   4   5   6   7
-                           8   9  10  11  12  13  14  15
-                          16  17  18  19  20  21  22  23
-                          24  25  26  27  28  29  30  31
-                          32  33  34  35  36  37  38  39
-                          40  41  42  43  44  45  46  47
-                          48  49  50  51  52  53  54  55
-                          56  57  58  59  60  61  62  63
-                          64  65  66  67  68  69  70  71
-                          72  73  74  75  76  77  78  79
-                          80  81  82  83  84  85  86  87
-                          88  89  90  91  92  93  94  95
-                          96  97  98  99 100 101 102 103
-                         104 105 106 107 108 109 110 111
-                         112 113 114 115 116 117 118 119
-                         120 121 122 123 124 125 126 127
-                         128 129 130 131 132 133 134 135
-                         136 137 138 139 140 141 142 143
-                         144 145 146 147 148 149 150 151
-                         152 153 154 155 156 157 158 159
-                         160 161 162 163 164 165 166 167
-                         168 169 170 171 172 173 174 175
-                         176 177 178 179 180 181 182 183
-                         184 185 186 187 188 189 190 191
-                         192 193 194 195 196 197 198 199
-                         200 201 202 203 204 205 206 207
-                         208 209 210 211 212 213 214 215
-                         216 217 218 219 220 221 222 223
-                         224 225 226 227 228 229 230 231
-                         232 233 234 235 236 237 238 239
-                         240 241 242 243 244 245 246 247
-                         248 249 250 251 252 253 254 255
-                         256>;
-        };
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clk32k_in: clock@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
-        };
-        gpio-keys {
-                compatible = "gpio-keys";
-                lid {
-                        label = "Lid";
-                        gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
-                        linux,input-type = <5>;
-                        linux,code = <KEY_RESERVED>;
-                        debounce-interval = <1>;
-                        gpio-key,wakeup;
-                };
-                power {
-                        label = "Power";
-                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
-                        debounce-interval = <30>;
-                        gpio-key,wakeup;
-                };
-        };
-        panel: panel {
-                compatible = "auo,b133xtn01";
-                backlight = <&backlight>;
-                ddc-i2c-bus = <&dpaux>;
-        };
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                vdd_mux: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        regulator-name = "+VDD_MUX";
-                        regulator-min-microvolt = <12000000>;
-                        regulator-max-microvolt = <12000000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                };
-                vdd_5v0_sys: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "+5V_SYS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        vin-supply = <&vdd_mux>;
-                };
-                vdd_3v3_sys: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "+3.3V_SYS";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        vin-supply = <&vdd_mux>;
-                };
-                vdd_3v3_run: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "+3.3V_RUN";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_sys>;
-                };
-                vdd_3v3_hdmi: regulator@4 {
-                        compatible = "regulator-fixed";
-                        reg = <4>;
-                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        vin-supply = <&vdd_3v3_run>;
-                };
-                vdd_led: regulator@5 {
-                        compatible = "regulator-fixed";
-                        reg = <5>;
-                        regulator-name = "+VDD_LED";
-                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_mux>;
-                };
-                vdd_5v0_ts: regulator@6 {
-                        compatible = "regulator-fixed";
-                        reg = <6>;
-                        regulator-name = "+5V_VDD_TS_SW";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-boot-on;
-                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-                vdd_usb1_vbus: regulator@7 {
-                        compatible = "regulator-fixed";
-                        reg = <7>;
-                        regulator-name = "+5V_USB_HS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        gpio-open-drain;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-                vdd_usb3_vbus: regulator@8 {
-                        compatible = "regulator-fixed";
-                        reg = <8>;
-                        regulator-name = "+5V_USB_SS";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        gpio-open-drain;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-                vdd_3v3_panel: regulator@9 {
-                        compatible = "regulator-fixed";
-                        reg = <9>;
-                        regulator-name = "+3.3V_PANEL";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_run>;
-                };
-                vdd_3v3_lp0: regulator@10 {
-                        compatible = "regulator-fixed";
-                        reg = <10>;
-                        regulator-name = "+3.3V_LP0";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        /*
-                         * TODO: find a way to wire this up with the USB EHCI
-                         * controllers so that it can be enabled on demand.
-                         */
-                        regulator-always-on;
-                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_3v3_sys>;
-                };
-                vdd_hdmi_pll: regulator@11 {
-                        compatible = "regulator-fixed";
-                        reg = <11>;
-                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
-                        regulator-min-microvolt = <1050000>;
-                        regulator-max-microvolt = <1050000>;
-                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
-                        vin-supply = <&vdd_1v05_run>;
-                };
-                vdd_5v0_hdmi: regulator@12 {
-                        compatible = "regulator-fixed";
-                        reg = <12>;
-                        regulator-name = "+5V_HDMI_CON";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&vdd_5v0_sys>;
-                };
-        };
-        sound {
-                compatible = "nvidia,tegra-audio-max98090-nyan-big",
-                             "nvidia,tegra-audio-max98090";
-                nvidia,model = "Acer Chromebook 13";
-                nvidia,audio-routing =
-                        "Headphones", "HPR",
-                        "Headphones", "HPL",
-                        "Speakers", "SPKR",
-                        "Speakers", "SPKL",
-                        "Mic Jack", "MICBIAS",
-                        "DMICL", "Int Mic",
-                        "DMICR", "Int Mic",
-                        "IN34", "Mic Jack";
-                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,audio-codec = <&acodec>;
-                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
-                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                         <&tegra_car TEGRA124_CLK_EXTERN1>;
-                clock-names = "pll_a", "pll_a_out0", "mclk";
-                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
-                nvidia,mic-det-gpios =
-                                <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
-        };
 };
-#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
new file mode 100644
index 000000000000..9ecd108f56cf
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -0,0 +1,2049 @@
+/ {
+        clock@0,60006000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        /* TODO: Add 528MHz frequency */
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+        emc@0,7001b000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000060
+                                        0x00000000
+                                        0x00000018
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000005
+                                        0x00000005
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000064
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000007
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000000
+                                        0x00000005
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000026
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000007
+                                        0x0000000f
+                                        0x00000006
+                                        0x00000006
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x000000a0
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000001
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000001
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000134
+                                        0x00000000
+                                        0x0000004d
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000008
+                                        0x0000000f
+                                        0x0000000c
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000013f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000015
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000370
+                                        0x0000000a
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000003
+                                        0x00000011
+                                        0x00000000
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000202
+                                        0x00000000
+                                        0x00000080
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x0000000f
+                                        0x0000000f
+                                        0x00000013
+                                        0x00000013
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000001
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000213
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000022
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+                                nvidia,emc-configuration = <
+                                        0x00000004
+                                        0x0000001a
+                                        0x00000000
+                                        0x00000003
+                                        0x00000001
+                                        0x00000004
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x0000000c
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000304
+                                        0x00000000
+                                        0x000000c1
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000018
+                                        0x0000000f
+                                        0x0000001c
+                                        0x0000001c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000031c
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x000fc000
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x0000fc00
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000033
+                                        0x00000000
+                                        0x00000042
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000f2f3
+                                        0x80000713
+                                        0x0000000a
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x0000088d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000009
+                                        0x00000035
+                                        0x00000000
+                                        0x00000007
+                                        0x00000002
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000003
+                                        0x00000003
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000006
+                                        0x00000002
+                                        0x00000000
+                                        0x00000004
+                                        0x00000006
+                                        0x00010000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000d
+                                        0x0000000f
+                                        0x00000011
+                                        0x00000607
+                                        0x00000000
+                                        0x00000181
+                                        0x00000002
+                                        0x00000002
+                                        0x00000001
+                                        0x00000000
+                                        0x00000032
+                                        0x0000000f
+                                        0x00000038
+                                        0x00000038
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000007
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000638
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x106aa298
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00064000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000c000
+                                        0x00000000
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+                                        0x0000c000
+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00090000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x00009000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000505
+                                        0x81f1f108
+                                        0x07070004
+                                        0x0000003f
+                                        0x016eeeee
+                                        0x51451400
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000066
+                                        0x00000000
+                                        0x00000100
+                                        0x000c000c
+                                        0x00000000
+                                        0x00000003
+                                        0x0000d2b3
+                                        0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0174000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000000d
+                                        0x0000004c
+                                        0x00000000
+                                        0x00000009
+                                        0x00000003
+                                        0x00000004
+                                        0x00000008
+                                        0x00000002
+                                        0x00000009
+                                        0x00000003
+                                        0x00000003
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000007
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x0000000e
+                                        0x00000010
+                                        0x00000012
+                                        0x000008e4
+                                        0x00000000
+                                        0x00000239
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x0000004a
+                                        0x0000000e
+                                        0x00000051
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000009
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000924
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00000000
+                                        0x00090000
+                                        0x00090000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
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+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00060000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x00006000
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x00000096
+                                        0x00000000
+                                        0x00000100
+                                        0x0174000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x800012d7
+                                        0x00000009
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000012
+                                        0x00000065
+                                        0x00000000
+                                        0x0000000c
+                                        0x00000004
+                                        0x00000005
+                                        0x00000008
+                                        0x00000002
+                                        0x0000000a
+                                        0x00000004
+                                        0x00000004
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x00000003
+                                        0x00000005
+                                        0x00000002
+                                        0x00000000
+                                        0x00000001
+                                        0x00000008
+                                        0x00020000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0000000f
+                                        0x00000010
+                                        0x00000012
+                                        0x00000bd1
+                                        0x00000000
+                                        0x000002f4
+                                        0x00000001
+                                        0x00000008
+                                        0x00000001
+                                        0x00000000
+                                        0x00000063
+                                        0x0000000f
+                                        0x0000006b
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x0000000d
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x00000c11
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0x002c00a0
+                                        0x00008000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00030000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00068000
+                                        0x00068000
+                                        0x00000000
+                                        0x00068000
+                                        0x00068000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00058000
+                                        0x00058000
+                                        0x00058000
+                                        0x00058000
+                                        0x00005800
+                                        0x00005800
+                                        0x00005800
+                                        0x00005800
+                                        0x10000280
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc081
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0000003f
+                                        0x000000c6
+                                        0x00000000
+                                        0x00000100
+                                        0x015b000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000052a3
+                                        0x8000188b
+                                        0x00000009
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0128000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x0000001c
+                                        0x0000009a
+                                        0x00000000
+                                        0x00000013
+                                        0x00000007
+                                        0x00000007
+                                        0x0000000b
+                                        0x00000003
+                                        0x00000010
+                                        0x00000007
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000000
+                                        0x00000005
+                                        0x00000005
+                                        0x0000000a
+                                        0x00000002
+                                        0x00000000
+                                        0x00000003
+                                        0x0000000b
+                                        0x00070000
+                                        0x00000003
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000002
+                                        0x00000012
+                                        0x00000016
+                                        0x00000018
+                                        0x00001208
+                                        0x00000000
+                                        0x00000482
+                                        0x00000002
+                                        0x0000000d
+                                        0x00000001
+                                        0x00000000
+                                        0x00000096
+                                        0x00000015
+                                        0x000000a2
+                                        0x00000200
+                                        0x00000004
+                                        0x00000005
+                                        0x00000004
+                                        0x00000015
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x00001248
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00e00b1
+                                        0x00008000
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00040000
+                                        0x00040000
+                                        0x00000000
+                                        0x00040000
+                                        0x00040000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000005
+                                        0x00000007
+                                        0x00000004
+                                        0x00000006
+                                        0x00000007
+                                        0x00000004
+                                        0x00000004
+                                        0x00000001
+                                        0x00000005
+                                        0x00000007
+                                        0x00000004
+                                        0x00000006
+                                        0x00000007
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x51451420
+                                        0x00514514
+                                        0x00514514
+                                        0x51451400
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x0128000c
+                                        0x00000000
+                                        0x00000003
+                                        0x000040a0
+                                        0x800024a9
+                                        0x0000000e
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200018>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f8000c>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+                                nvidia,emc-configuration = <
+                                        0x00000025
+                                        0x000000cc
+                                        0x00000000
+                                        0x0000001a
+                                        0x00000009
+                                        0x00000008
+                                        0x0000000d
+                                        0x00000004
+                                        0x00000013
+                                        0x00000009
+                                        0x00000009
+                                        0x00000003
+                                        0x00000002
+                                        0x00000000
+                                        0x00000006
+                                        0x00000006
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x0000000d
+                                        0x00080000
+                                        0x00000004
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000001
+                                        0x00000014
+                                        0x00000018
+                                        0x0000001a
+                                        0x000017e2
+                                        0x00000000
+                                        0x000005f8
+                                        0x00000003
+                                        0x00000011
+                                        0x00000001
+                                        0x00000000
+                                        0x000000c6
+                                        0x00000018
+                                        0x000000d6
+                                        0x00000200
+                                        0x00000005
+                                        0x00000006
+                                        0x00000005
+                                        0x0000001d
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00001822
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x104ab098
+                                        0xe00700b1
+                                        0x00008000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000008
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x0002c000
+                                        0x0002c000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000000
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x00000008
+                                        0x00000008
+                                        0x00000005
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000008
+                                        0x0000000a
+                                        0x0000000a
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x0000000e
+                                        0x100002a0
+                                        0x00000000
+                                        0x00111111
+                                        0x00000000
+                                        0x00000000
+                                        0x77ffc085
+                                        0x00000202
+                                        0x81f1f108
+                                        0x07070004
+                                        0x00000000
+                                        0x016eeeee
+                                        0x61861820
+                                        0x00492492
+                                        0x00492492
+                                        0x61861800
+                                        0x0606003f
+                                        0x00000000
+                                        0x00000000
+                                        0x00000100
+                                        0x00f8000c
+                                        0x00000000
+                                        0x00000004
+                                        0x00004080
+                                        0x80003012
+                                        0x0000000f
+                                >;
+                        };
+                };
+        };
+        memory-controller@0,70019000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,emem-configuration = <
+                                        0x40040001
+                                        0x8000000a
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x77e30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,emem-configuration = <
+                                        0x40020001
+                                        0x80000012
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x76230303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,emem-configuration = <
+                                        0xa0000001
+                                        0x80000017
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74a30303
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000001
+                                        0x8000001e
+                                        0x00000001
+                                        0x00000001
+                                        0x00000002
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0402
+                                        0x74230403
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000001
+                                        0x80000026
+                                        0x00000001
+                                        0x00000001
+                                        0x00000003
+                                        0x00000000
+                                        0x00000002
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000003
+                                        0x00000006
+                                        0x06030203
+                                        0x000a0403
+                                        0x73c30504
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,emem-configuration = <
+                                        0x01000003
+                                        0x80000040
+                                        0x00000001
+                                        0x00000001
+                                        0x00000005
+                                        0x00000002
+                                        0x00000004
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000003
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040203
+                                        0x000a0405
+                                        0x73840a06
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,emem-configuration = <
+                                        0x08000004
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000004
+                                        0x00000005
+                                        0x00000001
+                                        0x00000002
+                                        0x00000007
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000b0607
+                                        0x77450e08
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,emem-configuration = <
+                                        0x0f000005
+                                        0x80000040
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000005
+                                        0x00000007
+                                        0x00000001
+                                        0x00000002
+                                        0x00000008
+                                        0x00000002
+                                        0x00000002
+                                        0x00000004
+                                        0x00000006
+                                        0x06040202
+                                        0x000d0709
+                                        0x7586120a
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,emem-configuration = <
+                                        0x0f000007
+                                        0x80000040
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000d
+                                        0x00000008
+                                        0x0000000a
+                                        0x00000001
+                                        0x00000002
+                                        0x00000009
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000006
+                                        0x06050202
+                                        0x0010090d
+                                        0x7428180e
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,emem-configuration = <
+                                        0x00000009
+                                        0x80000040
+                                        0x00000003
+                                        0x00000004
+                                        0x0000000e
+                                        0x00000009
+                                        0x0000000b
+                                        0x00000001
+                                        0x00000003
+                                        0x0000000b
+                                        0x00000002
+                                        0x00000002
+                                        0x00000005
+                                        0x00000007
+                                        0x07050202
+                                        0x00130b0e
+                                        0x73a91b0f
+                                        0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,emem-configuration = <
+                                        0x0e00000b
+                                        0x80000040
+                                        0x00000004
+                                        0x00000005
+                                        0x00000013
+                                        0x0000000c
+                                        0x0000000f
+                                        0x00000002
+                                        0x00000003
+                                        0x0000000c
+                                        0x00000002
+                                        0x00000002
+                                        0x00000006
+                                        0x00000008
+                                        0x08060202
+                                        0x00160d13
+                                        0x734c2414
+                                        0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
new file mode 100644
index 000000000000..0d30c514ffad
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -0,0 +1,1334 @@
+/dts-v1/;
+#include "tegra124-nyan.dtsi"
+#include "tegra124-nyan-blaze-emc.dtsi"
+/ {
+        model = "HP Chromebook 14";
+        compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124";
+        panel: panel {
+                compatible = "samsung,ltn140at29-301";
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&dpaux>;
+        };
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
+                             "nvidia,tegra-audio-max98090-nyan",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "GoogleNyanBlaze";
+        };
+        pinmux@0,70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_default>;
+                pinmux_default: common {
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb1 {
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pc7 {
+                                nvidia,pins = "pc7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg0 {
+                                nvidia,pins = "pg0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg1 {
+                                nvidia,pins = "pg1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg2 {
+                                nvidia,pins = "pg2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg3 {
+                                nvidia,pins = "pg3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg5 {
+                                nvidia,pins = "pg5";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 {
+                                nvidia,pins = "ph4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph5 {
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 {
+                                nvidia,pins = "ph6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 {
+                                nvidia,pins = "pi0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi1 {
+                                nvidia,pins = "pi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi2 {
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 {
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi5 {
+                                nvidia,pins = "pi5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi6 {
+                                nvidia,pins = "pi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi7 {
+                                nvidia,pins = "pi7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj0 {
+                                nvidia,pins = "pj0";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 {
+                                nvidia,pins = "pk1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk3 {
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 {
+                                nvidia,pins = "pk4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk7 {
+                                nvidia,pins = "pk7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row16_pt0 {
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 {
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 {
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w2_aud_pw2 {
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x3_aud_px3 {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 {
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_out_pee4 {
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_clk_lb_in_pee5 {
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "dp";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en2_pff1 {
+                                nvidia,pins = "usb_vbus_en2_pff1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
new file mode 100644
index 000000000000..a9aec23e06f2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -0,0 +1,695 @@
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+/ {
+        aliases {
+                rtc0 = "/i2c@0,7000d000/pmic@40";
+                rtc1 = "/rtc@0,7000e000";
+                serial0 = &uarta;
+        };
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+        host1x@0,50000000 {
+                hdmi@0,54280000 {
+                        status = "okay";
+                        vdd-supply = <&vdd_3v3_hdmi>;
+                        pll-supply = <&vdd_hdmi_pll>;
+                        hdmi-supply = <&vdd_5v0_hdmi>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+                sor@0,54540000 {
+                        status = "okay";
+                        nvidia,dpaux = <&dpaux>;
+                        nvidia,panel = <&panel>;
+                };
+                dpaux@0,545c0000 {
+                        vdd-supply = <&vdd_3v3_panel>;
+                        status = "okay";
+                };
+        };
+        serial@0,70006000 {
+                /* Debug connector on the bottom of the board near SD card. */
+                status = "okay";
+        };
+        pwm@0,7000a000 {
+                status = "okay";
+        };
+        i2c@0,7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                acodec: audio-codec@10 {
+                        compatible = "maxim,max98090";
+                        reg = <0x10>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                };
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+        i2c@0,7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+                trackpad@15 {
+                        compatible = "elan,ekth3000";
+                        reg = <0x15>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                };
+        };
+        i2c@0,7000c500 {
+                status = "okay";
+                clock-frequency = <400000>;
+                tpm@20 {
+                        compatible = "infineon,slb9645tt";
+                        reg = <0x20>;
+                };
+        };
+        hdmi_ddc: i2c@0,7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@0,7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                        ams,system-power-controller;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+                                gpio1 {
+                                        pins = "gpio1";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+                                gpio2_4_7 {
+                                        pins = "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+                                gpio3_6 {
+                                        pins = "gpio3", "gpio6";
+                                        bias-high-impedance;
+                                };
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "clk32k-out";
+                                        bias-pull-down;
+                                };
+                        };
+                        regulators {
+                                vsup-sd2-supply = <&vdd_5v0_sys>;
+                                vsup-sd3-supply = <&vdd_5v0_sys>;
+                                vsup-sd4-supply = <&vdd_5v0_sys>;
+                                vsup-sd5-supply = <&vdd_5v0_sys>;
+                                vin-ldo0-supply = <&vdd_1v35_lp0>;
+                                vin-ldo1-6-supply = <&vdd_3v3_run>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
+                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
+                                vin-ldo11-supply = <&vdd_3v3_run>;
+                                sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <2>;
+                                };
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <4000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <1>;
+                                };
+                                vdd_1v35_lp0: sd2 {
+                                        regulator-name = "+1.35V_LP0(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                sd3 {
+                                        regulator-name = "+1.35V_LP0(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                vdd_1v05_run: sd4 {
+                                        regulator-name = "+1.05V_RUN";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+1.8V_VDDIO";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                                ldo0 {
+                                        regulator-name = "+1.05V_RUN_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,ext-control = <1>;
+                                };
+                                ldo1 {
+                                        regulator-name = "+1.8V_RUN_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo2 {
+                                        regulator-name = "+1.2V_GEN_AVDD";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                                ldo3 {
+                                        regulator-name = "+1.00V_LP0_VDD_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+                                vdd_run_cam: ldo4 {
+                                        regulator-name = "+3.3V_RUN_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo5 {
+                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "+VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo7 {
+                                        regulator-name = "+1.05V_RUN_CAM_REAR";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                ldo9 {
+                                        regulator-name = "+2.8V_RUN_TOUCH";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo10 {
+                                        regulator-name = "+2.8V_RUN_CAM_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo11 {
+                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+        spi@0,7000d400 {
+                status = "okay";
+                cros_ec: cros-ec@0 {
+                        compatible = "google,cros-ec-spi";
+                        spi-max-frequency = <3000000>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                        reg = <0>;
+                        google,cros-ec-spi-msg-delay = <2000>;
+                        i2c-tunnel {
+                                compatible = "google,cros-ec-i2c-tunnel";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                google,remote-bus = <0>;
+                                charger: bq24735@9 {
+                                        compatible = "ti,bq24735";
+                                        reg = <0x9>;
+                                        interrupt-parent = <&gpio>;
+                                        interrupts = <TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                        ti,ac-detect-gpios = <&gpio
+                                                        TEGRA_GPIO(J, 0)
+                                                        GPIO_ACTIVE_HIGH>;
+                                };
+                                battery: sbs-battery@b {
+                                        compatible = "sbs,sbs-battery";
+                                        reg = <0xb>;
+                                        sbs,i2c-retry-count = <2>;
+                                        sbs,poll-retry-count = <10>;
+                                        power-supplies = <&charger>;
+                                };
+                        };
+                };
+        };
+        spi@0,7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        spi-max-frequency = <25000000>;
+                        reg = <0>;
+                };
+        };
+        pmc@0,7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <0>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+        };
+        hda@0,70030000 {
+                status = "okay";
+        };
+        sdhci0_pwrseq: sdhci0_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
+        };
+        sdhci@0,700b0000 { /* WiFi/BT on this bus */
+                status = "okay";
+                bus-width = <4>;
+                no-1-8-v;
+                non-removable;
+                mmc-pwrseq = <&sdhci0_pwrseq>;
+                vmmc-supply = <&vdd_3v3_lp0>;
+                vqmmc-supply = <&vddio_1v8>;
+                keep-power-in-suspend;
+        };
+        sdhci@0,700b0400 { /* SD Card on this bus */
+                status = "okay";
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                no-1-8-v;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+        sdhci@0,700b0600 { /* eMMC on this bus */
+                status = "okay";
+                bus-width = <8>;
+                no-1-8-v;
+                non-removable;
+        };
+        ahub@0,70300000 {
+                i2s@0,70301100 {
+                        status = "okay";
+                };
+        };
+        usb@0,7d000000 { /* Rear external USB port. */
+                status = "okay";
+        };
+        usb-phy@0,7d000000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb1_vbus>;
+        };
+        usb@0,7d004000 { /* Internal webcam. */
+                status = "okay";
+        };
+        usb-phy@0,7d004000 {
+                status = "okay";
+                vbus-supply = <&vdd_run_cam>;
+        };
+        usb@0,7d008000 { /* Left external USB port. */
+                status = "okay";
+        };
+        usb-phy@0,7d008000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb3_vbus>;
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_led>;
+                pwms = <&pwm 1 1000000>;
+                default-brightness-level = <224>;
+                brightness-levels =
+                        <  0   1   2   3   4   5   6   7
+                           8   9  10  11  12  13  14  15
+                          16  17  18  19  20  21  22  23
+                          24  25  26  27  28  29  30  31
+                          32  33  34  35  36  37  38  39
+                          40  41  42  43  44  45  46  47
+                          48  49  50  51  52  53  54  55
+                          56  57  58  59  60  61  62  63
+                          64  65  66  67  68  69  70  71
+                          72  73  74  75  76  77  78  79
+                          80  81  82  83  84  85  86  87
+                          88  89  90  91  92  93  94  95
+                          96  97  98  99 100 101 102 103
+                         104 105 106 107 108 109 110 111
+                         112 113 114 115 116 117 118 119
+                         120 121 122 123 124 125 126 127
+                         128 129 130 131 132 133 134 135
+                         136 137 138 139 140 141 142 143
+                         144 145 146 147 148 149 150 151
+                         152 153 154 155 156 157 158 159
+                         160 161 162 163 164 165 166 167
+                         168 169 170 171 172 173 174 175
+                         176 177 178 179 180 181 182 183
+                         184 185 186 187 188 189 190 191
+                         192 193 194 195 196 197 198 199
+                         200 201 202 203 204 205 206 207
+                         208 209 210 211 212 213 214 215
+                         216 217 218 219 220 221 222 223
+                         224 225 226 227 228 229 230 231
+                         232 233 234 235 236 237 238 239
+                         240 241 242 243 244 245 246 247
+                         248 249 250 251 252 253 254 255
+                         256>;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                lid {
+                        label = "Lid";
+                        gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+                        linux,input-type = <5>;
+                        linux,code = <KEY_RESERVED>;
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <30>;
+                        gpio-key,wakeup;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_mux: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+VDD_MUX";
+                        regulator-min-microvolt = <12000000>;
+                        regulator-max-microvolt = <12000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+                vdd_5v0_sys: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "+5V_SYS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+                vdd_3v3_sys: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "+3.3V_SYS";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+                vdd_3v3_run: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "+3.3V_RUN";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+                vdd_3v3_hdmi: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+                vdd_led: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "+VDD_LED";
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_mux>;
+                };
+                vdd_5v0_ts: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "+5V_VDD_TS_SW";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_usb1_vbus: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "+5V_USB_HS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_usb3_vbus: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "+5V_USB_SS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_3v3_panel: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "+3.3V_PANEL";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+                vdd_3v3_lp0: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "+3.3V_LP0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        /*
+                         * TODO: find a way to wire this up with the USB EHCI
+                         * controllers so that it can be enabled on demand.
+                         */
+                        regulator-always-on;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+                vdd_hdmi_pll: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_1v05_run>;
+                };
+                vdd_5v0_hdmi: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "+5V_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+        };
+        sound {
+                nvidia,audio-routing =
+                        "Headphones", "HPR",
+                        "Headphones", "HPL",
+                        "Speakers", "SPKR",
+                        "Speakers", "SPKL",
+                        "Mic Jack", "MICBIAS",
+                        "DMICL", "Int Mic",
+                        "DMICR", "Int Mic",
+                        "IN34", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&acodec>;
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
+                nvidia,mic-det-gpios =
+                                <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+        };
+        gpio-restart {
+                compatible = "gpio-restart";
+                gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                priority = <200>;
+        };
+};
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index db85695aa7aa..cf01c818b8ea 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -220,6 +220,7 @@
                reg = <0x0 0x60006000 0x0 0x1000>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+                nvidia,external-memory-controller = <&emc>;
        };
        flow-controller@0,60007000 {
@@ -227,6 +228,17 @@
                reg = <0x0 0x60007000 0x0 0x1000>;
        };
+        actmon@0,6000c800 {
+                compatible = "nvidia,tegra124-actmon";
+                reg = <0x0 0x6000c800 0x0 0x400>;
+                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
+                         <&tegra_car TEGRA124_CLK_EMC>;
+                clock-names = "actmon", "emc";
+                resets = <&tegra_car 119>;
+                reset-names = "actmon";
+        };
        gpio: gpio@0,6000d000 {
                compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -582,6 +594,13 @@
                #iommu-cells = <1>;
        };
+        emc: emc@0,7001b000 {
+                compatible = "nvidia,tegra124-emc";
+                reg = <0x0 0x7001b000 0x0 0x1000>;
+                nvidia,memory-controller = <&mc>;
+        };
        sata@0,70020000 {
                compatible = "nvidia,tegra124-ahci";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 6b157eeabcc5..3dede3934446 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -62,71 +62,1652 @@
                pinctrl-0 = <&state_default>;
                state_default: pinmux {
-                        sdmmc1_clk_pz0 {
+                        clk_32k_out_pa0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,pins = "clk_32k_out_pa0";
-                                nvidia,function = "sdmmc1";
+                                nvidia,function = "blink";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };
-                        sdmmc1_cmd_pz1 {
+                        uart3_cts_n_pa1 {
-                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                nvidia,pins = "uart3_cts_n_pa1";
-                                                "sdmmc1_dat0_py7",
+                                nvidia,function = "uartc";
-                                                "sdmmc1_dat1_py6",
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                                "sdmmc1_dat2_py5",
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                                "sdmmc1_dat3_py4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,function = "sdmmc1";
+                        };
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc3_clk_pa6 {
                                nvidia,pins = "sdmmc3_clk_pa6";
                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc3_cmd_pa7 {
-                                nvidia,pins =   "sdmmc3_cmd_pa7",
+                                nvidia,pins = "sdmmc3_cmd_pa7";
-                                                "sdmmc3_dat0_pb7",
-                                                "sdmmc3_dat1_pb6",
-                                                "sdmmc3_dat2_pb5",
-                                                "sdmmc3_dat3_pb4";
                                nvidia,function = "sdmmc3";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        sdmmc4_clk_pcc4 {
+                        gmi_a17_pb0 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                nvidia,pins = "gmi_a17_pb0";
-                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_a18_pb1 {
+                                nvidia,pins = "gmi_a18_pb1";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pwr0_pb2 {
+                                nvidia,pins = "lcd_pwr0_pb2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pclk_pb3 {
+                                nvidia,pins = "lcd_pclk_pb3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_pwr1_pc1 {
+                                nvidia,pins = "lcd_pwr1_pc1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_pwr2_pc6 {
+                                nvidia,pins = "lcd_pwr2_pc6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_wp_n_pc7 {
+                                nvidia,pins = "gmi_wp_n_pc7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat5_pd0 {
+                                nvidia,pins = "sdmmc3_dat5_pd0";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat4_pd1 {
+                                nvidia,pins = "sdmmc3_dat4_pd1";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_dc1_pd2 {
+                                nvidia,pins = "lcd_dc1_pd2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat6_pd3 {
+                                nvidia,pins = "sdmmc3_dat6_pd3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat7_pd4 {
+                                nvidia,pins = "sdmmc3_dat7_pd4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d1_pd5 {
+                                nvidia,pins = "vi_d1_pd5";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_vsync_pd6 {
+                                nvidia,pins = "vi_vsync_pd6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_hsync_pd7 {
+                                nvidia,pins = "vi_hsync_pd7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d0_pe0 {
+                                nvidia,pins = "lcd_d0_pe0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d1_pe1 {
+                                nvidia,pins = "lcd_d1_pe1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d2_pe2 {
+                                nvidia,pins = "lcd_d2_pe2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d3_pe3 {
+                                nvidia,pins = "lcd_d3_pe3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d4_pe4 {
+                                nvidia,pins = "lcd_d4_pe4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d5_pe5 {
+                                nvidia,pins = "lcd_d5_pe5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d6_pe6 {
+                                nvidia,pins = "lcd_d6_pe6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d7_pe7 {
+                                nvidia,pins = "lcd_d7_pe7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d8_pf0 {
+                                nvidia,pins = "lcd_d8_pf0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d9_pf1 {
+                                nvidia,pins = "lcd_d9_pf1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d10_pf2 {
+                                nvidia,pins = "lcd_d10_pf2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d11_pf3 {
+                                nvidia,pins = "lcd_d11_pf3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d12_pf4 {
+                                nvidia,pins = "lcd_d12_pf4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d13_pf5 {
+                                nvidia,pins = "lcd_d13_pf5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d14_pf6 {
+                                nvidia,pins = "lcd_d14_pf6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d15_pf7 {
+                                nvidia,pins = "lcd_d15_pf7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad0_pg0 {
+                                nvidia,pins = "gmi_ad0_pg0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad1_pg1 {
+                                nvidia,pins = "gmi_ad1_pg1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad2_pg2 {
+                                nvidia,pins = "gmi_ad2_pg2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad3_pg3 {
+                                nvidia,pins = "gmi_ad3_pg3";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad4_pg4 {
+                                nvidia,pins = "gmi_ad4_pg4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad5_pg5 {
+                                nvidia,pins = "gmi_ad5_pg5";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad6_pg6 {
+                                nvidia,pins = "gmi_ad6_pg6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad7_pg7 {
+                                nvidia,pins = "gmi_ad7_pg7";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad8_ph0 {
+                                nvidia,pins = "gmi_ad8_ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad9_ph1 {
+                                nvidia,pins = "gmi_ad9_ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad10_ph2 {
+                                nvidia,pins = "gmi_ad10_ph2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad11_ph3 {
+                                nvidia,pins = "gmi_ad11_ph3";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad12_ph4 {
+                                nvidia,pins = "gmi_ad12_ph4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad13_ph5 {
+                                nvidia,pins = "gmi_ad13_ph5";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad14_ph6 {
+                                nvidia,pins = "gmi_ad14_ph6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_wr_n_pi0 {
+                                nvidia,pins = "gmi_wr_n_pi0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_oe_n_pi1 {
+                                nvidia,pins = "gmi_oe_n_pi1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_dqs_pi2 {
+                                nvidia,pins = "gmi_dqs_pi2";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_iordy_pi5 {
+                                nvidia,pins = "gmi_iordy_pi5";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_cs7_n_pi6 {
+                                nvidia,pins = "gmi_cs7_n_pi6";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_wait_pi7 {
+                                nvidia,pins = "gmi_wait_pi7";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_de_pj1 {
+                                nvidia,pins = "lcd_de_pj1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_hsync_pj3 {
+                                nvidia,pins = "lcd_hsync_pj3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_vsync_pj4 {
+                                nvidia,pins = "lcd_vsync_pj4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_a16_pj7 {
+                                nvidia,pins = "gmi_a16_pj7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_adv_n_pk0 {
+                                nvidia,pins = "gmi_adv_n_pk0";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_clk_pk1 {
+                                nvidia,pins = "gmi_clk_pk1";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_cs2_n_pk3 {
+                                nvidia,pins = "gmi_cs2_n_pk3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_cs3_n_pk4 {
+                                nvidia,pins = "gmi_cs3_n_pk4";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_a19_pk7 {
+                                nvidia,pins = "gmi_a19_pk7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d2_pl0 {
+                                nvidia,pins = "vi_d2_pl0";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d3_pl1 {
+                                nvidia,pins = "vi_d3_pl1";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d4_pl2 {
+                                nvidia,pins = "vi_d4_pl2";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi_d5_pl3 {
+                                nvidia,pins = "vi_d5_pl3";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d6_pl4 {
+                                nvidia,pins = "vi_d6_pl4";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi_d7_pl5 {
+                                nvidia,pins = "vi_d7_pl5";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d8_pl6 {
+                                nvidia,pins = "vi_d8_pl6";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d9_pl7 {
+                                nvidia,pins = "vi_d9_pl7";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d16_pm0 {
+                                nvidia,pins = "lcd_d16_pm0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d17_pm1 {
+                                nvidia,pins = "lcd_d17_pm1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d18_pm2 {
+                                nvidia,pins = "lcd_d18_pm2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d19_pm3 {
+                                nvidia,pins = "lcd_d19_pm3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d20_pm4 {
+                                nvidia,pins = "lcd_d20_pm4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d21_pm5 {
+                                nvidia,pins = "lcd_d21_pm5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d22_pm6 {
+                                nvidia,pins = "lcd_d22_pm6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_d23_pm7 {
+                                nvidia,pins = "lcd_d23_pm7";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_cs0_n_pn4 {
+                                nvidia,pins = "lcd_cs0_n_pn4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sdout_pn5 {
+                                nvidia,pins = "lcd_sdout_pn5";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_dc0_pn6 {
+                                nvidia,pins = "lcd_dc0_pn6";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_pclk_pt0 {
+                                nvidia,pins = "vi_pclk_pt0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_mclk_pt1 {
+                                nvidia,pins = "vi_mclk_pt1";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d10_pt2 {
+                                nvidia,pins = "vi_d10_pt2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d11_pt3 {
+                                nvidia,pins = "vi_d11_pt3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        vi_d0_pt4 {
+                                nvidia,pins = "vi_d0_pt4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck_pu7 {
+                                nvidia,pins = "jtag_rtck_pu7";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv2 {
+                                nvidia,pins = "pv2";
+                                nvidia,function = "owr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv3 {
+                                nvidia,pins = "pv3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        crt_hsync_pv6 {
+                                nvidia,pins = "crt_hsync_pv6";
+                                nvidia,function = "crt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        crt_vsync_pv7 {
+                                nvidia,pins = "crt_vsync_pv7";
+                                nvidia,function = "crt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd_cs1_n_pw0 {
+                                nvidia,pins = "lcd_cs1_n_pw0";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_m1_pw1 {
+                                nvidia,pins = "lcd_m1_pw1";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi2_cs1_n_pw2 {
+                                nvidia,pins = "spi2_cs1_n_pw2";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk1_out_pw4 {
+                                nvidia,pins = "clk1_out_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "extperiph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi2_sck_px2 {
+                                nvidia,pins = "spi2_sck_px2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_mosi_px4 {
+                                nvidia,pins = "spi1_mosi_px4";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_sck_px5 {
+                                nvidia,pins = "spi1_sck_px5";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_cs0_n_px6 {
+                                nvidia,pins = "spi1_cs0_n_px6";
+                                nvidia,function = "spi1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spi1_miso_px7 {
+                                nvidia,pins = "spi1_miso_px7";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sdin_pz2 {
+                                nvidia,pins = "lcd_sdin_pz2";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_wr_n_pz3 {
+                                nvidia,pins = "lcd_wr_n_pz3";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_sck_pz4 {
+                                nvidia,pins = "lcd_sck_pz4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sys_clk_req_pz5 {
+                                nvidia,pins = "sys_clk_req_pz5";
+                                nvidia,function = "sysclk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                nvidia,pins = "sdmmc4_dat0_paa0";
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
                                nvidia,function = "sdmmc4";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
-                        dap2_fs_pa2 {
+                        sdmmc4_dat1_paa1 {
-                                nvidia,pins =   "dap2_fs_pa2",
+                                nvidia,pins = "sdmmc4_dat1_paa1";
-                                                "dap2_sclk_pa3",
+                                nvidia,function = "sdmmc4";
-                                                "dap2_din_pa4",
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                                                "dap2_dout_pa5";
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "vgp5";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "i2s4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "i2s4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_rst_n_pcc3 {
+                                nvidia,pins = "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "dap";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l2_rst_n_pcc6 {
+                                nvidia,pins = "pex_l2_rst_n_pcc6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l2_clkreq_n_pcc7 {
+                                nvidia,pins = "pex_l2_clkreq_n_pcc7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_prsnt_n_pdd0 {
+                                nvidia,pins = "pex_l0_prsnt_n_pdd0";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        pex_l1_prsnt_n_pdd4 {
-                                nvidia,pins =   "pex_l1_prsnt_n_pdd4",
+                                nvidia,pins = "pex_l1_prsnt_n_pdd4";
-                                                "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "pcie";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l2_prsnt_n_pdd7 {
+                                nvidia,pins = "pex_l2_prsnt_n_pdd7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "dev3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk1_req_pee2 {
+                                nvidia,pins = "clk1_req_pee2";
+                                nvidia,function = "dap";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "owr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdio3 {
                                nvidia,pins = "drive_sdio3";
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 36cafbfa1bfa..606753eb72c8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -12,6 +12,12 @@
                bootargs = "console=ttyLP0,115200";
        };
+        clk16m: clk16m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -47,6 +53,21 @@
        status  = "okay";
 };
+&dspi1 {
+        status = "okay";
+        mcp2515can: can@0 {
+                compatible = "microchip,mcp2515";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can_int>;
+                reg = <0>;
+                clocks = <&clk16m>;
+                spi-max-frequency = <10000000>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <11 GPIO_ACTIVE_LOW>;
+        };
+};
 &esdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_esdhc1>;
@@ -94,3 +115,13 @@
 &usbh1 {
        vbus-supply = <&usbh_vbus_reg>;
 };
+&iomuxc {
+        vf610-colibri {
+                pinctrl_can_int: can_int {
+                        fsl,pins = <
+                                VF610_PAD_PTB21__GPIO_43        0x22ed
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 5c2b7320856d..fbef0828e930 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -23,6 +23,12 @@
        status = "okay";
 };
+&dspi1 {
+        bus-num = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_dspi1>;
+};
 &edma0 {
        status = "okay";
 };
@@ -107,6 +113,15 @@
                        >;
                };
+                pinctrl_dspi1: dspi1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD5__DSPI1_CS0               0x33e2
+                                VF610_PAD_PTD6__DSPI1_SIN               0x33e1
+                                VF610_PAD_PTD7__DSPI1_SOUT              0x33e2
+                                VF610_PAD_PTD8__DSPI1_SCK               0x33e2
+                        >;
+                };
                pinctrl_esdhc1: esdhc1grp {
                        fsl,pins = <
                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2d1ddf..e976d2fa1527 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
        };
        soc {
-                interrupt-parent = <&intc>;
                aips-bus@40000000 {
                        intc: interrupt-controller@40002000 {
                                compatible = "arm,cortex-a9-gic";
                                #interrupt-cells = <3>;
                                interrupt-controller;
+                                interrupt-parent = <&intc>;
                                reg = <0x40003000 0x1000>,
                                      <0x40002100 0x100>;
                        };
@@ -40,145 +39,17 @@
                                compatible = "arm,cortex-a9-global-timer";
                                reg = <0x40002200 0x20>;
                                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                                clocks = <&clks VF610_CLK_PLATFORM_BUS>;
                        };
                };
        };
 };
-&adc0 {
+&mscm_ir {
-        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-parent = <&intc>;
-};
-&adc1 {
-        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-&can0 {
-        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-&can1 {
-        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-&dspi0 {
-        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-&edma0 {
-        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-&edma1 {
-        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-&esdhc1 {
-        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-&fec0 {
-        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-&fec1 {
-        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-&ftm {
-        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio0 {
-        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio1 {
-        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio2 {
-        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio3 {
-        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio4 {
-        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-&i2c0 {
-        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-&pit {
-        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-&qspi0 {
-        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-&sai2 {
-        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-&snvsrtc {
-        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-&src {
-        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart0 {
-        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart1 {
-        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart2 {
-        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart3 {
-        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart4 {
-        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart5 {
-        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbdev0 {
-        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbh1 {
-        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbphy0 {
-        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbphy1 {
-        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 };
 &wdoga5 {
-        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce15eaf..4aa335166be7 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
+                interrupt-parent = <&mscm_ir>;
                ranges;
                aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
                        #size-cells = <1>;
                        ranges;
+                        mscm_cpucfg: cpucfg@40001000 {
+                                compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+                                reg = <0x40001000 0x800>;
+                        };
+                        mscm_ir: interrupt-controller@40001800 {
+                                compatible = "fsl,vf610-mscm-ir";
+                                reg = <0x40001800 0x400>;
+                                fsl,cpucfg = <&mscm_cpucfg>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
                        edma0: dma-controller@40018000 {
                                #dma-cells = <2>;
                                compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
                                        <0x40024000 0x1000>,
                                        <0x40025000 0x1000>;
                                dma-channels = <32>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+                                                <9 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                clock-names = "dmamux0", "dmamux1";
                                clocks = <&clks VF610_CLK_DMAMUX0>,
                                        <&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
                        can0: flexcan@40020000 {
                                compatible = "fsl,vf610-flexcan";
                                reg = <0x40020000 0x4000>;
+                                interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_FLEXCAN0>,
                                         <&clks VF610_CLK_FLEXCAN0>;
                                clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
                        uart0: serial@40027000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40027000 0x1000>;
+                                interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART0>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
                        uart1: serial@40028000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40028000 0x1000>;
+                                interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART1>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
                        uart2: serial@40029000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40029000 0x1000>;
+                                interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART2>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
                        uart3: serial@4002a000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x4002a000 0x1000>;
+                                interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART3>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 8>,
@@ -133,15 +155,29 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-dspi";
                                reg = <0x4002c000 0x1000>;
+                                interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_DSPI0>;
                                clock-names = "dspi";
                                spi-num-chipselects = <5>;
                                status = "disabled";
                        };
+                        dspi1: dspi1@4002d000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-dspi";
+                                reg = <0x4002d000 0x1000>;
+                                interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_DSPI1>;
+                                clock-names = "dspi";
+                                spi-num-chipselects = <5>;
+                                status = "disabled";
+                        };
                        sai2: sai@40031000 {
                                compatible = "fsl,vf610-sai";
                                reg = <0x40031000 0x1000>;
+                                interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_SAI2>;
                                clock-names = "sai";
                                dma-names = "tx", "rx";
@@ -153,6 +189,7 @@
                        pit: pit@40037000 {
                                compatible = "fsl,vf610-pit";
                                reg = <0x40037000 0x1000>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_PIT>;
                                clock-names = "pit";
                        };
@@ -186,6 +223,7 @@
                        adc0: adc@4003b000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x4003b000 0x1000>;
+                                interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ADC0>;
                                clock-names = "adc";
                                status = "disabled";
@@ -194,6 +232,7 @@
                        wdoga5: wdog@4003e000 {
                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
                                reg = <0x4003e000 0x1000>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_WDT>;
                                clock-names = "wdog";
                                status = "disabled";
@@ -204,6 +243,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-qspi";
                                reg = <0x40044000 0x1000>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_QSPI0_EN>,
                                        <&clks VF610_CLK_QSPI0>;
                                clock-names = "qspi_en", "qspi";
@@ -213,7 +253,6 @@
                        iomuxc: iomuxc@40048000 {
                                compatible = "fsl,vf610-iomuxc";
                                reg = <0x40048000 0x1000>;
-                                #gpio-range-cells = <3>;
                        };
                        gpio0: gpio@40049000 {
@@ -221,6 +260,7 @@
                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +271,7 @@
                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +282,7 @@
                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +293,7 @@
                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +304,7 @@
                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +318,7 @@
                        usbphy0: usbphy@40050800 {
                                compatible = "fsl,vf610-usbphy";
                                reg = <0x40050800 0x400>;
+                                interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBPHY0>;
                                fsl,anatop = <&anatop>;
                                status = "disabled";
@@ -282,6 +327,7 @@
                        usbphy1: usbphy@40050c00 {
                                compatible = "fsl,vf610-usbphy";
                                reg = <0x40050c00 0x400>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBPHY1>;
                                fsl,anatop = <&anatop>;
                                status = "disabled";
@@ -292,6 +338,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-i2c";
                                reg = <0x40066000 0x1000>;
+                                interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_I2C0>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 50>,
@@ -311,6 +358,7 @@
                        usbdev0: usb@40034000 {
                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                reg = <0x40034000 0x800>;
+                                interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBC0>;
                                fsl,usbphy = <&usbphy0>;
                                fsl,usbmisc = <&usbmisc0 0>;
@@ -329,6 +377,7 @@
                        src: src@4006e000 {
                                compatible = "fsl,vf610-src", "syscon";
                                reg = <0x4006e000 0x1000>;
+                                interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
@@ -345,6 +394,9 @@
                                        <0x400a1000 0x1000>,
                                        <0x400a2000 0x1000>;
                                dma-channels = <32>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+                                                <11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                clock-names = "dmamux0", "dmamux1";
                                clocks = <&clks VF610_CLK_DMAMUX2>,
                                        <&clks VF610_CLK_DMAMUX3>;
@@ -360,6 +412,7 @@
                                snvsrtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
+                                        interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks VF610_CLK_SNVS>;
                                        clock-names = "snvs-rtc";
                                };
@@ -368,6 +421,7 @@
                        uart4: serial@400a9000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400a9000 0x1000>;
+                                interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART4>;
                                clock-names = "ipg";
                                status = "disabled";
@@ -376,6 +430,7 @@
                        uart5: serial@400aa000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400aa000 0x1000>;
+                                interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART5>;
                                clock-names = "ipg";
                                status = "disabled";
@@ -384,6 +439,7 @@
                        adc1: adc@400bb000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x400bb000 0x1000>;
+                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ADC1>;
                                clock-names = "adc";
                                status = "disabled";
@@ -392,6 +448,7 @@
                        esdhc1: esdhc@400b2000 {
                                compatible = "fsl,imx53-esdhc";
                                reg = <0x400b2000 0x1000>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_IPG_BUS>,
                                        <&clks VF610_CLK_PLATFORM_BUS>,
                                        <&clks VF610_CLK_ESDHC1>;
@@ -402,6 +459,7 @@
                        usbh1: usb@400b4000 {
                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                reg = <0x400b4000 0x800>;
+                                interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBC1>;
                                fsl,usbphy = <&usbphy1>;
                                fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +478,7 @@
                        ftm: ftm@400b8000 {
                                compatible = "fsl,ftm-timer";
                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
                                clock-names = "ftm-evt", "ftm-src",
                                        "ftm-evt-counter-en", "ftm-src-counter-en";
                                clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +491,7 @@
                        fec0: ethernet@400d0000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d0000 0x1000>;
+                                interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET>;
@@ -442,6 +502,7 @@
                        fec1: ethernet@400d1000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d1000 0x1000>;
+                                interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET>;
@@ -452,6 +513,7 @@
                        can1: flexcan@400d4000 {
                                compatible = "fsl,vf610-flexcan";
                                reg = <0x400d4000 0x4000>;
+                                interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_FLEXCAN1>,
                                         <&clks VF610_CLK_FLEXCAN1>;
                                clock-names = "ipg", "per";
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index 3c165fc2dce2..5f8a52ac7edf 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -55,22 +55,81 @@ bool mcpm_is_available(void)
        return (platform_ops) ? true : false;
 }
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int mcpm_cpu_use_count[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
+static inline bool mcpm_cluster_unused(unsigned int cluster)
+{
+        int i, cnt;
+        for (i = 0, cnt = 0; i < MAX_CPUS_PER_CLUSTER; i++)
+                cnt |= mcpm_cpu_use_count[cluster][i];
+        return !cnt;
+}
 int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster)
 {
+        bool cpu_is_down, cluster_is_down;
+        int ret = 0;
        if (!platform_ops)
                return -EUNATCH; /* try not to shadow power_up errors */
        might_sleep();
-        return platform_ops->power_up(cpu, cluster);
+        /* backward compatibility callback */
+        if (platform_ops->power_up)
+                return platform_ops->power_up(cpu, cluster);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&mcpm_lock);
+        cpu_is_down = !mcpm_cpu_use_count[cluster][cpu];
+        cluster_is_down = mcpm_cluster_unused(cluster);
+        mcpm_cpu_use_count[cluster][cpu]++;
+        /*
+         * The only possible values are:
+         * 0 = CPU down
+         * 1 = CPU (still) up
+         * 2 = CPU requested to be up before it had a chance
+         *     to actually make itself down.
+         * Any other value is a bug.
+         */
+        BUG_ON(mcpm_cpu_use_count[cluster][cpu] != 1 &&
+               mcpm_cpu_use_count[cluster][cpu] != 2);
+        if (cluster_is_down)
+                ret = platform_ops->cluster_powerup(cluster);
+        if (cpu_is_down && !ret)
+                ret = platform_ops->cpu_powerup(cpu, cluster);
+        arch_spin_unlock(&mcpm_lock);
+        local_irq_enable();
+        return ret;
 }
 typedef void (*phys_reset_t)(unsigned long);
 void mcpm_cpu_power_down(void)
 {
+        unsigned int mpidr, cpu, cluster;
+        bool cpu_going_down, last_man;
        phys_reset_t phys_reset;
-        if (WARN_ON_ONCE(!platform_ops || !platform_ops->power_down))
+        if (WARN_ON_ONCE(!platform_ops))
-                return;
+               return;
        BUG_ON(!irqs_disabled());
        /*
@@ -79,28 +138,65 @@ void mcpm_cpu_power_down(void)
         */
        setup_mm_for_reboot();
-        platform_ops->power_down();
+        /* backward compatibility callback */
+        if (platform_ops->power_down) {
+                platform_ops->power_down();
+                goto not_dead;
+        }
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        __mcpm_cpu_going_down(cpu, cluster);
+        arch_spin_lock(&mcpm_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        mcpm_cpu_use_count[cluster][cpu]--;
+        BUG_ON(mcpm_cpu_use_count[cluster][cpu] != 0 &&
+               mcpm_cpu_use_count[cluster][cpu] != 1);
+        cpu_going_down = !mcpm_cpu_use_count[cluster][cpu];
+        last_man = mcpm_cluster_unused(cluster);
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                platform_ops->cpu_powerdown_prepare(cpu, cluster);
+                platform_ops->cluster_powerdown_prepare(cluster);
+                arch_spin_unlock(&mcpm_lock);
+                platform_ops->cluster_cache_disable();
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                if (cpu_going_down)
+                        platform_ops->cpu_powerdown_prepare(cpu, cluster);
+                arch_spin_unlock(&mcpm_lock);
+                /*
+                 * If cpu_going_down is false here, that means a power_up
+                 * request raced ahead of us.  Even if we do not want to
+                 * shut this CPU down, the caller still expects execution
+                 * to return through the system resume entry path, like
+                 * when the WFI is aborted due to a new IRQ or the like..
+                 * So let's continue with cache cleaning in all cases.
+                 */
+                platform_ops->cpu_cache_disable();
+        }
+        __mcpm_cpu_down(cpu, cluster);
+        /* Now we are prepared for power-down, do it: */
+        if (cpu_going_down)
+                wfi();
+not_dead:
        /*
         * It is possible for a power_up request to happen concurrently
         * with a power_down request for the same CPU. In this case the
-         * power_down method might not be able to actually enter a
+         * CPU might not be able to actually enter a powered down state
-         * powered down state with the WFI instruction if the power_up
+         * with the WFI instruction if the power_up request has removed
-         * method has removed the required reset condition.  The
+         * the required reset condition.  We must perform a re-entry in
-         * power_down method is then allowed to return. We must perform
+         * the kernel as if the power_up method just had deasserted reset
-         * a re-entry in the kernel as if the power_up method just had
+         * on the CPU.
-         * deasserted reset on the CPU.
-         *
-         * To simplify race issues, the platform specific implementation
-         * must accommodate for the possibility of unordered calls to
-         * power_down and power_up with a usage count. Therefore, if a
-         * call to power_up is issued for a CPU that is not down, then
-         * the next call to power_down must not attempt a full shutdown
-         * but only do the minimum (normally disabling L1 cache and CPU
-         * coherency) and return just as if a concurrent power_up request
-         * had happened as described above.
         */
        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
        phys_reset(virt_to_phys(mcpm_entry_point));
@@ -125,26 +221,66 @@ int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster)
 void mcpm_cpu_suspend(u64 expected_residency)
 {
-        phys_reset_t phys_reset;
+        if (WARN_ON_ONCE(!platform_ops))
-        if (WARN_ON_ONCE(!platform_ops || !platform_ops->suspend))
                return;
-        BUG_ON(!irqs_disabled());
-        /* Very similar to mcpm_cpu_power_down() */
+        /* backward compatibility callback */
-        setup_mm_for_reboot();
+        if (platform_ops->suspend) {
-        platform_ops->suspend(expected_residency);
+                phys_reset_t phys_reset;
-        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
+                BUG_ON(!irqs_disabled());
-        phys_reset(virt_to_phys(mcpm_entry_point));
+                setup_mm_for_reboot();
-        BUG();
+                platform_ops->suspend(expected_residency);
+                phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
+                phys_reset(virt_to_phys(mcpm_entry_point));
+                BUG();
+        }
+        /* Some platforms might have to enable special resume modes, etc. */
+        if (platform_ops->cpu_suspend_prepare) {
+                unsigned int mpidr = read_cpuid_mpidr();
+                unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+                unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 
+                arch_spin_lock(&mcpm_lock);
+                platform_ops->cpu_suspend_prepare(cpu, cluster);
+                arch_spin_unlock(&mcpm_lock);
+        }
+        mcpm_cpu_power_down();
 }
 int mcpm_cpu_powered_up(void)
 {
+        unsigned int mpidr, cpu, cluster;
+        bool cpu_was_down, first_man;
+        unsigned long flags;
        if (!platform_ops)
                return -EUNATCH;
-        if (platform_ops->powered_up)
+        /* backward compatibility callback */
+        if (platform_ops->powered_up) {
                platform_ops->powered_up();
+                return 0;
+        }
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        local_irq_save(flags);
+        arch_spin_lock(&mcpm_lock);
+        cpu_was_down = !mcpm_cpu_use_count[cluster][cpu];
+        first_man = mcpm_cluster_unused(cluster);
+        if (first_man && platform_ops->cluster_is_up)
+                platform_ops->cluster_is_up(cluster);
+        if (cpu_was_down)
+                mcpm_cpu_use_count[cluster][cpu] = 1;
+        if (platform_ops->cpu_is_up)
+                platform_ops->cpu_is_up(cpu, cluster);
+        arch_spin_unlock(&mcpm_lock);
+        local_irq_restore(flags);
        return 0;
 }
@@ -334,8 +470,10 @@ int __init mcpm_sync_init(
        }
        mpidr = read_cpuid_mpidr();
        this_cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        for_each_online_cpu(i)
+        for_each_online_cpu(i) {
+                mcpm_cpu_use_count[this_cluster][i] = 1;
                mcpm_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
+        }
        mcpm_sync.clusters[this_cluster].cluster = CLUSTER_UP;
        sync_cache_w(&mcpm_sync);
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
deleted file mode 100644
index 9e9a72e3d30f..000000000000
--- a/arch/arm/configs/ape6evm_defconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_EMBEDDED=y
-CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
-CONFIG_ARCH_SHMOBILE_LEGACY=y
-CONFIG_ARCH_R8A73A4=y
-CONFIG_MACH_APE6EVM=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_CPU_BPREDICT_DISABLE=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_SMP=y
-CONFIG_SCHED_MC=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_NR_CPUS=8
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-# CONFIG_HW_PERF_EVENTS is not set
-# CONFIG_COMPACTION is not set
-# CONFIG_CROSS_MEMORY_ATTACH is not set
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6_SIT is not set
-CONFIG_NETFILTER=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER_USER_HELPER is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CADENCE is not set
-CONFIG_SMC91X=y
-CONFIG_SMSC911X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=12
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_SH_MOBILE=y
-CONFIG_GPIO_SH_PFC=y
-CONFIG_GPIOLIB=y
-# CONFIG_HWMON is not set
-CONFIG_THERMAL=y
-CONFIG_RCAR_THERMAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MAX8973=y
-# CONFIG_HID is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHI=y
-CONFIG_MMC_SH_MMCIF=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_DMADEVICES=y
-CONFIG_SH_DMAE=y
-# CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_ROOT_NFS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 811e72bbe642..bcef49a21801 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_AT91=y
+CONFIG_SOC_SAM_V4_V5=y
 CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9=y
-CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 1d8935359fd0..d034c96c039b 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -26,6 +26,8 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_EXYNOS_CPUIDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_PM=y
@@ -34,6 +36,14 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_NET_KEY=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_MWIFIEX=y
+CONFIG_MWIFIEX_SDIO=y
 CONFIG_RFKILL_REGULATOR=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
@@ -91,9 +101,11 @@ CONFIG_CHARGER_MAX77693=y
 CONFIG_CHARGER_TPS65090=y
 CONFIG_HWMON=y
 CONFIG_SENSORS_LM90=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_THERMAL=y
 CONFIG_THERMAL=y
 CONFIG_EXYNOS_THERMAL=y
-CONFIG_EXYNOS_THERMAL_CORE=y
+CONFIG_THERMAL_EMULATION=y
 CONFIG_WATCHDOG=y
 CONFIG_S3C2410_WATCHDOG=y
 CONFIG_MFD_CROS_EC=y
@@ -118,6 +130,7 @@ CONFIG_REGULATOR_S2MPS11=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_DRM=y
+CONFIG_DRM_EXYNOS_HDMI=y
 CONFIG_DRM_BRIDGE=y
 CONFIG_DRM_PTN3460=y
 CONFIG_DRM_PS8622=y
@@ -171,10 +184,11 @@ CONFIG_RTC_DRV_S5M=y
 CONFIG_RTC_DRV_S3C=y
 CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC_CHARDEV=y
 CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_COMMON_CLK_MAX77802=y
 CONFIG_COMMON_CLK_S2MPS11=y
-CONFIG_EXYNOS_IOMMU=y
 CONFIG_EXTCON=y
 CONFIG_EXTCON_MAX14577=y
 CONFIG_EXTCON_MAX77693=y
@@ -197,6 +211,8 @@ CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_CRAMFS=y
 CONFIG_ROMFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e6b0007355f8..d3a8018639de 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -24,9 +24,8 @@ CONFIG_ARCH_MXC=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_APF9328=y
 CONFIG_MACH_MX21ADS=y
-CONFIG_MACH_MX25_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX25SD=y
-CONFIG_MACH_IMX25_DT=y
+CONFIG_SOC_IMX25=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
@@ -177,6 +176,7 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
 # CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index cf1e71e2f60a..fdeb1c83dcb5 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -71,6 +71,9 @@ CONFIG_IPV6=y
 CONFIG_NETFILTER=y
 CONFIG_CAN=y
 CONFIG_CAN_FLEXCAN=y
+CONFIG_BT=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_3WIRE=y
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_RFKILL=y
@@ -168,6 +171,7 @@ CONFIG_SPI=y
 CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MC9S08DZ60=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_STMPE=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_RESET=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
deleted file mode 100644
index 05a529311b4d..000000000000
--- a/arch/arm/configs/mackerel_defconfig
+++ /dev/null
@@ -1,157 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE_LEGACY=y
-CONFIG_ARCH_SH7372=y
-CONFIG_MACH_MACKEREL=y
-CONFIG_MEMORY_SIZE=0x10000000
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_KEXEC=y
-CONFIG_VFP=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_SH_MOBILE=y
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_REGULATOR=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SH_MOBILE_LCDC=y
-CONFIG_FB_SH_MOBILE_HDMI=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_SOC_SH4_FSI=y
-CONFIG_USB=y
-CONFIG_USB_RENESAS_USBHS_HCD=y
-CONFIG_USB_RENESAS_USBHS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_RENESAS_USBHS_UDC=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHI=y
-CONFIG_MMC_SH_MMCIF=y
-CONFIG_DMADEVICES=y
-CONFIG_SH_DMAE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=y
-CONFIG_NLS_CODEPAGE_775=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_855=y
-CONFIG_NLS_CODEPAGE_857=y
-CONFIG_NLS_CODEPAGE_860=y
-CONFIG_NLS_CODEPAGE_861=y
-CONFIG_NLS_CODEPAGE_862=y
-CONFIG_NLS_CODEPAGE_863=y
-CONFIG_NLS_CODEPAGE_864=y
-CONFIG_NLS_CODEPAGE_865=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-CONFIG_NLS_ISO8859_4=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_ISO8859_6=y
-CONFIG_NLS_ISO8859_7=y
-CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_KOI8_U=y
-CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
deleted file mode 100644
index dd18c9e527d6..000000000000
--- a/arch/arm/configs/msm_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ARCH_MSM=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_CLEANCACHE=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_CFG80211=y
-CONFIG_RFKILL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_SLIP=y
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-# CONFIG_USB_NET_ZAURUS is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_THERMAL=y
-CONFIG_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_FB=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_ACM=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_RTC_CLASS=y
-CONFIG_STAGING=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT4_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_CIFS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOCKUP_DETECTOR=y
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_TIMER_STATS=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 9d56781a8f80..f69a459f4f92 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -13,7 +13,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_KIRKWOOD=y
 CONFIG_MACH_NETXBIG=y
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_IMX25_DT=y
+CONFIG_SOC_IMX25=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_ARCH_U300=y
 CONFIG_PCI_MVEBU=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 06075b6d2463..ab86655c1f4b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -12,10 +12,12 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_VIRT=y
+CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
 CONFIG_MACH_ARMADA_38X=y
+CONFIG_MACH_ARMADA_39X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
@@ -91,6 +93,7 @@ CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_TRUSTED_FOUNDATIONS=y
 CONFIG_PCI=y
+CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_KEYSTONE=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
@@ -133,6 +136,9 @@ CONFIG_CAN_BCM=y
 CONFIG_CAN_DEV=y
 CONFIG_CAN_XILINXCAN=y
 CONFIG_CAN_MCP251X=y
+CONFIG_BT=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
 CONFIG_RFKILL=y
@@ -200,6 +206,8 @@ CONFIG_USB_NET_SMSC95XX=y
 CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=m
 CONFIG_RT2800USB=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
@@ -208,6 +216,7 @@ CONFIG_KEYBOARD_SPEAR=y
 CONFIG_KEYBOARD_ST_KEYSCAN=y
 CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_ELAN_I2C=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=y
 CONFIG_TOUCHSCREEN_ST1232=m
@@ -308,6 +317,7 @@ CONFIG_BATTERY_SBS=y
 CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
 CONFIG_POWER_RESET_KEYSTONE=y
 CONFIG_POWER_RESET_SUN6I=y
 CONFIG_POWER_RESET_RMOBILE=y
@@ -505,7 +515,6 @@ CONFIG_DW_DMAC=y
 CONFIG_MV_XOR=y
 CONFIG_TEGRA20_APB_DMA=y
 CONFIG_SH_DMAE=y
-CONFIG_RCAR_AUDMAC_PP=m
 CONFIG_RCAR_DMAC=y
 CONFIG_STE_DMA40=y
 CONFIG_SIRF_DMA=y
@@ -533,6 +542,8 @@ CONFIG_MSM_MMCC_8960=y
 CONFIG_MSM_MMCC_8974=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_ARM_TEGRA_DEVFREQ=m
 CONFIG_MEMORY=y
 CONFIG_TI_AEMIF=y
 CONFIG_IIO=y
@@ -550,6 +561,7 @@ CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_STIH41X_USB=y
 CONFIG_PHY_STIH407_USB=y
 CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN9I_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 73673e95f23c..cacc9f4055a7 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -5,6 +5,7 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -12,6 +13,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
 CONFIG_MACH_ARMADA_38X=y
+CONFIG_MACH_ARMADA_39X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_PCI=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index c7906c2fd645..b47e7c6628c9 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -149,6 +149,7 @@ CONFIG_EXT4_FS=y
 CONFIG_FSCACHE=m
 CONFIG_FSCACHE_STATS=y
 CONFIG_CACHEFILES=m
+CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_JFFS2_FS=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index a7dce674f1be..0c8a78734536 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -34,7 +33,6 @@ CONFIG_ARCH_OMAP16XX=y
 CONFIG_MACH_OMAP_INNOVATOR=y
 CONFIG_MACH_OMAP_H2=y
 CONFIG_MACH_OMAP_H3=y
-CONFIG_MACH_OMAP_HTCWIZARD=y
 CONFIG_MACH_HERALD=y
 CONFIG_MACH_OMAP_OSK=y
 CONFIG_MACH_OMAP_PERSEUS2=y
@@ -55,7 +53,6 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="root=1f03 rootfstype=jffs2"
@@ -80,8 +77,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_IPV6=y
 CONFIG_NETFILTER=y
 CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
 CONFIG_BT_RFCOMM=y
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=y
@@ -92,11 +87,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 # CONFIG_PROC_EVENTS is not set
 CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=3
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
@@ -113,11 +104,9 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_TUN=y
 CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_USB_CATC=y
 CONFIG_USB_KAWETH=y
@@ -158,7 +147,6 @@ CONFIG_SPI_OMAP_UWIRE=y
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_OMAP_WATCHDOG=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
@@ -168,7 +156,6 @@ CONFIG_FB_OMAP_LCDC_EXTERNAL=y
 CONFIG_FB_OMAP_LCDC_HWA742=y
 CONFIG_FB_OMAP_MANUAL_UPDATE=y
 CONFIG_FB_OMAP_LCD_MIPID=y
-CONFIG_FB_OMAP_BOOTLOADER_INIT=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -194,7 +181,6 @@ CONFIG_SND_OMAP_SOC=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_PHY=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
@@ -261,9 +247,7 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_ECB=y
 CONFIG_CRYPTO_PCBC=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 8e108599e1af..9ff7b54b2a83 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -1,3 +1,4 @@
+CONFIG_KERNEL_LZMA=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_FHANDLE=y
@@ -86,17 +87,33 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_LRO is not set
 CONFIG_NETFILTER=y
+CONFIG_PHONET=m
 CONFIG_CAN=m
 CONFIG_CAN_C_CAN=m
 CONFIG_CAN_C_CAN_PLATFORM=m
 CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
 CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_H4=y
 CONFIG_BT_HCIUART_BCSP=y
 CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
 CONFIG_BT_HCIBCM203X=m
 CONFIG_BT_HCIBPA10X=m
 CONFIG_CFG80211=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_AF_RXRPC=m
+CONFIG_RXKAD=m
 CONFIG_MAC80211=m
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -163,6 +180,7 @@ CONFIG_USB_EPSON2888=y
 CONFIG_USB_EHCI_HCD=m
 CONFIG_USB_OHCI_HCD=m
 CONFIG_USB_KC2190=y
+CONFIG_USB_CDC_PHONET=m
 CONFIG_LIBERTAS=m
 CONFIG_LIBERTAS_USB=m
 CONFIG_LIBERTAS_SDIO=m
@@ -209,6 +227,10 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_TI_QSPI=m
+CONFIG_HSI=m
+CONFIG_OMAP_SSI=m
+CONFIG_NOKIA_MODEM=m
+CONFIG_SSI_PROTOCOL=m
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
@@ -334,6 +356,7 @@ CONFIG_USB_CONFIGFS_ECM=y
 CONFIG_USB_CONFIGFS_ECM_SUBSET=y
 CONFIG_USB_CONFIGFS_RNDIS=y
 CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_PHONET=y
 CONFIG_USB_CONFIGFS_MASS_STORAGE=y
 CONFIG_USB_CONFIGFS_F_LB_SS=y
 CONFIG_USB_CONFIGFS_F_FS=y
@@ -342,6 +365,7 @@ CONFIG_USB_CONFIGFS_F_UAC2=y
 CONFIG_USB_CONFIGFS_F_MIDI=y
 CONFIG_USB_CONFIGFS_F_HID=y
 CONFIG_USB_ZERO=m
+CONFIG_USB_G_NOKIA=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=y
 CONFIG_MMC_OMAP=y
@@ -349,6 +373,7 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_PWM=m
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_ONESHOT=m
@@ -368,6 +393,7 @@ CONFIG_TI_EDMA=y
 CONFIG_DMA_OMAP=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXTCON=m
+CONFIG_EXTCON_GPIO=m
 CONFIG_EXTCON_PALMAS=m
 CONFIG_TI_EMIF=m
 CONFIG_PWM=y
@@ -390,6 +416,7 @@ CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_SUMMARY=y
 CONFIG_JFFS2_FS_XATTR=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 8c7da3319d82..d2f2babfd47a 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -97,9 +97,9 @@ CONFIG_PINCTRL_APQ8084=y
 CONFIG_PINCTRL_IPQ8064=y
 CONFIG_PINCTRL_MSM8960=y
 CONFIG_PINCTRL_MSM8X74=y
+CONFIG_GPIOLIB=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_MSM=y
 CONFIG_THERMAL=y
@@ -125,7 +125,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
 CONFIG_USB_GADGET_VBUS_DRAW=500
 CONFIG_MMC=y
-CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
@@ -134,14 +134,15 @@ CONFIG_RTC_CLASS=y
 CONFIG_DMADEVICES=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_STAGING=y
-CONFIG_QCOM_GSBI=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_APQ_MMCC_8084=y
-CONFIG_IPQ_GCC_806X=y
+CONFIG_IPQ_LCC_806X=y
 CONFIG_MSM_GCC_8660=y
+CONFIG_MSM_LCC_8960=y
 CONFIG_MSM_MMCC_8960=y
 CONFIG_MSM_MMCC_8974=y
 CONFIG_MSM_IOMMU=y
+CONFIG_QCOM_GSBI=y
 CONFIG_PHY_QCOM_APQ8064_SATA=y
 CONFIG_PHY_QCOM_IPQ806X_SATA=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index b17036088726..b58618e2d13c 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -12,7 +12,9 @@ CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R7S72100=y
+CONFIG_ARCH_R8A73A4=y
 CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7778=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
@@ -92,7 +94,6 @@ CONFIG_INPUT_ADXL34X=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_EM=y
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
@@ -109,6 +110,9 @@ CONFIG_SPI_SH_HSPI=y
 CONFIG_GPIO_EM=y
 CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_PCF857X=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_RMOBILE=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
@@ -121,6 +125,7 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_AS3711=y
 CONFIG_REGULATOR_DA9210=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8973=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_CONTROLLER=y
@@ -133,6 +138,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_RENESAS_VSP1=y
 # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
 CONFIG_VIDEO_ADV7180=y
+CONFIG_VIDEO_ML86V7667=y
 CONFIG_DRM=y
 CONFIG_DRM_RCAR_DU=y
 CONFIG_FB_SH_MOBILE_LCDC=y
@@ -167,6 +173,7 @@ CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RS5C372=y
 CONFIG_RTC_DRV_S35390A=y
+CONFIG_RTC_DRV_RX8581=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_RCAR_DMAC=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 8f6a5702b696..8ecba00dcd83 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -107,6 +107,7 @@ CONFIG_RTC_DRV_SUN6I=y
 CONFIG_RTC_DRV_SUNXI=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN9I_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
diff --git a/arch/arm/include/asm/arm-cci.h b/arch/arm/include/asm/arm-cci.h
new file mode 100644
index 000000000000..fe77f7ab7e6b
--- /dev/null
+++ b/arch/arm/include/asm/arm-cci.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/include/asm/arm-cci.h
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ARM_CCI_H
+#define __ASM_ARM_CCI_H
+#ifdef CONFIG_MCPM
+#include <asm/mcpm.h>
+/*
+ * We don't have a reliable way of detecting whether,
+ * if we have access to secure-only registers, unless
+ * mcpm is registered.
+ */
+static inline bool platform_has_secure_cci_access(void)
+{
+        return mcpm_is_available();
+}
+#else
+static inline bool platform_has_secure_cci_access(void)
+{
+        return false;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index 3446f6a1d9fa..50b378f59e08 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -171,12 +171,73 @@ void mcpm_cpu_suspend(u64 expected_residency);
 int mcpm_cpu_powered_up(void);
 /*
- * Platform specific methods used in the implementation of the above API.
+ * Platform specific callbacks used in the implementation of the above API.
+ *
+ * cpu_powerup:
+ * Make given CPU runable. Called with MCPM lock held and IRQs disabled.
+ * The given cluster is assumed to be set up (cluster_powerup would have
+ * been called beforehand). Must return 0 for success or negative error code.
+ *
+ * cluster_powerup:
+ * Set up power for given cluster. Called with MCPM lock held and IRQs
+ * disabled. Called before first cpu_powerup when cluster is down. Must
+ * return 0 for success or negative error code.
+ *
+ * cpu_suspend_prepare:
+ * Special suspend configuration. Called on target CPU with MCPM lock held
+ * and IRQs disabled. This callback is optional. If provided, it is called
+ * before cpu_powerdown_prepare.
+ *
+ * cpu_powerdown_prepare:
+ * Configure given CPU for power down. Called on target CPU with MCPM lock
+ * held and IRQs disabled. Power down must be effective only at the next WFI instruction.
+ *
+ * cluster_powerdown_prepare:
+ * Configure given cluster for power down. Called on one CPU from target
+ * cluster with MCPM lock held and IRQs disabled. A cpu_powerdown_prepare
+ * for each CPU in the cluster has happened when this occurs.
+ *
+ * cpu_cache_disable:
+ * Clean and disable CPU level cache for the calling CPU. Called on with IRQs
+ * disabled only. The CPU is no longer cache coherent with the rest of the
+ * system when this returns.
+ *
+ * cluster_cache_disable:
+ * Clean and disable the cluster wide cache as well as the CPU level cache
+ * for the calling CPU. No call to cpu_cache_disable will happen for this
+ * CPU. Called with IRQs disabled and only when all the other CPUs are done
+ * with their own cpu_cache_disable. The cluster is no longer cache coherent
+ * with the rest of the system when this returns.
+ *
+ * cpu_is_up:
+ * Called on given CPU after it has been powered up or resumed. The MCPM lock
+ * is held and IRQs disabled. This callback is optional.
+ *
+ * cluster_is_up:
+ * Called by the first CPU to be powered up or resumed in given cluster.
+ * The MCPM lock is held and IRQs disabled. This callback is optional. If
+ * provided, it is called before cpu_is_up for that CPU.
+ *
+ * wait_for_powerdown:
+ * Wait until given CPU is powered down. This is called in sleeping context.
+ * Some reasonable timeout must be considered. Must return 0 for success or
+ * negative error code.
 */
 struct mcpm_platform_ops {
+        int (*cpu_powerup)(unsigned int cpu, unsigned int cluster);
+        int (*cluster_powerup)(unsigned int cluster);
+        void (*cpu_suspend_prepare)(unsigned int cpu, unsigned int cluster);
+        void (*cpu_powerdown_prepare)(unsigned int cpu, unsigned int cluster);
+        void (*cluster_powerdown_prepare)(unsigned int cluster);
+        void (*cpu_cache_disable)(void);
+        void (*cluster_cache_disable)(void);
+        void (*cpu_is_up)(unsigned int cpu, unsigned int cluster);
+        void (*cluster_is_up)(unsigned int cluster);
+        int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
+        /* deprecated callbacks */
        int (*power_up)(unsigned int cpu, unsigned int cluster);
        void (*power_down)(void);
-        int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
        void (*suspend)(u64);
        void (*powered_up)(void);
 };
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
index e55a9426b496..b03024fa671f 100644
--- a/arch/arm/include/debug/msm.S
+++ b/arch/arm/include/debug/msm.S
@@ -16,24 +16,17 @@
 */
        .macro  addruart, rp, rv, tmp
-#ifdef CONFIG_DEBUG_UART_PHYS
        ldr     \rp, =CONFIG_DEBUG_UART_PHYS
        ldr     \rv, =CONFIG_DEBUG_UART_VIRT
-#endif
        .endm
        .macro  senduart, rd, rx
 ARM_BE8(rev     \rd, \rd )
-#ifdef CONFIG_DEBUG_QCOM_UARTDM
        @ Write the 1 character to UARTDM_TF
        str     \rd, [\rx, #0x70]
-#else
-        str     \rd, [\rx, #0x0C]
-#endif
        .endm
        .macro  waituart, rd, rx
-#ifdef CONFIG_DEBUG_QCOM_UARTDM
        @ check for TX_EMT in UARTDM_SR
        ldr     \rd, [\rx, #0x08]
 ARM_BE8(rev     \rd, \rd )
@@ -55,13 +48,6 @@ ARM_BE8(rev     \rd, \rd )
        str     \rd, [\rx, #0x40]
        @ UARTDM reg. Read to induce delay
        ldr     \rd, [\rx, #0x08]
-#else
-        @ wait for TX_READY
-1001:   ldr     \rd, [\rx, #0x08]
-ARM_BE8(rev     \rd, \rd )
-        tst     \rd, #0x04
-        beq     1001b
-#endif
        .endm
        .macro  busyuart, rd, rx
diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig
new file mode 100644
index 000000000000..2c44b930505a
--- /dev/null
+++ b/arch/arm/mach-alpine/Kconfig
@@ -0,0 +1,12 @@
+config ARCH_ALPINE
+        bool "Annapurna Labs Alpine platform" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select GENERIC_IRQ_CHIP
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_SMP
+        select MFD_SYSCON
+        select PCI
+        select PCI_HOST_GENERIC
+        help
+          This enables support for the Annapurna Labs Alpine V1 boards.
diff --git a/arch/arm/mach-alpine/Makefile b/arch/arm/mach-alpine/Makefile
new file mode 100644
index 000000000000..b6674890be71
--- /dev/null
+++ b/arch/arm/mach-alpine/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += alpine_machine.o
+obj-$(CONFIG_SMP)               += platsmp.o alpine_cpu_pm.o
diff --git a/arch/arm/mach-alpine/alpine_cpu_pm.c b/arch/arm/mach-alpine/alpine_cpu_pm.c
new file mode 100644
index 000000000000..121c77c4b53c
--- /dev/null
+++ b/arch/arm/mach-alpine/alpine_cpu_pm.c
@@ -0,0 +1,70 @@
+/*
+ * Low-level power-management support for Alpine platform.
+ *
+ * Copyright (C) 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include "alpine_cpu_pm.h"
+#include "alpine_cpu_resume.h"
+/* NB registers */
+#define AL_SYSFAB_POWER_CONTROL(cpu)    (0x2000 + (cpu)*0x100 + 0x20)
+static struct regmap *al_sysfabric;
+static struct al_cpu_resume_regs __iomem *al_cpu_resume_regs;
+static int wakeup_supported;
+int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr)
+{
+        if (!wakeup_supported)
+                return -ENOSYS;
+        /*
+         * Set CPU resume address -
+         * secure firmware running on boot will jump to this address
+         * after setting proper CPU mode, and initialiing e.g. secure
+         * regs (the same mode all CPUs are booted to - usually HYP)
+         */
+        writel(phys_resume_addr,
+               &al_cpu_resume_regs->per_cpu[phys_cpu].resume_addr);
+        /* Power-up the CPU */
+        regmap_write(al_sysfabric, AL_SYSFAB_POWER_CONTROL(phys_cpu), 0);
+        return 0;
+}
+void __init alpine_cpu_pm_init(void)
+{
+        struct device_node *np;
+        uint32_t watermark;
+        al_sysfabric = syscon_regmap_lookup_by_compatible("al,alpine-sysfabric-service");
+        np = of_find_compatible_node(NULL, NULL, "al,alpine-cpu-resume");
+        al_cpu_resume_regs = of_iomap(np, 0);
+        wakeup_supported = !IS_ERR(al_sysfabric) && al_cpu_resume_regs;
+        if (wakeup_supported) {
+                watermark = readl(&al_cpu_resume_regs->watermark);
+                wakeup_supported = (watermark & AL_CPU_RESUME_MAGIC_NUM_MASK)
+                                    == AL_CPU_RESUME_MAGIC_NUM;
+        }
+}
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-alpine/alpine_cpu_pm.h
index 2d9ca0455745..5179e697c492 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-alpine/alpine_cpu_pm.h
@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-at91/include/mach/io.h
+ * Low-level power-management support for Alpine platform.
 *
- *  Copyright (C) 2003 SAN People
+ * Copyright (C) 2015 Annapurna Labs Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -12,16 +12,15 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_IO_H
+#ifndef __ALPINE_CPU_PM_H__
-#define __ASM_ARCH_IO_H
+#define __ALPINE_CPU_PM_H__
+/* Alpine CPU Power Management Services Initialization */
+void alpine_cpu_pm_init(void);
-#define IO_SPACE_LIMIT          0xFFFFFFFF
+/* Wake-up a CPU */
-#define __io(a)                 __typesafe_io(a)
+int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr);
-#endif
+#endif /* __ALPINE_CPU_PM_H__ */
diff --git a/arch/arm/mach-alpine/alpine_cpu_resume.h b/arch/arm/mach-alpine/alpine_cpu_resume.h
new file mode 100644
index 000000000000..c80150c0d2d8
--- /dev/null
+++ b/arch/arm/mach-alpine/alpine_cpu_resume.h
@@ -0,0 +1,38 @@
+/*
+ * Annapurna labs cpu-resume register structure.
+ *
+ * Copyright (C) 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef ALPINE_CPU_RESUME_H_
+#define ALPINE_CPU_RESUME_H_
+/* Per-cpu regs */
+struct al_cpu_resume_regs_per_cpu {
+        uint32_t        flags;
+        uint32_t        resume_addr;
+};
+/* general regs */
+struct al_cpu_resume_regs {
+        /* Watermark for validating the CPU resume struct */
+        uint32_t watermark;
+        uint32_t flags;
+        struct al_cpu_resume_regs_per_cpu per_cpu[];
+};
+/* The expected magic number for validating the resume addresses */
+#define AL_CPU_RESUME_MAGIC_NUM         0xf0e1d200
+#define AL_CPU_RESUME_MAGIC_NUM_MASK    0xffffff00
+#endif /* ALPINE_CPU_RESUME_H_ */
diff --git a/arch/arm/mach-alpine/alpine_machine.c b/arch/arm/mach-alpine/alpine_machine.c
new file mode 100644
index 000000000000..b8e2145e962b
--- /dev/null
+++ b/arch/arm/mach-alpine/alpine_machine.c
@@ -0,0 +1,28 @@
+/*
+ * Machine declaration for Alpine platforms.
+ *
+ * Copyright (C) 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+static const char * const al_match[] __initconst = {
+        "al,alpine",
+        NULL,
+};
+DT_MACHINE_START(AL_DT, "Annapurna Labs Alpine")
+        .dt_compat      = al_match,
+MACHINE_END
diff --git a/arch/arm/mach-alpine/platsmp.c b/arch/arm/mach-alpine/platsmp.c
new file mode 100644
index 000000000000..f78429f48bd6
--- /dev/null
+++ b/arch/arm/mach-alpine/platsmp.c
@@ -0,0 +1,49 @@
+/*
+ * SMP operations for Alpine platform.
+ *
+ * Copyright (C) 2015 Annapurna Labs Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <asm/smp_plat.h>
+#include "alpine_cpu_pm.h"
+static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        phys_addr_t addr;
+        addr = virt_to_phys(secondary_startup);
+        if (addr > (phys_addr_t)(uint32_t)(-1)) {
+                pr_err("FAIL: resume address over 32bit (%pa)", &addr);
+                return -EINVAL;
+        }
+        return alpine_cpu_wakeup(cpu_logical_map(cpu), (uint32_t)addr);
+}
+static void __init alpine_smp_prepare_cpus(unsigned int max_cpus)
+{
+        alpine_cpu_pm_init();
+}
+static struct smp_operations alpine_smp_ops __initdata = {
+        .smp_prepare_cpus       = alpine_smp_prepare_cpus,
+        .smp_boot_secondary     = alpine_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(alpine_smp, "al,alpine-smp", &alpine_smp_ops);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c74a44324e5b..fd95f34945f4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,55 +1,15 @@
-if ARCH_AT91
+menuconfig ARCH_AT91
+        bool "Atmel SoCs"
-config HAVE_AT91_UTMI
+        depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
-        bool
+        select ARCH_REQUIRE_GPIOLIB
-config HAVE_AT91_USB_CLK
-        bool
-config COMMON_CLK_AT91
-        bool
-        select COMMON_CLK
-config HAVE_AT91_SMD
-        bool
-config HAVE_AT91_H32MX
-        bool
-config SOC_SAMA5
-        bool
-        select ATMEL_AIC5_IRQ
        select COMMON_CLK_AT91
-        select CPU_V7
+        select PINCTRL
-        select GENERIC_CLOCKEVENTS
+        select PINCTRL_AT91
-        select MEMORY
+        select SOC_BUS
-        select ATMEL_SDRAMC
-        select PHYLIB if NETDEVICES
-menu "Atmel AT91 System-on-Chip"
-choice
-        prompt "Core type"
-config SOC_SAM_V4_V5
-        bool "ARM9 AT91SAM9/AT91RM9200"
-        help
-          Select this if you are using one of Atmel's AT91SAM9 or
-          AT91RM9200 SoC.
-config SOC_SAM_V7
-        bool "Cortex A5"
-        help
-          Select this if you are using one of Atmel's SAMA5D3 SoC.
-endchoice
-comment "Atmel AT91 Processor"
+if ARCH_AT91
-if SOC_SAM_V7
 config SOC_SAMA5D3
-        bool "SAMA5D3 family"
+        bool "SAMA5D3 family" if ARCH_MULTI_V7
        select SOC_SAMA5
        select HAVE_FB_ATMEL
        select HAVE_AT91_UTMI
@@ -60,9 +20,8 @@ config SOC_SAMA5D3
          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
 config SOC_SAMA5D4
-        bool "SAMA5D4 family"
+        bool "SAMA5D4 family" if ARCH_MULTI_V7
        select SOC_SAMA5
-        select CLKSRC_MMIO
        select CACHE_L2X0
        select HAVE_FB_ATMEL
        select HAVE_AT91_UTMI
@@ -71,29 +30,31 @@ config SOC_SAMA5D4
        select HAVE_AT91_H32MX
        help
          Select this if you are using one of Atmel's SAMA5D4 family SoC.
-endif
-if SOC_SAM_V4_V5
 config SOC_AT91RM9200
-        bool "AT91RM9200"
+        bool "AT91RM9200" if ARCH_MULTI_V4T
        select ATMEL_AIC_IRQ
-        select COMMON_CLK_AT91
+        select ATMEL_ST
        select CPU_ARM920T
-        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_USB_CLK
+        select MIGHT_HAVE_PCI
+        select SOC_SAM_V4_V5
+        select SRAM if PM
+        help
+          Select this if you are using Atmel's AT91RM9200 SoC.
 config SOC_AT91SAM9
-        bool "AT91SAM9"
+        bool "AT91SAM9" if ARCH_MULTI_V5
        select ATMEL_AIC_IRQ
        select ATMEL_SDRAMC
-        select COMMON_CLK_AT91
        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_SMD
        select HAVE_AT91_USB_CLK
        select HAVE_AT91_UTMI
        select HAVE_FB_ATMEL
        select MEMORY
+        select SOC_SAM_V4_V5
+        select SRAM if PM
        help
          Select this if you are using one of those Atmel SoC:
            AT91SAM9260
@@ -112,40 +73,35 @@ config SOC_AT91SAM9
            AT91SAM9X25
            AT91SAM9X35
            AT91SAM9XE
-endif # SOC_SAM_V4_V5
-comment "AT91 Feature Selections"
+config HAVE_AT91_UTMI
+        bool
-config AT91_SLOW_CLOCK
+config HAVE_AT91_USB_CLK
-        bool "Suspend-to-RAM disables main oscillator"
+        bool
-        select SRAM
-        depends on SUSPEND
-        help
-          Select this if you want Suspend-to-RAM to save the most power
-          possible (without powering off the CPU) by disabling the PLLs
-          and main oscillator so that only the 32 KiHz clock is available.
-          When only that slow-clock is available, some peripherals lose
+config COMMON_CLK_AT91
-          functionality.  Many can't issue wakeup events unless faster
+        bool
-          clocks are available.  Some lose their operating state and
+        select COMMON_CLK
-          need to be completely re-initialized.
-config AT91_TIMER_HZ
+config HAVE_AT91_SMD
-       int "Kernel HZ (jiffies per second)"
+        bool
-       range 32 1024
-       depends on ARCH_AT91
+config HAVE_AT91_H32MX
-       default "128" if SOC_AT91RM9200
+        bool
-       default "100"
-       help
-          On AT91rm9200 chips where you're using a system clock derived
-          from the 32768 Hz hardware clock, this tick rate should divide
-          it exactly: use a power-of-two value, such as 128 or 256, to
-          reduce timing errors caused by rounding.
-          On AT91sam926x chips, or otherwise when using a higher precision
+config SOC_SAM_V4_V5
-          system clock (of at least several MHz), rounding is less of a
+        bool
-          problem so it can be safer to use a decimal values like 100.
-endmenu
+config SOC_SAM_V7
+        bool
+config SOC_SAMA5
+        bool
+        select ATMEL_AIC5_IRQ
+        select ATMEL_SDRAMC
+        select MEMORY
+        select SOC_SAM_V7
+        select SRAM if PM
 endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 827fdbcce1c7..4fa8b4541e64 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,20 +1,25 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-obj-y           := setup.o
+obj-y           := soc.o
 obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 # CPU-specific support
-obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o at91rm9200_time.o
+obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o
 obj-$(CONFIG_SOC_AT91SAM9)      += at91sam9.o
 obj-$(CONFIG_SOC_SAMA5)         += sama5.o
 # Power Management
 obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_AT91_SLOW_CLOCK)   += pm_slowclock.o
+obj-$(CONFIG_PM)                += pm_suspend.o
+ifeq ($(CONFIG_CPU_V7),y)
+AFLAGS_pm_suspend.o := -march=armv7-a
+endif
 ifeq ($(CONFIG_PM_DEBUG),y)
 CFLAGS_pm.o += -DDEBUG
 endif
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 8fcfb70f7124..eaf58f88ef5d 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -8,60 +8,42 @@
 * Licensed under GPLv2 or later.
 */
-#include <linux/types.h>
+#include <linux/clk-provider.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/clk-provider.h>
-#include <asm/setup.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
 #include <asm/system_misc.h>
-#include <mach/at91_st.h>
 #include "generic.h"
+#include "soc.h"
-static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
+static const struct at91_soc rm9200_socs[] = {
-{
+        AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
-        /*
+        { /* sentinel */ },
-         * Perform a hardware reset with the use of the Watchdog timer.
+};
-         */
-        at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
-}
-static void __init at91rm9200_dt_timer_init(void)
-{
-        of_clk_init(NULL);
-        at91rm9200_timer_init();
-}
 static void __init at91rm9200_dt_device_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        struct soc_device *soc;
+        struct device *soc_dev = NULL;
+        soc = at91_soc_init(rm9200_socs);
+        if (soc != NULL)
+                soc_dev = soc_device_to_device(soc);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
        arm_pm_idle = at91rm9200_idle;
-        arm_pm_restart = at91rm9200_restart;
        at91rm9200_pm_init();
 }
 static const char *at91rm9200_dt_board_compat[] __initconst = {
        "atmel,at91rm9200",
        NULL
 };
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
-        .init_time      = at91rm9200_dt_timer_init,
-        .map_io         = at91_map_io,
        .init_machine   = at91rm9200_dt_device_init,
        .dt_compat      = at91rm9200_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
deleted file mode 100644
index b00d09555f2b..000000000000
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/at91rm9200_time.c
- *
- *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2003 ATMEL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/export.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/mach/time.h>
-#include <mach/at91_st.h>
-#include <mach/hardware.h>
-static unsigned long last_crtr;
-static u32 irqmask;
-static struct clock_event_device clkevt;
-#define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
-/*
- * The ST_CRTR is updated asynchronously to the master clock ... but
- * the updates as seen by the CPU don't seem to be strictly monotonic.
- * Waiting until we read the same value twice avoids glitching.
- */
-static inline unsigned long read_CRTR(void)
-{
-        unsigned long x1, x2;
-        x1 = at91_st_read(AT91_ST_CRTR);
-        do {
-                x2 = at91_st_read(AT91_ST_CRTR);
-                if (x1 == x2)
-                        break;
-                x1 = x2;
-        } while (1);
-        return x1;
-}
-/*
- * IRQ handler for the timer.
- */
-static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
-{
-        u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
-        /*
-         * irqs should be disabled here, but as the irq is shared they are only
-         * guaranteed to be off if the timer irq is registered first.
-         */
-        WARN_ON_ONCE(!irqs_disabled());
-        /* simulate "oneshot" timer with alarm */
-        if (sr & AT91_ST_ALMS) {
-                clkevt.event_handler(&clkevt);
-                return IRQ_HANDLED;
-        }
-        /* periodic mode should handle delayed ticks */
-        if (sr & AT91_ST_PITS) {
-                u32     crtr = read_CRTR();
-                while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
-                        last_crtr += RM9200_TIMER_LATCH;
-                        clkevt.event_handler(&clkevt);
-                }
-                return IRQ_HANDLED;
-        }
-        /* this irq is shared ... */
-        return IRQ_NONE;
-}
-static struct irqaction at91rm9200_timer_irq = {
-        .name           = "at91_tick",
-        .flags          = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91rm9200_timer_interrupt,
-        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
-};
-static cycle_t read_clk32k(struct clocksource *cs)
-{
-        return read_CRTR();
-}
-static struct clocksource clk32k = {
-        .name           = "32k_counter",
-        .rating         = 150,
-        .read           = read_clk32k,
-        .mask           = CLOCKSOURCE_MASK(20),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-static void
-clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
-{
-        /* Disable and flush pending timer interrupts */
-        at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-        at91_st_read(AT91_ST_SR);
-        last_crtr = read_CRTR();
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* PIT for periodic irqs; fixed rate of 1/HZ */
-                irqmask = AT91_ST_PITS;
-                at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* ALM for oneshot irqs, set by next_event()
-                 * before 32 seconds have passed
-                 */
-                irqmask = AT91_ST_ALMS;
-                at91_st_write(AT91_ST_RTAR, last_crtr);
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                irqmask = 0;
-                break;
-        }
-        at91_st_write(AT91_ST_IER, irqmask);
-}
-static int
-clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
-{
-        u32             alm;
-        int             status = 0;
-        BUG_ON(delta < 2);
-        /* The alarm IRQ uses absolute time (now+delta), not the relative
-         * time (delta) in our calling convention.  Like all clockevents
-         * using such "match" hardware, we have a race to defend against.
-         *
-         * Our defense here is to have set up the clockevent device so the
-         * delta is at least two.  That way we never end up writing RTAR
-         * with the value then held in CRTR ... which would mean the match
-         * wouldn't trigger until 32 seconds later, after CRTR wraps.
-         */
-        alm = read_CRTR();
-        /* Cancel any pending alarm; flush any pending IRQ */
-        at91_st_write(AT91_ST_RTAR, alm);
-        at91_st_read(AT91_ST_SR);
-        /* Schedule alarm by writing RTAR. */
-        alm += delta;
-        at91_st_write(AT91_ST_RTAR, alm);
-        return status;
-}
-static struct clock_event_device clkevt = {
-        .name           = "at91_tick",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 150,
-        .set_next_event = clkevt32k_next_event,
-        .set_mode       = clkevt32k_mode,
-};
-void __iomem *at91_st_base;
-EXPORT_SYMBOL_GPL(at91_st_base);
-static const struct of_device_id at91rm9200_st_timer_ids[] = {
-        { .compatible = "atmel,at91rm9200-st" },
-        { /* sentinel */ }
-};
-static int __init of_at91rm9200_st_init(void)
-{
-        struct device_node *np;
-        int ret;
-        np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
-        if (!np)
-                goto err;
-        at91_st_base = of_iomap(np, 0);
-        if (!at91_st_base)
-                goto node_err;
-        /* Get the interrupts property */
-        ret = irq_of_parse_and_map(np, 0);
-        if (!ret)
-                goto ioremap_err;
-        at91rm9200_timer_irq.irq = ret;
-        of_node_put(np);
-        return 0;
-ioremap_err:
-        iounmap(at91_st_base);
-node_err:
-        of_node_put(np);
-err:
-        return -EINVAL;
-}
-/*
- * ST (system timer) module supports both clockevents and clocksource.
- */
-void __init at91rm9200_timer_init(void)
-{
-        /* For device tree enabled device: initialize here */
-        of_at91rm9200_st_init();
-        /* Disable all timer interrupts, and clear any pending ones */
-        at91_st_write(AT91_ST_IDR,
-                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-        at91_st_read(AT91_ST_SR);
-        /* Make IRQs happen for the system timer */
-        setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
-        /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
-         * directly for the clocksource and all clockevents, after adjusting
-         * its prescaler from the 1 Hz default.
-         */
-        at91_st_write(AT91_ST_RTMR, 1);
-        /* Setup timer clockevent, with minimum of two ticks (important!!) */
-        clkevt.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
-                                        2, AT91_ST_ALMV);
-        /* register clocksource */
-        clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
-}
diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c
index 56e3ba73ec40..e47a2093a0e7 100644
--- a/arch/arm/mach-at91/at91sam9.c
+++ b/arch/arm/mach-at91/at91sam9.c
@@ -7,29 +7,68 @@
 * Licensed under GPLv2 or later.
 */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/clk-provider.h>
-#include <asm/system_misc.h>
-#include <asm/setup.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
+#include <asm/system_misc.h>
-#include <asm/mach/irq.h>
 #include "generic.h"
+#include "soc.h"
-static void __init at91sam9_dt_device_init(void)
+static const struct at91_soc at91sam9_socs[] = {
+        AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
+        AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
+        AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
+        AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
+        AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
+        AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
+                 "at91sam9m11", "at91sam9g45"),
+        AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
+                 "at91sam9m10", "at91sam9g45"),
+        AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
+                 "at91sam9g46", "at91sam9g45"),
+        AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
+                 "at91sam9g45", "at91sam9g45"),
+        AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
+                 "at91sam9g15", "at91sam9x5"),
+        AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
+                 "at91sam9g35", "at91sam9x5"),
+        AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
+                 "at91sam9x35", "at91sam9x5"),
+        AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
+                 "at91sam9g25", "at91sam9x5"),
+        AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
+                 "at91sam9x25", "at91sam9x5"),
+        AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
+                 "at91sam9cn12", "at91sam9n12"),
+        AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
+                 "at91sam9n12", "at91sam9n12"),
+        AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
+                 "at91sam9cn11", "at91sam9n12"),
+        AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
+        AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
+        AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
+        { /* sentinel */ },
+};
+static void __init at91sam9_common_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        struct soc_device *soc;
+        struct device *soc_dev = NULL;
+        soc = at91_soc_init(at91sam9_socs);
+        if (soc != NULL)
+                soc_dev = soc_device_to_device(soc);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
        arm_pm_idle = at91sam9_idle;
+}
+static void __init at91sam9_dt_device_init(void)
+{
+        at91sam9_common_init();
        at91sam9260_pm_init();
 }
@@ -40,16 +79,13 @@ static const char *at91_dt_board_compat[] __initconst = {
 DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
        /* Maintainer: Atmel */
-        .map_io         = at91_map_io,
        .init_machine   = at91sam9_dt_device_init,
        .dt_compat      = at91_dt_board_compat,
 MACHINE_END
 static void __init at91sam9g45_dt_device_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        at91sam9_common_init();
-        arm_pm_idle = at91sam9_idle;
        at91sam9g45_pm_init();
 }
@@ -60,16 +96,13 @@ static const char *at91sam9g45_board_compat[] __initconst = {
 DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
        /* Maintainer: Atmel */
-        .map_io         = at91_map_io,
        .init_machine   = at91sam9g45_dt_device_init,
        .dt_compat      = at91sam9g45_board_compat,
 MACHINE_END
 static void __init at91sam9x5_dt_device_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        at91sam9_common_init();
-        arm_pm_idle = at91sam9_idle;
        at91sam9x5_pm_init();
 }
@@ -81,7 +114,6 @@ static const char *at91sam9x5_board_compat[] __initconst = {
 DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
        /* Maintainer: Atmel */
-        .map_io         = at91_map_io,
        .init_machine   = at91sam9x5_dt_device_init,
        .dt_compat      = at91sam9x5_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 583369ffc284..b0fa7dc7286d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -18,17 +18,10 @@
 extern void __init at91_map_io(void);
 extern void __init at91_alt_map_io(void);
- /* Timer */
-extern void at91rm9200_timer_init(void);
 /* idle */
 extern void at91rm9200_idle(void);
 extern void at91sam9_idle(void);
-/* Matrix */
-extern void at91_ioremap_matrix(u32 base_addr);
 #ifdef CONFIG_PM
 extern void __init at91rm9200_pm_init(void);
 extern void __init at91sam9260_pm_init(void);
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
deleted file mode 100644
index 42925e8f78e4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_dbgu.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_DBGU_H
-#define AT91_DBGU_H
-#define AT91_DBGU_CR            (0x00)  /* Control Register */
-#define AT91_DBGU_MR            (0x04)  /* Mode Register */
-#define AT91_DBGU_IER           (0x08)  /* Interrupt Enable Register */
-#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
-#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
-#define AT91_DBGU_IDR           (0x0c)  /* Interrupt Disable Register */
-#define AT91_DBGU_IMR           (0x10)  /* Interrupt Mask Register */
-#define AT91_DBGU_SR            (0x14)  /* Status Register */
-#define AT91_DBGU_RHR           (0x18)  /* Receiver Holding Register */
-#define AT91_DBGU_THR           (0x1c)  /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR          (0x20)  /* Baud Rate Generator Register */
-#define AT91_DBGU_CIDR          (0x40)  /* Chip ID Register */
-#define AT91_DBGU_EXID          (0x44)  /* Chip ID Extension Register */
-#define AT91_DBGU_FNR           (0x48)  /* Force NTRST Register [SAM9 only] */
-#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
-/*
- * Some AT91 parts that don't have full DEBUG units still support the ID
- * and extensions register.
- */
-#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
-#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
-#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
-#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
-#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
-#define                 AT91_CIDR_SRAMSIZ_1K    (1 << 16)
-#define                 AT91_CIDR_SRAMSIZ_2K    (2 << 16)
-#define                 AT91_CIDR_SRAMSIZ_112K  (4 << 16)
-#define                 AT91_CIDR_SRAMSIZ_4K    (5 << 16)
-#define                 AT91_CIDR_SRAMSIZ_80K   (6 << 16)
-#define                 AT91_CIDR_SRAMSIZ_160K  (7 << 16)
-#define                 AT91_CIDR_SRAMSIZ_8K    (8 << 16)
-#define                 AT91_CIDR_SRAMSIZ_16K   (9 << 16)
-#define                 AT91_CIDR_SRAMSIZ_32K   (10 << 16)
-#define                 AT91_CIDR_SRAMSIZ_64K   (11 << 16)
-#define                 AT91_CIDR_SRAMSIZ_128K  (12 << 16)
-#define                 AT91_CIDR_SRAMSIZ_256K  (13 << 16)
-#define                 AT91_CIDR_SRAMSIZ_96K   (14 << 16)
-#define                 AT91_CIDR_SRAMSIZ_512K  (15 << 16)
-#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
-#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
-#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
deleted file mode 100644
index f8996c954131..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_matrix.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2
- */
-#ifndef __MACH_AT91_MATRIX_H__
-#define __MACH_AT91_MATRIX_H__
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_matrix_base;
-#define at91_matrix_read(field) \
-        __raw_readl(at91_matrix_base + field)
-#define at91_matrix_write(field, value) \
-        __raw_writel(value, at91_matrix_base + field)
-#else
-.extern at91_matrix_base
-#endif
-#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index e4492b151fee..493bc486e858 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[];
 .extern at91_ramc_base
 #endif
-#define AT91_MEMCTRL_MC         0
-#define AT91_MEMCTRL_SDRAMC     1
-#define AT91_MEMCTRL_DDRSDR     2
 #include <soc/at91/at91rm9200_sdramc.h>
 #include <soc/at91/at91sam9_ddrsdr.h>
 #include <soc/at91/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
deleted file mode 100644
index 67fdbd13c3ed..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_st.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System Timer (ST) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_ST_H
-#define AT91_ST_H
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_st_base;
-#define at91_st_read(field) \
-        __raw_readl(at91_st_base + field)
-#define at91_st_write(field, value) \
-        __raw_writel(value, at91_st_base + field)
-#else
-.extern at91_st_base
-#endif
-#define AT91_ST_CR              0x00                    /* Control Register */
-#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
-#define AT91_ST_PIMR            0x04                    /* Period Interval Mode Register */
-#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
-#define AT91_ST_WDMR            0x08                    /* Watchdog Mode Register */
-#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
-#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
-#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
-#define AT91_ST_RTMR            0x0c                    /* Real-time Mode Register */
-#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
-#define AT91_ST_SR              0x10                    /* Status Register */
-#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
-#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
-#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
-#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
-#define AT91_ST_IER             0x14                    /* Interrupt Enable Register */
-#define AT91_ST_IDR             0x18                    /* Interrupt Disable Register */
-#define AT91_ST_IMR             0x1c                    /* Interrupt Mask Register */
-#define AT91_ST_RTAR            0x20                    /* Real-time Alarm Register */
-#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
-#define AT91_ST_CRTR            0x24                    /* Current Real-time Register */
-#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
deleted file mode 100644
index e67317c67761..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
-#define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
-#define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
-#define AT91RM9200_ID_PIOD      5       /* Parallel IO Controller D */
-#define AT91RM9200_ID_US0       6       /* USART 0 */
-#define AT91RM9200_ID_US1       7       /* USART 1 */
-#define AT91RM9200_ID_US2       8       /* USART 2 */
-#define AT91RM9200_ID_US3       9       /* USART 3 */
-#define AT91RM9200_ID_MCI       10      /* Multimedia Card Interface */
-#define AT91RM9200_ID_UDP       11      /* USB Device Port */
-#define AT91RM9200_ID_TWI       12      /* Two-Wire Interface */
-#define AT91RM9200_ID_SPI       13      /* Serial Peripheral Interface */
-#define AT91RM9200_ID_SSC0      14      /* Serial Synchronous Controller 0 */
-#define AT91RM9200_ID_SSC1      15      /* Serial Synchronous Controller 1 */
-#define AT91RM9200_ID_SSC2      16      /* Serial Synchronous Controller 2 */
-#define AT91RM9200_ID_TC0       17      /* Timer Counter 0 */
-#define AT91RM9200_ID_TC1       18      /* Timer Counter 1 */
-#define AT91RM9200_ID_TC2       19      /* Timer Counter 2 */
-#define AT91RM9200_ID_TC3       20      /* Timer Counter 3 */
-#define AT91RM9200_ID_TC4       21      /* Timer Counter 4 */
-#define AT91RM9200_ID_TC5       22      /* Timer Counter 5 */
-#define AT91RM9200_ID_UHP       23      /* USB Host port */
-#define AT91RM9200_ID_EMAC      24      /* Ethernet MAC */
-#define AT91RM9200_ID_IRQ0      25      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91RM9200_ID_IRQ1      26      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91RM9200_ID_IRQ2      27      /* Advanced Interrupt Controller (IRQ2) */
-#define AT91RM9200_ID_IRQ3      28      /* Advanced Interrupt Controller (IRQ3) */
-#define AT91RM9200_ID_IRQ4      29      /* Advanced Interrupt Controller (IRQ4) */
-#define AT91RM9200_ID_IRQ5      30      /* Advanced Interrupt Controller (IRQ5) */
-#define AT91RM9200_ID_IRQ6      31      /* Advanced Interrupt Controller (IRQ6) */
-/*
- * Peripheral physical base addresses.
- */
-#define AT91RM9200_BASE_TCB0    0xfffa0000
-#define AT91RM9200_BASE_TC0     0xfffa0000
-#define AT91RM9200_BASE_TC1     0xfffa0040
-#define AT91RM9200_BASE_TC2     0xfffa0080
-#define AT91RM9200_BASE_TCB1    0xfffa4000
-#define AT91RM9200_BASE_TC3     0xfffa4000
-#define AT91RM9200_BASE_TC4     0xfffa4040
-#define AT91RM9200_BASE_TC5     0xfffa4080
-#define AT91RM9200_BASE_UDP     0xfffb0000
-#define AT91RM9200_BASE_MCI     0xfffb4000
-#define AT91RM9200_BASE_TWI     0xfffb8000
-#define AT91RM9200_BASE_EMAC    0xfffbc000
-#define AT91RM9200_BASE_US0     0xfffc0000
-#define AT91RM9200_BASE_US1     0xfffc4000
-#define AT91RM9200_BASE_US2     0xfffc8000
-#define AT91RM9200_BASE_US3     0xfffcc000
-#define AT91RM9200_BASE_SSC0    0xfffd0000
-#define AT91RM9200_BASE_SSC1    0xfffd4000
-#define AT91RM9200_BASE_SSC2    0xfffd8000
-#define AT91RM9200_BASE_SPI     0xfffe0000
-/*
- * System Peripherals
- */
-#define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
-#define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
-#define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
-#define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
-#define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
-#define AT91RM9200_BASE_ST      0xfffffd00      /* System Timer */
-#define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
-#define AT91RM9200_BASE_MC      0xffffff00      /* Memory Controllers */
-/*
- * Internal Memory.
- */
-#define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
-#define AT91RM9200_ROM_SIZE     SZ_128K         /* Internal ROM size (128Kb) */
-#define AT91RM9200_SRAM_BASE    0x00200000      /* Internal SRAM base address */
-#define AT91RM9200_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
-#define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
deleted file mode 100644
index 416c7b6c56d3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260.h
- *
- * (C) 2006 Andrew Victor
- *
- * Common definitions.
- * Based on AT91SAM9260 datasheet revision A (Preliminary).
- *
- * Includes also definitions for AT91SAM9XE and AT91SAM9G families
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC      5       /* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0      6       /* USART 0 */
-#define AT91SAM9260_ID_US1      7       /* USART 1 */
-#define AT91SAM9260_ID_US2      8       /* USART 2 */
-#define AT91SAM9260_ID_MCI      9       /* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP      10      /* USB Device Port */
-#define AT91SAM9260_ID_TWI      11      /* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0     12      /* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1     13      /* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC      14      /* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0      17      /* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1      18      /* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2      19      /* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP      20      /* USB Host port */
-#define AT91SAM9260_ID_EMAC     21      /* Ethernet */
-#define AT91SAM9260_ID_ISI      22      /* Image Sensor Interface */
-#define AT91SAM9260_ID_US3      23      /* USART 3 */
-#define AT91SAM9260_ID_US4      24      /* USART 4 */
-#define AT91SAM9260_ID_US5      25      /* USART 5 */
-#define AT91SAM9260_ID_TC3      26      /* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4      27      /* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5      28      /* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9260_BASE_TCB0           0xfffa0000
-#define AT91SAM9260_BASE_TC0            0xfffa0000
-#define AT91SAM9260_BASE_TC1            0xfffa0040
-#define AT91SAM9260_BASE_TC2            0xfffa0080
-#define AT91SAM9260_BASE_UDP            0xfffa4000
-#define AT91SAM9260_BASE_MCI            0xfffa8000
-#define AT91SAM9260_BASE_TWI            0xfffac000
-#define AT91SAM9260_BASE_US0            0xfffb0000
-#define AT91SAM9260_BASE_US1            0xfffb4000
-#define AT91SAM9260_BASE_US2            0xfffb8000
-#define AT91SAM9260_BASE_SSC            0xfffbc000
-#define AT91SAM9260_BASE_ISI            0xfffc0000
-#define AT91SAM9260_BASE_EMAC           0xfffc4000
-#define AT91SAM9260_BASE_SPI0           0xfffc8000
-#define AT91SAM9260_BASE_SPI1           0xfffcc000
-#define AT91SAM9260_BASE_US3            0xfffd0000
-#define AT91SAM9260_BASE_US4            0xfffd4000
-#define AT91SAM9260_BASE_US5            0xfffd8000
-#define AT91SAM9260_BASE_TCB1           0xfffdc000
-#define AT91SAM9260_BASE_TC3            0xfffdc000
-#define AT91SAM9260_BASE_TC4            0xfffdc040
-#define AT91SAM9260_BASE_TC5            0xfffdc080
-#define AT91SAM9260_BASE_ADC            0xfffe0000
-/*
- * System Peripherals
- */
-#define AT91SAM9260_BASE_ECC    0xffffe800
-#define AT91SAM9260_BASE_SDRAMC 0xffffea00
-#define AT91SAM9260_BASE_SMC    0xffffec00
-#define AT91SAM9260_BASE_MATRIX 0xffffee00
-#define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
-#define AT91SAM9260_BASE_PIOA   0xfffff400
-#define AT91SAM9260_BASE_PIOB   0xfffff600
-#define AT91SAM9260_BASE_PIOC   0xfffff800
-#define AT91SAM9260_BASE_RSTC   0xfffffd00
-#define AT91SAM9260_BASE_SHDWC  0xfffffd10
-#define AT91SAM9260_BASE_RTT    0xfffffd20
-#define AT91SAM9260_BASE_PIT    0xfffffd30
-#define AT91SAM9260_BASE_WDT    0xfffffd40
-#define AT91SAM9260_BASE_GPBR   0xfffffd50
-/*
- * Internal Memory.
- */
-#define AT91SAM9260_ROM_BASE    0x00100000      /* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-#define AT91SAM9260_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
-#define AT91SAM9260_SRAM_BASE   0x002FF000      /* Internal SRAM base address */
-#define AT91SAM9260_SRAM_SIZE   SZ_8K           /* Internal SRAM size (8Kb) */
-#define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
-#define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
-#define AT91SAM9G20_SRAM_BASE   0x002FC000      /* Internal SRAM base address */
-#define AT91SAM9G20_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
-#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
deleted file mode 100644
index f459df420629..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
- *
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_EBICSA      0x11C                   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
-#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
deleted file mode 100644
index a041406d06ee..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9261.h
- *
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91SAM9261 datasheet revision E. (Preliminary)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
-#define AT91SAM9261_ID_US0      6       /* USART 0 */
-#define AT91SAM9261_ID_US1      7       /* USART 1 */
-#define AT91SAM9261_ID_US2      8       /* USART 2 */
-#define AT91SAM9261_ID_MCI      9       /* Multimedia Card Interface */
-#define AT91SAM9261_ID_UDP      10      /* USB Device Port */
-#define AT91SAM9261_ID_TWI      11      /* Two-Wire Interface */
-#define AT91SAM9261_ID_SPI0     12      /* Serial Peripheral Interface 0 */
-#define AT91SAM9261_ID_SPI1     13      /* Serial Peripheral Interface 1 */
-#define AT91SAM9261_ID_SSC0     14      /* Serial Synchronous Controller 0 */
-#define AT91SAM9261_ID_SSC1     15      /* Serial Synchronous Controller 1 */
-#define AT91SAM9261_ID_SSC2     16      /* Serial Synchronous Controller 2 */
-#define AT91SAM9261_ID_TC0      17      /* Timer Counter 0 */
-#define AT91SAM9261_ID_TC1      18      /* Timer Counter 1 */
-#define AT91SAM9261_ID_TC2      19      /* Timer Counter 2 */
-#define AT91SAM9261_ID_UHP      20      /* USB Host port */
-#define AT91SAM9261_ID_LCDC     21      /* LDC Controller */
-#define AT91SAM9261_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9261_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9261_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9261_BASE_TCB0           0xfffa0000
-#define AT91SAM9261_BASE_TC0            0xfffa0000
-#define AT91SAM9261_BASE_TC1            0xfffa0040
-#define AT91SAM9261_BASE_TC2            0xfffa0080
-#define AT91SAM9261_BASE_UDP            0xfffa4000
-#define AT91SAM9261_BASE_MCI            0xfffa8000
-#define AT91SAM9261_BASE_TWI            0xfffac000
-#define AT91SAM9261_BASE_US0            0xfffb0000
-#define AT91SAM9261_BASE_US1            0xfffb4000
-#define AT91SAM9261_BASE_US2            0xfffb8000
-#define AT91SAM9261_BASE_SSC0           0xfffbc000
-#define AT91SAM9261_BASE_SSC1           0xfffc0000
-#define AT91SAM9261_BASE_SSC2           0xfffc4000
-#define AT91SAM9261_BASE_SPI0           0xfffc8000
-#define AT91SAM9261_BASE_SPI1           0xfffcc000
-/*
- * System Peripherals
- */
-#define AT91SAM9261_BASE_SMC    0xffffec00
-#define AT91SAM9261_BASE_MATRIX 0xffffee00
-#define AT91SAM9261_BASE_SDRAMC 0xffffea00
-#define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
-#define AT91SAM9261_BASE_PIOA   0xfffff400
-#define AT91SAM9261_BASE_PIOB   0xfffff600
-#define AT91SAM9261_BASE_PIOC   0xfffff800
-#define AT91SAM9261_BASE_RSTC   0xfffffd00
-#define AT91SAM9261_BASE_SHDWC  0xfffffd10
-#define AT91SAM9261_BASE_RTT    0xfffffd20
-#define AT91SAM9261_BASE_PIT    0xfffffd30
-#define AT91SAM9261_BASE_WDT    0xfffffd40
-#define AT91SAM9261_BASE_GPBR   0xfffffd50
-/*
- * Internal Memory.
- */
-#define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
-#define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
-#define AT91SAM9G10_SRAM_BASE   AT91SAM9261_SRAM_BASE   /* Internal SRAM base address */
-#define AT91SAM9G10_SRAM_SIZE   0x00004000      /* Internal SRAM size (16Kb) */
-#define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-#define AT91SAM9261_UHP_BASE    0x00500000      /* USB Host controller */
-#define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
deleted file mode 100644
index a50cdf8b8ca4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
- *
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-#define AT91_MATRIX_MCFG        0x00                    /* Master Configuration Register */
-#define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_SCFG0       0x04                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       0x08                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       0x0C                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       0x10                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       0x14                    /* Slave Configuration Register 4 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
-#define AT91_MATRIX_TCR         0x24                    /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define                 AT91_MATRIX_ITCM_64             (7 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define                 AT91_MATRIX_DTCM_64             (7 << 4)
-#define AT91_MATRIX_EBICSA      0x30                    /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_USBPUCR     0x34                    /* USB Pad Pull-Up Control Register */
-#define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
deleted file mode 100644
index d201029d60b3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9263.h
- *
- * (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9263_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9263_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9263_ID_PIOCDE   4       /* Parallel IO Controller C, D and E */
-#define AT91SAM9263_ID_US0      7       /* USART 0 */
-#define AT91SAM9263_ID_US1      8       /* USART 1 */
-#define AT91SAM9263_ID_US2      9       /* USART 2 */
-#define AT91SAM9263_ID_MCI0     10      /* Multimedia Card Interface 0 */
-#define AT91SAM9263_ID_MCI1     11      /* Multimedia Card Interface 1 */
-#define AT91SAM9263_ID_CAN      12      /* CAN */
-#define AT91SAM9263_ID_TWI      13      /* Two-Wire Interface */
-#define AT91SAM9263_ID_SPI0     14      /* Serial Peripheral Interface 0 */
-#define AT91SAM9263_ID_SPI1     15      /* Serial Peripheral Interface 1 */
-#define AT91SAM9263_ID_SSC0     16      /* Serial Synchronous Controller 0 */
-#define AT91SAM9263_ID_SSC1     17      /* Serial Synchronous Controller 1 */
-#define AT91SAM9263_ID_AC97C    18      /* AC97 Controller */
-#define AT91SAM9263_ID_TCB      19      /* Timer Counter 0, 1 and 2 */
-#define AT91SAM9263_ID_PWMC     20      /* Pulse Width Modulation Controller */
-#define AT91SAM9263_ID_EMAC     21      /* Ethernet */
-#define AT91SAM9263_ID_2DGE     23      /* 2D Graphic Engine */
-#define AT91SAM9263_ID_UDP      24      /* USB Device Port */
-#define AT91SAM9263_ID_ISI      25      /* Image Sensor Interface */
-#define AT91SAM9263_ID_LCDC     26      /* LCD Controller */
-#define AT91SAM9263_ID_DMA      27      /* DMA Controller */
-#define AT91SAM9263_ID_UHP      29      /* USB Host port */
-#define AT91SAM9263_ID_IRQ0     30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9263_ID_IRQ1     31      /* Advanced Interrupt Controller (IRQ1) */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9263_BASE_UDP            0xfff78000
-#define AT91SAM9263_BASE_TCB0           0xfff7c000
-#define AT91SAM9263_BASE_TC0            0xfff7c000
-#define AT91SAM9263_BASE_TC1            0xfff7c040
-#define AT91SAM9263_BASE_TC2            0xfff7c080
-#define AT91SAM9263_BASE_MCI0           0xfff80000
-#define AT91SAM9263_BASE_MCI1           0xfff84000
-#define AT91SAM9263_BASE_TWI            0xfff88000
-#define AT91SAM9263_BASE_US0            0xfff8c000
-#define AT91SAM9263_BASE_US1            0xfff90000
-#define AT91SAM9263_BASE_US2            0xfff94000
-#define AT91SAM9263_BASE_SSC0           0xfff98000
-#define AT91SAM9263_BASE_SSC1           0xfff9c000
-#define AT91SAM9263_BASE_AC97C          0xfffa0000
-#define AT91SAM9263_BASE_SPI0           0xfffa4000
-#define AT91SAM9263_BASE_SPI1           0xfffa8000
-#define AT91SAM9263_BASE_CAN            0xfffac000
-#define AT91SAM9263_BASE_PWMC           0xfffb8000
-#define AT91SAM9263_BASE_EMAC           0xfffbc000
-#define AT91SAM9263_BASE_ISI            0xfffc4000
-#define AT91SAM9263_BASE_2DGE           0xfffc8000
-/*
- * System Peripherals
- */
-#define AT91SAM9263_BASE_ECC0   0xffffe000
-#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
-#define AT91SAM9263_BASE_SMC0   0xffffe400
-#define AT91SAM9263_BASE_ECC1   0xffffe600
-#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
-#define AT91SAM9263_BASE_SMC1   0xffffea00
-#define AT91SAM9263_BASE_MATRIX 0xffffec00
-#define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
-#define AT91SAM9263_BASE_PIOA   0xfffff200
-#define AT91SAM9263_BASE_PIOB   0xfffff400
-#define AT91SAM9263_BASE_PIOC   0xfffff600
-#define AT91SAM9263_BASE_PIOD   0xfffff800
-#define AT91SAM9263_BASE_PIOE   0xfffffa00
-#define AT91SAM9263_BASE_RSTC   0xfffffd00
-#define AT91SAM9263_BASE_SHDWC  0xfffffd10
-#define AT91SAM9263_BASE_RTT0   0xfffffd20
-#define AT91SAM9263_BASE_PIT    0xfffffd30
-#define AT91SAM9263_BASE_WDT    0xfffffd40
-#define AT91SAM9263_BASE_RTT1   0xfffffd50
-#define AT91SAM9263_BASE_GPBR   0xfffffd60
-#define AT91_SMC        AT91_SMC0
-/*
- * Internal Memory.
- */
-#define AT91SAM9263_SRAM0_BASE  0x00300000      /* Internal SRAM 0 base address */
-#define AT91SAM9263_SRAM0_SIZE  (80 * SZ_1K)    /* Internal SRAM 0 size (80Kb) */
-#define AT91SAM9263_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT91SAM9263_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
-#define AT91SAM9263_SRAM1_BASE  0x00500000      /* Internal SRAM 1 base address */
-#define AT91SAM9263_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
-#define AT91SAM9263_LCDC_BASE   0x00700000      /* LCD Controller */
-#define AT91SAM9263_DMAC_BASE   0x00800000      /* DMA Controller */
-#define AT91SAM9263_UHP_BASE    0x00a00000      /* USB Host controller */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
deleted file mode 100644
index ebb5fdb565e0..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
- *
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define AT91_MATRIX_EBI0CSA     0x120                   /* EBI0 Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
-#define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
-#define         AT91_MATRIX_EBI0_CS3A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI0_CS3A_SMC               (0 << 3)
-#define                 AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_MATRIX_EBI0_CS4A           (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI0_CS4A_SMC               (0 << 4)
-#define                 AT91_MATRIX_EBI0_CS4A_SMC_CF1           (1 << 4)
-#define         AT91_MATRIX_EBI0_CS5A           (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI0_CS5A_SMC               (0 << 5)
-#define                 AT91_MATRIX_EBI0_CS5A_SMC_CF2           (1 << 5)
-#define         AT91_MATRIX_EBI0_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI0_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
-#define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
-#define AT91_MATRIX_EBI1CSA     0x124                   /* EBI1 Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
-#define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
-#define         AT91_MATRIX_EBI1_CS2A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI1_CS2A_SMC               (0 << 3)
-#define                 AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_MATRIX_EBI1_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI1_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI1_VDDIOMSEL_1_8V         (0 << 16)
-#define                 AT91_MATRIX_EBI1_VDDIOMSEL_3_3V         (1 << 16)
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 175e1fdd9fe8..ff54a0ce90e3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,8 +16,6 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
-#include <mach/cpu.h>
 #ifndef __ASSEMBLY__
 struct sam9_smc_config {
        /* Setup register */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
deleted file mode 100644
index 8eba1021f533..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9G45 family
- *
- *  Copyright (C) 2008-2009 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9G45_ID_PIOA     2       /* Parallel I/O Controller A */
-#define AT91SAM9G45_ID_PIOB     3       /* Parallel I/O Controller B */
-#define AT91SAM9G45_ID_PIOC     4       /* Parallel I/O Controller C */
-#define AT91SAM9G45_ID_PIODE    5       /* Parallel I/O Controller D and E */
-#define AT91SAM9G45_ID_TRNG     6       /* True Random Number Generator */
-#define AT91SAM9G45_ID_US0      7       /* USART 0 */
-#define AT91SAM9G45_ID_US1      8       /* USART 1 */
-#define AT91SAM9G45_ID_US2      9       /* USART 2 */
-#define AT91SAM9G45_ID_US3      10      /* USART 3 */
-#define AT91SAM9G45_ID_MCI0     11      /* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9G45_ID_TWI0     12      /* Two-Wire Interface 0 */
-#define AT91SAM9G45_ID_TWI1     13      /* Two-Wire Interface 1 */
-#define AT91SAM9G45_ID_SPI0     14      /* Serial Peripheral Interface 0 */
-#define AT91SAM9G45_ID_SPI1     15      /* Serial Peripheral Interface 1 */
-#define AT91SAM9G45_ID_SSC0     16      /* Synchronous Serial Controller 0 */
-#define AT91SAM9G45_ID_SSC1     17      /* Synchronous Serial Controller 1 */
-#define AT91SAM9G45_ID_TCB      18      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9G45_ID_PWMC     19      /* Pulse Width Modulation Controller */
-#define AT91SAM9G45_ID_TSC      20      /* Touch Screen ADC Controller */
-#define AT91SAM9G45_ID_DMA      21      /* DMA Controller */
-#define AT91SAM9G45_ID_UHPHS    22      /* USB Host High Speed */
-#define AT91SAM9G45_ID_LCDC     23      /* LCD Controller */
-#define AT91SAM9G45_ID_AC97C    24      /* AC97 Controller */
-#define AT91SAM9G45_ID_EMAC     25      /* Ethernet MAC */
-#define AT91SAM9G45_ID_ISI      26      /* Image Sensor Interface */
-#define AT91SAM9G45_ID_UDPHS    27      /* USB Device High Speed */
-#define AT91SAM9G45_ID_AESTDESSHA 28    /* AES + T-DES + SHA */
-#define AT91SAM9G45_ID_MCI1     29      /* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9G45_ID_VDEC     30      /* Video Decoder */
-#define AT91SAM9G45_ID_IRQ0     31      /* Advanced Interrupt Controller */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9G45_BASE_UDPHS          0xfff78000
-#define AT91SAM9G45_BASE_TCB0           0xfff7c000
-#define AT91SAM9G45_BASE_TC0            0xfff7c000
-#define AT91SAM9G45_BASE_TC1            0xfff7c040
-#define AT91SAM9G45_BASE_TC2            0xfff7c080
-#define AT91SAM9G45_BASE_MCI0           0xfff80000
-#define AT91SAM9G45_BASE_TWI0           0xfff84000
-#define AT91SAM9G45_BASE_TWI1           0xfff88000
-#define AT91SAM9G45_BASE_US0            0xfff8c000
-#define AT91SAM9G45_BASE_US1            0xfff90000
-#define AT91SAM9G45_BASE_US2            0xfff94000
-#define AT91SAM9G45_BASE_US3            0xfff98000
-#define AT91SAM9G45_BASE_SSC0           0xfff9c000
-#define AT91SAM9G45_BASE_SSC1           0xfffa0000
-#define AT91SAM9G45_BASE_SPI0           0xfffa4000
-#define AT91SAM9G45_BASE_SPI1           0xfffa8000
-#define AT91SAM9G45_BASE_AC97C          0xfffac000
-#define AT91SAM9G45_BASE_TSC            0xfffb0000
-#define AT91SAM9G45_BASE_ISI            0xfffb4000
-#define AT91SAM9G45_BASE_PWMC           0xfffb8000
-#define AT91SAM9G45_BASE_EMAC           0xfffbc000
-#define AT91SAM9G45_BASE_AES            0xfffc0000
-#define AT91SAM9G45_BASE_TDES           0xfffc4000
-#define AT91SAM9G45_BASE_SHA            0xfffc8000
-#define AT91SAM9G45_BASE_TRNG           0xfffcc000
-#define AT91SAM9G45_BASE_MCI1           0xfffd0000
-#define AT91SAM9G45_BASE_TCB1           0xfffd4000
-#define AT91SAM9G45_BASE_TC3            0xfffd4000
-#define AT91SAM9G45_BASE_TC4            0xfffd4040
-#define AT91SAM9G45_BASE_TC5            0xfffd4080
-/*
- * System Peripherals
- */
-#define AT91SAM9G45_BASE_ECC    0xffffe200
-#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
-#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
-#define AT91SAM9G45_BASE_DMA    0xffffec00
-#define AT91SAM9G45_BASE_SMC    0xffffe800
-#define AT91SAM9G45_BASE_MATRIX 0xffffea00
-#define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
-#define AT91SAM9G45_BASE_PIOA   0xfffff200
-#define AT91SAM9G45_BASE_PIOB   0xfffff400
-#define AT91SAM9G45_BASE_PIOC   0xfffff600
-#define AT91SAM9G45_BASE_PIOD   0xfffff800
-#define AT91SAM9G45_BASE_PIOE   0xfffffa00
-#define AT91SAM9G45_BASE_RSTC   0xfffffd00
-#define AT91SAM9G45_BASE_SHDWC  0xfffffd10
-#define AT91SAM9G45_BASE_RTT    0xfffffd20
-#define AT91SAM9G45_BASE_PIT    0xfffffd30
-#define AT91SAM9G45_BASE_WDT    0xfffffd40
-#define AT91SAM9G45_BASE_RTC    0xfffffdb0
-#define AT91SAM9G45_BASE_GPBR   0xfffffd60
-/*
- * Internal Memory.
- */
-#define AT91SAM9G45_SRAM_BASE   0x00300000      /* Internal SRAM base address */
-#define AT91SAM9G45_SRAM_SIZE   SZ_64K          /* Internal SRAM size (64Kb) */
-#define AT91SAM9G45_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT91SAM9G45_ROM_SIZE    SZ_64K          /* Internal ROM size (64Kb) */
-#define AT91SAM9G45_LCDC_BASE   0x00500000      /* LCD Controller */
-#define AT91SAM9G45_UDPHS_FIFO  0x00600000      /* USB Device HS controller */
-#define AT91SAM9G45_OHCI_BASE   0x00700000      /* USB Host controller (OHCI) */
-#define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
-#define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
-/*
- * DMA peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0           0
-#define AT_DMA_ID_SPI0_TX        1
-#define AT_DMA_ID_SPI0_RX        2
-#define AT_DMA_ID_SPI1_TX        3
-#define AT_DMA_ID_SPI1_RX        4
-#define AT_DMA_ID_SSC0_TX        5
-#define AT_DMA_ID_SSC0_RX        6
-#define AT_DMA_ID_SSC1_TX        7
-#define AT_DMA_ID_SSC1_RX        8
-#define AT_DMA_ID_AC97_TX        9
-#define AT_DMA_ID_AC97_RX       10
-#define AT_DMA_ID_AES_TX        11
-#define AT_DMA_ID_AES_RX        12
-#define AT_DMA_ID_MCI1          13
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
deleted file mode 100644
index b76e2ed2fbc2..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9G45 family
- *
- *  Copyright (C) 2008-2009 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9G45_MATRIX_H
-#define AT91SAM9G45_MATRIX_H
-#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       0x24                    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      0x28                    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      0x2C                    /* Master Configuration Register 11 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define                 AT91_MATRIX_ULBT_THIRTYTWO      (5 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
-#define                 AT91_MATRIX_ULBT_128            (7 << 0)
-#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
-#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
-#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-#define         AT91_MATRIX_RCB9                (1 << 9)
-#define         AT91_MATRIX_RCB10               (1 << 10)
-#define         AT91_MATRIX_RCB11               (1 << 11)
-#define AT91_MATRIX_TCMR        0x110                   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define                 AT91_MATRIX_DTCM_64             (7 << 4)
-#define         AT91_MATRIX_TCM_NWS             (0x1 << 11)     /* Wait state TCM register */
-#define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
-#define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
-#define AT91_MATRIX_VIDEO       0x118                   /* Video Mode Configuration Register */
-#define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
-#define                 AT91C_VDEC_SEL_OFF              (0 << 0)
-#define                 AT91C_VDEC_SEL_ON               (1 << 0)
-#define AT91_MATRIX_EBICSA      0x128                   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
-#define                 AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
-#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
-#define                 AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
-#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
-#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
-#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
-#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
-#define AT91_MATRIX_WPMR        0x1E4                   /* Write Protect Mode Register */
-#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
-#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
-#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
-#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR        0x1E8                   /* Write Protect Status Register */
-#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
-#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
-#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
-#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
deleted file mode 100644
index 0151bcf6163c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * SoC specific header file for the AT91SAM9N12
- *
- * Copyright (C) 2012 Atmel Corporation
- *
- * Common definitions, based on AT91SAM9N12 SoC datasheet
- *
- * Licensed under GPLv2 or later
- */
-#ifndef _AT91SAM9N12_H_
-#define _AT91SAM9N12_H_
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9N12_ID_PIOAB    2       /* Parallel I/O Controller A and B */
-#define AT91SAM9N12_ID_PIOCD    3       /* Parallel I/O Controller C and D */
-#define AT91SAM9N12_ID_FUSE     4       /* FUSE Controller */
-#define AT91SAM9N12_ID_USART0   5       /* USART 0 */
-#define AT91SAM9N12_ID_USART1   6       /* USART 1 */
-#define AT91SAM9N12_ID_USART2   7       /* USART 2 */
-#define AT91SAM9N12_ID_USART3   8       /* USART 3 */
-#define AT91SAM9N12_ID_TWI0     9       /* Two-Wire Interface 0 */
-#define AT91SAM9N12_ID_TWI1     10      /* Two-Wire Interface 1 */
-#define AT91SAM9N12_ID_MCI      12      /* High Speed Multimedia Card Interface */
-#define AT91SAM9N12_ID_SPI0     13      /* Serial Peripheral Interface 0 */
-#define AT91SAM9N12_ID_SPI1     14      /* Serial Peripheral Interface 1 */
-#define AT91SAM9N12_ID_UART0    15      /* UART 0 */
-#define AT91SAM9N12_ID_UART1    16      /* UART 1 */
-#define AT91SAM9N12_ID_TCB      17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9N12_ID_PWM      18      /* Pulse Width Modulation Controller */
-#define AT91SAM9N12_ID_ADC      19      /* ADC Controller */
-#define AT91SAM9N12_ID_DMA      20      /* DMA Controller */
-#define AT91SAM9N12_ID_UHP      22      /* USB Host High Speed */
-#define AT91SAM9N12_ID_UDP      23      /* USB Device High Speed */
-#define AT91SAM9N12_ID_LCDC     25      /* LCD Controller */
-#define AT91SAM9N12_ID_ISI      25      /* Image Sensor Interface */
-#define AT91SAM9N12_ID_SSC      28      /* Synchronous Serial Controller */
-#define AT91SAM9N12_ID_TRNG     30      /* TRNG */
-#define AT91SAM9N12_ID_IRQ0     31      /* Advanced Interrupt Controller */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9N12_BASE_USART0 0xf801c000
-#define AT91SAM9N12_BASE_USART1 0xf8020000
-#define AT91SAM9N12_BASE_USART2 0xf8024000
-#define AT91SAM9N12_BASE_USART3 0xf8028000
-/*
- * System Peripherals
- */
-#define AT91SAM9N12_BASE_RTC    0xfffffeb0
-/*
- * Internal Memory.
- */
-#define AT91SAM9N12_SRAM_BASE   0x00300000      /* Internal SRAM base address */
-#define AT91SAM9N12_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
-#define AT91SAM9N12_ROM_BASE    0x00100000      /* Internal ROM base address */
-#define AT91SAM9N12_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
deleted file mode 100644
index 40060cd62fa9..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9N12
- *
- * Copyright (C) 2012 Atmel Corporation.
- *
- * Only EBI related registers.
- * Write Protect register definitions may be useful.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef _AT91SAM9N12_MATRIX_H_
-#define _AT91SAM9N12_MATRIX_H_
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x118)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
-#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
-#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
-#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
-#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
-#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
-#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
-#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
-#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
-#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
-#define                 AT91_MATRIX_MP_ON                       (1 << 25)
-#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
-#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
-#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
-#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
-#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
-#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
-#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
-#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
-#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
deleted file mode 100644
index a15db56d33fa..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260.h
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9RL_ID_PIOA      2       /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB      3       /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC      4       /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD      5       /* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0       6       /* USART 0 */
-#define AT91SAM9RL_ID_US1       7       /* USART 1 */
-#define AT91SAM9RL_ID_US2       8       /* USART 2 */
-#define AT91SAM9RL_ID_US3       9       /* USART 3 */
-#define AT91SAM9RL_ID_MCI       10      /* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0      11      /* TWI 0 */
-#define AT91SAM9RL_ID_TWI1      12      /* TWI 1 */
-#define AT91SAM9RL_ID_SPI       13      /* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0      14      /* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1      15      /* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0       16      /* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1       17      /* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2       18      /* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC      19      /* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC       20      /* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA       21      /* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS     22      /* USB Device HS */
-#define AT91SAM9RL_ID_LCDC      23      /* LCD Controller */
-#define AT91SAM9RL_ID_AC97C     24      /* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0      31      /* Advanced Interrupt Controller (IRQ0) */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9RL_BASE_TCB0    0xfffa0000
-#define AT91SAM9RL_BASE_TC0     0xfffa0000
-#define AT91SAM9RL_BASE_TC1     0xfffa0040
-#define AT91SAM9RL_BASE_TC2     0xfffa0080
-#define AT91SAM9RL_BASE_MCI     0xfffa4000
-#define AT91SAM9RL_BASE_TWI0    0xfffa8000
-#define AT91SAM9RL_BASE_TWI1    0xfffac000
-#define AT91SAM9RL_BASE_US0     0xfffb0000
-#define AT91SAM9RL_BASE_US1     0xfffb4000
-#define AT91SAM9RL_BASE_US2     0xfffb8000
-#define AT91SAM9RL_BASE_US3     0xfffbc000
-#define AT91SAM9RL_BASE_SSC0    0xfffc0000
-#define AT91SAM9RL_BASE_SSC1    0xfffc4000
-#define AT91SAM9RL_BASE_PWMC    0xfffc8000
-#define AT91SAM9RL_BASE_SPI     0xfffcc000
-#define AT91SAM9RL_BASE_TSC     0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS   0xfffd4000
-#define AT91SAM9RL_BASE_AC97C   0xfffd8000
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
-#define AT91SAM9RL_BASE_DMA     0xffffe600
-#define AT91SAM9RL_BASE_ECC     0xffffe800
-#define AT91SAM9RL_BASE_SDRAMC  0xffffea00
-#define AT91SAM9RL_BASE_SMC     0xffffec00
-#define AT91SAM9RL_BASE_MATRIX  0xffffee00
-#define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
-#define AT91SAM9RL_BASE_PIOA    0xfffff400
-#define AT91SAM9RL_BASE_PIOB    0xfffff600
-#define AT91SAM9RL_BASE_PIOC    0xfffff800
-#define AT91SAM9RL_BASE_PIOD    0xfffffa00
-#define AT91SAM9RL_BASE_RSTC    0xfffffd00
-#define AT91SAM9RL_BASE_SHDWC   0xfffffd10
-#define AT91SAM9RL_BASE_RTT     0xfffffd20
-#define AT91SAM9RL_BASE_PIT     0xfffffd30
-#define AT91SAM9RL_BASE_WDT     0xfffffd40
-#define AT91SAM9RL_BASE_GPBR    0xfffffd60
-#define AT91SAM9RL_BASE_RTC     0xfffffe00
-/*
- * Internal Memory.
- */
-#define AT91SAM9RL_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
-#define AT91SAM9RL_ROM_BASE     0x00400000      /* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
-#define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
-#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
deleted file mode 100644
index 6d160adadafc..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-#ifndef AT91SAM9RL_MATRIX_H
-#define AT91SAM9RL_MATRIX_H
-#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define AT91_MATRIX_EBICSA      0x120                   /* EBI0 Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
-#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
deleted file mode 100644
index 2fc76c49e97c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9x5 family
- *
- *  Copyright (C) 2009-2012 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9x5 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef AT91SAM9X5_H
-#define AT91SAM9X5_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9X5_ID_PIOAB     2       /* Parallel I/O Controller A and B */
-#define AT91SAM9X5_ID_PIOCD     3       /* Parallel I/O Controller C and D */
-#define AT91SAM9X5_ID_SMD       4       /* SMD Soft Modem (SMD) */
-#define AT91SAM9X5_ID_USART0    5       /* USART 0 */
-#define AT91SAM9X5_ID_USART1    6       /* USART 1 */
-#define AT91SAM9X5_ID_USART2    7       /* USART 2 */
-#define AT91SAM9X5_ID_USART3    8       /* USART 3 */
-#define AT91SAM9X5_ID_TWI0      9       /* Two-Wire Interface 0 */
-#define AT91SAM9X5_ID_TWI1      10      /* Two-Wire Interface 1 */
-#define AT91SAM9X5_ID_TWI2      11      /* Two-Wire Interface 2 */
-#define AT91SAM9X5_ID_MCI0      12      /* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9X5_ID_SPI0      13      /* Serial Peripheral Interface 0 */
-#define AT91SAM9X5_ID_SPI1      14      /* Serial Peripheral Interface 1 */
-#define AT91SAM9X5_ID_UART0     15      /* UART 0 */
-#define AT91SAM9X5_ID_UART1     16      /* UART 1 */
-#define AT91SAM9X5_ID_TCB       17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9X5_ID_PWM       18      /* Pulse Width Modulation Controller */
-#define AT91SAM9X5_ID_ADC       19      /* ADC Controller */
-#define AT91SAM9X5_ID_DMA0      20      /* DMA Controller 0 */
-#define AT91SAM9X5_ID_DMA1      21      /* DMA Controller 1 */
-#define AT91SAM9X5_ID_UHPHS     22      /* USB Host High Speed */
-#define AT91SAM9X5_ID_UDPHS     23      /* USB Device High Speed */
-#define AT91SAM9X5_ID_EMAC0     24      /* Ethernet MAC0 */
-#define AT91SAM9X5_ID_LCDC      25      /* LCD Controller */
-#define AT91SAM9X5_ID_ISI       25      /* Image Sensor Interface */
-#define AT91SAM9X5_ID_MCI1      26      /* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9X5_ID_EMAC1     27      /* Ethernet MAC1 */
-#define AT91SAM9X5_ID_SSC       28      /* Synchronous Serial Controller */
-#define AT91SAM9X5_ID_CAN0      29      /* CAN Controller 0 */
-#define AT91SAM9X5_ID_CAN1      30      /* CAN Controller 1 */
-#define AT91SAM9X5_ID_IRQ0      31      /* Advanced Interrupt Controller */
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9X5_BASE_USART0  0xf801c000
-#define AT91SAM9X5_BASE_USART1  0xf8020000
-#define AT91SAM9X5_BASE_USART2  0xf8024000
-/*
- * System Peripherals
- */
-#define AT91SAM9X5_BASE_RTC     0xfffffeb0
-/*
- * Internal Memory.
- */
-#define AT91SAM9X5_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#define AT91SAM9X5_SRAM_SIZE    SZ_32K          /* Internal SRAM size (32Kb) */
-#define AT91SAM9X5_ROM_BASE     0x00400000      /* Internal ROM base address */
-#define AT91SAM9X5_ROM_SIZE     SZ_64K          /* Internal ROM size (64Kb) */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
deleted file mode 100644
index a606d3966470..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9x5 family
- *
- *  Copyright (C) 2009-2012 Atmel Corporation.
- *
- * Only EBI related registers.
- * Write Protect register definitions may be useful.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef AT91SAM9X5_MATRIX_H
-#define AT91SAM9X5_MATRIX_H
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
-#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
-#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
-#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
-#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
-#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
-#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
-#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
-#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
-#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
-#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
-#define                 AT91_MATRIX_MP_ON                       (1 << 25)
-#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
-#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
-#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
-#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
-#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
-#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
-#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
-#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
-#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
deleted file mode 100644
index ce7c80a44983..000000000000
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/cpu.h
- *
- * Copyright (C) 2006 SAN People
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __MACH_CPU_H__
-#define __MACH_CPU_H__
-#define ARCH_ID_AT91RM9200      0x09290780
-#define ARCH_ID_AT91SAM9260     0x019803a0
-#define ARCH_ID_AT91SAM9261     0x019703a0
-#define ARCH_ID_AT91SAM9263     0x019607a0
-#define ARCH_ID_AT91SAM9G10     0x019903a0
-#define ARCH_ID_AT91SAM9G20     0x019905a0
-#define ARCH_ID_AT91SAM9RL64    0x019b03a0
-#define ARCH_ID_AT91SAM9G45     0x819b05a0
-#define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
-#define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
-#define ARCH_ID_AT91SAM9X5      0x819a05a0
-#define ARCH_ID_AT91SAM9N12     0x819a07a0
-#define ARCH_ID_AT91SAM9XE128   0x329973a0
-#define ARCH_ID_AT91SAM9XE256   0x329a93a0
-#define ARCH_ID_AT91SAM9XE512   0x329aa3a0
-#define ARCH_ID_AT91M40800      0x14080044
-#define ARCH_ID_AT91R40807      0x44080746
-#define ARCH_ID_AT91M40807      0x14080745
-#define ARCH_ID_AT91R40008      0x44000840
-#define ARCH_ID_SAMA5           0x8A5C07C0
-#define ARCH_EXID_AT91SAM9M11   0x00000001
-#define ARCH_EXID_AT91SAM9M10   0x00000002
-#define ARCH_EXID_AT91SAM9G46   0x00000003
-#define ARCH_EXID_AT91SAM9G45   0x00000004
-#define ARCH_EXID_AT91SAM9G15   0x00000000
-#define ARCH_EXID_AT91SAM9G35   0x00000001
-#define ARCH_EXID_AT91SAM9X35   0x00000002
-#define ARCH_EXID_AT91SAM9G25   0x00000003
-#define ARCH_EXID_AT91SAM9X25   0x00000004
-#define ARCH_EXID_SAMA5D3       0x00004300
-#define ARCH_EXID_SAMA5D31      0x00444300
-#define ARCH_EXID_SAMA5D33      0x00414300
-#define ARCH_EXID_SAMA5D34      0x00414301
-#define ARCH_EXID_SAMA5D35      0x00584300
-#define ARCH_EXID_SAMA5D36      0x00004301
-#define ARCH_EXID_SAMA5D4       0x00000007
-#define ARCH_EXID_SAMA5D41      0x00000001
-#define ARCH_EXID_SAMA5D42      0x00000002
-#define ARCH_EXID_SAMA5D43      0x00000003
-#define ARCH_EXID_SAMA5D44      0x00000004
-#define ARCH_FAMILY_AT91SAM9    0x01900000
-#define ARCH_FAMILY_AT91SAM9XE  0x02900000
-/* RM9200 type */
-#define ARCH_REVISON_9200_BGA   (0 << 0)
-#define ARCH_REVISON_9200_PQFP  (1 << 0)
-#ifndef __ASSEMBLY__
-enum at91_soc_type {
-        /* 920T */
-        AT91_SOC_RM9200,
-        /* SAM92xx */
-        AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
-        /* SAM9Gxx */
-        AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
-        /* SAM9RL */
-        AT91_SOC_SAM9RL,
-        /* SAM9X5 */
-        AT91_SOC_SAM9X5,
-        /* SAM9N12 */
-        AT91_SOC_SAM9N12,
-        /* SAMA5D3 */
-        AT91_SOC_SAMA5D3,
-        /* SAMA5D4 */
-        AT91_SOC_SAMA5D4,
-        /* Unknown type */
-        AT91_SOC_UNKNOWN,
-};
-enum at91_soc_subtype {
-        /* RM9200 */
-        AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
-        /* SAM9260 */
-        AT91_SOC_SAM9XE,
-        /* SAM9G45 */
-        AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
-        /* SAM9X5 */
-        AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
-        AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
-        /* SAMA5D3 */
-        AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
-        AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
-        /* SAMA5D4 */
-        AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
-        AT91_SOC_SAMA5D44,
-        /* No subtype for this SoC */
-        AT91_SOC_SUBTYPE_NONE,
-        /* Unknown subtype */
-        AT91_SOC_SUBTYPE_UNKNOWN,
-};
-struct at91_socinfo {
-        unsigned int type, subtype;
-        unsigned int cidr, exid;
-};
-extern struct at91_socinfo at91_soc_initdata;
-const char *at91_get_soc_type(struct at91_socinfo *c);
-const char *at91_get_soc_subtype(struct at91_socinfo *c);
-static inline int at91_soc_is_detected(void)
-{
-        return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
-}
-#ifdef CONFIG_SOC_AT91RM9200
-#define cpu_is_at91rm9200()     (at91_soc_initdata.type == AT91_SOC_RM9200)
-#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
-#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
-#else
-#define cpu_is_at91rm9200()     (0)
-#define cpu_is_at91rm9200_bga() (0)
-#define cpu_is_at91rm9200_pqfp() (0)
-#endif
-#ifdef CONFIG_SOC_AT91SAM9
-#define cpu_is_at91sam9xe()     (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
-#define cpu_is_at91sam9260()    (at91_soc_initdata.type == AT91_SOC_SAM9260)
-#define cpu_is_at91sam9g20()    (at91_soc_initdata.type == AT91_SOC_SAM9G20)
-#define cpu_is_at91sam9261()    (at91_soc_initdata.type == AT91_SOC_SAM9261)
-#define cpu_is_at91sam9g10()    (at91_soc_initdata.type == AT91_SOC_SAM9G10)
-#define cpu_is_at91sam9263()    (at91_soc_initdata.type == AT91_SOC_SAM9263)
-#define cpu_is_at91sam9rl()     (at91_soc_initdata.type == AT91_SOC_SAM9RL)
-#define cpu_is_at91sam9g45()    (at91_soc_initdata.type == AT91_SOC_SAM9G45)
-#define cpu_is_at91sam9g45es()  (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
-#define cpu_is_at91sam9m10()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
-#define cpu_is_at91sam9g46()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
-#define cpu_is_at91sam9m11()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
-#define cpu_is_at91sam9x5()     (at91_soc_initdata.type == AT91_SOC_SAM9X5)
-#define cpu_is_at91sam9g15()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
-#define cpu_is_at91sam9g35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
-#define cpu_is_at91sam9x35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
-#define cpu_is_at91sam9g25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
-#define cpu_is_at91sam9x25()    (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
-#define cpu_is_at91sam9n12()    (at91_soc_initdata.type == AT91_SOC_SAM9N12)
-#else
-#define cpu_is_at91sam9xe()     (0)
-#define cpu_is_at91sam9260()    (0)
-#define cpu_is_at91sam9g20()    (0)
-#define cpu_is_at91sam9261()    (0)
-#define cpu_is_at91sam9g10()    (0)
-#define cpu_is_at91sam9263()    (0)
-#define cpu_is_at91sam9rl()     (0)
-#define cpu_is_at91sam9g45()    (0)
-#define cpu_is_at91sam9g45es()  (0)
-#define cpu_is_at91sam9m10()    (0)
-#define cpu_is_at91sam9g46()    (0)
-#define cpu_is_at91sam9m11()    (0)
-#define cpu_is_at91sam9x5()     (0)
-#define cpu_is_at91sam9g15()    (0)
-#define cpu_is_at91sam9g35()    (0)
-#define cpu_is_at91sam9x35()    (0)
-#define cpu_is_at91sam9g25()    (0)
-#define cpu_is_at91sam9x25()    (0)
-#define cpu_is_at91sam9n12()    (0)
-#endif
-#ifdef CONFIG_SOC_SAMA5D3
-#define cpu_is_sama5d3()        (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
-#else
-#define cpu_is_sama5d3()        (0)
-#endif
-#ifdef CONFIG_SOC_SAMA5D4
-#define cpu_is_sama5d4()        (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
-#else
-#define cpu_is_sama5d4()        (0)
-#endif
-/*
- * Since this is ARM, we will never run on any AVR32 CPU. But these
- * definitions may reduce clutter in common drivers.
- */
-#define cpu_is_at32ap7000()     (0)
-#endif /* __ASSEMBLY__ */
-#endif /* __MACH_CPU_H__ */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
deleted file mode 100644
index cacbaa52418f..000000000000
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/hardware.h
- *
- *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2003 ATMEL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-/* DBGU base */
-/* rm9200, 9260/9g20, 9261/9g10, 9rl */
-#define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45, sama5d3 */
-#define AT91_BASE_DBGU1 0xffffee00
-/* sama5d4 */
-#define AT91_BASE_DBGU2 0xfc069000
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91sam9n12.h>
-#include <mach/sama5d3.h>
-#include <mach/sama5d4.h>
-/*
- * On all at91 except rm9200 and x40 have the System Controller starts
- * at address 0xffffc000 and has a size of 16KiB.
- *
- * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
- * at 0xfffff000
- *
- * Removes the individual definitions of AT91_BASE_SYS and
- * replaces them with a common version at base 0xfffffc000 and size 16KiB
- * and map the same memory space
- */
-#define AT91_BASE_SYS   0xffffc000
-/*
- * On sama5d4 there is no system controller, we map some needed peripherals
- */
-#define AT91_ALT_BASE_SYS       0xfc069000
-/*
- * On all at91 have the Advanced Interrupt Controller starts at address
- * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
- */
-#define AT91_AIC        0xfffff000
-#define AT91_PMC        0xfffffc00
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#ifdef CONFIG_MMU
-/*
- * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
- * to 0xFEF78000 .. 0xFF000000.  (544Kb)
- */
-#define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
-/*
- * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
- * to 0xFB069000 .. 0xFB06F000.  (24Kb)
- */
-#define AT91_ALT_IO_PHYS_BASE   AT91_ALT_BASE_SYS
-#define AT91_ALT_IO_VIRT_BASE   IOMEM(0xFB069000)
-#else
-/*
- * Identity mapping for the non MMU case.
- */
-#define AT91_IO_PHYS_BASE       AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
-#define AT91_ALT_IO_PHYS_BASE   AT91_ALT_BASE_SYS
-#define AT91_ALT_IO_VIRT_BASE   IOMEM(AT91_ALT_BASE_SYS)
-#endif
-#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
- /* Convert a physical IO address to virtual IO address */
-#define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
-#define AT91_ALT_IO_P2V(x)      ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
-/*
- * Virtual to Physical Address mapping for IO devices.
- */
-#define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_ALT_VA_BASE_SYS    AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
- /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_MAX           SZ_1M
-#define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
-/* External Memory Map */
-#define AT91_CHIPSELECT_0       0x10000000
-#define AT91_CHIPSELECT_1       0x20000000
-#define AT91_CHIPSELECT_2       0x30000000
-#define AT91_CHIPSELECT_3       0x40000000
-#define AT91_CHIPSELECT_4       0x50000000
-#define AT91_CHIPSELECT_5       0x60000000
-#define AT91_CHIPSELECT_6       0x70000000
-#define AT91_CHIPSELECT_7       0x80000000
-/* Clocks */
-#define AT91_SLOW_CLOCK         32768           /* slow clock */
-/*
- * FIXME: this is needed to communicate between the pinctrl driver and
- * the PM implementation in the machine. Possibly part of the PM
- * implementation should be moved down into the pinctrl driver and get
- * called as part of the generic suspend/resume path.
- */
-#ifndef __ASSEMBLY__
-extern void at91_pinctrl_gpio_suspend(void);
-extern void at91_pinctrl_gpio_resume(void);
-#endif
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
deleted file mode 100644
index 25613d8c6dcd..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D3 family
- *
- *  Copyright (C) 2013 Atmel,
- *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
- *
- * Common definitions.
- * Based on SAMA5D3 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef SAMA5D3_H
-#define SAMA5D3_H
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ              0      /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS              1      /* System Peripherals */
-#define SAMA5D3_ID_DBGU          2      /* debug Unit (usually no special interrupt line) */
-#define AT91_ID_PIT              3      /* PIT */
-#define SAMA5D3_ID_WDT           4      /* Watchdog Timer Interrupt */
-#define SAMA5D3_ID_HSMC          5      /* Static Memory Controller */
-#define SAMA5D3_ID_PIOA          6      /* PIOA */
-#define SAMA5D3_ID_PIOB          7      /* PIOB */
-#define SAMA5D3_ID_PIOC          8      /* PIOC */
-#define SAMA5D3_ID_PIOD          9      /* PIOD */
-#define SAMA5D3_ID_PIOE         10      /* PIOE */
-#define SAMA5D3_ID_SMD          11      /* SMD Soft Modem */
-#define SAMA5D3_ID_USART0       12      /* USART0 */
-#define SAMA5D3_ID_USART1       13      /* USART1 */
-#define SAMA5D3_ID_USART2       14      /* USART2 */
-#define SAMA5D3_ID_USART3       15      /* USART3 */
-#define SAMA5D3_ID_UART0        16      /* UART 0 */
-#define SAMA5D3_ID_UART1        17      /* UART 1 */
-#define SAMA5D3_ID_TWI0         18      /* Two-Wire Interface 0 */
-#define SAMA5D3_ID_TWI1         19      /* Two-Wire Interface 1 */
-#define SAMA5D3_ID_TWI2         20      /* Two-Wire Interface 2 */
-#define SAMA5D3_ID_HSMCI0       21      /* MCI */
-#define SAMA5D3_ID_HSMCI1       22      /* MCI */
-#define SAMA5D3_ID_HSMCI2       23      /* MCI */
-#define SAMA5D3_ID_SPI0         24      /* Serial Peripheral Interface 0 */
-#define SAMA5D3_ID_SPI1         25      /* Serial Peripheral Interface 1 */
-#define SAMA5D3_ID_TC0          26      /* Timer Counter 0 */
-#define SAMA5D3_ID_TC1          27      /* Timer Counter 2 */
-#define SAMA5D3_ID_PWM          28      /* Pulse Width Modulation Controller */
-#define SAMA5D3_ID_ADC          29      /* Touch Screen ADC Controller */
-#define SAMA5D3_ID_DMA0         30      /* DMA Controller 0 */
-#define SAMA5D3_ID_DMA1         31      /* DMA Controller 1 */
-#define SAMA5D3_ID_UHPHS        32      /* USB Host High Speed */
-#define SAMA5D3_ID_UDPHS        33      /* USB Device High Speed */
-#define SAMA5D3_ID_GMAC         34      /* Gigabit Ethernet MAC */
-#define SAMA5D3_ID_EMAC         35      /* Ethernet MAC */
-#define SAMA5D3_ID_LCDC         36      /* LCD Controller */
-#define SAMA5D3_ID_ISI          37      /* Image Sensor Interface */
-#define SAMA5D3_ID_SSC0         38      /* Synchronous Serial Controller 0 */
-#define SAMA5D3_ID_SSC1         39      /* Synchronous Serial Controller 1 */
-#define SAMA5D3_ID_CAN0         40      /* CAN Controller 0 */
-#define SAMA5D3_ID_CAN1         41      /* CAN Controller 1 */
-#define SAMA5D3_ID_SHA          42      /* Secure Hash Algorithm */
-#define SAMA5D3_ID_AES          43      /* Advanced Encryption Standard */
-#define SAMA5D3_ID_TDES         44      /* Triple Data Encryption Standard */
-#define SAMA5D3_ID_TRNG         45      /* True Random Generator Number */
-#define SAMA5D3_ID_IRQ0         47      /* Advanced Interrupt Controller (IRQ0) */
-/*
- * User Peripheral physical base addresses.
- */
-#define SAMA5D3_BASE_USART0     0xf001c000
-#define SAMA5D3_BASE_USART1     0xf0020000
-#define SAMA5D3_BASE_USART2     0xf8020000
-#define SAMA5D3_BASE_USART3     0xf8024000
-/*
- * System Peripherals
- */
-#define SAMA5D3_BASE_RTC        0xfffffeb0
-/*
- * Internal Memory
- */
-#define SAMA5D3_SRAM_BASE       0x00300000      /* Internal SRAM base address */
-#define SAMA5D3_SRAM_SIZE       (128 * SZ_1K)   /* Internal SRAM size (128Kb) */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
deleted file mode 100644
index f256a45d9854..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D4 family
- *
- *  Copyright (C) 2013 Atmel Corporation,
- *                     Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * Common definitions.
- * Based on SAMA5D4 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef SAMA5D4_H
-#define SAMA5D4_H
-/*
- * User Peripheral physical base addresses.
- */
-#define SAMA5D4_BASE_USART3     0xfc00c000 /* (USART3 non-secure) Base Address */
-#define SAMA5D4_BASE_PMC        0xf0018000 /* (PMC) Base Address */
-#define SAMA5D4_BASE_MPDDRC     0xf0010000 /* (MPDDRC) Base Address */
-#define SAMA5D4_BASE_PIOD       0xfc068000 /* (PIOD) Base Address */
-/* Some other peripherals */
-#define SAMA5D4_BASE_SYS2       SAMA5D4_BASE_PIOD
-/*
- * Internal Memory.
- */
-#define SAMA5D4_NS_SRAM_BASE     0x00210000      /* Internal SRAM base address Non-Secure */
-#define SAMA5D4_NS_SRAM_SIZE     (64 * SZ_1K)   /* Internal SRAM size Non-Secure part (64Kb) */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
deleted file mode 100644
index 4ebb609369e3..000000000000
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/uncompress.h
- *
- * Copyright (C) 2003 SAN People
- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <linux/io.h>
-#include <linux/atmel_serial.h>
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
-#include <mach/cpu.h>
-void __iomem *at91_uart;
-static const u32 uarts_rm9200[] = {
-        AT91_BASE_DBGU0,
-        AT91RM9200_BASE_US0,
-        AT91RM9200_BASE_US1,
-        AT91RM9200_BASE_US2,
-        AT91RM9200_BASE_US3,
-        0,
-};
-static const u32 uarts_sam9260[] = {
-        AT91_BASE_DBGU0,
-        AT91SAM9260_BASE_US0,
-        AT91SAM9260_BASE_US1,
-        AT91SAM9260_BASE_US2,
-        AT91SAM9260_BASE_US3,
-        AT91SAM9260_BASE_US4,
-        AT91SAM9260_BASE_US5,
-        0,
-};
-static const u32 uarts_sam9261[] = {
-        AT91_BASE_DBGU0,
-        AT91SAM9261_BASE_US0,
-        AT91SAM9261_BASE_US1,
-        AT91SAM9261_BASE_US2,
-        0,
-};
-static const u32 uarts_sam9263[] = {
-        AT91_BASE_DBGU1,
-        AT91SAM9263_BASE_US0,
-        AT91SAM9263_BASE_US1,
-        AT91SAM9263_BASE_US2,
-        0,
-};
-static const u32 uarts_sam9g45[] = {
-        AT91_BASE_DBGU1,
-        AT91SAM9G45_BASE_US0,
-        AT91SAM9G45_BASE_US1,
-        AT91SAM9G45_BASE_US2,
-        AT91SAM9G45_BASE_US3,
-        0,
-};
-static const u32 uarts_sam9rl[] = {
-        AT91_BASE_DBGU0,
-        AT91SAM9RL_BASE_US0,
-        AT91SAM9RL_BASE_US1,
-        AT91SAM9RL_BASE_US2,
-        AT91SAM9RL_BASE_US3,
-        0,
-};
-static const u32 uarts_sam9x5[] = {
-        AT91_BASE_DBGU0,
-        AT91SAM9X5_BASE_USART0,
-        AT91SAM9X5_BASE_USART1,
-        AT91SAM9X5_BASE_USART2,
-        0,
-};
-static const u32 uarts_sama5d3[] = {
-        AT91_BASE_DBGU1,
-        SAMA5D3_BASE_USART0,
-        SAMA5D3_BASE_USART1,
-        SAMA5D3_BASE_USART2,
-        SAMA5D3_BASE_USART3,
-        0,
-};
-static const u32 uarts_sama5d4[] = {
-        AT91_BASE_DBGU2,
-        SAMA5D4_BASE_USART3,
-        0,
-};
-static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
-{
-        u32 cidr, socid;
-        cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
-        socid = cidr & ~AT91_CIDR_VERSION;
-        switch (socid) {
-        case ARCH_ID_AT91RM9200:
-                return uarts_rm9200;
-        case ARCH_ID_AT91SAM9G20:
-        case ARCH_ID_AT91SAM9260:
-                return uarts_sam9260;
-        case ARCH_ID_AT91SAM9261:
-                return uarts_sam9261;
-        case ARCH_ID_AT91SAM9263:
-                return uarts_sam9263;
-        case ARCH_ID_AT91SAM9G45:
-                return uarts_sam9g45;
-        case ARCH_ID_AT91SAM9RL64:
-                return uarts_sam9rl;
-        case ARCH_ID_AT91SAM9N12:
-        case ARCH_ID_AT91SAM9X5:
-                return uarts_sam9x5;
-        case ARCH_ID_SAMA5:
-                cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
-                if (cidr & ARCH_EXID_SAMA5D3)
-                        return uarts_sama5d3;
-                else if (cidr & ARCH_EXID_SAMA5D4)
-                        return uarts_sama5d4;
-                break;
-        }
-        /* at91sam9g10 */
-        if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
-                return uarts_sam9261;
-        }
-        /* at91sam9xe */
-        else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
-                return uarts_sam9260;
-        }
-        return NULL;
-}
-static inline void arch_decomp_setup(void)
-{
-        int i = 0;
-        const u32* usarts;
-        usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
-        if (!usarts)
-                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
-        if (!usarts)
-                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
-        if (!usarts) {
-                at91_uart = NULL;
-                return;
-        }
-        do {
-                /* physical address */
-                at91_uart = (void __iomem *)usarts[i];
-                if (__raw_readl(at91_uart + ATMEL_US_BRGR))
-                        return;
-                i++;
-        } while (usarts[i]);
-        at91_uart = NULL;
-}
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int c)
-{
-        if (!at91_uart)
-                return;
-        while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
-                barrier();
-        __raw_writel(c, at91_uart + ATMEL_US_THR);
-}
-static inline void flush(void)
-{
-        if (!at91_uart)
-                return;
-        /* wait for transmission to complete */
-        while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
-                barrier();
-}
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index aa4116e9452f..5062699cbb12 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,19 +29,26 @@
 #include <linux/atomic.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
+#include <asm/fncpy.h>
-#include <mach/cpu.h>
+#include <asm/cacheflush.h>
-#include <mach/hardware.h>
 #include "generic.h"
 #include "pm.h"
+/*
+ * FIXME: this is needed to communicate between the pinctrl driver and
+ * the PM implementation in the machine. Possibly part of the PM
+ * implementation should be moved down into the pinctrl driver and get
+ * called as part of the generic suspend/resume path.
+ */
+extern void at91_pinctrl_gpio_suspend(void);
+extern void at91_pinctrl_gpio_resume(void);
 static struct {
        unsigned long uhp_udp_mask;
        int memctrl;
 } at91_pm_data;
-static void (*at91_pm_standby)(void);
 void __iomem *at91_ramc_base[2];
 static int at91_pm_valid_state(suspend_state_t state)
@@ -119,76 +126,67 @@ int at91_suspend_entering_slow_clock(void)
 }
 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
+static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
-static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
                          void __iomem *ramc1, int memctrl);
-#ifdef CONFIG_AT91_SLOW_CLOCK
+extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
-extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
                            void __iomem *ramc1, int memctrl);
-extern u32 at91_slow_clock_sz;
+extern u32 at91_pm_suspend_in_sram_sz;
-#endif
+static void at91_pm_suspend(suspend_state_t state)
+{
+        unsigned int pm_data = at91_pm_data.memctrl;
+        pm_data |= (state == PM_SUSPEND_MEM) ?
+                                AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+        flush_cache_all();
+        outer_disable();
+        at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
+                                at91_ramc_base[1], pm_data);
+        outer_resume();
+}
 static int at91_pm_enter(suspend_state_t state)
 {
        at91_pinctrl_gpio_suspend();
        switch (state) {
+        /*
+         * Suspend-to-RAM is like STANDBY plus slow clock mode, so
+         * drivers must suspend more deeply, the master clock switches
+         * to the clk32k and turns off the main oscillator
+         */
+        case PM_SUSPEND_MEM:
                /*
-                 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
+                 * Ensure that clocks are in a valid state.
-                 * drivers must suspend more deeply:  only the master clock
-                 * controller may be using the main oscillator.
                 */
-                case PM_SUSPEND_MEM:
+                if (!at91_pm_verify_clocks())
-                        /*
+                        goto error;
-                         * Ensure that clocks are in a valid state.
-                         */
-                        if (!at91_pm_verify_clocks())
-                                goto error;
-                        /*
-                         * Enter slow clock mode by switching over to clk32k and
-                         * turning off the main oscillator; reverse on wakeup.
-                         */
-                        if (slow_clock) {
-#ifdef CONFIG_AT91_SLOW_CLOCK
-                                /* copy slow_clock handler to SRAM, and call it */
-                                memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
-#endif
-                                slow_clock(at91_pmc_base, at91_ramc_base[0],
-                                           at91_ramc_base[1],
-                                           at91_pm_data.memctrl);
-                                break;
-                        } else {
-                                pr_info("AT91: PM - no slow clock mode enabled ...\n");
-                                /* FALLTHROUGH leaving master clock alone */
-                        }
-                /*
+                at91_pm_suspend(state);
-                 * STANDBY mode has *all* drivers suspended; ignores irqs not
-                 * marked as 'wakeup' event sources; and reduces DRAM power.
-                 * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
-                 * nothing fancy done with main or cpu clocks.
-                 */
-                case PM_SUSPEND_STANDBY:
-                        /*
-                         * NOTE: the Wait-for-Interrupt instruction needs to be
-                         * in icache so no SDRAM accesses are needed until the
-                         * wakeup IRQ occurs and self-refresh is terminated.
-                         * For ARM 926 based chips, this requirement is weaker
-                         * as at91sam9 can access a RAM in self-refresh mode.
-                         */
-                        if (at91_pm_standby)
-                                at91_pm_standby();
-                        break;
-                case PM_SUSPEND_ON:
+                break;
-                        cpu_do_idle();
-                        break;
-                default:
+        /*
-                        pr_debug("AT91: PM - bogus suspend state %d\n", state);
+         * STANDBY mode has *all* drivers suspended; ignores irqs not
-                        goto error;
+         * marked as 'wakeup' event sources; and reduces DRAM power.
+         * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
+         * nothing fancy done with main or cpu clocks.
+         */
+        case PM_SUSPEND_STANDBY:
+                at91_pm_suspend(state);
+                break;
+        case PM_SUSPEND_ON:
+                cpu_do_idle();
+                break;
+        default:
+                pr_debug("AT91: PM - bogus suspend state %d\n", state);
+                goto error;
        }
 error:
@@ -218,12 +216,99 @@ static struct platform_device at91_cpuidle_device = {
        .name = "cpuidle-at91",
 };
-void at91_pm_set_standby(void (*at91_standby)(void))
+static void at91_pm_set_standby(void (*at91_standby)(void))
 {
-        if (at91_standby) {
+        if (at91_standby)
                at91_cpuidle_device.dev.platform_data = at91_standby;
-                at91_pm_standby = at91_standby;
+}
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ *
+ * Self-refresh mode is exited as soon as a memory access is made, but we don't
+ * know for sure when that happens. However, we need to restore the low-power
+ * mode if it was enabled before going idle. Restoring low-power mode while
+ * still in self-refresh is "not recommended", but seems to work.
+ */
+static void at91rm9200_standby(void)
+{
+        u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+        asm volatile(
+                "b    1f\n\t"
+                ".align    5\n\t"
+                "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
+                "    str    %0, [%1, %2]\n\t"
+                "    str    %3, [%1, %4]\n\t"
+                "    mcr    p15, 0, %0, c7, c0, 4\n\t"
+                "    str    %5, [%1, %2]"
+                :
+                : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
+                  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+                  "r" (lpr));
+}
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static void at91_ddr_standby(void)
+{
+        /* Those two values allow us to delay self-refresh activation
+         * to the maximum. */
+        u32 lpr0, lpr1 = 0;
+        u32 saved_lpr0, saved_lpr1 = 0;
+        if (at91_ramc_base[1]) {
+                saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+                lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+                lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+        }
+        saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+        lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+        lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+        /* self-refresh mode now */
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+        cpu_do_idle();
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
+}
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static void at91sam9_sdram_standby(void)
+{
+        u32 lpr0, lpr1 = 0;
+        u32 saved_lpr0, saved_lpr1 = 0;
+        if (at91_ramc_base[1]) {
+                saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
+                lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
+                lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
        }
+        saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
+        lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
+        lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+        /* self-refresh mode now */
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+        cpu_do_idle();
+        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
 }
 static const struct of_device_id ramc_ids[] __initconst = {
@@ -263,7 +348,6 @@ static __init void at91_dt_ramc(void)
        at91_pm_set_standby(standby);
 }
-#ifdef CONFIG_AT91_SLOW_CLOCK
 static void __init at91_pm_sram_init(void)
 {
        struct gen_pool *sram_pool;
@@ -291,30 +375,36 @@ static void __init at91_pm_sram_init(void)
                return;
        }
-        sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
+        sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
        if (!sram_base) {
-                pr_warn("%s: unable to alloc ocram!\n", __func__);
+                pr_warn("%s: unable to alloc sram!\n", __func__);
                return;
        }
        sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
-        slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
+        at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
-}
+                                        at91_pm_suspend_in_sram_sz, false);
-#endif
+        if (!at91_suspend_sram_fn) {
+                pr_warn("SRAM: Could not map\n");
+                return;
+        }
+        /* Copy the pm suspend handler to SRAM */
+        at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
+                        &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
+}
 static void __init at91_pm_init(void)
 {
-#ifdef CONFIG_AT91_SLOW_CLOCK
        at91_pm_sram_init();
-#endif
-        pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
        if (at91_cpuidle_device.dev.platform_data)
                platform_device_register(&at91_cpuidle_device);
-        suspend_set_ops(&at91_pm_ops);
+        if (at91_suspend_sram_fn)
+                suspend_set_ops(&at91_pm_ops);
+        else
+                pr_info("AT91: PM not supported, due to no SRAM allocated\n");
 }
 void __init at91rm9200_pm_init(void)
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 86c0aa819d25..ecd875a91d52 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,100 +15,16 @@
 #include <mach/at91_ramc.h>
-#ifdef CONFIG_PM
+#define AT91_MEMCTRL_MC         0
-extern void at91_pm_set_standby(void (*at91_standby)(void));
+#define AT91_MEMCTRL_SDRAMC     1
-#else
+#define AT91_MEMCTRL_DDRSDR     2
-static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
-#endif
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- *
- * Self-refresh mode is exited as soon as a memory access is made, but we don't
- * know for sure when that happens. However, we need to restore the low-power
- * mode if it was enabled before going idle. Restoring low-power mode while
- * still in self-refresh is "not recommended", but seems to work.
- */
-static inline void at91rm9200_standby(void)
-{
-        u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
-        asm volatile(
-                "b    1f\n\t"
-                ".align    5\n\t"
-                "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
-                "    str    %0, [%1, %2]\n\t"
-                "    str    %3, [%1, %4]\n\t"
-                "    mcr    p15, 0, %0, c7, c0, 4\n\t"
-                "    str    %5, [%1, %2]"
-                :
-                : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
-                  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
-                  "r" (lpr));
-}
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91_ddr_standby(void)
-{
-        /* Those two values allow us to delay self-refresh activation
-         * to the maximum. */
-        u32 lpr0, lpr1 = 0;
-        u32 saved_lpr0, saved_lpr1 = 0;
-        if (at91_ramc_base[1]) {
-                saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
-                lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
-                lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-        }
-        saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
-        lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
-        lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-        /* self-refresh mode now */
-        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
-        if (at91_ramc_base[1])
-                at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
-        cpu_do_idle();
-        at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
-        if (at91_ramc_base[1])
-                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
-}
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91sam9_sdram_standby(void)
-{
-        u32 lpr0, lpr1 = 0;
-        u32 saved_lpr0, saved_lpr1 = 0;
-        if (at91_ramc_base[1]) {
-                saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
-                lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
-                lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-        }
-        saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
-        lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
-        lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-        /* self-refresh mode now */
+#define AT91_PM_MEMTYPE_MASK    0x0f
-        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
-        if (at91_ramc_base[1])
-                at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
-        cpu_do_idle();
+#define AT91_PM_MODE_OFFSET     4
+#define AT91_PM_MODE_MASK       0x01
+#define AT91_PM_MODE(x)         (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
-        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
+#define AT91_PM_SLOW_CLOCK      0x01
-        if (at91_ramc_base[1])
-                at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
deleted file mode 100644
index 931f0e302c03..000000000000
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * arch/arm/mach-at91/pm_slow_clock.S
- *
- *  Copyright (C) 2006 Savin Zlobec
- *
- * AT91SAM9 support:
- *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/linkage.h>
-#include <linux/clk/at91_pmc.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-/*
- * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
- * clock during suspend by adjusting its prescalar and divisor.
- * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
- *       are errata regarding adjusting the prescalar and divisor.
- */
-#undef SLOWDOWN_MASTER_CLOCK
-pmc     .req    r0
-sdramc  .req    r1
-ramc1   .req    r2
-memctrl .req    r3
-tmp1    .req    r4
-tmp2    .req    r5
-/*
- * Wait until master clock is ready (after switching master clock source)
- */
-        .macro wait_mckrdy
-1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     tmp1, #AT91_PMC_MCKRDY
-        beq     1b
-        .endm
-/*
- * Wait until master oscillator has stabilized.
- */
-        .macro wait_moscrdy
-1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     tmp1, #AT91_PMC_MOSCS
-        beq     1b
-        .endm
-/*
- * Wait until PLLA has locked.
- */
-        .macro wait_pllalock
-1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     tmp1, #AT91_PMC_LOCKA
-        beq     1b
-        .endm
-/*
- * Wait until PLLB has locked.
- */
-        .macro wait_pllblock
-1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     tmp1, #AT91_PMC_LOCKB
-        beq     1b
-        .endm
-        .text
-        .arm
-/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
- *                      void __iomem *ramc1, int memctrl)
- */
-ENTRY(at91_slow_clock)
-        /* Save registers on stack */
-        stmfd   sp!, {r4 - r12, lr}
-        /*
-         * Register usage:
-         *  R0 = Base address of AT91_PMC
-         *  R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
-         *  R2 = Base address of second RAM Controller or 0 if not present
-         *  R3 = Memory controller
-         *  R4 = temporary register
-         *  R5 = temporary register
-         */
-        /* Drain write buffer */
-        mov     tmp1, #0
-        mcr     p15, 0, tmp1, c7, c10, 4
-        cmp     memctrl, #AT91_MEMCTRL_MC
-        bne     ddr_sr_enable
-        /*
-         * at91rm9200 Memory controller
-         */
-        /* Put SDRAM in self-refresh mode */
-        mov     tmp1, #1
-        str     tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
-        b       sdr_sr_done
-        /*
-         * DDRSDR Memory controller
-         */
-ddr_sr_enable:
-        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
-        bne     sdr_sr_enable
-        /* LPDDR1 --> force DDR2 mode during self-refresh */
-        ldr     tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-        str     tmp1, .saved_sam9_mdr
-        bic     tmp1, tmp1, #~AT91_DDRSDRC_MD
-        cmp     tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
-        ldreq   tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-        biceq   tmp1, tmp1, #AT91_DDRSDRC_MD
-        orreq   tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
-        streq   tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-        /* prepare for DDRAM self-refresh mode */
-        ldr     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-        str     tmp1, .saved_sam9_lpr
-        bic     tmp1, #AT91_DDRSDRC_LPCB
-        orr     tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-        /* figure out if we use the second ram controller */
-        cmp     ramc1, #0
-        beq     ddr_no_2nd_ctrl
-        ldr     tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-        str     tmp2, .saved_sam9_mdr1
-        bic     tmp2, tmp2, #~AT91_DDRSDRC_MD
-        cmp     tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
-        ldreq   tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-        biceq   tmp2, tmp2, #AT91_DDRSDRC_MD
-        orreq   tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
-        streq   tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-        ldr     tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-        str     tmp2, .saved_sam9_lpr1
-        bic     tmp2, #AT91_DDRSDRC_LPCB
-        orr     tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-        /* Enable DDRAM self-refresh mode */
-        str     tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-ddr_no_2nd_ctrl:
-        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-        b       sdr_sr_done
-        /*
-         * SDRAMC Memory controller
-         */
-sdr_sr_enable:
-        /* Enable SDRAM self-refresh mode */
-        ldr     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-        str     tmp1, .saved_sam9_lpr
-        bic     tmp1, #AT91_SDRAMC_LPCB
-        orr     tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-sdr_sr_done:
-        /* Save Master clock setting */
-        ldr     tmp1, [pmc, #AT91_PMC_MCKR]
-        str     tmp1, .saved_mckr
-        /*
-         * Set the Master clock source to slow clock
-         */
-        bic     tmp1, tmp1, #AT91_PMC_CSS
-        str     tmp1, [pmc, #AT91_PMC_MCKR]
-        wait_mckrdy
-#ifdef SLOWDOWN_MASTER_CLOCK
-        /*
-         * Set the Master Clock PRES and MDIV fields.
-         *
-         * See AT91RM9200 errata #27 and #28 for details.
-         */
-        mov     tmp1, #0
-        str     tmp1, [pmc, #AT91_PMC_MCKR]
-        wait_mckrdy
-#endif
-        /* Save PLLA setting and disable it */
-        ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
-        str     tmp1, .saved_pllar
-        mov     tmp1, #AT91_PMC_PLLCOUNT
-        orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
-        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
-        /* Save PLLB setting and disable it */
-        ldr     tmp1, [pmc, #AT91_CKGR_PLLBR]
-        str     tmp1, .saved_pllbr
-        mov     tmp1, #AT91_PMC_PLLCOUNT
-        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
-        /* Turn off the main oscillator */
-        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
-        bic     tmp1, tmp1, #AT91_PMC_MOSCEN
-        orr     tmp1, tmp1, #AT91_PMC_KEY
-        str     tmp1, [pmc, #AT91_CKGR_MOR]
-        /* Wait for interrupt */
-        mcr     p15, 0, tmp1, c7, c0, 4
-        /* Turn on the main oscillator */
-        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
-        orr     tmp1, tmp1, #AT91_PMC_MOSCEN
-        orr     tmp1, tmp1, #AT91_PMC_KEY
-        str     tmp1, [pmc, #AT91_CKGR_MOR]
-        wait_moscrdy
-        /* Restore PLLB setting */
-        ldr     tmp1, .saved_pllbr
-        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
-        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
-        bne     1f
-        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
-        beq     2f
-1:
-        wait_pllblock
-2:
-        /* Restore PLLA setting */
-        ldr     tmp1, .saved_pllar
-        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
-        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
-        bne     3f
-        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
-        beq     4f
-3:
-        wait_pllalock
-4:
-#ifdef SLOWDOWN_MASTER_CLOCK
-        /*
-         * First set PRES if it was not 0,
-         * than set CSS and MDIV fields.
-         *
-         * See AT91RM9200 errata #27 and #28 for details.
-         */
-        ldr     tmp1, .saved_mckr
-        tst     tmp1, #AT91_PMC_PRES
-        beq     2f
-        and     tmp1, tmp1, #AT91_PMC_PRES
-        str     tmp1, [pmc, #AT91_PMC_MCKR]
-        wait_mckrdy
-#endif
-        /*
-         * Restore master clock setting
-         */
-2:      ldr     tmp1, .saved_mckr
-        str     tmp1, [pmc, #AT91_PMC_MCKR]
-        wait_mckrdy
-        /*
-         * at91rm9200 Memory controller
-         * Do nothing - self-refresh is automatically disabled.
-         */
-        cmp     memctrl, #AT91_MEMCTRL_MC
-        beq     ram_restored
-        /*
-         * DDRSDR Memory controller
-         */
-        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
-        bne     sdr_en_restore
-        /* Restore MDR in case of LPDDR1 */
-        ldr     tmp1, .saved_sam9_mdr
-        str     tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-        /* Restore LPR on AT91 with DDRAM */
-        ldr     tmp1, .saved_sam9_lpr
-        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-        /* if we use the second ram controller */
-        cmp     ramc1, #0
-        ldrne   tmp2, .saved_sam9_mdr1
-        strne   tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-        ldrne   tmp2, .saved_sam9_lpr1
-        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-        b       ram_restored
-        /*
-         * SDRAMC Memory controller
-         */
-sdr_en_restore:
-        /* Restore LPR on AT91 with SDRAM */
-        ldr     tmp1, .saved_sam9_lpr
-        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-ram_restored:
-        /* Restore registers, and return */
-        ldmfd   sp!, {r4 - r12, pc}
-.saved_mckr:
-        .word 0
-.saved_pllar:
-        .word 0
-.saved_pllbr:
-        .word 0
-.saved_sam9_lpr:
-        .word 0
-.saved_sam9_lpr1:
-        .word 0
-.saved_sam9_mdr:
-        .word 0
-.saved_sam9_mdr1:
-        .word 0
-ENTRY(at91_slow_clock_sz)
-        .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
new file mode 100644
index 000000000000..bd22b2c8a051
--- /dev/null
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -0,0 +1,337 @@
+/*
+ * arch/arm/mach-at91/pm_slow_clock.S
+ *
+ *  Copyright (C) 2006 Savin Zlobec
+ *
+ * AT91SAM9 support:
+ *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/clk/at91_pmc.h>
+#include <mach/at91_ramc.h>
+#include "pm.h"
+#define SRAMC_SELF_FRESH_ACTIVE         0x01
+#define SRAMC_SELF_FRESH_EXIT           0x00
+pmc     .req    r0
+tmp1    .req    r4
+tmp2    .req    r5
+/*
+ * Wait until master clock is ready (after switching master clock source)
+ */
+        .macro wait_mckrdy
+1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MCKRDY
+        beq     1b
+        .endm
+/*
+ * Wait until master oscillator has stabilized.
+ */
+        .macro wait_moscrdy
+1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MOSCS
+        beq     1b
+        .endm
+/*
+ * Wait until PLLA has locked.
+ */
+        .macro wait_pllalock
+1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_LOCKA
+        beq     1b
+        .endm
+/*
+ * Put the processor to enter the idle state
+ */
+        .macro at91_cpu_idle
+#if defined(CONFIG_CPU_V7)
+        mov     tmp1, #AT91_PMC_PCK
+        str     tmp1, [pmc, #AT91_PMC_SCDR]
+        dsb
+        wfi             @ Wait For Interrupt
+#else
+        mcr     p15, 0, tmp1, c7, c0, 4
+#endif
+        .endm
+        .text
+        .arm
+/*
+ * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
+ *                      void __iomem *ramc1, int memctrl)
+ * @input param:
+ *      @r0: base address of AT91_PMC
+ *      @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+ *      @r2: base address of second SDRAM Controller or 0 if not present
+ *      @r3: pm information
+ */
+ENTRY(at91_pm_suspend_in_sram)
+        /* Save registers on stack */
+        stmfd   sp!, {r4 - r12, lr}
+        /* Drain write buffer */
+        mov     tmp1, #0
+        mcr     p15, 0, tmp1, c7, c10, 4
+        str     r0, .pmc_base
+        str     r1, .sramc_base
+        str     r2, .sramc1_base
+        and     r0, r3, #AT91_PM_MEMTYPE_MASK
+        str     r0, .memtype
+        lsr     r0, r3, #AT91_PM_MODE_OFFSET
+        and     r0, r0, #AT91_PM_MODE_MASK
+        str     r0, .pm_mode
+        /* Active the self-refresh mode */
+        mov     r0, #SRAMC_SELF_FRESH_ACTIVE
+        bl      at91_sramc_self_refresh
+        ldr     r0, .pm_mode
+        tst     r0, #AT91_PM_SLOW_CLOCK
+        beq     skip_disable_main_clock
+        ldr     pmc, .pmc_base
+        /* Save Master clock setting */
+        ldr     tmp1, [pmc, #AT91_PMC_MCKR]
+        str     tmp1, .saved_mckr
+        /*
+         * Set the Master clock source to slow clock
+         */
+        bic     tmp1, tmp1, #AT91_PMC_CSS
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
+        wait_mckrdy
+        /* Save PLLA setting and disable it */
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
+        str     tmp1, .saved_pllar
+        mov     tmp1, #AT91_PMC_PLLCOUNT
+        orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
+        /* Turn off the main oscillator */
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        bic     tmp1, tmp1, #AT91_PMC_MOSCEN
+        orr     tmp1, tmp1, #AT91_PMC_KEY
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
+skip_disable_main_clock:
+        ldr     pmc, .pmc_base
+        /* Wait for interrupt */
+        at91_cpu_idle
+        ldr     r0, .pm_mode
+        tst     r0, #AT91_PM_SLOW_CLOCK
+        beq     skip_enable_main_clock
+        ldr     pmc, .pmc_base
+        /* Turn on the main oscillator */
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        orr     tmp1, tmp1, #AT91_PMC_MOSCEN
+        orr     tmp1, tmp1, #AT91_PMC_KEY
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
+        wait_moscrdy
+        /* Restore PLLA setting */
+        ldr     tmp1, .saved_pllar
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
+        bne     3f
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
+        beq     4f
+3:
+        wait_pllalock
+4:
+        /*
+         * Restore master clock setting
+         */
+        ldr     tmp1, .saved_mckr
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
+        wait_mckrdy
+skip_enable_main_clock:
+        /* Exit the self-refresh mode */
+        mov     r0, #SRAMC_SELF_FRESH_EXIT
+        bl      at91_sramc_self_refresh
+        /* Restore registers, and return */
+        ldmfd   sp!, {r4 - r12, pc}
+ENDPROC(at91_pm_suspend_in_sram)
+/*
+ * void at91_sramc_self_refresh(unsigned int is_active)
+ *
+ * @input param:
+ *      @r0: 1 - active self-refresh mode
+ *           0 - exit self-refresh mode
+ * register usage:
+ *      @r1: memory type
+ *      @r2: base address of the sram controller
+ */
+ENTRY(at91_sramc_self_refresh)
+        ldr     r1, .memtype
+        ldr     r2, .sramc_base
+        cmp     r1, #AT91_MEMCTRL_MC
+        bne     ddrc_sf
+        /*
+         * at91rm9200 Memory controller
+         */
+         /*
+          * For exiting the self-refresh mode, do nothing,
+          * automatically exit the self-refresh mode.
+          */
+        tst     r0, #SRAMC_SELF_FRESH_ACTIVE
+        beq     exit_sramc_sf
+        /* Active SDRAM self-refresh mode */
+        mov     r3, #1
+        str     r3, [r2, #AT91RM9200_SDRAMC_SRR]
+        b       exit_sramc_sf
+ddrc_sf:
+        cmp     r1, #AT91_MEMCTRL_DDRSDR
+        bne     sdramc_sf
+        /*
+         * DDR Memory controller
+         */
+        tst     r0, #SRAMC_SELF_FRESH_ACTIVE
+        beq     ddrc_exit_sf
+        /* LPDDR1 --> force DDR2 mode during self-refresh */
+        ldr     r3, [r2, #AT91_DDRSDRC_MDR]
+        str     r3, .saved_sam9_mdr
+        bic     r3, r3, #~AT91_DDRSDRC_MD
+        cmp     r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+        ldreq   r3, [r2, #AT91_DDRSDRC_MDR]
+        biceq   r3, r3, #AT91_DDRSDRC_MD
+        orreq   r3, r3, #AT91_DDRSDRC_MD_DDR2
+        streq   r3, [r2, #AT91_DDRSDRC_MDR]
+        /* Active DDRC self-refresh mode */
+        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     r3, .saved_sam9_lpr
+        bic     r3, r3, #AT91_DDRSDRC_LPCB
+        orr     r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        /* If using the 2nd ddr controller */
+        ldr     r2, .sramc1_base
+        cmp     r2, #0
+        beq     no_2nd_ddrc
+        ldr     r3, [r2, #AT91_DDRSDRC_MDR]
+        str     r3, .saved_sam9_mdr1
+        bic     r3, r3, #~AT91_DDRSDRC_MD
+        cmp     r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+        ldreq   r3, [r2, #AT91_DDRSDRC_MDR]
+        biceq   r3, r3, #AT91_DDRSDRC_MD
+        orreq   r3, r3, #AT91_DDRSDRC_MD_DDR2
+        streq   r3, [r2, #AT91_DDRSDRC_MDR]
+        /* Active DDRC self-refresh mode */
+        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     r3, .saved_sam9_lpr1
+        bic     r3, r3, #AT91_DDRSDRC_LPCB
+        orr     r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+no_2nd_ddrc:
+        b       exit_sramc_sf
+ddrc_exit_sf:
+        /* Restore MDR in case of LPDDR1 */
+        ldr     r3, .saved_sam9_mdr
+        str     r3, [r2, #AT91_DDRSDRC_MDR]
+        /* Restore LPR on AT91 with DDRAM */
+        ldr     r3, .saved_sam9_lpr
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        /* If using the 2nd ddr controller */
+        ldr     r2, .sramc1_base
+        cmp     r2, #0
+        ldrne   r3, .saved_sam9_mdr1
+        strne   r3, [r2, #AT91_DDRSDRC_MDR]
+        ldrne   r3, .saved_sam9_lpr1
+        strne   r3, [r2, #AT91_DDRSDRC_LPR]
+        b       exit_sramc_sf
+        /*
+         * SDRAMC Memory controller
+         */
+sdramc_sf:
+        tst     r0, #SRAMC_SELF_FRESH_ACTIVE
+        beq     sdramc_exit_sf
+        /* Active SDRAMC self-refresh mode */
+        ldr     r3, [r2, #AT91_SDRAMC_LPR]
+        str     r3, .saved_sam9_lpr
+        bic     r3, r3, #AT91_SDRAMC_LPCB
+        orr     r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_SDRAMC_LPR]
+sdramc_exit_sf:
+        ldr     r3, .saved_sam9_lpr
+        str     r3, [r2, #AT91_SDRAMC_LPR]
+exit_sramc_sf:
+        mov     pc, lr
+ENDPROC(at91_sramc_self_refresh)
+.pmc_base:
+        .word 0
+.sramc_base:
+        .word 0
+.sramc1_base:
+        .word 0
+.memtype:
+        .word 0
+.pm_mode:
+        .word 0
+.saved_mckr:
+        .word 0
+.saved_pllar:
+        .word 0
+.saved_sam9_lpr:
+        .word 0
+.saved_sam9_lpr1:
+        .word 0
+.saved_sam9_mdr:
+        .word 0
+.saved_sam9_mdr1:
+        .word 0
+ENTRY(at91_pm_suspend_in_sram_sz)
+        .word .-at91_pm_suspend_in_sram
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index 03dcb441f3d2..41d829d8e7d5 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -7,48 +7,48 @@
 * Licensed under GPLv2 or later.
 */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/micrel_phy.h>
 #include <linux/of.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/phy.h>
-#include <linux/clk-provider.h>
-#include <linux/phy.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 #include "generic.h"
+#include "soc.h"
-static int ksz8081_phy_fixup(struct phy_device *phy)
+static const struct at91_soc sama5_socs[] = {
-{
+        AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
-        int value;
+                 "sama5d31", "sama5d3"),
+        AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
-        value = phy_read(phy, 0x16);
+                 "sama5d33", "sama5d3"),
-        value &= ~0x20;
+        AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
-        phy_write(phy, 0x16, value);
+                 "sama5d34", "sama5d3"),
+        AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
-        return 0;
+                 "sama5d35", "sama5d3"),
-}
+        AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
+                 "sama5d36", "sama5d3"),
+        AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
+                 "sama5d41", "sama5d4"),
+        AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
+                 "sama5d42", "sama5d4"),
+        AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
+                 "sama5d43", "sama5d4"),
+        AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
+                 "sama5d44", "sama5d4"),
+        { /* sentinel */ },
+};
 static void __init sama5_dt_device_init(void)
 {
-        if (of_machine_is_compatible("atmel,sama5d4ek") &&
+        struct soc_device *soc;
-           IS_ENABLED(CONFIG_PHYLIB)) {
+        struct device *soc_dev = NULL;
-                phy_register_fixup_for_id("fc028000.etherne:00",
-                                                ksz8081_phy_fixup);
-        }
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        soc = at91_soc_init(sama5_socs);
+        if (soc != NULL)
+                soc_dev = soc_device_to_device(soc);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
        at91sam9x5_pm_init();
 }
@@ -59,44 +59,10 @@ static const char *sama5_dt_board_compat[] __initconst = {
 DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
        /* Maintainer: Atmel */
-        .map_io         = at91_map_io,
        .init_machine   = sama5_dt_device_init,
        .dt_compat      = sama5_dt_board_compat,
 MACHINE_END
-static struct map_desc at91_io_desc[] __initdata = {
-        {
-        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
-        .pfn            = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
-        .length         = SZ_512,
-        .type           = MT_DEVICE,
-        },
-        {
-        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
-        .pfn            = __phys_to_pfn(SAMA5D4_BASE_PMC),
-        .length         = SZ_512,
-        .type           = MT_DEVICE,
-        },
-        { /* On sama5d4, we use USART3 as serial console */
-        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
-        .pfn            = __phys_to_pfn(SAMA5D4_BASE_USART3),
-        .length         = SZ_256,
-        .type           = MT_DEVICE,
-        },
-        { /* A bunch of peripheral with fine grained IO space */
-        .virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
-        .pfn            = __phys_to_pfn(SAMA5D4_BASE_SYS2),
-        .length         = SZ_2K,
-        .type           = MT_DEVICE,
-        },
-};
-static void __init sama5_alt_map_io(void)
-{
-        at91_alt_map_io();
-        iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
-}
 static const char *sama5_alt_dt_board_compat[] __initconst = {
        "atmel,sama5d4",
        NULL
@@ -104,7 +70,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = {
 DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
        /* Maintainer: Atmel */
-        .map_io         = sama5_alt_map_io,
        .init_machine   = sama5_dt_device_init,
        .dt_compat      = sama5_alt_dt_board_compat,
        .l2c_aux_mask   = ~0UL,
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
deleted file mode 100644
index 4e58bc90ed21..000000000000
--- a/arch/arm/mach-at91/setup.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2007 Atmel Corporation.
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2
- */
-#define pr_fmt(fmt)     "AT91: " fmt
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/pm.h>
-#include <linux/of_address.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/system_misc.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include "generic.h"
-#include "pm.h"
-struct at91_socinfo at91_soc_initdata;
-EXPORT_SYMBOL(at91_soc_initdata);
-static struct map_desc at91_io_desc __initdata __maybe_unused = {
-        .virtual        = (unsigned long)AT91_VA_BASE_SYS,
-        .pfn            = __phys_to_pfn(AT91_BASE_SYS),
-        .length         = SZ_16K,
-        .type           = MT_DEVICE,
-};
-static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
-        .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
-        .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
-        .length         = 24 * SZ_1K,
-        .type           = MT_DEVICE,
-};
-static void __init soc_detect(u32 dbgu_base)
-{
-        u32 cidr, socid;
-        cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
-        socid = cidr & ~AT91_CIDR_VERSION;
-        switch (socid) {
-        case ARCH_ID_AT91RM9200:
-                at91_soc_initdata.type = AT91_SOC_RM9200;
-                if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
-                        at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
-                break;
-        case ARCH_ID_AT91SAM9260:
-                at91_soc_initdata.type = AT91_SOC_SAM9260;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-                break;
-        case ARCH_ID_AT91SAM9261:
-                at91_soc_initdata.type = AT91_SOC_SAM9261;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-                break;
-        case ARCH_ID_AT91SAM9263:
-                at91_soc_initdata.type = AT91_SOC_SAM9263;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-                break;
-        case ARCH_ID_AT91SAM9G20:
-                at91_soc_initdata.type = AT91_SOC_SAM9G20;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-                break;
-        case ARCH_ID_AT91SAM9G45:
-                at91_soc_initdata.type = AT91_SOC_SAM9G45;
-                if (cidr == ARCH_ID_AT91SAM9G45ES)
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
-                break;
-        case ARCH_ID_AT91SAM9RL64:
-                at91_soc_initdata.type = AT91_SOC_SAM9RL;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-                break;
-        case ARCH_ID_AT91SAM9X5:
-                at91_soc_initdata.type = AT91_SOC_SAM9X5;
-                break;
-        case ARCH_ID_AT91SAM9N12:
-                at91_soc_initdata.type = AT91_SOC_SAM9N12;
-                break;
-        case ARCH_ID_SAMA5:
-                at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
-                if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
-                        at91_soc_initdata.type = AT91_SOC_SAMA5D3;
-                }
-                break;
-        }
-        /* at91sam9g10 */
-        if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
-                at91_soc_initdata.type = AT91_SOC_SAM9G10;
-                at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-        }
-        /* at91sam9xe */
-        else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
-                at91_soc_initdata.type = AT91_SOC_SAM9260;
-                at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
-        }
-        if (!at91_soc_is_detected())
-                return;
-        at91_soc_initdata.cidr = cidr;
-        /* sub version of soc */
-        if (!at91_soc_initdata.exid)
-                at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
-        if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
-                switch (at91_soc_initdata.exid) {
-                case ARCH_EXID_AT91SAM9M10:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
-                        break;
-                case ARCH_EXID_AT91SAM9G46:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
-                        break;
-                case ARCH_EXID_AT91SAM9M11:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
-                        break;
-                }
-        }
-        if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
-                switch (at91_soc_initdata.exid) {
-                case ARCH_EXID_AT91SAM9G15:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
-                        break;
-                case ARCH_EXID_AT91SAM9G35:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
-                        break;
-                case ARCH_EXID_AT91SAM9X35:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
-                        break;
-                case ARCH_EXID_AT91SAM9G25:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
-                        break;
-                case ARCH_EXID_AT91SAM9X25:
-                        at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
-                        break;
-                }
-        }
-        if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
-                switch (at91_soc_initdata.exid) {
-                case ARCH_EXID_SAMA5D31:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
-                        break;
-                case ARCH_EXID_SAMA5D33:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
-                        break;
-                case ARCH_EXID_SAMA5D34:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
-                        break;
-                case ARCH_EXID_SAMA5D35:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
-                        break;
-                case ARCH_EXID_SAMA5D36:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
-                        break;
-                }
-        }
-}
-static void __init alt_soc_detect(u32 dbgu_base)
-{
-        u32 cidr, socid;
-        /* SoC ID */
-        cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
-        socid = cidr & ~AT91_CIDR_VERSION;
-        switch (socid) {
-        case ARCH_ID_SAMA5:
-                at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
-                if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
-                        at91_soc_initdata.type = AT91_SOC_SAMA5D3;
-                } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
-                        at91_soc_initdata.type = AT91_SOC_SAMA5D4;
-                }
-                break;
-        }
-        if (!at91_soc_is_detected())
-                return;
-        at91_soc_initdata.cidr = cidr;
-        /* sub version of soc */
-        if (!at91_soc_initdata.exid)
-                at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
-        if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
-                switch (at91_soc_initdata.exid) {
-                case ARCH_EXID_SAMA5D41:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
-                        break;
-                case ARCH_EXID_SAMA5D42:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
-                        break;
-                case ARCH_EXID_SAMA5D43:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
-                        break;
-                case ARCH_EXID_SAMA5D44:
-                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
-                        break;
-                }
-        }
-}
-static const char *soc_name[] = {
-        [AT91_SOC_RM9200]       = "at91rm9200",
-        [AT91_SOC_SAM9260]      = "at91sam9260",
-        [AT91_SOC_SAM9261]      = "at91sam9261",
-        [AT91_SOC_SAM9263]      = "at91sam9263",
-        [AT91_SOC_SAM9G10]      = "at91sam9g10",
-        [AT91_SOC_SAM9G20]      = "at91sam9g20",
-        [AT91_SOC_SAM9G45]      = "at91sam9g45",
-        [AT91_SOC_SAM9RL]       = "at91sam9rl",
-        [AT91_SOC_SAM9X5]       = "at91sam9x5",
-        [AT91_SOC_SAM9N12]      = "at91sam9n12",
-        [AT91_SOC_SAMA5D3]      = "sama5d3",
-        [AT91_SOC_SAMA5D4]      = "sama5d4",
-        [AT91_SOC_UNKNOWN]      = "Unknown",
-};
-const char *at91_get_soc_type(struct at91_socinfo *c)
-{
-        return soc_name[c->type];
-}
-EXPORT_SYMBOL(at91_get_soc_type);
-static const char *soc_subtype_name[] = {
-        [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
-        [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
-        [AT91_SOC_SAM9XE]       = "at91sam9xe",
-        [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
-        [AT91_SOC_SAM9M10]      = "at91sam9m10",
-        [AT91_SOC_SAM9G46]      = "at91sam9g46",
-        [AT91_SOC_SAM9M11]      = "at91sam9m11",
-        [AT91_SOC_SAM9G15]      = "at91sam9g15",
-        [AT91_SOC_SAM9G35]      = "at91sam9g35",
-        [AT91_SOC_SAM9X35]      = "at91sam9x35",
-        [AT91_SOC_SAM9G25]      = "at91sam9g25",
-        [AT91_SOC_SAM9X25]      = "at91sam9x25",
-        [AT91_SOC_SAMA5D31]     = "sama5d31",
-        [AT91_SOC_SAMA5D33]     = "sama5d33",
-        [AT91_SOC_SAMA5D34]     = "sama5d34",
-        [AT91_SOC_SAMA5D35]     = "sama5d35",
-        [AT91_SOC_SAMA5D36]     = "sama5d36",
-        [AT91_SOC_SAMA5D41]     = "sama5d41",
-        [AT91_SOC_SAMA5D42]     = "sama5d42",
-        [AT91_SOC_SAMA5D43]     = "sama5d43",
-        [AT91_SOC_SAMA5D44]     = "sama5d44",
-        [AT91_SOC_SUBTYPE_NONE] = "None",
-        [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
-};
-const char *at91_get_soc_subtype(struct at91_socinfo *c)
-{
-        return soc_subtype_name[c->subtype];
-}
-EXPORT_SYMBOL(at91_get_soc_subtype);
-void __init at91_map_io(void)
-{
-        /* Map peripherals */
-        iotable_init(&at91_io_desc, 1);
-        at91_soc_initdata.type = AT91_SOC_UNKNOWN;
-        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
-        soc_detect(AT91_BASE_DBGU0);
-        if (!at91_soc_is_detected())
-                soc_detect(AT91_BASE_DBGU1);
-        if (!at91_soc_is_detected())
-                panic(pr_fmt("Impossible to detect the SOC type"));
-        pr_info("Detected soc type: %s\n",
-                at91_get_soc_type(&at91_soc_initdata));
-        if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
-                pr_info("Detected soc subtype: %s\n",
-                        at91_get_soc_subtype(&at91_soc_initdata));
-}
-void __init at91_alt_map_io(void)
-{
-        /* Map peripherals */
-        iotable_init(&at91_alt_io_desc, 1);
-        at91_soc_initdata.type = AT91_SOC_UNKNOWN;
-        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
-        alt_soc_detect(AT91_BASE_DBGU2);
-        if (!at91_soc_is_detected())
-                panic("AT91: Impossible to detect the SOC type");
-        pr_info("AT91: Detected soc type: %s\n",
-                at91_get_soc_type(&at91_soc_initdata));
-        if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
-                pr_info("AT91: Detected soc subtype: %s\n",
-                        at91_get_soc_subtype(&at91_soc_initdata));
-}
-void __iomem *at91_matrix_base;
-EXPORT_SYMBOL_GPL(at91_matrix_base);
-void __init at91_ioremap_matrix(u32 base_addr)
-{
-        at91_matrix_base = ioremap(base_addr, 512);
-        if (!at91_matrix_base)
-                panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
-}
diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c
new file mode 100644
index 000000000000..54343ffa3e53
--- /dev/null
+++ b/arch/arm/mach-at91/soc.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2015 Atmel
+ *
+ * Alexandre Belloni <alexandre.belloni@free-electrons.com
+ * Boris Brezillon <boris.brezillon@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+#define pr_fmt(fmt)     "AT91: " fmt
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+#include "soc.h"
+#define AT91_DBGU_CIDR                  0x40
+#define AT91_DBGU_CIDR_VERSION(x)       ((x) & 0x1f)
+#define AT91_DBGU_CIDR_EXT              BIT(31)
+#define AT91_DBGU_CIDR_MATCH_MASK       0x7fffffe0
+#define AT91_DBGU_EXID                  0x44
+struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
+{
+        struct soc_device_attribute *soc_dev_attr;
+        const struct at91_soc *soc;
+        struct soc_device *soc_dev;
+        struct device_node *np;
+        void __iomem *regs;
+        u32 cidr, exid;
+        np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
+        if (!np)
+                np = of_find_compatible_node(NULL, NULL,
+                                             "atmel,at91sam9260-dbgu");
+        if (!np) {
+                pr_warn("Could not find DBGU node");
+                return NULL;
+        }
+        regs = of_iomap(np, 0);
+        of_node_put(np);
+        if (!regs) {
+                pr_warn("Could not map DBGU iomem range");
+                return NULL;
+        }
+        cidr = readl(regs + AT91_DBGU_CIDR);
+        exid = readl(regs + AT91_DBGU_EXID);
+        iounmap(regs);
+        for (soc = socs; soc->name; soc++) {
+                if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK))
+                        continue;
+                if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid)
+                        break;
+        }
+        if (!soc->name) {
+                pr_warn("Could not find matching SoC description\n");
+                return NULL;
+        }
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return NULL;
+        soc_dev_attr->family = soc->family;
+        soc_dev_attr->soc_id = soc->name;
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
+                                           AT91_DBGU_CIDR_VERSION(cidr));
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                pr_warn("Could not register SoC device\n");
+                return NULL;
+        }
+        if (soc->family)
+                pr_info("Detected SoC family: %s\n", soc->family);
+        pr_info("Detected SoC: %s, revision %X\n", soc->name,
+                AT91_DBGU_CIDR_VERSION(cidr));
+        return soc_dev;
+}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
new file mode 100644
index 000000000000..be23c400596b
--- /dev/null
+++ b/arch/arm/mach-at91/soc.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2015 Atmel
+ *
+ * Boris Brezillon <boris.brezillon@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+#ifndef __AT91_SOC_H
+#define __AT91_SOC_H
+#include <linux/sys_soc.h>
+struct at91_soc {
+        u32 cidr_match;
+        u32 exid_match;
+        const char *name;
+        const char *family;
+};
+#define AT91_SOC(__cidr, __exid, __name, __family)              \
+        {                                                       \
+                .cidr_match = (__cidr),                         \
+                .exid_match = (__exid),                         \
+                .name = (__name),                               \
+                .family = (__family),                           \
+        }
+struct soc_device * __init
+at91_soc_init(const struct at91_soc *socs);
+#define AT91RM9200_CIDR_MATCH           0x09290780
+#define AT91SAM9260_CIDR_MATCH          0x019803a0
+#define AT91SAM9261_CIDR_MATCH          0x019703a0
+#define AT91SAM9263_CIDR_MATCH          0x019607a0
+#define AT91SAM9G20_CIDR_MATCH          0x019905a0
+#define AT91SAM9RL64_CIDR_MATCH         0x019b03a0
+#define AT91SAM9G45_CIDR_MATCH          0x019b05a0
+#define AT91SAM9X5_CIDR_MATCH           0x019a05a0
+#define AT91SAM9N12_CIDR_MATCH          0x019a07a0
+#define AT91SAM9M11_EXID_MATCH          0x00000001
+#define AT91SAM9M10_EXID_MATCH          0x00000002
+#define AT91SAM9G46_EXID_MATCH          0x00000003
+#define AT91SAM9G45_EXID_MATCH          0x00000004
+#define AT91SAM9G15_EXID_MATCH          0x00000000
+#define AT91SAM9G35_EXID_MATCH          0x00000001
+#define AT91SAM9X35_EXID_MATCH          0x00000002
+#define AT91SAM9G25_EXID_MATCH          0x00000003
+#define AT91SAM9X25_EXID_MATCH          0x00000004
+#define AT91SAM9CN12_EXID_MATCH         0x00000005
+#define AT91SAM9N12_EXID_MATCH          0x00000006
+#define AT91SAM9CN11_EXID_MATCH         0x00000009
+#define AT91SAM9XE128_CIDR_MATCH        0x329973a0
+#define AT91SAM9XE256_CIDR_MATCH        0x329a93a0
+#define AT91SAM9XE512_CIDR_MATCH        0x329aa3a0
+#define SAMA5D3_CIDR_MATCH              0x0a5c07c0
+#define SAMA5D31_EXID_MATCH             0x00444300
+#define SAMA5D33_EXID_MATCH             0x00414300
+#define SAMA5D34_EXID_MATCH             0x00414301
+#define SAMA5D35_EXID_MATCH             0x00584300
+#define SAMA5D36_EXID_MATCH             0x00004301
+#define SAMA5D4_CIDR_MATCH              0x0a5c07c0
+#define SAMA5D41_EXID_MATCH             0x00000001
+#define SAMA5D42_EXID_MATCH             0x00000002
+#define SAMA5D43_EXID_MATCH             0x00000003
+#define SAMA5D44_EXID_MATCH             0x00000004
+#endif /* __AT91_SOC_H */
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
index 30dc58be51b8..7ae894c7849b 100644
--- a/arch/arm/mach-bcm/bcm_cygnus.c
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -13,7 +13,7 @@
 #include <asm/mach/arch.h>
-static const char const *bcm_cygnus_dt_compat[] = {
+static const char * const bcm_cygnus_dt_compat[] __initconst = {
        "brcm,cygnus",
        NULL,
 };
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index fb38c726e987..f46b78dd6136 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -73,7 +73,6 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
        __raw_writel(reg, PM_SOFT_RST_REG);
 }
-EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
 void cns3xxx_pwr_soft_rst(unsigned int block)
 {
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index cd30f6f5f2ff..dd8f5312b2c0 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -200,17 +200,6 @@ config DA850_UI_SD_VIDEO_PORT
 endchoice
-config DA850_WL12XX
-        bool "AM18x wl1271 daughter board"
-        depends on MACH_DAVINCI_DA850_EVM
-        help
-          The wl1271 daughter card for AM18x EVMs is a combo wireless
-          connectivity add-on card, based on the LS Research TiWi module with
-          Texas Instruments' wl1271 solution.
-          Say Y if you want to use a wl1271 expansion card connected to the
-          AM18x EVM.
 config MACH_MITYOMAPL138
        bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
        depends on ARCH_DAVINCI_DA850
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
index d9b2acd12393..1128e1d8e4b4 100644
--- a/arch/arm/mach-davinci/asp.h
+++ b/arch/arm/mach-davinci/asp.h
@@ -21,6 +21,9 @@
 /* Bases of da830 McASP1 register banks */
 #define DAVINCI_DA830_MCASP1_REG_BASE   0x01D04000
+/* Bases of da830 McASP2 register banks */
+#define DAVINCI_DA830_MCASP2_REG_BASE   0x01D08000
 /* EDMA channels of dm644x and dm355 */
 #define DAVINCI_DMA_ASP0_TX     2
 #define DAVINCI_DMA_ASP0_RX     3
@@ -40,6 +43,10 @@
 #define DAVINCI_DA830_DMA_MCASP1_AREVT  2
 #define DAVINCI_DA830_DMA_MCASP1_AXEVT  3
+/* EDMA channels of da830 McASP2 */
+#define DAVINCI_DA830_DMA_MCASP2_AREVT  4
+#define DAVINCI_DA830_DMA_MCASP2_AXEVT  5
 /* Interrupts */
 #define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
 #define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6b5a97da9fe3..1ed545cc2b83 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -38,7 +38,6 @@
 #include <linux/regulator/fixed.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#include <linux/wl12xx.h>
 #include <mach/common.h>
 #include <mach/cp_intc.h>
@@ -60,9 +59,6 @@
 #define DA850_MMCSD_CD_PIN              GPIO_TO_PIN(4, 0)
 #define DA850_MMCSD_WP_PIN              GPIO_TO_PIN(4, 1)
-#define DA850_WLAN_EN                   GPIO_TO_PIN(6, 9)
-#define DA850_WLAN_IRQ                  GPIO_TO_PIN(6, 10)
 #define DA850_MII_MDIO_CLKEN_PIN        GPIO_TO_PIN(2, 6)
 static struct mtd_partition da850evm_spiflash_part[] = {
@@ -1343,109 +1339,6 @@ static __init void da850_vpif_init(void)
 static __init void da850_vpif_init(void) {}
 #endif
-#ifdef CONFIG_DA850_WL12XX
-static void wl12xx_set_power(int index, bool power_on)
-{
-        static bool power_state;
-        pr_debug("Powering %s wl12xx", power_on ? "on" : "off");
-        if (power_on == power_state)
-                return;
-        power_state = power_on;
-        if (power_on) {
-                /* Power up sequence required for wl127x devices */
-                gpio_set_value(DA850_WLAN_EN, 1);
-                usleep_range(15000, 15000);
-                gpio_set_value(DA850_WLAN_EN, 0);
-                usleep_range(1000, 1000);
-                gpio_set_value(DA850_WLAN_EN, 1);
-                msleep(70);
-        } else {
-                gpio_set_value(DA850_WLAN_EN, 0);
-        }
-}
-static struct davinci_mmc_config da850_wl12xx_mmc_config = {
-        .set_power      = wl12xx_set_power,
-        .wires          = 4,
-        .max_freq       = 25000000,
-        .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
-                          MMC_CAP_POWER_OFF_CARD,
-};
-static const short da850_wl12xx_pins[] __initconst = {
-        DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2,
-        DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD,
-        DA850_GPIO6_9, DA850_GPIO6_10,
-        -1
-};
-static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
-        .irq                    = -1,
-        .board_ref_clock        = WL12XX_REFCLOCK_38,
-        .platform_quirks        = WL12XX_PLATFORM_QUIRK_EDGE_IRQ,
-};
-static __init int da850_wl12xx_init(void)
-{
-        int ret;
-        ret = davinci_cfg_reg_list(da850_wl12xx_pins);
-        if (ret) {
-                pr_err("wl12xx/mmc mux setup failed: %d\n", ret);
-                goto exit;
-        }
-        ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config);
-        if (ret) {
-                pr_err("wl12xx/mmc registration failed: %d\n", ret);
-                goto exit;
-        }
-        ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en");
-        if (ret) {
-                pr_err("Could not request wl12xx enable gpio: %d\n", ret);
-                goto exit;
-        }
-        ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq");
-        if (ret) {
-                pr_err("Could not request wl12xx irq gpio: %d\n", ret);
-                goto free_wlan_en;
-        }
-        da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ);
-        ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data);
-        if (ret) {
-                pr_err("Could not set wl12xx data: %d\n", ret);
-                goto free_wlan_irq;
-        }
-        return 0;
-free_wlan_irq:
-        gpio_free(DA850_WLAN_IRQ);
-free_wlan_en:
-        gpio_free(DA850_WLAN_EN);
-exit:
-        return ret;
-}
-#else /* CONFIG_DA850_WL12XX */
-static __init int da850_wl12xx_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_DA850_WL12XX */
 #define DA850EVM_SATA_REFCLKPN_RATE     (100 * 1000 * 1000)
 static __init void da850_evm_init(void)
@@ -1502,11 +1395,6 @@ static __init void da850_evm_init(void)
                if (ret)
                        pr_warn("%s: MMCSD0 registration failed: %d\n",
                                __func__, ret);
-                ret = da850_wl12xx_init();
-                if (ret)
-                        pr_warn("%s: WL12xx initialization failed: %d\n",
-                                __func__, ret);
        }
        davinci_serial_init(da8xx_serial_device);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index b85b781b05fd..ddfdd820e6f2 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -463,16 +463,23 @@ static struct resource da830_mcasp1_resources[] = {
        },
        /* TX event */
        {
+                .name   = "tx",
                .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
                .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
                .flags  = IORESOURCE_DMA,
        },
        /* RX event */
        {
+                .name   = "rx",
                .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
                .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
                .flags  = IORESOURCE_DMA,
        },
+        {
+                .name   = "common",
+                .start  = IRQ_DA8XX_MCASPINT,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device da830_mcasp1_device = {
@@ -482,6 +489,41 @@ static struct platform_device da830_mcasp1_device = {
        .resource       = da830_mcasp1_resources,
 };
+static struct resource da830_mcasp2_resources[] = {
+        {
+                .name   = "mpu",
+                .start  = DAVINCI_DA830_MCASP2_REG_BASE,
+                .end    = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* TX event */
+        {
+                .name   = "tx",
+                .start  = DAVINCI_DA830_DMA_MCASP2_AXEVT,
+                .end    = DAVINCI_DA830_DMA_MCASP2_AXEVT,
+                .flags  = IORESOURCE_DMA,
+        },
+        /* RX event */
+        {
+                .name   = "rx",
+                .start  = DAVINCI_DA830_DMA_MCASP2_AREVT,
+                .end    = DAVINCI_DA830_DMA_MCASP2_AREVT,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .name   = "common",
+                .start  = IRQ_DA8XX_MCASPINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device da830_mcasp2_device = {
+        .name           = "davinci-mcasp",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(da830_mcasp2_resources),
+        .resource       = da830_mcasp2_resources,
+};
 static struct resource da850_mcasp_resources[] = {
        {
                .name   = "mpu",
@@ -491,16 +533,23 @@ static struct resource da850_mcasp_resources[] = {
        },
        /* TX event */
        {
+                .name   = "tx",
                .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
                .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
                .flags  = IORESOURCE_DMA,
        },
        /* RX event */
        {
+                .name   = "rx",
                .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
                .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
                .flags  = IORESOURCE_DMA,
        },
+        {
+                .name   = "common",
+                .start  = IRQ_DA8XX_MCASPINT,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device da850_mcasp_device = {
@@ -512,14 +561,31 @@ static struct platform_device da850_mcasp_device = {
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
-        /* DA830/OMAP-L137 has 3 instances of McASP */
+        struct platform_device *pdev;
-        if (cpu_is_davinci_da830() && id == 1) {
-                da830_mcasp1_device.dev.platform_data = pdata;
+        switch (id) {
-                platform_device_register(&da830_mcasp1_device);
+        case 0:
-        } else if (cpu_is_davinci_da850()) {
+                /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
-                da850_mcasp_device.dev.platform_data = pdata;
+                pdev = &da850_mcasp_device;
-                platform_device_register(&da850_mcasp_device);
+                break;
+        case 1:
+                /* Valid for DA830/OMAP-L137 only */
+                if (!cpu_is_davinci_da830())
+                        return;
+                pdev = &da830_mcasp1_device;
+                break;
+        case 2:
+                /* Valid for DA830/OMAP-L137 only */
+                if (!cpu_is_davinci_da830())
+                        return;
+                pdev = &da830_mcasp2_device;
+                break;
+        default:
+                return;
        }
+        pdev->dev.platform_data = pdata;
+        platform_device_register(pdev);
 }
 static struct resource da8xx_pruss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 6c3bbea7d77d..3f842bb266d6 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
        [IRQ_DM646X_EMACMISCINT]        = 7,
        [IRQ_DM646X_MCASP0TXINT]        = 7,
        [IRQ_DM646X_MCASP0RXINT]        = 7,
-        [IRQ_AEMIFINT]                  = 7,
        [IRQ_DM646X_RESERVED_3]         = 7,
        [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
        [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
@@ -610,19 +609,31 @@ static struct resource dm646x_mcasp0_resources[] = {
                .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
                .flags  = IORESOURCE_MEM,
        },
-        /* first TX, then RX */
        {
+                .name   = "tx",
                .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
                .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
                .flags  = IORESOURCE_DMA,
        },
        {
+                .name   = "rx",
                .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
                .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
                .flags  = IORESOURCE_DMA,
        },
+        {
+                .name   = "tx",
+                .start  = IRQ_DM646X_MCASP0TXINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "rx",
+                .start  = IRQ_DM646X_MCASP0RXINT,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
+/* DIT mode only, rx is not supported */
 static struct resource dm646x_mcasp1_resources[] = {
        {
                .name   = "mpu",
@@ -630,17 +641,16 @@ static struct resource dm646x_mcasp1_resources[] = {
                .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
                .flags  = IORESOURCE_MEM,
        },
-        /* DIT mode, only TX event */
        {
+                .name   = "tx",
                .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
                .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
                .flags  = IORESOURCE_DMA,
        },
-        /* DIT mode, dummy entry */
        {
-                .start  = -1,
+                .name   = "tx",
-                .end    = -1,
+                .start  = IRQ_DM646X_MCASP1TXINT,
-                .flags  = IORESOURCE_DMA,
+                .flags  = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dc..edb2ca62321a 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -129,8 +129,8 @@
 #define IRQ_DM646X_EMACMISCINT  27
 #define IRQ_DM646X_MCASP0TXINT  28
 #define IRQ_DM646X_MCASP0RXINT  29
+#define IRQ_DM646X_MCASP1TXINT  30
 #define IRQ_DM646X_RESERVED_3   31
-#define IRQ_DM646X_MCASP1TXINT  32
 #define IRQ_DM646X_VLQINT       38
 #define IRQ_DM646X_UARTINT2     42
 #define IRQ_DM646X_SPINT0       43
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 603820e5aba7..81064cd61a0a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -123,7 +123,7 @@ config SOC_EXYNOS5800
 config EXYNOS5420_MCPM
        bool "Exynos5420 Multi-Cluster PM support"
        depends on MCPM && SOC_EXYNOS5420
-        select ARM_CCI
+        select ARM_CCI400_PORT_CTRL
        select ARM_CPU_SUSPEND
        help
          This is needed to provide CPU and cluster power management
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f70eca7ee705..acd5b560b728 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -126,6 +126,12 @@ enum {
 void exynos_firmware_init(void);
+/* CPU BOOT mode flag for Exynos3250 SoC bootloader */
+#define C2_STATE        (1 << 3)
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
 extern u32 exynos_get_eint_wake_mask(void);
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f44c2e05c82e..bcde0dd668df 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -206,7 +206,7 @@ static void __init exynos_dt_machine_init(void)
        if (!IS_ENABLED(CONFIG_SMP))
                exynos_sysram_init();
-#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
+#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
        if (of_machine_is_compatible("samsung,exynos4210"))
                exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
 #endif
@@ -214,6 +214,7 @@ static void __init exynos_dt_machine_init(void)
            of_machine_is_compatible("samsung,exynos4212") ||
            (of_machine_is_compatible("samsung,exynos4412") &&
             of_machine_is_compatible("samsung,trats2")) ||
+            of_machine_is_compatible("samsung,exynos3250") ||
            of_machine_is_compatible("samsung,exynos5250"))
                platform_device_register(&exynos_cpuidle);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 4791a3cc00f9..1bd35763f12e 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,7 +48,13 @@ static int exynos_do_idle(unsigned long mode)
                __raw_writel(virt_to_phys(exynos_cpu_resume_ns),
                             sysram_ns_base_addr + 0x24);
                __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
-                exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
+                if (soc_is_exynos3250()) {
+                        exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
+                                   SMC_POWERSTATE_IDLE, 0);
+                        exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
+                                   SMC_POWERSTATE_IDLE, 0);
+                } else
+                        exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
                break;
        case FW_DO_IDLE_SLEEP:
                exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
@@ -206,3 +212,28 @@ void __init exynos_firmware_init(void)
                outer_cache.configure = exynos_l2_configure;
        }
 }
+#define REG_CPU_STATE_ADDR      (sysram_ns_base_addr + 0x28)
+#define BOOT_MODE_MASK          0x1f
+void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+        unsigned int tmp;
+        tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+        if (mode & BOOT_MODE_MASK)
+                tmp &= ~BOOT_MODE_MASK;
+        tmp |= mode;
+        __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
+void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
+{
+        unsigned int tmp;
+        tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+        tmp &= ~mode;
+        __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+}
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index b0d3c2e876fb..9bdf54795f05 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -61,25 +61,7 @@ static void __iomem *ns_sram_base_addr;
        : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
          "r9", "r10", "lr", "memory")
-/*
+static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
- * We can't use regular spinlocks. In the switcher case, it is possible
- * for an outbound CPU to call power_down() after its inbound counterpart
- * is already live using the same logical CPU number which trips lockdep
- * debugging.
- */
-static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
-static int
-cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
-#define exynos_cluster_usecnt(cluster) \
-        (cpu_use_count[0][cluster] +   \
-         cpu_use_count[1][cluster] +   \
-         cpu_use_count[2][cluster] +   \
-         cpu_use_count[3][cluster])
-#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
-static int exynos_power_up(unsigned int cpu, unsigned int cluster)
 {
        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
@@ -88,127 +70,65 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
                cluster >= EXYNOS5420_NR_CLUSTERS)
                return -EINVAL;
-        /*
+        exynos_cpu_power_up(cpunr);
-         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+        return 0;
-         * variant exists, we need to disable IRQs manually here.
+}
-         */
-        local_irq_disable();
-        arch_spin_lock(&exynos_mcpm_lock);
-        cpu_use_count[cpu][cluster]++;
-        if (cpu_use_count[cpu][cluster] == 1) {
-                bool was_cluster_down =
-                        (exynos_cluster_usecnt(cluster) == 1);
-                /*
-                 * Turn on the cluster (L2/COMMON) and then power on the
-                 * cores.
-                 */
-                if (was_cluster_down)
-                        exynos_cluster_power_up(cluster);
-                exynos_cpu_power_up(cpunr);
-        } else if (cpu_use_count[cpu][cluster] != 2) {
-                /*
-                 * The only possible values are:
-                 * 0 = CPU down
-                 * 1 = CPU (still) up
-                 * 2 = CPU requested to be up before it had a chance
-                 *     to actually make itself down.
-                 * Any other value is a bug.
-                 */
-                BUG();
-        }
-        arch_spin_unlock(&exynos_mcpm_lock);
+static int exynos_cluster_powerup(unsigned int cluster)
-        local_irq_enable();
+{
+        pr_debug("%s: cluster %u\n", __func__, cluster);
+        if (cluster >= EXYNOS5420_NR_CLUSTERS)
+                return -EINVAL;
+        exynos_cluster_power_up(cluster);
        return 0;
 }
-/*
+static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
- * NOTE: This function requires the stack data to be visible through power down
- * and can only be executed on processors like A15 and A7 that hit the cache
- * with the C bit clear in the SCTLR register.
- */
-static void exynos_power_down(void)
 {
-        unsigned int mpidr, cpu, cluster;
+        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
-        bool last_man = false, skip_wfi = false;
-        unsigned int cpunr;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
                        cluster >= EXYNOS5420_NR_CLUSTERS);
+        exynos_cpu_power_down(cpunr);
+}
-        __mcpm_cpu_going_down(cpu, cluster);
+static void exynos_cluster_powerdown_prepare(unsigned int cluster)
+{
-        arch_spin_lock(&exynos_mcpm_lock);
+        pr_debug("%s: cluster %u\n", __func__, cluster);
-        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
-        cpu_use_count[cpu][cluster]--;
+        exynos_cluster_power_down(cluster);
-        if (cpu_use_count[cpu][cluster] == 0) {
+}
-                exynos_cpu_power_down(cpunr);
-                if (exynos_cluster_unused(cluster)) {
-                        exynos_cluster_power_down(cluster);
-                        last_man = true;
-                }
-        } else if (cpu_use_count[cpu][cluster] == 1) {
-                /*
-                 * A power_up request went ahead of us.
-                 * Even if we do not want to shut this CPU down,
-                 * the caller expects a certain state as if the WFI
-                 * was aborted.  So let's continue with cache cleaning.
-                 */
-                skip_wfi = true;
-        } else {
-                BUG();
-        }
-        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
-                arch_spin_unlock(&exynos_mcpm_lock);
-                if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
-                        /*
-                         * On the Cortex-A15 we need to disable
-                         * L2 prefetching before flushing the cache.
-                         */
-                        asm volatile(
-                        "mcr    p15, 1, %0, c15, c0, 3\n\t"
-                        "isb\n\t"
-                        "dsb"
-                        : : "r" (0x400));
-                }
-                /* Flush all cache levels for this cluster. */
+static void exynos_cpu_cache_disable(void)
-                exynos_v7_exit_coherency_flush(all);
+{
+        /* Disable and flush the local CPU cache. */
+        exynos_v7_exit_coherency_flush(louis);
+}
+static void exynos_cluster_cache_disable(void)
+{
+        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
                /*
-                 * Disable cluster-level coherency by masking
+                 * On the Cortex-A15 we need to disable
-                 * incoming snoops and DVM messages:
+                 * L2 prefetching before flushing the cache.
                 */
-                cci_disable_port_by_cpu(mpidr);
+                asm volatile(
+                "mcr    p15, 1, %0, c15, c0, 3\n\t"
-                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+                "isb\n\t"
-        } else {
+                "dsb"
-                arch_spin_unlock(&exynos_mcpm_lock);
+                : : "r" (0x400));
-                /* Disable and flush the local CPU cache. */
-                exynos_v7_exit_coherency_flush(louis);
        }
-        __mcpm_cpu_down(cpu, cluster);
+        /* Flush all cache levels for this cluster. */
+        exynos_v7_exit_coherency_flush(all);
-        /* Now we are prepared for power-down, do it: */
-        if (!skip_wfi)
-                wfi();
-        /* Not dead at this point?  Let our caller cope. */
+        /*
+         * Disable cluster-level coherency by masking
+         * incoming snoops and DVM messages:
+         */
+        cci_disable_port_by_cpu(read_cpuid_mpidr());
 }
 static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
@@ -222,10 +142,8 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
        /* Wait for the core state to be OFF */
        while (tries--) {
-                if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                if ((exynos_cpu_power_state(cpunr) == 0))
-                        if ((exynos_cpu_power_state(cpunr) == 0))
+                        return 0; /* success: the CPU is halted */
-                                return 0; /* success: the CPU is halted */
-                }
                /* Otherwise, wait and retry: */
                msleep(1);
@@ -234,63 +152,23 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
        return -ETIMEDOUT; /* timeout */
 }
-static void exynos_powered_up(void)
+static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
-{
-        unsigned int mpidr, cpu, cluster;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        arch_spin_lock(&exynos_mcpm_lock);
-        if (cpu_use_count[cpu][cluster] == 0)
-                cpu_use_count[cpu][cluster] = 1;
-        arch_spin_unlock(&exynos_mcpm_lock);
-}
-static void exynos_suspend(u64 residency)
 {
-        unsigned int mpidr, cpunr;
+        /* especially when resuming: make sure power control is set */
+        exynos_cpu_powerup(cpu, cluster);
-        exynos_power_down();
-        /*
-         * Execution reaches here only if cpu did not power down.
-         * Hence roll back the changes done in exynos_power_down function.
-         *
-         * CAUTION: "This function requires the stack data to be visible through
-         * power down and can only be executed on processors like A15 and A7
-         * that hit the cache with the C bit clear in the SCTLR register."
-        */
-        mpidr = read_cpuid_mpidr();
-        cpunr = exynos_pmu_cpunr(mpidr);
-        exynos_cpu_power_up(cpunr);
 }
 static const struct mcpm_platform_ops exynos_power_ops = {
-        .power_up               = exynos_power_up,
+        .cpu_powerup            = exynos_cpu_powerup,
-        .power_down             = exynos_power_down,
+        .cluster_powerup        = exynos_cluster_powerup,
+        .cpu_powerdown_prepare  = exynos_cpu_powerdown_prepare,
+        .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
+        .cpu_cache_disable      = exynos_cpu_cache_disable,
+        .cluster_cache_disable  = exynos_cluster_cache_disable,
        .wait_for_powerdown     = exynos_wait_for_powerdown,
-        .suspend                = exynos_suspend,
+        .cpu_is_up              = exynos_cpu_is_up,
-        .powered_up             = exynos_powered_up,
 };
-static void __init exynos_mcpm_usage_count_init(void)
-{
-        unsigned int mpidr, cpu, cluster;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
-        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
-                        cluster >= EXYNOS5420_NR_CLUSTERS);
-        cpu_use_count[cpu][cluster] = 1;
-}
 /*
 * Enable cluster-level coherency, in preparation for turning on the MMU.
 */
@@ -302,19 +180,6 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
        "b      cci_enable_port_for_self");
 }
-static void __init exynos_cache_off(void)
-{
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
-                /* disable L2 prefetching on the Cortex-A15 */
-                asm volatile(
-                "mcr    p15, 1, %0, c15, c0, 3\n\t"
-                "isb\n\t"
-                "dsb"
-                : : "r" (0x400));
-        }
-        exynos_v7_exit_coherency_flush(all);
-}
 static const struct of_device_id exynos_dt_mcpm_match[] = {
        { .compatible = "samsung,exynos5420" },
        { .compatible = "samsung,exynos5800" },
@@ -370,13 +235,11 @@ static int __init exynos_mcpm_init(void)
         */
        pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
-        exynos_mcpm_usage_count_init();
        ret = mcpm_platform_register(&exynos_power_ops);
        if (!ret)
                ret = mcpm_sync_init(exynos_pm_power_up_setup);
        if (!ret)
-                ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
+                ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
        if (ret) {
                iounmap(ns_sram_base_addr);
                return ret;
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d2e9f12d12f1..ebd135bb0995 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -126,6 +126,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 */
 void exynos_cpu_power_down(int cpu)
 {
+        u32 core_conf;
        if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
                /*
                 * Bypass power down for CPU0 during suspend. Check for
@@ -137,7 +139,10 @@ void exynos_cpu_power_down(int cpu)
                if (!(val & S5P_CORE_LOCAL_PWR_EN))
                        return;
        }
-        pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+        core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+        core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
+        pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 }
 /**
@@ -148,7 +153,12 @@ void exynos_cpu_power_down(int cpu)
 */
 void exynos_cpu_power_up(int cpu)
 {
-        pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+        u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
+        if (soc_is_exynos3250())
+                core_conf |= S5P_CORE_AUTOWAKEUP_EN;
+        pmu_raw_writel(core_conf,
                        EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 }
@@ -226,6 +236,10 @@ static void exynos_core_restart(u32 core_id)
        if (!of_machine_is_compatible("samsung,exynos3250"))
                return;
+        while (!pmu_raw_readl(S5P_PMU_SPARE2))
+                udelay(10);
+        udelay(10);
        val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
        val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
        pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
@@ -346,7 +360,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                call_firmware_op(cpu_boot, core_id);
-                arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+                if (soc_is_exynos3250())
+                        dsb_sev();
+                else
+                        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
                if (pen_release == -1)
                        break;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e6209dadc00d..cc75ab448be3 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -127,6 +127,8 @@ int exynos_pm_central_resume(void)
 static void exynos_set_wakeupmask(long mask)
 {
        pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+        if (soc_is_exynos3250())
+                pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
 }
 static void exynos_cpu_set_boot_vector(long flags)
@@ -140,7 +142,7 @@ static int exynos_aftr_finisher(unsigned long flags)
 {
        int ret;
-        exynos_set_wakeupmask(0x0000ff3e);
+        exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e);
        /* Set value of power down register for aftr mode */
        exynos_sys_powerdown_conf(SYS_AFTR);
@@ -157,8 +159,13 @@ static int exynos_aftr_finisher(unsigned long flags)
 void exynos_enter_aftr(void)
 {
+        unsigned int cpuid = smp_processor_id();
        cpu_pm_enter();
+        if (soc_is_exynos3250())
+                exynos_set_boot_flag(cpuid, C2_STATE);
        exynos_pm_central_suspend();
        if (of_machine_is_compatible("samsung,exynos4212") ||
@@ -178,9 +185,13 @@ void exynos_enter_aftr(void)
        exynos_pm_central_resume();
+        if (soc_is_exynos3250())
+                exynos_clear_boot_flag(cpuid, C2_STATE);
        cpu_pm_exit();
 }
+#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
 static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
 static int exynos_cpu0_enter_aftr(void)
@@ -302,3 +313,4 @@ struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
        .pre_enter_aftr         = exynos_pre_enter_aftr,
        .post_enter_aftr                = exynos_post_enter_aftr,
 };
+#endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 37266a826437..cbe56b35aea0 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -37,6 +37,7 @@ struct exynos_pm_domain {
        struct clk *oscclk;
        struct clk *clk[MAX_CLK_PER_DOMAIN];
        struct clk *pclk[MAX_CLK_PER_DOMAIN];
+        struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
 };
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -45,14 +46,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
        void __iomem *base;
        u32 timeout, pwr;
        char *op;
+        int i;
        pd = container_of(domain, struct exynos_pm_domain, pd);
        base = pd->base;
+        for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                if (IS_ERR(pd->asb_clk[i]))
+                        break;
+                clk_prepare_enable(pd->asb_clk[i]);
+        }
        /* Set oscclk before powering off a domain*/
        if (!power_on) {
-                int i;
                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
                        if (IS_ERR(pd->clk[i]))
                                break;
@@ -81,8 +87,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
        /* Restore clocks after powering on a domain*/
        if (power_on) {
-                int i;
                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
                        if (IS_ERR(pd->clk[i]))
                                break;
@@ -92,6 +96,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
                }
        }
+        for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                if (IS_ERR(pd->asb_clk[i]))
+                        break;
+                clk_disable_unprepare(pd->asb_clk[i]);
+        }
        return 0;
 }
@@ -125,12 +135,21 @@ static __init int exynos4_pm_init_power_domain(void)
                        return -ENOMEM;
                }
-                pd->pd.name = kstrdup(np->name, GFP_KERNEL);
+                pd->pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
                pd->name = pd->pd.name;
                pd->base = of_iomap(np, 0);
                pd->pd.power_off = exynos_pd_power_off;
                pd->pd.power_on = exynos_pd_power_on;
+                for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                        char clk_name[8];
+                        snprintf(clk_name, sizeof(clk_name), "asb%d", i);
+                        pd->asb_clk[i] = clk_get(dev, clk_name);
+                        if (IS_ERR(pd->asb_clk[i]))
+                                break;
+                }
                pd->oscclk = clk_get(dev, "oscclk");
                if (IS_ERR(pd->oscclk))
                        goto no_clk;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index eb461e1c325a..b7614333d296 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -43,12 +43,14 @@
 #define S5P_WAKEUP_STAT                         0x0600
 #define S5P_EINT_WAKEUP_MASK                    0x0604
 #define S5P_WAKEUP_MASK                         0x0608
+#define S5P_WAKEUP_MASK2                                0x0614
 #define S5P_INFORM0                             0x0800
 #define S5P_INFORM1                             0x0804
 #define S5P_INFORM5                             0x0814
 #define S5P_INFORM6                             0x0818
 #define S5P_INFORM7                             0x081C
+#define S5P_PMU_SPARE2                          0x0908
 #define S5P_PMU_SPARE3                          0x090C
 #define EXYNOS_IROM_DATA2                       0x0988
@@ -182,6 +184,7 @@
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG          (0x3 << 8)
+#define S5P_CORE_AUTOWAKEUP_EN                  (1 << 31)
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     0x1154
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index f7b82f9c1e21..c2845717bc8f 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -17,6 +17,8 @@
 #define SMC_CMD_SLEEP           (-3)
 #define SMC_CMD_CPU1BOOT        (-4)
 #define SMC_CMD_CPU0AFTR        (-5)
+#define SMC_CMD_SAVE            (-6)
+#define SMC_CMD_SHUTDOWN        (-7)
 /* For CP15 Access */
 #define SMC_CMD_C15RESUME       (-11)
 /* For L2 Cache Access */
@@ -32,4 +34,11 @@ extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
 #endif /* __ASSEMBLY__ */
+/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define OP_TYPE_CORE            0x0
+#define OP_TYPE_CLUSTER         0x1
+/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define SMC_POWERSTATE_IDLE     0x1
 #endif
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 2146d918aedd..3e6aea7f83af 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -65,8 +65,6 @@ static struct sleep_save exynos_core_save[] = {
 struct exynos_pm_data {
        const struct exynos_wkup_irq *wkup_irq;
-        struct sleep_save *extra_save;
-        int num_extra_save;
        unsigned int wake_disable_mask;
        unsigned int *release_ret_regs;
@@ -77,7 +75,7 @@ struct exynos_pm_data {
        int (*cpu_suspend)(unsigned long);
 };
-struct exynos_pm_data *pm_data;
+static const struct exynos_pm_data *pm_data;
 static int exynos5420_cpu_state;
 static unsigned int exynos_pmu_spare3;
@@ -106,7 +104,7 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
        { /* sentinel */ },
 };
-unsigned int exynos_release_ret_regs[] = {
+static unsigned int exynos_release_ret_regs[] = {
        S5P_PAD_RET_MAUDIO_OPTION,
        S5P_PAD_RET_GPIO_OPTION,
        S5P_PAD_RET_UART_OPTION,
@@ -117,7 +115,7 @@ unsigned int exynos_release_ret_regs[] = {
        REG_TABLE_END,
 };
-unsigned int exynos3250_release_ret_regs[] = {
+static unsigned int exynos3250_release_ret_regs[] = {
        S5P_PAD_RET_MAUDIO_OPTION,
        S5P_PAD_RET_GPIO_OPTION,
        S5P_PAD_RET_UART_OPTION,
@@ -130,7 +128,7 @@ unsigned int exynos3250_release_ret_regs[] = {
        REG_TABLE_END,
 };
-unsigned int exynos5420_release_ret_regs[] = {
+static unsigned int exynos5420_release_ret_regs[] = {
        EXYNOS_PAD_RET_DRAM_OPTION,
        EXYNOS_PAD_RET_MAUDIO_OPTION,
        EXYNOS_PAD_RET_JTAG_OPTION,
@@ -349,10 +347,6 @@ static void exynos_pm_prepare(void)
        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-         if (pm_data->extra_save)
-                s3c_pm_do_save(pm_data->extra_save,
-                                pm_data->num_extra_save);
        exynos_pm_enter_sleep_mode();
        /* ensure at least INFORM0 has the resume address */
@@ -475,10 +469,6 @@ static void exynos_pm_resume(void)
        /* For release retention */
        exynos_pm_release_retention();
-        if (pm_data->extra_save)
-                s3c_pm_do_restore_core(pm_data->extra_save,
-                                        pm_data->num_extra_save);
        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
        if (cpuid == ARM_CPU_PART_CORTEX_A9)
@@ -685,7 +675,7 @@ static const struct exynos_pm_data exynos5250_pm_data = {
        .cpu_suspend    = exynos_cpu_suspend,
 };
-static struct exynos_pm_data exynos5420_pm_data = {
+static const struct exynos_pm_data exynos5420_pm_data = {
        .wkup_irq       = exynos5250_wkup_irq,
        .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
        .release_ret_regs = exynos5420_release_ret_regs,
@@ -736,7 +726,7 @@ void __init exynos_pm_init(void)
        if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL)))
                pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
-        pm_data = (struct exynos_pm_data *) match->data;
+        pm_data = (const struct exynos_pm_data *) match->data;
        /* All wakeup disable */
        tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c8dffcee9736..3a3d3e9d7bfd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -21,6 +21,7 @@ config MXC_AVIC
 config MXC_DEBUG_BOARD
        bool "Enable MXC debug board(for 3-stack)"
+        depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS
        help
          The debug board is an integral part of the MXC 3-stack(PDK)
          platforms, it can be attached or removed from the peripheral
@@ -50,6 +51,7 @@ config HAVE_IMX_ANATOP
 config HAVE_IMX_GPC
        bool
+        select PM_GENERIC_DOMAINS if PM
 config HAVE_IMX_MMDC
        bool
@@ -77,13 +79,6 @@ config SOC_IMX21
        select IMX_HAVE_IOMUX_V1
        select MXC_AVIC
-config SOC_IMX25
-        bool
-        select ARCH_MXC_IOMUX_V3
-        select CPU_ARM926T
-        select MXC_AVIC
-        select PINCTRL_IMX25
 config SOC_IMX27
        bool
        select CPU_ARM926T
@@ -149,62 +144,6 @@ config MACH_MX21ADS
          Include support for MX21ADS platform. This includes specific
          configurations for the board and its peripherals.
-comment "MX25 platforms:"
-config MACH_MX25_3DS
-        bool "Support MX25PDK (3DS) Platform"
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMXDI_RTC
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select SOC_IMX25
-config MACH_EUKREA_CPUIMX25SD
-        bool "Support Eukrea CPUIMX25 Platform"
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMXDI_RTC
-        select IMX_HAVE_PLATFORM_IMX_FB
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select USB_ULPI_VIEWPORT if USB_ULPI
-        select SOC_IMX25
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX25SD
-        default MACH_EUKREA_MBIMXSD25_BASEBOARD
-config MACH_EUKREA_MBIMXSD25_BASEBOARD
-        bool "Eukrea MBIMXSD development board"
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-endchoice
-config MACH_IMX25_DT
-        bool "Support i.MX25 platforms from device tree"
-        select SOC_IMX25
-        help
-          Include support for Freescale i.MX25 based platforms
-          using the device tree for discovery
 comment "MX27 platforms:"
 config MACH_MX27ADS
@@ -557,6 +496,20 @@ config MACH_VPR200
 endif
+if ARCH_MULTI_V5
+comment "Device tree only"
+config SOC_IMX25
+        bool "i.MX25 support"
+        select ARCH_MXC_IOMUX_V3
+        select CPU_ARM926T
+        select MXC_AVIC
+        select PINCTRL_IMX25
+        help
+          This enables support for Freescale i.MX25 processor
+endif
 if ARCH_MULTI_V7
 comment "Device tree only"
@@ -635,9 +588,10 @@ config SOC_VF610
        select ARM_GIC
        select PINCTRL_VF610
        select PL310_ERRATA_769419 if CACHE_L2X0
+        select SMP_ON_UP if SMP
        help
-          This enable support for Freescale Vybrid VF610 processor.
+          This enables support for Freescale Vybrid VF610 processor.
 choice
        prompt "Clocksource for scheduler clock"
@@ -667,7 +621,7 @@ config SOC_LS1021A
        select ZONE_DMA if ARM_LPAE
        help
-          This enable support for Freescale LS1021A processor.
+          This enables support for Freescale LS1021A processor.
 endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8d1b10180908..3244cf1d2773 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-y := time.o cpu.o system.o irq-common.o
 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
-obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
@@ -48,12 +48,6 @@ obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
 # i.MX21 based machines
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
-# i.MX25 based machines
-obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
-obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 59c0c8558c6b..9c2633a9de9f 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -30,7 +30,6 @@
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
-#include "mx25.h"
 #define CCM_MPCTL       0x00
 #define CCM_UPCTL       0x04
@@ -239,80 +238,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
        return 0;
 }
-int __init mx25_clocks_init(void)
-{
-        void __iomem *ccm;
-        ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
-        __mx25_clocks_init(24000000, ccm);
-        clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        /* i.mx25 has the i.mx21 type uart */
-        clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
-        clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
-        clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
-        /* i.mx25 has the i.mx35 type cspi */
-        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
-        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
-        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
-        clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
-        clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
-        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-        clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
-        clk_register_clkdev(clk[dummy], "audmux", NULL);
-        clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
-        clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
-        /* i.mx25 has the i.mx35 type sdma */
-        clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
-        clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
-        clk_register_clkdev(clk[iim_ipg], "iim", NULL);
-        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
-        return 0;
-}
 static void __init mx25_clocks_init_dt(struct device_node *np)
 {
        struct device_node *refnp;
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d04a430607b8..469a150bf98f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_mipi_core_cfg;
 static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
@@ -246,6 +247,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
        clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
        clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
+        clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
        if (cpu_is_imx6dl()) {
                clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
                clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -400,7 +402,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
        clk[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
        clk[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
-        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "video_27m",         base + 0x70, 4);
        clk[IMX6QDL_CLK_I2C1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
        clk[IMX6QDL_CLK_I2C2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
        clk[IMX6QDL_CLK_I2C3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
@@ -415,7 +417,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
        clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
        clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
-        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);
+        clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
+        clk[IMX6QDL_CLK_MIPI_IPG]     = imx_clk_gate2_shared("mipi_ipg", "ipg",             base + 0x74, 16, &share_count_mipi_core_cfg);
        if (cpu_is_imx6dl())
                /*
                 * The multiplexer and divider of the imx6q clock gpu2d get
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1028b6c505c4..0f04e30b726d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -23,13 +23,11 @@ struct of_device_id;
 void mx1_map_io(void);
 void mx21_map_io(void);
-void mx25_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
 void imx1_init_early(void);
 void imx21_init_early(void);
-void imx25_init_early(void);
 void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
@@ -37,13 +35,11 @@ void mxc_init_irq(void __iomem *);
 void tzic_init_irq(void);
 void mx1_init_irq(void);
 void mx21_init_irq(void);
-void mx25_init_irq(void);
 void mx27_init_irq(void);
 void mx31_init_irq(void);
 void mx35_init_irq(void);
 void imx1_soc_init(void);
 void imx21_soc_init(void);
-void imx25_soc_init(void);
 void imx27_soc_init(void);
 void imx31_soc_init(void);
 void imx35_soc_init(void);
@@ -51,7 +47,6 @@ void epit_timer_init(void __iomem *base, int irq);
 void mxc_timer_init(void __iomem *, int);
 int mx1_clocks_init(unsigned long fref);
 int mx21_clocks_init(unsigned long lref, unsigned long fref);
-int mx25_clocks_init(void);
 int mx27_clocks_init(unsigned long fref);
 int mx31_clocks_init(unsigned long fref);
 int mx35_clocks_init(void);
@@ -71,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
 void imx_init_revision_from_anatop(void);
 struct device *imx_soc_device_init(void);
 void imx6_enable_rbc(bool enable);
+void imx_gpc_check_dt(void);
 void imx_gpc_set_arm_power_in_lpm(bool power_off);
 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
@@ -106,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 #endif
 void imx_src_init(void);
-void imx_gpc_init(void);
 void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index 96ec64b5ff7d..d0ad67e802d3 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -11,6 +11,8 @@
 */
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include "iim.h"
 #include "hardware.h"
@@ -20,8 +22,15 @@ static int mx25_cpu_rev = -1;
 static int mx25_read_cpu_rev(void)
 {
        u32 rev;
+        void __iomem *iim_base;
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
+        iim_base = of_iomap(np, 0);
+        BUG_ON(!iim_base);
+        rev = readl(iim_base + MXC_IIMSREV);
+        iounmap(iim_base);
-        rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
        switch (rev) {
        case 0x00:
                return IMX_CHIP_REVISION_1_0;
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
deleted file mode 100644
index 61a114cddc39..000000000000
--- a/arch/arm/mach-imx/devices-imx25.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-extern const struct imx_fec_data imx25_fec_data;
-#define imx25_add_fec(pdata)    \
-        imx_add_fec(&imx25_fec_data, pdata)
-extern const struct imx_flexcan_data imx25_flexcan_data[];
-#define imx25_add_flexcan(id)   \
-        imx_add_flexcan(&imx25_flexcan_data[id])
-#define imx25_add_flexcan0()            imx25_add_flexcan(0)
-#define imx25_add_flexcan1()            imx25_add_flexcan(1)
-extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
-#define imx25_add_fsl_usb2_udc(pdata)   \
-        imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
-extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
-#define imx25_add_imxdi_rtc()   \
-        imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
-extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
-#define imx25_add_imx2_wdt()    \
-        imx_add_imx2_wdt(&imx25_imx2_wdt_data)
-extern const struct imx_imx_fb_data imx25_imx_fb_data;
-#define imx25_add_imx_fb(pdata) \
-        imx_add_imx_fb(&imx25_imx_fb_data, pdata)
-extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
-#define imx25_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
-#define imx25_add_imx_i2c0(pdata)       imx25_add_imx_i2c(0, pdata)
-#define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
-#define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
-extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
-#define imx25_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
-extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
-#define imx25_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
-extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
-#define imx25_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
-#define imx25_add_imx_uart0(pdata)      imx25_add_imx_uart(0, pdata)
-#define imx25_add_imx_uart1(pdata)      imx25_add_imx_uart(1, pdata)
-#define imx25_add_imx_uart2(pdata)      imx25_add_imx_uart(2, pdata)
-#define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
-#define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
-extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
-#define imx25_add_mx2_camera(pdata)     \
-        imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
-#define imx25_add_mxc_ehci_otg(pdata)   \
-        imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
-#define imx25_add_mxc_ehci_hs(pdata)    \
-        imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
-extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
-#define imx25_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
-extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
-#define imx25_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
-extern const struct imx_spi_imx_data imx25_cspi_data[];
-#define imx25_add_spi_imx(id, pdata)    \
-        imx_add_spi_imx(&imx25_cspi_data[id], pdata)
-#define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
-#define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
-#define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 1d2cc1805f3e..3a552989248e 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -21,9 +21,6 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
 config IMX_HAVE_PLATFORM_IMX2_WDT
        bool
-config IMX_HAVE_PLATFORM_IMXDI_RTC
-        bool
 config IMX_HAVE_PLATFORM_IMX_FB
        bool
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 8fdb12b4ca7e..e5cf587bc1a0 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -8,7 +8,6 @@ obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index d86f9250b4ee..b403a4fe2892 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -19,11 +19,6 @@
                .irq = soc ## _INT_FEC,                                 \
        }
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fec_data imx25_fec_data __initconst =
-        imx_fec_data_entry_single(MX25, "imx25-fec");
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_fec_data imx27_fec_data __initconst =
        imx_fec_data_entry_single(MX27, "imx27-fec");
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 23b0061347cb..25e1de6f3a47 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -18,11 +18,6 @@
                .irq = soc ## _INT_USB_OTG,                             \
        }
-#ifdef CONFIG_SOC_IMX25
-const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
        imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 25a47c616b2d..7df6328306f9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -29,11 +29,6 @@ const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
        imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
        imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 644ac2689882..ae9791522fc8 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -31,16 +31,6 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
        imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
-#define imx25_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
-        imx25_imx_i2c_data_entry(0, 1),
-        imx25_imx_i2c_data_entry(1, 2),
-        imx25_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 #define imx27_imx_i2c_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index f42200b7aca9..479e4d70dbf9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -21,11 +21,6 @@ const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
        imx_imx_keypad_data_entry_single(MX21, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX25, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
        imx_imx_keypad_data_entry_single(MX27, SZ_16);
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index 1c7c721ebff1..6f0e94eb29ee 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -30,15 +30,6 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
-#define imx25_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
-        imx25_imx_ssi_data_entry(0, 1),
-        imx25_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
 #define imx27_imx_ssi_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 8c01836bc1d4..6962cff4a950 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -47,18 +47,6 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
 };
 #endif
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
-#define imx25_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_imx_uart_data_entry(0, 1),
-        imx25_imx_uart_data_entry(1, 2),
-        imx25_imx_uart_data_entry(2, 3),
-        imx25_imx_uart_data_entry(3, 4),
-        imx25_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
 #define imx27_imx_uart_data_entry(_id, _hwid)                           \
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 54f63bc25ca4..8c134c8d7500 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -25,11 +25,6 @@ const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
        imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
-        imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
        imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
deleted file mode 100644
index 5bb490d556ea..000000000000
--- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include "../hardware.h"
-#include "devices-common.h"
-#define imx_imxdi_rtc_data_entry_single(soc)                            \
-        {                                                               \
-                .iobase = soc ## _DRYICE_BASE_ADDR,                     \
-                .irq = soc ## _INT_DRYICE,                              \
-        }
-#ifdef CONFIG_SOC_IMX25
-const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
-        imx_imxdi_rtc_data_entry_single(MX25);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-struct platform_device *__init imx_add_imxdi_rtc(
-                const struct imx_imxdi_rtc_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device("imxdi_rtc", 0,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index b53e1f348f51..4c377c33242c 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -27,11 +27,6 @@
                .irqemmaprp = soc ## _INT_EMMAPRP,                      \
        }
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
        imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 296353662ff0..4537abd2a8f2 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -18,13 +18,6 @@
                .irq = soc ## _INT_USB_ ## hs,                          \
        }
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
-const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX25, 1, HS);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
        imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index fa618a34f462..676df4920c7b 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -34,11 +34,6 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
        imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
        imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index aca825d74c48..5e9707b47f92 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -39,17 +39,6 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 };
 #endif
-#ifdef CONFIG_SOC_IMX25
-/* i.mx25 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
-#define imx25_cspi_data_entry(_id, _hwid)                               \
-        imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K)
-        imx25_cspi_data_entry(0, 1),
-        imx25_cspi_data_entry(1, 2),
-        imx25_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
 #define imx27_cspi_data_entry(_id, _hwid)                               \
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
deleted file mode 100644
index 42a5a3d14c5f..000000000000
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-#include "ehci.h"
-#include "hardware.h"
-#define USBCTRL_OTGBASE_OFFSET  0x600
-#define MX25_OTG_SIC_SHIFT      29
-#define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
-#define MX25_OTG_PM_BIT         (1 << 24)
-#define MX25_OTG_PP_BIT         (1 << 11)
-#define MX25_OTG_OCPOL_BIT      (1 << 3)
-#define MX25_H1_SIC_SHIFT       21
-#define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
-#define MX25_H1_PP_BIT          (1 << 18)
-#define MX25_H1_PM_BIT          (1 << 16)
-#define MX25_H1_IPPUE_UP_BIT    (1 << 7)
-#define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
-#define MX25_H1_TLL_BIT         (1 << 5)
-#define MX25_H1_USBTE_BIT       (1 << 4)
-#define MX25_H1_OCPOL_BIT       (1 << 2)
-int mx25_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-        v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-        switch (port) {
-        case 0: /* OTG port */
-                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
-                        MX25_OTG_OCPOL_BIT);
-                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                        v |= MX25_OTG_PM_BIT;
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_OTG_PP_BIT;
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_OTG_OCPOL_BIT;
-                break;
-        case 1: /* H1 port */
-                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
-                        MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
-                        MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
-                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
-                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                        v |= MX25_H1_PM_BIT;
-                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                        v |= MX25_H1_PP_BIT;
-                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                        v |= MX25_H1_OCPOL_BIT;
-                if (!(flags & MXC_EHCI_TTL_ENABLED))
-                        v |= MX25_H1_TLL_BIT;
-                if (flags & MXC_EHCI_INTERNAL_PHY)
-                        v |= MX25_H1_USBTE_BIT;
-                if (flags & MXC_EHCI_IPPUE_DOWN)
-                        v |= MX25_H1_IPPUE_DOWN_BIT;
-                if (flags & MXC_EHCI_IPPUE_UP)
-                        v |= MX25_H1_IPPUE_UP_BIT;
-                break;
-        default:
-                return -EINVAL;
-        }
-        writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-        return 0;
-}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
deleted file mode 100644
index e77cc3af6db2..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/spi/spi.h>
-#include <video/platform_lcd.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "devices-imx25.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
-        /* LCD */
-        MX25_PAD_LD0__LD0,
-        MX25_PAD_LD1__LD1,
-        MX25_PAD_LD2__LD2,
-        MX25_PAD_LD3__LD3,
-        MX25_PAD_LD4__LD4,
-        MX25_PAD_LD5__LD5,
-        MX25_PAD_LD6__LD6,
-        MX25_PAD_LD7__LD7,
-        MX25_PAD_LD8__LD8,
-        MX25_PAD_LD9__LD9,
-        MX25_PAD_LD10__LD10,
-        MX25_PAD_LD11__LD11,
-        MX25_PAD_LD12__LD12,
-        MX25_PAD_LD13__LD13,
-        MX25_PAD_LD14__LD14,
-        MX25_PAD_LD15__LD15,
-        MX25_PAD_GPIO_E__LD16,
-        MX25_PAD_GPIO_F__LD17,
-        MX25_PAD_HSYNC__HSYNC,
-        MX25_PAD_VSYNC__VSYNC,
-        MX25_PAD_LSCLK__LSCLK,
-        MX25_PAD_OE_ACD__OE_ACD,
-        MX25_PAD_CONTRAST__CONTRAST,
-        /* LCD_PWR */
-        MX25_PAD_PWM__GPIO_1_26,
-        /* LED */
-        MX25_PAD_POWER_FAIL__GPIO_3_19,
-        /* SWITCH */
-        MX25_PAD_VSTBY_ACK__GPIO_3_18,
-        /* UART2 */
-        MX25_PAD_UART2_RTS__UART2_RTS,
-        MX25_PAD_UART2_CTS__UART2_CTS,
-        MX25_PAD_UART2_TXD__UART2_TXD,
-        MX25_PAD_UART2_RXD__UART2_RXD,
-        /* SD1 */
-        MX25_PAD_SD1_CMD__SD1_CMD,
-        MX25_PAD_SD1_CLK__SD1_CLK,
-        MX25_PAD_SD1_DATA0__SD1_DATA0,
-        MX25_PAD_SD1_DATA1__SD1_DATA1,
-        MX25_PAD_SD1_DATA2__SD1_DATA2,
-        MX25_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD1 CD */
-        MX25_PAD_DE_B__GPIO_2_20,
-        /* I2S */
-        MX25_PAD_KPP_COL3__AUD5_TXFS,
-        MX25_PAD_KPP_COL2__AUD5_TXC,
-        MX25_PAD_KPP_COL1__AUD5_RXD,
-        MX25_PAD_KPP_COL0__AUD5_TXD,
-        /* CAN */
-        MX25_PAD_GPIO_D__CAN2_RX,
-        MX25_PAD_GPIO_C__CAN2_TX,
-        /* SPI1 */
-        MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
-        MX25_PAD_CSPI1_MISO__CSPI1_MISO,
-        MX25_PAD_CSPI1_SS0__GPIO_1_16,
-        MX25_PAD_CSPI1_SS1__GPIO_1_17,
-        MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
-        MX25_PAD_CSPI1_RDY__GPIO_2_22,
-};
-#define GPIO_LED1               IMX_GPIO_NR(3, 19)
-#define GPIO_SWITCH1    IMX_GPIO_NR(3, 18)
-#define GPIO_SD1CD              IMX_GPIO_NR(2, 20)
-#define GPIO_LCDPWR             IMX_GPIO_NR(1, 26)
-#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 16)
-#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 17)
-#define GPIO_SPI1_IRQ   IMX_GPIO_NR(2, 22)
-static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
-        {
-                .mode   = {
-                        .name           = "CMO-QVGA",
-                        .refresh        = 60,
-                        .xres           = 320,
-                        .yres           = 240,
-                        .pixclock       = KHZ2PICOS(6500),
-                        .left_margin    = 30,
-                        .right_margin   = 38,
-                        .upper_margin   = 20,
-                        .lower_margin   = 3,
-                        .hsync_len      = 15,
-                        .vsync_len      = 4,
-                },
-                .bpp    = 16,
-                .pcr    = 0xCAD08B80,
-        }, {
-                .mode = {
-                        .name           = "DVI-VGA",
-                        .refresh        = 60,
-                        .xres           = 640,
-                        .yres           = 480,
-                        .pixclock       = 32000,
-                        .hsync_len      = 7,
-                        .left_margin    = 100,
-                        .right_margin   = 100,
-                        .vsync_len      = 7,
-                        .upper_margin   = 7,
-                        .lower_margin   = 100,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        }, {
-                .mode = {
-                        .name           = "DVI-SVGA",
-                        .refresh        = 60,
-                        .xres           = 800,
-                        .yres           = 600,
-                        .pixclock       = 25000,
-                        .hsync_len      = 7,
-                        .left_margin    = 75,
-                        .right_margin   = 75,
-                        .vsync_len      = 7,
-                        .upper_margin   = 7,
-                        .lower_margin   = 75,
-                },
-                .pcr            = 0xFA208B80,
-                .bpp            = 16,
-        },
-};
-static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
-        .mode           = eukrea_mximxsd_modes,
-        .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00040060,
-};
-static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power)
-                gpio_direction_output(GPIO_LCDPWR, 1);
-        else
-                gpio_direction_output(GPIO_LCDPWR, 0);
-}
-static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
-        .set_power              = eukrea_mbimxsd_lcd_power_set,
-};
-static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
-};
-static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = GPIO_LED1,
-        },
-};
-static const struct gpio_led_platform_data
-                eukrea_mbimxsd_led_info __initconst = {
-        .leds           = eukrea_mbimxsd_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
-};
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
-        {
-                .gpio           = GPIO_SWITCH1,
-                .code           = BTN_0,
-                .desc           = "BP1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-static const struct gpio_keys_platform_data
-                eukrea_mbimxsd_button_data __initconst = {
-        .buttons        = eukrea_mbimxsd_gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
-};
-static struct platform_device *platform_devices[] __initdata = {
-        &eukrea_mbimxsd_lcd_powerdev,
-};
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-static const
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
-        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-static struct esdhc_platform_data sd1_pdata = {
-        .cd_gpio = GPIO_SD1CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_NONE,
-};
-static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_0,
-        },
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-        },
-};
-static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
-static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
-        .chipselect     = eukrea_mbimxsd25_spi_cs,
-        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
-};
-/*
- * system init for baseboard usage. Will be called by cpuimx25 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd25_baseboard_init(void)
-{
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
-                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
-                printk(KERN_ERR "error setting mbimxsd pads !\n");
-        imx25_add_imx_uart1(&uart_pdata);
-        imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
-        imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
-        imx25_add_flexcan1();
-        imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
-        gpio_request(GPIO_LED1, "LED1");
-        gpio_direction_output(GPIO_LED1, 1);
-        gpio_free(GPIO_LED1);
-        gpio_request(GPIO_SWITCH1, "SWITCH1");
-        gpio_direction_input(GPIO_SWITCH1);
-        gpio_free(GPIO_SWITCH1);
-        gpio_request(GPIO_LCDPWR, "LCDPWR");
-        gpio_direction_output(GPIO_LCDPWR, 1);
-        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
-                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
-        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
-        gpio_direction_input(GPIO_SPI1_IRQ);
-        gpio_free(GPIO_SPI1_IRQ);
-        imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
-        spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
-                ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
-        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
-}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 14d6c8249b76..6edc940e0865 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -100,7 +100,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
        .num_modes      = ARRAY_SIZE(fb_modedb),
 };
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
        /* LCD */
        MX35_PAD_LD0__IPU_DISPB_DAT_0,
        MX35_PAD_LD1__IPU_DISPB_DAT_1,
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 745caa18ab2c..4d60005e9277 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,15 +10,25 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
 #include <linux/irqchip/arm-gic.h>
 #include "common.h"
+#include "hardware.h"
+#define GPC_CNTR                0x000
 #define GPC_IMR1                0x008
+#define GPC_PGC_GPU_PDN         0x260
+#define GPC_PGC_GPU_PUPSCR      0x264
+#define GPC_PGC_GPU_PDNSCR      0x268
 #define GPC_PGC_CPU_PDN         0x2a0
 #define GPC_PGC_CPU_PUPSCR      0x2a4
 #define GPC_PGC_CPU_PDNSCR      0x2a8
@@ -26,6 +36,19 @@
 #define GPC_PGC_SW_SHIFT        0x0
 #define IMR_NUM                 4
+#define GPC_MAX_IRQS            (IMR_NUM * 32)
+#define GPU_VPU_PUP_REQ         BIT(1)
+#define GPU_VPU_PDN_REQ         BIT(0)
+#define GPC_CLK_MAX             6
+struct pu_domain {
+        struct generic_pm_domain base;
+        struct regulator *reg;
+        struct clk *clk[GPC_CLK_MAX];
+        int num_clks;
+};
 static void __iomem *gpc_base;
 static u32 gpc_wake_irqs[IMR_NUM];
@@ -77,17 +100,17 @@ void imx_gpc_post_resume(void)
 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned int idx = d->hwirq / 32 - 1;
+        unsigned int idx = d->hwirq / 32;
        u32 mask;
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return -EINVAL;
        mask = 1 << d->hwirq % 32;
        gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
                                  gpc_wake_irqs[idx] & ~mask;
+        /*
+         * Do *not* call into the parent, as the GIC doesn't have any
+         * wake-up facility...
+         */
        return 0;
 }
@@ -117,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
        void __iomem *reg;
        u32 val;
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
        val = readl_relaxed(reg);
        val &= ~(1 << hwirq % 32);
        writel_relaxed(val, reg);
@@ -128,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
        void __iomem *reg;
        u32 val;
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
        val = readl_relaxed(reg);
        val |= 1 << (hwirq % 32);
        writel_relaxed(val, reg);
@@ -136,37 +159,319 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
 static void imx_gpc_irq_unmask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
        imx_gpc_hwirq_unmask(d->hwirq);
+        irq_chip_unmask_parent(d);
 }
 static void imx_gpc_irq_mask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
        imx_gpc_hwirq_mask(d->hwirq);
+        irq_chip_mask_parent(d);
 }
-void __init imx_gpc_init(void)
+static struct irq_chip imx_gpc_chip = {
+        .name                   = "GPC",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = imx_gpc_irq_mask,
+        .irq_unmask             = imx_gpc_irq_unmask,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .irq_set_wake           = imx_gpc_irq_set_wake,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+                                struct device_node *controller,
+                                const u32 *intspec,
+                                unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
 {
-        struct device_node *np;
+        if (domain->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
+        return 0;
+}
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+                                  unsigned int irq,
+                                  unsigned int nr_irqs, void *data)
+{
+        struct of_phandle_args *args = data;
+        struct of_phandle_args parent_args;
+        irq_hw_number_t hwirq;
        int i;
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        if (args->args_count != 3)
-        gpc_base = of_iomap(np, 0);
+                return -EINVAL; /* Not GIC compliant */
-        WARN_ON(!gpc_base);
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        hwirq = args->args[1];
+        if (hwirq >= GPC_MAX_IRQS)
+                return -EINVAL; /* Can't deal with this */
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
+                                              &imx_gpc_chip, NULL);
+        parent_args = *args;
+        parent_args.np = domain->parent->of_node;
+        return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
+}
+static struct irq_domain_ops imx_gpc_domain_ops = {
+        .xlate  = imx_gpc_domain_xlate,
+        .alloc  = imx_gpc_domain_alloc,
+        .free   = irq_domain_free_irqs_common,
+};
+static int __init imx_gpc_init(struct device_node *node,
+                               struct device_node *parent)
+{
+        struct irq_domain *parent_domain, *domain;
+        int i;
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
+                return -ENODEV;
+        }
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
+        gpc_base = of_iomap(node, 0);
+        if (WARN_ON(!gpc_base))
+                return -ENOMEM;
+        domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
+                                          node, &imx_gpc_domain_ops,
+                                          NULL);
+        if (!domain) {
+                iounmap(gpc_base);
+                return -ENOMEM;
+        }
        /* Initially mask all interrupts */
        for (i = 0; i < IMR_NUM; i++)
                writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
-        /* Register GPC as the secondary interrupt controller behind GIC */
+        return 0;
-        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+}
-        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
-        gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+/*
+ * We cannot use the IRQCHIP_DECLARE macro that lives in
+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
+ */
+OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
+void __init imx_gpc_check_dt(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        if (WARN_ON(!np ||
+                    !of_find_property(np, "interrupt-controller", NULL)))
+                pr_warn("Outdated DT detected, system is about to crash!!!\n");
+}
+#ifdef CONFIG_PM_GENERIC_DOMAINS
+static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+        int iso, iso2sw;
+        u32 val;
+        /* Read ISO and ISO2SW power down delays */
+        val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
+        iso = val & 0x3f;
+        iso2sw = (val >> 8) & 0x3f;
+        /* Gate off PU domain when GPU/VPU when powered down */
+        writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+        /* Request GPC to power down GPU/VPU */
+        val = readl_relaxed(gpc_base + GPC_CNTR);
+        val |= GPU_VPU_PDN_REQ;
+        writel_relaxed(val, gpc_base + GPC_CNTR);
+        /* Wait ISO + ISO2SW IPG clock cycles */
+        ndelay((iso + iso2sw) * 1000 / 66);
+}
+static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+        struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+        _imx6q_pm_pu_power_off(genpd);
+        if (pu->reg)
+                regulator_disable(pu->reg);
+        return 0;
+}
+static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
+{
+        struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
+        int i, ret, sw, sw2iso;
+        u32 val;
+        if (pu->reg)
+                ret = regulator_enable(pu->reg);
+        if (pu->reg && ret) {
+                pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
+                return ret;
+        }
+        /* Enable reset clocks for all devices in the PU domain */
+        for (i = 0; i < pu->num_clks; i++)
+                clk_prepare_enable(pu->clk[i]);
+        /* Gate off PU domain when GPU/VPU when powered down */
+        writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+        /* Read ISO and ISO2SW power down delays */
+        val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
+        sw = val & 0x3f;
+        sw2iso = (val >> 8) & 0x3f;
+        /* Request GPC to power up GPU/VPU */
+        val = readl_relaxed(gpc_base + GPC_CNTR);
+        val |= GPU_VPU_PUP_REQ;
+        writel_relaxed(val, gpc_base + GPC_CNTR);
+        /* Wait ISO + ISO2SW IPG clock cycles */
+        ndelay((sw + sw2iso) * 1000 / 66);
+        /* Disable reset clocks for all devices in the PU domain */
+        for (i = 0; i < pu->num_clks; i++)
+                clk_disable_unprepare(pu->clk[i]);
+        return 0;
+}
+static struct generic_pm_domain imx6q_arm_domain = {
+        .name = "ARM",
+};
+static struct pu_domain imx6q_pu_domain = {
+        .base = {
+                .name = "PU",
+                .power_off = imx6q_pm_pu_power_off,
+                .power_on = imx6q_pm_pu_power_on,
+                .power_off_latency_ns = 25000,
+                .power_on_latency_ns = 2000000,
+        },
+};
+static struct generic_pm_domain imx6sl_display_domain = {
+        .name = "DISPLAY",
+};
+static struct generic_pm_domain *imx_gpc_domains[] = {
+        &imx6q_arm_domain,
+        &imx6q_pu_domain.base,
+        &imx6sl_display_domain,
+};
+static struct genpd_onecell_data imx_gpc_onecell_data = {
+        .domains = imx_gpc_domains,
+        .num_domains = ARRAY_SIZE(imx_gpc_domains),
+};
+static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
+{
+        struct clk *clk;
+        bool is_off;
+        int i;
+        imx6q_pu_domain.reg = pu_reg;
+        for (i = 0; ; i++) {
+                clk = of_clk_get(dev->of_node, i);
+                if (IS_ERR(clk))
+                        break;
+                if (i >= GPC_CLK_MAX) {
+                        dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
+                        goto clk_err;
+                }
+                imx6q_pu_domain.clk[i] = clk;
+        }
+        imx6q_pu_domain.num_clks = i;
+        is_off = IS_ENABLED(CONFIG_PM);
+        if (is_off) {
+                _imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
+        } else {
+                /*
+                 * Enable power if compiled without CONFIG_PM in case the
+                 * bootloader disabled it.
+                 */
+                imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
+        }
+        pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
+        return of_genpd_add_provider_onecell(dev->of_node,
+                                             &imx_gpc_onecell_data);
+clk_err:
+        while (i--)
+                clk_put(imx6q_pu_domain.clk[i]);
+        return -EINVAL;
+}
+#else
+static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
+{
+        return 0;
+}
+#endif /* CONFIG_PM_GENERIC_DOMAINS */
+static int imx_gpc_probe(struct platform_device *pdev)
+{
+        struct regulator *pu_reg;
+        int ret;
+        pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
+        if (PTR_ERR(pu_reg) == -ENODEV)
+                pu_reg = NULL;
+        if (IS_ERR(pu_reg)) {
+                ret = PTR_ERR(pu_reg);
+                dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
+                return ret;
+        }
+        return imx_gpc_genpd_init(&pdev->dev, pu_reg);
+}
+static const struct of_device_id imx_gpc_dt_ids[] = {
+        { .compatible = "fsl,imx6q-gpc" },
+        { .compatible = "fsl,imx6sl-gpc" },
+        { }
+};
+static struct platform_driver imx_gpc_driver = {
+        .driver = {
+                .name = "imx-gpc",
+                .owner = THIS_MODULE,
+                .of_match_table = imx_gpc_dt_ids,
+        },
+        .probe = imx_gpc_probe,
+};
+static int __init imx_pgc_init(void)
+{
+        return platform_driver_register(&imx_gpc_driver);
 }
+subsys_initcall(imx_pgc_init);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 66b2b564c463..76af2c03c241 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -112,7 +112,6 @@
 #include "mx21.h"
 #include "mx27.h"
 #include "mx1.h"
-#include "mx25.h"
 #define imx_map_entry(soc, name, _type) {                               \
        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
diff --git a/arch/arm/mach-imx/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h
deleted file mode 100644
index be51e838375c..000000000000
--- a/arch/arm/mach-imx/iomux-mx25.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * arch/arm/plat-mxc/include/mach/iomux-mx25.h
- *
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * based on arch/arm/mach-mx25/mx25_pins.h
- *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and
- * arch/arm/plat-mxc/include/mach/iomux-mx35.h
- *    Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX25_H__
-#define __MACH_IOMUX_MX25_H__
-#include "iomux-v3.h"
-/*
- * IOMUX/PAD Bit field definitions
- */
-#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
-#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
-#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__NF_CE3            IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__NF_CE1            IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__NF_CE2            IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
-#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
-#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
-#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
-#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
-#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
-#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
-#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__PWM4_PWMO    IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
-#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D2__CSPI3_MOSI     IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D3__CSPI3_MISO     IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D4__CSPI3_SCLK     IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D5__CSPI3_RDY      IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
-#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
-#define KPP_CTL_ROW     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define KPP_CTL_COL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
-#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
-#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL0__AUD5_TXD     IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL1__AUD5_RXD     IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL2__UART4_RTS    IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL2__AUD5_TXC     IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
-#define MX25_PAD_KPP_COL3__UART4_CTS    IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_KPP_COL3__AUD5_TXFS    IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
-#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
-#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
-#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
-#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
-#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
-#endif /* __MACH_IOMUX_MX25_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 0a5adba61e0b..2e4a0ddca76c 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -114,7 +114,7 @@ enum iomux_gp_func {
 */
 int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
 /*
- * setups mutliple pins
+ * setups multiple pins
 * convenient way to call the above function with tables
 */
 int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index d61f9606fc56..a53b2e64f98d 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
        return 0;
 }
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+                unsigned count)
 {
-        iomux_v3_cfg_t *p = pad_list;
+        const iomux_v3_cfg_t *p = pad_list;
        int i;
        int ret;
diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
index 2fa3b5430102..f79e165a3b3c 100644
--- a/arch/arm/mach-imx/iomux-v3.h
+++ b/arch/arm/mach-imx/iomux-v3.h
@@ -128,10 +128,11 @@ typedef u64 iomux_v3_cfg_t;
 int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 /*
- * setups mutliple pads
+ * setups multiple pads
 * convenient way to call the above function with tables
 */
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+                unsigned count);
 /*
 * Initialise the iomux controller
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 62a6e02f4763..922ffd6ca039 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
        },
 };
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
+static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
        /* UART1 */
        MX35_PAD_CTS1__UART1_CTS,
        MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
deleted file mode 100644
index b2ee6e009fe4..000000000000
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
- * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "devices-imx25.h"
-#include "ehci.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
-        /* FEC - RMII */
-        MX25_PAD_FEC_MDC__FEC_MDC,
-        MX25_PAD_FEC_MDIO__FEC_MDIO,
-        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-        /* I2C1 */
-        MX25_PAD_I2C1_CLK__I2C1_CLK,
-        MX25_PAD_I2C1_DAT__I2C1_DAT,
-};
-static const struct fec_platform_data mx25_fec_pdata __initconst = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
-};
-static const struct mxc_nand_platform_data
-eukrea_cpuimx25_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-static const struct imxi2c_platform_data
-eukrea_cpuimx25_i2c0_data __initconst = {
-        .bitrate = 100000,
-};
-static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-static const struct mxc_usbh_platform_data otg_pdata __initconst = {
-        .init   = eukrea_cpuimx25_otg_init,
-        .portsc = MXC_EHCI_MODE_UTMI,
-};
-static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
-                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
-}
-static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
-        .init   = eukrea_cpuimx25_usbh2_init,
-        .portsc = MXC_EHCI_MODE_SERIAL,
-};
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI,
-        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
-};
-static bool otg_mode_host __initdata;
-static int __init eukrea_cpuimx25_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
-static void __init eukrea_cpuimx25_init(void)
-{
-        imx25_soc_init();
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
-                        ARRAY_SIZE(eukrea_cpuimx25_pads)))
-                printk(KERN_ERR "error setting cpuimx25 pads !\n");
-        imx25_add_imx_uart0(&uart_pdata);
-        imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        imx25_add_imxdi_rtc();
-        imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx2_wdt();
-        i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
-                                ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
-        imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
-        if (otg_mode_host)
-                imx25_add_mxc_ehci_otg(&otg_pdata);
-        else
-                imx25_add_fsl_usb2_udc(&otg_device_pdata);
-        imx25_add_mxc_ehci_hs(&usbh2_pdata);
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
-        eukrea_mbimxsd25_baseboard_init();
-#endif
-}
-static void __init eukrea_cpuimx25_timer_init(void)
-{
-        mx25_clocks_init();
-}
-MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
-        /* Maintainer: Eukrea Electromatique */
-        .atag_offset = 0x100,
-        .map_io = mx25_map_io,
-        .init_early = imx25_init_early,
-        .init_irq = mx25_init_irq,
-        .init_time = eukrea_cpuimx25_timer_init,
-        .init_machine = eukrea_cpuimx25_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/mach-imx25.c
index 25defbdb06c4..9379fd0a7b4d 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/mach-imx25.c
@@ -10,12 +10,29 @@
 */
 #include <linux/irq.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include "common.h"
-#include "mx25.h"
+#include "hardware.h"
+static void __init imx25_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX25);
+}
+static void __init mx25_init_irq(void)
+{
+        struct device_node *np;
+        void __iomem *avic_base;
+        np = of_find_compatible_node(NULL, NULL, "fsl,avic");
+        avic_base = of_iomap(np, 0);
+        BUG_ON(!avic_base);
+        mxc_init_irq(avic_base);
+}
 static const char * const imx25_dt_board_compat[] __initconst = {
        "fsl,imx25",
@@ -23,7 +40,6 @@ static const char * const imx25_dt_board_compat[] __initconst = {
 };
 DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
-        .map_io         = mx25_map_io,
        .init_early     = imx25_init_early,
        .init_irq       = mx25_init_irq,
        .dt_compat      = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9de3412af406..3ab61549ce0f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -388,10 +388,10 @@ static void __init imx6q_map_io(void)
 static void __init imx6q_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 24bfaaf944c8..12a1b098fc6a 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
 static void __init imx6sl_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 66988eb6a3a4..f17b7004c24b 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
 static void __init imx6sx_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
deleted file mode 100644
index 0d01e367b062..000000000000
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-/*
- * This machine is known as:
- *  - i.MX25 3-Stack Development System
- *  - i.MX25 Platform Development Kit (i.MX25 PDK)
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/usb/otg.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "devices-imx25.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx25.h"
-#include "mx25.h"
-#define MX25PDK_CAN_PWDN        IMX_GPIO_NR(4, 6)
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static iomux_v3_cfg_t mx25pdk_pads[] = {
-        MX25_PAD_FEC_MDC__FEC_MDC,
-        MX25_PAD_FEC_MDIO__FEC_MDIO,
-        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-        MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
-        MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
-        /* LCD */
-        MX25_PAD_LD0__LD0,
-        MX25_PAD_LD1__LD1,
-        MX25_PAD_LD2__LD2,
-        MX25_PAD_LD3__LD3,
-        MX25_PAD_LD4__LD4,
-        MX25_PAD_LD5__LD5,
-        MX25_PAD_LD6__LD6,
-        MX25_PAD_LD7__LD7,
-        MX25_PAD_LD8__LD8,
-        MX25_PAD_LD9__LD9,
-        MX25_PAD_LD10__LD10,
-        MX25_PAD_LD11__LD11,
-        MX25_PAD_LD12__LD12,
-        MX25_PAD_LD13__LD13,
-        MX25_PAD_LD14__LD14,
-        MX25_PAD_LD15__LD15,
-        MX25_PAD_GPIO_E__LD16,
-        MX25_PAD_GPIO_F__LD17,
-        MX25_PAD_HSYNC__HSYNC,
-        MX25_PAD_VSYNC__VSYNC,
-        MX25_PAD_LSCLK__LSCLK,
-        MX25_PAD_OE_ACD__OE_ACD,
-        MX25_PAD_CONTRAST__CONTRAST,
-        /* Keypad */
-        MX25_PAD_KPP_ROW0__KPP_ROW0,
-        MX25_PAD_KPP_ROW1__KPP_ROW1,
-        MX25_PAD_KPP_ROW2__KPP_ROW2,
-        MX25_PAD_KPP_ROW3__KPP_ROW3,
-        MX25_PAD_KPP_COL0__KPP_COL0,
-        MX25_PAD_KPP_COL1__KPP_COL1,
-        MX25_PAD_KPP_COL2__KPP_COL2,
-        MX25_PAD_KPP_COL3__KPP_COL3,
-        /* SD1 */
-        MX25_PAD_SD1_CMD__SD1_CMD,
-        MX25_PAD_SD1_CLK__SD1_CLK,
-        MX25_PAD_SD1_DATA0__SD1_DATA0,
-        MX25_PAD_SD1_DATA1__SD1_DATA1,
-        MX25_PAD_SD1_DATA2__SD1_DATA2,
-        MX25_PAD_SD1_DATA3__SD1_DATA3,
-        MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
-        MX25_PAD_A15__GPIO_2_1, /* CardDetect */
-        /* I2C1 */
-        MX25_PAD_I2C1_CLK__I2C1_CLK,
-        MX25_PAD_I2C1_DAT__I2C1_DAT,
-        /* CAN1 */
-        MX25_PAD_GPIO_A__CAN1_TX,
-        MX25_PAD_GPIO_B__CAN1_RX,
-        MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */
-};
-static const struct fec_platform_data mx25_fec_pdata __initconst = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
-};
-#define FEC_ENABLE_GPIO         IMX_GPIO_NR(2, 3)
-#define FEC_RESET_B_GPIO        IMX_GPIO_NR(4, 8)
-static void __init mx25pdk_fec_reset(void)
-{
-        gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
-        gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
-        gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
-        gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
-        udelay(2);
-        /* turn on PHY power and lift reset */
-        gpio_set_value(FEC_ENABLE_GPIO, 1);
-        gpio_set_value(FEC_RESET_B_GPIO, 1);
-}
-static const struct mxc_nand_platform_data
-mx25pdk_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-static struct imx_fb_videomode mx25pdk_modes[] = {
-        {
-                .mode   = {
-                        .name           = "CRT-VGA",
-                        .refresh        = 60,
-                        .xres           = 640,
-                        .yres           = 480,
-                        .pixclock       = 39683,
-                        .left_margin    = 45,
-                        .right_margin   = 114,
-                        .upper_margin   = 33,
-                        .lower_margin   = 11,
-                        .hsync_len      = 1,
-                        .vsync_len      = 1,
-                },
-                .bpp    = 16,
-                .pcr    = 0xFA208B80,
-        },
-};
-static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
-        .mode           = mx25pdk_modes,
-        .num_modes      = ARRAY_SIZE(mx25pdk_modes),
-        .pwmr           = 0x00A903FF,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020010,
-};
-static const uint32_t mx25pdk_keymap[] = {
-        KEY(0, 0, KEY_UP),
-        KEY(0, 1, KEY_DOWN),
-        KEY(0, 2, KEY_VOLUMEDOWN),
-        KEY(0, 3, KEY_HOME),
-        KEY(1, 0, KEY_RIGHT),
-        KEY(1, 1, KEY_LEFT),
-        KEY(1, 2, KEY_ENTER),
-        KEY(1, 3, KEY_VOLUMEUP),
-        KEY(2, 0, KEY_F6),
-        KEY(2, 1, KEY_F8),
-        KEY(2, 2, KEY_F9),
-        KEY(2, 3, KEY_F10),
-        KEY(3, 0, KEY_F1),
-        KEY(3, 1, KEY_F2),
-        KEY(3, 2, KEY_F3),
-        KEY(3, 3, KEY_POWER),
-};
-static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
-        .keymap         = mx25pdk_keymap,
-        .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
-};
-static int mx25pdk_usbh2_init(struct platform_device *pdev)
-{
-        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
-        .init   = mx25pdk_usbh2_init,
-        .portsc = MXC_EHCI_MODE_SERIAL,
-};
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI,
-};
-static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
-        .bitrate = 100000,
-};
-#define SD1_GPIO_WP     IMX_GPIO_NR(2, 0)
-#define SD1_GPIO_CD     IMX_GPIO_NR(2, 1)
-static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
-        .wp_gpio = SD1_GPIO_WP,
-        .cd_gpio = SD1_GPIO_CD,
-        .wp_type = ESDHC_WP_GPIO,
-        .cd_type = ESDHC_CD_GPIO,
-};
-static void __init mx25pdk_init(void)
-{
-        imx25_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
-                        ARRAY_SIZE(mx25pdk_pads));
-        imx25_add_imx_uart0(&uart_pdata);
-        imx25_add_fsl_usb2_udc(&otg_device_pdata);
-        imx25_add_mxc_ehci_hs(&usbh2_pdata);
-        imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        imx25_add_imxdi_rtc();
-        imx25_add_imx_fb(&mx25pdk_fb_pdata);
-        imx25_add_imx2_wdt();
-        mx25pdk_fec_reset();
-        imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx_keypad(&mx25pdk_keymap_data);
-        imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
-        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
-        gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
-        imx25_add_flexcan0();
-}
-static void __init mx25pdk_timer_init(void)
-{
-        mx25_clocks_init();
-}
-MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx25_map_io,
-        .init_early = imx25_init_early,
-        .init_irq = mx25_init_irq,
-        .init_time      = mx25pdk_timer_init,
-        .init_machine = mx25pdk_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 72cd77d21f63..7e315f00648d 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -166,7 +166,7 @@ static struct platform_device *devices[] __initdata = {
        &mx35pdk_flash,
 };
-static iomux_v3_cfg_t mx35pdk_pads[] = {
+static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
        /* UART1 */
        MX35_PAD_CTS1__UART1_CTS,
        MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index b623bcaca76c..e447e59c0604 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
        &pcm043_flash,
 };
-static iomux_v3_cfg_t pcm043_pads[] = {
+static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
        /* UART1 */
        MX35_PAD_CTS1__UART1_CTS,
        MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 97836e94451c..27a8f7e3ec08 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
        }
 };
-static iomux_v3_cfg_t vpr200_pads[] = {
+static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
        /* UART1 */
        MX35_PAD_TXD1__UART1_TXD_MUX,
        MX35_PAD_RXD1__UART1_RXD_MUX,
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
deleted file mode 100644
index 5211f62c624e..000000000000
--- a/arch/arm/mach-imx/mm-imx25.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/pinctrl/machine.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-#include "mx25.h"
-/*
- * This table defines static virtual address mappings for I/O regions.
- * These are the mappings common across all MX25 boards.
- */
-static struct map_desc mx25_io_desc[] __initdata = {
-        imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
-};
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx25_map_io(void)
-{
-        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
-}
-void __init imx25_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX25);
-        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-}
-void __init mx25_init_irq(void)
-{
-        mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
-}
-static struct sdma_platform_data imx25_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx25.bin",
-};
-static const struct resource imx25_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
-};
-void __init imx25_soc_init(void)
-{
-        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
-        mxc_device_init();
-        /* i.mx25 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
-        mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
-        mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
-        mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
-        pinctrl_provide_dummies();
-        /* i.mx25 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
-        /* i.mx25 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
-                                        ARRAY_SIZE(imx25_audmux_res));
-}
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h
deleted file mode 100644
index ec466400a200..000000000000
--- a/arch/arm/mach-imx/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
-#ifndef __MACH_MX25_H__
-#define __MACH_MX25_H__
-#define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_SIZE                 SZ_1M
-#define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_SIZE                 SZ_1M
-#define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_SIZE                  SZ_1M
-#define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
-#define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
-#define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
-#define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
-#define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
-#define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
-#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
-#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
-#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
-#define MX25_GPIO4_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0x9c000)
-#define MX25_PWM2_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa0000)
-#define MX25_GPIO3_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xa4000)
-#define MX25_PWM3_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa8000)
-#define MX25_PWM4_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xc8000)
-#define MX25_GPIO1_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xd0000)
-#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
-#define MX25_PWM1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xe0000)
-#define MX25_UART1_BASE_ADDR            0x43f90000
-#define MX25_UART2_BASE_ADDR            0x43f94000
-#define MX25_AUDMUX_BASE_ADDR           0x43fb0000
-#define MX25_UART3_BASE_ADDR            0x5000c000
-#define MX25_UART4_BASE_ADDR            0x50008000
-#define MX25_UART5_BASE_ADDR            0x5002c000
-#define MX25_CSPI3_BASE_ADDR            0x50004000
-#define MX25_CSPI2_BASE_ADDR            0x50010000
-#define MX25_FEC_BASE_ADDR              0x50038000
-#define MX25_SSI2_BASE_ADDR             0x50014000
-#define MX25_SSI1_BASE_ADDR             0x50034000
-#define MX25_NFC_BASE_ADDR              0xbb000000
-#define MX25_IIM_BASE_ADDR              0x53ff0000
-#define MX25_DRYICE_BASE_ADDR           0x53ffc000
-#define MX25_ESDHC1_BASE_ADDR           0x53fb4000
-#define MX25_ESDHC2_BASE_ADDR           0x53fb8000
-#define MX25_LCDC_BASE_ADDR             0x53fbc000
-#define MX25_KPP_BASE_ADDR              0x43fa8000
-#define MX25_SDMA_BASE_ADDR             0x53fd4000
-#define MX25_USB_BASE_ADDR              0x53ff4000
-#define MX25_USB_OTG_BASE_ADDR                  (MX25_USB_BASE_ADDR + 0x0000)
-/*
- * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
- * for the host controller.  Early documentation drafts specified 0x400 and
- * Freescale internal sources confirm only the latter value to work.
- */
-#define MX25_USB_HS_BASE_ADDR                   (MX25_USB_BASE_ADDR + 0x0400)
-#define MX25_CSI_BASE_ADDR              0x53ff8000
-#define MX25_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX25_IO_ADDRESS(x)              IOMEM(MX25_IO_P2V(x))
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX25_INT_CSPI3          (NR_IRQS_LEGACY + 0)
-#define MX25_INT_I2C1           (NR_IRQS_LEGACY + 3)
-#define MX25_INT_I2C2           (NR_IRQS_LEGACY + 4)
-#define MX25_INT_UART4          (NR_IRQS_LEGACY + 5)
-#define MX25_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
-#define MX25_INT_ESDHC1         (NR_IRQS_LEGACY + 9)
-#define MX25_INT_I2C3           (NR_IRQS_LEGACY + 10)
-#define MX25_INT_SSI2           (NR_IRQS_LEGACY + 11)
-#define MX25_INT_SSI1           (NR_IRQS_LEGACY + 12)
-#define MX25_INT_CSPI2          (NR_IRQS_LEGACY + 13)
-#define MX25_INT_CSPI1          (NR_IRQS_LEGACY + 14)
-#define MX25_INT_GPIO3          (NR_IRQS_LEGACY + 16)
-#define MX25_INT_CSI            (NR_IRQS_LEGACY + 17)
-#define MX25_INT_UART3          (NR_IRQS_LEGACY + 18)
-#define MX25_INT_GPIO4          (NR_IRQS_LEGACY + 23)
-#define MX25_INT_KPP            (NR_IRQS_LEGACY + 24)
-#define MX25_INT_DRYICE         (NR_IRQS_LEGACY + 25)
-#define MX25_INT_PWM1           (NR_IRQS_LEGACY + 26)
-#define MX25_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX25_INT_NFC            (NR_IRQS_LEGACY + 33)
-#define MX25_INT_SDMA           (NR_IRQS_LEGACY + 34)
-#define MX25_INT_USB_HS         (NR_IRQS_LEGACY + 35)
-#define MX25_INT_PWM2           (NR_IRQS_LEGACY + 36)
-#define MX25_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
-#define MX25_INT_LCDC           (NR_IRQS_LEGACY + 39)
-#define MX25_INT_UART5          (NR_IRQS_LEGACY + 40)
-#define MX25_INT_PWM3           (NR_IRQS_LEGACY + 41)
-#define MX25_INT_PWM4           (NR_IRQS_LEGACY + 42)
-#define MX25_INT_CAN1           (NR_IRQS_LEGACY + 43)
-#define MX25_INT_CAN2           (NR_IRQS_LEGACY + 44)
-#define MX25_INT_UART1          (NR_IRQS_LEGACY + 45)
-#define MX25_INT_GPIO2          (NR_IRQS_LEGACY + 51)
-#define MX25_INT_GPIO1          (NR_IRQS_LEGACY + 52)
-#define MX25_INT_GPT1           (NR_IRQS_LEGACY + 54)
-#define MX25_INT_FEC            (NR_IRQS_LEGACY + 57)
-#define MX25_DMA_REQ_SSI2_RX1   22
-#define MX25_DMA_REQ_SSI2_TX1   23
-#define MX25_DMA_REQ_SSI2_RX0   24
-#define MX25_DMA_REQ_SSI2_TX0   25
-#define MX25_DMA_REQ_SSI1_RX1   26
-#define MX25_DMA_REQ_SSI1_TX1   27
-#define MX25_DMA_REQ_SSI1_RX0   28
-#define MX25_DMA_REQ_SSI1_TX0   29
-#ifndef __ASSEMBLY__
-extern int mx25_revision(void);
-#endif
-#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 46fd695203c7..6a7c6fc780cc 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
         *    Low-Power mode.
         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
         *    is set (set bits 0-1 of CCM_CLPCR).
+         *
+         * Note that IRQ #32 is GIC SPI #0.
         */
-        imx_gpc_hwirq_unmask(32);
+        imx_gpc_hwirq_unmask(0);
        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_hwirq_mask(32);
+        imx_gpc_hwirq_mask(0);
        return 0;
 }
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index f7e463ca0287..9f59e58da3a4 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -1,6 +1,7 @@
 menuconfig ARCH_MEDIATEK
        bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
        select ARM_GIC
+        select PINCTRL
        select MTK_TIMER
        help
          Support for Mediatek MT65xx & MT81xx SoCs
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 18301dc9d2e7..0743e2059645 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -1,8 +1,11 @@
 menuconfig ARCH_MESON
        bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_IRQ_CHIP
        select ARM_GIC
        select CACHE_L2X0
+        select PINCTRL
+        select PINCTRL_MESON
 if ARCH_MESON
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
deleted file mode 100644
index a6b50e62a495..000000000000
--- a/arch/arm/mach-msm/Kconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-if ARCH_MSM
-choice
-        prompt "Qualcomm MSM SoC Type"
-        default ARCH_MSM7X00A
-        depends on ARCH_MSM
-config ARCH_MSM7X00A
-        bool "MSM7x00A / MSM7x01A"
-        select ARCH_MSM_ARM11
-        select CPU_V6
-        select GPIO_MSM_V1
-        select MACH_TROUT if !MACH_HALIBUT
-        select MSM_PROC_COMM
-        select MSM_SMD
-        select CLKSRC_QCOM
-        select MSM_SMD_PKG3
-config ARCH_MSM7X30
-        bool "MSM7x30"
-        select ARCH_MSM_SCORPION
-        select CPU_V7
-        select GPIO_MSM_V1
-        select MACH_MSM7X30_SURF # if !
-        select MSM_GPIOMUX
-        select MSM_PROC_COMM
-        select MSM_SMD
-        select CLKSRC_QCOM
-        select MSM_VIC
-config ARCH_QSD8X50
-        bool "QSD8X50"
-        select ARCH_MSM_SCORPION
-        select CPU_V7
-        select GPIO_MSM_V1
-        select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
-        select MSM_GPIOMUX
-        select MSM_PROC_COMM
-        select MSM_SMD
-        select CLKSRC_QCOM
-        select MSM_VIC
-endchoice
-config MSM_SOC_REV_A
-        bool
-config  ARCH_MSM_ARM11
-        bool
-config  ARCH_MSM_SCORPION
-        bool
-config  MSM_VIC
-        bool
-menu "Qualcomm MSM Board Type"
-        depends on ARCH_MSM
-config MACH_HALIBUT
-        depends on ARCH_MSM
-        depends on ARCH_MSM7X00A
-        bool "Halibut Board (QCT SURF7201A)"
-        help
-          Support for the Qualcomm SURF7201A eval board.
-config MACH_TROUT
-        depends on ARCH_MSM
-        depends on ARCH_MSM7X00A
-        bool "HTC Dream (aka trout)"
-        help
-          Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
-config MACH_MSM7X30_SURF
-        depends on ARCH_MSM7X30
-        bool "MSM7x30 SURF"
-        help
-          Support for the Qualcomm MSM7x30 SURF eval board.
-config MACH_QSD8X50_SURF
-        depends on ARCH_QSD8X50
-        bool "QSD8x50 SURF"
-        help
-          Support for the Qualcomm QSD8x50 SURF eval board.
-config MACH_QSD8X50A_ST1_5
-        depends on ARCH_QSD8X50
-        bool "QSD8x50A ST1.5"
-        select MSM_SOC_REV_A
-        help
-          Support for the Qualcomm ST1.5.
-endmenu
-config MSM_SMD_PKG3
-        bool
-config MSM_PROC_COMM
-        bool
-config MSM_SMD
-        bool
-config MSM_GPIOMUX
-        bool
-        help
-          Support for MSM V1 TLMM GPIOMUX architecture.
-endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
deleted file mode 100644
index 27c078a568df..000000000000
--- a/arch/arm/mach-msm/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
-obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_MSM_VIC) += irq-vic.o
-obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
-obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
-obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
-obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
-obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
-obj-$(CONFIG_MSM_SMD) += last_radio_log.o
-obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
-obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
-obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
-obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
-obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
-obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
deleted file mode 100644
index 9b803a578b4d..000000000000
--- a/arch/arm/mach-msm/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-  zreladdr-y            += 0x10008000
-params_phys-y           := 0x10000100
-initrd_phys-y           := 0x10800000
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
deleted file mode 100644
index fc832040c6e9..000000000000
--- a/arch/arm/mach-msm/board-halibut.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* linux/arch/arm/mach-msm/board-halibut.c
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/smc91x.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/setup.h>
-#include <mach/irqs.h>
-#include <mach/msm_iomap.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include "devices.h"
-#include "common.h"
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = 0x9C004300,
-                .end    = 0x9C004400,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = MSM_GPIO_TO_INT(49),
-                .end    = MSM_GPIO_TO_INT(49),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-static struct smc91x_platdata smc91x_platdata = {
-        .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-        .dev.platform_data = &smc91x_platdata,
-};
-static struct platform_device *devices[] __initdata = {
-        &msm_clock_7x01a,
-        &msm_device_gpio_7201,
-        &msm_device_uart3,
-        &msm_device_smd,
-        &msm_device_nand,
-        &msm_device_hsusb,
-        &msm_device_i2c,
-        &smc91x_device,
-};
-static void __init halibut_init_early(void)
-{
-        arch_ioremap_caller = __msm_ioremap_caller;
-}
-static void __init halibut_init_irq(void)
-{
-        msm_init_irq();
-}
-static void __init halibut_init(void)
-{
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-static void __init halibut_map_io(void)
-{
-        msm_map_common_io();
-}
-static void __init halibut_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
-        .atag_offset    = 0x100,
-        .map_io         = halibut_map_io,
-        .init_early     = halibut_init_early,
-        .init_irq       = halibut_init_irq,
-        .init_machine   = halibut_init,
-        .init_late      = halibut_init_late,
-        .init_time      = msm7x01_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
deleted file mode 100644
index 8f5ecdc4f3ce..000000000000
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/smsc911x.h>
-#include <linux/usb/msm_hsusb.h>
-#include <linux/clkdev.h>
-#include <linux/memblock.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-#include <asm/setup.h>
-#include <mach/clk.h>
-#include <mach/msm_iomap.h>
-#include <mach/dma.h>
-#include <mach/vreg.h>
-#include "devices.h"
-#include "gpiomux.h"
-#include "proc_comm.h"
-#include "common.h"
-static void __init msm7x30_fixup(struct tag *tag, char **cmdline)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
-                        tag->u.mem.start = 0;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-static void __init msm7x30_reserve(void)
-{
-        memblock_remove(0x0, SZ_2M);
-}
-static int hsusb_phy_init_seq[] = {
-        0x30, 0x32,     /* Enable and set Pre-Emphasis Depth to 20% */
-        0x02, 0x36,     /* Disable CDR Auto Reset feature */
-        -1
-};
-static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
-{
-        int ret;
-        if (assert) {
-                ret = clk_reset(link_clk, CLK_RESET_ASSERT);
-                if (ret)
-                        pr_err("usb hs_clk assert failed\n");
-        } else {
-                ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
-                if (ret)
-                        pr_err("usb hs_clk deassert failed\n");
-        }
-        return ret;
-}
-static int hsusb_phy_clk_reset(struct clk *phy_clk)
-{
-        int ret;
-        ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
-        if (ret) {
-                pr_err("usb phy clk assert failed\n");
-                return ret;
-        }
-        usleep_range(10000, 12000);
-        ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
-        if (ret)
-                pr_err("usb phy clk deassert failed\n");
-        return ret;
-}
-static struct msm_otg_platform_data msm_otg_pdata = {
-        .phy_init_seq           = hsusb_phy_init_seq,
-        .mode                   = USB_DR_MODE_PERIPHERAL,
-        .otg_control            = OTG_PHY_CONTROL,
-        .link_clk_reset         = hsusb_link_clk_reset,
-        .phy_clk_reset          = hsusb_phy_clk_reset,
-};
-struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-        [49] = { /* UART2 RFR */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [50] = { /* UART2 CTS */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [51] = { /* UART2 RX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-        [52] = { /* UART2 TX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
-        },
-#endif
-};
-static struct platform_device *devices[] __initdata = {
-        &msm_clock_7x30,
-        &msm_device_gpio_7x30,
-#if defined(CONFIG_SERIAL_MSM)
-        &msm_device_uart2,
-#endif
-        &msm_device_smd,
-        &msm_device_otg,
-        &msm_device_hsusb,
-        &msm_device_hsusb_host,
-};
-static void __init msm7x30_init_irq(void)
-{
-        msm_init_irq();
-}
-static void __init msm7x30_init(void)
-{
-        msm_device_otg.dev.platform_data = &msm_otg_pdata;
-        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
-        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-static void __init msm7x30_map_io(void)
-{
-        msm_map_msm7x30_io();
-}
-static void __init msm7x30_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
-        .atag_offset = 0x100,
-        .fixup = msm7x30_fixup,
-        .reserve = msm7x30_reserve,
-        .map_io = msm7x30_map_io,
-        .init_irq = msm7x30_init_irq,
-        .init_machine = msm7x30_init,
-        .init_late = msm7x30_init_late,
-        .init_time      = msm7x30_timer_init,
-MACHINE_END
-MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
-        .atag_offset = 0x100,
-        .fixup = msm7x30_fixup,
-        .reserve = msm7x30_reserve,
-        .map_io = msm7x30_map_io,
-        .init_irq = msm7x30_init_irq,
-        .init_machine = msm7x30_init,
-        .init_late = msm7x30_init_late,
-        .init_time      = msm7x30_timer_init,
-MACHINE_END
-MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
-        .atag_offset = 0x100,
-        .fixup = msm7x30_fixup,
-        .reserve = msm7x30_reserve,
-        .map_io = msm7x30_map_io,
-        .init_irq = msm7x30_init_irq,
-        .init_machine = msm7x30_init,
-        .init_late = msm7x30_init_late,
-        .init_time      = msm7x30_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
deleted file mode 100644
index 10016a3bc698..000000000000
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/usb/msm_hsusb.h>
-#include <linux/err.h>
-#include <linux/clkdev.h>
-#include <linux/smc91x.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <mach/irqs.h>
-#include <mach/sirc.h>
-#include <mach/vreg.h>
-#include <mach/clk.h>
-#include <linux/platform_data/mmc-msm_sdcc.h>
-#include "devices.h"
-#include "common.h"
-static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
-/* Leave smc91x resources empty here, as we'll fill them in
- * at run-time: they vary from board to board, and the true
- * configuration won't be known until boot.
- */
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-static struct smc91x_platdata smc91x_platdata = {
-        .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-        .dev.platform_data = &smc91x_platdata,
-};
-static int __init msm_init_smc91x(void)
-{
-        if (machine_is_qsd8x50_surf()) {
-                smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
-                smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
-                smc91x_resources[1].start =
-                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
-                smc91x_resources[1].end   =
-                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
-                platform_device_register(&smc91x_device);
-        }
-        return 0;
-}
-module_init(msm_init_smc91x);
-static int hsusb_phy_init_seq[] = {
-        0x08, 0x31,     /* Increase HS Driver Amplitude */
-        0x20, 0x32,     /* Enable and set Pre-Emphasis Depth to 10% */
-        -1
-};
-static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
-{
-        int ret;
-        if (assert) {
-                ret = clk_reset(link_clk, CLK_RESET_ASSERT);
-                if (ret)
-                        pr_err("usb hs_clk assert failed\n");
-        } else {
-                ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
-                if (ret)
-                        pr_err("usb hs_clk deassert failed\n");
-        }
-        return ret;
-}
-static int hsusb_phy_clk_reset(struct clk *phy_clk)
-{
-        int ret;
-        ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
-        if (ret) {
-                pr_err("usb phy clk assert failed\n");
-                return ret;
-        }
-        usleep_range(10000, 12000);
-        ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
-        if (ret)
-                pr_err("usb phy clk deassert failed\n");
-        return ret;
-}
-static struct msm_otg_platform_data msm_otg_pdata = {
-        .phy_init_seq           = hsusb_phy_init_seq,
-        .mode                   = USB_DR_MODE_PERIPHERAL,
-        .otg_control            = OTG_PHY_CONTROL,
-        .link_clk_reset         = hsusb_link_clk_reset,
-        .phy_clk_reset          = hsusb_phy_clk_reset,
-};
-static struct platform_device *devices[] __initdata = {
-        &msm_clock_8x50,
-        &msm_device_gpio_8x50,
-        &msm_device_uart3,
-        &msm_device_smd,
-        &msm_device_otg,
-        &msm_device_hsusb,
-        &msm_device_hsusb_host,
-};
-static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
-        {51, "sdc1_dat_3"},
-        {52, "sdc1_dat_2"},
-        {53, "sdc1_dat_1"},
-        {54, "sdc1_dat_0"},
-        {55, "sdc1_cmd"},
-        {56, "sdc1_clk"}
-};
-static struct vreg *vreg_mmc;
-static unsigned long vreg_sts;
-static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
-{
-        int rc = 0;
-        struct platform_device *pdev;
-        pdev = container_of(dv, struct platform_device, dev);
-        if (vdd == 0) {
-                if (!vreg_sts)
-                        return 0;
-                clear_bit(pdev->id, &vreg_sts);
-                if (!vreg_sts) {
-                        rc = vreg_disable(vreg_mmc);
-                        if (rc)
-                                pr_err("vreg_mmc disable failed for slot "
-                                                "%d: %d\n", pdev->id, rc);
-                }
-                return 0;
-        }
-        if (!vreg_sts) {
-                rc = vreg_set_level(vreg_mmc, 2900);
-                if (rc)
-                        pr_err("vreg_mmc set level failed for slot %d: %d\n",
-                                        pdev->id, rc);
-                rc = vreg_enable(vreg_mmc);
-                if (rc)
-                        pr_err("vreg_mmc enable failed for slot %d: %d\n",
-                                        pdev->id, rc);
-        }
-        set_bit(pdev->id, &vreg_sts);
-        return 0;
-}
-static struct msm_mmc_gpio_data sdc1_gpio = {
-        .gpio = sdc1_gpio_cfg,
-        .size = ARRAY_SIZE(sdc1_gpio_cfg),
-};
-static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
-        .ocr_mask       = MMC_VDD_27_28 | MMC_VDD_28_29,
-        .translate_vdd  = msm_sdcc_setup_power,
-        .gpio_data = &sdc1_gpio,
-};
-static void __init qsd8x50_init_mmc(void)
-{
-        vreg_mmc = vreg_get(NULL, "gp5");
-        if (IS_ERR(vreg_mmc)) {
-                pr_err("vreg get for vreg_mmc failed (%ld)\n",
-                                PTR_ERR(vreg_mmc));
-                return;
-        }
-        msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
-}
-static void __init qsd8x50_map_io(void)
-{
-        msm_map_qsd8x50_io();
-}
-static void __init qsd8x50_init_irq(void)
-{
-        msm_init_irq();
-        msm_init_sirc();
-}
-static void __init qsd8x50_init(void)
-{
-        msm_device_otg.dev.platform_data = &msm_otg_pdata;
-        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
-        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        qsd8x50_init_mmc();
-}
-static void __init qsd8x50_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
-        .atag_offset = 0x100,
-        .map_io = qsd8x50_map_io,
-        .init_irq = qsd8x50_init_irq,
-        .init_machine = qsd8x50_init,
-        .init_late = qsd8x50_init_late,
-        .init_time      = qsd8x50_timer_init,
-MACHINE_END
-MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
-        .atag_offset = 0x100,
-        .map_io = qsd8x50_map_io,
-        .init_irq = qsd8x50_init_irq,
-        .init_machine = qsd8x50_init,
-        .init_late = qsd8x50_init_late,
-        .init_time      = qsd8x50_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
deleted file mode 100644
index e50967926dcd..000000000000
--- a/arch/arm/mach-msm/board-sapphire.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* linux/arch/arm/mach-msm/board-sapphire.c
- * Copyright (C) 2007-2009 HTC Corporation.
- * Author: Thomas Tsai <thomas_tsai@htc.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <mach/vreg.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/setup.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/memblock.h>
-#include "gpio_chip.h"
-#include "board-sapphire.h"
-#include "proc_comm.h"
-#include "devices.h"
-#include "common.h"
-void msm_init_irq(void);
-void msm_init_gpio(void);
-static struct platform_device *devices[] __initdata = {
-        &msm_device_smd,
-        &msm_device_dmov,
-        &msm_device_nand,
-        &msm_device_uart1,
-        &msm_device_uart3,
-};
-void msm_timer_init(void);
-static void __init sapphire_init_irq(void)
-{
-        msm_init_irq();
-}
-static void __init sapphire_init(void)
-{
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-static struct map_desc sapphire_io_desc[] __initdata = {
-        {
-                .virtual = SAPPHIRE_CPLD_BASE,
-                .pfn     = __phys_to_pfn(SAPPHIRE_CPLD_START),
-                .length  = SAPPHIRE_CPLD_SIZE,
-                .type    = MT_DEVICE_NONSHARED
-        }
-};
-static void __init sapphire_fixup(struct tag *tags, char **cmdline)
-{
-        int smi_sz = parse_tag_smi((const struct tag *)tags);
-        if (smi_sz == 32) {
-                memblock_add(PHYS_OFFSET, 84*SZ_1M);
-        } else if (smi_sz == 64) {
-                memblock_add(PHYS_OFFSET, 101*SZ_1M);
-        } else {
-                memblock_add(PHYS_OFFSET, 101*SZ_1M);
-                /* Give a default value when not get smi size */
-                smi_sz = 64;
-        }
-}
-static void __init sapphire_map_io(void)
-{
-        msm_map_common_io();
-        iotable_init(sapphire_io_desc, ARRAY_SIZE(sapphire_io_desc));
-        msm_clock_init();
-}
-static void __init sapphire_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(SAPPHIRE, "sapphire")
-/* Maintainer: Brian Swetland <swetland@google.com> */
-        .atag_offset    = 0x100,
-        .fixup          = sapphire_fixup,
-        .map_io         = sapphire_map_io,
-        .init_irq       = sapphire_init_irq,
-        .init_machine   = sapphire_init,
-        .init_late      = sapphire_init_late,
-        .init_time      = msm_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
deleted file mode 100644
index 722ad63b7edc..000000000000
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * linux/arch/arm/mach-msm/gpio.c
- *
- * Copyright (C) 2005 HP Labs
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include "board-trout.h"
-static uint8_t trout_int_mask[2] = {
-        [0] = 0xff, /* mask all interrupts */
-        [1] = 0xff,
-};
-static uint8_t trout_sleep_int_mask[] = {
-        [0] = 0xff,
-        [1] = 0xff,
-};
-struct msm_gpio_chip {
-        struct gpio_chip        chip;
-        void __iomem            *reg;   /* Base of register bank */
-        u8                      shadow;
-};
-#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
-static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
-        unsigned mask = 1 << offset;
-        return !!(readb(msm_gpio->reg) & mask);
-}
-static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
-        unsigned mask = 1 << offset;
-        if (val)
-                msm_gpio->shadow |= mask;
-        else
-                msm_gpio->shadow &= ~mask;
-        writeb(msm_gpio->shadow, msm_gpio->reg);
-}
-static int msm_gpiolib_direction_input(struct gpio_chip *chip,
-                                        unsigned offset)
-{
-        msm_gpiolib_set(chip, offset, 0);
-        return 0;
-}
-static int msm_gpiolib_direction_output(struct gpio_chip *chip,
-                                         unsigned offset, int val)
-{
-        msm_gpiolib_set(chip, offset, val);
-        return 0;
-}
-static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        return TROUT_GPIO_TO_INT(offset + chip->base);
-}
-#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)           \
-        {                                                               \
-                .chip = {                                               \
-                        .label            = name,                       \
-                        .direction_input  = msm_gpiolib_direction_input,\
-                        .direction_output = msm_gpiolib_direction_output, \
-                        .get              = msm_gpiolib_get,            \
-                        .set              = msm_gpiolib_set,            \
-                        .to_irq           = trout_gpio_to_irq,          \
-                        .base             = base_gpio,                  \
-                        .ngpio            = 8,                          \
-                },                                                      \
-                .reg = reg_num + TROUT_CPLD_BASE,                       \
-                .shadow = shadow_val,                                   \
-        }
-static struct msm_gpio_chip msm_gpio_banks[] = {
-#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
-        /* H2W pins <-> UART1 */
-        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
-#else
-        /* H2W pins <-> UART3, Bluetooth <-> UART1 */
-        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x80),
-#endif
-        /* I2C pull */
-        TROUT_GPIO_BANK("MISC3", 0x02,   TROUT_GPIO_MISC3_BASE, 0x04),
-        TROUT_GPIO_BANK("MISC4", 0x04,   TROUT_GPIO_MISC4_BASE, 0),
-        /* mmdi 32k en */
-        TROUT_GPIO_BANK("MISC5", 0x06,   TROUT_GPIO_MISC5_BASE, 0x04),
-        TROUT_GPIO_BANK("INT2", 0x08,    TROUT_GPIO_INT2_BASE,  0),
-        TROUT_GPIO_BANK("MISC1", 0x0a,   TROUT_GPIO_MISC1_BASE, 0),
-        TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
-};
-static void trout_gpio_irq_ack(struct irq_data *d)
-{
-        int bank = TROUT_INT_TO_BANK(d->irq);
-        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
-        int reg = TROUT_BANK_TO_STAT_REG(bank);
-        /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
-        writeb(mask, TROUT_CPLD_BASE + reg);
-}
-static void trout_gpio_irq_mask(struct irq_data *d)
-{
-        unsigned long flags;
-        uint8_t reg_val;
-        int bank = TROUT_INT_TO_BANK(d->irq);
-        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
-        int reg = TROUT_BANK_TO_MASK_REG(bank);
-        local_irq_save(flags);
-        reg_val = trout_int_mask[bank] |= mask;
-        /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
-               d->irq, bank, reg_val);*/
-        writeb(reg_val, TROUT_CPLD_BASE + reg);
-        local_irq_restore(flags);
-}
-static void trout_gpio_irq_unmask(struct irq_data *d)
-{
-        unsigned long flags;
-        uint8_t reg_val;
-        int bank = TROUT_INT_TO_BANK(d->irq);
-        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
-        int reg = TROUT_BANK_TO_MASK_REG(bank);
-        local_irq_save(flags);
-        reg_val = trout_int_mask[bank] &= ~mask;
-        /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
-               d->irq, bank, reg_val);*/
-        writeb(reg_val, TROUT_CPLD_BASE + reg);
-        local_irq_restore(flags);
-}
-int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        unsigned long flags;
-        int bank = TROUT_INT_TO_BANK(d->irq);
-        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
-        local_irq_save(flags);
-        if(on)
-                trout_sleep_int_mask[bank] &= ~mask;
-        else
-                trout_sleep_int_mask[bank] |= mask;
-        local_irq_restore(flags);
-        return 0;
-}
-static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        int j, m;
-        unsigned v;
-        int bank;
-        int stat_reg;
-        int int_base = TROUT_INT_START;
-        uint8_t int_mask;
-        for (bank = 0; bank < 2; bank++) {
-                stat_reg = TROUT_BANK_TO_STAT_REG(bank);
-                v = readb(TROUT_CPLD_BASE + stat_reg);
-                int_mask = trout_int_mask[bank];
-                if (v & int_mask) {
-                        writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg);
-                        printk(KERN_ERR "trout_gpio_irq_handler: got masked "
-                               "interrupt: %d:%02x\n", bank, v & int_mask);
-                }
-                v &= ~int_mask;
-                while (v) {
-                        m = v & -v;
-                        j = fls(m) - 1;
-                        /*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b"
-                               "it %d irq %d\n", bank, v, m, j, int_base + j);*/
-                        v &= ~m;
-                        generic_handle_irq(int_base + j);
-                }
-                int_base += TROUT_INT_BANK0_COUNT;
-        }
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-}
-static struct irq_chip trout_gpio_irq_chip = {
-        .name          = "troutgpio",
-        .irq_ack       = trout_gpio_irq_ack,
-        .irq_mask      = trout_gpio_irq_mask,
-        .irq_unmask    = trout_gpio_irq_unmask,
-        .irq_set_wake  = trout_gpio_irq_set_wake,
-};
-/*
- * Called from the processor-specific init to enable GPIO pin support.
- */
-int __init trout_init_gpio(void)
-{
-        int i;
-        for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
-                irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
-                                         handle_edge_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-        for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
-                gpiochip_add(&msm_gpio_banks[i].chip);
-        irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
-        irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
-        irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
-        return 0;
-}
-postcore_initcall(trout_init_gpio);
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
deleted file mode 100644
index 3723e55819d6..000000000000
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* linux/arch/arm/mach-msm/board-trout-mmc.c
-** Author: Brian Swetland <swetland@google.com>
-*/
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sdio_ids.h>
-#include <linux/err.h>
-#include <linux/debugfs.h>
-#include <asm/io.h>
-#include <mach/vreg.h>
-#include <linux/platform_data/mmc-msm_sdcc.h>
-#include "devices.h"
-#include "board-trout.h"
-#include "proc_comm.h"
-#define DEBUG_SDSLOT_VDD 1
-/* ---- COMMON ---- */
-static void config_gpio_table(uint32_t *table, int len)
-{
-        int n;
-        unsigned id;
-        for(n = 0; n < len; n++) {
-                id = table[n];
-                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0);
-        }
-}
-/* ---- SDCARD ---- */
-static uint32_t sdcard_on_gpio_table[] = {
-        PCOM_GPIO_CFG(62, 2, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA), /* CLK */
-        PCOM_GPIO_CFG(63, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* CMD */
-        PCOM_GPIO_CFG(64, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT3 */
-        PCOM_GPIO_CFG(65, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT2 */
-        PCOM_GPIO_CFG(66, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT1 */
-        PCOM_GPIO_CFG(67, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT0 */
-};
-static uint32_t sdcard_off_gpio_table[] = {
-        PCOM_GPIO_CFG(62, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CLK */
-        PCOM_GPIO_CFG(63, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CMD */
-        PCOM_GPIO_CFG(64, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT3 */
-        PCOM_GPIO_CFG(65, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT2 */
-        PCOM_GPIO_CFG(66, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT1 */
-        PCOM_GPIO_CFG(67, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT0 */
-};
-static uint opt_disable_sdcard;
-static int __init trout_disablesdcard_setup(char *str)
-{
-        int cal = simple_strtol(str, NULL, 0);
-        
-        opt_disable_sdcard = cal;
-        return 1;
-}
-__setup("board_trout.disable_sdcard=", trout_disablesdcard_setup);
-static struct vreg *vreg_sdslot;        /* SD slot power */
-struct mmc_vdd_xlat {
-        int mask;
-        int level;
-};
-static struct mmc_vdd_xlat mmc_vdd_table[] = {
-        { MMC_VDD_165_195,      1800 },
-        { MMC_VDD_20_21,        2050 },
-        { MMC_VDD_21_22,        2150 },
-        { MMC_VDD_22_23,        2250 },
-        { MMC_VDD_23_24,        2350 },
-        { MMC_VDD_24_25,        2450 },
-        { MMC_VDD_25_26,        2550 },
-        { MMC_VDD_26_27,        2650 },
-        { MMC_VDD_27_28,        2750 },
-        { MMC_VDD_28_29,        2850 },
-        { MMC_VDD_29_30,        2950 },
-};
-static unsigned int sdslot_vdd = 0xffffffff;
-static unsigned int sdslot_vreg_enabled;
-static uint32_t trout_sdslot_switchvdd(struct device *dev, unsigned int vdd)
-{
-        int i, rc;
-        BUG_ON(!vreg_sdslot);
-        if (vdd == sdslot_vdd)
-                return 0;
-        sdslot_vdd = vdd;
-        if (vdd == 0) {
-#if DEBUG_SDSLOT_VDD
-                printk("%s: Disabling SD slot power\n", __func__);
-#endif
-                config_gpio_table(sdcard_off_gpio_table,
-                                  ARRAY_SIZE(sdcard_off_gpio_table));
-                vreg_disable(vreg_sdslot);
-                sdslot_vreg_enabled = 0;
-                return 0;
-        }
-        if (!sdslot_vreg_enabled) {
-                rc = vreg_enable(vreg_sdslot);
-                if (rc) {
-                        printk(KERN_ERR "%s: Error enabling vreg (%d)\n",
-                               __func__, rc);
-                }
-                config_gpio_table(sdcard_on_gpio_table,
-                                  ARRAY_SIZE(sdcard_on_gpio_table));
-                sdslot_vreg_enabled = 1;
-        }
-        for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) {
-                if (mmc_vdd_table[i].mask == (1 << vdd)) {
-#if DEBUG_SDSLOT_VDD
-                        printk("%s: Setting level to %u\n",
-                                __func__, mmc_vdd_table[i].level);
-#endif
-                        rc = vreg_set_level(vreg_sdslot,
-                                            mmc_vdd_table[i].level);
-                        if (rc) {
-                                printk(KERN_ERR
-                                       "%s: Error setting vreg level (%d)\n",
-                                       __func__, rc);
-                        }
-                        return 0;
-                }
-        }
-        printk(KERN_ERR "%s: Invalid VDD %d specified\n", __func__, vdd);
-        return 0;
-}
-static unsigned int trout_sdslot_status(struct device *dev)
-{
-        unsigned int status;
-        status = (unsigned int) gpio_get_value(TROUT_GPIO_SDMC_CD_N);
-        return (!status);
-}
-#define TROUT_MMC_VDD   MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \
-                        | MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \
-                        | MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \
-                        | MMC_VDD_28_29 | MMC_VDD_29_30
-static struct msm_mmc_platform_data trout_sdslot_data = {
-        .ocr_mask       = TROUT_MMC_VDD,
-        .status         = trout_sdslot_status,
-        .translate_vdd  = trout_sdslot_switchvdd,
-};
-int __init trout_init_mmc(unsigned int sys_rev)
-{
-        sdslot_vreg_enabled = 0;
-        vreg_sdslot = vreg_get(0, "gp6");
-        if (IS_ERR(vreg_sdslot))
-                return PTR_ERR(vreg_sdslot);
-        irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
-        if (!opt_disable_sdcard)
-                msm_add_sdcc(2, &trout_sdslot_data,
-                             TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0);
-        else
-                printk(KERN_INFO "trout: SD-Card interface disabled\n");
-        return 0;
-}
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
deleted file mode 100644
index 77b0a26f897f..000000000000
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* linux/arch/arm/mach-msm/board-trout-mddi.c
-** Author: Brian Swetland <swetland@google.com>
-*/
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/err.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/system_info.h>
-#include <linux/platform_data/video-msm_fb.h>
-#include <mach/vreg.h>
-#include "board-trout.h"
-#include "proc_comm.h"
-#include "clock-pcom.h"
-#include "devices.h"
-#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
-#define MDDI_CLIENT_CORE_BASE  0x108000
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define SPI_BLOCK_BASE         0x120000
-#define I2C_BLOCK_BASE         0x130000
-#define PWM_BLOCK_BASE         0x140000
-#define GPIO_BLOCK_BASE        0x150000
-#define SYSTEM_BLOCK1_BASE     0x160000
-#define SYSTEM_BLOCK2_BASE     0x170000
-#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
-#define SYSCLKENA   (MDDI_CLIENT_CORE_BASE|0x2C)
-#define PWM0OFF       (PWM_BLOCK_BASE|0x1C)
-#define V_VDDE2E_VDD2_GPIO 0
-#define MDDI_RST_N 82
-#define MDDICAP0    (MDDI_CLIENT_CORE_BASE|0x00)
-#define MDDICAP1    (MDDI_CLIENT_CORE_BASE|0x04)
-#define MDDICAP2    (MDDI_CLIENT_CORE_BASE|0x08)
-#define MDDICAP3    (MDDI_CLIENT_CORE_BASE|0x0C)
-#define MDCAPCHG    (MDDI_CLIENT_CORE_BASE|0x10)
-#define MDCRCERC    (MDDI_CLIENT_CORE_BASE|0x14)
-#define TTBUSSEL    (MDDI_CLIENT_CORE_BASE|0x18)
-#define DPSET0      (MDDI_CLIENT_CORE_BASE|0x1C)
-#define DPSET1      (MDDI_CLIENT_CORE_BASE|0x20)
-#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
-#define DPRUN       (MDDI_CLIENT_CORE_BASE|0x28)
-#define SYSCKENA    (MDDI_CLIENT_CORE_BASE|0x2C)
-#define TESTMODE    (MDDI_CLIENT_CORE_BASE|0x30)
-#define FIFOMONI    (MDDI_CLIENT_CORE_BASE|0x34)
-#define INTMONI     (MDDI_CLIENT_CORE_BASE|0x38)
-#define MDIOBIST    (MDDI_CLIENT_CORE_BASE|0x3C)
-#define MDIOPSET    (MDDI_CLIENT_CORE_BASE|0x40)
-#define BITMAP0     (MDDI_CLIENT_CORE_BASE|0x44)
-#define BITMAP1     (MDDI_CLIENT_CORE_BASE|0x48)
-#define BITMAP2     (MDDI_CLIENT_CORE_BASE|0x4C)
-#define BITMAP3     (MDDI_CLIENT_CORE_BASE|0x50)
-#define BITMAP4     (MDDI_CLIENT_CORE_BASE|0x54)
-#define SRST        (LCD_CONTROL_BLOCK_BASE|0x00)
-#define PORT_ENB    (LCD_CONTROL_BLOCK_BASE|0x04)
-#define START       (LCD_CONTROL_BLOCK_BASE|0x08)
-#define PORT        (LCD_CONTROL_BLOCK_BASE|0x0C)
-#define CMN         (LCD_CONTROL_BLOCK_BASE|0x10)
-#define GAMMA       (LCD_CONTROL_BLOCK_BASE|0x14)
-#define INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
-#define INTMSK      (LCD_CONTROL_BLOCK_BASE|0x1C)
-#define MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
-#define HDE_LEFT    (LCD_CONTROL_BLOCK_BASE|0x24)
-#define VDE_TOP     (LCD_CONTROL_BLOCK_BASE|0x28)
-#define PXL         (LCD_CONTROL_BLOCK_BASE|0x30)
-#define HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HSW         (LCD_CONTROL_BLOCK_BASE|0x38)
-#define HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define HDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x40)
-#define VCYCLE      (LCD_CONTROL_BLOCK_BASE|0x44)
-#define VSW         (LCD_CONTROL_BLOCK_BASE|0x48)
-#define VDE_START   (LCD_CONTROL_BLOCK_BASE|0x4C)
-#define VDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x50)
-#define WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
-#define WSYN_DLY    (LCD_CONTROL_BLOCK_BASE|0x58)
-#define REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
-#define VSYNIF      (LCD_CONTROL_BLOCK_BASE|0x60)
-#define WRSTB       (LCD_CONTROL_BLOCK_BASE|0x64)
-#define RDSTB       (LCD_CONTROL_BLOCK_BASE|0x68)
-#define ASY_DATA    (LCD_CONTROL_BLOCK_BASE|0x6C)
-#define ASY_DATB    (LCD_CONTROL_BLOCK_BASE|0x70)
-#define ASY_DATC    (LCD_CONTROL_BLOCK_BASE|0x74)
-#define ASY_DATD    (LCD_CONTROL_BLOCK_BASE|0x78)
-#define ASY_DATE    (LCD_CONTROL_BLOCK_BASE|0x7C)
-#define ASY_DATF    (LCD_CONTROL_BLOCK_BASE|0x80)
-#define ASY_DATG    (LCD_CONTROL_BLOCK_BASE|0x84)
-#define ASY_DATH    (LCD_CONTROL_BLOCK_BASE|0x88)
-#define ASY_CMDSET  (LCD_CONTROL_BLOCK_BASE|0x8C)
-#define SSICTL      (SPI_BLOCK_BASE|0x00)
-#define SSITIME     (SPI_BLOCK_BASE|0x04)
-#define SSITX       (SPI_BLOCK_BASE|0x08)
-#define SSIRX       (SPI_BLOCK_BASE|0x0C)
-#define SSIINTC     (SPI_BLOCK_BASE|0x10)
-#define SSIINTS     (SPI_BLOCK_BASE|0x14)
-#define SSIDBG1     (SPI_BLOCK_BASE|0x18)
-#define SSIDBG2     (SPI_BLOCK_BASE|0x1C)
-#define SSIID       (SPI_BLOCK_BASE|0x20)
-#define WKREQ       (SYSTEM_BLOCK1_BASE|0x00)
-#define CLKENB      (SYSTEM_BLOCK1_BASE|0x04)
-#define DRAMPWR     (SYSTEM_BLOCK1_BASE|0x08)
-#define INTMASK     (SYSTEM_BLOCK1_BASE|0x0C)
-#define GPIOSEL     (SYSTEM_BLOCK2_BASE|0x00)
-#define GPIODATA    (GPIO_BLOCK_BASE|0x00)
-#define GPIODIR     (GPIO_BLOCK_BASE|0x04)
-#define GPIOIS      (GPIO_BLOCK_BASE|0x08)
-#define GPIOIBE     (GPIO_BLOCK_BASE|0x0C)
-#define GPIOIEV     (GPIO_BLOCK_BASE|0x10)
-#define GPIOIE      (GPIO_BLOCK_BASE|0x14)
-#define GPIORIS     (GPIO_BLOCK_BASE|0x18)
-#define GPIOMIS     (GPIO_BLOCK_BASE|0x1C)
-#define GPIOIC      (GPIO_BLOCK_BASE|0x20)
-#define GPIOOMS     (GPIO_BLOCK_BASE|0x24)
-#define GPIOPC      (GPIO_BLOCK_BASE|0x28)
-#define GPIOID      (GPIO_BLOCK_BASE|0x30)
-#define SPI_WRITE(reg, val) \
-        { SSITX,        0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
-        { 0, 5 },
-#define SPI_WRITE1(reg) \
-        { SSITX,        (reg) & 0xff }, \
-        { 0, 5 },
-struct mddi_table {
-        uint32_t reg;
-        uint32_t value;
-};
-static struct mddi_table mddi_toshiba_init_table[] = {
-        { DPSET0,       0x09e90046 },
-        { DPSET1,       0x00000118 },
-        { DPSUS,        0x00000000 },
-        { DPRUN,        0x00000001 },
-        { 1,            14         }, /* msleep 14 */
-        { SYSCKENA,     0x00000001 },
-        { CLKENB,       0x0000A1EF },  /*    # SYS.CLKENB  # Enable clocks for each module (without DCLK , i2cCLK) */
-        { GPIODATA,     0x02000200 },  /*   # GPI .GPIODATA  # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
-        { GPIODIR,      0x000030D  },  /* 24D   # GPI .GPIODIR  # Select direction of GPIO port (0,2,3,6,9 output) */
-        { GPIOSEL,      0/*0x00000173*/},  /*   # SYS.GPIOSEL  # GPIO port multiplexing control */
-        { GPIOPC,       0x03C300C0 },  /*   # GPI .GPIOPC  # GPIO2,3 PD cut */
-        { WKREQ,        0x00000000 },  /*   # SYS.WKREQ  # Wake-up request event is VSYNC alignment */
-        { GPIOIBE,      0x000003FF },
-        { GPIOIS,       0x00000000 },
-        { GPIOIC,       0x000003FF },
-        { GPIOIE,       0x00000000 },
-        { GPIODATA,     0x00040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
-        { 1,            1          }, /* msleep 1 */
-        { GPIODATA,     0x02040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
-        { DRAMPWR,      0x00000001 }, /* eDRAM power */
-};
-#define GPIOSEL_VWAKEINT (1U << 0)
-#define INTMASK_VWAKEOUT (1U << 0)
-static int trout_new_backlight = 1;
-static struct vreg *vreg_mddi_1v5;
-static struct vreg *vreg_lcm_2v85;
-static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
-                                     struct mddi_table *table, size_t count)
-{
-        int i;
-        for (i = 0; i < count; i++) {
-                uint32_t reg = table[i].reg;
-                uint32_t value = table[i].value;
-                if (reg == 0)
-                        udelay(value);
-                else if (reg == 1)
-                        msleep(value);
-                else
-                        client_data->remote_write(client_data, value, reg);
-        }
-}
-static int trout_mddi_toshiba_client_init(
-        struct msm_mddi_bridge_platform_data *bridge_data,
-        struct msm_mddi_client_data *client_data)
-{
-        int panel_id;
-        client_data->auto_hibernate(client_data, 0);
-        trout_process_mddi_table(client_data, mddi_toshiba_init_table,
-                                 ARRAY_SIZE(mddi_toshiba_init_table));
-        client_data->auto_hibernate(client_data, 1);
-        panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
-        if (panel_id > 1) {
-                printk(KERN_WARNING "unknown panel id at mddi_enable\n");
-                return -1;
-        }
-        return 0;
-}
-static int trout_mddi_toshiba_client_uninit(
-        struct msm_mddi_bridge_platform_data *bridge_data,
-        struct msm_mddi_client_data *client_data)
-{
-        return 0;
-}
-static struct resource resources_msm_fb[] = {
-        {
-                .start = MSM_FB_BASE,
-                .end = MSM_FB_BASE + MSM_FB_SIZE,
-                .flags = IORESOURCE_MEM,
-        },
-};
-struct msm_mddi_bridge_platform_data toshiba_client_data = {
-        .init = trout_mddi_toshiba_client_init,
-        .uninit = trout_mddi_toshiba_client_uninit,
-        .fb_data = {
-                .xres = 320,
-                .yres = 480,
-                .width = 45,
-                .height = 67,
-                .output_format = 0,
-        },
-};
-static struct msm_mddi_platform_data mddi_pdata = {
-        .clk_rate = 122880000,
-        .fb_resource = resources_msm_fb,
-        .num_clients = 1,
-        .client_platform_data = {
-                {
-                        .product_id = (0xd263 << 16 | 0),
-                        .name = "mddi_c_d263_0000",
-                        .id = 0,
-                        .client_data = &toshiba_client_data,
-                        .clk_rate = 0,
-                },
-        },
-};
-int __init trout_init_panel(void)
-{
-        int rc;
-        if (!machine_is_trout())
-                return 0;
-        vreg_mddi_1v5 = vreg_get(0, "gp2");
-        if (IS_ERR(vreg_mddi_1v5))
-                return PTR_ERR(vreg_mddi_1v5);
-        vreg_lcm_2v85 = vreg_get(0, "gp4");
-        if (IS_ERR(vreg_lcm_2v85))
-                return PTR_ERR(vreg_lcm_2v85);
-        trout_new_backlight = system_rev >= 5;
-        if (trout_new_backlight) {
-                uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
-                                                GPIO_NO_PULL, GPIO_8MA);
-                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
-        } else {
-                uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
-                                                GPIO_NO_PULL, GPIO_8MA);
-                uint32_t id = P_GP_CLK;
-                uint32_t rate = 19200000;
-                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
-                msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
-                if (id < 0)
-                        pr_err("trout_init_panel: set clock rate failed\n");
-        }
-        rc = platform_device_register(&msm_device_mdp);
-        if (rc)
-                return rc;
-        msm_device_mddi0.dev.platform_data = &mddi_pdata;
-        return platform_device_register(&msm_device_mddi0);
-}
-device_initcall(trout_init_panel);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
deleted file mode 100644
index ba3edd3a46cb..000000000000
--- a/arch/arm/mach-msm/board-trout.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* linux/arch/arm/mach-msm/board-trout.c
- *
- * Copyright (C) 2009 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#define pr_fmt(fmt) "%s: " fmt, __func__
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clkdev.h>
-#include <linux/memblock.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <mach/hardware.h>
-#include <mach/msm_iomap.h>
-#include "devices.h"
-#include "board-trout.h"
-#include "common.h"
-extern int trout_init_mmc(unsigned int);
-static struct platform_device *devices[] __initdata = {
-        &msm_clock_7x01a,
-        &msm_device_gpio_7201,
-        &msm_device_uart3,
-        &msm_device_smd,
-        &msm_device_nand,
-        &msm_device_hsusb,
-        &msm_device_i2c,
-};
-static void __init trout_init_early(void)
-{
-        arch_ioremap_caller = __msm_ioremap_caller;
-}
-static void __init trout_init_irq(void)
-{
-        msm_init_irq();
-}
-static void __init trout_fixup(struct tag *tags, char **cmdline)
-{
-        memblock_add(PHYS_OFFSET, 101*SZ_1M);
-}
-static void __init trout_init(void)
-{
-        int rc;
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        if (IS_ENABLED(CONFIG_MMC)) {
-                rc = trout_init_mmc(system_rev);
-                if (rc)
-                        pr_crit("MMC init failure (%d)\n", rc);
-        }
-}
-static struct map_desc trout_io_desc[] __initdata = {
-        {
-                .virtual = (unsigned long)TROUT_CPLD_BASE,
-                .pfn     = __phys_to_pfn(TROUT_CPLD_START),
-                .length  = TROUT_CPLD_SIZE,
-                .type    = MT_DEVICE_NONSHARED
-        }
-};
-static void __init trout_map_io(void)
-{
-        msm_map_common_io();
-        iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
-#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
-        /* route UART3 to the "H2W" extended usb connector */
-        writeb(0x80, TROUT_CPLD_BASE + 0x00);
-#endif
-}
-static void __init trout_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(TROUT, "HTC Dream")
-        .atag_offset    = 0x100,
-        .fixup          = trout_fixup,
-        .map_io         = trout_map_io,
-        .init_early     = trout_init_early,
-        .init_irq       = trout_init_irq,
-        .init_machine   = trout_init,
-        .init_late      = trout_init_late,
-        .init_time      = msm7x01_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
deleted file mode 100644
index adb757abbb92..000000000000
--- a/arch/arm/mach-msm/board-trout.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* linux/arch/arm/mach-msm/board-trout.h
-** Author: Brian Swetland <swetland@google.com>
-*/
-#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
-#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
-#include "common.h"
-#define MSM_SMI_BASE            0x00000000
-#define MSM_SMI_SIZE            0x00800000
-#define MSM_EBI_BASE            0x10000000
-#define MSM_EBI_SIZE            0x06e00000
-#define MSM_PMEM_GPU0_BASE      0x00000000
-#define MSM_PMEM_GPU0_SIZE      0x00700000
-#define MSM_PMEM_MDP_BASE       0x02000000
-#define MSM_PMEM_MDP_SIZE       0x00800000
-#define MSM_PMEM_ADSP_BASE      0x02800000
-#define MSM_PMEM_ADSP_SIZE      0x00800000
-#define MSM_PMEM_CAMERA_BASE    0x03000000
-#define MSM_PMEM_CAMERA_SIZE    0x00800000
-#define MSM_FB_BASE             0x03800000
-#define MSM_FB_SIZE             0x00100000
-#define MSM_LINUX_BASE          MSM_EBI_BASE
-#define MSM_LINUX_SIZE          0x06500000
-#define MSM_PMEM_GPU1_SIZE      0x800000
-#define MSM_PMEM_GPU1_BASE      (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
-#define MSM_RAM_CONSOLE_BASE    (MSM_EBI_BASE + 0x6d00000)
-#define MSM_RAM_CONSOLE_SIZE    (128 * SZ_1K)
-#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
-#error invalid memory map
-#endif
-#define DECLARE_MSM_IOMAP
-#include <mach/msm_iomap.h>
-#define TROUT_4_BALL_UP_0     1
-#define TROUT_4_BALL_LEFT_0   18
-#define TROUT_4_BALL_DOWN_0   57
-#define TROUT_4_BALL_RIGHT_0  91
-#define TROUT_5_BALL_UP_0     94
-#define TROUT_5_BALL_LEFT_0   18
-#define TROUT_5_BALL_DOWN_0   90
-#define TROUT_5_BALL_RIGHT_0  19
-#define TROUT_POWER_KEY     20
-#define TROUT_4_TP_LS_EN    19
-#define TROUT_5_TP_LS_EN    1
-#define TROUT_CPLD_BASE   IOMEM(0xE8100000)
-#define TROUT_CPLD_START  0x98000000
-#define TROUT_CPLD_SIZE   SZ_4K
-#define TROUT_GPIO_CABLE_IN1            (83)
-#define TROUT_GPIO_CABLE_IN2            (49)
-#define TROUT_GPIO_START (128)
-#define TROUT_GPIO_INT_MASK0_REG            (0x0c)
-#define TROUT_GPIO_INT_STAT0_REG            (0x0e)
-#define TROUT_GPIO_INT_MASK1_REG            (0x14)
-#define TROUT_GPIO_INT_STAT1_REG            (0x10)
-#define TROUT_GPIO_HAPTIC_PWM               (28)
-#define TROUT_GPIO_PS_HOLD                  (25)
-#define TROUT_GPIO_MISC2_BASE               (TROUT_GPIO_START + 0x00)
-#define TROUT_GPIO_MISC3_BASE               (TROUT_GPIO_START + 0x08)
-#define TROUT_GPIO_MISC4_BASE               (TROUT_GPIO_START + 0x10)
-#define TROUT_GPIO_MISC5_BASE               (TROUT_GPIO_START + 0x18)
-#define TROUT_GPIO_INT2_BASE                (TROUT_GPIO_START + 0x20)
-#define TROUT_GPIO_MISC1_BASE               (TROUT_GPIO_START + 0x28)
-#define TROUT_GPIO_VIRTUAL_BASE             (TROUT_GPIO_START + 0x30)
-#define TROUT_GPIO_INT5_BASE                (TROUT_GPIO_START + 0x48)
-#define TROUT_GPIO_CHARGER_EN               (TROUT_GPIO_MISC2_BASE + 0)
-#define TROUT_GPIO_ISET                     (TROUT_GPIO_MISC2_BASE + 1)
-#define TROUT_GPIO_H2W_DAT_DIR              (TROUT_GPIO_MISC2_BASE + 2)
-#define TROUT_GPIO_H2W_CLK_DIR              (TROUT_GPIO_MISC2_BASE + 3)
-#define TROUT_GPIO_H2W_DAT_GPO              (TROUT_GPIO_MISC2_BASE + 4)
-#define TROUT_GPIO_H2W_CLK_GPO              (TROUT_GPIO_MISC2_BASE + 5)
-#define TROUT_GPIO_H2W_SEL0                 (TROUT_GPIO_MISC2_BASE + 6)
-#define TROUT_GPIO_H2W_SEL1                 (TROUT_GPIO_MISC2_BASE + 7)
-#define TROUT_GPIO_SPOTLIGHT_EN             (TROUT_GPIO_MISC3_BASE + 0)
-#define TROUT_GPIO_FLASH_EN                 (TROUT_GPIO_MISC3_BASE + 1)
-#define TROUT_GPIO_I2C_PULL                 (TROUT_GPIO_MISC3_BASE + 2)
-#define TROUT_GPIO_TP_I2C_PULL              (TROUT_GPIO_MISC3_BASE + 3)
-#define TROUT_GPIO_TP_EN                    (TROUT_GPIO_MISC3_BASE + 4)
-#define TROUT_GPIO_JOG_EN                   (TROUT_GPIO_MISC3_BASE + 5)
-#define TROUT_GPIO_UI_LED_EN                (TROUT_GPIO_MISC3_BASE + 6)
-#define TROUT_GPIO_QTKEY_LED_EN             (TROUT_GPIO_MISC3_BASE + 7)
-#define TROUT_GPIO_VCM_PWDN                 (TROUT_GPIO_MISC4_BASE + 0)
-#define TROUT_GPIO_USB_H2W_SW               (TROUT_GPIO_MISC4_BASE + 1)
-#define TROUT_GPIO_COMPASS_RST_N            (TROUT_GPIO_MISC4_BASE + 2)
-#define TROUT_GPIO_HAPTIC_EN_UP             (TROUT_GPIO_MISC4_BASE + 3)
-#define TROUT_GPIO_HAPTIC_EN_MAIN           (TROUT_GPIO_MISC4_BASE + 4)
-#define TROUT_GPIO_USB_PHY_RST_N            (TROUT_GPIO_MISC4_BASE + 5)
-#define TROUT_GPIO_WIFI_PA_RESETX           (TROUT_GPIO_MISC4_BASE + 6)
-#define TROUT_GPIO_WIFI_EN                  (TROUT_GPIO_MISC4_BASE + 7)
-#define TROUT_GPIO_BT_32K_EN                (TROUT_GPIO_MISC5_BASE + 0)
-#define TROUT_GPIO_MAC_32K_EN               (TROUT_GPIO_MISC5_BASE + 1)
-#define TROUT_GPIO_MDDI_32K_EN              (TROUT_GPIO_MISC5_BASE + 2)
-#define TROUT_GPIO_COMPASS_32K_EN           (TROUT_GPIO_MISC5_BASE + 3)
-#define TROUT_GPIO_NAVI_ACT_N               (TROUT_GPIO_INT2_BASE + 0)
-#define TROUT_GPIO_COMPASS_IRQ              (TROUT_GPIO_INT2_BASE + 1)
-#define TROUT_GPIO_SLIDING_DET              (TROUT_GPIO_INT2_BASE + 2)
-#define TROUT_GPIO_AUD_HSMIC_DET_N          (TROUT_GPIO_INT2_BASE + 3)
-#define TROUT_GPIO_SD_DOOR_N                (TROUT_GPIO_INT2_BASE + 4)
-#define TROUT_GPIO_CAM_BTN_STEP1_N          (TROUT_GPIO_INT2_BASE + 5)
-#define TROUT_GPIO_CAM_BTN_STEP2_N          (TROUT_GPIO_INT2_BASE + 6)
-#define TROUT_GPIO_TP_ATT_N                 (TROUT_GPIO_INT2_BASE + 7)
-#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE   (TROUT_GPIO_NAVI_ACT_N)
-#define TROUT_GPIO_BANK0_LAST_INT_SOURCE    (TROUT_GPIO_TP_ATT_N)
-#define TROUT_GPIO_H2W_DAT_GPI              (TROUT_GPIO_MISC1_BASE + 0)
-#define TROUT_GPIO_H2W_CLK_GPI              (TROUT_GPIO_MISC1_BASE + 1)
-#define TROUT_GPIO_CPLD128_VER_0            (TROUT_GPIO_MISC1_BASE + 4)
-#define TROUT_GPIO_CPLD128_VER_1            (TROUT_GPIO_MISC1_BASE + 5)
-#define TROUT_GPIO_CPLD128_VER_2            (TROUT_GPIO_MISC1_BASE + 6)
-#define TROUT_GPIO_CPLD128_VER_3            (TROUT_GPIO_MISC1_BASE + 7)
-#define TROUT_GPIO_SDMC_CD_N                (TROUT_GPIO_VIRTUAL_BASE + 0)
-#define TROUT_GPIO_END                      (TROUT_GPIO_SDMC_CD_N)
-#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE   (TROUT_GPIO_SDMC_CD_N)
-#define TROUT_GPIO_BANK1_LAST_INT_SOURCE    (TROUT_GPIO_SDMC_CD_N)
-#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
-        (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
-#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
-#define TROUT_INT_BANK0_COUNT (8)
-#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
-#define TROUT_INT_BANK1_COUNT (1)
-#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
-                        TROUT_INT_BANK1_COUNT - 1)
-#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
-        (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
-        (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
-#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
-#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
-#define TROUT_BANK_TO_MASK_REG(bank) \
-        (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
-#define TROUT_BANK_TO_STAT_REG(bank) \
-        (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
-#endif /* GUARD */
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
deleted file mode 100644
index f5b69d736ee5..000000000000
--- a/arch/arm/mach-msm/clock-pcom.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <mach/clk.h>
-#include "proc_comm.h"
-#include "clock.h"
-#include "clock-pcom.h"
-struct clk_pcom {
-        unsigned id;
-        unsigned long flags;
-        struct msm_clk msm_clk;
-};
-static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
-{
-        return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
-}
-static int pc_clk_enable(struct clk_hw *hw)
-{
-        unsigned id = to_clk_pcom(hw)->id;
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-static void pc_clk_disable(struct clk_hw *hw)
-{
-        unsigned id = to_clk_pcom(hw)->id;
-        msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
-}
-static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
-{
-        int rc;
-        unsigned id = to_clk_pcom(hw)->id;
-        if (action == CLK_RESET_ASSERT)
-                rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
-        else
-                rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_DEASSERT, &id, NULL);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
-                           unsigned long p_rate)
-{
-        struct clk_pcom *p = to_clk_pcom(hw);
-        unsigned id = p->id, rate = new_rate;
-        int rc;
-        /*
-         * The rate _might_ be rounded off to the nearest KHz value by the
-         * remote function. So a return value of 0 doesn't necessarily mean
-         * that the exact rate was set successfully.
-         */
-        if (p->flags & CLKFLAG_MIN)
-                rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
-        else
-                rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
-{
-        unsigned id = to_clk_pcom(hw)->id;
-        if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
-                return 0;
-        else
-                return id;
-}
-static int pc_clk_is_enabled(struct clk_hw *hw)
-{
-        unsigned id = to_clk_pcom(hw)->id;
-        if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
-                return 0;
-        else
-                return id;
-}
-static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                              unsigned long *p_rate)
-{
-        /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
-        return rate;
-}
-static struct clk_ops clk_ops_pcom = {
-        .enable = pc_clk_enable,
-        .disable = pc_clk_disable,
-        .set_rate = pc_clk_set_rate,
-        .recalc_rate = pc_clk_recalc_rate,
-        .is_enabled = pc_clk_is_enabled,
-        .round_rate = pc_clk_round_rate,
-};
-static int msm_clock_pcom_probe(struct platform_device *pdev)
-{
-        const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
-        int i, ret;
-        for (i = 0; i < pdata->num_lookups; i++) {
-                const struct clk_pcom_desc *desc = &pdata->lookup[i];
-                struct clk *c;
-                struct clk_pcom *p;
-                struct clk_hw *hw;
-                struct clk_init_data init;
-                p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
-                if (!p)
-                        return -ENOMEM;
-                p->id = desc->id;
-                p->flags = desc->flags;
-                p->msm_clk.reset = pc_clk_reset;
-                hw = &p->msm_clk.hw;
-                hw->init = &init;
-                init.name = desc->name;
-                init.ops = &clk_ops_pcom;
-                init.num_parents = 0;
-                init.flags = CLK_IS_ROOT;
-                if (!(p->flags & CLKFLAG_AUTO_OFF))
-                        init.flags |= CLK_IGNORE_UNUSED;
-                c = devm_clk_register(&pdev->dev, hw);
-                ret = clk_register_clkdev(c, desc->con, desc->dev);
-                if (ret)
-                        return ret;
-        }
-        return 0;
-}
-static struct platform_driver msm_clock_pcom_driver = {
-        .probe          = msm_clock_pcom_probe,
-        .driver         = {
-                .name   = "msm-clock-pcom",
-        },
-};
-module_platform_driver(msm_clock_pcom_driver);
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
deleted file mode 100644
index 5bb164fd46a8..000000000000
--- a/arch/arm/mach-msm/clock-pcom.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
-/* clock IDs used by the modem processor */
-#define P_ACPU_CLK      0   /* Applications processor clock */
-#define P_ADM_CLK       1   /* Applications data mover clock */
-#define P_ADSP_CLK      2   /* ADSP clock */
-#define P_EBI1_CLK      3   /* External bus interface 1 clock */
-#define P_EBI2_CLK      4   /* External bus interface 2 clock */
-#define P_ECODEC_CLK    5   /* External CODEC clock */
-#define P_EMDH_CLK      6   /* External MDDI host clock */
-#define P_GP_CLK        7   /* General purpose clock */
-#define P_GRP_3D_CLK    8   /* Graphics clock */
-#define P_I2C_CLK       9   /* I2C clock */
-#define P_ICODEC_RX_CLK 10  /* Internal CODEX RX clock */
-#define P_ICODEC_TX_CLK 11  /* Internal CODEX TX clock */
-#define P_IMEM_CLK      12  /* Internal graphics memory clock */
-#define P_MDC_CLK       13  /* MDDI client clock */
-#define P_MDP_CLK       14  /* Mobile display processor clock */
-#define P_PBUS_CLK      15  /* Peripheral bus clock */
-#define P_PCM_CLK       16  /* PCM clock */
-#define P_PMDH_CLK      17  /* Primary MDDI host clock */
-#define P_SDAC_CLK      18  /* Stereo DAC clock */
-#define P_SDC1_CLK      19  /* Secure Digital Card clocks */
-#define P_SDC1_P_CLK    20
-#define P_SDC2_CLK      21
-#define P_SDC2_P_CLK    22
-#define P_SDC3_CLK      23
-#define P_SDC3_P_CLK    24
-#define P_SDC4_CLK      25
-#define P_SDC4_P_CLK    26
-#define P_TSIF_CLK      27  /* Transport Stream Interface clocks */
-#define P_TSIF_REF_CLK  28
-#define P_TV_DAC_CLK    29  /* TV clocks */
-#define P_TV_ENC_CLK    30
-#define P_UART1_CLK     31  /* UART clocks */
-#define P_UART2_CLK     32
-#define P_UART3_CLK     33
-#define P_UART1DM_CLK   34
-#define P_UART2DM_CLK   35
-#define P_USB_HS_CLK    36  /* High speed USB core clock */
-#define P_USB_HS_P_CLK  37  /* High speed USB pbus clock */
-#define P_USB_OTG_CLK   38  /* Full speed USB clock */
-#define P_VDC_CLK       39  /* Video controller clock */
-#define P_VFE_MDC_CLK   40  /* Camera / Video Front End clock */
-#define P_VFE_CLK       41  /* VFE MDDI client clock */
-#define P_MDP_LCDC_PCLK_CLK     42
-#define P_MDP_LCDC_PAD_PCLK_CLK 43
-#define P_MDP_VSYNC_CLK 44
-#define P_SPI_CLK       45
-#define P_VFE_AXI_CLK   46
-#define P_USB_HS2_CLK   47  /* High speed USB 2 core clock */
-#define P_USB_HS2_P_CLK 48  /* High speed USB 2 pbus clock */
-#define P_USB_HS3_CLK   49  /* High speed USB 3 core clock */
-#define P_USB_HS3_P_CLK 50  /* High speed USB 3 pbus clock */
-#define P_GRP_3D_P_CLK  51  /* Graphics pbus clock */
-#define P_USB_PHY_CLK   52  /* USB PHY clock */
-#define P_USB_HS_CORE_CLK       53  /* High speed USB 1 core clock */
-#define P_USB_HS2_CORE_CLK      54  /* High speed USB 2 core clock */
-#define P_USB_HS3_CORE_CLK      55  /* High speed USB 3 core clock */
-#define P_CAM_M_CLK             56
-#define P_CAMIF_PAD_P_CLK       57
-#define P_GRP_2D_CLK            58
-#define P_GRP_2D_P_CLK          59
-#define P_I2S_CLK               60
-#define P_JPEG_CLK              61
-#define P_JPEG_P_CLK            62
-#define P_LPA_CODEC_CLK         63
-#define P_LPA_CORE_CLK          64
-#define P_LPA_P_CLK             65
-#define P_MDC_IO_CLK            66
-#define P_MDC_P_CLK             67
-#define P_MFC_CLK               68
-#define P_MFC_DIV2_CLK          69
-#define P_MFC_P_CLK             70
-#define P_QUP_I2C_CLK           71
-#define P_ROTATOR_IMEM_CLK      72
-#define P_ROTATOR_P_CLK         73
-#define P_VFE_CAMIF_CLK         74
-#define P_VFE_P_CLK             75
-#define P_VPE_CLK               76
-#define P_I2C_2_CLK             77
-#define P_MI2S_CODEC_RX_S_CLK   78
-#define P_MI2S_CODEC_RX_M_CLK   79
-#define P_MI2S_CODEC_TX_S_CLK   80
-#define P_MI2S_CODEC_TX_M_CLK   81
-#define P_PMDH_P_CLK            82
-#define P_EMDH_P_CLK            83
-#define P_SPI_P_CLK             84
-#define P_TSIF_P_CLK            85
-#define P_MDP_P_CLK             86
-#define P_SDAC_M_CLK            87
-#define P_MI2S_S_CLK            88
-#define P_MI2S_M_CLK            89
-#define P_AXI_ROTATOR_CLK       90
-#define P_HDMI_CLK              91
-#define P_CSI0_CLK              92
-#define P_CSI0_VFE_CLK          93
-#define P_CSI0_P_CLK            94
-#define P_CSI1_CLK              95
-#define P_CSI1_VFE_CLK          96
-#define P_CSI1_P_CLK            97
-#define P_GSBI_CLK              98
-#define P_GSBI_P_CLK            99
-#define P_CE_CLK                100 /* Crypto engine */
-#define P_CODEC_SSBI_CLK        101
-#define P_NR_CLKS               102
-struct clk_pcom_desc {
-        unsigned id;
-        const char *name;
-        const char *con;
-        const char *dev;
-        unsigned long flags;
-};
-struct pcom_clk_pdata {
-        struct clk_pcom_desc *lookup;
-        u32 num_lookups;
-};
-#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .id = P_##clk_id,                                       \
-        .name = #clk_id,                                        \
-        .con = clk_name,                                        \
-        .dev = clk_dev,                                         \
-        .flags = clk_flags,                                     \
-        }
-#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
deleted file mode 100644
index 35ea02b52483..000000000000
--- a/arch/arm/mach-msm/clock.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* arch/arm/mach-msm/clock.c
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk-provider.h>
-#include <linux/module.h>
-#include "clock.h"
-int clk_reset(struct clk *clk, enum clk_reset_action action)
-{
-        struct clk_hw *hw = __clk_get_hw(clk);
-        struct msm_clk *m = to_msm_clk(hw);
-        return m->reset(hw, action);
-}
-EXPORT_SYMBOL(clk_reset);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
deleted file mode 100644
index 42d29dd7aafc..000000000000
--- a/arch/arm/mach-msm/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* arch/arm/mach-msm/clock.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_H
-#include <linux/clk-provider.h>
-#include <mach/clk.h>
-#define CLK_FIRST_AVAILABLE_FLAG        0x00000100
-#define CLKFLAG_AUTO_OFF                0x00000200
-#define CLKFLAG_MIN                     0x00000400
-#define CLKFLAG_MAX                     0x00000800
-#define OFF CLKFLAG_AUTO_OFF
-#define CLK_MIN CLKFLAG_MIN
-#define CLK_MAX CLKFLAG_MAX
-#define CLK_MINMAX (CLK_MIN | CLK_MAX)
-struct msm_clk {
-        int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
-        struct clk_hw hw;
-};
-static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
-{
-        return container_of(hw, struct msm_clk, hw);
-}
-#endif
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
deleted file mode 100644
index 572479a3c7be..000000000000
--- a/arch/arm/mach-msm/common.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_COMMON_H
-#define __MACH_COMMON_H
-extern void msm7x01_timer_init(void);
-extern void msm7x30_timer_init(void);
-extern void qsd8x50_timer_init(void);
-extern void msm_map_common_io(void);
-extern void msm_map_msm7x30_io(void);
-extern void msm_map_qsd8x50_io(void);
-extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
-                                          unsigned int mtype, void *caller);
-struct msm_mmc_platform_data;
-extern void msm_add_devices(void);
-extern void msm_init_irq(void);
-extern void msm_init_gpio(void);
-extern int msm_add_sdcc(unsigned int controller,
-                        struct msm_mmc_platform_data *plat,
-                        unsigned int stat_irq, unsigned long stat_irq_flags);
-#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
-extern int smd_debugfs_init(void);
-#else
-static inline int smd_debugfs_init(void) { return 0; }
-#endif
-#endif
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
deleted file mode 100644
index d83404d4b328..000000000000
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* linux/arch/arm/mach-msm/devices.c
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/clkdev.h>
-#include <mach/irqs.h>
-#include <mach/msm_iomap.h>
-#include "devices.h"
-#include <asm/mach/flash.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include "clock.h"
-#include "clock-pcom.h"
-#include <linux/platform_data/mmc-msm_sdcc.h>
-static struct resource msm_gpio_resources[] = {
-        {
-                .start  = 32 + 0,
-                .end    = 32 + 0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 32 + 1,
-                .end    = 32 + 1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 0xa9200800,
-                .end    = 0xa9200800 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio1"
-        },
-        {
-                .start  = 0xa9300C00,
-                .end    = 0xa9300C00 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio2"
-        },
-};
-struct platform_device msm_device_gpio_7201 = {
-        .name   = "gpio-msm-7201",
-        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
-        .resource       = msm_gpio_resources,
-};
-static struct resource resources_uart1[] = {
-        {
-                .start  = INT_UART1,
-                .end    = INT_UART1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART1_PHYS,
-                .end    = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "uart_resource"
-        },
-};
-static struct resource resources_uart2[] = {
-        {
-                .start  = INT_UART2,
-                .end    = INT_UART2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART2_PHYS,
-                .end    = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "uart_resource"
-        },
-};
-static struct resource resources_uart3[] = {
-        {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART3_PHYS,
-                .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "uart_resource"
-        },
-};
-struct platform_device msm_device_uart1 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart1),
-        .resource       = resources_uart1,
-};
-struct platform_device msm_device_uart2 = {
-        .name   = "msm_serial",
-        .id     = 1,
-        .num_resources  = ARRAY_SIZE(resources_uart2),
-        .resource       = resources_uart2,
-};
-struct platform_device msm_device_uart3 = {
-        .name   = "msm_serial",
-        .id     = 2,
-        .num_resources  = ARRAY_SIZE(resources_uart3),
-        .resource       = resources_uart3,
-};
-static struct resource resources_i2c[] = {
-        {
-                .start  = MSM_I2C_PHYS,
-                .end    = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_PWB_I2C,
-                .end    = INT_PWB_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_i2c = {
-        .name           = "msm_i2c",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(resources_i2c),
-        .resource       = resources_i2c,
-};
-static struct resource resources_hsusb[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_hsusb = {
-        .name           = "msm_hsusb",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_hsusb),
-        .resource       = resources_hsusb,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct flash_platform_data msm_nand_data = {
-        .parts          = NULL,
-        .nr_parts       = 0,
-};
-static struct resource resources_nand[] = {
-        [0] = {
-                .start  = 7,
-                .end    = 7,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-struct platform_device msm_device_nand = {
-        .name           = "msm_nand",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_nand),
-        .resource       = resources_nand,
-        .dev            = {
-                .platform_data  = &msm_nand_data,
-        },
-};
-struct platform_device msm_device_smd = {
-        .name   = "msm_smd",
-        .id     = -1,
-};
-static struct resource resources_sdc1[] = {
-        {
-                .start  = MSM_SDC1_PHYS,
-                .end    = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC1_0,
-                .end    = INT_SDC1_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc2[] = {
-        {
-                .start  = MSM_SDC2_PHYS,
-                .end    = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC2_0,
-                .end    = INT_SDC2_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc3[] = {
-        {
-                .start  = MSM_SDC3_PHYS,
-                .end    = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC3_0,
-                .end    = INT_SDC3_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc4[] = {
-        {
-                .start  = MSM_SDC4_PHYS,
-                .end    = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC4_0,
-                .end    = INT_SDC4_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-struct platform_device msm_device_sdc1 = {
-        .name           = "msm_sdcc",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(resources_sdc1),
-        .resource       = resources_sdc1,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc2 = {
-        .name           = "msm_sdcc",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(resources_sdc2),
-        .resource       = resources_sdc2,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc3 = {
-        .name           = "msm_sdcc",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(resources_sdc3),
-        .resource       = resources_sdc3,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc4 = {
-        .name           = "msm_sdcc",
-        .id             = 4,
-        .num_resources  = ARRAY_SIZE(resources_sdc4),
-        .resource       = resources_sdc4,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct platform_device *msm_sdcc_devices[] __initdata = {
-        &msm_device_sdc1,
-        &msm_device_sdc2,
-        &msm_device_sdc3,
-        &msm_device_sdc4,
-};
-int __init msm_add_sdcc(unsigned int controller,
-                        struct msm_mmc_platform_data *plat,
-                        unsigned int stat_irq, unsigned long stat_irq_flags)
-{
-        struct platform_device  *pdev;
-        struct resource *res;
-        if (controller < 1 || controller > 4)
-                return -EINVAL;
-        pdev = msm_sdcc_devices[controller-1];
-        pdev->dev.platform_data = plat;
-        res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
-        if (!res)
-                return -EINVAL;
-        else if (stat_irq) {
-                res->start = res->end = stat_irq;
-                res->flags &= ~IORESOURCE_DISABLED;
-                res->flags |= stat_irq_flags;
-        }
-        return platform_device_register(pdev);
-}
-static struct resource resources_mddi0[] = {
-        {
-                .start  = MSM_PMDH_PHYS,
-                .end    = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_MDDI_PRI,
-                .end    = INT_MDDI_PRI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource resources_mddi1[] = {
-        {
-                .start  = MSM_EMDH_PHYS,
-                .end    = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_MDDI_EXT,
-                .end    = INT_MDDI_EXT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_mddi0 = {
-        .name = "msm_mddi",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(resources_mddi0),
-        .resource = resources_mddi0,
-        .dev = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_mddi1 = {
-        .name = "msm_mddi",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(resources_mddi1),
-        .resource = resources_mddi1,
-        .dev = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct resource resources_mdp[] = {
-        {
-                .start  = MSM_MDP_PHYS,
-                .end    = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
-                .name   = "mdp",
-                .flags  = IORESOURCE_MEM
-        },
-        {
-                .start  = INT_MDP,
-                .end    = INT_MDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_mdp = {
-        .name = "msm_mdp",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(resources_mdp),
-        .resource = resources_mdp,
-};
-static struct clk_pcom_desc msm_clocks_7x01a[] = {
-        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
-        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
-        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, 0),
-        CLK_PCOM("ebi2_clk",    EBI2_CLK,       NULL, 0),
-        CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
-        CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF),
-        CLK_PCOM("gp_clk",              GP_CLK,         NULL, 0),
-        CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, OFF),
-        CLK_PCOM("i2c_clk",     I2C_CLK,        "msm_i2c.0", 0),
-        CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
-        CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
-        CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
-        CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
-        CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
-        CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, 0),
-        CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
-        CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
-        CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
-        CLK_PCOM("sdc_clk",     SDC1_CLK,       "msm_sdcc.1", OFF),
-        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     "msm_sdcc.1", OFF),
-        CLK_PCOM("sdc_clk",     SDC2_CLK,       "msm_sdcc.2", OFF),
-        CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     "msm_sdcc.2", OFF),
-        CLK_PCOM("sdc_clk",     SDC3_CLK,       "msm_sdcc.3", OFF),
-        CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     "msm_sdcc.3", OFF),
-        CLK_PCOM("sdc_clk",     SDC4_CLK,       "msm_sdcc.4", OFF),
-        CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     "msm_sdcc.4", OFF),
-        CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
-        CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
-        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
-        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("core",        UART1_CLK,      "msm_serial.0", OFF),
-        CLK_PCOM("core",        UART2_CLK,      "msm_serial.1", 0),
-        CLK_PCOM("core",        UART3_CLK,      "msm_serial.2", OFF),
-        CLK_PCOM("uart1dm_clk", UART1DM_CLK,    NULL, OFF),
-        CLK_PCOM("uart2dm_clk", UART2DM_CLK,    NULL, 0),
-        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     "msm_hsusb", OFF),
-        CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   "msm_hsusb", OFF),
-        CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
-        CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF ),
-        CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, OFF),
-        CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
-};
-static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
-        .lookup = msm_clocks_7x01a,
-        .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
-};
-struct platform_device msm_clock_7x01a = {
-        .name = "msm-clock-pcom",
-        .dev.platform_data = &msm_clock_7x01a_pdata,
-};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
deleted file mode 100644
index c15ea8ab20a7..000000000000
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/clkdev.h>
-#include <mach/irqs.h>
-#include <mach/msm_iomap.h>
-#include <mach/dma.h>
-#include "devices.h"
-#include "smd_private.h"
-#include "common.h"
-#include <asm/mach/flash.h>
-#include "clock.h"
-#include "clock-pcom.h"
-#include <linux/platform_data/mmc-msm_sdcc.h>
-static struct resource msm_gpio_resources[] = {
-        {
-                .start  = 32 + 18,
-                .end    = 32 + 18,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 32 + 19,
-                .end    = 32 + 19,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 0xac001000,
-                .end    = 0xac001000 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio1"
-        },
-        {
-                .start  = 0xac101400,
-                .end    = 0xac101400 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio2"
-        },
-};
-struct platform_device msm_device_gpio_7x30 = {
-        .name   = "gpio-msm-7x30",
-        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
-        .resource       = msm_gpio_resources,
-};
-static struct resource resources_uart2[] = {
-        {
-                .start  = INT_UART2,
-                .end    = INT_UART2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART2_PHYS,
-                .end    = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "uart_resource"
-        },
-};
-struct platform_device msm_device_uart2 = {
-        .name   = "msm_serial",
-        .id     = 1,
-        .num_resources  = ARRAY_SIZE(resources_uart2),
-        .resource       = resources_uart2,
-};
-struct platform_device msm_device_smd = {
-        .name   = "msm_smd",
-        .id     = -1,
-};
-static struct resource resources_otg[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_otg = {
-        .name           = "msm_otg",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_otg),
-        .resource       = resources_otg,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct resource resources_hsusb[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_hsusb = {
-        .name           = "msm_hsusb",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_hsusb),
-        .resource       = resources_hsusb,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static u64 dma_mask = 0xffffffffULL;
-static struct resource resources_hsusb_host[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_hsusb_host = {
-        .name           = "msm_hsusb_host",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
-        .resource       = resources_hsusb_host,
-        .dev            = {
-                .dma_mask               = &dma_mask,
-                .coherent_dma_mask      = 0xffffffffULL,
-        },
-};
-static struct clk_pcom_desc msm_clocks_7x30[] = {
-        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
-        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
-        CLK_PCOM("cam_m_clk",   CAM_M_CLK,      NULL, 0),
-        CLK_PCOM("camif_pad_pclk",      CAMIF_PAD_P_CLK,        NULL, OFF),
-        CLK_PCOM("ce_clk",      CE_CLK, NULL, 0),
-        CLK_PCOM("codec_ssbi_clk",      CODEC_SSBI_CLK, NULL, 0),
-        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
-        CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
-        CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
-        CLK_PCOM("emdh_pclk",   EMDH_P_CLK,     NULL, OFF),
-        CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
-        CLK_PCOM("grp_2d_clk",  GRP_2D_CLK,     NULL, 0),
-        CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK,   NULL, 0),
-        CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
-        CLK_PCOM("grp_pclk",    GRP_3D_P_CLK,   NULL, 0),
-        CLK_PCOM("hdmi_clk",    HDMI_CLK,       NULL, 0),
-        CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
-        CLK_PCOM("jpeg_clk",    JPEG_CLK,       NULL, OFF),
-        CLK_PCOM("jpeg_pclk",   JPEG_P_CLK,     NULL, OFF),
-        CLK_PCOM("lpa_codec_clk",       LPA_CODEC_CLK,          NULL, 0),
-        CLK_PCOM("lpa_core_clk",        LPA_CORE_CLK,           NULL, 0),
-        CLK_PCOM("lpa_pclk",            LPA_P_CLK,              NULL, 0),
-        CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
-        CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
-        CLK_PCOM("mddi_pclk",   PMDH_P_CLK,     NULL, 0),
-        CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
-        CLK_PCOM("mdp_pclk",    MDP_P_CLK,      NULL, 0),
-        CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
-        CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
-        CLK_PCOM("mdp_vsync_clk",       MDP_VSYNC_CLK,  NULL, 0),
-        CLK_PCOM("mfc_clk",             MFC_CLK,                NULL, 0),
-        CLK_PCOM("mfc_div2_clk",        MFC_DIV2_CLK,           NULL, 0),
-        CLK_PCOM("mfc_pclk",            MFC_P_CLK,              NULL, 0),
-        CLK_PCOM("mi2s_m_clk",          MI2S_M_CLK,             NULL, 0),
-        CLK_PCOM("mi2s_s_clk",          MI2S_S_CLK,             NULL, 0),
-        CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK,  NULL, 0),
-        CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK,  NULL, 0),
-        CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK,  NULL, 0),
-        CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK,  NULL, 0),
-        CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
-        CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
-        CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK,                NULL, 0),
-        CLK_PCOM("rotator_imem_clk",    ROTATOR_IMEM_CLK,       NULL, OFF),
-        CLK_PCOM("rotator_pclk",        ROTATOR_P_CLK,          NULL, OFF),
-        CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
-        CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
-        CLK_PCOM("spi_pclk",    SPI_P_CLK,      NULL, 0),
-        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
-        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("core",        UART2_CLK,      "msm_serial.1", 0),
-        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
-        CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
-        CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
-        CLK_PCOM("usb_hs_core_clk",     USB_HS_CORE_CLK,        NULL, OFF),
-        CLK_PCOM("usb_hs2_clk",         USB_HS2_CLK,            NULL, OFF),
-        CLK_PCOM("usb_hs2_pclk",        USB_HS2_P_CLK,          NULL, OFF),
-        CLK_PCOM("usb_hs2_core_clk",    USB_HS2_CORE_CLK,       NULL, OFF),
-        CLK_PCOM("usb_hs3_clk",         USB_HS3_CLK,            NULL, OFF),
-        CLK_PCOM("usb_hs3_pclk",        USB_HS3_P_CLK,          NULL, OFF),
-        CLK_PCOM("usb_hs3_core_clk",    USB_HS3_CORE_CLK,       NULL, OFF),
-        CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF | CLK_MIN),
-        CLK_PCOM("vfe_camif_clk",       VFE_CAMIF_CLK,  NULL, 0),
-        CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, 0),
-        CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, 0),
-        CLK_PCOM("vfe_pclk",    VFE_P_CLK,      NULL, OFF),
-        CLK_PCOM("vpe_clk",     VPE_CLK,        NULL, 0),
-        /* 7x30 v2 hardware only. */
-        CLK_PCOM("csi_clk",     CSI0_CLK,       NULL, 0),
-        CLK_PCOM("csi_pclk",    CSI0_P_CLK,     NULL, 0),
-        CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK,   NULL, 0),
-};
-static struct pcom_clk_pdata msm_clock_7x30_pdata = {
-        .lookup = msm_clocks_7x30,
-        .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
-};
-struct platform_device msm_clock_7x30 = {
-        .name = "msm-clock-pcom",
-        .dev.platform_data = &msm_clock_7x30_pdata,
-};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
deleted file mode 100644
index 9e1e9ce07b1a..000000000000
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <mach/irqs.h>
-#include <mach/msm_iomap.h>
-#include <mach/dma.h>
-#include "devices.h"
-#include "common.h"
-#include <asm/mach/flash.h>
-#include <linux/platform_data/mmc-msm_sdcc.h>
-#include "clock.h"
-#include "clock-pcom.h"
-static struct resource msm_gpio_resources[] = {
-        {
-                .start  = 64 + 165 + 9,
-                .end    = 64 + 165 + 9,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 64 + 165 + 10,
-                .end    = 64 + 165 + 10,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = 0xa9000800,
-                .end    = 0xa9000800 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio1"
-        },
-        {
-                .start  = 0xa9100C00,
-                .end    = 0xa9100C00 + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "gpio2"
-        },
-};
-struct platform_device msm_device_gpio_8x50 = {
-        .name   = "gpio-msm-8x50",
-        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
-        .resource       = msm_gpio_resources,
-};
-static struct resource resources_uart3[] = {
-        {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART3_PHYS,
-                .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-                .name  = "uart_resource"
-        },
-};
-struct platform_device msm_device_uart3 = {
-        .name   = "msm_serial",
-        .id     = 2,
-        .num_resources  = ARRAY_SIZE(resources_uart3),
-        .resource       = resources_uart3,
-};
-struct platform_device msm_device_smd = {
-        .name   = "msm_smd",
-        .id     = -1,
-};
-static struct resource resources_otg[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_otg = {
-        .name           = "msm_otg",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_otg),
-        .resource       = resources_otg,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct resource resources_hsusb[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_hsusb = {
-        .name           = "msm_hsusb",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_hsusb),
-        .resource       = resources_hsusb,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static u64 dma_mask = 0xffffffffULL;
-static struct resource resources_hsusb_host[] = {
-        {
-                .start  = MSM_HSUSB_PHYS,
-                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_HS,
-                .end    = INT_USB_HS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device msm_device_hsusb_host = {
-        .name           = "msm_hsusb_host",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
-        .resource       = resources_hsusb_host,
-        .dev            = {
-                .dma_mask               = &dma_mask,
-                .coherent_dma_mask      = 0xffffffffULL,
-        },
-};
-static struct resource resources_sdc1[] = {
-        {
-                .start  = MSM_SDC1_PHYS,
-                .end    = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC1_0,
-                .end    = INT_SDC1_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc2[] = {
-        {
-                .start  = MSM_SDC2_PHYS,
-                .end    = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC2_0,
-                .end    = INT_SDC2_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc3[] = {
-        {
-                .start  = MSM_SDC3_PHYS,
-                .end    = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC3_0,
-                .end    = INT_SDC3_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-static struct resource resources_sdc4[] = {
-        {
-                .start  = MSM_SDC4_PHYS,
-                .end    = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_SDC4_0,
-                .end    = INT_SDC4_0,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "cmd_irq",
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
-                .name   = "status_irq"
-        },
-        {
-                .start  = 8,
-                .end    = 8,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-struct platform_device msm_device_sdc1 = {
-        .name           = "msm_sdcc",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(resources_sdc1),
-        .resource       = resources_sdc1,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc2 = {
-        .name           = "msm_sdcc",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(resources_sdc2),
-        .resource       = resources_sdc2,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc3 = {
-        .name           = "msm_sdcc",
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(resources_sdc3),
-        .resource       = resources_sdc3,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device msm_device_sdc4 = {
-        .name           = "msm_sdcc",
-        .id             = 4,
-        .num_resources  = ARRAY_SIZE(resources_sdc4),
-        .resource       = resources_sdc4,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct platform_device *msm_sdcc_devices[] __initdata = {
-        &msm_device_sdc1,
-        &msm_device_sdc2,
-        &msm_device_sdc3,
-        &msm_device_sdc4,
-};
-int __init msm_add_sdcc(unsigned int controller,
-                        struct msm_mmc_platform_data *plat,
-                        unsigned int stat_irq, unsigned long stat_irq_flags)
-{
-        struct platform_device  *pdev;
-        struct resource *res;
-        if (controller < 1 || controller > 4)
-                return -EINVAL;
-        pdev = msm_sdcc_devices[controller-1];
-        pdev->dev.platform_data = plat;
-        res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
-        if (!res)
-                return -EINVAL;
-        else if (stat_irq) {
-                res->start = res->end = stat_irq;
-                res->flags &= ~IORESOURCE_DISABLED;
-                res->flags |= stat_irq_flags;
-        }
-        return platform_device_register(pdev);
-}
-static struct clk_pcom_desc msm_clocks_8x50[] = {
-        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
-        CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
-        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
-        CLK_PCOM("ebi2_clk",    EBI2_CLK,       NULL, 0),
-        CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
-        CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
-        CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
-        CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
-        CLK_PCOM("i2c_clk",     I2C_CLK,        NULL, 0),
-        CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
-        CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
-        CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
-        CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
-        CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
-        CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
-        CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
-        CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
-        CLK_PCOM("mdp_vsync_clk",       MDP_VSYNC_CLK,  NULL, 0),
-        CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
-        CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
-        CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
-        CLK_PCOM("sdc_clk",     SDC1_CLK,       "msm_sdcc.1", OFF),
-        CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     "msm_sdcc.1", OFF),
-        CLK_PCOM("sdc_clk",     SDC2_CLK,       "msm_sdcc.2", OFF),
-        CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     "msm_sdcc.2", OFF),
-        CLK_PCOM("sdc_clk",     SDC3_CLK,       "msm_sdcc.3", OFF),
-        CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     "msm_sdcc.3", OFF),
-        CLK_PCOM("sdc_clk",     SDC4_CLK,       "msm_sdcc.4", OFF),
-        CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     "msm_sdcc.4", OFF),
-        CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
-        CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
-        CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
-        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
-        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-        CLK_PCOM("core",        UART1_CLK,      NULL, OFF),
-        CLK_PCOM("core",        UART2_CLK,      NULL, 0),
-        CLK_PCOM("core",        UART3_CLK,      "msm_serial.2", OFF),
-        CLK_PCOM("uartdm_clk",  UART1DM_CLK,    NULL, OFF),
-        CLK_PCOM("uartdm_clk",  UART2DM_CLK,    NULL, 0),
-        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     NULL, OFF),
-        CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   NULL, OFF),
-        CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
-        CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF | CLK_MIN),
-        CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, OFF),
-        CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
-        CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK,    NULL, OFF),
-        CLK_PCOM("usb_hs2_clk", USB_HS2_CLK,    NULL, OFF),
-        CLK_PCOM("usb_hs2_pclk",        USB_HS2_P_CLK,  NULL, OFF),
-        CLK_PCOM("usb_hs3_clk", USB_HS3_CLK,    NULL, OFF),
-        CLK_PCOM("usb_hs3_pclk",        USB_HS3_P_CLK,  NULL, OFF),
-        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
-};
-static struct pcom_clk_pdata msm_clock_8x50_pdata = {
-        .lookup = msm_clocks_8x50,
-        .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
-};
-struct platform_device msm_clock_8x50 = {
-        .name = "msm-clock-pcom",
-        .dev.platform_data = &msm_clock_8x50_pdata,
-};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
deleted file mode 100644
index dccefad9f9b9..000000000000
--- a/arch/arm/mach-msm/devices.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* linux/arch/arm/mach-msm/devices.h
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
-#define __ARCH_ARM_MACH_MSM_DEVICES_H
-extern struct platform_device msm_device_gpio_7201;
-extern struct platform_device msm_device_gpio_7x30;
-extern struct platform_device msm_device_gpio_8x50;
-extern struct platform_device msm_device_uart1;
-extern struct platform_device msm_device_uart2;
-extern struct platform_device msm_device_uart3;
-extern struct platform_device msm8960_device_uart_gsbi2;
-extern struct platform_device msm8960_device_uart_gsbi5;
-extern struct platform_device msm_device_sdc1;
-extern struct platform_device msm_device_sdc2;
-extern struct platform_device msm_device_sdc3;
-extern struct platform_device msm_device_sdc4;
-extern struct platform_device msm_device_hsusb;
-extern struct platform_device msm_device_otg;
-extern struct platform_device msm_device_hsusb_host;
-extern struct platform_device msm_device_i2c;
-extern struct platform_device msm_device_smd;
-extern struct platform_device msm_device_nand;
-extern struct platform_device msm_device_mddi0;
-extern struct platform_device msm_device_mddi1;
-extern struct platform_device msm_device_mdp;
-extern struct platform_device msm_clock_7x01a;
-extern struct platform_device msm_clock_7x30;
-extern struct platform_device msm_clock_8x50;
-#endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
deleted file mode 100644
index fb9762464718..000000000000
--- a/arch/arm/mach-msm/dma.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* linux/arch/arm/mach-msm/dma.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/completion.h>
-#include <linux/module.h>
-#include <mach/dma.h>
-#include <mach/msm_iomap.h>
-#define MSM_DMOV_CHANNEL_COUNT 16
-#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
-#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
-#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
-#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
-#if defined(CONFIG_ARCH_MSM7X30)
-#define DMOV_SD_AARM DMOV_SD2
-#else
-#define DMOV_SD_AARM DMOV_SD3
-#endif
-#define DMOV_CMD_PTR(ch)      DMOV_SD_AARM(0x000, ch)
-#define DMOV_RSLT(ch)         DMOV_SD_AARM(0x040, ch)
-#define DMOV_FLUSH0(ch)       DMOV_SD_AARM(0x080, ch)
-#define DMOV_FLUSH1(ch)       DMOV_SD_AARM(0x0C0, ch)
-#define DMOV_FLUSH2(ch)       DMOV_SD_AARM(0x100, ch)
-#define DMOV_FLUSH3(ch)       DMOV_SD_AARM(0x140, ch)
-#define DMOV_FLUSH4(ch)       DMOV_SD_AARM(0x180, ch)
-#define DMOV_FLUSH5(ch)       DMOV_SD_AARM(0x1C0, ch)
-#define DMOV_STATUS(ch)       DMOV_SD_AARM(0x200, ch)
-#define DMOV_ISR              DMOV_SD_AARM(0x380, 0)
-#define DMOV_CONFIG(ch)       DMOV_SD_AARM(0x300, ch)
-enum {
-        MSM_DMOV_PRINT_ERRORS = 1,
-        MSM_DMOV_PRINT_IO = 2,
-        MSM_DMOV_PRINT_FLOW = 4
-};
-static DEFINE_SPINLOCK(msm_dmov_lock);
-static struct clk *msm_dmov_clk;
-static unsigned int channel_active;
-static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
-static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
-unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS;
-#define MSM_DMOV_DPRINTF(mask, format, args...) \
-        do { \
-                if ((mask) & msm_dmov_print_mask) \
-                        printk(KERN_ERR format, args); \
-        } while (0)
-#define PRINT_ERROR(format, args...) \
-        MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_ERRORS, format, args);
-#define PRINT_IO(format, args...) \
-        MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_IO, format, args);
-#define PRINT_FLOW(format, args...) \
-        MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args);
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
-{
-        writel((graceful << 31), DMOV_FLUSH0(id));
-}
-EXPORT_SYMBOL_GPL(msm_dmov_stop_cmd);
-void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
-{
-        unsigned long irq_flags;
-        unsigned int status;
-        spin_lock_irqsave(&msm_dmov_lock, irq_flags);
-        if (!channel_active)
-                clk_enable(msm_dmov_clk);
-        dsb();
-        status = readl(DMOV_STATUS(id));
-        if (list_empty(&ready_commands[id]) &&
-                (status & DMOV_STATUS_CMD_PTR_RDY)) {
-#if 0
-                if (list_empty(&active_commands[id])) {
-                        PRINT_FLOW("msm_dmov_enqueue_cmd(%d), enable interrupt\n", id);
-                        writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id));
-                }
-#endif
-                if (cmd->execute_func)
-                        cmd->execute_func(cmd);
-                PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status);
-                list_add_tail(&cmd->list, &active_commands[id]);
-                if (!channel_active)
-                        enable_irq(INT_ADM_AARM);
-                channel_active |= 1U << id;
-                writel(cmd->cmdptr, DMOV_CMD_PTR(id));
-        } else {
-                if (!channel_active)
-                        clk_disable(msm_dmov_clk);
-                if (list_empty(&active_commands[id]))
-                        PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status);
-                PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status %x\n", id, status);
-                list_add_tail(&cmd->list, &ready_commands[id]);
-        }
-        spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
-}
-EXPORT_SYMBOL_GPL(msm_dmov_enqueue_cmd);
-struct msm_dmov_exec_cmdptr_cmd {
-        struct msm_dmov_cmd dmov_cmd;
-        struct completion complete;
-        unsigned id;
-        unsigned int result;
-        struct msm_dmov_errdata err;
-};
-static void
-dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd,
-                               unsigned int result,
-                               struct msm_dmov_errdata *err)
-{
-        struct msm_dmov_exec_cmdptr_cmd *cmd = container_of(_cmd, struct msm_dmov_exec_cmdptr_cmd, dmov_cmd);
-        cmd->result = result;
-        if (result != 0x80000002 && err)
-                memcpy(&cmd->err, err, sizeof(struct msm_dmov_errdata));
-        complete(&cmd->complete);
-}
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr)
-{
-        struct msm_dmov_exec_cmdptr_cmd cmd;
-        PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr);
-        cmd.dmov_cmd.cmdptr = cmdptr;
-        cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func;
-        cmd.dmov_cmd.execute_func = NULL;
-        cmd.id = id;
-        init_completion(&cmd.complete);
-        msm_dmov_enqueue_cmd(id, &cmd.dmov_cmd);
-        wait_for_completion(&cmd.complete);
-        if (cmd.result != 0x80000002) {
-                PRINT_ERROR("dmov_exec_cmdptr(%d): ERROR, result: %x\n", id, cmd.result);
-                PRINT_ERROR("dmov_exec_cmdptr(%d):  flush: %x %x %x %x\n",
-                        id, cmd.err.flush[0], cmd.err.flush[1], cmd.err.flush[2], cmd.err.flush[3]);
-                return -EIO;
-        }
-        PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr);
-        return 0;
-}
-static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
-{
-        unsigned int int_status, mask, id;
-        unsigned long irq_flags;
-        unsigned int ch_status;
-        unsigned int ch_result;
-        struct msm_dmov_cmd *cmd;
-        spin_lock_irqsave(&msm_dmov_lock, irq_flags);
-        int_status = readl(DMOV_ISR); /* read and clear interrupt */
-        PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status);
-        while (int_status) {
-                mask = int_status & -int_status;
-                id = fls(mask) - 1;
-                PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n", int_status, mask, id);
-                int_status &= ~mask;
-                ch_status = readl(DMOV_STATUS(id));
-                if (!(ch_status & DMOV_STATUS_RSLT_VALID)) {
-                        PRINT_FLOW("msm_datamover_irq_handler id %d, result not valid %x\n", id, ch_status);
-                        continue;
-                }
-                do {
-                        ch_result = readl(DMOV_RSLT(id));
-                        if (list_empty(&active_commands[id])) {
-                                PRINT_ERROR("msm_datamover_irq_handler id %d, got result "
-                                        "with no active command, status %x, result %x\n",
-                                        id, ch_status, ch_result);
-                                cmd = NULL;
-                        } else
-                                cmd = list_entry(active_commands[id].next, typeof(*cmd), list);
-                        PRINT_FLOW("msm_datamover_irq_handler id %d, status %x, result %x\n", id, ch_status, ch_result);
-                        if (ch_result & DMOV_RSLT_DONE) {
-                                PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n",
-                                        id, ch_status);
-                                PRINT_IO("msm_datamover_irq_handler id %d, got result "
-                                        "for %p, result %x\n", id, cmd, ch_result);
-                                if (cmd) {
-                                        list_del(&cmd->list);
-                                        dsb();
-                                        cmd->complete_func(cmd, ch_result, NULL);
-                                }
-                        }
-                        if (ch_result & DMOV_RSLT_FLUSH) {
-                                struct msm_dmov_errdata errdata;
-                                errdata.flush[0] = readl(DMOV_FLUSH0(id));
-                                errdata.flush[1] = readl(DMOV_FLUSH1(id));
-                                errdata.flush[2] = readl(DMOV_FLUSH2(id));
-                                errdata.flush[3] = readl(DMOV_FLUSH3(id));
-                                errdata.flush[4] = readl(DMOV_FLUSH4(id));
-                                errdata.flush[5] = readl(DMOV_FLUSH5(id));
-                                PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
-                                PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
-                                if (cmd) {
-                                        list_del(&cmd->list);
-                                        dsb();
-                                        cmd->complete_func(cmd, ch_result, &errdata);
-                                }
-                        }
-                        if (ch_result & DMOV_RSLT_ERROR) {
-                                struct msm_dmov_errdata errdata;
-                                errdata.flush[0] = readl(DMOV_FLUSH0(id));
-                                errdata.flush[1] = readl(DMOV_FLUSH1(id));
-                                errdata.flush[2] = readl(DMOV_FLUSH2(id));
-                                errdata.flush[3] = readl(DMOV_FLUSH3(id));
-                                errdata.flush[4] = readl(DMOV_FLUSH4(id));
-                                errdata.flush[5] = readl(DMOV_FLUSH5(id));
-                                PRINT_ERROR("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
-                                PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
-                                if (cmd) {
-                                        list_del(&cmd->list);
-                                        dsb();
-                                        cmd->complete_func(cmd, ch_result, &errdata);
-                                }
-                                /* this does not seem to work, once we get an error */
-                                /* the datamover will no longer accept commands */
-                                writel(0, DMOV_FLUSH0(id));
-                        }
-                        ch_status = readl(DMOV_STATUS(id));
-                        PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
-                        if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
-                                cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
-                                list_move_tail(&cmd->list, &active_commands[id]);
-                                if (cmd->execute_func)
-                                        cmd->execute_func(cmd);
-                                PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
-                                writel(cmd->cmdptr, DMOV_CMD_PTR(id));
-                        }
-                } while (ch_status & DMOV_STATUS_RSLT_VALID);
-                if (list_empty(&active_commands[id]) && list_empty(&ready_commands[id]))
-                        channel_active &= ~(1U << id);
-                PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
-        }
-        if (!channel_active) {
-                disable_irq_nosync(INT_ADM_AARM);
-                clk_disable(msm_dmov_clk);
-        }
-        spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
-        return IRQ_HANDLED;
-}
-static int __init msm_init_datamover(void)
-{
-        int i;
-        int ret;
-        struct clk *clk;
-        for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
-                INIT_LIST_HEAD(&ready_commands[i]);
-                INIT_LIST_HEAD(&active_commands[i]);
-                writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i));
-        }
-        clk = clk_get(NULL, "adm_clk");
-        if (IS_ERR(clk))
-                return PTR_ERR(clk);
-        clk_prepare(clk);
-        msm_dmov_clk = clk;
-        ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
-        if (ret)
-                return ret;
-        disable_irq(INT_ADM_AARM);
-        return 0;
-}
-module_init(msm_init_datamover);
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
deleted file mode 100644
index f7a4ea593c95..000000000000
--- a/arch/arm/mach-msm/gpiomux-8x50.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include "gpiomux.h"
-#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
-        #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
-                                        | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
-        #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
-                                        | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
-#else
-        #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
-        #define SDCC_CLK_ACTV_CFG 0
-#endif
-#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
-                                | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
-struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
-        [86] = { /* UART3 RX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
-        },
-        [87] = { /* UART3 TX */
-                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
-                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
-        },
-        /* SDC1 data[3:0] & CMD */
-        [51 ... 55] = {
-                .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
-                .suspended = SDC1_SUSPEND_CONFIG
-        },
-        /* SDC1 CLK */
-        [56] = {
-                .active = SDCC_CLK_ACTV_CFG,
-                .suspended = SDC1_SUSPEND_CONFIG
-        },
-};
diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h
deleted file mode 100644
index 71d86feba450..000000000000
--- a/arch/arm/mach-msm/gpiomux-v1.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
-#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
-#if defined(CONFIG_ARCH_MSM7X30)
-#define GPIOMUX_NGPIOS 182
-#elif defined(CONFIG_ARCH_QSD8X50)
-#define GPIOMUX_NGPIOS 165
-#else
-#define GPIOMUX_NGPIOS 133
-#endif
-typedef u32 gpiomux_config_t;
-enum {
-        GPIOMUX_DRV_2MA  = 0UL << 17,
-        GPIOMUX_DRV_4MA  = 1UL << 17,
-        GPIOMUX_DRV_6MA  = 2UL << 17,
-        GPIOMUX_DRV_8MA  = 3UL << 17,
-        GPIOMUX_DRV_10MA = 4UL << 17,
-        GPIOMUX_DRV_12MA = 5UL << 17,
-        GPIOMUX_DRV_14MA = 6UL << 17,
-        GPIOMUX_DRV_16MA = 7UL << 17,
-};
-enum {
-        GPIOMUX_FUNC_GPIO = 0UL,
-        GPIOMUX_FUNC_1    = 1UL,
-        GPIOMUX_FUNC_2    = 2UL,
-        GPIOMUX_FUNC_3    = 3UL,
-        GPIOMUX_FUNC_4    = 4UL,
-        GPIOMUX_FUNC_5    = 5UL,
-        GPIOMUX_FUNC_6    = 6UL,
-        GPIOMUX_FUNC_7    = 7UL,
-        GPIOMUX_FUNC_8    = 8UL,
-        GPIOMUX_FUNC_9    = 9UL,
-        GPIOMUX_FUNC_A    = 10UL,
-        GPIOMUX_FUNC_B    = 11UL,
-        GPIOMUX_FUNC_C    = 12UL,
-        GPIOMUX_FUNC_D    = 13UL,
-        GPIOMUX_FUNC_E    = 14UL,
-        GPIOMUX_FUNC_F    = 15UL,
-};
-enum {
-        GPIOMUX_PULL_NONE   = 0UL << 15,
-        GPIOMUX_PULL_DOWN   = 1UL << 15,
-        GPIOMUX_PULL_KEEPER = 2UL << 15,
-        GPIOMUX_PULL_UP     = 3UL << 15,
-};
-#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
deleted file mode 100644
index 2b8e2d217082..000000000000
--- a/arch/arm/mach-msm/gpiomux.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include "gpiomux.h"
-#include "proc_comm.h"
-static DEFINE_SPINLOCK(gpiomux_lock);
-static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
-{
-        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
-                                ((gpio & 0x3ff) << 4);
-        unsigned tlmm_disable = 0;
-        int rc;
-        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
-                           &tlmm_config, &tlmm_disable);
-        if (rc)
-                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
-                       __func__, rc, tlmm_config, tlmm_disable);
-}
-int msm_gpiomux_write(unsigned gpio,
-                      gpiomux_config_t active,
-                      gpiomux_config_t suspended)
-{
-        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
-        unsigned long irq_flags;
-        gpiomux_config_t setting;
-        if (gpio >= GPIOMUX_NGPIOS)
-                return -EINVAL;
-        spin_lock_irqsave(&gpiomux_lock, irq_flags);
-        if (active & GPIOMUX_VALID)
-                cfg->active = active;
-        if (suspended & GPIOMUX_VALID)
-                cfg->suspended = suspended;
-        setting = cfg->ref ? active : suspended;
-        if (setting & GPIOMUX_VALID)
-                __msm_gpiomux_write(gpio, setting);
-        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
-        return 0;
-}
-EXPORT_SYMBOL(msm_gpiomux_write);
-int msm_gpiomux_get(unsigned gpio)
-{
-        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
-        unsigned long irq_flags;
-        if (gpio >= GPIOMUX_NGPIOS)
-                return -EINVAL;
-        spin_lock_irqsave(&gpiomux_lock, irq_flags);
-        if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
-                __msm_gpiomux_write(gpio, cfg->active);
-        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
-        return 0;
-}
-EXPORT_SYMBOL(msm_gpiomux_get);
-int msm_gpiomux_put(unsigned gpio)
-{
-        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
-        unsigned long irq_flags;
-        if (gpio >= GPIOMUX_NGPIOS)
-                return -EINVAL;
-        spin_lock_irqsave(&gpiomux_lock, irq_flags);
-        BUG_ON(cfg->ref == 0);
-        if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
-                __msm_gpiomux_write(gpio, cfg->suspended);
-        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
-        return 0;
-}
-EXPORT_SYMBOL(msm_gpiomux_put);
-static int __init gpiomux_init(void)
-{
-        unsigned n;
-        for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
-                msm_gpiomux_configs[n].ref = 0;
-                if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
-                        continue;
-                __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
-        }
-        return 0;
-}
-postcore_initcall(gpiomux_init);
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
deleted file mode 100644
index 4410d7766f93..000000000000
--- a/arch/arm/mach-msm/gpiomux.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
-#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <mach/msm_gpiomux.h>
-#include "gpiomux-v1.h"
-/**
- * struct msm_gpiomux_config: gpiomux settings for one gpio line.
- *
- * A complete gpiomux config is the bitwise-or of a drive-strength,
- * function, and pull.  For functions other than GPIO, the OE
- * is hard-wired according to the function.  For GPIO mode,
- * OE is controlled by gpiolib.
- *
- * Available settings differ by target; see the gpiomux header
- * specific to your target arch for available configurations.
- *
- * @active: The configuration to be installed when the line is
- * active, or its reference count is > 0.
- * @suspended: The configuration to be installed when the line
- * is suspended, or its reference count is 0.
- * @ref: The reference count of the line.  For internal use of
- * the gpiomux framework only.
- */
-struct msm_gpiomux_config {
-        gpiomux_config_t active;
-        gpiomux_config_t suspended;
-        unsigned         ref;
-};
-/**
- * @GPIOMUX_VALID:      If set, the config field contains 'good data'.
- *                      The absence of this bit will prevent the gpiomux
- *                      system from applying the configuration under all
- *                      circumstances.
- */
-enum {
-        GPIOMUX_VALID    = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
-        GPIOMUX_CTL_MASK = GPIOMUX_VALID,
-};
-#ifdef CONFIG_MSM_GPIOMUX
-/* Each architecture must provide its own instance of this table.
- * To avoid having gpiomux manage any given gpio, one or both of
- * the entries can avoid setting GPIOMUX_VALID - the absence
- * of that flag will prevent the configuration from being applied
- * during state transitions.
- */
-extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
-/* Install a new configuration to the gpio line.  To avoid overwriting
- * a configuration, leave the VALID bit out.
- */
-int msm_gpiomux_write(unsigned gpio,
-                      gpiomux_config_t active,
-                      gpiomux_config_t suspended);
-#else
-static inline int msm_gpiomux_write(unsigned gpio,
-                                    gpiomux_config_t active,
-                                    gpiomux_config_t suspended)
-{
-        return -ENOSYS;
-}
-#endif
-#endif
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
deleted file mode 100644
index fd4f4a7a83b3..000000000000
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_CLK_H
-#define __MACH_CLK_H
-/* Magic rate value for use with PM QOS to request the board's maximum
- * supported AXI rate. PM QOS will only pass positive s32 rate values
- * through to the clock driver, so INT_MAX is used.
- */
-#define MSM_AXI_MAX_FREQ        LONG_MAX
-enum clk_reset_action {
-        CLK_RESET_DEASSERT      = 0,
-        CLK_RESET_ASSERT        = 1
-};
-struct clk;
-/* Assert/Deassert reset to a hardware block associated with a clock */
-int clk_reset(struct clk *clk, enum clk_reset_action action);
-#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
deleted file mode 100644
index a72d48d42342..000000000000
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* linux/include/asm-arm/arch-msm/dma.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_DMA_H
-#include <linux/list.h>
-struct msm_dmov_errdata {
-        uint32_t flush[6];
-};
-struct msm_dmov_cmd {
-        struct list_head list;
-        unsigned int cmdptr;
-        void (*complete_func)(struct msm_dmov_cmd *cmd,
-                              unsigned int result,
-                              struct msm_dmov_errdata *err);
-        void (*execute_func)(struct msm_dmov_cmd *cmd);
-        void *data;
-};
-#ifndef CONFIG_ARCH_MSM8X60
-void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-#else
-static inline
-void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
-static inline
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
-static inline
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
-#endif
-#define DMOV_CMD_LIST         (0 << 29) /* does not work */
-#define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
-#define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
-#define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
-#define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
-#define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
-#define DMOV_RSLT_ERROR       (1 << 3)
-#define DMOV_RSLT_FLUSH       (1 << 2)
-#define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
-#define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
-#define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
-#define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
-#define DMOV_STATUS_RSLT_VALID       (1 << 1)
-#define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
-#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
-#define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
-#define DMOV_CONFIG_IRQ_EN             (1 << 0)
-/* channel assignments */
-#define DMOV_NAND_CHAN        7
-#define DMOV_NAND_CRCI_CMD    5
-#define DMOV_NAND_CRCI_DATA   4
-#define DMOV_SDC1_CHAN        8
-#define DMOV_SDC1_CRCI        6
-#define DMOV_SDC2_CHAN        8
-#define DMOV_SDC2_CRCI        7
-#define DMOV_TSIF_CHAN        10
-#define DMOV_TSIF_CRCI        10
-#define DMOV_USB_CHAN         11
-/* no client rate control ifc (eg, ram) */
-#define DMOV_NONE_CRCI        0
-/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
- * is going to walk a list of 32bit pointers as described below.  Each
- * pointer points to a *array* of dmov_s, etc structs.  The last pointer
- * in the list is marked with CMD_PTR_LP.  The last struct in each array
- * is marked with CMD_LC (see below).
- */
-#define CMD_PTR_ADDR(addr)  ((addr) >> 3)
-#define CMD_PTR_LP          (1 << 31) /* last pointer */
-#define CMD_PTR_PT          (3 << 29) /* ? */
-/* Single Item Mode */
-typedef struct {
-        unsigned cmd;
-        unsigned src;
-        unsigned dst;
-        unsigned len;
-} dmov_s;
-/* Scatter/Gather Mode */
-typedef struct {
-        unsigned cmd;
-        unsigned src_dscr;
-        unsigned dst_dscr;
-        unsigned _reserved;
-} dmov_sg;
-/* Box mode */
-typedef struct {
-        uint32_t cmd;
-        uint32_t src_row_addr;
-        uint32_t dst_row_addr;
-        uint32_t src_dst_len;
-        uint32_t num_rows;
-        uint32_t row_offset;
-} dmov_box;
-/* bits for the cmd field of the above structures */
-#define CMD_LC      (1 << 31)  /* last command */
-#define CMD_FR      (1 << 22)  /* force result -- does not work? */
-#define CMD_OCU     (1 << 21)  /* other channel unblock */
-#define CMD_OCB     (1 << 20)  /* other channel block */
-#define CMD_TCB     (1 << 19)  /* ? */
-#define CMD_DAH     (1 << 18)  /* destination address hold -- does not work?*/
-#define CMD_SAH     (1 << 17)  /* source address hold -- does not work? */
-#define CMD_MODE_SINGLE     (0 << 0) /* dmov_s structure used */
-#define CMD_MODE_SG         (1 << 0) /* untested */
-#define CMD_MODE_IND_SG     (2 << 0) /* untested */
-#define CMD_MODE_BOX        (3 << 0) /* untested */
-#define CMD_DST_SWAP_BYTES  (1 << 14) /* exchange each byte n with byte n+1 */
-#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
-#define CMD_DST_SWAP_WORDS  (1 << 16) /* exchange each word n with word n+1 */
-#define CMD_SRC_SWAP_BYTES  (1 << 11) /* exchange each byte n with byte n+1 */
-#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
-#define CMD_SRC_SWAP_WORDS  (1 << 13) /* exchange each word n with word n+1 */
-#define CMD_DST_CRCI(n)     (((n) & 15) << 7)
-#define CMD_SRC_CRCI(n)     (((n) & 15) << 3)
-#endif
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
deleted file mode 100644
index f2ae9087f654..000000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#if !defined(CONFIG_ARM_GIC)
-#include <mach/msm_iomap.h>
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
-#endif
diff --git a/arch/arm/mach-msm/include/mach/hardware.h b/arch/arm/mach-msm/include/mach/hardware.h
deleted file mode 100644
index 2d126091ae41..000000000000
--- a/arch/arm/mach-msm/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-msm/include/mach/hardware.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_HARDWARE_H
-#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x00.h b/arch/arm/mach-msm/include/mach/irqs-7x00.h
deleted file mode 100644
index f1fe70612fe9..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x00.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- */
-#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
-#define __ASM_ARCH_MSM_IRQS_7X00_H
-/* MSM ARM11 Interrupt Numbers */
-/* See 80-VE113-1 A, pp219-221     */
-#define INT_A9_M2A_0         0
-#define INT_A9_M2A_1         1
-#define INT_A9_M2A_2         2
-#define INT_A9_M2A_3         3
-#define INT_A9_M2A_4         4
-#define INT_A9_M2A_5         5
-#define INT_A9_M2A_6         6
-#define INT_GP_TIMER_EXP     7
-#define INT_DEBUG_TIMER_EXP  8
-#define INT_UART1            9
-#define INT_UART2            10
-#define INT_UART3            11
-#define INT_UART1_RX         12
-#define INT_UART2_RX         13
-#define INT_UART3_RX         14
-#define INT_USB_OTG          15
-#define INT_MDDI_PRI         16
-#define INT_MDDI_EXT         17
-#define INT_MDDI_CLIENT      18
-#define INT_MDP              19
-#define INT_GRAPHICS         20
-#define INT_ADM_AARM         21
-#define INT_ADSP_A11         22
-#define INT_ADSP_A9_A11      23
-#define INT_SDC1_0           24
-#define INT_SDC1_1           25
-#define INT_SDC2_0           26
-#define INT_SDC2_1           27
-#define INT_KEYSENSE         28
-#define INT_TCHSCRN_SSBI     29
-#define INT_TCHSCRN1         30
-#define INT_TCHSCRN2         31
-#define INT_GPIO_GROUP1      (32 + 0)
-#define INT_GPIO_GROUP2      (32 + 1)
-#define INT_PWB_I2C          (32 + 2)
-#define INT_SOFTRESET        (32 + 3)
-#define INT_NAND_WR_ER_DONE  (32 + 4)
-#define INT_NAND_OP_DONE     (32 + 5)
-#define INT_PBUS_ARM11       (32 + 6)
-#define INT_AXI_MPU_SMI      (32 + 7)
-#define INT_AXI_MPU_EBI1     (32 + 8)
-#define INT_AD_HSSD          (32 + 9)
-#define INT_ARM11_PMU        (32 + 10)
-#define INT_ARM11_DMA        (32 + 11)
-#define INT_TSIF_IRQ         (32 + 12)
-#define INT_UART1DM_IRQ      (32 + 13)
-#define INT_UART1DM_RX       (32 + 14)
-#define INT_USB_HS           (32 + 15)
-#define INT_SDC3_0           (32 + 16)
-#define INT_SDC3_1           (32 + 17)
-#define INT_SDC4_0           (32 + 18)
-#define INT_SDC4_1           (32 + 19)
-#define INT_UART2DM_RX       (32 + 20)
-#define INT_UART2DM_IRQ      (32 + 21)
-/* 22-31 are reserved */
-#define NR_MSM_IRQS 64
-#define NR_GPIO_IRQS 122
-#define NR_BOARD_IRQS 64
-#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
deleted file mode 100644
index 1f15902655fd..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x30.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
-#define __ASM_ARCH_MSM_IRQS_7X30_H
-/* MSM ACPU Interrupt Numbers */
-#define INT_DEBUG_TIMER_EXP     0
-#define INT_GPT0_TIMER_EXP      1
-#define INT_GPT1_TIMER_EXP      2
-#define INT_WDT0_ACCSCSSBARK    3
-#define INT_WDT1_ACCSCSSBARK    4
-#define INT_AVS_SVIC            5
-#define INT_AVS_SVIC_SW_DONE    6
-#define INT_SC_DBG_RX_FULL      7
-#define INT_SC_DBG_TX_EMPTY     8
-#define INT_ARM11_PM            9
-#define INT_AVS_REQ_DOWN        10
-#define INT_AVS_REQ_UP          11
-#define INT_SC_ACG              12
-/* SCSS_VICFIQSTS0[13:15] are RESERVED */
-#define INT_L2_SVICCPUIRPTREQ   16
-#define INT_L2_SVICDMANSIRPTREQ 17
-#define INT_L2_SVICDMASIRPTREQ  18
-#define INT_L2_SVICSLVIRPTREQ   19
-#define INT_AD5A_MPROC_APPS_0   20
-#define INT_AD5A_MPROC_APPS_1   21
-#define INT_A9_M2A_0            22
-#define INT_A9_M2A_1            23
-#define INT_A9_M2A_2            24
-#define INT_A9_M2A_3            25
-#define INT_A9_M2A_4            26
-#define INT_A9_M2A_5            27
-#define INT_A9_M2A_6            28
-#define INT_A9_M2A_7            29
-#define INT_A9_M2A_8            30
-#define INT_A9_M2A_9            31
-#define INT_AXI_EBI1_SC         (32 + 0)
-#define INT_IMEM_ERR            (32 + 1)
-#define INT_AXI_EBI0_SC         (32 + 2)
-#define INT_PBUS_SC_IRQC        (32 + 3)
-#define INT_PERPH_BUS_BPM       (32 + 4)
-#define INT_CC_TEMP_SENSE       (32 + 5)
-#define INT_UXMC_EBI0           (32 + 6)
-#define INT_UXMC_EBI1           (32 + 7)
-#define INT_EBI2_OP_DONE        (32 + 8)
-#define INT_EBI2_WR_ER_DONE     (32 + 9)
-#define INT_TCSR_SPSS_CE        (32 + 10)
-#define INT_EMDH                (32 + 11)
-#define INT_PMDH                (32 + 12)
-#define INT_MDC                 (32 + 13)
-#define INT_MIDI_TO_SUPSS       (32 + 14)
-#define INT_LPA_2               (32 + 15)
-#define INT_GPIO_GROUP1_SECURE  (32 + 16)
-#define INT_GPIO_GROUP2_SECURE  (32 + 17)
-#define INT_GPIO_GROUP1         (32 + 18)
-#define INT_GPIO_GROUP2         (32 + 19)
-#define INT_MPRPH_SOFTRESET     (32 + 20)
-#define INT_PWB_I2C             (32 + 21)
-#define INT_PWB_I2C_2           (32 + 22)
-#define INT_TSSC_SAMPLE         (32 + 23)
-#define INT_TSSC_PENUP          (32 + 24)
-#define INT_TCHSCRN_SSBI        (32 + 25)
-#define INT_FM_RDS              (32 + 26)
-#define INT_KEYSENSE            (32 + 27)
-#define INT_USB_OTG_HS          (32 + 28)
-#define INT_USB_OTG_HS2         (32 + 29)
-#define INT_USB_OTG_HS3         (32 + 30)
-#define INT_CSI                 (32 + 31)
-#define INT_SPI_OUTPUT          (64 + 0)
-#define INT_SPI_INPUT           (64 + 1)
-#define INT_SPI_ERROR           (64 + 2)
-#define INT_UART1               (64 + 3)
-#define INT_UART1_RX            (64 + 4)
-#define INT_UART2               (64 + 5)
-#define INT_UART2_RX            (64 + 6)
-#define INT_UART3               (64 + 7)
-#define INT_UART3_RX            (64 + 8)
-#define INT_UART1DM_IRQ         (64 + 9)
-#define INT_UART1DM_RX          (64 + 10)
-#define INT_UART2DM_IRQ         (64 + 11)
-#define INT_UART2DM_RX          (64 + 12)
-#define INT_TSIF                (64 + 13)
-#define INT_ADM_SC1             (64 + 14)
-#define INT_ADM_SC2             (64 + 15)
-#define INT_MDP                 (64 + 16)
-#define INT_VPE                 (64 + 17)
-#define INT_GRP_2D              (64 + 18)
-#define INT_GRP_3D              (64 + 19)
-#define INT_ROTATOR             (64 + 20)
-#define INT_MFC720              (64 + 21)
-#define INT_JPEG                (64 + 22)
-#define INT_VFE                 (64 + 23)
-#define INT_TV_ENC              (64 + 24)
-#define INT_PMIC_SSBI           (64 + 25)
-#define INT_MPM_1               (64 + 26)
-#define INT_TCSR_SPSS_SAMPLE    (64 + 27)
-#define INT_TCSR_SPSS_PENUP     (64 + 28)
-#define INT_MPM_2               (64 + 29)
-#define INT_SDC1_0              (64 + 30)
-#define INT_SDC1_1              (64 + 31)
-#define INT_SDC3_0              (96 + 0)
-#define INT_SDC3_1              (96 + 1)
-#define INT_SDC2_0              (96 + 2)
-#define INT_SDC2_1              (96 + 3)
-#define INT_SDC4_0              (96 + 4)
-#define INT_SDC4_1              (96 + 5)
-#define INT_PWB_QUP_IN          (96 + 6)
-#define INT_PWB_QUP_OUT         (96 + 7)
-#define INT_PWB_QUP_ERR         (96 + 8)
-#define INT_SCSS_WDT0_BITE      (96 + 9)
-/* SCSS_VICFIQSTS3[10:31] are RESERVED */
-/* Retrofit universal macro names */
-#define INT_ADM_AARM            INT_ADM_SC2
-#define INT_USB_HS              INT_USB_OTG_HS
-#define INT_USB_OTG             INT_USB_OTG_HS
-#define INT_TCHSCRN1            INT_TSSC_SAMPLE
-#define INT_TCHSCRN2            INT_TSSC_PENUP
-#define INT_GP_TIMER_EXP        INT_GPT0_TIMER_EXP
-#define INT_ADSP_A11            INT_AD5A_MPROC_APPS_0
-#define INT_ADSP_A9_A11         INT_AD5A_MPROC_APPS_1
-#define INT_MDDI_EXT            INT_EMDH
-#define INT_MDDI_PRI            INT_PMDH
-#define INT_MDDI_CLIENT         INT_MDC
-#define INT_NAND_WR_ER_DONE     INT_EBI2_WR_ER_DONE
-#define INT_NAND_OP_DONE        INT_EBI2_OP_DONE
-#define NR_MSM_IRQS             128
-#define NR_GPIO_IRQS            182
-#define PMIC8058_IRQ_BASE       (NR_MSM_IRQS + NR_GPIO_IRQS)
-#define NR_PMIC8058_GPIO_IRQS   40
-#define NR_PMIC8058_MPP_IRQS    12
-#define NR_PMIC8058_MISC_IRQS   8
-#define NR_PMIC8058_IRQS        (NR_PMIC8058_GPIO_IRQS +\
-                                NR_PMIC8058_MPP_IRQS +\
-                                NR_PMIC8058_MISC_IRQS)
-#define NR_BOARD_IRQS           NR_PMIC8058_IRQS
-#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
deleted file mode 100644
index 26adbe0e9406..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-8x50.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
-#define __ASM_ARCH_MSM_IRQS_8XXX_H
-/* MSM ACPU Interrupt Numbers */
-#define INT_A9_M2A_0         0
-#define INT_A9_M2A_1         1
-#define INT_A9_M2A_2         2
-#define INT_A9_M2A_3         3
-#define INT_A9_M2A_4         4
-#define INT_A9_M2A_5         5
-#define INT_A9_M2A_6         6
-#define INT_GP_TIMER_EXP     7
-#define INT_DEBUG_TIMER_EXP  8
-#define INT_SIRC_0           9
-#define INT_SDC3_0           10
-#define INT_SDC3_1           11
-#define INT_SDC4_0           12
-#define INT_SDC4_1           13
-#define INT_AD6_EXT_VFR      14
-#define INT_USB_OTG          15
-#define INT_MDDI_PRI         16
-#define INT_MDDI_EXT         17
-#define INT_MDDI_CLIENT      18
-#define INT_MDP              19
-#define INT_GRAPHICS         20
-#define INT_ADM_AARM         21
-#define INT_ADSP_A11         22
-#define INT_ADSP_A9_A11      23
-#define INT_SDC1_0           24
-#define INT_SDC1_1           25
-#define INT_SDC2_0           26
-#define INT_SDC2_1           27
-#define INT_KEYSENSE         28
-#define INT_TCHSCRN_SSBI     29
-#define INT_TCHSCRN1         30
-#define INT_TCHSCRN2         31
-#define INT_TCSR_MPRPH_SC1   (32 + 0)
-#define INT_USB_FS2          (32 + 1)
-#define INT_PWB_I2C          (32 + 2)
-#define INT_SOFTRESET        (32 + 3)
-#define INT_NAND_WR_ER_DONE  (32 + 4)
-#define INT_NAND_OP_DONE     (32 + 5)
-#define INT_TCSR_MPRPH_SC2   (32 + 6)
-#define INT_OP_PEN           (32 + 7)
-#define INT_AD_HSSD          (32 + 8)
-#define INT_ARM11_PM         (32 + 9)
-#define INT_SDMA_NON_SECURE  (32 + 10)
-#define INT_TSIF_IRQ         (32 + 11)
-#define INT_UART1DM_IRQ      (32 + 12)
-#define INT_UART1DM_RX       (32 + 13)
-#define INT_SDMA_SECURE      (32 + 14)
-#define INT_SI2S_SLAVE       (32 + 15)
-#define INT_SC_I2CPU         (32 + 16)
-#define INT_SC_DBG_RDTRFULL  (32 + 17)
-#define INT_SC_DBG_WDTRFULL  (32 + 18)
-#define INT_SCPLL_CTL_DONE   (32 + 19)
-#define INT_UART2DM_IRQ      (32 + 20)
-#define INT_UART2DM_RX       (32 + 21)
-#define INT_VDC_MEC          (32 + 22)
-#define INT_VDC_DB           (32 + 23)
-#define INT_VDC_AXI          (32 + 24)
-#define INT_VFE              (32 + 25)
-#define INT_USB_HS           (32 + 26)
-#define INT_AUDIO_OUT0       (32 + 27)
-#define INT_AUDIO_OUT1       (32 + 28)
-#define INT_CRYPTO           (32 + 29)
-#define INT_AD6M_IDLE        (32 + 30)
-#define INT_SIRC_1           (32 + 31)
-#define NR_GPIO_IRQS 165
-#define NR_MSM_IRQS 64
-#define NR_BOARD_IRQS 64
-#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
deleted file mode 100644
index 164d355c96ea..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_IRQS_H
-#define __ASM_ARCH_MSM_IRQS_H
-#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
-#if defined(CONFIG_ARCH_MSM7X30)
-#include "irqs-7x30.h"
-#elif defined(CONFIG_ARCH_QSD8X50)
-#include "irqs-8x50.h"
-#include "sirc.h"
-#elif defined(CONFIG_ARCH_MSM_ARM11)
-#include "irqs-7x00.h"
-#else
-#error "Unknown architecture specification"
-#endif
-#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
-#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_gpiomux.h b/arch/arm/mach-msm/include/mach/msm_gpiomux.h
deleted file mode 100644
index 0c7d3936e02f..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_gpiomux.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _LINUX_MSM_GPIOMUX_H
-#define _LINUX_MSM_GPIOMUX_H
-#ifdef CONFIG_MSM_GPIOMUX
-/* Increment a gpio's reference count, possibly activating the line. */
-int __must_check msm_gpiomux_get(unsigned gpio);
-/* Decrement a gpio's reference count, possibly suspending the line. */
-int msm_gpiomux_put(unsigned gpio);
-#else
-static inline int __must_check msm_gpiomux_get(unsigned gpio)
-{
-        return -ENOSYS;
-}
-static inline int msm_gpiomux_put(unsigned gpio)
-{
-        return -ENOSYS;
-}
-#endif
-#endif /* _LINUX_MSM_GPIOMUX_H */
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
deleted file mode 100644
index 67dc0e98b958..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* arch/arm/mach-msm/include/mach/msm_iomap.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
-#define __ASM_ARCH_MSM_IOMAP_7X00_H
-#include <asm/sizes.h>
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-#define MSM_VIC_BASE          IOMEM(0xE0000000)
-#define MSM_VIC_PHYS          0xC0000000
-#define MSM_VIC_SIZE          SZ_4K
-#define MSM7X00_CSR_PHYS      0xC0100000
-#define MSM7X00_CSR_SIZE      SZ_4K
-#define MSM_DMOV_BASE         IOMEM(0xE0002000)
-#define MSM_DMOV_PHYS         0xA9700000
-#define MSM_DMOV_SIZE         SZ_4K
-#define MSM7X00_GPIO1_PHYS        0xA9200000
-#define MSM7X00_GPIO1_SIZE        SZ_4K
-#define MSM7X00_GPIO2_PHYS        0xA9300000
-#define MSM7X00_GPIO2_SIZE        SZ_4K
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xA8600000
-#define MSM_CLK_CTL_SIZE      SZ_4K
-#define MSM_SHARED_RAM_BASE   IOMEM(0xE0100000)
-#define MSM_SHARED_RAM_PHYS   0x01F00000
-#define MSM_SHARED_RAM_SIZE   SZ_1M
-#define MSM_UART1_PHYS        0xA9A00000
-#define MSM_UART1_SIZE        SZ_4K
-#define MSM_UART2_PHYS        0xA9B00000
-#define MSM_UART2_SIZE        SZ_4K
-#define MSM_UART3_PHYS        0xA9C00000
-#define MSM_UART3_SIZE        SZ_4K
-#define MSM_SDC1_PHYS         0xA0400000
-#define MSM_SDC1_SIZE         SZ_4K
-#define MSM_SDC2_PHYS         0xA0500000
-#define MSM_SDC2_SIZE         SZ_4K
-#define MSM_SDC3_PHYS         0xA0600000
-#define MSM_SDC3_SIZE         SZ_4K
-#define MSM_SDC4_PHYS         0xA0700000
-#define MSM_SDC4_SIZE         SZ_4K
-#define MSM_I2C_PHYS          0xA9900000
-#define MSM_I2C_SIZE          SZ_4K
-#define MSM_HSUSB_PHYS        0xA0800000
-#define MSM_HSUSB_SIZE        SZ_4K
-#define MSM_PMDH_PHYS         0xAA600000
-#define MSM_PMDH_SIZE         SZ_4K
-#define MSM_EMDH_PHYS         0xAA700000
-#define MSM_EMDH_SIZE         SZ_4K
-#define MSM_MDP_PHYS          0xAA200000
-#define MSM_MDP_SIZE          0x000F0000
-#define MSM_MDC_PHYS          0xAA500000
-#define MSM_MDC_SIZE          SZ_1M
-#define MSM_AD5_PHYS          0xAC000000
-#define MSM_AD5_SIZE          (SZ_1M*13)
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
deleted file mode 100644
index 198202c267c8..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
-#define __ASM_ARCH_MSM_IOMAP_7X30_H
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-#define MSM_VIC_BASE          IOMEM(0xE0000000)
-#define MSM_VIC_PHYS          0xC0080000
-#define MSM_VIC_SIZE          SZ_4K
-#define MSM7X30_CSR_PHYS      0xC0100000
-#define MSM7X30_CSR_SIZE      SZ_4K
-#define MSM_DMOV_BASE         IOMEM(0xE0002000)
-#define MSM_DMOV_PHYS         0xAC400000
-#define MSM_DMOV_SIZE         SZ_4K
-#define MSM7X30_GPIO1_PHYS        0xAC001000
-#define MSM7X30_GPIO1_SIZE        SZ_4K
-#define MSM7X30_GPIO2_PHYS        0xAC101000
-#define MSM7X30_GPIO2_SIZE        SZ_4K
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xAB800000
-#define MSM_CLK_CTL_SIZE      SZ_4K
-#define MSM_CLK_CTL_SH2_BASE  IOMEM(0xE0006000)
-#define MSM_CLK_CTL_SH2_PHYS  0xABA01000
-#define MSM_CLK_CTL_SH2_SIZE  SZ_4K
-#define MSM_ACC_BASE          IOMEM(0xE0007000)
-#define MSM_ACC_PHYS          0xC0101000
-#define MSM_ACC_SIZE          SZ_4K
-#define MSM_SAW_BASE          IOMEM(0xE0008000)
-#define MSM_SAW_PHYS          0xC0102000
-#define MSM_SAW_SIZE          SZ_4K
-#define MSM_GCC_BASE          IOMEM(0xE0009000)
-#define MSM_GCC_PHYS          0xC0182000
-#define MSM_GCC_SIZE          SZ_4K
-#define MSM_TCSR_BASE         IOMEM(0xE000A000)
-#define MSM_TCSR_PHYS         0xAB600000
-#define MSM_TCSR_SIZE         SZ_4K
-#define MSM_SHARED_RAM_BASE   IOMEM(0xE0100000)
-#define MSM_SHARED_RAM_PHYS   0x00100000
-#define MSM_SHARED_RAM_SIZE   SZ_1M
-#define MSM_UART1_PHYS        0xACA00000
-#define MSM_UART1_SIZE        SZ_4K
-#define MSM_UART2_PHYS        0xACB00000
-#define MSM_UART2_SIZE        SZ_4K
-#define MSM_UART3_PHYS        0xACC00000
-#define MSM_UART3_SIZE        SZ_4K
-#define MSM_MDC_BASE          IOMEM(0xE0200000)
-#define MSM_MDC_PHYS          0xAA500000
-#define MSM_MDC_SIZE          SZ_1M
-#define MSM_AD5_BASE          IOMEM(0xE0300000)
-#define MSM_AD5_PHYS          0xA7000000
-#define MSM_AD5_SIZE          (SZ_1M*13)
-#define MSM_HSUSB_PHYS        0xA3600000
-#define MSM_HSUSB_SIZE        SZ_1K
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
deleted file mode 100644
index 0faa894729b7..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
-#define __ASM_ARCH_MSM_IOMAP_8X50_H
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-#define MSM_VIC_BASE          IOMEM(0xE0000000)
-#define MSM_VIC_PHYS          0xAC000000
-#define MSM_VIC_SIZE          SZ_4K
-#define QSD8X50_CSR_PHYS      0xAC100000
-#define QSD8X50_CSR_SIZE      SZ_4K
-#define MSM_DMOV_BASE         IOMEM(0xE0002000)
-#define MSM_DMOV_PHYS         0xA9700000
-#define MSM_DMOV_SIZE         SZ_4K
-#define QSD8X50_GPIO1_PHYS        0xA9000000
-#define QSD8X50_GPIO1_SIZE        SZ_4K
-#define QSD8X50_GPIO2_PHYS        0xA9100000
-#define QSD8X50_GPIO2_SIZE        SZ_4K
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xA8600000
-#define MSM_CLK_CTL_SIZE      SZ_4K
-#define MSM_SIRC_BASE         IOMEM(0xE1006000)
-#define MSM_SIRC_PHYS         0xAC200000
-#define MSM_SIRC_SIZE         SZ_4K
-#define MSM_SCPLL_BASE        IOMEM(0xE1007000)
-#define MSM_SCPLL_PHYS        0xA8800000
-#define MSM_SCPLL_SIZE        SZ_4K
-#ifdef CONFIG_MSM_SOC_REV_A
-#define MSM_SMI_BASE 0xE0000000
-#else
-#define MSM_SMI_BASE 0x00000000
-#endif
-#define MSM_SHARED_RAM_BASE   IOMEM(0xE0100000)
-#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
-#define MSM_SHARED_RAM_SIZE   SZ_1M
-#define MSM_UART1_PHYS        0xA9A00000
-#define MSM_UART1_SIZE        SZ_4K
-#define MSM_UART2_PHYS        0xA9B00000
-#define MSM_UART2_SIZE        SZ_4K
-#define MSM_UART3_PHYS        0xA9C00000
-#define MSM_UART3_SIZE        SZ_4K
-#define MSM_MDC_BASE          IOMEM(0xE0200000)
-#define MSM_MDC_PHYS          0xAA500000
-#define MSM_MDC_SIZE          SZ_1M
-#define MSM_AD5_BASE          IOMEM(0xE0300000)
-#define MSM_AD5_PHYS          0xAC000000
-#define MSM_AD5_SIZE          (SZ_1M*13)
-#define MSM_I2C_SIZE          SZ_4K
-#define MSM_I2C_PHYS          0xA9900000
-#define MSM_HSUSB_PHYS        0xA0800000
-#define MSM_HSUSB_SIZE        SZ_1K
-#define MSM_NAND_PHYS           0xA0A00000
-#define MSM_TSIF_PHYS        (0xa0100000)
-#define MSM_TSIF_SIZE        (0x200)
-#define MSM_TSSC_PHYS         0xAA300000
-#define MSM_UART1DM_PHYS      0xA0200000
-#define MSM_UART2DM_PHYS      0xA0900000
-#define MSM_SDC1_PHYS          0xA0300000
-#define MSM_SDC1_SIZE          SZ_4K
-#define MSM_SDC2_PHYS          0xA0400000
-#define MSM_SDC2_SIZE          SZ_4K
-#define MSM_SDC3_PHYS          0xA0500000
-#define MSM_SDC3_SIZE           SZ_4K
-#define MSM_SDC4_PHYS          0xA0600000
-#define MSM_SDC4_SIZE          SZ_4K
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
deleted file mode 100644
index 0e4f49157684..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-#ifndef __ASM_ARCH_MSM_IOMAP_H
-#define __ASM_ARCH_MSM_IOMAP_H
-#include <asm/sizes.h>
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-#if defined(CONFIG_ARCH_MSM7X30)
-#include "msm_iomap-7x30.h"
-#elif defined(CONFIG_ARCH_QSD8X50)
-#include "msm_iomap-8x50.h"
-#else
-#include "msm_iomap-7x00.h"
-#endif
-/* Virtual addresses shared across all MSM targets. */
-#define MSM_CSR_BASE            IOMEM(0xE0001000)
-#define MSM_GPIO1_BASE          IOMEM(0xE0003000)
-#define MSM_GPIO2_BASE          IOMEM(0xE0004000)
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
deleted file mode 100644
index 029463ec8756..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* linux/include/asm-arm/arch-msm/msm_smd.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_SMD_H
-#define __ASM_ARCH_MSM_SMD_H
-typedef struct smd_channel smd_channel_t;
-extern int (*msm_check_for_modem_crash)(void);
-/* warning: notify() may be called before open returns */
-int smd_open(const char *name, smd_channel_t **ch, void *priv,
-             void (*notify)(void *priv, unsigned event));
-#define SMD_EVENT_DATA 1
-#define SMD_EVENT_OPEN 2
-#define SMD_EVENT_CLOSE 3
-int smd_close(smd_channel_t *ch);
-/* passing a null pointer for data reads and discards */
-int smd_read(smd_channel_t *ch, void *data, int len);
-/* Write to stream channels may do a partial write and return
-** the length actually written.
-** Write to packet channels will never do a partial write --
-** it will return the requested length written or an error.
-*/
-int smd_write(smd_channel_t *ch, const void *data, int len);
-int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
-int smd_write_avail(smd_channel_t *ch);
-int smd_read_avail(smd_channel_t *ch);
-/* Returns the total size of the current packet being read.
-** Returns 0 if no packets available or a stream channel.
-*/
-int smd_cur_packet_size(smd_channel_t *ch);
-/* used for tty unthrottling and the like -- causes the notify()
-** callback to be called from the same lock context as is used
-** when it is called from channel updates
-*/
-void smd_kick(smd_channel_t *ch);
-#if 0
-/* these are interruptable waits which will block you until the specified
-** number of bytes are readable or writable.
-*/
-int smd_wait_until_readable(smd_channel_t *ch, int bytes);
-int smd_wait_until_writable(smd_channel_t *ch, int bytes);
-#endif
-typedef enum {
-        SMD_PORT_DS = 0,
-        SMD_PORT_DIAG,
-        SMD_PORT_RPC_CALL,
-        SMD_PORT_RPC_REPLY,
-        SMD_PORT_BT,
-        SMD_PORT_CONTROL,
-        SMD_PORT_MEMCPY_SPARE1,
-        SMD_PORT_DATA1,
-        SMD_PORT_DATA2,
-        SMD_PORT_DATA3,
-        SMD_PORT_DATA4,
-        SMD_PORT_DATA5,
-        SMD_PORT_DATA6,
-        SMD_PORT_DATA7,
-        SMD_PORT_DATA8,
-        SMD_PORT_DATA9,
-        SMD_PORT_DATA10,
-        SMD_PORT_DATA11,
-        SMD_PORT_DATA12,
-        SMD_PORT_DATA13,
-        SMD_PORT_DATA14,
-        SMD_PORT_DATA15,
-        SMD_PORT_DATA16,
-        SMD_PORT_DATA17,
-        SMD_PORT_DATA18,
-        SMD_PORT_DATA19,
-        SMD_PORT_DATA20,
-        SMD_PORT_GPS_NMEA,
-        SMD_PORT_BRIDGE_1,
-        SMD_PORT_BRIDGE_2,
-        SMD_PORT_BRIDGE_3,
-        SMD_PORT_BRIDGE_4,
-        SMD_PORT_BRIDGE_5,
-        SMD_PORT_LOOPBACK,
-        SMD_PORT_CS_APPS_MODEM,
-        SMD_PORT_CS_APPS_DSP,
-        SMD_PORT_CS_MODEM_DSP,
-        SMD_NUM_PORTS,
-} smd_port_id_type;
-#endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
deleted file mode 100644
index ef55868a5b8a..000000000000
--- a/arch/arm/mach-msm/include/mach/sirc.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MSM_SIRC_H
-#define __ASM_ARCH_MSM_SIRC_H
-struct sirc_regs_t {
-        void    *int_enable;
-        void    *int_enable_clear;
-        void    *int_enable_set;
-        void    *int_type;
-        void    *int_polarity;
-        void    *int_clear;
-};
-struct sirc_cascade_regs {
-        void    *int_status;
-        unsigned int    cascade_irq;
-};
-void msm_init_sirc(void);
-void msm_sirc_enter_sleep(void);
-void msm_sirc_exit_sleep(void);
-#if defined(CONFIG_ARCH_MSM_SCORPION)
-#include <mach/msm_iomap.h>
-/*
- * Secondary interrupt controller interrupts
- */
-#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
-#define INT_UART1                     (FIRST_SIRC_IRQ + 0)
-#define INT_UART2                     (FIRST_SIRC_IRQ + 1)
-#define INT_UART3                     (FIRST_SIRC_IRQ + 2)
-#define INT_UART1_RX                  (FIRST_SIRC_IRQ + 3)
-#define INT_UART2_RX                  (FIRST_SIRC_IRQ + 4)
-#define INT_UART3_RX                  (FIRST_SIRC_IRQ + 5)
-#define INT_SPI_INPUT                 (FIRST_SIRC_IRQ + 6)
-#define INT_SPI_OUTPUT                (FIRST_SIRC_IRQ + 7)
-#define INT_SPI_ERROR                 (FIRST_SIRC_IRQ + 8)
-#define INT_GPIO_GROUP1               (FIRST_SIRC_IRQ + 9)
-#define INT_GPIO_GROUP2               (FIRST_SIRC_IRQ + 10)
-#define INT_GPIO_GROUP1_SECURE        (FIRST_SIRC_IRQ + 11)
-#define INT_GPIO_GROUP2_SECURE        (FIRST_SIRC_IRQ + 12)
-#define INT_AVS_SVIC                  (FIRST_SIRC_IRQ + 13)
-#define INT_AVS_REQ_UP                (FIRST_SIRC_IRQ + 14)
-#define INT_AVS_REQ_DOWN              (FIRST_SIRC_IRQ + 15)
-#define INT_PBUS_ERR                  (FIRST_SIRC_IRQ + 16)
-#define INT_AXI_ERR                   (FIRST_SIRC_IRQ + 17)
-#define INT_SMI_ERR                   (FIRST_SIRC_IRQ + 18)
-#define INT_EBI1_ERR                  (FIRST_SIRC_IRQ + 19)
-#define INT_IMEM_ERR                  (FIRST_SIRC_IRQ + 20)
-#define INT_TEMP_SENSOR               (FIRST_SIRC_IRQ + 21)
-#define INT_TV_ENC                    (FIRST_SIRC_IRQ + 22)
-#define INT_GRP2D                     (FIRST_SIRC_IRQ + 23)
-#define INT_GSBI_QUP                  (FIRST_SIRC_IRQ + 24)
-#define INT_SC_ACG                    (FIRST_SIRC_IRQ + 25)
-#define INT_WDT0                      (FIRST_SIRC_IRQ + 26)
-#define INT_WDT1                      (FIRST_SIRC_IRQ + 27)
-#if defined(CONFIG_MSM_SOC_REV_A)
-#define NR_SIRC_IRQS                  28
-#define SIRC_MASK                     0x0FFFFFFF
-#else
-#define NR_SIRC_IRQS                  23
-#define SIRC_MASK                     0x007FFFFF
-#endif
-#define LAST_SIRC_IRQ                 (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
-#define SPSS_SIRC_INT_SELECT          (MSM_SIRC_BASE + 0x00)
-#define SPSS_SIRC_INT_ENABLE          (MSM_SIRC_BASE + 0x04)
-#define SPSS_SIRC_INT_ENABLE_CLEAR    (MSM_SIRC_BASE + 0x08)
-#define SPSS_SIRC_INT_ENABLE_SET      (MSM_SIRC_BASE + 0x0C)
-#define SPSS_SIRC_INT_TYPE            (MSM_SIRC_BASE + 0x10)
-#define SPSS_SIRC_INT_POLARITY        (MSM_SIRC_BASE + 0x14)
-#define SPSS_SIRC_SECURITY            (MSM_SIRC_BASE + 0x18)
-#define SPSS_SIRC_IRQ_STATUS          (MSM_SIRC_BASE + 0x1C)
-#define SPSS_SIRC_IRQ1_STATUS         (MSM_SIRC_BASE + 0x20)
-#define SPSS_SIRC_RAW_STATUS          (MSM_SIRC_BASE + 0x24)
-#define SPSS_SIRC_INT_CLEAR           (MSM_SIRC_BASE + 0x28)
-#define SPSS_SIRC_SOFT_INT            (MSM_SIRC_BASE + 0x2C)
-#endif
-#endif
diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h
deleted file mode 100644
index 6626e7864e28..000000000000
--- a/arch/arm/mach-msm/include/mach/vreg.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/arch-msm/vreg.h
- *
- * Copyright (C) 2008 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_MSM_VREG_H
-#define __ARCH_ARM_MACH_MSM_VREG_H
-struct vreg;
-struct vreg *vreg_get(struct device *dev, const char *id);
-void vreg_put(struct vreg *vreg);
-int vreg_enable(struct vreg *vreg);
-int vreg_disable(struct vreg *vreg);
-int vreg_set_level(struct vreg *vreg, unsigned mv);
-#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
deleted file mode 100644
index b042dca1f633..000000000000
--- a/arch/arm/mach-msm/io.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* arch/arm/mach-msm/io.c
- *
- * MSM7K, QSD io support
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/bug.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <mach/msm_iomap.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                          \
-                .virtual = (unsigned long) MSM_##name##_BASE, \
-                .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
-                .length = chip##_##name##_SIZE, \
-                .type = mem_type, \
-         }
-#define MSM_DEVICE_TYPE(name, mem_type) \
-                MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
-#define MSM_CHIP_DEVICE(name, chip) \
-                MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
-#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
-#if defined(CONFIG_ARCH_MSM7X00A)
-static struct map_desc msm_io_desc[] __initdata = {
-        MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
-        {
-                .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
-                .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
-                .length =   MSM_SHARED_RAM_SIZE,
-                .type =     MT_DEVICE,
-        },
-#if defined(CONFIG_DEBUG_MSM_UART)
-        {
-                /* Must be last: virtual and pfn filled in by debug_ll_addr() */
-                .length = SZ_4K,
-                .type = MT_DEVICE_NONSHARED,
-        }
-#endif
-};
-void __init msm_map_common_io(void)
-{
-        size_t size = ARRAY_SIZE(msm_io_desc);
-        /* Make sure the peripheral register window is closed, since
-         * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
-         * pages are peripheral interface or not.
-         */
-        asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
-#if defined(CONFIG_DEBUG_MSM_UART)
-#ifdef CONFIG_MMU
-        debug_ll_addr(&msm_io_desc[size - 1].pfn,
-                      &msm_io_desc[size - 1].virtual);
-#endif
-        msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
-#endif
-        iotable_init(msm_io_desc, size);
-}
-#endif
-#ifdef CONFIG_ARCH_QSD8X50
-static struct map_desc qsd8x50_io_desc[] __initdata = {
-        MSM_DEVICE(VIC),
-        MSM_CHIP_DEVICE(CSR, QSD8X50),
-        MSM_DEVICE(DMOV),
-        MSM_CHIP_DEVICE(GPIO1, QSD8X50),
-        MSM_CHIP_DEVICE(GPIO2, QSD8X50),
-        MSM_DEVICE(CLK_CTL),
-        MSM_DEVICE(SIRC),
-        MSM_DEVICE(SCPLL),
-        MSM_DEVICE(AD5),
-        MSM_DEVICE(MDC),
-        {
-                .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
-                .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
-                .length =   MSM_SHARED_RAM_SIZE,
-                .type =     MT_DEVICE,
-        },
-};
-void __init msm_map_qsd8x50_io(void)
-{
-        debug_ll_io_init();
-        iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
-}
-#endif /* CONFIG_ARCH_QSD8X50 */
-#ifdef CONFIG_ARCH_MSM7X30
-static struct map_desc msm7x30_io_desc[] __initdata = {
-        MSM_DEVICE(VIC),
-        MSM_CHIP_DEVICE(CSR, MSM7X30),
-        MSM_DEVICE(DMOV),
-        MSM_CHIP_DEVICE(GPIO1, MSM7X30),
-        MSM_CHIP_DEVICE(GPIO2, MSM7X30),
-        MSM_DEVICE(CLK_CTL),
-        MSM_DEVICE(CLK_CTL_SH2),
-        MSM_DEVICE(AD5),
-        MSM_DEVICE(MDC),
-        MSM_DEVICE(ACC),
-        MSM_DEVICE(SAW),
-        MSM_DEVICE(GCC),
-        MSM_DEVICE(TCSR),
-        {
-                .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
-                .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
-                .length =   MSM_SHARED_RAM_SIZE,
-                .type =     MT_DEVICE,
-        },
-};
-void __init msm_map_msm7x30_io(void)
-{
-        debug_ll_io_init();
-        iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
-}
-#endif /* CONFIG_ARCH_MSM7X30 */
-#ifdef CONFIG_ARCH_MSM7X00A
-void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
-                                   unsigned int mtype, void *caller)
-{
-        if (mtype == MT_DEVICE) {
-                /* The peripherals in the 88000000 - D0000000 range
-                 * are only accessible by type MT_DEVICE_NONSHARED.
-                 * Adjust mtype as necessary to make this "just work."
-                 */
-                if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
-                        mtype = MT_DEVICE_NONSHARED;
-        }
-        return __arm_ioremap_caller(phys_addr, size, mtype, caller);
-}
-#endif
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
deleted file mode 100644
index 1b54f807c2d0..000000000000
--- a/arch/arm/mach-msm/irq-vic.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-#include <linux/timer.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-#include <mach/msm_iomap.h>
-#include "smd_private.h"
-enum {
-        IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
-        IRQ_DEBUG_SLEEP_INT = 1U << 1,
-        IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
-        IRQ_DEBUG_SLEEP = 1U << 3,
-        IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
-};
-static int msm_irq_debug_mask;
-module_param_named(debug_mask, msm_irq_debug_mask, int,
-                   S_IRUGO | S_IWUSR | S_IWGRP);
-#define VIC_REG(off) (MSM_VIC_BASE + (off))
-#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
-#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
-#define VIC_INT_SELECT0     VIC_REG(0x0000)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT1     VIC_REG(0x0004)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT2     VIC_REG(0x0008)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT3     VIC_REG(0x000C)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_EN0         VIC_REG(0x0010)
-#define VIC_INT_EN1         VIC_REG(0x0014)
-#define VIC_INT_EN2         VIC_REG(0x0018)
-#define VIC_INT_EN3         VIC_REG(0x001C)
-#define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
-#define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
-#define VIC_INT_ENCLEAR2    VIC_REG(0x0028)
-#define VIC_INT_ENCLEAR3    VIC_REG(0x002C)
-#define VIC_INT_ENSET0      VIC_REG(0x0030)
-#define VIC_INT_ENSET1      VIC_REG(0x0034)
-#define VIC_INT_ENSET2      VIC_REG(0x0038)
-#define VIC_INT_ENSET3      VIC_REG(0x003C)
-#define VIC_INT_TYPE0       VIC_REG(0x0040)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_TYPE1       VIC_REG(0x0044)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_TYPE2       VIC_REG(0x0048)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_TYPE3       VIC_REG(0x004C)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_POLARITY0   VIC_REG(0x0050)  /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY1   VIC_REG(0x0054)  /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY2   VIC_REG(0x0058)  /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY3   VIC_REG(0x005C)  /* 1: NEG, 0: POS */
-#define VIC_NO_PEND_VAL     VIC_REG(0x0060)
-#if defined(CONFIG_ARCH_MSM_SCORPION)
-#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
-#define VIC_INT_MASTEREN    VIC_REG(0x0068)  /* 1: IRQ, 2: FIQ     */
-#define VIC_CONFIG          VIC_REG(0x006C)  /* 1: USE SC VIC */
-#else
-#define VIC_INT_MASTEREN    VIC_REG(0x0064)  /* 1: IRQ, 2: FIQ     */
-#define VIC_PROTECTION      VIC_REG(0x006C)  /* 1: ENABLE          */
-#define VIC_CONFIG          VIC_REG(0x0068)  /* 1: USE ARM1136 VIC */
-#endif
-#define VIC_IRQ_STATUS0     VIC_REG(0x0080)
-#define VIC_IRQ_STATUS1     VIC_REG(0x0084)
-#define VIC_IRQ_STATUS2     VIC_REG(0x0088)
-#define VIC_IRQ_STATUS3     VIC_REG(0x008C)
-#define VIC_FIQ_STATUS0     VIC_REG(0x0090)
-#define VIC_FIQ_STATUS1     VIC_REG(0x0094)
-#define VIC_FIQ_STATUS2     VIC_REG(0x0098)
-#define VIC_FIQ_STATUS3     VIC_REG(0x009C)
-#define VIC_RAW_STATUS0     VIC_REG(0x00A0)
-#define VIC_RAW_STATUS1     VIC_REG(0x00A4)
-#define VIC_RAW_STATUS2     VIC_REG(0x00A8)
-#define VIC_RAW_STATUS3     VIC_REG(0x00AC)
-#define VIC_INT_CLEAR0      VIC_REG(0x00B0)
-#define VIC_INT_CLEAR1      VIC_REG(0x00B4)
-#define VIC_INT_CLEAR2      VIC_REG(0x00B8)
-#define VIC_INT_CLEAR3      VIC_REG(0x00BC)
-#define VIC_SOFTINT0        VIC_REG(0x00C0)
-#define VIC_SOFTINT1        VIC_REG(0x00C4)
-#define VIC_SOFTINT2        VIC_REG(0x00C8)
-#define VIC_SOFTINT3        VIC_REG(0x00CC)
-#define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)  /* pending int # */
-#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)  /* pending vector addr */
-#define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)
-#if defined(CONFIG_ARCH_MSM_SCORPION)
-#define VIC_FIQ_VEC_RD      VIC_REG(0x00DC)
-#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
-#define VIC_FIQ_VEC_WR      VIC_REG(0x00E4)
-#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E8)
-#define VIC_IRQ_IN_STACK    VIC_REG(0x00EC)
-#define VIC_FIQ_IN_SERVICE  VIC_REG(0x00F0)
-#define VIC_FIQ_IN_STACK    VIC_REG(0x00F4)
-#define VIC_TEST_BUS_SEL    VIC_REG(0x00F8)
-#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
-#else
-#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E0)
-#define VIC_IRQ_IN_STACK    VIC_REG(0x00E4)
-#define VIC_TEST_BUS_SEL    VIC_REG(0x00E8)
-#endif
-#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
-#define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))
-#if defined(CONFIG_ARCH_MSM7X30)
-#define VIC_NUM_REGS        4
-#else
-#define VIC_NUM_REGS        2
-#endif
-#if VIC_NUM_REGS == 2
-#define DPRINT_REGS(base_reg, format, ...)                              \
-        printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__,              \
-                        readl(base_reg ## 0), readl(base_reg ## 1))
-#define DPRINT_ARRAY(array, format, ...)                                \
-        printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__,              \
-                        array[0], array[1])
-#elif VIC_NUM_REGS == 4
-#define DPRINT_REGS(base_reg, format, ...) \
-        printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__,        \
-                        readl(base_reg ## 0), readl(base_reg ## 1),     \
-                        readl(base_reg ## 2), readl(base_reg ## 3))
-#define DPRINT_ARRAY(array, format, ...)                                \
-        printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__,        \
-                        array[0], array[1],                             \
-                        array[2], array[3])
-#else
-#error "VIC_NUM_REGS set to illegal value"
-#endif
-static uint32_t msm_irq_smsm_wake_enable[2];
-static struct {
-        uint32_t int_en[2];
-        uint32_t int_type;
-        uint32_t int_polarity;
-        uint32_t int_select;
-} msm_irq_shadow_reg[VIC_NUM_REGS];
-static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
-#define SMSM_FAKE_IRQ (0xff)
-static uint8_t msm_irq_to_smsm[NR_IRQS] = {
-        [INT_MDDI_EXT] = 1,
-        [INT_MDDI_PRI] = 2,
-        [INT_MDDI_CLIENT] = 3,
-        [INT_USB_OTG] = 4,
-        [INT_PWB_I2C] = 5,
-        [INT_SDC1_0] = 6,
-        [INT_SDC1_1] = 7,
-        [INT_SDC2_0] = 8,
-        [INT_SDC2_1] = 9,
-        [INT_ADSP_A9_A11] = 10,
-        [INT_UART1] = 11,
-        [INT_UART2] = 12,
-        [INT_UART3] = 13,
-        [INT_UART1_RX] = 14,
-        [INT_UART2_RX] = 15,
-        [INT_UART3_RX] = 16,
-        [INT_UART1DM_IRQ] = 17,
-        [INT_UART1DM_RX] = 18,
-        [INT_KEYSENSE] = 19,
-#if !defined(CONFIG_ARCH_MSM7X30)
-        [INT_AD_HSSD] = 20,
-#endif
-        [INT_NAND_WR_ER_DONE] = 21,
-        [INT_NAND_OP_DONE] = 22,
-        [INT_TCHSCRN1] = 23,
-        [INT_TCHSCRN2] = 24,
-        [INT_TCHSCRN_SSBI] = 25,
-        [INT_USB_HS] = 26,
-        [INT_UART2DM_RX] = 27,
-        [INT_UART2DM_IRQ] = 28,
-        [INT_SDC4_1] = 29,
-        [INT_SDC4_0] = 30,
-        [INT_SDC3_1] = 31,
-        [INT_SDC3_0] = 32,
-        /* fake wakeup interrupts */
-        [INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
-        [INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
-        [INT_A9_M2A_0] = SMSM_FAKE_IRQ,
-        [INT_A9_M2A_1] = SMSM_FAKE_IRQ,
-        [INT_A9_M2A_5] = SMSM_FAKE_IRQ,
-        [INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
-        [INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
-        [INT_ADSP_A11] = SMSM_FAKE_IRQ,
-#ifdef CONFIG_ARCH_QSD8X50
-        [INT_SIRC_0] = SMSM_FAKE_IRQ,
-        [INT_SIRC_1] = SMSM_FAKE_IRQ,
-#endif
-};
-static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
-{
-        int i;
-        for (i = 0; i < VIC_NUM_REGS; i++)
-                writel(val, base + (i * 4));
-}
-static void msm_irq_ack(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq);
-        writel(1 << (d->irq & 31), reg);
-}
-static void msm_irq_mask(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
-        uint32_t mask = 1UL << (d->irq & 31);
-        int smsm_irq = msm_irq_to_smsm[d->irq];
-        msm_irq_shadow_reg[index].int_en[0] &= ~mask;
-        writel(mask, reg);
-        if (smsm_irq == 0)
-                msm_irq_idle_disable[index] &= ~mask;
-        else {
-                mask = 1UL << (smsm_irq - 1);
-                msm_irq_smsm_wake_enable[0] &= ~mask;
-        }
-}
-static void msm_irq_unmask(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
-        uint32_t mask = 1UL << (d->irq & 31);
-        int smsm_irq = msm_irq_to_smsm[d->irq];
-        msm_irq_shadow_reg[index].int_en[0] |= mask;
-        writel(mask, reg);
-        if (smsm_irq == 0)
-                msm_irq_idle_disable[index] |= mask;
-        else {
-                mask = 1UL << (smsm_irq - 1);
-                msm_irq_smsm_wake_enable[0] |= mask;
-        }
-}
-static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
-        uint32_t mask = 1UL << (d->irq & 31);
-        int smsm_irq = msm_irq_to_smsm[d->irq];
-        if (smsm_irq == 0) {
-                printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq);
-                return -EINVAL;
-        }
-        if (on)
-                msm_irq_shadow_reg[index].int_en[1] |= mask;
-        else
-                msm_irq_shadow_reg[index].int_en[1] &= ~mask;
-        if (smsm_irq == SMSM_FAKE_IRQ)
-                return 0;
-        mask = 1UL << (smsm_irq - 1);
-        if (on)
-                msm_irq_smsm_wake_enable[1] |= mask;
-        else
-                msm_irq_smsm_wake_enable[1] &= ~mask;
-        return 0;
-}
-static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq);
-        void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
-        int b = 1 << (d->irq & 31);
-        uint32_t polarity;
-        uint32_t type;
-        polarity = msm_irq_shadow_reg[index].int_polarity;
-        if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
-                polarity |= b;
-        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
-                polarity &= ~b;
-        writel(polarity, preg);
-        msm_irq_shadow_reg[index].int_polarity = polarity;
-        type = msm_irq_shadow_reg[index].int_type;
-        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
-                type |= b;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-        }
-        if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
-                type &= ~b;
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        }
-        writel(type, treg);
-        msm_irq_shadow_reg[index].int_type = type;
-        return 0;
-}
-static struct irq_chip msm_irq_chip = {
-        .name          = "msm",
-        .irq_disable   = msm_irq_mask,
-        .irq_ack       = msm_irq_ack,
-        .irq_mask      = msm_irq_mask,
-        .irq_unmask    = msm_irq_unmask,
-        .irq_set_wake  = msm_irq_set_wake,
-        .irq_set_type  = msm_irq_set_type,
-};
-void __init msm_init_irq(void)
-{
-        unsigned n;
-        /* select level interrupts */
-        msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
-        /* select highlevel interrupts */
-        msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
-        /* select IRQ for all INTs */
-        msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
-        /* disable all INTs */
-        msm_irq_write_all_regs(VIC_INT_EN0, 0);
-        /* don't use vic */
-        writel(0, VIC_CONFIG);
-        /* enable interrupt controller */
-        writel(3, VIC_INT_MASTEREN);
-        for (n = 0; n < NR_MSM_IRQS; n++) {
-                irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
-                set_irq_flags(n, IRQF_VALID);
-        }
-}
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
deleted file mode 100644
index ea514be390c6..000000000000
--- a/arch/arm/mach-msm/irq.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* linux/arch/arm/mach-msm/irq.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-#include <linux/timer.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/msm_iomap.h>
-#define VIC_REG(off) (MSM_VIC_BASE + (off))
-#define VIC_INT_SELECT0     VIC_REG(0x0000)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_SELECT1     VIC_REG(0x0004)  /* 1: FIQ, 0: IRQ */
-#define VIC_INT_EN0         VIC_REG(0x0010)
-#define VIC_INT_EN1         VIC_REG(0x0014)
-#define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
-#define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
-#define VIC_INT_ENSET0      VIC_REG(0x0030)
-#define VIC_INT_ENSET1      VIC_REG(0x0034)
-#define VIC_INT_TYPE0       VIC_REG(0x0040)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_TYPE1       VIC_REG(0x0044)  /* 1: EDGE, 0: LEVEL  */
-#define VIC_INT_POLARITY0   VIC_REG(0x0050)  /* 1: NEG, 0: POS */
-#define VIC_INT_POLARITY1   VIC_REG(0x0054)  /* 1: NEG, 0: POS */
-#define VIC_NO_PEND_VAL     VIC_REG(0x0060)
-#define VIC_INT_MASTEREN    VIC_REG(0x0064)  /* 1: IRQ, 2: FIQ     */
-#define VIC_PROTECTION      VIC_REG(0x006C)  /* 1: ENABLE          */
-#define VIC_CONFIG          VIC_REG(0x0068)  /* 1: USE ARM1136 VIC */
-#define VIC_IRQ_STATUS0     VIC_REG(0x0080)
-#define VIC_IRQ_STATUS1     VIC_REG(0x0084)
-#define VIC_FIQ_STATUS0     VIC_REG(0x0090)
-#define VIC_FIQ_STATUS1     VIC_REG(0x0094)
-#define VIC_RAW_STATUS0     VIC_REG(0x00A0)
-#define VIC_RAW_STATUS1     VIC_REG(0x00A4)
-#define VIC_INT_CLEAR0      VIC_REG(0x00B0)
-#define VIC_INT_CLEAR1      VIC_REG(0x00B4)
-#define VIC_SOFTINT0        VIC_REG(0x00C0)
-#define VIC_SOFTINT1        VIC_REG(0x00C4)
-#define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)  /* pending int # */
-#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)  /* pending vector addr */
-#define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)
-#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E0)
-#define VIC_IRQ_IN_STACK    VIC_REG(0x00E4)
-#define VIC_TEST_BUS_SEL    VIC_REG(0x00E8)
-#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
-#define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))
-static void msm_irq_ack(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
-        writel(1 << (d->irq & 31), reg);
-}
-static void msm_irq_mask(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
-        writel(1 << (d->irq & 31), reg);
-}
-static void msm_irq_unmask(struct irq_data *d)
-{
-        void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
-        writel(1 << (d->irq & 31), reg);
-}
-static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        return -EINVAL;
-}
-static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
-        void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
-        int b = 1 << (d->irq & 31);
-        if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
-                writel(readl(preg) | b, preg);
-        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
-                writel(readl(preg) & (~b), preg);
-        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
-                writel(readl(treg) | b, treg);
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-        }
-        if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
-                writel(readl(treg) & (~b), treg);
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        }
-        return 0;
-}
-static struct irq_chip msm_irq_chip = {
-        .name          = "msm",
-        .irq_ack       = msm_irq_ack,
-        .irq_mask      = msm_irq_mask,
-        .irq_unmask    = msm_irq_unmask,
-        .irq_set_wake  = msm_irq_set_wake,
-        .irq_set_type  = msm_irq_set_type,
-};
-void __init msm_init_irq(void)
-{
-        unsigned n;
-        /* select level interrupts */
-        writel(0, VIC_INT_TYPE0);
-        writel(0, VIC_INT_TYPE1);
-        /* select highlevel interrupts */
-        writel(0, VIC_INT_POLARITY0);
-        writel(0, VIC_INT_POLARITY1);
-        /* select IRQ for all INTs */
-        writel(0, VIC_INT_SELECT0);
-        writel(0, VIC_INT_SELECT1);
-        /* disable all INTs */
-        writel(0, VIC_INT_EN0);
-        writel(0, VIC_INT_EN1);
-        /* don't use 1136 vic */
-        writel(0, VIC_CONFIG);
-        /* enable interrupt controller */
-        writel(1, VIC_INT_MASTEREN);
-        for (n = 0; n < NR_MSM_IRQS; n++) {
-                irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
-                set_irq_flags(n, IRQF_VALID);
-        }
-}
diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c
deleted file mode 100644
index 9c392a29fc7e..000000000000
--- a/arch/arm/mach-msm/last_radio_log.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* arch/arm/mach-msm/last_radio_log.c
- *
- * Extract the log from a modem crash though SMEM
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/proc_fs.h>
-#include <linux/uaccess.h>
-#include "smd_private.h"
-static void *radio_log_base;
-static size_t radio_log_size;
-extern void *smem_item(unsigned id, unsigned *size);
-static ssize_t last_radio_log_read(struct file *file, char __user *buf,
-                        size_t len, loff_t *offset)
-{
-        return simple_read_from_buffer(buf, len, offset,
-                                radio_log_base, radio_log_size);
-}
-static struct file_operations last_radio_log_fops = {
-        .read = last_radio_log_read,
-        .llseek = default_llseek,
-};
-void msm_init_last_radio_log(struct module *owner)
-{
-        struct proc_dir_entry *entry;
-        if (last_radio_log_fops.owner) {
-                pr_err("%s: already claimed\n", __func__);
-                return;
-        }
-        radio_log_base = smem_item(SMEM_CLKREGIM_BSP, &radio_log_size);
-        if (!radio_log_base) {
-                pr_err("%s: could not retrieve SMEM_CLKREGIM_BSP\n", __func__);
-                return;
-        }
-        entry = proc_create("last_radio_log", S_IRUGO, NULL,
-                                &last_radio_log_fops);
-        if (!entry) {
-                pr_err("%s: could not create proc entry for radio log\n",
-                                __func__);
-                return;
-        }
-        pr_err("%s: last radio log is %d bytes long\n", __func__,
-                radio_log_size);
-        last_radio_log_fops.owner = owner;
-        proc_set_size(entry, radio_log_size);
-}
-EXPORT_SYMBOL(msm_init_last_radio_log);
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
deleted file mode 100644
index 507f5ca80697..000000000000
--- a/arch/arm/mach-msm/proc_comm.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* arch/arm/mach-msm/proc_comm.c
- *
- * Copyright (C) 2007-2008 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <mach/msm_iomap.h>
-#include "proc_comm.h"
-static inline void msm_a2m_int(uint32_t irq)
-{
-#if defined(CONFIG_ARCH_MSM7X30)
-        writel(1 << irq, MSM_GCC_BASE + 0x8);
-#else
-        writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
-#endif
-}
-static inline void notify_other_proc_comm(void)
-{
-        msm_a2m_int(6);
-}
-#define APP_COMMAND 0x00
-#define APP_STATUS  0x04
-#define APP_DATA1   0x08
-#define APP_DATA2   0x0C
-#define MDM_COMMAND 0x10
-#define MDM_STATUS  0x14
-#define MDM_DATA1   0x18
-#define MDM_DATA2   0x1C
-static DEFINE_SPINLOCK(proc_comm_lock);
-/* The higher level SMD support will install this to
- * provide a way to check for and handle modem restart.
- */
-int (*msm_check_for_modem_crash)(void);
-/* Poll for a state change, checking for possible
- * modem crashes along the way (so we don't wait
- * forever while the ARM9 is blowing up).
- *
- * Return an error in the event of a modem crash and
- * restart so the msm_proc_comm() routine can restart
- * the operation from the beginning.
- */
-static int proc_comm_wait_for(void __iomem *addr, unsigned value)
-{
-        for (;;) {
-                if (readl(addr) == value)
-                        return 0;
-                if (msm_check_for_modem_crash)
-                        if (msm_check_for_modem_crash())
-                                return -EAGAIN;
-        }
-}
-int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
-{
-        void __iomem *base = MSM_SHARED_RAM_BASE;
-        unsigned long flags;
-        int ret;
-        spin_lock_irqsave(&proc_comm_lock, flags);
-        for (;;) {
-                if (proc_comm_wait_for(base + MDM_STATUS, PCOM_READY))
-                        continue;
-                writel(cmd, base + APP_COMMAND);
-                writel(data1 ? *data1 : 0, base + APP_DATA1);
-                writel(data2 ? *data2 : 0, base + APP_DATA2);
-                notify_other_proc_comm();
-                if (proc_comm_wait_for(base + APP_COMMAND, PCOM_CMD_DONE))
-                        continue;
-                if (readl(base + APP_STATUS) != PCOM_CMD_FAIL) {
-                        if (data1)
-                                *data1 = readl(base + APP_DATA1);
-                        if (data2)
-                                *data2 = readl(base + APP_DATA2);
-                        ret = 0;
-                } else {
-                        ret = -EIO;
-                }
-                break;
-        }
-        writel(PCOM_CMD_IDLE, base + APP_COMMAND);
-        spin_unlock_irqrestore(&proc_comm_lock, flags);
-        return ret;
-}
-/*
- * We need to wait for the ARM9 to at least partially boot
- * up before we can continue. Since the ARM9 does resource
- * allocation, if we dont' wait we could end up crashing or in
- * and unknown state. This function should be called early to
- * wait on the ARM9.
- */
-void proc_comm_boot_wait(void)
-{
-        void __iomem *base = MSM_SHARED_RAM_BASE;
- 
-        proc_comm_wait_for(base + MDM_STATUS, PCOM_READY);
- 
-}
diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h
deleted file mode 100644
index e8d043a0e990..000000000000
--- a/arch/arm/mach-msm/proc_comm.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* arch/arm/mach-msm/proc_comm.h
- *
- * Copyright (c) 2007 QUALCOMM Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _ARCH_ARM_MACH_MSM_PROC_COMM_H_
-#define _ARCH_ARM_MACH_MSM_PROC_COMM_H_
-#include <linux/init.h>
-enum {
-        PCOM_CMD_IDLE = 0x0,
-        PCOM_CMD_DONE,
-        PCOM_RESET_APPS,
-        PCOM_RESET_CHIP,
-        PCOM_CONFIG_NAND_MPU,
-        PCOM_CONFIG_USB_CLKS,
-        PCOM_GET_POWER_ON_STATUS,
-        PCOM_GET_WAKE_UP_STATUS,
-        PCOM_GET_BATT_LEVEL,
-        PCOM_CHG_IS_CHARGING,
-        PCOM_POWER_DOWN,
-        PCOM_USB_PIN_CONFIG,
-        PCOM_USB_PIN_SEL,
-        PCOM_SET_RTC_ALARM,
-        PCOM_NV_READ,
-        PCOM_NV_WRITE,
-        PCOM_GET_UUID_HIGH,
-        PCOM_GET_UUID_LOW,
-        PCOM_GET_HW_ENTROPY,
-        PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
-        PCOM_CLKCTL_RPC_ENABLE,
-        PCOM_CLKCTL_RPC_DISABLE,
-        PCOM_CLKCTL_RPC_RESET,
-        PCOM_CLKCTL_RPC_SET_FLAGS,
-        PCOM_CLKCTL_RPC_SET_RATE,
-        PCOM_CLKCTL_RPC_MIN_RATE,
-        PCOM_CLKCTL_RPC_MAX_RATE,
-        PCOM_CLKCTL_RPC_RATE,
-        PCOM_CLKCTL_RPC_PLL_REQUEST,
-        PCOM_CLKCTL_RPC_ENABLED,
-        PCOM_VREG_SWITCH,
-        PCOM_VREG_SET_LEVEL,
-        PCOM_GPIO_TLMM_CONFIG_GROUP,
-        PCOM_GPIO_TLMM_UNCONFIG_GROUP,
-        PCOM_NV_WRITE_BYTES_4_7,
-        PCOM_CONFIG_DISP,
-        PCOM_GET_FTM_BOOT_COUNT,
-        PCOM_RPC_GPIO_TLMM_CONFIG_EX,
-        PCOM_PM_MPP_CONFIG,
-        PCOM_GPIO_IN,
-        PCOM_GPIO_OUT,
-        PCOM_RESET_MODEM,
-        PCOM_RESET_CHIP_IMM,
-        PCOM_PM_VID_EN,
-        PCOM_VREG_PULLDOWN,
-        PCOM_GET_MODEM_VERSION,
-        PCOM_CLK_REGIME_SEC_RESET,
-        PCOM_CLK_REGIME_SEC_RESET_ASSERT,
-        PCOM_CLK_REGIME_SEC_RESET_DEASSERT,
-        PCOM_CLK_REGIME_SEC_PLL_REQUEST_WRP,
-        PCOM_CLK_REGIME_SEC_ENABLE,
-        PCOM_CLK_REGIME_SEC_DISABLE,
-        PCOM_CLK_REGIME_SEC_IS_ON,
-        PCOM_CLK_REGIME_SEC_SEL_CLK_INV,
-        PCOM_CLK_REGIME_SEC_SEL_CLK_SRC,
-        PCOM_CLK_REGIME_SEC_SEL_CLK_DIV,
-        PCOM_CLK_REGIME_SEC_ICODEC_CLK_ENABLE,
-        PCOM_CLK_REGIME_SEC_ICODEC_CLK_DISABLE,
-        PCOM_CLK_REGIME_SEC_SEL_SPEED,
-        PCOM_CLK_REGIME_SEC_CONFIG_GP_CLK_WRP,
-        PCOM_CLK_REGIME_SEC_CONFIG_MDH_CLK_WRP,
-        PCOM_CLK_REGIME_SEC_USB_XTAL_ON,
-        PCOM_CLK_REGIME_SEC_USB_XTAL_OFF,
-        PCOM_CLK_REGIME_SEC_SET_QDSP_DME_MODE,
-        PCOM_CLK_REGIME_SEC_SWITCH_ADSP_CLK,
-        PCOM_CLK_REGIME_SEC_GET_MAX_ADSP_CLK_KHZ,
-        PCOM_CLK_REGIME_SEC_GET_I2C_CLK_KHZ,
-        PCOM_CLK_REGIME_SEC_MSM_GET_CLK_FREQ_KHZ,
-        PCOM_CLK_REGIME_SEC_SEL_VFE_SRC,
-        PCOM_CLK_REGIME_SEC_MSM_SEL_CAMCLK,
-        PCOM_CLK_REGIME_SEC_MSM_SEL_LCDCLK,
-        PCOM_CLK_REGIME_SEC_VFE_RAIL_OFF,
-        PCOM_CLK_REGIME_SEC_VFE_RAIL_ON,
-        PCOM_CLK_REGIME_SEC_GRP_RAIL_OFF,
-        PCOM_CLK_REGIME_SEC_GRP_RAIL_ON,
-        PCOM_CLK_REGIME_SEC_VDC_RAIL_OFF,
-        PCOM_CLK_REGIME_SEC_VDC_RAIL_ON,
-        PCOM_CLK_REGIME_SEC_LCD_CTRL,
-        PCOM_CLK_REGIME_SEC_REGISTER_FOR_CPU_RESOURCE,
-        PCOM_CLK_REGIME_SEC_DEREGISTER_FOR_CPU_RESOURCE,
-        PCOM_CLK_REGIME_SEC_RESOURCE_REQUEST_WRP,
-        PCOM_CLK_REGIME_MSM_SEC_SEL_CLK_OWNER,
-        PCOM_CLK_REGIME_SEC_DEVMAN_REQUEST_WRP,
-        PCOM_GPIO_CONFIG,
-        PCOM_GPIO_CONFIGURE_GROUP,
-        PCOM_GPIO_TLMM_SET_PORT,
-        PCOM_GPIO_TLMM_CONFIG_EX,
-        PCOM_SET_FTM_BOOT_COUNT,
-        PCOM_RESERVED0,
-        PCOM_RESERVED1,
-        PCOM_CUSTOMER_CMD1,
-        PCOM_CUSTOMER_CMD2,
-        PCOM_CUSTOMER_CMD3,
-        PCOM_CLK_REGIME_ENTER_APPSBL_CHG_MODE,
-        PCOM_CLK_REGIME_EXIT_APPSBL_CHG_MODE,
-        PCOM_CLK_REGIME_SEC_RAIL_DISABLE,
-        PCOM_CLK_REGIME_SEC_RAIL_ENABLE,
-        PCOM_CLK_REGIME_SEC_RAIL_CONTROL,
-        PCOM_SET_SW_WATCHDOG_STATE,
-        PCOM_PM_MPP_CONFIG_DIGITAL_INPUT,
-        PCOM_PM_MPP_CONFIG_I_SINK,
-        PCOM_RESERVED_101,
-        PCOM_MSM_HSUSB_PHY_RESET,
-        PCOM_GET_BATT_MV_LEVEL,
-        PCOM_CHG_USB_IS_PC_CONNECTED,
-        PCOM_CHG_USB_IS_CHARGER_CONNECTED,
-        PCOM_CHG_USB_IS_DISCONNECTED,
-        PCOM_CHG_USB_IS_AVAILABLE,
-        PCOM_CLK_REGIME_SEC_MSM_SEL_FREQ,
-        PCOM_CLK_REGIME_SEC_SET_PCLK_AXI_POLICY,
-        PCOM_CLKCTL_RPC_RESET_ASSERT,
-        PCOM_CLKCTL_RPC_RESET_DEASSERT,
-        PCOM_CLKCTL_RPC_RAIL_ON,
-        PCOM_CLKCTL_RPC_RAIL_OFF,
-        PCOM_CLKCTL_RPC_RAIL_ENABLE,
-        PCOM_CLKCTL_RPC_RAIL_DISABLE,
-        PCOM_CLKCTL_RPC_RAIL_CONTROL,
-        PCOM_CLKCTL_RPC_MIN_MSMC1,
-        PCOM_NUM_CMDS,
-};
-enum {
-        PCOM_INVALID_STATUS = 0x0,
-        PCOM_READY,
-        PCOM_CMD_RUNNING,
-        PCOM_CMD_SUCCESS,
-        PCOM_CMD_FAIL,
-        PCOM_CMD_FAIL_FALSE_RETURNED,
-        PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_SERVER,
-        PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_CLIENT,
-        PCOM_CMD_FAIL_CMD_UNREGISTERED,
-        PCOM_CMD_FAIL_CMD_LOCKED,
-        PCOM_CMD_FAIL_SERVER_NOT_YET_READY,
-        PCOM_CMD_FAIL_BAD_DESTINATION,
-        PCOM_CMD_FAIL_SERVER_RESET,
-        PCOM_CMD_FAIL_SMSM_NOT_INIT,
-        PCOM_CMD_FAIL_PROC_COMM_BUSY,
-        PCOM_CMD_FAIL_PROC_COMM_NOT_INIT,
-};
-/* List of VREGs that support the Pull Down Resistor setting. */
-enum vreg_pdown_id {
-        PM_VREG_PDOWN_MSMA_ID,
-        PM_VREG_PDOWN_MSMP_ID,
-        PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */
-        PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */
-        PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */
-        PM_VREG_PDOWN_GP3_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */
-        PM_VREG_PDOWN_GP4_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_GP1_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_TCXO_ID,
-        PM_VREG_PDOWN_PA_ID,
-        PM_VREG_PDOWN_RFTX_ID,
-        PM_VREG_PDOWN_RFRX1_ID,
-        PM_VREG_PDOWN_RFRX2_ID,
-        PM_VREG_PDOWN_SYNT_ID,
-        PM_VREG_PDOWN_WLAN_ID,
-        PM_VREG_PDOWN_USB_ID,
-        PM_VREG_PDOWN_MMC_ID,
-        PM_VREG_PDOWN_RUIM_ID,
-        PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */
-        PM_VREG_PDOWN_GP2_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_GP5_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_GP6_ID,   /* Supported in PM7500 only */
-        PM_VREG_PDOWN_RF_ID,
-        PM_VREG_PDOWN_RF_VCO_ID,
-        PM_VREG_PDOWN_MPLL_ID,
-        PM_VREG_PDOWN_S2_ID,
-        PM_VREG_PDOWN_S3_ID,
-        PM_VREG_PDOWN_RFUBM_ID,
-        /* new for HAN */
-        PM_VREG_PDOWN_RF1_ID,
-        PM_VREG_PDOWN_RF2_ID,
-        PM_VREG_PDOWN_RFA_ID,
-        PM_VREG_PDOWN_CDC2_ID,
-        PM_VREG_PDOWN_RFTX2_ID,
-        PM_VREG_PDOWN_USIM_ID,
-        PM_VREG_PDOWN_USB2P6_ID,
-        PM_VREG_PDOWN_USB3P3_ID,
-        PM_VREG_PDOWN_INVALID_ID,
-        /* backward compatible enums only */
-        PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID,
-        PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID,
-        PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID,
-        PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID,
-        PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID,
-        PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID,
-        PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID,
-        PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID,
-        PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID,
-        PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID,
-        PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID
-};
-enum {
-        PCOM_CLKRGM_APPS_RESET_USB_PHY  = 34,
-        PCOM_CLKRGM_APPS_RESET_USBH     = 37,
-};
-/* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */
-#define GPIO_ENABLE     0
-#define GPIO_DISABLE    1
-#define GPIO_INPUT      0
-#define GPIO_OUTPUT     1
-#define GPIO_NO_PULL    0
-#define GPIO_PULL_DOWN  1
-#define GPIO_KEEPER     2
-#define GPIO_PULL_UP    3
-#define GPIO_2MA        0
-#define GPIO_4MA        1
-#define GPIO_6MA        2
-#define GPIO_8MA        3
-#define GPIO_10MA       4
-#define GPIO_12MA       5
-#define GPIO_14MA       6
-#define GPIO_16MA       7
-#define PCOM_GPIO_CFG(gpio, func, dir, pull, drvstr) \
-                ((((gpio) & 0x3FF) << 4)        | \
-                ((func) & 0xf)                  | \
-                (((dir) & 0x1) << 14)           | \
-                (((pull) & 0x3) << 15)          | \
-                (((drvstr) & 0xF) << 17))
-int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
-void proc_comm_boot_wait(void);
-#endif
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
deleted file mode 100644
index 689e78c95f38..000000000000
--- a/arch/arm/mach-msm/sirc.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/irq.h>
-static unsigned int int_enable;
-static unsigned int wake_enable;
-static struct sirc_regs_t sirc_regs = {
-        .int_enable       = SPSS_SIRC_INT_ENABLE,
-        .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
-        .int_enable_set   = SPSS_SIRC_INT_ENABLE_SET,
-        .int_type         = SPSS_SIRC_INT_TYPE,
-        .int_polarity     = SPSS_SIRC_INT_POLARITY,
-        .int_clear        = SPSS_SIRC_INT_CLEAR,
-};
-static struct sirc_cascade_regs sirc_reg_table[] = {
-        {
-                .int_status  = SPSS_SIRC_IRQ_STATUS,
-                .cascade_irq = INT_SIRC_0,
-        }
-};
-/* Mask off the given interrupt. Keep the int_enable mask in sync with
-   the enable reg, so it can be restored after power collapse. */
-static void sirc_irq_mask(struct irq_data *d)
-{
-        unsigned int mask;
-        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
-        writel(mask, sirc_regs.int_enable_clear);
-        int_enable &= ~mask;
-        return;
-}
-/* Unmask the given interrupt. Keep the int_enable mask in sync with
-   the enable reg, so it can be restored after power collapse. */
-static void sirc_irq_unmask(struct irq_data *d)
-{
-        unsigned int mask;
-        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
-        writel(mask, sirc_regs.int_enable_set);
-        int_enable |= mask;
-        return;
-}
-static void sirc_irq_ack(struct irq_data *d)
-{
-        unsigned int mask;
-        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
-        writel(mask, sirc_regs.int_clear);
-        return;
-}
-static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        unsigned int mask;
-        /* Used to set the interrupt enable mask during power collapse. */
-        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
-        if (on)
-                wake_enable |= mask;
-        else
-                wake_enable &= ~mask;
-        return 0;
-}
-static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        unsigned int mask;
-        unsigned int val;
-        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
-        val = readl(sirc_regs.int_polarity);
-        if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
-                val |= mask;
-        else
-                val &= ~mask;
-        writel(val, sirc_regs.int_polarity);
-        val = readl(sirc_regs.int_type);
-        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
-                val |= mask;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-        } else {
-                val &= ~mask;
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        }
-        writel(val, sirc_regs.int_type);
-        return 0;
-}
-/* Finds the pending interrupt on the passed cascade irq and redrives it */
-static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int reg = 0;
-        unsigned int sirq;
-        unsigned int status;
-        while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
-                (sirc_reg_table[reg].cascade_irq != irq))
-                reg++;
-        status = readl(sirc_reg_table[reg].int_status);
-        status &= SIRC_MASK;
-        if (status == 0)
-                return;
-        for (sirq = 0;
-             (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
-             sirq++)
-                ;
-        generic_handle_irq(sirq+FIRST_SIRC_IRQ);
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-}
-static struct irq_chip sirc_irq_chip = {
-        .name          = "sirc",
-        .irq_ack       = sirc_irq_ack,
-        .irq_mask      = sirc_irq_mask,
-        .irq_unmask    = sirc_irq_unmask,
-        .irq_set_wake  = sirc_irq_set_wake,
-        .irq_set_type  = sirc_irq_set_type,
-};
-void __init msm_init_sirc(void)
-{
-        int i;
-        int_enable = 0;
-        wake_enable = 0;
-        for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
-                irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-        for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
-                irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
-                                        sirc_irq_handler);
-                irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
-        }
-        return;
-}
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
deleted file mode 100644
index 7550f5a08956..000000000000
--- a/arch/arm/mach-msm/smd.c
+++ /dev/null
@@ -1,1034 +0,0 @@
-/* arch/arm/mach-msm/smd.c
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/wait.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <mach/msm_smd.h>
-#include "smd_private.h"
-#include "proc_comm.h"
-#if defined(CONFIG_ARCH_QSD8X50)
-#define CONFIG_QDSP6 1
-#endif
-#define MODULE_NAME "msm_smd"
-enum {
-        MSM_SMD_DEBUG = 1U << 0,
-        MSM_SMSM_DEBUG = 1U << 0,
-};
-static int msm_smd_debug_mask;
-struct shared_info {
-        int ready;
-        void __iomem *state;
-};
-static unsigned dummy_state[SMSM_STATE_COUNT];
-static struct shared_info smd_info = {
-        /* FIXME: not a real __iomem pointer */
-        .state = &dummy_state,
-};
-module_param_named(debug_mask, msm_smd_debug_mask,
-                   int, S_IRUGO | S_IWUSR | S_IWGRP);
-static unsigned last_heap_free = 0xffffffff;
-static inline void notify_other_smsm(void)
-{
-        msm_a2m_int(5);
-#ifdef CONFIG_QDSP6
-        msm_a2m_int(8);
-#endif
-}
-static inline void notify_modem_smd(void)
-{
-        msm_a2m_int(0);
-}
-static inline void notify_dsp_smd(void)
-{
-        msm_a2m_int(8);
-}
-static void smd_diag(void)
-{
-        char *x;
-        x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
-        if (x != 0) {
-                x[SZ_DIAG_ERR_MSG - 1] = 0;
-                pr_debug("DIAG '%s'\n", x);
-        }
-}
-/* call when SMSM_RESET flag is set in the A9's smsm_state */
-static void handle_modem_crash(void)
-{
-        pr_err("ARM9 has CRASHED\n");
-        smd_diag();
-        /* in this case the modem or watchdog should reboot us */
-        for (;;)
-                ;
-}
-uint32_t raw_smsm_get_state(enum smsm_state_item item)
-{
-        return readl(smd_info.state + item * 4);
-}
-static int check_for_modem_crash(void)
-{
-        if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET) {
-                handle_modem_crash();
-                return -1;
-        }
-        return 0;
-}
-/* the spinlock is used to synchronize between the
- * irq handler and code that mutates the channel
- * list or fiddles with channel state
- */
-DEFINE_SPINLOCK(smd_lock);
-DEFINE_SPINLOCK(smem_lock);
-/* the mutex is used during open() and close()
- * operations to avoid races while creating or
- * destroying smd_channel structures
- */
-static DEFINE_MUTEX(smd_creation_mutex);
-static int smd_initialized;
-LIST_HEAD(smd_ch_closed_list);
-LIST_HEAD(smd_ch_list_modem);
-LIST_HEAD(smd_ch_list_dsp);
-static unsigned char smd_ch_allocated[64];
-static struct work_struct probe_work;
-/* how many bytes are available for reading */
-static int smd_stream_read_avail(struct smd_channel *ch)
-{
-        return (ch->recv->head - ch->recv->tail) & ch->fifo_mask;
-}
-/* how many bytes we are free to write */
-static int smd_stream_write_avail(struct smd_channel *ch)
-{
-        return ch->fifo_mask -
-                ((ch->send->head - ch->send->tail) & ch->fifo_mask);
-}
-static int smd_packet_read_avail(struct smd_channel *ch)
-{
-        if (ch->current_packet) {
-                int n = smd_stream_read_avail(ch);
-                if (n > ch->current_packet)
-                        n = ch->current_packet;
-                return n;
-        } else {
-                return 0;
-        }
-}
-static int smd_packet_write_avail(struct smd_channel *ch)
-{
-        int n = smd_stream_write_avail(ch);
-        return n > SMD_HEADER_SIZE ? n - SMD_HEADER_SIZE : 0;
-}
-static int ch_is_open(struct smd_channel *ch)
-{
-        return (ch->recv->state == SMD_SS_OPENED) &&
-                (ch->send->state == SMD_SS_OPENED);
-}
-/* provide a pointer and length to readable data in the fifo */
-static unsigned ch_read_buffer(struct smd_channel *ch, void **ptr)
-{
-        unsigned head = ch->recv->head;
-        unsigned tail = ch->recv->tail;
-        *ptr = (void *) (ch->recv_data + tail);
-        if (tail <= head)
-                return head - tail;
-        else
-                return ch->fifo_size - tail;
-}
-/* advance the fifo read pointer after data from ch_read_buffer is consumed */
-static void ch_read_done(struct smd_channel *ch, unsigned count)
-{
-        BUG_ON(count > smd_stream_read_avail(ch));
-        ch->recv->tail = (ch->recv->tail + count) & ch->fifo_mask;
-        ch->send->fTAIL = 1;
-}
-/* basic read interface to ch_read_{buffer,done} used
- * by smd_*_read() and update_packet_state()
- * will read-and-discard if the _data pointer is null
- */
-static int ch_read(struct smd_channel *ch, void *_data, int len)
-{
-        void *ptr;
-        unsigned n;
-        unsigned char *data = _data;
-        int orig_len = len;
-        while (len > 0) {
-                n = ch_read_buffer(ch, &ptr);
-                if (n == 0)
-                        break;
-                if (n > len)
-                        n = len;
-                if (_data)
-                        memcpy(data, ptr, n);
-                data += n;
-                len -= n;
-                ch_read_done(ch, n);
-        }
-        return orig_len - len;
-}
-static void update_stream_state(struct smd_channel *ch)
-{
-        /* streams have no special state requiring updating */
-}
-static void update_packet_state(struct smd_channel *ch)
-{
-        unsigned hdr[5];
-        int r;
-        /* can't do anything if we're in the middle of a packet */
-        if (ch->current_packet != 0)
-                return;
-        /* don't bother unless we can get the full header */
-        if (smd_stream_read_avail(ch) < SMD_HEADER_SIZE)
-                return;
-        r = ch_read(ch, hdr, SMD_HEADER_SIZE);
-        BUG_ON(r != SMD_HEADER_SIZE);
-        ch->current_packet = hdr[0];
-}
-/* provide a pointer and length to next free space in the fifo */
-static unsigned ch_write_buffer(struct smd_channel *ch, void **ptr)
-{
-        unsigned head = ch->send->head;
-        unsigned tail = ch->send->tail;
-        *ptr = (void *) (ch->send_data + head);
-        if (head < tail) {
-                return tail - head - 1;
-        } else {
-                if (tail == 0)
-                        return ch->fifo_size - head - 1;
-                else
-                        return ch->fifo_size - head;
-        }
-}
-/* advace the fifo write pointer after freespace
- * from ch_write_buffer is filled
- */
-static void ch_write_done(struct smd_channel *ch, unsigned count)
-{
-        BUG_ON(count > smd_stream_write_avail(ch));
-        ch->send->head = (ch->send->head + count) & ch->fifo_mask;
-        ch->send->fHEAD = 1;
-}
-static void ch_set_state(struct smd_channel *ch, unsigned n)
-{
-        if (n == SMD_SS_OPENED) {
-                ch->send->fDSR = 1;
-                ch->send->fCTS = 1;
-                ch->send->fCD = 1;
-        } else {
-                ch->send->fDSR = 0;
-                ch->send->fCTS = 0;
-                ch->send->fCD = 0;
-        }
-        ch->send->state = n;
-        ch->send->fSTATE = 1;
-        ch->notify_other_cpu();
-}
-static void do_smd_probe(void)
-{
-        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
-        if (shared->heap_info.free_offset != last_heap_free) {
-                last_heap_free = shared->heap_info.free_offset;
-                schedule_work(&probe_work);
-        }
-}
-static void smd_state_change(struct smd_channel *ch,
-                             unsigned last, unsigned next)
-{
-        ch->last_state = next;
-        pr_debug("ch %d %d -> %d\n", ch->n, last, next);
-        switch (next) {
-        case SMD_SS_OPENING:
-                ch->recv->tail = 0;
-        case SMD_SS_OPENED:
-                if (ch->send->state != SMD_SS_OPENED)
-                        ch_set_state(ch, SMD_SS_OPENED);
-                ch->notify(ch->priv, SMD_EVENT_OPEN);
-                break;
-        case SMD_SS_FLUSHING:
-        case SMD_SS_RESET:
-                /* we should force them to close? */
-        default:
-                ch->notify(ch->priv, SMD_EVENT_CLOSE);
-        }
-}
-static void handle_smd_irq(struct list_head *list, void (*notify)(void))
-{
-        unsigned long flags;
-        struct smd_channel *ch;
-        int do_notify = 0;
-        unsigned ch_flags;
-        unsigned tmp;
-        spin_lock_irqsave(&smd_lock, flags);
-        list_for_each_entry(ch, list, ch_list) {
-                ch_flags = 0;
-                if (ch_is_open(ch)) {
-                        if (ch->recv->fHEAD) {
-                                ch->recv->fHEAD = 0;
-                                ch_flags |= 1;
-                                do_notify |= 1;
-                        }
-                        if (ch->recv->fTAIL) {
-                                ch->recv->fTAIL = 0;
-                                ch_flags |= 2;
-                                do_notify |= 1;
-                        }
-                        if (ch->recv->fSTATE) {
-                                ch->recv->fSTATE = 0;
-                                ch_flags |= 4;
-                                do_notify |= 1;
-                        }
-                }
-                tmp = ch->recv->state;
-                if (tmp != ch->last_state)
-                        smd_state_change(ch, ch->last_state, tmp);
-                if (ch_flags) {
-                        ch->update_state(ch);
-                        ch->notify(ch->priv, SMD_EVENT_DATA);
-                }
-        }
-        if (do_notify)
-                notify();
-        spin_unlock_irqrestore(&smd_lock, flags);
-        do_smd_probe();
-}
-static irqreturn_t smd_modem_irq_handler(int irq, void *data)
-{
-        handle_smd_irq(&smd_ch_list_modem, notify_modem_smd);
-        return IRQ_HANDLED;
-}
-#if defined(CONFIG_QDSP6)
-static irqreturn_t smd_dsp_irq_handler(int irq, void *data)
-{
-        handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
-        return IRQ_HANDLED;
-}
-#endif
-static void smd_fake_irq_handler(unsigned long arg)
-{
-        handle_smd_irq(&smd_ch_list_modem, notify_modem_smd);
-        handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
-}
-static DECLARE_TASKLET(smd_fake_irq_tasklet, smd_fake_irq_handler, 0);
-static inline int smd_need_int(struct smd_channel *ch)
-{
-        if (ch_is_open(ch)) {
-                if (ch->recv->fHEAD || ch->recv->fTAIL || ch->recv->fSTATE)
-                        return 1;
-                if (ch->recv->state != ch->last_state)
-                        return 1;
-        }
-        return 0;
-}
-void smd_sleep_exit(void)
-{
-        unsigned long flags;
-        struct smd_channel *ch;
-        int need_int = 0;
-        spin_lock_irqsave(&smd_lock, flags);
-        list_for_each_entry(ch, &smd_ch_list_modem, ch_list) {
-                if (smd_need_int(ch)) {
-                        need_int = 1;
-                        break;
-                }
-        }
-        list_for_each_entry(ch, &smd_ch_list_dsp, ch_list) {
-                if (smd_need_int(ch)) {
-                        need_int = 1;
-                        break;
-                }
-        }
-        spin_unlock_irqrestore(&smd_lock, flags);
-        do_smd_probe();
-        if (need_int) {
-                if (msm_smd_debug_mask & MSM_SMD_DEBUG)
-                        pr_info("smd_sleep_exit need interrupt\n");
-                tasklet_schedule(&smd_fake_irq_tasklet);
-        }
-}
-void smd_kick(smd_channel_t *ch)
-{
-        unsigned long flags;
-        unsigned tmp;
-        spin_lock_irqsave(&smd_lock, flags);
-        ch->update_state(ch);
-        tmp = ch->recv->state;
-        if (tmp != ch->last_state) {
-                ch->last_state = tmp;
-                if (tmp == SMD_SS_OPENED)
-                        ch->notify(ch->priv, SMD_EVENT_OPEN);
-                else
-                        ch->notify(ch->priv, SMD_EVENT_CLOSE);
-        }
-        ch->notify(ch->priv, SMD_EVENT_DATA);
-        ch->notify_other_cpu();
-        spin_unlock_irqrestore(&smd_lock, flags);
-}
-static int smd_is_packet(int chn, unsigned type)
-{
-        type &= SMD_KIND_MASK;
-        if (type == SMD_KIND_PACKET)
-                return 1;
-        if (type == SMD_KIND_STREAM)
-                return 0;
-        /* older AMSS reports SMD_KIND_UNKNOWN always */
-        if ((chn > 4) || (chn == 1))
-                return 1;
-        else
-                return 0;
-}
-static int smd_stream_write(smd_channel_t *ch, const void *_data, int len)
-{
-        void *ptr;
-        const unsigned char *buf = _data;
-        unsigned xfer;
-        int orig_len = len;
-        if (len < 0)
-                return -EINVAL;
-        while ((xfer = ch_write_buffer(ch, &ptr)) != 0) {
-                if (!ch_is_open(ch))
-                        break;
-                if (xfer > len)
-                        xfer = len;
-                memcpy(ptr, buf, xfer);
-                ch_write_done(ch, xfer);
-                len -= xfer;
-                buf += xfer;
-                if (len == 0)
-                        break;
-        }
-        ch->notify_other_cpu();
-        return orig_len - len;
-}
-static int smd_packet_write(smd_channel_t *ch, const void *_data, int len)
-{
-        unsigned hdr[5];
-        if (len < 0)
-                return -EINVAL;
-        if (smd_stream_write_avail(ch) < (len + SMD_HEADER_SIZE))
-                return -ENOMEM;
-        hdr[0] = len;
-        hdr[1] = hdr[2] = hdr[3] = hdr[4] = 0;
-        smd_stream_write(ch, hdr, sizeof(hdr));
-        smd_stream_write(ch, _data, len);
-        return len;
-}
-static int smd_stream_read(smd_channel_t *ch, void *data, int len)
-{
-        int r;
-        if (len < 0)
-                return -EINVAL;
-        r = ch_read(ch, data, len);
-        if (r > 0)
-                ch->notify_other_cpu();
-        return r;
-}
-static int smd_packet_read(smd_channel_t *ch, void *data, int len)
-{
-        unsigned long flags;
-        int r;
-        if (len < 0)
-                return -EINVAL;
-        if (len > ch->current_packet)
-                len = ch->current_packet;
-        r = ch_read(ch, data, len);
-        if (r > 0)
-                ch->notify_other_cpu();
-        spin_lock_irqsave(&smd_lock, flags);
-        ch->current_packet -= r;
-        update_packet_state(ch);
-        spin_unlock_irqrestore(&smd_lock, flags);
-        return r;
-}
-static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
-{
-        struct smd_channel *ch;
-        ch = kzalloc(sizeof(struct smd_channel), GFP_KERNEL);
-        if (ch == 0) {
-                pr_err("smd_alloc_channel() out of memory\n");
-                return -1;
-        }
-        ch->n = cid;
-        if (_smd_alloc_channel(ch)) {
-                kfree(ch);
-                return -1;
-        }
-        ch->fifo_mask = ch->fifo_size - 1;
-        ch->type = type;
-        if ((type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
-                ch->notify_other_cpu = notify_modem_smd;
-        else
-                ch->notify_other_cpu = notify_dsp_smd;
-        if (smd_is_packet(cid, type)) {
-                ch->read = smd_packet_read;
-                ch->write = smd_packet_write;
-                ch->read_avail = smd_packet_read_avail;
-                ch->write_avail = smd_packet_write_avail;
-                ch->update_state = update_packet_state;
-        } else {
-                ch->read = smd_stream_read;
-                ch->write = smd_stream_write;
-                ch->read_avail = smd_stream_read_avail;
-                ch->write_avail = smd_stream_write_avail;
-                ch->update_state = update_stream_state;
-        }
-        if ((type & 0xff) == 0)
-                memcpy(ch->name, "SMD_", 4);
-        else
-                memcpy(ch->name, "DSP_", 4);
-        memcpy(ch->name + 4, name, 20);
-        ch->name[23] = 0;
-        ch->pdev.name = ch->name;
-        ch->pdev.id = -1;
-        pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
-                ch->n, ch->fifo_size, ch->name);
-        mutex_lock(&smd_creation_mutex);
-        list_add(&ch->ch_list, &smd_ch_closed_list);
-        mutex_unlock(&smd_creation_mutex);
-        platform_device_register(&ch->pdev);
-        return 0;
-}
-static void smd_channel_probe_worker(struct work_struct *work)
-{
-        struct smd_alloc_elm *shared;
-        unsigned ctype;
-        unsigned type;
-        unsigned n;
-        shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
-        if (!shared) {
-                pr_err("cannot find allocation table\n");
-                return;
-        }
-        for (n = 0; n < 64; n++) {
-                if (smd_ch_allocated[n])
-                        continue;
-                if (!shared[n].ref_count)
-                        continue;
-                if (!shared[n].name[0])
-                        continue;
-                ctype = shared[n].ctype;
-                type = ctype & SMD_TYPE_MASK;
-                /* DAL channels are stream but neither the modem,
-                 * nor the DSP correctly indicate this.  Fixup manually.
-                 */
-                if (!memcmp(shared[n].name, "DAL", 3))
-                        ctype = (ctype & (~SMD_KIND_MASK)) | SMD_KIND_STREAM;
-                type = shared[n].ctype & SMD_TYPE_MASK;
-                if ((type == SMD_TYPE_APPS_MODEM) ||
-                    (type == SMD_TYPE_APPS_DSP))
-                        if (!smd_alloc_channel(shared[n].name, shared[n].cid, ctype))
-                                smd_ch_allocated[n] = 1;
-        }
-}
-static void do_nothing_notify(void *priv, unsigned flags)
-{
-}
-struct smd_channel *smd_get_channel(const char *name)
-{
-        struct smd_channel *ch;
-        mutex_lock(&smd_creation_mutex);
-        list_for_each_entry(ch, &smd_ch_closed_list, ch_list) {
-                if (!strcmp(name, ch->name)) {
-                        list_del(&ch->ch_list);
-                        mutex_unlock(&smd_creation_mutex);
-                        return ch;
-                }
-        }
-        mutex_unlock(&smd_creation_mutex);
-        return NULL;
-}
-int smd_open(const char *name, smd_channel_t **_ch,
-             void *priv, void (*notify)(void *, unsigned))
-{
-        struct smd_channel *ch;
-        unsigned long flags;
-        if (smd_initialized == 0) {
-                pr_info("smd_open() before smd_init()\n");
-                return -ENODEV;
-        }
-        ch = smd_get_channel(name);
-        if (!ch)
-                return -ENODEV;
-        if (notify == 0)
-                notify = do_nothing_notify;
-        ch->notify = notify;
-        ch->current_packet = 0;
-        ch->last_state = SMD_SS_CLOSED;
-        ch->priv = priv;
-        *_ch = ch;
-        spin_lock_irqsave(&smd_lock, flags);
-        if ((ch->type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
-                list_add(&ch->ch_list, &smd_ch_list_modem);
-        else
-                list_add(&ch->ch_list, &smd_ch_list_dsp);
-        /* If the remote side is CLOSING, we need to get it to
-         * move to OPENING (which we'll do by moving from CLOSED to
-         * OPENING) and then get it to move from OPENING to
-         * OPENED (by doing the same state change ourselves).
-         *
-         * Otherwise, it should be OPENING and we can move directly
-         * to OPENED so that it will follow.
-         */
-        if (ch->recv->state == SMD_SS_CLOSING) {
-                ch->send->head = 0;
-                ch_set_state(ch, SMD_SS_OPENING);
-        } else {
-                ch_set_state(ch, SMD_SS_OPENED);
-        }
-        spin_unlock_irqrestore(&smd_lock, flags);
-        smd_kick(ch);
-        return 0;
-}
-int smd_close(smd_channel_t *ch)
-{
-        unsigned long flags;
-        if (ch == 0)
-                return -1;
-        spin_lock_irqsave(&smd_lock, flags);
-        ch->notify = do_nothing_notify;
-        list_del(&ch->ch_list);
-        ch_set_state(ch, SMD_SS_CLOSED);
-        spin_unlock_irqrestore(&smd_lock, flags);
-        mutex_lock(&smd_creation_mutex);
-        list_add(&ch->ch_list, &smd_ch_closed_list);
-        mutex_unlock(&smd_creation_mutex);
-        return 0;
-}
-int smd_read(smd_channel_t *ch, void *data, int len)
-{
-        return ch->read(ch, data, len);
-}
-int smd_write(smd_channel_t *ch, const void *data, int len)
-{
-        return ch->write(ch, data, len);
-}
-int smd_write_atomic(smd_channel_t *ch, const void *data, int len)
-{
-        unsigned long flags;
-        int res;
-        spin_lock_irqsave(&smd_lock, flags);
-        res = ch->write(ch, data, len);
-        spin_unlock_irqrestore(&smd_lock, flags);
-        return res;
-}
-int smd_read_avail(smd_channel_t *ch)
-{
-        return ch->read_avail(ch);
-}
-int smd_write_avail(smd_channel_t *ch)
-{
-        return ch->write_avail(ch);
-}
-int smd_wait_until_readable(smd_channel_t *ch, int bytes)
-{
-        return -1;
-}
-int smd_wait_until_writable(smd_channel_t *ch, int bytes)
-{
-        return -1;
-}
-int smd_cur_packet_size(smd_channel_t *ch)
-{
-        return ch->current_packet;
-}
-/* ------------------------------------------------------------------------- */
-void *smem_alloc(unsigned id, unsigned size)
-{
-        return smem_find(id, size);
-}
-void __iomem *smem_item(unsigned id, unsigned *size)
-{
-        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
-        struct smem_heap_entry *toc = shared->heap_toc;
-        if (id >= SMEM_NUM_ITEMS)
-                return NULL;
-        if (toc[id].allocated) {
-                *size = toc[id].size;
-                return (MSM_SHARED_RAM_BASE + toc[id].offset);
-        } else {
-                *size = 0;
-        }
-        return NULL;
-}
-void *smem_find(unsigned id, unsigned size_in)
-{
-        unsigned size;
-        void *ptr;
-        ptr = smem_item(id, &size);
-        if (!ptr)
-                return 0;
-        size_in = ALIGN(size_in, 8);
-        if (size_in != size) {
-                pr_err("smem_find(%d, %d): wrong size %d\n",
-                       id, size_in, size);
-                return 0;
-        }
-        return ptr;
-}
-static irqreturn_t smsm_irq_handler(int irq, void *data)
-{
-        unsigned long flags;
-        unsigned apps, modm;
-        spin_lock_irqsave(&smem_lock, flags);
-        apps = raw_smsm_get_state(SMSM_STATE_APPS);
-        modm = raw_smsm_get_state(SMSM_STATE_MODEM);
-        if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
-                pr_info("<SM %08x %08x>\n", apps, modm);
-        if (modm & SMSM_RESET)
-                handle_modem_crash();
-        do_smd_probe();
-        spin_unlock_irqrestore(&smem_lock, flags);
-        return IRQ_HANDLED;
-}
-int smsm_change_state(enum smsm_state_item item,
-                      uint32_t clear_mask, uint32_t set_mask)
-{
-        void __iomem *addr = smd_info.state + item * 4;
-        unsigned long flags;
-        unsigned state;
-        if (!smd_info.ready)
-                return -EIO;
-        spin_lock_irqsave(&smem_lock, flags);
-        if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET)
-                handle_modem_crash();
-        state = (readl(addr) & ~clear_mask) | set_mask;
-        writel(state, addr);
-        if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
-                pr_info("smsm_change_state %d %x\n", item, state);
-        notify_other_smsm();
-        spin_unlock_irqrestore(&smem_lock, flags);
-        return 0;
-}
-uint32_t smsm_get_state(enum smsm_state_item item)
-{
-        unsigned long flags;
-        uint32_t rv;
-        spin_lock_irqsave(&smem_lock, flags);
-        rv = readl(smd_info.state + item * 4);
-        if (item == SMSM_STATE_MODEM && (rv & SMSM_RESET))
-                handle_modem_crash();
-        spin_unlock_irqrestore(&smem_lock, flags);
-        return rv;
-}
-#ifdef CONFIG_ARCH_MSM_SCORPION
-int smsm_set_sleep_duration(uint32_t delay)
-{
-        struct msm_dem_slave_data *ptr;
-        ptr = smem_find(SMEM_APPS_DEM_SLAVE_DATA, sizeof(*ptr));
-        if (ptr == NULL) {
-                pr_err("smsm_set_sleep_duration <SM NO APPS_DEM_SLAVE_DATA>\n");
-                return -EIO;
-        }
-        if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
-                pr_info("smsm_set_sleep_duration %d -> %d\n",
-                       ptr->sleep_time, delay);
-        ptr->sleep_time = delay;
-        return 0;
-}
-#else
-int smsm_set_sleep_duration(uint32_t delay)
-{
-        uint32_t *ptr;
-        ptr = smem_find(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
-        if (ptr == NULL) {
-                pr_err("smsm_set_sleep_duration <SM NO SLEEP_DELAY>\n");
-                return -EIO;
-        }
-        if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
-                pr_info("smsm_set_sleep_duration %d -> %d\n",
-                       *ptr, delay);
-        *ptr = delay;
-        return 0;
-}
-#endif
-int smd_core_init(void)
-{
-        int r;
-        /* wait for essential items to be initialized */
-        for (;;) {
-                unsigned size;
-                void __iomem *state;
-                state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
-                if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
-                        smd_info.state = state;
-                        break;
-                }
-        }
-        smd_info.ready = 1;
-        r = request_irq(INT_A9_M2A_0, smd_modem_irq_handler,
-                        IRQF_TRIGGER_RISING, "smd_dev", 0);
-        if (r < 0)
-                return r;
-        r = enable_irq_wake(INT_A9_M2A_0);
-        if (r < 0)
-                pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_0\n");
-        r = request_irq(INT_A9_M2A_5, smsm_irq_handler,
-                        IRQF_TRIGGER_RISING, "smsm_dev", 0);
-        if (r < 0) {
-                free_irq(INT_A9_M2A_0, 0);
-                return r;
-        }
-        r = enable_irq_wake(INT_A9_M2A_5);
-        if (r < 0)
-                pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_5\n");
-#if defined(CONFIG_QDSP6)
-        r = request_irq(INT_ADSP_A11, smd_dsp_irq_handler,
-                        IRQF_TRIGGER_RISING, "smd_dsp", 0);
-        if (r < 0) {
-                free_irq(INT_A9_M2A_0, 0);
-                free_irq(INT_A9_M2A_5, 0);
-                return r;
-        }
-#endif
-        /* check for any SMD channels that may already exist */
-        do_smd_probe();
-        /* indicate that we're up and running */
-        smsm_change_state(SMSM_STATE_APPS,
-                          ~0, SMSM_INIT | SMSM_SMDINIT | SMSM_RPCINIT | SMSM_RUN);
-#ifdef CONFIG_ARCH_MSM_SCORPION
-        smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
-#endif
-        return 0;
-}
-static int msm_smd_probe(struct platform_device *pdev)
-{
-        /*
-         * If we haven't waited for the ARM9 to boot up till now,
-         * then we need to wait here. Otherwise this should just
-         * return immediately.
-         */
-        proc_comm_boot_wait();
-        INIT_WORK(&probe_work, smd_channel_probe_worker);
-        if (smd_core_init()) {
-                pr_err("smd_core_init() failed\n");
-                return -1;
-        }
-        do_smd_probe();
-        msm_check_for_modem_crash = check_for_modem_crash;
-        msm_init_last_radio_log(THIS_MODULE);
-        smd_initialized = 1;
-        return 0;
-}
-static struct platform_driver msm_smd_driver = {
-        .probe = msm_smd_probe,
-        .driver = {
-                .name = MODULE_NAME,
-        },
-};
-static int __init msm_smd_init(void)
-{
-        return platform_driver_register(&msm_smd_driver);
-}
-module_init(msm_smd_init);
-MODULE_DESCRIPTION("MSM Shared Memory Core");
-MODULE_AUTHOR("Brian Swetland <swetland@google.com>");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
deleted file mode 100644
index 8056b3e5590f..000000000000
--- a/arch/arm/mach-msm/smd_debug.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* arch/arm/mach-msm/smd_debug.c
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/debugfs.h>
-#include <linux/list.h>
-#include <mach/msm_iomap.h>
-#include "smd_private.h"
-#if defined(CONFIG_DEBUG_FS)
-static char *chstate(unsigned n)
-{
-        switch (n) {
-        case SMD_SS_CLOSED:
-                return "CLOSED";
-        case SMD_SS_OPENING:
-                return "OPENING";
-        case SMD_SS_OPENED:
-                return "OPENED";
-        case SMD_SS_FLUSHING:
-                return "FLUSHING";
-        case SMD_SS_CLOSING:
-                return "CLOSING";
-        case SMD_SS_RESET:
-                return "RESET";
-        case SMD_SS_RESET_OPENING:
-                return "ROPENING";
-        default:
-                return "UNKNOWN";
-        }
-}
-static int dump_ch(char *buf, int max, struct smd_channel *ch)
-{
-        volatile struct smd_half_channel *s = ch->send;
-        volatile struct smd_half_channel *r = ch->recv;
-        return scnprintf(
-                buf, max,
-                "ch%02d:"
-                " %8s(%05d/%05d) %c%c%c%c%c%c%c <->"
-                " %8s(%05d/%05d) %c%c%c%c%c%c%c '%s'\n", ch->n,
-                chstate(s->state), s->tail, s->head,
-                s->fDSR ? 'D' : 'd',
-                s->fCTS ? 'C' : 'c',
-                s->fCD ? 'C' : 'c',
-                s->fRI ? 'I' : 'i',
-                s->fHEAD ? 'W' : 'w',
-                s->fTAIL ? 'R' : 'r',
-                s->fSTATE ? 'S' : 's',
-                chstate(r->state), r->tail, r->head,
-                r->fDSR ? 'D' : 'd',
-                r->fCTS ? 'R' : 'r',
-                r->fCD ? 'C' : 'c',
-                r->fRI ? 'I' : 'i',
-                r->fHEAD ? 'W' : 'w',
-                r->fTAIL ? 'R' : 'r',
-                r->fSTATE ? 'S' : 's',
-                ch->name
-                );
-}
-static int debug_read_stat(char *buf, int max)
-{
-        char *msg;
-        int i = 0;
-        msg = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
-        if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET)
-                i += scnprintf(buf + i, max - i,
-                               "smsm: ARM9 HAS CRASHED\n");
-        i += scnprintf(buf + i, max - i, "smsm: a9: %08x a11: %08x\n",
-                       raw_smsm_get_state(SMSM_STATE_MODEM),
-                       raw_smsm_get_state(SMSM_STATE_APPS));
-#ifdef CONFIG_ARCH_MSM_SCORPION
-        i += scnprintf(buf + i, max - i, "smsm dem: apps: %08x modem: %08x "
-                       "qdsp6: %08x power: %08x time: %08x\n",
-                       raw_smsm_get_state(SMSM_STATE_APPS_DEM),
-                       raw_smsm_get_state(SMSM_STATE_MODEM_DEM),
-                       raw_smsm_get_state(SMSM_STATE_QDSP6_DEM),
-                       raw_smsm_get_state(SMSM_STATE_POWER_MASTER_DEM),
-                       raw_smsm_get_state(SMSM_STATE_TIME_MASTER_DEM));
-#endif
-        if (msg) {
-                msg[SZ_DIAG_ERR_MSG - 1] = 0;
-                i += scnprintf(buf + i, max - i, "diag: '%s'\n", msg);
-        }
-        return i;
-}
-static int debug_read_mem(char *buf, int max)
-{
-        unsigned n;
-        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
-        struct smem_heap_entry *toc = shared->heap_toc;
-        int i = 0;
-        i += scnprintf(buf + i, max - i,
-                       "heap: init=%d free=%d remain=%d\n",
-                       shared->heap_info.initialized,
-                       shared->heap_info.free_offset,
-                       shared->heap_info.heap_remaining);
-        for (n = 0; n < SMEM_NUM_ITEMS; n++) {
-                if (toc[n].allocated == 0)
-                        continue;
-                i += scnprintf(buf + i, max - i,
-                               "%04d: offset %08x size %08x\n",
-                               n, toc[n].offset, toc[n].size);
-        }
-        return i;
-}
-static int debug_read_ch(char *buf, int max)
-{
-        struct smd_channel *ch;
-        unsigned long flags;
-        int i = 0;
-        spin_lock_irqsave(&smd_lock, flags);
-        list_for_each_entry(ch, &smd_ch_list_dsp, ch_list)
-                i += dump_ch(buf + i, max - i, ch);
-        list_for_each_entry(ch, &smd_ch_list_modem, ch_list)
-                i += dump_ch(buf + i, max - i, ch);
-        list_for_each_entry(ch, &smd_ch_closed_list, ch_list)
-                i += dump_ch(buf + i, max - i, ch);
-        spin_unlock_irqrestore(&smd_lock, flags);
-        return i;
-}
-static int debug_read_version(char *buf, int max)
-{
-        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
-        unsigned version = shared->version[VERSION_MODEM];
-        return sprintf(buf, "%d.%d\n", version >> 16, version & 0xffff);
-}
-static int debug_read_build_id(char *buf, int max)
-{
-        unsigned size;
-        void *data;
-        data = smem_item(SMEM_HW_SW_BUILD_ID, &size);
-        if (!data)
-                return 0;
-        if (size >= max)
-                size = max;
-        memcpy(buf, data, size);
-        return size;
-}
-static int debug_read_alloc_tbl(char *buf, int max)
-{
-        struct smd_alloc_elm *shared;
-        int n, i = 0;
-        shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
-        for (n = 0; n < 64; n++) {
-                if (shared[n].ref_count == 0)
-                        continue;
-                i += scnprintf(buf + i, max - i,
-                               "%03d: %-20s cid=%02d type=%03d "
-                               "kind=%02d ref_count=%d\n",
-                               n, shared[n].name, shared[n].cid,
-                               shared[n].ctype & 0xff,
-                               (shared[n].ctype >> 8) & 0xf,
-                               shared[n].ref_count);
-        }
-        return i;
-}
-#define DEBUG_BUFMAX 4096
-static char debug_buffer[DEBUG_BUFMAX];
-static ssize_t debug_read(struct file *file, char __user *buf,
-                          size_t count, loff_t *ppos)
-{
-        int (*fill)(char *buf, int max) = file->private_data;
-        int bsize = fill(debug_buffer, DEBUG_BUFMAX);
-        return simple_read_from_buffer(buf, count, ppos, debug_buffer, bsize);
-}
-static const struct file_operations debug_ops = {
-        .read = debug_read,
-        .open = simple_open,
-        .llseek = default_llseek,
-};
-static void debug_create(const char *name, umode_t mode,
-                         struct dentry *dent,
-                         int (*fill)(char *buf, int max))
-{
-        debugfs_create_file(name, mode, dent, fill, &debug_ops);
-}
-int __init smd_debugfs_init(void)
-{
-        struct dentry *dent;
-        dent = debugfs_create_dir("smd", 0);
-        if (IS_ERR(dent))
-                return 1;
-        debug_create("ch", 0444, dent, debug_read_ch);
-        debug_create("stat", 0444, dent, debug_read_stat);
-        debug_create("mem", 0444, dent, debug_read_mem);
-        debug_create("version", 0444, dent, debug_read_version);
-        debug_create("tbl", 0444, dent, debug_read_alloc_tbl);
-        debug_create("build", 0444, dent, debug_read_build_id);
-        return 0;
-}
-#endif
-#define MAX_NUM_SLEEP_CLIENTS           64
-#define MAX_SLEEP_NAME_LEN              8
-#define NUM_GPIO_INT_REGISTERS          6
-#define GPIO_SMEM_NUM_GROUPS            2
-#define GPIO_SMEM_MAX_PC_INTERRUPTS     8
-struct tramp_gpio_save {
-        unsigned int enable;
-        unsigned int detect;
-        unsigned int polarity;
-};
-struct tramp_gpio_smem {
-        uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
-        uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
-        uint32_t enabled[NUM_GPIO_INT_REGISTERS];
-        uint32_t detection[NUM_GPIO_INT_REGISTERS];
-        uint32_t polarity[NUM_GPIO_INT_REGISTERS];
-};
-void smsm_print_sleep_info(void)
-{
-        unsigned long flags;
-        uint32_t *ptr;
-#ifndef CONFIG_ARCH_MSM_SCORPION
-        struct tramp_gpio_smem *gpio;
-        struct smsm_interrupt_info *int_info;
-#endif
-        spin_lock_irqsave(&smem_lock, flags);
-        ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
-        if (ptr)
-                pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr);
-        ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr));
-        if (ptr)
-                pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr);
-        ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr));
-        if (ptr)
-                pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr);
-#ifndef CONFIG_ARCH_MSM_SCORPION
-        int_info = smem_alloc(SMEM_SMSM_INT_INFO, sizeof(*int_info));
-        if (int_info)
-                pr_info("SMEM_SMSM_INT_INFO %x %x %x\n",
-                        int_info->interrupt_mask,
-                        int_info->pending_interrupts,
-                        int_info->wakeup_reason);
-        gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*gpio));
-        if (gpio) {
-                int i;
-                for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++)
-                        pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n",
-                                i, gpio->enabled[i], gpio->detection[i],
-                                gpio->polarity[i]);
-                for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
-                        pr_info("SMEM_GPIO_INT: %d: f %d: %d %d...\n",
-                                i, gpio->num_fired[i], gpio->fired[i][0],
-                                gpio->fired[i][1]);
-        }
-#else
-#endif
-        spin_unlock_irqrestore(&smem_lock, flags);
-}
diff --git a/arch/arm/mach-msm/smd_private.h b/arch/arm/mach-msm/smd_private.h
deleted file mode 100644
index 727bfe68aa9b..000000000000
--- a/arch/arm/mach-msm/smd_private.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* arch/arm/mach-msm/smd_private.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
-#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <mach/msm_iomap.h>
-struct smem_heap_info {
-        unsigned initialized;
-        unsigned free_offset;
-        unsigned heap_remaining;
-        unsigned reserved;
-};
-struct smem_heap_entry {
-        unsigned allocated;
-        unsigned offset;
-        unsigned size;
-        unsigned reserved;
-};
-struct smem_proc_comm {
-        unsigned command;
-        unsigned status;
-        unsigned data1;
-        unsigned data2;
-};
-#define PC_APPS  0
-#define PC_MODEM 1
-#define VERSION_SMD       0
-#define VERSION_QDSP6     4
-#define VERSION_APPS_SBL  6
-#define VERSION_MODEM_SBL 7
-#define VERSION_APPS      8
-#define VERSION_MODEM     9
-struct smem_shared {
-        struct smem_proc_comm proc_comm[4];
-        unsigned version[32];
-        struct smem_heap_info heap_info;
-        struct smem_heap_entry heap_toc[512];
-};
-#define SMSM_V1_SIZE            (sizeof(unsigned) * 8)
-#define SMSM_V2_SIZE            (sizeof(unsigned) * 4)
-#ifdef CONFIG_MSM_SMD_PKG3
-struct smsm_interrupt_info {
-        uint32_t interrupt_mask;
-        uint32_t pending_interrupts;
-        uint32_t wakeup_reason;
-};
-#else
-#define DEM_MAX_PORT_NAME_LEN (20)
-struct msm_dem_slave_data {
-        uint32_t sleep_time;
-        uint32_t interrupt_mask;
-        uint32_t resources_used;
-        uint32_t reserved1;
-        uint32_t wakeup_reason;
-        uint32_t pending_interrupts;
-        uint32_t rpc_prog;
-        uint32_t rpc_proc;
-        char     smd_port_name[DEM_MAX_PORT_NAME_LEN];
-        uint32_t reserved2;
-};
-#endif
-#define SZ_DIAG_ERR_MSG 0xC8
-#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
-#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
-#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
-#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
-#define SMSM_INIT               0x00000001
-#define SMSM_SMDINIT            0x00000008
-#define SMSM_RPCINIT            0x00000020
-#define SMSM_RESET              0x00000040
-#define SMSM_RSA                0x00000080
-#define SMSM_RUN                0x00000100
-#define SMSM_PWRC               0x00000200
-#define SMSM_TIMEWAIT           0x00000400
-#define SMSM_TIMEINIT           0x00000800
-#define SMSM_PWRC_EARLY_EXIT    0x00001000
-#define SMSM_WFPI               0x00002000
-#define SMSM_SLEEP              0x00004000
-#define SMSM_SLEEPEXIT          0x00008000
-#define SMSM_APPS_REBOOT        0x00020000
-#define SMSM_SYSTEM_POWER_DOWN  0x00040000
-#define SMSM_SYSTEM_REBOOT      0x00080000
-#define SMSM_SYSTEM_DOWNLOAD    0x00100000
-#define SMSM_PWRC_SUSPEND       0x00200000
-#define SMSM_APPS_SHUTDOWN      0x00400000
-#define SMSM_SMD_LOOPBACK       0x00800000
-#define SMSM_RUN_QUIET          0x01000000
-#define SMSM_MODEM_WAIT         0x02000000
-#define SMSM_MODEM_BREAK        0x04000000
-#define SMSM_MODEM_CONTINUE     0x08000000
-#define SMSM_UNKNOWN            0x80000000
-#define SMSM_WKUP_REASON_RPC    0x00000001
-#define SMSM_WKUP_REASON_INT    0x00000002
-#define SMSM_WKUP_REASON_GPIO   0x00000004
-#define SMSM_WKUP_REASON_TIMER  0x00000008
-#define SMSM_WKUP_REASON_ALARM  0x00000010
-#define SMSM_WKUP_REASON_RESET  0x00000020
-#ifdef CONFIG_ARCH_MSM7X00A
-enum smsm_state_item {
-        SMSM_STATE_APPS = 1,
-        SMSM_STATE_MODEM = 3,
-        SMSM_STATE_COUNT,
-};
-#else
-enum smsm_state_item {
-        SMSM_STATE_APPS,
-        SMSM_STATE_MODEM,
-        SMSM_STATE_HEXAGON,
-        SMSM_STATE_APPS_DEM,
-        SMSM_STATE_MODEM_DEM,
-        SMSM_STATE_QDSP6_DEM,
-        SMSM_STATE_POWER_MASTER_DEM,
-        SMSM_STATE_TIME_MASTER_DEM,
-        SMSM_STATE_COUNT,
-};
-#endif
-void *smem_alloc(unsigned id, unsigned size);
-int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
-uint32_t smsm_get_state(enum smsm_state_item item);
-int smsm_set_sleep_duration(uint32_t delay);
-void smsm_print_sleep_info(void);
-#define SMEM_NUM_SMD_CHANNELS        64
-typedef enum {
-        /* fixed items */
-        SMEM_PROC_COMM = 0,
-        SMEM_HEAP_INFO,
-        SMEM_ALLOCATION_TABLE,
-        SMEM_VERSION_INFO,
-        SMEM_HW_RESET_DETECT,
-        SMEM_AARM_WARM_BOOT,
-        SMEM_DIAG_ERR_MESSAGE,
-        SMEM_SPINLOCK_ARRAY,
-        SMEM_MEMORY_BARRIER_LOCATION,
-        /* dynamic items */
-        SMEM_AARM_PARTITION_TABLE,
-        SMEM_AARM_BAD_BLOCK_TABLE,
-        SMEM_RESERVE_BAD_BLOCKS,
-        SMEM_WM_UUID,
-        SMEM_CHANNEL_ALLOC_TBL,
-        SMEM_SMD_BASE_ID,
-        SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
-        SMEM_SMEM_LOG_EVENTS,
-        SMEM_SMEM_STATIC_LOG_IDX,
-        SMEM_SMEM_STATIC_LOG_EVENTS,
-        SMEM_SMEM_SLOW_CLOCK_SYNC,
-        SMEM_SMEM_SLOW_CLOCK_VALUE,
-        SMEM_BIO_LED_BUF,
-        SMEM_SMSM_SHARED_STATE,
-        SMEM_SMSM_INT_INFO,
-        SMEM_SMSM_SLEEP_DELAY,
-        SMEM_SMSM_LIMIT_SLEEP,
-        SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
-        SMEM_KEYPAD_KEYS_PRESSED,
-        SMEM_KEYPAD_STATE_UPDATED,
-        SMEM_KEYPAD_STATE_IDX,
-        SMEM_GPIO_INT,
-        SMEM_MDDI_LCD_IDX,
-        SMEM_MDDI_HOST_DRIVER_STATE,
-        SMEM_MDDI_LCD_DISP_STATE,
-        SMEM_LCD_CUR_PANEL,
-        SMEM_MARM_BOOT_SEGMENT_INFO,
-        SMEM_AARM_BOOT_SEGMENT_INFO,
-        SMEM_SLEEP_STATIC,
-        SMEM_SCORPION_FREQUENCY,
-        SMEM_SMD_PROFILES,
-        SMEM_TSSC_BUSY,
-        SMEM_HS_SUSPEND_FILTER_INFO,
-        SMEM_BATT_INFO,
-        SMEM_APPS_BOOT_MODE,
-        SMEM_VERSION_FIRST,
-        SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
-        SMEM_OSS_RRCASN1_BUF1,
-        SMEM_OSS_RRCASN1_BUF2,
-        SMEM_ID_VENDOR0,
-        SMEM_ID_VENDOR1,
-        SMEM_ID_VENDOR2,
-        SMEM_HW_SW_BUILD_ID,
-        SMEM_SMD_BLOCK_PORT_BASE_ID,
-        SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
-        SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
-        SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
-        SMEM_SCLK_CONVERSION,
-        SMEM_SMD_SMSM_INTR_MUX,
-        SMEM_SMSM_CPU_INTR_MASK,
-        SMEM_APPS_DEM_SLAVE_DATA,
-        SMEM_QDSP6_DEM_SLAVE_DATA,
-        SMEM_CLKREGIM_BSP,
-        SMEM_CLKREGIM_SOURCES,
-        SMEM_SMD_FIFO_BASE_ID,
-        SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
-        SMEM_POWER_ON_STATUS_INFO,
-        SMEM_DAL_AREA,
-        SMEM_SMEM_LOG_POWER_IDX,
-        SMEM_SMEM_LOG_POWER_WRAP,
-        SMEM_SMEM_LOG_POWER_EVENTS,
-        SMEM_ERR_CRASH_LOG,
-        SMEM_ERR_F3_TRACE_LOG,
-        SMEM_NUM_ITEMS,
-} smem_mem_type;
-#define SMD_SS_CLOSED           0x00000000
-#define SMD_SS_OPENING          0x00000001
-#define SMD_SS_OPENED           0x00000002
-#define SMD_SS_FLUSHING         0x00000003
-#define SMD_SS_CLOSING          0x00000004
-#define SMD_SS_RESET            0x00000005
-#define SMD_SS_RESET_OPENING    0x00000006
-#define SMD_BUF_SIZE            8192
-#define SMD_CHANNELS            64
-#define SMD_HEADER_SIZE         20
-struct smd_alloc_elm {
-        char name[20];
-        uint32_t cid;
-        uint32_t ctype;
-        uint32_t ref_count;
-};
-struct smd_half_channel {
-        unsigned state;
-        unsigned char fDSR;
-        unsigned char fCTS;
-        unsigned char fCD;
-        unsigned char fRI;
-        unsigned char fHEAD;
-        unsigned char fTAIL;
-        unsigned char fSTATE;
-        unsigned char fUNUSED;
-        unsigned tail;
-        unsigned head;
-} __attribute__(( aligned(4), packed ));
-/* Only used on SMD package v3 on msm7201a */
-struct smd_shared_v1 {
-        struct smd_half_channel ch0;
-        unsigned char data0[SMD_BUF_SIZE];
-        struct smd_half_channel ch1;
-        unsigned char data1[SMD_BUF_SIZE];
-};
-/* Used on SMD package v4 */
-struct smd_shared_v2 {
-        struct smd_half_channel ch0;
-        struct smd_half_channel ch1;
-};
-struct smd_channel {
-        volatile struct smd_half_channel *send;
-        volatile struct smd_half_channel *recv;
-        unsigned char *send_data;
-        unsigned char *recv_data;
-        unsigned fifo_mask;
-        unsigned fifo_size;
-        unsigned current_packet;
-        unsigned n;
-        struct list_head ch_list;
-        void *priv;
-        void (*notify)(void *priv, unsigned flags);
-        int (*read)(struct smd_channel *ch, void *data, int len);
-        int (*write)(struct smd_channel *ch, const void *data, int len);
-        int (*read_avail)(struct smd_channel *ch);
-        int (*write_avail)(struct smd_channel *ch);
-        void (*update_state)(struct smd_channel *ch);
-        unsigned last_state;
-        void (*notify_other_cpu)(void);
-        unsigned type;
-        char name[32];
-        struct platform_device pdev;
-};
-#define SMD_TYPE_MASK           0x0FF
-#define SMD_TYPE_APPS_MODEM     0x000
-#define SMD_TYPE_APPS_DSP       0x001
-#define SMD_TYPE_MODEM_DSP      0x002
-#define SMD_KIND_MASK           0xF00
-#define SMD_KIND_UNKNOWN        0x000
-#define SMD_KIND_STREAM         0x100
-#define SMD_KIND_PACKET         0x200
-extern struct list_head smd_ch_closed_list;
-extern struct list_head smd_ch_list_modem;
-extern struct list_head smd_ch_list_dsp;
-extern spinlock_t smd_lock;
-extern spinlock_t smem_lock;
-void *smem_find(unsigned id, unsigned size);
-void *smem_item(unsigned id, unsigned *size);
-uint32_t raw_smsm_get_state(enum smsm_state_item item);
-extern void msm_init_last_radio_log(struct module *);
-#ifdef CONFIG_MSM_SMD_PKG3
-/*
- * This allocator assumes an SMD Package v3 which only exists on
- * MSM7x00 SoC's.
- */
-static inline int _smd_alloc_channel(struct smd_channel *ch)
-{
-        struct smd_shared_v1 *shared1;
-        shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
-        if (!shared1) {
-                pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
-                return -1;
-        }
-        ch->send = &shared1->ch0;
-        ch->recv = &shared1->ch1;
-        ch->send_data = shared1->data0;
-        ch->recv_data = shared1->data1;
-        ch->fifo_size = SMD_BUF_SIZE;
-        return 0;
-}
-#else
-/*
- * This allocator assumes an SMD Package v4, the most common
- * and the default.
- */
-static inline int _smd_alloc_channel(struct smd_channel *ch)
-{
-        struct smd_shared_v2 *shared2;
-        void *buffer;
-        unsigned buffer_sz;
-        shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
-        buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
-        if (!buffer)
-                return -1;
-        /* buffer must be a power-of-two size */
-        if (buffer_sz & (buffer_sz - 1))
-                return -1;
-        buffer_sz /= 2;
-        ch->send = &shared2->ch0;
-        ch->recv = &shared2->ch1;
-        ch->send_data = buffer;
-        ch->recv_data = buffer + buffer_sz;
-        ch->fifo_size = buffer_sz;
-        return 0;
-}
-#endif /* CONFIG_MSM_SMD_PKG3 */
-#if defined(CONFIG_ARCH_MSM7X30)
-static inline void msm_a2m_int(uint32_t irq)
-{
-        writel(1 << irq, MSM_GCC_BASE + 0x8);
-}
-#else
-static inline void msm_a2m_int(uint32_t irq)
-{
-        writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
-}
-#endif /* CONFIG_ARCH_MSM7X30 */
-#endif
diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c
deleted file mode 100644
index bd66ed04d6dc..000000000000
--- a/arch/arm/mach-msm/vreg.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* arch/arm/mach-msm/vreg.c
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/debugfs.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <mach/vreg.h>
-#include "proc_comm.h"
-struct vreg {
-        const char *name;
-        unsigned id;
-        int status;
-        unsigned refcnt;
-};
-#define VREG(_name, _id, _status, _refcnt) \
-        { .name = _name, .id = _id, .status = _status, .refcnt = _refcnt }
-static struct vreg vregs[] = {
-        VREG("msma",    0, 0, 0),
-        VREG("msmp",    1, 0, 0),
-        VREG("msme1",   2, 0, 0),
-        VREG("msmc1",   3, 0, 0),
-        VREG("msmc2",   4, 0, 0),
-        VREG("gp3",     5, 0, 0),
-        VREG("msme2",   6, 0, 0),
-        VREG("gp4",     7, 0, 0),
-        VREG("gp1",     8, 0, 0),
-        VREG("tcxo",    9, 0, 0),
-        VREG("pa",      10, 0, 0),
-        VREG("rftx",    11, 0, 0),
-        VREG("rfrx1",   12, 0, 0),
-        VREG("rfrx2",   13, 0, 0),
-        VREG("synt",    14, 0, 0),
-        VREG("wlan",    15, 0, 0),
-        VREG("usb",     16, 0, 0),
-        VREG("boost",   17, 0, 0),
-        VREG("mmc",     18, 0, 0),
-        VREG("ruim",    19, 0, 0),
-        VREG("msmc0",   20, 0, 0),
-        VREG("gp2",     21, 0, 0),
-        VREG("gp5",     22, 0, 0),
-        VREG("gp6",     23, 0, 0),
-        VREG("rf",      24, 0, 0),
-        VREG("rf_vco",  26, 0, 0),
-        VREG("mpll",    27, 0, 0),
-        VREG("s2",      28, 0, 0),
-        VREG("s3",      29, 0, 0),
-        VREG("rfubm",   30, 0, 0),
-        VREG("ncp",     31, 0, 0),
-        VREG("gp7",     32, 0, 0),
-        VREG("gp8",     33, 0, 0),
-        VREG("gp9",     34, 0, 0),
-        VREG("gp10",    35, 0, 0),
-        VREG("gp11",    36, 0, 0),
-        VREG("gp12",    37, 0, 0),
-        VREG("gp13",    38, 0, 0),
-        VREG("gp14",    39, 0, 0),
-        VREG("gp15",    40, 0, 0),
-        VREG("gp16",    41, 0, 0),
-        VREG("gp17",    42, 0, 0),
-        VREG("s4",      43, 0, 0),
-        VREG("usb2",    44, 0, 0),
-        VREG("wlan2",   45, 0, 0),
-        VREG("xo_out",  46, 0, 0),
-        VREG("lvsw0",   47, 0, 0),
-        VREG("lvsw1",   48, 0, 0),
-};
-struct vreg *vreg_get(struct device *dev, const char *id)
-{
-        int n;
-        for (n = 0; n < ARRAY_SIZE(vregs); n++) {
-                if (!strcmp(vregs[n].name, id))
-                        return vregs + n;
-        }
-        return ERR_PTR(-ENOENT);
-}
-void vreg_put(struct vreg *vreg)
-{
-}
-int vreg_enable(struct vreg *vreg)
-{
-        unsigned id = vreg->id;
-        unsigned enable = 1;
-        if (vreg->refcnt == 0)
-                vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
-        if ((vreg->refcnt < UINT_MAX) && (!vreg->status))
-                vreg->refcnt++;
-        return vreg->status;
-}
-int vreg_disable(struct vreg *vreg)
-{
-        unsigned id = vreg->id;
-        unsigned enable = 0;
-        if (!vreg->refcnt)
-                return 0;
-        if (vreg->refcnt == 1)
-                vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
-        if (!vreg->status)
-                vreg->refcnt--;
-        return vreg->status;
-}
-int vreg_set_level(struct vreg *vreg, unsigned mv)
-{
-        unsigned id = vreg->id;
-        vreg->status = msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
-        return vreg->status;
-}
-#if defined(CONFIG_DEBUG_FS)
-static int vreg_debug_set(void *data, u64 val)
-{
-        struct vreg *vreg = data;
-        switch (val) {
-        case 0:
-                vreg_disable(vreg);
-                break;
-        case 1:
-                vreg_enable(vreg);
-                break;
-        default:
-                vreg_set_level(vreg, val);
-                break;
-        }
-        return 0;
-}
-static int vreg_debug_get(void *data, u64 *val)
-{
-        struct vreg *vreg = data;
-        if (!vreg->status)
-                *val = 0;
-        else
-                *val = 1;
-        return 0;
-}
-static int vreg_debug_count_set(void *data, u64 val)
-{
-        struct vreg *vreg = data;
-        if (val > UINT_MAX)
-                val = UINT_MAX;
-        vreg->refcnt = val;
-        return 0;
-}
-static int vreg_debug_count_get(void *data, u64 *val)
-{
-        struct vreg *vreg = data;
-        *val = vreg->refcnt;
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(vreg_count_fops, vreg_debug_count_get,
-                        vreg_debug_count_set, "%llu\n");
-static int __init vreg_debug_init(void)
-{
-        struct dentry *dent;
-        int n;
-        char name[32];
-        const char *refcnt_name = "_refcnt";
-        dent = debugfs_create_dir("vreg", 0);
-        if (IS_ERR(dent))
-                return 0;
-        for (n = 0; n < ARRAY_SIZE(vregs); n++) {
-                (void) debugfs_create_file(vregs[n].name, 0644,
-                                           dent, vregs + n, &vreg_fops);
-                strlcpy(name, vregs[n].name, sizeof(name));
-                strlcat(name, refcnt_name, sizeof(name));
-                (void) debugfs_create_file(name, 0644,
-                                           dent, vregs + n, &vreg_count_fops);
-        }
-        return 0;
-}
-device_initcall(vreg_debug_init);
-#endif
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c1e4567a5ab3..97473168d6b6 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -64,6 +64,20 @@ config MACH_ARMADA_38X
          Say 'Y' here if you want your kernel to support boards based
          on the Marvell Armada 380/385 SoC with device tree.
+config MACH_ARMADA_39X
+        bool "Marvell Armada 39x boards" if ARCH_MULTI_V7
+        select ARM_GIC
+        select ARMADA_39X_CLK
+        select CACHE_L2X0
+        select HAVE_ARM_SCU
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
+        select MACH_MVEBU_V7
+        select PINCTRL_ARMADA_39X
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 39x SoC with device tree.
 config MACH_ARMADA_XP
        bool "Marvell Armada XP boards" if ARCH_MULTI_V7
        select ARMADA_XP_CLK
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 89a139ed7d5b..afee9083ad92 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -184,7 +184,7 @@ static void __init mvebu_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static const char * const armada_370_xp_dt_compat[] = {
+static const char * const armada_370_xp_dt_compat[] __initconst = {
        "marvell,armada-370-xp",
        NULL,
 };
@@ -205,7 +205,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
        .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
-static const char * const armada_375_dt_compat[] = {
+static const char * const armada_375_dt_compat[] __initconst = {
        "marvell,armada375",
        NULL,
 };
@@ -219,7 +219,7 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
        .dt_compat      = armada_375_dt_compat,
 MACHINE_END
-static const char * const armada_38x_dt_compat[] = {
+static const char * const armada_38x_dt_compat[] __initconst = {
        "marvell,armada380",
        "marvell,armada385",
        NULL,
@@ -232,3 +232,17 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
        .restart        = mvebu_restart,
        .dt_compat      = armada_38x_dt_compat,
 MACHINE_END
+static const char * const armada_39x_dt_compat[] __initconst = {
+        "marvell,armada390",
+        "marvell,armada398",
+        NULL,
+};
+DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
+        .init_irq       = mvebu_init_irq,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_39x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index b50464ec1130..5a1741500a30 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -27,7 +27,7 @@ static void __init dove_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static const char * const dove_dt_compat[] = {
+static const char * const dove_dt_compat[] __initconst = {
        "marvell,dove",
        NULL
 };
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 6b5310828eb2..925f75f54268 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -186,7 +186,7 @@ static void __init kirkwood_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
-static const char * const kirkwood_dt_board_compat[] = {
+static const char * const kirkwood_dt_board_compat[] __initconst = {
        "marvell,kirkwood",
        NULL
 };
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 2ec1a42b4321..df0a9cc5da59 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -110,3 +110,5 @@ CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
                      &mvebu_cortex_a9_smp_ops);
 CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
                      &armada_38x_smp_ops);
+CPU_METHOD_OF_DECLARE(mvebu_armada_390_smp, "marvell,armada-390-smp",
+                      &armada_38x_smp_ops);
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 8b9f5e202ccf..4f4e22206ae5 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -415,6 +415,9 @@ static __init int armada_38x_cpuidle_init(void)
        void __iomem *mpsoc_base;
        u32 reg;
+        pr_warn("CPU idle is currently broken on Armada 38x: disabling");
+        return 0;
        np = of_find_compatible_node(NULL, NULL,
                                     "marvell,armada-380-coherency-fabric");
        if (!np)
@@ -476,6 +479,16 @@ static int __init mvebu_v7_cpu_pm_init(void)
                return 0;
        of_node_put(np);
+        /*
+         * Currently the CPU idle support for Armada 38x is broken, as
+         * the CPU hotplug uses some of the CPU idle functions it is
+         * broken too, so let's disable it
+         */
+        if (of_machine_is_compatible("marvell,armada380")) {
+                cpu_hotplug_disable();
+                pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling");
+        }
        if (of_machine_is_compatible("marvell,armadaxp"))
                ret = armada_xp_cpuidle_init();
        else if (of_machine_is_compatible("marvell,armada370"))
@@ -489,7 +502,8 @@ static int __init mvebu_v7_cpu_pm_init(void)
                return ret;
        mvebu_v7_pmsu_enable_l2_powerdown_onidle();
-        platform_device_register(&mvebu_v7_cpuidle_device);
+        if (mvebu_v7_cpuidle_device.name)
+                platform_device_register(&mvebu_v7_cpuidle_device);
        cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
        return 0;
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 34b4c0044961..dd94567c3628 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -71,13 +71,7 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
-#ifndef CONFIG_OMAP_32K_TIMER
+static unsigned short enable_dyn_sleep;
-static unsigned short enable_dyn_sleep = 0;
-#else
-static unsigned short enable_dyn_sleep = 1;
 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
                         char *buf)
@@ -90,8 +84,9 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 {
        unsigned short value;
        if (sscanf(buf, "%hu", &value) != 1 ||
-            (value != 0 && value != 1)) {
+            (value != 0 && value != 1) ||
-                printk(KERN_ERR "idle_sleep_store: Invalid value\n");
+            (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
+                pr_err("idle_sleep_store: Invalid value\n");
                return -EINVAL;
        }
        enable_dyn_sleep = value;
@@ -101,7 +96,6 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 static struct kobj_attribute sleep_while_idle_attr =
        __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
-#endif
 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
@@ -115,16 +109,11 @@ void omap1_pm_idle(void)
 {
        extern __u32 arm_idlect1_mask;
        __u32 use_idlect1 = arm_idlect1_mask;
-        int do_sleep = 0;
        local_fiq_disable();
 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
-#warning Enable 32kHz OS timer in order to allow sleep states in idle
        use_idlect1 = use_idlect1 & ~(1 << 9);
-#else
-        if (enable_dyn_sleep)
-                do_sleep = 1;
 #endif
 #ifdef CONFIG_OMAP_DM_TIMER
@@ -134,10 +123,12 @@ void omap1_pm_idle(void)
        if (omap_dma_running())
                use_idlect1 &= ~(1 << 6);
-        /* We should be able to remove the do_sleep variable and multiple
+        /*
+         * We should be able to remove the do_sleep variable and multiple
         * tests above as soon as drivers, timer and DMA code have been fixed.
-         * Even the sleep block count should become obsolete. */
+         * Even the sleep block count should become obsolete.
-        if ((use_idlect1 != ~0) || !do_sleep) {
+         */
+        if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
                __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
                if (cpu_is_omap15xx())
@@ -635,15 +626,25 @@ static const struct platform_suspend_ops omap_pm_ops = {
 static int __init omap_pm_init(void)
 {
+        int error = 0;
-#ifdef CONFIG_OMAP_32K_TIMER
-        int error;
-#endif
        if (!cpu_class_is_omap1())
                return -ENODEV;
-        printk("Power Management for TI OMAP.\n");
+        pr_info("Power Management for TI OMAP.\n");
+        if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
+                pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
+        if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
+                pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
+        if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
+            IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
+                /* OMAP16xx only */
+                pr_info("OMAP1 PM: sleep states in idle enabled\n");
+                enable_dyn_sleep = 1;
+        }
        /*
         * We copy the assembler sleep/wakeup routines to SRAM.
@@ -693,17 +694,15 @@ static int __init omap_pm_init(void)
        omap_pm_init_debugfs();
 #endif
-#ifdef CONFIG_OMAP_32K_TIMER
        error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
        if (error)
                printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
-#endif
        if (cpu_is_omap16xx()) {
                /* configure LOW_PWR pin */
                omap_cfg_reg(T20_1610_LOW_PWR);
        }
-        return 0;
+        return error;
 }
 __initcall(omap_pm_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2b8e47788062..6468f15f060c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -69,6 +69,7 @@ config SOC_DRA7XX
        select ARM_GIC
        select HAVE_ARM_ARCH_TIMER
        select IRQ_CROSSBAR
+        select ARM_ERRATA_798181 if SMP
 config ARCH_OMAP2PLUS
        bool
@@ -80,6 +81,7 @@ config ARCH_OMAP2PLUS
        select GENERIC_IRQ_CHIP
        select MACH_OMAP_GENERIC
        select MEMORY
+        select MFD_SYSCON
        select OMAP_DM_TIMER
        select OMAP_GPMC
        select PINCTRL
@@ -175,12 +177,6 @@ config MACH_OMAP3_BEAGLE
        default y
        select OMAP_PACKAGE_CBB
-config MACH_DEVKIT8000
-        bool "DEVKIT8000 board"
-        depends on ARCH_OMAP3
-        default y
-        select OMAP_PACKAGE_CUS
 config MACH_OMAP_LDP
        bool "OMAP3 LDP board"
        depends on ARCH_OMAP3
@@ -225,12 +221,6 @@ config MACH_OMAP3_PANDORA
        select OMAP_PACKAGE_CBB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-config MACH_TOUCHBOOK
-        bool "OMAP3 Touch Book"
-        depends on ARCH_OMAP3
-        default y
-        select OMAP_PACKAGE_CBB
 config MACH_NOKIA_N810
       bool
@@ -260,12 +250,6 @@ config MACH_CM_T35
 config MACH_CM_T3730
       bool
-config MACH_SBC3530
-        bool "OMAP3 SBC STALKER board"
-        depends on ARCH_OMAP3
-        default y
-        select OMAP_PACKAGE_CUS
 config OMAP3_SDRC_AC_TIMING
        bool "Enable SDRC AC timing register changes"
        depends on ARCH_OMAP3
@@ -278,27 +262,6 @@ config OMAP3_SDRC_AC_TIMING
          wish to say no.  Selecting yes without understanding what is
          going on could result in system crashes;
-config OMAP4_ERRATA_I688
-        bool "OMAP4 errata: Async Bridge Corruption"
-        depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
-        select ARCH_HAS_BARRIERS
-        help
-          If a data is stalled inside asynchronous bridge because of back
-          pressure, it may be accepted multiple times, creating pointer
-          misalignment that will corrupt next transfers on that data path
-          until next reset of the system (No recovery procedure once the
-          issue is hit, the path remains consistently broken). Async bridge
-          can be found on path between MPU to EMIF and MPU to L3 interconnect.
-          This situation can happen only when the idle is initiated by a
-          Master Request Disconnection (which is trigged by software when
-          executing WFI on CPU).
-          The work-around for this errata needs all the initiators connected
-          through async bridge must ensure that data path is properly drained
-          before issuing WFI. This condition will be met if one Strongly ordered
-          access is performed to the target right before executing the WFI.
-          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
-          IO barrier ensure that there is no synchronisation loss on initiators
-          operating on both interconnect port simultaneously.
 endmenu
 endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b83f18fcec9b..ec002bd4af77 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -243,7 +243,6 @@ obj-$(CONFIG_SOC_OMAP2420)		+= msdi.o
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o pdata-quirks.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
 obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
 obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
@@ -254,9 +253,6 @@ obj-$(CONFIG_MACH_NOKIA_RX51)		+= board-rx51.o sdram-nokia.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51-peripherals.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51-video.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
-obj-$(CONFIG_MACH_TOUCHBOOK)            += board-omap3touchbook.o
-obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
 # Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
deleted file mode 100644
index d8e4f346936a..000000000000
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ /dev/null
@@ -1,654 +0,0 @@
-/*
- * board-devkit8000.c - TimLL Devkit8000
- *
- * Copyright (C) 2009 Kim Botherway
- * Copyright (C) 2010 Thomas Weber
- *
- * Modified from mach-omap2/board-omap3beagle.c
- *
- * Initial code: Syed Mohammed Khasim
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/mmc/host.h>
-#include <linux/usb/phy.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include "id.h"
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include "common.h"
-#include "gpmc.h"
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include <video/omapdss.h>
-#include <video/omap-panel-data.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/dm9000.h>
-#include <linux/interrupt.h>
-#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mux.h"
-#include "hsmmc.h"
-#include "board-flash.h"
-#include "common-board-devices.h"
-#define NAND_CS                 0
-#define OMAP_DM9000_GPIO_IRQ    25
-#define OMAP3_DEVKIT_TS_GPIO    27
-static struct mtd_partition devkit8000_nand_partitions[] = {
-        /* All the partition sizes are listed in terms of NAND block size */
-        {
-                .name           = "X-Loader",
-                .offset         = 0,
-                .size           = 4 * NAND_BLOCK_SIZE,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-                .size           = 15 * NAND_BLOCK_SIZE,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot Env",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
-                .size           = 1 * NAND_BLOCK_SIZE,
-        },
-        {
-                .name           = "Kernel",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
-                .size           = 32 * NAND_BLOCK_SIZE,
-        },
-        {
-                .name           = "File System",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = 29,
-                .deferred       = true,
-        },
-        {}      /* Terminator */
-};
-static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-/* ads7846 on SPI */
-static struct regulator_consumer_supply devkit8000_vio_supply[] = {
-        REGULATOR_SUPPLY("vcc", "spi2.0"),
-};
-static const struct display_timing devkit8000_lcd_videomode = {
-        .pixelclock     = { 0, 40000000, 0 },
-        .hactive = { 0, 800, 0 },
-        .hfront_porch = { 0, 1, 0 },
-        .hback_porch = { 0, 1, 0 },
-        .hsync_len = { 0, 48, 0 },
-        .vactive = { 0, 480, 0 },
-        .vfront_porch = { 0, 12, 0 },
-        .vback_porch = { 0, 25, 0 },
-        .vsync_len = { 0, 3, 0 },
-        .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-                DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-static struct panel_dpi_platform_data devkit8000_lcd_pdata = {
-        .name                   = "lcd",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .display_timing         = &devkit8000_lcd_videomode,
-        .enable_gpio            = -1,   /* filled in code */
-        .backlight_gpio         = -1,
-};
-static struct platform_device devkit8000_lcd_device = {
-        .name                   = "panel-dpi",
-        .id                     = 0,
-        .dev.platform_data      = &devkit8000_lcd_pdata,
-};
-static struct connector_dvi_platform_data devkit8000_dvi_connector_pdata = {
-        .name                   = "dvi",
-        .source                 = "tfp410.0",
-        .i2c_bus_num            = 1,
-};
-static struct platform_device devkit8000_dvi_connector_device = {
-        .name                   = "connector-dvi",
-        .id                     = 0,
-        .dev.platform_data      = &devkit8000_dvi_connector_pdata,
-};
-static struct encoder_tfp410_platform_data devkit8000_tfp410_pdata = {
-        .name                   = "tfp410.0",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .power_down_gpio        = -1,   /* filled in code */
-};
-static struct platform_device devkit8000_tfp410_device = {
-        .name                   = "tfp410",
-        .id                     = 0,
-        .dev.platform_data      = &devkit8000_tfp410_pdata,
-};
-static struct connector_atv_platform_data devkit8000_tv_pdata = {
-        .name = "tv",
-        .source = "venc.0",
-        .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .invert_polarity = false,
-};
-static struct platform_device devkit8000_tv_connector_device = {
-        .name                   = "connector-analog-tv",
-        .id                     = 0,
-        .dev.platform_data      = &devkit8000_tv_pdata,
-};
-static struct omap_dss_board_info devkit8000_dss_data = {
-        .default_display_name = "lcd",
-};
-static uint32_t board_keymap[] = {
-        KEY(0, 0, KEY_1),
-        KEY(1, 0, KEY_2),
-        KEY(2, 0, KEY_3),
-        KEY(0, 1, KEY_4),
-        KEY(1, 1, KEY_5),
-        KEY(2, 1, KEY_6),
-        KEY(3, 1, KEY_F5),
-        KEY(0, 2, KEY_7),
-        KEY(1, 2, KEY_8),
-        KEY(2, 2, KEY_9),
-        KEY(3, 2, KEY_F6),
-        KEY(0, 3, KEY_F7),
-        KEY(1, 3, KEY_0),
-        KEY(2, 3, KEY_F8),
-        PERSISTENT_KEY(4, 5),
-        KEY(4, 4, KEY_VOLUMEUP),
-        KEY(5, 5, KEY_VOLUMEDOWN),
-        0
-};
-static struct matrix_keymap_data board_map_data = {
-        .keymap                 = board_keymap,
-        .keymap_size            = ARRAY_SIZE(board_keymap),
-};
-static struct twl4030_keypad_data devkit8000_kp_data = {
-        .keymap_data    = &board_map_data,
-        .rows           = 6,
-        .cols           = 6,
-        .rep            = 1,
-};
-static struct gpio_led gpio_leds[];
-static int devkit8000_twl_gpio_setup(struct device *dev,
-                unsigned gpio, unsigned ngpio)
-{
-        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        mmc[0].gpio_cd = gpio + 0;
-        omap_hsmmc_late_init(mmc);
-        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-        /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */
-        devkit8000_lcd_pdata.enable_gpio = gpio + TWL4030_GPIO_MAX + 0;
-        /* gpio + 7 is "DVI_PD" (out, active low) */
-        devkit8000_tfp410_pdata.power_down_gpio = gpio + 7;
-        return 0;
-}
-static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
-        .use_leds       = true,
-        .pulldowns      = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
-                                | BIT(15) | BIT(16) | BIT(17),
-        .setup          = devkit8000_twl_gpio_setup,
-};
-static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
-};
-/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
-static struct regulator_init_data devkit8000_vmmc1 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vmmc1_supply),
-        .consumer_supplies      = devkit8000_vmmc1_supply,
-};
-/* VPLL1 for digital video outputs */
-static struct regulator_init_data devkit8000_vpll1 = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vpll1_supplies),
-        .consumer_supplies      = devkit8000_vpll1_supplies,
-};
-/* VAUX4 for ads7846 and nubs */
-static struct regulator_init_data devkit8000_vio = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(devkit8000_vio_supply),
-        .consumer_supplies      = devkit8000_vio_supply,
-};
-static struct twl4030_platform_data devkit8000_twldata = {
-        /* platform_data for children goes here */
-        .gpio           = &devkit8000_gpio_data,
-        .vmmc1          = &devkit8000_vmmc1,
-        .vpll1          = &devkit8000_vpll1,
-        .vio            = &devkit8000_vio,
-        .keypad         = &devkit8000_kp_data,
-};
-static int __init devkit8000_i2c_init(void)
-{
-        omap3_pmic_get_config(&devkit8000_twldata,
-                          TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
-                          TWL_COMMON_REGULATOR_VDAC);
-        omap3_pmic_init("tps65930", &devkit8000_twldata);
-        /* Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 400, NULL, 0);
-        return 0;
-}
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = 186,
-                .active_low             = true,
-        },
-        {
-                .name                   = "led2",
-                .default_trigger        = "mmc0",
-                .gpio                   = 163,
-                .active_low             = true,
-        },
-        {
-                .name                   = "ledB",
-                .default_trigger        = "none",
-                .gpio                   = 153,
-                .active_low             = true,
-        },
-        {
-                .name                   = "led3",
-                .default_trigger        = "none",
-                .gpio                   = 164,
-                .active_low             = true,
-        },
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        },
-};
-static struct gpio_keys_button gpio_buttons[] = {
-        {
-                .code                   = BTN_EXTRA,
-                .gpio                   = 26,
-                .desc                   = "user",
-                .wakeup                 = 1,
-        },
-};
-static struct gpio_keys_platform_data gpio_key_info = {
-        .buttons        = gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-};
-static struct platform_device keys_gpio = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_key_info,
-        },
-};
-#define OMAP_DM9000_BASE        0x2c000000
-static struct resource omap_dm9000_resources[] = {
-        [0] = {
-                .start          = OMAP_DM9000_BASE,
-                .end            = (OMAP_DM9000_BASE + 0x4 - 1),
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = (OMAP_DM9000_BASE + 0x400),
-                .end            = (OMAP_DM9000_BASE + 0x400 + 0x4 - 1),
-                .flags          = IORESOURCE_MEM,
-        },
-        [2] = {
-                .flags          = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-        },
-};
-static struct dm9000_plat_data omap_dm9000_platdata = {
-        .flags = DM9000_PLATF_16BITONLY,
-};
-static struct platform_device omap_dm9000_dev = {
-        .name = "dm9000",
-        .id = -1,
-        .num_resources  = ARRAY_SIZE(omap_dm9000_resources),
-        .resource       = omap_dm9000_resources,
-        .dev = {
-                .platform_data = &omap_dm9000_platdata,
-        },
-};
-static void __init omap_dm9000_init(void)
-{
-        unsigned char *eth_addr = omap_dm9000_platdata.dev_addr;
-        struct omap_die_id odi;
-        int ret;
-        ret = gpio_request_one(OMAP_DM9000_GPIO_IRQ, GPIOF_IN, "dm9000 irq");
-        if (ret < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n",
-                        OMAP_DM9000_GPIO_IRQ);
-                return;
-        }
-        /* init the mac address using DIE id */
-        omap_get_die_id(&odi);
-        eth_addr[0] = 0x02; /* locally administered */
-        eth_addr[1] = odi.id_1 & 0xff;
-        eth_addr[2] = (odi.id_0 & 0xff000000) >> 24;
-        eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16;
-        eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8;
-        eth_addr[5] = (odi.id_0 & 0x000000ff);
-}
-static struct platform_device *devkit8000_devices[] __initdata = {
-        &leds_gpio,
-        &keys_gpio,
-        &omap_dm9000_dev,
-        &devkit8000_lcd_device,
-        &devkit8000_tfp410_device,
-        &devkit8000_dvi_connector_device,
-        &devkit8000_tv_connector_device,
-};
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-};
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* nCS and IRQ for Devkit8000 ethernet */
-        OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0),
-        OMAP3_MUX(ETK_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
-        /* McSPI 2*/
-        OMAP3_MUX(MCSPI2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCSPI2_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(MCSPI2_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCSPI2_CS0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(MCSPI2_CS1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        /* PENDOWN GPIO */
-        OMAP3_MUX(ETK_D13, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
-        /* mUSB */
-        OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* USB 1 */
-        OMAP3_MUX(ETK_CTL, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(ETK_D8, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D9, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D0, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D2, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        OMAP3_MUX(ETK_D7, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        /* MMC 1 */
-        OMAP3_MUX(SDMMC1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(SDMMC1_DAT7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McBSP 2 */
-        OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        /* I2C 1 */
-        OMAP3_MUX(I2C1_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(I2C1_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* I2C 2 */
-        OMAP3_MUX(I2C2_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(I2C2_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* I2C 3 */
-        OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* I2C 4 */
-        OMAP3_MUX(I2C4_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(I2C4_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* serial ports */
-        OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* DSS */
-        OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        /* expansion port */
-        /* McSPI 1 */
-        OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP3_MUX(MCSPI1_CS3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        /* HDQ */
-        OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McSPI4 */
-        OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
-        /* MMC 2 */
-        OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        /* I2C3 */
-        OMAP3_MUX(I2C3_SCL, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(I2C3_SDA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* TPS IRQ */
-        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
-                        OMAP_PIN_INPUT_PULLUP),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-static void __init devkit8000_init(void)
-{
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-        omap_serial_init();
-        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-        omap_dm9000_init();
-        omap_hsmmc_init(mmc);
-        devkit8000_i2c_init();
-        omap_dm9000_resources[2].start = gpio_to_irq(OMAP_DM9000_GPIO_IRQ);
-        platform_add_devices(devkit8000_devices,
-                        ARRAY_SIZE(devkit8000_devices));
-        omap_display_init(&devkit8000_dss_data);
-        omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
-        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
-        usb_musb_init(NULL);
-        usbhs_init(&usbhs_bdata);
-        board_nand_init(devkit8000_nand_partitions,
-                        ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
-                        NAND_BUSWIDTH_16, NULL);
-        omap_twl4030_audio_init("omap3beagle", NULL);
-        /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
-}
-MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap3_map_io,
-        .init_early     = omap35xx_init_early,
-        .init_irq       = omap3_init_irq,
-        .init_machine   = devkit8000_init,
-        .init_late      = omap35xx_init_late,
-        .init_time      = omap3_secure_sync32k_timer_init,
-        .restart        = omap3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
deleted file mode 100644
index 6311f4b1ee44..000000000000
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-omap3evm.c
- *
- * Copyright (C) 2008 Guangzhou EMA-Tech
- *
- * Modified from mach-omap2/board-omap3evm.c
- *
- * Initial code: Syed Mohammed Khasim
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/mmc/host.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/interrupt.h>
-#include <linux/smsc911x.h>
-#include <linux/platform_data/at24.h>
-#include <linux/usb/phy.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include "common.h"
-#include "gpmc.h"
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include <video/omapdss.h>
-#include <video/omap-panel-data.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mux.h"
-#include "hsmmc.h"
-#include "common-board-devices.h"
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include "gpmc-smsc911x.h"
-#define OMAP3STALKER_ETHR_START 0x2c000000
-#define OMAP3STALKER_ETHR_SIZE  1024
-#define OMAP3STALKER_ETHR_GPIO_IRQ      19
-#define OMAP3STALKER_SMC911X_CS 5
-static struct omap_smsc911x_platform_data smsc911x_cfg = {
-        .cs             = OMAP3STALKER_SMC911X_CS,
-        .gpio_irq       = OMAP3STALKER_ETHR_GPIO_IRQ,
-        .gpio_reset     = -EINVAL,
-        .flags          = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
-};
-static inline void __init omap3stalker_init_eth(void)
-{
-        omap_mux_init_gpio(19, OMAP_PIN_INPUT_PULLUP);
-        gpmc_smsc911x_init(&smsc911x_cfg);
-}
-#else
-static inline void __init omap3stalker_init_eth(void)
-{
-        return;
-}
-#endif
-/*
- * OMAP3 DSS control signals
- */
-#define DSS_ENABLE_GPIO 199
-#define LCD_PANEL_BKLIGHT_GPIO  210
-#define ENABLE_VPLL2_DEV_GRP    0xE0
-static void __init omap3_stalker_display_init(void)
-{
-        return;
-}
-static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = {
-        .name                   = "dvi",
-        .source                 = "tfp410.0",
-        .i2c_bus_num            = -1,
-};
-static struct platform_device omap3stalker_dvi_connector_device = {
-        .name                   = "connector-dvi",
-        .id                     = 0,
-        .dev.platform_data      = &omap3stalker_dvi_connector_pdata,
-};
-static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = {
-        .name                   = "tfp410.0",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .power_down_gpio        = DSS_ENABLE_GPIO,
-};
-static struct platform_device omap3stalker_tfp410_device = {
-        .name                   = "tfp410",
-        .id                     = 0,
-        .dev.platform_data      = &omap3stalker_tfp410_pdata,
-};
-static struct connector_atv_platform_data omap3stalker_tv_pdata = {
-        .name = "tv",
-        .source = "venc.0",
-        .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
-        .invert_polarity = false,
-};
-static struct platform_device omap3stalker_tv_connector_device = {
-        .name                   = "connector-analog-tv",
-        .id                     = 0,
-        .dev.platform_data      = &omap3stalker_tv_pdata,
-};
-static struct omap_dss_board_info omap3_stalker_dss_data = {
-        .default_display_name = "dvi",
-};
-static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
-};
-/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
-static struct regulator_init_data omap3stalker_vmmc1 = {
-        .constraints            = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(omap3stalker_vmmc1_supply),
-        .consumer_supplies      = omap3stalker_vmmc1_supply,
-};
-/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
-static struct regulator_init_data omap3stalker_vsim = {
-        .constraints            = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 3000000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(omap3stalker_vsim_supply),
-        .consumer_supplies      = omap3stalker_vsim_supply,
-};
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = 23,
-                .deferred       = true,
-         },
-        {}                      /* Terminator */
-};
-static struct gpio_keys_button gpio_buttons[] = {
-        {
-         .code          = BTN_EXTRA,
-         .gpio          = 18,
-         .desc          = "user",
-         .wakeup        = 1,
-         },
-};
-static struct gpio_keys_platform_data gpio_key_info = {
-        .buttons        = gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-};
-static struct platform_device keys_gpio = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &gpio_key_info,
-        },
-};
-static struct gpio_led gpio_leds[] = {
-        {
-         .name                  = "stalker:D8:usr0",
-         .default_trigger       = "default-on",
-         .gpio                  = 126,
-         },
-        {
-         .name                  = "stalker:D9:usr1",
-         .default_trigger       = "default-on",
-         .gpio                  = 127,
-         },
-        {
-         .name                  = "stalker:D3:mmc0",
-         .gpio                  = -EINVAL,      /* gets replaced */
-         .active_low            = true,
-         .default_trigger       = "mmc0",
-         },
-        {
-         .name                  = "stalker:D4:heartbeat",
-         .gpio                  = -EINVAL,      /* gets replaced */
-         .active_low            = true,
-         .default_trigger       = "heartbeat",
-         },
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        },
-};
-static int
-omap3stalker_twl_gpio_setup(struct device *dev,
-                            unsigned gpio, unsigned ngpio)
-{
-        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        mmc[0].gpio_cd = gpio + 0;
-        omap_hsmmc_late_init(mmc);
-        /*
-         * Most GPIOs are for USB OTG.  Some are mostly sent to
-         * the P2 connector; notably LEDA for the LCD backlight.
-         */
-        /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
-                         "EN_LCD_BKL");
-        /* gpio + 7 == DVI Enable */
-        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
-        /* TWL4030_GPIO_MAX + 1 == ledB (out, mmc0) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-        /* GPIO + 13 == ledsync (out, heartbeat) */
-        gpio_leds[3].gpio = gpio + 13;
-        platform_device_register(&leds_gpio);
-        return 0;
-}
-static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
-        .use_leds       = true,
-        .setup          = omap3stalker_twl_gpio_setup,
-};
-static uint32_t board_keymap[] = {
-        KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_DOWN),
-        KEY(0, 2, KEY_ENTER),
-        KEY(0, 3, KEY_M),
-        KEY(1, 0, KEY_RIGHT),
-        KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_I),
-        KEY(1, 3, KEY_N),
-        KEY(2, 0, KEY_A),
-        KEY(2, 1, KEY_E),
-        KEY(2, 2, KEY_J),
-        KEY(2, 3, KEY_O),
-        KEY(3, 0, KEY_B),
-        KEY(3, 1, KEY_F),
-        KEY(3, 2, KEY_K),
-        KEY(3, 3, KEY_P)
-};
-static struct matrix_keymap_data board_map_data = {
-        .keymap         = board_keymap,
-        .keymap_size    = ARRAY_SIZE(board_keymap),
-};
-static struct twl4030_keypad_data omap3stalker_kp_data = {
-        .keymap_data    = &board_map_data,
-        .rows           = 4,
-        .cols           = 4,
-        .rep            = 1,
-};
-static struct twl4030_platform_data omap3stalker_twldata = {
-        /* platform_data for children goes here */
-        .keypad         = &omap3stalker_kp_data,
-        .gpio           = &omap3stalker_gpio_data,
-        .vmmc1          = &omap3stalker_vmmc1,
-        .vsim           = &omap3stalker_vsim,
-};
-static struct at24_platform_data fram_info = {
-        .byte_len       = (64 * 1024) / 8,
-        .page_size      = 8192,
-        .flags          = AT24_FLAG_ADDR16 | AT24_FLAG_IRUGO,
-};
-static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
-        {
-         I2C_BOARD_INFO("24c64", 0x50),
-         .flags         = I2C_CLIENT_WAKE,
-         .platform_data = &fram_info,
-         },
-};
-static int __init omap3_stalker_i2c_init(void)
-{
-        omap3_pmic_get_config(&omap3stalker_twldata,
-                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
-                        TWL_COMMON_PDATA_AUDIO,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-        omap3stalker_twldata.vdac->constraints.apply_uV = true;
-        omap3stalker_twldata.vpll2->constraints.apply_uV = true;
-        omap3stalker_twldata.vpll2->constraints.name = "VDVI";
-        omap3_pmic_init("twl4030", &omap3stalker_twldata);
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
-                              ARRAY_SIZE(omap3stalker_i2c_boardinfo3));
-        return 0;
-}
-#define OMAP3_STALKER_TS_GPIO   175
-static struct usbhs_phy_data phy_data[] __initdata = {
-        {
-                .port = 2,
-                .reset_gpio = 21,
-                .vcc_gpio = -EINVAL,
-        },
-};
-static struct platform_device *omap3_stalker_devices[] __initdata = {
-        &keys_gpio,
-        &omap3stalker_tfp410_device,
-        &omap3stalker_dvi_connector_device,
-        &omap3stalker_tv_connector_device,
-};
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-};
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
-                  OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
-                  OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        {.reg_offset = OMAP_MUX_TERMINATOR},
-};
-#endif
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
-};
-static void __init omap3_stalker_init(void)
-{
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
-        omap_hsmmc_init(mmc);
-        omap3_stalker_i2c_init();
-        platform_add_devices(omap3_stalker_devices,
-                             ARRAY_SIZE(omap3_stalker_devices));
-        omap_display_init(&omap3_stalker_dss_data);
-        omap_serial_init();
-        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
-        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
-        usb_musb_init(NULL);
-        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-        usbhs_init(&usbhs_bdata);
-        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
-        omap_mux_init_gpio(21, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(18, OMAP_PIN_INPUT_PULLUP);
-        omap3stalker_init_eth();
-        omap3_stalker_display_init();
-/* Ensure SDRC pins are mux'd for self-refresh */
-        omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT);
-}
-MACHINE_START(SBC3530, "OMAP3 STALKER")
-        /* Maintainer: Jason Lam -lzg@ema-tech.com */
-        .atag_offset            = 0x100,
-        .map_io                 = omap3_map_io,
-        .init_early             = omap35xx_init_early,
-        .init_irq               = omap3_init_irq,
-        .init_machine           = omap3_stalker_init,
-        .init_late              = omap35xx_init_late,
-        .init_time              = omap3_secure_sync32k_timer_init,
-        .restart                = omap3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
deleted file mode 100644
index a01993e5500f..000000000000
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-omap3touchbook.c
- *
- * Copyright (C) 2009 Always Innovating
- *
- * Modified from mach-omap2/board-omap3beagleboard.c
- *
- * Initial code: Grégoire Gentil, Tim Yamin
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/mmc/host.h>
-#include <linux/usb/phy.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/system_info.h>
-#include "common.h"
-#include "gpmc.h"
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include "mux.h"
-#include "hsmmc.h"
-#include "board-flash.h"
-#include "common-board-devices.h"
-#include <asm/setup.h>
-#define OMAP3_AC_GPIO           136
-#define OMAP3_TS_GPIO           162
-#define TB_BL_PWM_TIMER         9
-#define TB_KILL_POWER_GPIO      168
-#define NAND_CS                 0
-static unsigned long touchbook_revision;
-static struct mtd_partition omap3touchbook_nand_partitions[] = {
-        /* All the partition sizes are listed in terms of NAND block size */
-        {
-                .name           = "X-Loader",
-                .offset         = 0,
-                .size           = 4 * NAND_BLOCK_SIZE,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-                .size           = 15 * NAND_BLOCK_SIZE,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot Env",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
-                .size           = 1 * NAND_BLOCK_SIZE,
-        },
-        {
-                .name           = "Kernel",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
-                .size           = 32 * NAND_BLOCK_SIZE,
-        },
-        {
-                .name           = "File System",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-#include "sdram-micron-mt46h32m32lf-6.h"
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = 29,
-                .deferred       = true,
-        },
-        {}      /* Terminator */
-};
-static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-static struct regulator_consumer_supply touchbook_vsim_supply[] = {
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
-};
-static struct gpio_led gpio_leds[];
-static int touchbook_twl_gpio_setup(struct device *dev,
-                unsigned gpio, unsigned ngpio)
-{
-        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        mmc[0].gpio_cd = gpio + 0;
-        omap_hsmmc_late_init(mmc);
-        /* REVISIT: need ehci-omap hooks for external VBUS
-         * power switch and overcurrent detect
-         */
-        gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC");
-        /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
-                         "nEN_USB_PWR");
-        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-        return 0;
-}
-static struct twl4030_gpio_platform_data touchbook_gpio_data = {
-        .use_leds       = true,
-        .pullups        = BIT(1),
-        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
-                                | BIT(15) | BIT(16) | BIT(17),
-        .setup          = touchbook_twl_gpio_setup,
-};
-static struct regulator_consumer_supply touchbook_vdac_supply[] = {
-{
-        .supply         = "vdac",
-},
-};
-static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
-{
-        .supply         = "vdvi",
-},
-};
-/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
-static struct regulator_init_data touchbook_vmmc1 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(touchbook_vmmc1_supply),
-        .consumer_supplies      = touchbook_vmmc1_supply,
-};
-/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
-static struct regulator_init_data touchbook_vsim = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 3000000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(touchbook_vsim_supply),
-        .consumer_supplies      = touchbook_vsim_supply,
-};
-static struct twl4030_platform_data touchbook_twldata = {
-        /* platform_data for children goes here */
-        .gpio           = &touchbook_gpio_data,
-        .vmmc1          = &touchbook_vmmc1,
-        .vsim           = &touchbook_vsim,
-};
-static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("bq27200", 0x55),
-        },
-};
-static int __init omap3_touchbook_i2c_init(void)
-{
-        /* Standard TouchBook bus */
-        omap3_pmic_get_config(&touchbook_twldata,
-                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-        touchbook_twldata.vdac->num_consumer_supplies =
-                                        ARRAY_SIZE(touchbook_vdac_supply);
-        touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
-        touchbook_twldata.vpll2->constraints.name = "VDVI";
-        touchbook_twldata.vpll2->num_consumer_supplies =
-                                        ARRAY_SIZE(touchbook_vdvi_supply);
-        touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
-        omap3_pmic_init("twl4030", &touchbook_twldata);
-        /* Additional TouchBook bus */
-        omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
-                        ARRAY_SIZE(touchBook_i2c_boardinfo));
-        return 0;
-}
-static struct ads7846_platform_data ads7846_pdata = {
-        .x_min                  = 100,
-        .y_min                  = 265,
-        .x_max                  = 3950,
-        .y_max                  = 3750,
-        .x_plate_ohms           = 40,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 5,
-        .debounce_rep           = 1,
-        .gpio_pendown           = OMAP3_TS_GPIO,
-        .keep_vref_on           = 1,
-};
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "touchbook::usr0",
-                .default_trigger        = "heartbeat",
-                .gpio                   = 150,
-        },
-        {
-                .name                   = "touchbook::usr1",
-                .default_trigger        = "mmc0",
-                .gpio                   = 149,
-        },
-        {
-                .name                   = "touchbook::pmu_stat",
-                .gpio                   = -EINVAL,      /* gets replaced */
-                .active_low             = true,
-        },
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        },
-};
-static struct gpio_keys_button gpio_buttons[] = {
-        {
-                .code                   = BTN_EXTRA,
-                .gpio                   = 7,
-                .desc                   = "user",
-                .wakeup                 = 1,
-        },
-        {
-                .code                   = KEY_POWER,
-                .gpio                   = 183,
-                .desc                   = "power",
-                .wakeup                 = 1,
-        },
-};
-static struct gpio_keys_platform_data gpio_key_info = {
-        .buttons        = gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-};
-static struct platform_device keys_gpio = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_key_info,
-        },
-};
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-static struct usbhs_phy_data phy_data[] __initdata = {
-        {
-                .port = 2,
-                .reset_gpio = 147,
-                .vcc_gpio = -EINVAL,
-        },
-};
-static struct platform_device *omap3_touchbook_devices[] __initdata = {
-        &leds_gpio,
-        &keys_gpio,
-};
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-};
-static void omap3_touchbook_poweroff(void)
-{
-        int pwr_off = TB_KILL_POWER_GPIO;
-        if (gpio_request_one(pwr_off, GPIOF_OUT_INIT_LOW, "DVI reset") < 0)
-                printk(KERN_ERR "Unable to get kill power GPIO\n");
-}
-static int __init early_touchbook_revision(char *p)
-{
-        if (!p)
-                return 0;
-        return kstrtoul(p, 10, &touchbook_revision);
-}
-early_param("tbr", early_touchbook_revision);
-static void __init omap3_touchbook_init(void)
-{
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        pm_power_off = omap3_touchbook_poweroff;
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
-                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
-                mmc[0].gpio_wp = 23;
-        } else {
-                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
-        }
-        omap_hsmmc_init(mmc);
-        omap3_touchbook_i2c_init();
-        platform_add_devices(omap3_touchbook_devices,
-                        ARRAY_SIZE(omap3_touchbook_devices));
-        omap_serial_init();
-        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
-                                  mt46h32m32lf6_sdrc_params);
-        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-        /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_request_one(176, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
-        /* Touchscreen and accelerometer */
-        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
-        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
-        usb_musb_init(NULL);
-        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-        usbhs_init(&usbhs_bdata);
-        board_nand_init(omap3touchbook_nand_partitions,
-                        ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
-                        NAND_BUSWIDTH_16, NULL);
-        /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
-}
-MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
-        /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap3_map_io,
-        .init_early     = omap3430_init_early,
-        .init_irq       = omap3_init_irq,
-        .init_machine   = omap3_touchbook_init,
-        .init_late      = omap3430_init_late,
-        .init_time      = omap3_secure_sync32k_timer_init,
-        .restart        = omap3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5c37ae..a699d7169307 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,9 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/bootmem.h>
 #include <asm/cpu.h>
 #include <trace/events/power.h>
@@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
 static bool clkdm_control = true;
 static LIST_HEAD(clk_hw_omap_clocks);
-void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+struct clk_iomap {
+        struct regmap *regmap;
+        void __iomem *mem;
+};
+static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
+static void clk_memmap_writel(u32 val, void __iomem *reg)
+{
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+        if (io->regmap)
+                regmap_write(io->regmap, r->offset, val);
+        else
+                writel_relaxed(val, io->mem + r->offset);
+}
+static u32 clk_memmap_readl(void __iomem *reg)
+{
+        u32 val;
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+        if (io->regmap)
+                regmap_read(io->regmap, r->offset, &val);
+        else
+                val = readl_relaxed(io->mem + r->offset);
+        return val;
+}
 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
 {
-        if (clk->flags & MEMMAP_ADDRESSING) {
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
-                writel_relaxed(val, clk_memmaps[r->index] + r->offset);
-        } else {
                writel_relaxed(val, reg);
-        }
+        else
+                clk_memmap_writel(val, reg);
 }
 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
 {
-        u32 val;
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
+                return readl_relaxed(reg);
+        else
+                return clk_memmap_readl(reg);
+}
-        if (clk->flags & MEMMAP_ADDRESSING) {
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        .clk_readl = clk_memmap_readl,
-                val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+        .clk_writel = clk_memmap_writel,
-        } else {
+};
-                val = readl_relaxed(reg);
-        }
-        return val;
+/**
+ * omap2_clk_provider_init - initialize a clock provider
+ * @match_table: DT device table to match for devices to init
+ * @np: device node pointer for the this clock provider
+ * @index: index for the clock provider
+ + @syscon: syscon regmap pointer
+ * @mem: iomem pointer for the clock provider memory area, only used if
+ *       syscon is not provided
+ *
+ * Initializes a clock provider module (CM/PRM etc.), registering
+ * the memory mapping at specified index and initializing the
+ * low level driver infrastructure. Returns 0 in success.
+ */
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem)
+{
+        struct clk_iomap *io;
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+        io = kzalloc(sizeof(*io), GFP_KERNEL);
+        io->regmap = syscon;
+        io->mem = mem;
+        clk_memmaps[index] = io;
+        ti_dt_clk_init_provider(np, index);
+        return 0;
+}
+/**
+ * omap2_clk_legacy_provider_init - initialize a legacy clock provider
+ * @index: index for the clock provider
+ * @mem: iomem pointer for the clock provider memory area
+ *
+ * Initializes a legacy clock provider memory mapping.
+ */
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
+{
+        struct clk_iomap *io;
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+        io = memblock_virt_alloc(sizeof(*io), 0);
+        io->mem = mem;
+        clk_memmaps[index] = io;
 }
 /*
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f96000..652ed0ab86ec 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
-extern void __iomem *clk_memmaps[];
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+struct regmap;
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem);
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
 void __init ti_clk_init_features(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87a79b6..1fe3e6b833d2 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
 extern int cm_register(struct cm_ll_data *cld);
 extern int cm_unregister(struct cm_ll_data *cld);
+int omap_cm_init(void);
+int omap2_cm_base_init(void);
 # endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9dcd05..3e5fd3587eb1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
        .wait_module_ready      = &omap2xxx_cm_wait_module_ready,
 };
-int __init omap2xxx_cm_init(void)
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
 {
        return cm_register(&omap2xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c597b0e1..7b8c79c0ce27 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
                                         u32 mdm);
-extern int __init omap2xxx_cm_init(void);
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac784278..7b181f929525 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
        .module_disable         = &am33xx_cm_module_disable,
 };
-int __init am33xx_cm_init(void)
+int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
 {
        return cm_register(&am33xx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2bc9d9..a91f7d282455 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
 #include "cm.h"
 #include "cm-regbits-33xx.h"
+#include "prcm-common.h"
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
@@ -374,6 +375,6 @@
 #ifndef __ASSEMBLER__
-int am33xx_cm_init(void);
+int am33xx_cm_init(const struct omap_prcm_init_data *data);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f035f9..187fa4386718 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
        .wait_module_ready      = &omap3xxx_cm_wait_module_ready,
 };
-int __init omap3xxx_cm_init(void)
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
        return cm_register(&omap3xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a8581c0c4..bc444e2080a1 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
-extern int __init omap3xxx_cm_init(void);
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a4af19..309a4c913448 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
 #define OMAP4_CM_CLKSTCTRL                              0x0000
 #define OMAP4_CM_STATICDEP                              0x0004
-void omap_cm_base_init(void);
+int omap4_cm_init(const struct omap_prcm_init_data *data);
-int omap4_cm_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fcedc48..23e8bcec34e3 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,14 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/bug.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include "cm2xxx.h"
 #include "cm3xxx.h"
+#include "cm33xx.h"
 #include "cm44xx.h"
+#include "clock.h"
 /*
 * cm_ll_data: function pointers to SoC-specific implementations of
@@ -33,6 +37,9 @@ void __iomem *cm_base;
 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
 void __iomem *cm2_base;
+#define CM_NO_CLOCKS            0x1
+#define CM_SINGLE_INSTANCE      0x2
 /**
 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
 * @cm: CM base virtual address
@@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
        return 0;
 }
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+        defined(CONFIG_SOC_DRA7XX)
+static struct omap_prcm_init_data cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap4_cm_init,
+};
+static struct omap_prcm_init_data cm2_data __initdata = {
+        .index = TI_CLKM_CM2,
+        .init = omap4_cm_init,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+static struct omap_prcm_init_data omap2_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap2xxx_cm_init,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap3xxx_cm_init,
+        .flags = CM_SINGLE_INSTANCE,
+        /*
+         * IVA2 offset is a negative value, must offset the cm_base address
+         * by this to get it to positive side on the iomap
+         */
+        .offset = -OMAP3430_IVA2_MOD,
+};
+#endif
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
+static struct omap_prcm_init_data am3_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = am33xx_cm_init,
+};
+#endif
+#ifdef CONFIG_SOC_AM43XX
+static struct omap_prcm_init_data am4_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = omap4_cm_init,
+};
+#endif
+static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-cm1", .data = &cm_data },
+        { .compatible = "ti,omap4-cm2", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,omap5-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,dra7-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
+#endif
+        { }
+};
+/**
+ * omap2_cm_base_init - initialize iomappings for the CM drivers
+ *
+ * Detects and initializes the iomappings for the CM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_cm_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
+        void __iomem *mem;
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
+                mem = of_iomap(np, 0);
+                if (!mem)
+                        return -ENOMEM;
+                if (data->index == TI_CLKM_CM)
+                        cm_base = mem + data->offset;
+                if (data->index == TI_CLKM_CM2)
+                        cm2_base = mem + data->offset;
+                data->mem = mem;
+                data->np = np;
+                if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
+                                   (cm_base && cm2_base)))
+                        data->init(data);
+        }
+        return 0;
+}
+/**
+ * omap_cm_init - low level init for the CM drivers
+ *
+ * Initializes the low level clock infrastructure for CM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_cm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = match->data;
+                if (data->flags & CM_NO_CLOCKS)
+                        continue;
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff66aff..2c0e07ed6b99 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 * Populates the base addresses of the _cm_bases
 * array used for read/write of cm module registers.
 */
-void omap_cm_base_init(void)
+static void omap_cm_base_init(void)
 {
        _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
        _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
        .module_disable         = &omap4_cminst_module_disable,
 };
-int __init omap4_cm_init(void)
+int __init omap4_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap_cm_base_init();
        return cm_register(&omap4xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 484cdadfb187..eae6a0e87c90 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -30,5 +30,4 @@ int __weak omap_secure_ram_reserve_memblock(void)
 void __init omap_reserve(void)
 {
        omap_secure_ram_reserve_memblock();
-        omap_barrier_reserve_memblock();
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 46e24581d624..cf3cf22ecd42 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -200,9 +200,6 @@ void __init omap4_map_io(void);
 void __init omap5_map_io(void);
 void __init ti81xx_map_io(void);
-/* omap_barriers_init() is OMAP4 only */
-void omap_barriers_init(void);
 /**
 * omap_test_timeout - busy-loop, testing a condition
 * @cond: condition to test until it evaluates to true
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4ab29c..af95a624fe71 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 #include "soc.h"
 #include "iomap.h"
@@ -25,13 +28,15 @@
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
+#include "clock.h"
 /* Used by omap3_ctrl_save_padconf() */
 #define START_PADCONF_SAVE              0x2
 #define PADCONF_SAVE_DONE               0x1
 static void __iomem *omap2_ctrl_base;
-static void __iomem *omap4_ctrl_pad_base;
+static s16 omap2_ctrl_offset;
+static struct regmap *omap2_ctrl_syscon;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -133,66 +138,79 @@ struct omap3_control_regs {
 static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
-#define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
+void __init omap2_set_globals_control(void __iomem *ctrl)
-#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
-void __init omap2_set_globals_control(void __iomem *ctrl,
-                                      void __iomem *ctrl_pad)
 {
        omap2_ctrl_base = ctrl;
-        omap4_ctrl_pad_base = ctrl_pad;
-}
-void __iomem *omap_ctrl_base_get(void)
-{
-        return omap2_ctrl_base;
 }
 u8 omap_ctrl_readb(u16 offset)
 {
-        return readb_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u8 byte_offset = offset & 0x3;
+        val = omap_ctrl_readl(offset);
+        return (val >> (byte_offset * 8)) & 0xff;
 }
 u16 omap_ctrl_readw(u16 offset)
 {
-        return readw_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u16 byte_offset = offset & 0x2;
+        val = omap_ctrl_readl(offset);
+        return (val >> (byte_offset * 8)) & 0xffff;
 }
 u32 omap_ctrl_readl(u16 offset)
 {
-        return readl_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                val = readl_relaxed(omap2_ctrl_base + offset);
+        else
+                regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                            &val);
+        return val;
 }
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
+        u32 tmp;
+        u8 byte_offset = offset & 0x3;
+        tmp = omap_ctrl_readl(offset);
+        tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
+        tmp |= val << (byte_offset * 8);
+        omap_ctrl_writel(tmp, offset);
 }
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
+        u32 tmp;
-}
+        u8 byte_offset = offset & 0x2;
-void omap_ctrl_writel(u32 val, u16 offset)
+        tmp = omap_ctrl_readl(offset);
-{
-        writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
-}
-/*
+        tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
- * On OMAP4 control pad are not addressable from control
+        tmp |= val << (byte_offset * 8);
- * core base. So the common omap_ctrl_read/write APIs breaks
- * Hence export separate APIs to manage the omap4 pad control
- * registers. This APIs will work only for OMAP4
- */
-u32 omap4_ctrl_pad_readl(u16 offset)
+        omap_ctrl_writel(tmp, offset);
-{
-        return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 }
-void omap4_ctrl_pad_writel(u32 val, u16 offset)
+void omap_ctrl_writel(u32 val, u16 offset)
 {
-        writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                writel_relaxed(val, omap2_ctrl_base + offset);
+        else
+                regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                             val);
 }
 #ifdef CONFIG_ARCH_OMAP3
@@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
        omap3_ctrl_setup_d2d_padconf();
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+struct control_init_data {
+        int index;
+        s16 offset;
+};
+static struct control_init_data ctrl_data = {
+        .index = TI_CLKM_CTRL,
+};
+static const struct control_init_data omap2_ctrl_data = {
+        .index = TI_CLKM_CTRL,
+        .offset = -OMAP2_CONTROL_GENERAL,
+};
+static const struct of_device_id omap_scrm_dt_match_table[] = {
+        { .compatible = "ti,am3-scm", .data = &ctrl_data },
+        { .compatible = "ti,am4-scm", .data = &ctrl_data },
+        { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
+        { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
+        { }
+};
+/**
+ * omap2_control_base_init - initialize iomappings for the control driver
+ *
+ * Detects and initializes the iomappings for the control driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_control_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct control_init_data *data;
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = (struct control_init_data *)match->data;
+                omap2_ctrl_base = of_iomap(np, 0);
+                if (!omap2_ctrl_base)
+                        return -ENOMEM;
+                omap2_ctrl_offset = data->offset;
+        }
+        return 0;
+}
+/**
+ * omap_control_init - low level init for the control driver
+ *
+ * Initializes the low level clock infrastructure for control driver.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_control_init(void)
+{
+        struct device_node *np, *scm_conf;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        struct regmap *syscon;
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = match->data;
+                /*
+                 * Check if we have scm_conf node, if yes, use this to
+                 * access clock registers.
+                 */
+                scm_conf = of_get_child_by_name(np, "scm_conf");
+                if (scm_conf) {
+                        syscon = syscon_node_to_regmap(scm_conf);
+                        if (IS_ERR(syscon))
+                                return PTR_ERR(syscon);
+                        omap2_ctrl_syscon = syscon;
+                        if (of_get_child_by_name(scm_conf, "clocks")) {
+                                ret = omap2_clk_provider_init(scm_conf,
+                                                              data->index,
+                                                              syscon, NULL);
+                                if (ret)
+                                        return ret;
+                        }
+                        iounmap(omap2_ctrl_base);
+                        omap2_ctrl_base = NULL;
+                } else {
+                        /* No scm_conf found, direct access */
+                        ret = omap2_clk_provider_init(np, data->index, NULL,
+                                                      omap2_ctrl_base);
+                        if (ret)
+                                return ret;
+                }
+        }
+        return 0;
+}
+/**
+ * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
+ *
+ * Legacy iomap init for clock provider. Needed only by legacy boot mode,
+ * where the base addresses are not parsed from DT, but still required
+ * by the clock driver to be setup properly.
+ */
+void __init omap3_control_legacy_iomap_init(void)
+{
+        omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8a487181210..80d2b7d8e36e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,15 +440,12 @@
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_ARCH_OMAP2PLUS
-extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
-extern u32 omap4_ctrl_pad_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
 extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
@@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 void omap3_ctrl_init(void);
-extern void omap2_set_globals_control(void __iomem *ctrl,
+int omap2_control_base_init(void);
-                                      void __iomem *ctrl_pad);
+int omap_control_init(void);
+void omap2_set_globals_control(void __iomem *ctrl);
+void __init omap3_control_legacy_iomap_init(void);
 #else
-#define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
 #define omap_ctrl_readl(x)              0
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..f492ae147c6a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 #include <video/omapdss.h>
 #include "omap_hwmod.h"
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
        { "dss_hdmi", "omapdss_hdmi", -1 },
 };
+#define OMAP4_DSIPHY_SYSCON_OFFSET              0x78
+static struct regmap *omap4_dsi_mux_syscon;
 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
        u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
                return -ENODEV;
        }
-        reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
        reg &= ~enable_mask;
        reg &= ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
        reg |= (lanes << enable_shift) & enable_mask;
        reg |= (lanes << pipd_shift) & pipd_mask;
-        omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
        return 0;
 }
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
                return r;
        }
+        /* add DSI info for omap4 */
+        node = of_find_node_by_name(NULL, "omap4_padconf_global");
+        if (node)
+                omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d5951b17b736..72918c4973ea 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -96,14 +96,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
        gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
        gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
-        if (gpmc_t) {
-                err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
-                if (err < 0) {
-                        pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
-                        return err;
-                }
-        }
        memset(&s, 0, sizeof(struct gpmc_settings));
        if (gpmc_nand_data->of_node)
                gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
@@ -111,6 +103,16 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                gpmc_set_legacy(gpmc_nand_data, &s);
        s.device_nand = true;
+        if (gpmc_t) {
+                err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s);
+                if (err < 0) {
+                        pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n",
+                               err);
+                        return err;
+                }
+        }
        err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
        if (err < 0)
                goto out_free_cs;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 53d197e0c1f3..f899e77ff5e6 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -293,7 +293,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
        if (ret < 0)
                return ret;
-        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
        if (ret < 0)
                return ret;
@@ -331,7 +331,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
        if (ret < 0)
                return ret;
-        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
        if (ret < 0)
                return ret;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 25f1beea453e..e3f713ffb06b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
 int omap_type(void)
 {
-        u32 val = 0;
+        static u32 val = OMAP2_DEVICETYPE_MASK;
+        if (val < OMAP2_DEVICETYPE_MASK)
+                return val;
        if (cpu_is_omap24xx()) {
                val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c4871c55bd8b..820dde8b5b04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -306,7 +306,6 @@ void __init am33xx_map_io(void)
 void __init omap4_map_io(void)
 {
        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
-        omap_barriers_init();
 }
 #endif
@@ -314,7 +313,6 @@ void __init omap4_map_io(void)
 void __init omap5_map_io(void)
 {
        iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
-        omap_barriers_init();
 }
 #endif
 /*
@@ -384,13 +382,9 @@ void __init omap2420_init_early(void)
        omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap2xxx_prm_init();
+        omap2_prcm_base_init();
-        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap242x_powerdomains_init();
        omap242x_clockdomains_init();
@@ -414,13 +408,9 @@ void __init omap2430_init_early(void)
        omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap2xxx_prm_init();
+        omap2_prcm_base_init();
-        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap243x_powerdomains_init();
        omap243x_clockdomains_init();
@@ -448,21 +438,30 @@ void __init omap3_init_early(void)
        omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
+        /* XXX: remove these once OMAP3 is DT only */
-                                  NULL);
+        if (!of_have_populated_dt()) {
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+                omap2_set_globals_control(
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
+                        OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
+                omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+                omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
+                                     NULL);
+        }
+        omap2_control_base_init();
        omap3xxx_check_revision();
        omap3xxx_check_features();
-        omap3xxx_prm_init();
+        omap2_prcm_base_init();
-        omap3xxx_cm_init();
+        /* XXX: remove these once OMAP3 is DT only */
+        if (!of_have_populated_dt()) {
+                omap3xxx_prm_init(NULL);
+                omap3xxx_cm_init(NULL);
+        }
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        omap3xxx_clockdomains_init();
        omap3xxx_hwmod_init();
        omap_hwmod_init_postsetup();
        if (!of_have_populated_dt()) {
-                omap3_prcm_legacy_iomaps_init();
+                omap3_control_legacy_iomap_init();
                if (soc_is_am35xx())
                        omap_clk_soc_init = am35xx_clk_legacy_init;
                else if (cpu_is_omap3630())
@@ -549,14 +548,10 @@ void __init ti814x_init_early(void)
 {
        omap2_set_globals_tap(TI814X_CLASS,
                              OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        ti81xx_clockdomains_init();
@@ -570,14 +565,10 @@ void __init ti816x_init_early(void)
 {
        omap2_set_globals_tap(TI816X_CLASS,
                              OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        ti81xx_clockdomains_init();
@@ -593,14 +584,10 @@ void __init am33xx_init_early(void)
 {
        omap2_set_globals_tap(AM335X_CLASS,
                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        am33xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
@@ -619,16 +606,10 @@ void __init am43xx_init_early(void)
 {
        omap2_set_globals_tap(AM335X_CLASS,
                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
-        omap_prm_base_init();
-        omap_cm_base_init();
        omap3xxx_check_revision();
        am33xx_check_features();
-        omap44xx_prm_init();
+        omap2_prcm_base_init();
-        omap4_cm_init();
        am43xx_powerdomains_init();
        am43xx_clockdomains_init();
        am43xx_hwmod_init();
@@ -648,19 +629,12 @@ void __init omap4430_init_early(void)
 {
        omap2_set_globals_tap(OMAP443X_CLASS,
                              OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
-        omap_prm_base_init();
+        omap2_control_base_init();
-        omap_cm_base_init();
        omap4xxx_check_revision();
        omap4xxx_check_features();
-        omap4_cm_init();
+        omap2_prcm_base_init();
        omap4_pm_init_early();
-        omap44xx_prm_init();
        omap44xx_voltagedomains_init();
        omap44xx_powerdomains_init();
        omap44xx_clockdomains_init();
@@ -683,18 +657,11 @@ void __init omap5_init_early(void)
 {
        omap2_set_globals_tap(OMAP54XX_CLASS,
                              OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
        omap4_pm_init_early();
-        omap_prm_base_init();
+        omap2_prcm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
        omap5xxx_check_revision();
-        omap4_cm_init();
        omap54xx_voltagedomains_init();
        omap54xx_powerdomains_init();
        omap54xx_clockdomains_init();
@@ -715,18 +682,11 @@ void __init omap5_init_late(void)
 void __init dra7xx_init_early(void)
 {
        omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
        omap4_pm_init_early();
-        omap_prm_base_init();
+        omap2_prcm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
        dra7xxx_check_revision();
-        omap4_cm_init();
        dra7xx_powerdomains_init();
        dra7xx_clockdomains_init();
        dra7xx_hwmod_init();
@@ -764,7 +724,11 @@ int __init omap_clk_init(void)
        ti_clk_init_features();
        if (of_have_populated_dt()) {
-                ret = of_prcm_init();
+                ret = omap_control_init();
+                if (ret)
+                        return ret;
+                ret = omap_prcm_init();
                if (ret)
                        return ret;
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 78064b0d4db5..176eef6ef338 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1053,7 +1053,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition,
                struct omap_mux *entry;
 #ifdef CONFIG_OMAP_MUX
-                if (!superset->muxnames || !superset->muxnames[0]) {
+                if (!superset->muxnames[0]) {
                        superset++;
                        continue;
                }
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index dec2b05d184b..af2851fbcdf0 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -70,13 +70,6 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
 extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
-#ifdef CONFIG_OMAP4_ERRATA_I688
-extern int omap_barrier_reserve_memblock(void);
-#else
-static inline void omap_barrier_reserve_memblock(void)
-{ }
-#endif
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 void set_cntfreq(void);
 #else
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 7bb116a6f86f..16350eefa66c 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -51,75 +51,6 @@ static void __iomem *twd_base;
 #define IRQ_LOCALTIMER          29
-#ifdef CONFIG_OMAP4_ERRATA_I688
-/* Used to implement memory barrier on DRAM path */
-#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
-void __iomem *dram_sync, *sram_sync;
-static phys_addr_t paddr;
-static u32 size;
-void omap_bus_sync(void)
-{
-        if (dram_sync && sram_sync) {
-                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
-                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
-                isb();
-        }
-}
-EXPORT_SYMBOL(omap_bus_sync);
-static int __init omap4_sram_init(void)
-{
-        struct device_node *np;
-        struct gen_pool *sram_pool;
-        np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
-        if (!np)
-                pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
-                        __func__);
-        sram_pool = of_get_named_gen_pool(np, "sram", 0);
-        if (!sram_pool)
-                pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
-                        __func__);
-        else
-                sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
-        return 0;
-}
-omap_arch_initcall(omap4_sram_init);
-/* Steal one page physical memory for barrier implementation */
-int __init omap_barrier_reserve_memblock(void)
-{
-        size = ALIGN(PAGE_SIZE, SZ_1M);
-        paddr = arm_memblock_steal(size, SZ_1M);
-        return 0;
-}
-void __init omap_barriers_init(void)
-{
-        struct map_desc dram_io_desc[1];
-        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
-        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
-        dram_io_desc[0].length = size;
-        dram_io_desc[0].type = MT_MEMORY_RW_SO;
-        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
-        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
-        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
-                (long long) paddr, dram_io_desc[0].virtual);
-}
-#else
-void __init omap_barriers_init(void)
-{}
-#endif
 void gic_dist_disable(void)
 {
        if (gic_dist_base_addr)
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index be9541e18650..166b18f515a2 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -690,6 +690,9 @@ struct dev_pm_domain omap_device_pm_domain = {
                USE_PLATFORM_PM_SLEEP_OPS
                .suspend_noirq = _od_suspend_noirq,
                .resume_noirq = _od_resume_noirq,
+                .freeze_noirq = _od_suspend_noirq,
+                .thaw_noirq = _od_resume_noirq,
+                .restore_noirq = _od_resume_noirq,
        }
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 8eb85925e444..e2223148ba4d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -20,6 +20,7 @@
 #include "omap_hwmod_33xx_43xx_common_data.h"
 #include "prcm43xx.h"
 #include "omap_hwmod_common_data.h"
+#include "hdq1w.h"
 /* IP blocks */
@@ -516,6 +517,33 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
        .parent_hwmod   = &am43xx_dss_core_hwmod,
 };
+/* HDQ1W */
+static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0014,
+        .syss_offs      = 0x0018,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
+        .name   = "hdq1w",
+        .sysc   = &am43xx_hdq1w_sysc,
+        .reset  = &omap_hdq1w_reset,
+};
+static struct omap_hwmod am43xx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .class          = &am43xx_hdq1w_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
 /* Interfaces */
 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
        .master         = &am33xx_l3_main_hwmod,
@@ -790,6 +818,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_hdq1w_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_wkup__synctimer,
        &am43xx_l4_ls__timer8,
@@ -889,6 +924,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
        &am43xx_l4_ls__dss,
        &am43xx_l4_ls__dss_dispc,
        &am43xx_l4_ls__dss_rfbi,
+        &am43xx_l4_ls__hdq1w,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 16fe7a1b7a35..0e64c2fac0b5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1726,21 +1726,6 @@ static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
        .sysc   = &dra7xx_timer_1ms_sysc,
 };
-static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
-        .name   = "timer",
-        .sysc   = &dra7xx_timer_secure_sysc,
-};
 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
        .rev_offs       = 0x0000,
        .sysc_offs      = 0x0010,
@@ -1804,7 +1789,7 @@ static struct omap_hwmod dra7xx_timer3_hwmod = {
 /* timer4 */
 static struct omap_hwmod dra7xx_timer4_hwmod = {
        .name           = "timer4",
-        .class          = &dra7xx_timer_secure_hwmod_class,
+        .class          = &dra7xx_timer_hwmod_class,
        .clkdm_name     = "l4per_clkdm",
        .main_clk       = "timer4_gfclk_mux",
        .prcm = {
@@ -1921,6 +1906,66 @@ static struct omap_hwmod dra7xx_timer11_hwmod = {
        },
 };
+/* timer13 */
+static struct omap_hwmod dra7xx_timer13_hwmod = {
+        .name           = "timer13",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per3_clkdm",
+        .main_clk       = "timer13_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer14 */
+static struct omap_hwmod dra7xx_timer14_hwmod = {
+        .name           = "timer14",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per3_clkdm",
+        .main_clk       = "timer14_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer15 */
+static struct omap_hwmod dra7xx_timer15_hwmod = {
+        .name           = "timer15",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per3_clkdm",
+        .main_clk       = "timer15_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer16 */
+static struct omap_hwmod dra7xx_timer16_hwmod = {
+        .name           = "timer16",
+        .class          = &dra7xx_timer_hwmod_class,
+        .clkdm_name     = "l4per3_clkdm",
+        .main_clk       = "timer16_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
 /*
 * 'uart' class
 *
@@ -3059,6 +3104,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* l4_per3 -> timer13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer13_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per3 -> timer14 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer14_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per3 -> timer15 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer15_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per3 -> timer16 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_timer16_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* l4_per1 -> uart1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
        .master         = &dra7xx_l4_per1_hwmod,
@@ -3295,6 +3372,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_per1__timer9,
        &dra7xx_l4_per1__timer10,
        &dra7xx_l4_per1__timer11,
+        &dra7xx_l4_per3__timer13,
+        &dra7xx_l4_per3__timer14,
+        &dra7xx_l4_per3__timer15,
+        &dra7xx_l4_per3__timer16,
        &dra7xx_l4_per1__uart1,
        &dra7xx_l4_per1__uart2,
        &dra7xx_l4_per1__uart3,
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index e642b079e9f3..af11511dda50 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/ti_wilink_st.h>
-#include <linux/wl12xx.h>
 #include <linux/platform_data/pinctrl-single.h>
 #include <linux/platform_data/iommu-omap.h>
@@ -35,34 +34,6 @@ struct pdata_init {
 struct of_dev_auxdata omap_auxdata_lookup[];
 static struct twl4030_gpio_platform_data twl_gpio_auxdata;
-#if IS_ENABLED(CONFIG_WL12XX)
-static struct wl12xx_platform_data wl12xx __initdata;
-static void __init __used legacy_init_wl12xx(unsigned ref_clock,
-                                             unsigned tcxo_clock,
-                                             int gpio)
-{
-        int res;
-        wl12xx.board_ref_clock = ref_clock;
-        wl12xx.board_tcxo_clock = tcxo_clock;
-        wl12xx.irq = gpio_to_irq(gpio);
-        res = wl12xx_set_platform_data(&wl12xx);
-        if (res) {
-                pr_err("error setting wl12xx data: %d\n", res);
-                return;
-        }
-}
-#else
-static inline void legacy_init_wl12xx(unsigned ref_clock,
-                                      unsigned tcxo_clock,
-                                      int gpio)
-{
-}
-#endif
 #ifdef CONFIG_MACH_NOKIA_N8X0
 static void __init omap2420_n8x0_legacy_init(void)
 {
@@ -129,7 +100,6 @@ static void __init omap3_sbc_t3730_twl_init(void)
 static void __init omap3_sbc_t3730_legacy_init(void)
 {
        omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
 }
 static void __init omap3_sbc_t3530_legacy_init(void)
@@ -159,14 +129,12 @@ static struct platform_device btwilink_device = {
 static void __init omap3_igep0020_rev_f_legacy_init(void)
 {
-        legacy_init_wl12xx(0, 0, 177);
        platform_device_register(&wl18xx_device);
        platform_device_register(&btwilink_device);
 }
 static void __init omap3_igep0030_rev_g_legacy_init(void)
 {
-        legacy_init_wl12xx(0, 0, 136);
        platform_device_register(&wl18xx_device);
        platform_device_register(&btwilink_device);
 }
@@ -174,12 +142,6 @@ static void __init omap3_igep0030_rev_g_legacy_init(void)
 static void __init omap3_evm_legacy_init(void)
 {
        hsmmc2_internal_input_clk();
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
-}
-static void __init omap3_zoom_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
 }
 static void am35xx_enable_emac_int(void)
@@ -246,7 +208,6 @@ static void __init omap3_sbc_t3517_legacy_init(void)
        am35xx_emac_reset();
        hsmmc2_internal_input_clk();
        omap3_sbc_t3517_wifi_init();
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
 }
 static void __init am3517_evm_legacy_init(void)
@@ -288,24 +249,6 @@ static void __init omap3_tao3530_legacy_init(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 */
-#ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_sdp_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_26,
-                           WL12XX_TCXOCLOCK_26, 53);
-}
-static void __init omap4_panda_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
-}
-static void __init var_som_om44_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41);
-}
-#endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
 static struct iommu_platform_data omap4_iommu_pdata = {
        .reset_name = "mmu_cache",
@@ -314,13 +257,6 @@ static struct iommu_platform_data omap4_iommu_pdata = {
 };
 #endif
-#ifdef CONFIG_SOC_AM33XX
-static void __init am335x_evmsk_legacy_init(void)
-{
-        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31);
-}
-#endif
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_uevm_legacy_init(void)
 {
@@ -421,19 +357,9 @@ static struct pdata_init pdata_quirks[] __initdata = {
        { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
        { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
        { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
-        { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
        { "ti,am3517-evm", am3517_evm_legacy_init, },
        { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
 #endif
-#ifdef CONFIG_ARCH_OMAP4
-        { "ti,omap4-sdp", omap4_sdp_legacy_init, },
-        { "ti,omap4-panda", omap4_panda_legacy_init, },
-        { "variscite,var-dvk-om44", var_som_om44_legacy_init, },
-        { "variscite,var-stk-om44", var_som_om44_legacy_init, },
-#endif
-#ifdef CONFIG_SOC_AM33XX
-        { "ti,am335x-evmsk", am335x_evmsk_legacy_init, },
-#endif
 #ifdef CONFIG_SOC_OMAP5
        { "ti,omap5-uevm", omap5_uevm_legacy_init, },
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a03aa2..b1aad7e1426c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
        /* Clear old wake-up events */
        /* REVISIT: These write to reserved bits? */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
        clk_enable(osc_ck);
        /* clear CORE wake-up events */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
        /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
        /* MPU domain wake events */
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
-                                    0x1);
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
-                                    0x20);
        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
         * it is in retention mode. */
        if (omap2_allow_mpu_retention()) {
                /* REVISIT: These write to reserved bits? */
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-                omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+                omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
                /* Try to enter MPU retention */
                pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df6001d..87b98bf92366 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
        int c;
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
-                                        ~(OMAP3430_ST_IO_MASK |
+                                    OMAP3430_ST_IO_CHAIN_MASK);
-                                          OMAP3430_ST_IO_CHAIN_MASK));
        return c ? IRQ_HANDLED : IRQ_NONE;
 }
@@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
         * these are handled in a separate handler to avoid acking
         * IO events before parsing in mux code
         */
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
-                                        OMAP3430_ST_IO_MASK |
+                                                   OMAP3430_ST_IO_CHAIN_MASK));
-                                        OMAP3430_ST_IO_CHAIN_MASK);
+        c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
-        c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
-        c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
-                c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+                c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
        }
        return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6163d66102a3..6ae0b3a1781e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
        .priority = _priority                           \
        }
+/**
+ * struct omap_prcm_init_data - PRCM driver init data
+ * @index: clock memory mapping index to be used
+ * @mem: IO mem pointer for this module
+ * @offset: module base address offset from the IO base
+ * @flags: PRCM module init flags
+ * @device_inst_offset: device instance offset within the module address space
+ * @init: low level PRCM init function for this module
+ * @np: device node for this PRCM module
+ */
+struct omap_prcm_init_data {
+        int index;
+        void __iomem *mem;
+        s16 offset;
+        u16 flags;
+        s32 device_inst_offset;
+        int (*init)(const struct omap_prcm_init_data *data);
+        struct device_node *np;
+};
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
        struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index ad7b3e9977f8..48df3b55057e 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -143,5 +143,6 @@
 #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET        0x0268
 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET     0x05C0
 #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET                0x0a20
+#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET              0x04a0
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6a2db8..233bc84fbc0e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,8 +19,9 @@
 extern void __iomem *prm_base;
 extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
-int of_prcm_init(void);
+int omap_prcm_init(void);
-void omap3_prcm_legacy_iomaps_init(void);
+int omap2_prm_base_init(void);
+int omap2_prcm_base_init(void);
 # endif
 /*
@@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
 *
 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
 * PRM_HAS_VOLTAGE: has voltage domains
+ * PRM_IRQ_DEFAULT: use default irq number for PRM irq
 */
-#define PRM_HAS_IO_WAKEUP       (1 << 0)
+#define PRM_HAS_IO_WAKEUP       BIT(0)
-#define PRM_HAS_VOLTAGE         (1 << 1)
+#define PRM_HAS_VOLTAGE         BIT(1)
+#define PRM_IRQ_DEFAULT         BIT(2)
 /*
 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -146,6 +149,9 @@ struct prm_ll_data {
        int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
                                     u16 offset);
        void (*reset_system)(void);
+        int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
+        u32 (*vp_check_txdone)(u8 vp_id);
+        void (*vp_clear_txdone)(u8 vp_id);
 };
 extern int prm_register(struct prm_ll_data *pld);
@@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
 void omap_prm_reset_system(void);
 void omap_prm_reconfigure_io_chain(void);
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+/*
+ * Voltage Processor (VP) identifiers
+ */
+#define OMAP3_VP_VDD_MPU_ID     0
+#define OMAP3_VP_VDD_CORE_ID    1
+#define OMAP4_VP_VDD_CORE_ID    0
+#define OMAP4_VP_VDD_IVA_ID     1
+#define OMAP4_VP_VDD_MPU_ID     2
+u32 omap_prm_vp_check_txdone(u8 vp_id);
+void omap_prm_vp_clear_txdone(u8 vp_id);
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index af0f15278fc2..752018ce129c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
 * Clears wakeup status bits for a given module, so that the device can
 * re-enter idle.
 */
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
        u32 wkst;
        wkst = omap2_prm_read_mod_reg(module, regs);
        wkst &= wkst_mask;
        omap2_prm_write_mod_reg(wkst, module, regs);
+        return 0;
 }
 int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
        .deassert_hardreset = &omap2_prm_deassert_hardreset,
        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
        .reset_system = &omap2xxx_prm_dpll_reset,
+        .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
 };
-int __init omap2xxx_prm_init(void)
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
 {
        return prm_register(&omap2xxx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 1d51643062f7..9008a9e55a1a 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,9 +124,7 @@
 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
-extern int __init omap2xxx_prm_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 02f628601b09..dcb5001d77da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
        .reset_system                   = am33xx_prm_global_warm_sw_reset,
 };
-int __init am33xx_prm_init(void)
+int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
 {
        return prm_register(&am33xx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 98ac41f271da..2bc4ec52ba78 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,7 +118,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 #ifndef __ASSEMBLER__
-int am33xx_prm_init(void);
+int am33xx_prm_init(const struct omap_prcm_init_data *data);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbdf83bc..62680aad2126 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -29,6 +29,7 @@
 #include "prm-regbits-34xx.h"
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "clock.h"
 static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 static void omap3xxx_prm_ocp_barrier(void);
@@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
+static u32 omap3_prm_vp_check_txdone(u8 vp_id)
 {
        struct omap3_vp *vp = &omap3_vp[vp_id];
        u32 irqstatus;
@@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
        return irqstatus & vp->tranxdone_status;
 }
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+static void omap3_prm_vp_clear_txdone(u8 vp_id)
 {
        struct omap3_vp *vp = &omap3_vp[vp_id];
@@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
 * @module: PRM module to clear wakeups from
 * @regs: register set to clear, 1 or 3
- * @ignore_bits: wakeup status bits to ignore
+ * @wkst_mask: wkst bits to clear
 *
 * The purpose of this function is to clear any wake-up events latched
 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 * that any peripheral wake-up events occurring while attempting to
 * clear the PM_WKST_x are detected and cleared.
 */
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
        u32 wkst, fclk, iclk, clken;
        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
        wkst = omap2_prm_read_mod_reg(module, wkst_off);
        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-        wkst &= ~ignore_bits;
+        wkst &= wkst_mask;
        if (wkst) {
                iclk = omap2_cm_read_mod_reg(module, iclk_off);
                fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
-                        wkst &= ~ignore_bits;
+                        wkst &= wkst_mask;
                        c++;
                }
                omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
        .deassert_hardreset = &omap2_prm_deassert_hardreset,
        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
        .reset_system = &omap3xxx_prm_dpll3_reset,
+        .clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
+        .vp_check_txdone = &omap3_prm_vp_check_txdone,
+        .vp_clear_txdone = &omap3_prm_vp_clear_txdone,
 };
-int __init omap3xxx_prm_init(void)
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_PRM,
+                                       prm_base + OMAP3430_IVA2_MOD);
        if (omap3_has_io_wakeup())
                prm_features |= PRM_HAS_IO_WAKEUP;
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8b739a..5f095eec339c 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
 #ifndef __ASSEMBLER__
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
 /*
 * OMAP3 access functions for voltage controller (VC) and
 * voltage proccessor (VP) in the PRM.
@@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap3xxx_prm_init(void);
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
 void omap3xxx_prm_iva_idle(void);
 void omap3_prm_reset_modem(void);
 int omap3xxx_prm_clear_global_cold_reset(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d6d6bc39e05c..4541700f743a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
        },
 };
-u32 omap4_prm_vp_check_txdone(u8 vp_id)
+static u32 omap4_prm_vp_check_txdone(u8 vp_id)
 {
        struct omap4_vp *vp = &omap4_vp[vp_id];
        u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
        return irqstatus & vp->tranxdone_status;
 }
-void omap4_prm_vp_clear_txdone(u8 vp_id)
+static void omap4_prm_vp_clear_txdone(u8 vp_id)
 {
        struct omap4_vp *vp = &omap4_vp[vp_id];
@@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .deassert_hardreset     = omap4_prminst_deassert_hardreset,
        .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
        .reset_system           = omap4_prminst_global_warm_sw_reset,
+        .vp_check_txdone        = omap4_prm_vp_check_txdone,
+        .vp_clear_txdone        = omap4_prm_vp_clear_txdone,
 };
-int __init omap44xx_prm_init(void)
+static const struct omap_prcm_init_data *prm_init_data;
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
 {
-        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
+        omap_prm_base_init();
+        prm_init_data = data;
+        if (data->flags & PRM_HAS_IO_WAKEUP)
                prm_features |= PRM_HAS_IO_WAKEUP;
-        if (!soc_is_dra7xx())
+        if (data->flags & PRM_HAS_VOLTAGE)
                prm_features |= PRM_HAS_VOLTAGE;
+        omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
        return prm_register(&omap44xx_prm_ll_data);
 }
-static const struct of_device_id omap_prm_dt_match_table[] = {
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,dra7-prm" },
-        { }
-};
 static int omap44xx_prm_late_init(void)
 {
-        struct device_node *np;
        int irq_num;
        if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
        if (!of_have_populated_dt())
                return 0;
-        np = of_find_matching_node(NULL, omap_prm_dt_match_table);
+        irq_num = of_irq_get(prm_init_data->np, 0);
+        /*
-        if (!np) {
+         * Already have OMAP4 IRQ num. For all other platforms, we need
-                /* Default loaded up with OMAP4 values */
+         * IRQ numbers from DT
-                if (!cpu_is_omap44xx())
+         */
-                        return 0;
+        if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
-        } else {
+                if (irq_num == -EPROBE_DEFER)
-                irq_num = of_irq_get(np, 0);
+                        return irq_num;
-                /*
-                 * Already have OMAP4 IRQ num. For all other platforms, we need
+                /* Have nothing to do */
-                 * IRQ numbers from DT
+                return 0;
-                 */
+        }
-                if (irq_num < 0 && !cpu_is_omap44xx()) {
-                        if (irq_num == -EPROBE_DEFER)
+        /* Once OMAP4 DT is filled as well */
-                                return irq_num;
+        if (irq_num >= 0) {
+                omap4_prcm_irq_setup.irq = irq_num;
-                        /* Have nothing to do */
+                omap4_prcm_irq_setup.xlate_irq = NULL;
-                        return 0;
-                }
-                /* Once OMAP4 DT is filled as well */
-                if (irq_num >= 0) {
-                        omap4_prcm_irq_setup.irq = irq_num;
-                        omap4_prcm_irq_setup.xlate_irq = NULL;
-                }
        }
        omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422faa16..efd6035d0871 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 #define OMAP4430_PRM_BASE               0x4a306000
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 714329565b90..3f139ebc8398 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -23,13 +23,11 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#include "prcm-common.h"
 /* Function prototypes */
 #ifndef __ASSEMBLER__
-/* OMAP4/OMAP5-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
 /*
 * OMAP4/OMAP5 access functions for voltage controller (VC) and
 * voltage proccessor (VP) in the PRM.
@@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap44xx_prm_init(void);
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e4411010309c..1eb22ff087dc 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 #define OMAP54XX_PRM_BASE               0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 4bb50fbf29be..cc1e6a2b97f6 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,8 +22,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
-#include "prm44xx_54xx.h"
 #include "prcm-common.h"
+#include "prm44xx_54xx.h"
 #include "prm.h"
 #define DRA7XX_PRM_BASE         0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba595cc..7add7994dbfc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,11 @@
 #include "prm2xxx_3xxx.h"
 #include "prm2xxx.h"
 #include "prm3xxx.h"
+#include "prm33xx.h"
 #include "prm44xx.h"
+#include "prm54xx.h"
+#include "prm7xx.h"
+#include "prcm43xx.h"
 #include "common.h"
 #include "clock.h"
 #include "cm.h"
@@ -534,6 +538,61 @@ void omap_prm_reset_system(void)
 }
 /**
+ * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
+ * @module: PRM module to clear wakeups from
+ * @regs: register to clear
+ * @wkst_mask: wkst bits to clear
+ *
+ * Clears any wakeup events for the module and register set defined.
+ * Uses SoC specific implementation to do the actual wakeup status
+ * clearing.
+ */
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+{
+        if (!prm_ll_data->clear_mod_irqs) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
+}
+/**
+ * omap_prm_vp_check_txdone - check voltage processor TX done status
+ *
+ * Checks if voltage processor transmission has been completed.
+ * Returns non-zero if a transmission has completed, 0 otherwise.
+ */
+u32 omap_prm_vp_check_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_check_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return 0;
+        }
+        return prm_ll_data->vp_check_txdone(vp_id);
+}
+/**
+ * omap_prm_vp_clear_txdone - clears voltage processor TX done status
+ *
+ * Clears the status bit for completed voltage processor transmission
+ * returned by prm_vp_check_txdone.
+ */
+void omap_prm_vp_clear_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_clear_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return;
+        }
+        prm_ll_data->vp_clear_txdone(vp_id);
+}
+/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
@@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
        return 0;
 }
-static const struct of_device_id omap_prcm_dt_match_table[] = {
+#ifdef CONFIG_ARCH_OMAP2
-        { .compatible = "ti,am3-prcm" },
+static struct omap_prcm_init_data omap2_prm_data __initdata = {
-        { .compatible = "ti,am3-scrm" },
+        .index = TI_CLKM_PRM,
-        { .compatible = "ti,am4-prcm" },
+        .init = omap2xxx_prm_init,
-        { .compatible = "ti,am4-scrm" },
-        { .compatible = "ti,dm814-prcm" },
-        { .compatible = "ti,dm814-scrm" },
-        { .compatible = "ti,dm816-prcm" },
-        { .compatible = "ti,dm816-scrm" },
-        { .compatible = "ti,omap2-prcm" },
-        { .compatible = "ti,omap2-scrm" },
-        { .compatible = "ti,omap3-prm" },
-        { .compatible = "ti,omap3-cm" },
-        { .compatible = "ti,omap3-scrm" },
-        { .compatible = "ti,omap4-cm1" },
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap4-cm2" },
-        { .compatible = "ti,omap4-scrm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,omap5-cm-core-aon" },
-        { .compatible = "ti,omap5-scrm" },
-        { .compatible = "ti,omap5-cm-core" },
-        { .compatible = "ti,dra7-prm" },
-        { .compatible = "ti,dra7-cm-core-aon" },
-        { .compatible = "ti,dra7-cm-core" },
-        { }
 };
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap3xxx_prm_init,
-static struct clk_hw_omap memmap_dummy_ck = {
+        /*
-        .flags = MEMMAP_ADDRESSING,
+         * IVA2 offset is a negative value, must offset the prm_base
+         * address by this to get it to positive
+         */
+        .offset = -OMAP3430_IVA2_MOD,
 };
+#endif
-static u32 prm_clk_readl(void __iomem *reg)
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
-{
+static struct omap_prcm_init_data am3_prm_data __initdata = {
-        return omap2_clk_readl(&memmap_dummy_ck, reg);
+        .index = TI_CLKM_PRM,
-}
+        .init = am33xx_prm_init,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+static struct omap_prcm_init_data omap4_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
+};
+#endif
+#ifdef CONFIG_SOC_OMAP5
+static struct omap_prcm_init_data omap5_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
+};
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+static struct omap_prcm_init_data dra7_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP,
+};
+#endif
-static void prm_clk_writel(u32 val, void __iomem *reg)
+#ifdef CONFIG_SOC_AM43XX
-{
+static struct omap_prcm_init_data am4_prm_data __initdata = {
-        omap2_clk_writel(val, &memmap_dummy_ck, reg);
+        .index = TI_CLKM_PRM,
-}
+        .init = omap44xx_prm_init,
+        .device_inst_offset = AM43XX_PRM_DEVICE_INST,
+};
+#endif
-static struct ti_clk_ll_ops omap_clk_ll_ops = {
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-        .clk_readl = prm_clk_readl,
+static struct omap_prcm_init_data scrm_data __initdata = {
-        .clk_writel = prm_clk_writel,
+        .index = TI_CLKM_SCRM,
+};
+#endif
+static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
+        { .compatible = "ti,omap4-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
+        { .compatible = "ti,omap5-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
+#endif
+        { }
 };
-int __init of_prcm_init(void)
+/**
+ * omap2_prm_base_init - initialize iomappings for the PRM driver
+ *
+ * Detects and initializes the iomappings for the PRM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_prm_base_init(void)
 {
        struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
        void __iomem *mem;
-        int memmap_index = 0;
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
-        for_each_matching_node(np, omap_prcm_dt_match_table) {
                mem = of_iomap(np, 0);
-                clk_memmaps[memmap_index] = mem;
+                if (!mem)
-                ti_dt_clk_init_provider(np, memmap_index);
+                        return -ENOMEM;
-                memmap_index++;
+                if (data->index == TI_CLKM_PRM)
+                        prm_base = mem + data->offset;
+                data->mem = mem;
+                data->np = np;
+                if (data->init)
+                        data->init(data);
        }
        return 0;
 }
-void __init omap3_prcm_legacy_iomaps_init(void)
+int __init omap2_prcm_base_init(void)
 {
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        int ret;
-        clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
+        ret = omap2_prm_base_init();
-        clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
+        if (ret)
-        clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
+                return ret;
+        return omap2_cm_base_init();
+}
+/**
+ * omap_prcm_init - low level init for the PRCM drivers
+ *
+ * Initializes the low level clock infrastructure for PRCM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_prcm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = match->data;
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+        omap_cm_init();
+        return 0;
 }
 static int __init prm_late_init(void)
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1a1dce..c4859c4d3646 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
 s32 omap4_prmst_get_prm_dev_inst(void)
 {
-        if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
-                return prm_dev_inst;
-        /* This cannot be done way early at boot.. as things are not setup */
-        if (cpu_is_omap44xx())
-                prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
-        else if (soc_is_omap54xx())
-                prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
-        else if (soc_is_dra7xx())
-                prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
-        else if (soc_is_am43xx())
-                prm_dev_inst = AM43XX_PRM_DEVICE_INST;
        return prm_dev_inst;
 }
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
+{
+        prm_dev_inst = dev_inst;
+}
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 {
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index fb1c9d7a2f9d..0c03d0731d7f 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -14,6 +14,7 @@
 #define PRM_INSTANCE_UNKNOWN    -1
 extern s32 omap4_prmst_get_prm_dev_inst(void);
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
 /*
 * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index b84a0122d823..ad1bb9431e94 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -333,11 +333,9 @@ ENDPROC(omap4_cpu_resume)
 #endif  /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
-#ifndef CONFIG_OMAP4_ERRATA_I688
 ENTRY(omap_bus_sync)
        ret     lr
 ENDPROC(omap_bus_sync)
-#endif
 ENTRY(omap_do_wfi)
        stmfd   sp!, {lr}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 8333400898fb..e554d9e66a1c 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -71,7 +71,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
        gpmc_calc_timings(&t, &tusb_async, &dev_t);
-        return gpmc_cs_set_timings(async_cs, &t);
+        return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
 }
 static int tusb_set_sync_mode(unsigned sysclk_ps)
@@ -98,7 +98,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
-        return gpmc_cs_set_timings(sync_cs, &t);
+        return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
 }
 /* tusb driver calls this when it changes the chip's clocking */
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080e4a6..7e0829682bd0 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
 struct voltagedomain;
-/*
- * Voltage Processor (VP) identifiers
- */
-#define OMAP3_VP_VDD_MPU_ID 0
-#define OMAP3_VP_VDD_CORE_ID 1
-#define OMAP4_VP_VDD_CORE_ID 0
-#define OMAP4_VP_VDD_IVA_ID 1
-#define OMAP4_VP_VDD_MPU_ID 2
 /* XXX document */
 #define VP_IDLE_TIMEOUT         200
 #define VP_TRANXDONE_TIMEOUT    300
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e026245e..b0590fe6ab01 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -28,8 +28,8 @@
 #include "prm2xxx_3xxx.h"
 static const struct omap_vp_ops omap3_vp_ops = {
-        .check_txdone = omap3_prm_vp_check_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
-        .clear_txdone = omap3_prm_vp_clear_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 /*
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index e62f6b018beb..2448bb9a8716 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -28,8 +28,8 @@
 #include "vp.h"
 static const struct omap_vp_ops omap4_vp_ops = {
-        .check_txdone = omap4_prm_vp_check_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
-        .clear_txdone = omap4_prm_vp_clear_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 /*
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index 48003ea652b9..2256cd1e25d1 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -22,7 +22,4 @@ config ARCH_MSM8974
        bool "Enable support for MSM8974"
        select HAVE_ARM_ARCH_TIMER
-config QCOM_SCM
-        bool
 endif
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
index 8f756ae1ae31..e324375fa919 100644
--- a/arch/arm/mach-qcom/Makefile
+++ b/arch/arm/mach-qcom/Makefile
@@ -1,5 +1,2 @@
 obj-y                   := board.o
 obj-$(CONFIG_SMP)       += platsmp.o
-obj-$(CONFIG_QCOM_SCM)  += scm.o scm-boot.o
-CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 09cffed4c0a4..5cde63a64b34 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -17,10 +17,10 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/qcom_scm.h>
 #include <asm/smp_plat.h>
-#include "scm-boot.h"
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL     0x35a0
 #define SCSS_CPU1CORE_RESET             0x2d80
@@ -319,25 +319,10 @@ static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu, map;
+        int cpu;
-        unsigned int flags = 0;
-        static const int cold_boot_flags[] = {
-                0,
-                SCM_FLAG_COLDBOOT_CPU1,
-                SCM_FLAG_COLDBOOT_CPU2,
-                SCM_FLAG_COLDBOOT_CPU3,
-        };
-        for_each_present_cpu(cpu) {
-                map = cpu_logical_map(cpu);
-                if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
-                        set_cpu_present(cpu, false);
-                        continue;
-                }
-                flags |= cold_boot_flags[map];
-        }
-        if (scm_set_boot_addr(virt_to_phys(secondary_startup_arm), flags)) {
+        if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
+                                        cpu_present_mask)) {
                for_each_present_cpu(cpu) {
                        if (cpu == smp_processor_id())
                                continue;
diff --git a/arch/arm/mach-qcom/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c
deleted file mode 100644
index e8ff7beb6218..000000000000
--- a/arch/arm/mach-qcom/scm-boot.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/module.h>
-#include <linux/slab.h>
-#include "scm.h"
-#include "scm-boot.h"
-/*
- * Set the cold/warm boot address for one of the CPU cores.
- */
-int scm_set_boot_addr(u32 addr, int flags)
-{
-        struct {
-                __le32 flags;
-                __le32 addr;
-        } cmd;
-        cmd.addr = cpu_to_le32(addr);
-        cmd.flags = cpu_to_le32(flags);
-        return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
-                        &cmd, sizeof(cmd), NULL, 0);
-}
-EXPORT_SYMBOL(scm_set_boot_addr);
diff --git a/arch/arm/mach-qcom/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h
deleted file mode 100644
index 3e210fb818bb..000000000000
--- a/arch/arm/mach-qcom/scm-boot.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_SCM_BOOT_H
-#define __MACH_SCM_BOOT_H
-#define SCM_BOOT_ADDR                   0x1
-#define SCM_FLAG_COLDBOOT_CPU1          0x01
-#define SCM_FLAG_COLDBOOT_CPU2          0x08
-#define SCM_FLAG_COLDBOOT_CPU3          0x20
-#define SCM_FLAG_WARMBOOT_CPU0          0x04
-#define SCM_FLAG_WARMBOOT_CPU1          0x02
-#define SCM_FLAG_WARMBOOT_CPU2          0x10
-#define SCM_FLAG_WARMBOOT_CPU3          0x40
-int scm_set_boot_addr(u32 addr, int flags);
-#endif
diff --git a/arch/arm/mach-qcom/scm.c b/arch/arm/mach-qcom/scm.c
deleted file mode 100644
index 1d9cf18c7091..000000000000
--- a/arch/arm/mach-qcom/scm.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <asm/outercache.h>
-#include <asm/cacheflush.h>
-#include "scm.h"
-#define SCM_ENOMEM              -5
-#define SCM_EOPNOTSUPP          -4
-#define SCM_EINVAL_ADDR         -3
-#define SCM_EINVAL_ARG          -2
-#define SCM_ERROR               -1
-#define SCM_INTERRUPTED         1
-static DEFINE_MUTEX(scm_lock);
-/**
- * struct scm_command - one SCM command buffer
- * @len: total available memory for command and response
- * @buf_offset: start of command buffer
- * @resp_hdr_offset: start of response buffer
- * @id: command to be executed
- * @buf: buffer returned from scm_get_command_buffer()
- *
- * An SCM command is laid out in memory as follows:
- *
- *      ------------------- <--- struct scm_command
- *      | command header  |
- *      ------------------- <--- scm_get_command_buffer()
- *      | command buffer  |
- *      ------------------- <--- struct scm_response and
- *      | response header |      scm_command_to_response()
- *      ------------------- <--- scm_get_response_buffer()
- *      | response buffer |
- *      -------------------
- *
- * There can be arbitrary padding between the headers and buffers so
- * you should always use the appropriate scm_get_*_buffer() routines
- * to access the buffers in a safe manner.
- */
-struct scm_command {
-        __le32 len;
-        __le32 buf_offset;
-        __le32 resp_hdr_offset;
-        __le32 id;
-        __le32 buf[0];
-};
-/**
- * struct scm_response - one SCM response buffer
- * @len: total available memory for response
- * @buf_offset: start of response data relative to start of scm_response
- * @is_complete: indicates if the command has finished processing
- */
-struct scm_response {
-        __le32 len;
-        __le32 buf_offset;
-        __le32 is_complete;
-};
-/**
- * alloc_scm_command() - Allocate an SCM command
- * @cmd_size: size of the command buffer
- * @resp_size: size of the response buffer
- *
- * Allocate an SCM command, including enough room for the command
- * and response headers as well as the command and response buffers.
- *
- * Returns a valid &scm_command on success or %NULL if the allocation fails.
- */
-static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size)
-{
-        struct scm_command *cmd;
-        size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
-                resp_size;
-        u32 offset;
-        cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
-        if (cmd) {
-                cmd->len = cpu_to_le32(len);
-                offset = offsetof(struct scm_command, buf);
-                cmd->buf_offset = cpu_to_le32(offset);
-                cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
-        }
-        return cmd;
-}
-/**
- * free_scm_command() - Free an SCM command
- * @cmd: command to free
- *
- * Free an SCM command.
- */
-static inline void free_scm_command(struct scm_command *cmd)
-{
-        kfree(cmd);
-}
-/**
- * scm_command_to_response() - Get a pointer to a scm_response
- * @cmd: command
- *
- * Returns a pointer to a response for a command.
- */
-static inline struct scm_response *scm_command_to_response(
-                const struct scm_command *cmd)
-{
-        return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
-}
-/**
- * scm_get_command_buffer() - Get a pointer to a command buffer
- * @cmd: command
- *
- * Returns a pointer to the command buffer of a command.
- */
-static inline void *scm_get_command_buffer(const struct scm_command *cmd)
-{
-        return (void *)cmd->buf;
-}
-/**
- * scm_get_response_buffer() - Get a pointer to a response buffer
- * @rsp: response
- *
- * Returns a pointer to a response buffer of a response.
- */
-static inline void *scm_get_response_buffer(const struct scm_response *rsp)
-{
-        return (void *)rsp + le32_to_cpu(rsp->buf_offset);
-}
-static int scm_remap_error(int err)
-{
-        pr_err("scm_call failed with error code %d\n", err);
-        switch (err) {
-        case SCM_ERROR:
-                return -EIO;
-        case SCM_EINVAL_ADDR:
-        case SCM_EINVAL_ARG:
-                return -EINVAL;
-        case SCM_EOPNOTSUPP:
-                return -EOPNOTSUPP;
-        case SCM_ENOMEM:
-                return -ENOMEM;
-        }
-        return -EINVAL;
-}
-static u32 smc(u32 cmd_addr)
-{
-        int context_id;
-        register u32 r0 asm("r0") = 1;
-        register u32 r1 asm("r1") = (u32)&context_id;
-        register u32 r2 asm("r2") = cmd_addr;
-        do {
-                asm volatile(
-                        __asmeq("%0", "r0")
-                        __asmeq("%1", "r0")
-                        __asmeq("%2", "r1")
-                        __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
-                        ".arch_extension sec\n"
-#endif
-                        "smc    #0      @ switch to secure world\n"
-                        : "=r" (r0)
-                        : "r" (r0), "r" (r1), "r" (r2)
-                        : "r3");
-        } while (r0 == SCM_INTERRUPTED);
-        return r0;
-}
-static int __scm_call(const struct scm_command *cmd)
-{
-        int ret;
-        u32 cmd_addr = virt_to_phys(cmd);
-        /*
-         * Flush the command buffer so that the secure world sees
-         * the correct data.
-         */
-        __cpuc_flush_dcache_area((void *)cmd, cmd->len);
-        outer_flush_range(cmd_addr, cmd_addr + cmd->len);
-        ret = smc(cmd_addr);
-        if (ret < 0)
-                ret = scm_remap_error(ret);
-        return ret;
-}
-static void scm_inv_range(unsigned long start, unsigned long end)
-{
-        u32 cacheline_size, ctr;
-        asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
-        cacheline_size = 4 << ((ctr >> 16) & 0xf);
-        start = round_down(start, cacheline_size);
-        end = round_up(end, cacheline_size);
-        outer_inv_range(start, end);
-        while (start < end) {
-                asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
-                     : "memory");
-                start += cacheline_size;
-        }
-        dsb();
-        isb();
-}
-/**
- * scm_call() - Send an SCM command
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @cmd_buf: command buffer
- * @cmd_len: length of the command buffer
- * @resp_buf: response buffer
- * @resp_len: length of the response buffer
- *
- * Sends a command to the SCM and waits for the command to finish processing.
- *
- * A note on cache maintenance:
- * Note that any buffers that are expected to be accessed by the secure world
- * must be flushed before invoking scm_call and invalidated in the cache
- * immediately after scm_call returns. Cache maintenance on the command and
- * response buffers is taken care of by scm_call; however, callers are
- * responsible for any other cached buffers passed over to the secure world.
- */
-int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
-                void *resp_buf, size_t resp_len)
-{
-        int ret;
-        struct scm_command *cmd;
-        struct scm_response *rsp;
-        unsigned long start, end;
-        cmd = alloc_scm_command(cmd_len, resp_len);
-        if (!cmd)
-                return -ENOMEM;
-        cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
-        if (cmd_buf)
-                memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
-        mutex_lock(&scm_lock);
-        ret = __scm_call(cmd);
-        mutex_unlock(&scm_lock);
-        if (ret)
-                goto out;
-        rsp = scm_command_to_response(cmd);
-        start = (unsigned long)rsp;
-        do {
-                scm_inv_range(start, start + sizeof(*rsp));
-        } while (!rsp->is_complete);
-        end = (unsigned long)scm_get_response_buffer(rsp) + resp_len;
-        scm_inv_range(start, end);
-        if (resp_buf)
-                memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
-out:
-        free_scm_command(cmd);
-        return ret;
-}
-EXPORT_SYMBOL(scm_call);
-u32 scm_get_version(void)
-{
-        int context_id;
-        static u32 version = -1;
-        register u32 r0 asm("r0");
-        register u32 r1 asm("r1");
-        if (version != -1)
-                return version;
-        mutex_lock(&scm_lock);
-        r0 = 0x1 << 8;
-        r1 = (u32)&context_id;
-        do {
-                asm volatile(
-                        __asmeq("%0", "r0")
-                        __asmeq("%1", "r1")
-                        __asmeq("%2", "r0")
-                        __asmeq("%3", "r1")
-#ifdef REQUIRES_SEC
-                        ".arch_extension sec\n"
-#endif
-                        "smc    #0      @ switch to secure world\n"
-                        : "=r" (r0), "=r" (r1)
-                        : "r" (r0), "r" (r1)
-                        : "r2", "r3");
-        } while (r0 == SCM_INTERRUPTED);
-        version = r1;
-        mutex_unlock(&scm_lock);
-        return version;
-}
-EXPORT_SYMBOL(scm_get_version);
diff --git a/arch/arm/mach-qcom/scm.h b/arch/arm/mach-qcom/scm.h
deleted file mode 100644
index 00b31ea58f29..000000000000
--- a/arch/arm/mach-qcom/scm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_SCM_H
-#define __MACH_SCM_H
-#define SCM_SVC_BOOT                    0x1
-#define SCM_SVC_PIL                     0x2
-extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
-                void *resp_buf, size_t resp_len);
-#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
-extern u32 scm_get_version(void);
-#endif
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index f26fcdca2445..5b4ca3c3c879 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -55,7 +55,7 @@ static int pmu_power_domain_is_on(int pd)
        return !(val & BIT(pd));
 }
-struct reset_control *rockchip_get_core_reset(int cpu)
+static struct reset_control *rockchip_get_core_reset(int cpu)
 {
        struct device *dev = get_cpu_device(cpu);
        struct device_node *np;
@@ -201,7 +201,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
        return 0;
 }
-static struct regmap_config rockchip_pmu_regmap_config = {
+static const struct regmap_config rockchip_pmu_regmap_config = {
        .reg_bits = 32,
        .val_bits = 32,
        .reg_stride = 4,
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 50cb781aaa36..b07d88602073 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level)
        regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
                    &rk3288_pmu_pwr_mode_con);
-        /* set bit 8 so that system will resume to FAST_BOOT_ADDR */
+        /*
+         * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
+         * PCLK_WDT_GATE - disable WDT during suspend.
+         */
        regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
-                     SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE);
+                     SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
+                     | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
        /* booting address of resuming system is from this register value */
        regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
@@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void)
                     rk3288_pmu_pwr_mode_con);
        regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
-                     rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE);
+                     rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
+                     | SGRF_FAST_BOOT_EN_WRITE);
 }
 static int rockchip_lpmode_enter(unsigned long arg)
@@ -209,6 +214,9 @@ static int rk3288_suspend_init(struct device_node *np)
        memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
               rk3288_bootram_sz);
+        regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
+        regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
        return 0;
 }
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 7c889c04604b..03ff31d8282d 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -50,6 +50,8 @@ static inline void rockchip_suspend_init(void)
 #define RK3288_SGRF_SOC_CON0            (0x0000)
 #define RK3288_SGRF_FAST_BOOT_ADDR      (0x0120)
+#define SGRF_PCLK_WDT_GATE              BIT(6)
+#define SGRF_PCLK_WDT_GATE_WRITE        BIT(22)
 #define SGRF_FAST_BOOT_EN               BIT(8)
 #define SGRF_FAST_BOOT_EN_WRITE         BIT(24)
@@ -63,6 +65,10 @@ static inline void rockchip_suspend_init(void)
 /* PMU_WAKEUP_CFG1 bits */
 #define PMU_ARMINT_WAKEUP_EN            BIT(0)
+/* wait 30ms for OSC stable and 30ms for pmic stable */
+#define OSC_STABL_CNT_THRESH    (32 * 30)
+#define PMU_STABL_CNT_THRESH    (32 * 30)
 enum rk3288_pwr_mode_con {
        PMU_PWR_MODE_EN = 0,
        PMU_CLK_CORE_SRC_GATE_EN,
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 79c49ff77f6e..23bec3a85b22 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -39,14 +39,14 @@ config CPU_S3C2412
        bool "SAMSUNG S3C2412"
        select CPU_ARM926T
        select S3C2412_COMMON_CLK
-        select S3C2412_PM if PM
+        select S3C2412_PM if PM_SLEEP
        help
          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 config CPU_S3C2416
        bool "SAMSUNG S3C2416/S3C2450"
        select CPU_ARM926T
-        select S3C2416_PM if PM
+        select S3C2416_PM if PM_SLEEP
        select S3C2443_COMMON_CLK
        help
          Support for the S3C2416 SoC from the S3C24XX line
@@ -55,7 +55,7 @@ config CPU_S3C2440
        bool "SAMSUNG S3C2440"
        select CPU_ARM920T
        select S3C2410_COMMON_CLK
-        select S3C2410_PM if PM
+        select S3C2410_PM if PM_SLEEP
        help
          Support for S3C2440 Samsung Mobile CPU based systems.
@@ -63,7 +63,7 @@ config CPU_S3C2442
        bool "SAMSUNG S3C2442"
        select CPU_ARM920T
        select S3C2410_COMMON_CLK
-        select S3C2410_PM if PM
+        select S3C2410_PM if PM_SLEEP
        help
          Support for S3C2442 Samsung Mobile CPU based systems.
@@ -228,11 +228,6 @@ config H1940BT
          This is a simple driver that is able to control
          the state of built in bluetooth chip on h1940.
-config PM_H1940
-        bool
-        help
-          Internal node for H1940 and related PM
 config MACH_N30
        bool "Acer N30 family"
        select S3C_DEV_NAND
@@ -362,6 +357,7 @@ if CPU_S3C2416
 config S3C2416_PM
        bool
        select S3C2412_PM_SLEEP
+        select SAMSUNG_WAKEMASK
        help
          Internal config node to apply S3C2416 power management
@@ -584,6 +580,11 @@ config MACH_SMDK2443
 endif   # CPU_S3C2443
+config PM_H1940
+        bool
+        help
+          Internal node for H1940 and related PM
 endmenu # SAMSUNG S3C24XX SoCs Support
 endif   # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index b40a22fe082a..05920c8a5764 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -32,7 +32,8 @@ obj-$(CONFIG_CPU_S3C2443)	+= s3c2443.o
 # PM
-obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM_SLEEP)          += irq-pm.o sleep.o
 # common code
diff --git a/arch/arm/mach-s3c24xx/include/mach/pm-core.h b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
index 2eef7e6f7675..69459dbbdcad 100644
--- a/arch/arm/mach-s3c24xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
@@ -10,6 +10,11 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include "regs-clock.h"
+#include "regs-irq.h"
 static inline void s3c_pm_debug_init_uart(void)
 {
@@ -42,8 +47,23 @@ static inline void s3c_pm_arch_stop_clocks(void)
        __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
 }
-static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+/* s3c2410_pm_show_resume_irqs
-                                    unsigned long mask);
+ *
+ * print any IRQs asserted at resume time (ie, we woke from)
+*/
+static inline void s3c_pm_show_resume_irqs(int start, unsigned long which,
+                                           unsigned long mask)
+{
+        int i;
+        which &= ~mask;
+        for (i = 0; i <= 31; i++) {
+                if (which & (1L<<i)) {
+                        S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
+                }
+        }
+}
 static inline void s3c_pm_arch_show_resume_irqs(void)
 {
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 44923895f558..c0e328e37bd6 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -23,6 +23,7 @@
 #include "s3c2412-power.h"
+#ifdef CONFIG_PM_SLEEP
 extern void s3c2412_sleep_enter(void);
 static int s3c2416_cpu_suspend(unsigned long arg)
@@ -70,7 +71,7 @@ static __init int s3c2416_pm_init(void)
 }
 arch_initcall(s3c2416_pm_init);
+#endif
 static void s3c2416_pm_resume(void)
 {
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index b19256ec8d40..5d510bca0844 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -50,6 +50,7 @@
 #define PFX "s3c24xx-pm: "
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save core_save[] = {
        /* we restore the timings here, with the proviso that the board
         * brings the system up in an slower, or equal frequency setting
@@ -67,6 +68,7 @@ static struct sleep_save core_save[] = {
        SAVE_ITEM(S3C2410_BANKCON4),
        SAVE_ITEM(S3C2410_BANKCON5),
 };
+#endif
 /* s3c_pm_check_resume_pin
 *
@@ -121,7 +123,7 @@ void s3c_pm_configure_extint(void)
        }
 }
+#ifdef CONFIG_PM_SLEEP
 void s3c_pm_restore_core(void)
 {
        s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
@@ -131,4 +133,4 @@ void s3c_pm_save_core(void)
 {
        s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 }
+#endif
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 2a6985a4a0ff..5061d66ca10c 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -121,7 +121,7 @@ int __init s3c2410_init(void)
 {
        printk("S3C2410: Initialising architecture\n");
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&s3c2410_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index ecf2c77ab88b..64a13605cfc3 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -172,7 +172,7 @@ int __init s3c2412_init(void)
 {
        printk("S3C2412: Initialising architecture\n");
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&s3c2412_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index bfd4da86deb8..3f8ca2a3ef17 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -98,7 +98,7 @@ int __init s3c2416_init(void)
        s3c_adc_setname("s3c2416-adc");
        s3c_rtc_setname("s3c2416-rtc");
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&s3c2416_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        register_syscore_ops(&s3c2416_irq_syscore_ops);
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 03d379f1fc52..eb733555fab5 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -57,11 +57,11 @@ int __init s3c2440_init(void)
        /* register suspend/resume handlers */
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&s3c2410_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-#endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
+#endif
        /* register our system device for everything else */
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 7b043349f1c8..893998ede022 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -60,11 +60,11 @@ int __init s3c2442_init(void)
 {
        printk("S3C2442: Initialising architecture\n");
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&s3c2410_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-#endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
+#endif
        return device_register(&s3c2442_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 177f97802745..b14119585dc7 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -108,7 +108,7 @@ static int __init s3c2442_core_init(void)
 core_initcall(s3c2442_core_init);
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save s3c244x_sleep[] = {
        SAVE_ITEM(S3C2440_DSC0),
        SAVE_ITEM(S3C2440_DSC1),
@@ -127,12 +127,9 @@ static void s3c244x_resume(void)
 {
        s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
 }
-#else
-#define s3c244x_suspend NULL
-#define s3c244x_resume  NULL
-#endif
 struct syscore_ops s3c244x_pm_syscore_ops = {
        .suspend        = s3c244x_suspend,
        .resume         = s3c244x_resume,
 };
+#endif
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 26ca2427e53d..eff95e950d81 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -189,6 +189,7 @@ endchoice
 config SMDK6410_WM1190_EV1
        bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
        depends on MACH_SMDK6410
+        depends on I2C=y
        select MFD_WM8350_I2C
        select REGULATOR
        select REGULATOR_WM8350
@@ -203,6 +204,7 @@ config SMDK6410_WM1190_EV1
 config SMDK6410_WM1192_EV1
        bool "Support Wolfson Microelectronics 1192-EV1 PMIC card"
        depends on MACH_SMDK6410
+        depends on I2C=y
        select MFD_WM831X
        select MFD_WM831X_I2C
        select REGULATOR
@@ -269,8 +271,8 @@ config MACH_SMARTQ7
 config MACH_WLF_CRAGG_6410
        bool "Wolfson Cragganmore 6410"
+        depends on I2C=y
        select CPU_S3C6410
-        select I2C
        select LEDS_GPIO_REGISTER
        select S3C64XX_DEV_SPI0
        select S3C64XX_SETUP_FB_24BPP
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 12f67b61ca5f..17f4b07ec763 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CPU_S3C6410)	+= s3c6410.o
 # PM
-obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM_SLEEP)          += irq-pm.o sleep.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 # DMA support
diff --git a/arch/arm/mach-s3c64xx/crag6410.h b/arch/arm/mach-s3c64xx/crag6410.h
index 7bc66682687e..dcbe17f5e5f8 100644
--- a/arch/arm/mach-s3c64xx/crag6410.h
+++ b/arch/arm/mach-s3c64xx/crag6410.h
@@ -14,6 +14,7 @@
 #include <mach/gpio-samsung.h>
 #define GLENFARCLAS_PMIC_IRQ_BASE       IRQ_BOARD_START
+#define BANFF_PMIC_IRQ_BASE             (IRQ_BOARD_START + 64)
 #define PCA935X_GPIO_BASE               GPIO_BOARD_START
 #define CODEC_GPIO_BASE                 (GPIO_BOARD_START + 8)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 10b913baab28..65c426bc45f7 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -554,6 +554,7 @@ static struct wm831x_touch_pdata touch_pdata = {
 static struct wm831x_pdata crag_pmic_pdata = {
        .wm831x_num = 1,
+        .irq_base = BANFF_PMIC_IRQ_BASE,
        .gpio_base = BANFF_PMIC_GPIO_BASE,
        .soft_shutdown = true,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 661eb662d051..b7447a92276e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -209,7 +209,7 @@ static struct platform_device smdk6410_smsc911x = {
 };
 #ifdef CONFIG_REGULATOR
-static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = {
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
        REGULATOR_SUPPLY("PVDD", "0-001b"),
        REGULATOR_SUPPLY("AVDD", "0-001b"),
 };
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index aaf7bea4032f..75b14e756383 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -194,6 +194,7 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
 }
 #endif
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save core_save[] = {
        SAVE_ITEM(S3C64XX_MEM0DRVCON),
        SAVE_ITEM(S3C64XX_MEM1DRVCON),
@@ -238,6 +239,7 @@ void s3c_pm_save_core(void)
        s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
        s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 }
+#endif
 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
 * put the per-cpu code in here until any new cpu comes along and changes
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2f36c85eec4b..0fb484221c90 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -62,6 +62,10 @@ config ARCH_R8A7740
        select ARCH_RMOBILE
        select RENESAS_INTC_IRQPIN
+config ARCH_R8A7778
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_RCAR_GEN1
 config ARCH_R8A7779
        bool "R-Car H1 (R8A77790)"
        select ARCH_RCAR_GEN1
@@ -69,15 +73,22 @@ config ARCH_R8A7779
 config ARCH_R8A7790
        bool "R-Car H2 (R8A77900)"
        select ARCH_RCAR_GEN2
+        select I2C
 config ARCH_R8A7791
        bool "R-Car M2-W (R8A77910)"
        select ARCH_RCAR_GEN2
+        select I2C
 config ARCH_R8A7794
        bool "R-Car E2 (R8A77940)"
        select ARCH_RCAR_GEN2
+config ARCH_SH73A0
+        bool "SH-Mobile AG5 (R8A73A00)"
+        select ARCH_RMOBILE
+        select RENESAS_INTC_IRQPIN
 comment "Renesas ARM SoCs Board Type"
 config MACH_MARZEN
@@ -92,13 +103,6 @@ if ARCH_SHMOBILE_LEGACY
 comment "Renesas ARM SoCs System Type"
-config ARCH_SH7372
-        bool "SH-Mobile AP4 (SH7372)"
-        select ARCH_RMOBILE
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_CPU_SUSPEND if PM || CPU_IDLE
-        select SH_INTC
 config ARCH_SH73A0
        bool "SH-Mobile AG5 (R8A73A00)"
        select ARCH_RMOBILE
@@ -108,13 +112,6 @@ config ARCH_SH73A0
        select SH_INTC
        select RENESAS_INTC_IRQPIN
-config ARCH_R8A73A4
-        bool "R-Mobile APE6 (R8A73A40)"
-        select ARCH_RMOBILE
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select RENESAS_IRQC
 config ARCH_R8A7740
        bool "R-Mobile A1 (R8A77400)"
        select ARCH_RMOBILE
@@ -136,33 +133,6 @@ config ARCH_R8A7779
 comment "Renesas ARM SoCs Board Type"
-config MACH_APE6EVM
-        bool "APE6EVM board"
-        depends on ARCH_R8A73A4
-        select SMSC_PHY if SMSC911X
-        select USE_OF
-config MACH_APE6EVM_REFERENCE
-        bool "APE6EVM board - Reference Device Tree Implementation"
-        depends on ARCH_R8A73A4
-        select SMSC_PHY if SMSC911X
-        select USE_OF
-        ---help---
-           Use reference implementation of APE6EVM board support
-           which makes a greater use of device tree at the expense
-           of not supporting a number of devices.
-           This is intended to aid developers
-config MACH_MACKEREL
-        bool "mackerel board"
-        depends on ARCH_SH7372
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SMSC_PHY if SMSC911X
-        select SND_SOC_AK4642 if SND_SIMPLE_CARD
-        select USE_OF
 config MACH_ARMADILLO800EVA
        bool "Armadillo-800 EVA board"
        depends on ARCH_R8A7740
@@ -209,20 +179,6 @@ config MACH_KZM9G
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
        select USE_OF
-config MACH_KZM9G_REFERENCE
-        bool "KZM-A9-GT board - Reference Device Tree Implementation"
-        depends on ARCH_SH73A0
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SND_SOC_AK4642 if SND_SIMPLE_CARD
-        select USE_OF
-        ---help---
-           Use reference implementation of KZM-A9-GT board support
-           which makes as greater use of device tree at the expense
-           of not supporting a number of devices.
-           This is intended to aid developers
 comment "Renesas ARM SoCs System Configuration"
 config CPU_HAS_INTEVT
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index d53996e6da97..89e463de4479 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,14 +6,13 @@
 obj-y                           := timer.o console.o
 # CPU objects
-obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o intc-sh7372.o pm-sh7372.o
+obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o pm-sh73a0.o
-obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A73A4)      += setup-r8a73a4.o
 obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += setup-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o pm-r8a7779.o
-obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o pm-r8a7790.o
+obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o
-obj-$(CONFIG_ARCH_R8A7791)      += setup-r8a7791.o pm-r8a7791.o
+obj-$(CONFIG_ARCH_R8A7791)      += setup-r8a7791.o
 obj-$(CONFIG_ARCH_R8A7794)      += setup-r8a7794.o
 obj-$(CONFIG_ARCH_EMEV2)        += setup-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)     += setup-r7s72100.o
@@ -21,9 +20,7 @@ obj-$(CONFIG_ARCH_R7S72100)	+= setup-r7s72100.o
 # Clock objects
 ifndef CONFIG_COMMON_CLK
 obj-y                           += clock.o
-obj-$(CONFIG_ARCH_SH7372)       += clock-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += clock-sh73a0.o
-obj-$(CONFIG_ARCH_R8A73A4)      += clock-r8a73a4.o
 obj-$(CONFIG_ARCH_R8A7740)      += clock-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += clock-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += clock-r8a7779.o
@@ -35,6 +32,8 @@ cpu-y				:= platsmp.o headsmp.o
 # Shared SoC family objects
 obj-$(CONFIG_ARCH_RCAR_GEN2)    += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
 CFLAGS_setup-rcar-gen2.o        += -march=armv7-a
+obj-$(CONFIG_ARCH_R8A7790)      += regulator-quirk-rcar-gen2.o
+obj-$(CONFIG_ARCH_R8A7791)      += regulator-quirk-rcar-gen2.o
 # SMP objects
 smp-y                           := $(cpu-y)
@@ -46,27 +45,20 @@ smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o platsmp-scu.o
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
-obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
 obj-$(CONFIG_PM_RCAR)           += pm-rcar.o
 obj-$(CONFIG_PM_RMOBILE)        += pm-rmobile.o
+obj-$(CONFIG_ARCH_RCAR_GEN2)    += pm-rcar-gen2.o
-# special sh7372 handling for IRQ objects and low level sleep code
-obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o sleep-sh7372.o
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen-reference.o
 else
-obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
-obj-$(CONFIG_MACH_APE6EVM_REFERENCE)    += board-ape6evm-reference.o
-obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
-obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
+obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o intc-sh73a0.o
-obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 endif
 # Framework support
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 02532bea5300..e1ef19cef89c 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,13 +1,9 @@
 # per-board load address for uImage
 loadaddr-y      :=
-loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
-loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
-loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
-loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
 __ZRELADDR      := $(sort $(loadaddr-y))
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
deleted file mode 100644
index 3b68370b03a0..000000000000
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * APE6EVM board support
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_device.h>
-#include <linux/sh_clk.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "r8a73a4.h"
-static void __init ape6evm_add_standard_devices(void)
-{
-        struct clk *parent;
-        struct clk *mp;
-        r8a73a4_clock_init();
-        /* MP clock parent = extal2 */
-        parent      = clk_get(NULL, "extal2");
-        mp          = clk_get(NULL, "mp");
-        BUG_ON(IS_ERR(parent) || IS_ERR(mp));
-        clk_set_parent(mp, parent);
-        clk_put(parent);
-        clk_put(mp);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char *ape6evm_boards_compat_dt[] __initdata = {
-        "renesas,ape6evm-reference",
-        NULL,
-};
-DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_early     = shmobile_init_delay,
-        .init_machine   = ape6evm_add_standard_devices,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = ape6evm_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
deleted file mode 100644
index 444f22d370f0..000000000000
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * APE6EVM board support
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/kernel.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/sh_clk.h>
-#include <linux/smsc911x.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "irqs.h"
-#include "r8a73a4.h"
-/* LEDS */
-static struct gpio_led ape6evm_leds[] = {
-        {
-                .name           = "gnss-en",
-                .gpio           = 28,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }, {
-                .name           = "nfc-nrst",
-                .gpio           = 126,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }, {
-                .name           = "gnss-nrst",
-                .gpio           = 132,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }, {
-                .name           = "bt-wakeup",
-                .gpio           = 232,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }, {
-                .name           = "strobe",
-                .gpio           = 250,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }, {
-                .name           = "bbresetout",
-                .gpio           = 288,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        },
-};
-static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = {
-        .leds           = ape6evm_leds,
-        .num_leds       = ARRAY_SIZE(ape6evm_leds),
-};
-/* GPIO KEY */
-#define GPIO_KEY(c, g, d, ...) \
-        { .code = c, .gpio = g, .desc = d, .active_low = 1 }
-static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_0,                 324,    "S16"),
-        GPIO_KEY(KEY_MENU,              325,    "S17"),
-        GPIO_KEY(KEY_HOME,              326,    "S18"),
-        GPIO_KEY(KEY_BACK,              327,    "S19"),
-        GPIO_KEY(KEY_VOLUMEUP,          328,    "S20"),
-        GPIO_KEY(KEY_VOLUMEDOWN,        329,    "S21"),
-};
-static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = {
-        .buttons        = gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-};
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-/* SMSC LAN9220 */
-static const struct resource lan9220_res[] __initconst = {
-        DEFINE_RES_MEM(0x08000000, 0x1000),
-        {
-                .start  = irq_pin(40), /* IRQ40 */
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-        },
-};
-static const struct smsc911x_platform_config lan9220_data __initconst = {
-        .flags          = SMSC911X_USE_32BIT,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-};
-/*
- * MMC0 power supplies:
- * Both Vcc and VccQ to eMMC on APE6EVM are supplied by a tps80032 voltage
- * regulator. Until support for it is added to this file we simulate the
- * Vcc supply by a fixed always-on regulator
- */
-static struct regulator_consumer_supply vcc_mmc0_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
-};
-/*
- * SDHI0 power supplies:
- * Vcc to SDHI0 on APE6EVM is supplied by a GPIO-switchable regulator. VccQ is
- * provided by the same tps80032 regulator as both MMC0 voltages - see comment
- * above
- */
-static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-};
-static struct regulator_init_data vcc_sdhi0_init_data = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi0_consumers),
-        .consumer_supplies      = vcc_sdhi0_consumers,
-};
-static const struct fixed_voltage_config vcc_sdhi0_info __initconst = {
-        .supply_name = "SDHI0 Vcc",
-        .microvolts = 3300000,
-        .gpio = 76,
-        .enable_high = 1,
-        .init_data = &vcc_sdhi0_init_data,
-};
-/*
- * SDHI1 power supplies:
- * Vcc and VccQ to SDHI1 on APE6EVM are both fixed at 3.3V
- */
-static struct regulator_consumer_supply vcc_sdhi1_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-};
-/* MMCIF */
-static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
-        .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
-        .slave_id_tx    = SHDMA_SLAVE_MMCIF0_TX,
-        .slave_id_rx    = SHDMA_SLAVE_MMCIF0_RX,
-        .ccs_unsupported = true,
-};
-static const struct resource mmcif0_resources[] __initconst = {
-        DEFINE_RES_MEM(0xee200000, 0x100),
-        DEFINE_RES_IRQ(gic_spi(169)),
-};
-/* SDHI0 */
-static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-};
-static const struct resource sdhi0_resources[] __initconst = {
-        DEFINE_RES_MEM(0xee100000, 0x100),
-        DEFINE_RES_IRQ(gic_spi(165)),
-};
-/* SDHI1 */
-static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_NEEDS_POLL,
-};
-static const struct resource sdhi1_resources[] __initconst = {
-        DEFINE_RES_MEM(0xee120000, 0x100),
-        DEFINE_RES_IRQ(gic_spi(166)),
-};
-static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = {
-        /* SCIFA0 console */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
-                                  "scifa0_data", "scifa0"),
-        /* SMSC */
-        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
-                                  "irqc_irq40", "irqc"),
-        /* MMCIF0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
-                                  "mmc0_data8", "mmc0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
-                                  "mmc0_ctrl", "mmc0"),
-        /* SDHI0: uSD: no WP */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
-                                  "sdhi0_data4", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
-                                  "sdhi0_ctrl", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
-                                  "sdhi0_cd", "sdhi0"),
-        /* SDHI1 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
-                                  "sdhi1_data4", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
-                                  "sdhi1_ctrl", "sdhi1"),
-};
-static void __init ape6evm_add_standard_devices(void)
-{
-        struct clk *parent;
-        struct clk *mp;
-        r8a73a4_clock_init();
-        /* MP clock parent = extal2 */
-        parent      = clk_get(NULL, "extal2");
-        mp          = clk_get(NULL, "mp");
-        BUG_ON(IS_ERR(parent) || IS_ERR(mp));
-        clk_set_parent(mp, parent);
-        clk_put(parent);
-        clk_put(mp);
-        pinctrl_register_mappings(ape6evm_pinctrl_map,
-                                  ARRAY_SIZE(ape6evm_pinctrl_map));
-        r8a73a4_pinmux_init();
-        r8a73a4_add_standard_devices();
-        /* LAN9220 ethernet */
-        gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        platform_device_register_resndata(NULL, "smsc911x", -1,
-                                          lan9220_res, ARRAY_SIZE(lan9220_res),
-                                          &lan9220_data, sizeof(lan9220_data));
-        regulator_register_always_on(1, "MMC0 Vcc", vcc_mmc0_consumers,
-                                     ARRAY_SIZE(vcc_mmc0_consumers), 2800000);
-        platform_device_register_resndata(NULL, "sh_mmcif", 0,
-                                          mmcif0_resources, ARRAY_SIZE(mmcif0_resources),
-                                          &mmcif0_pdata, sizeof(mmcif0_pdata));
-        platform_device_register_data(NULL, "reg-fixed-voltage", 2,
-                                      &vcc_sdhi0_info, sizeof(vcc_sdhi0_info));
-        platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
-                                          sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
-                                          &sdhi0_pdata, sizeof(sdhi0_pdata));
-        regulator_register_always_on(3, "SDHI1 Vcc", vcc_sdhi1_consumers,
-                                     ARRAY_SIZE(vcc_sdhi1_consumers), 3300000);
-        platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1,
-                                          sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
-                                          &sdhi1_pdata, sizeof(sdhi1_pdata));
-        platform_device_register_data(NULL, "gpio-keys", -1,
-                                      &ape6evm_keys_pdata,
-                                      sizeof(ape6evm_keys_pdata));
-        platform_device_register_data(NULL, "leds-gpio", -1,
-                                      &ape6evm_leds_pdata,
-                                      sizeof(ape6evm_leds_pdata));
-}
-static void __init ape6evm_legacy_init_time(void)
-{
-        /* Do not invoke DT-based timers via clocksource_of_init() */
-}
-static void __init ape6evm_legacy_init_irq(void)
-{
-        void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
-        void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-        /* Do not invoke DT-based interrupt code via irqchip_init() */
-}
-static const char *ape6evm_boards_compat_dt[] __initdata = {
-        "renesas,ape6evm",
-        NULL,
-};
-DT_MACHINE_START(APE6EVM_DT, "ape6evm")
-        .init_early     = shmobile_init_delay,
-        .init_irq       = ape6evm_legacy_init_irq,
-        .init_machine   = ape6evm_add_standard_devices,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = ape6evm_boards_compat_dt,
-        .init_time      = ape6evm_legacy_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index d649ade4a202..9a74efda3d18 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -36,7 +36,9 @@ static void __init bockw_init(void)
        void __iomem *fpga;
        void __iomem *pfc;
+#ifndef CONFIG_COMMON_CLK
        r8a7778_clock_init();
+#endif
        r8a7778_init_irq_extpin_dt(1);
        r8a7778_add_dt_devices();
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
deleted file mode 100644
index 2e82e44ab852..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * KZM-A9-GT board support - Reference Device Tree Implementation
- *
- * Copyright (C) 2012   Horms Solutions Ltd.
- *
- * Based on board-kzm9g.c
- * Copyright (C) 2012   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/input.h>
-#include <linux/of_platform.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "sh73a0.h"
-static void __init kzm_init(void)
-{
-        sh73a0_add_standard_devices_dt();
-#ifdef CONFIG_CACHE_L2X0
-        /* Shared attribute override enable, 64K*8way */
-        l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
-#endif
-}
-#define RESCNT2 IOMEM(0xe6188020)
-static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
-{
-        /* Do soft power on reset */
-        writel((1 << 31), RESCNT2);
-}
-static const char *kzm9g_boards_compat_dt[] __initdata = {
-        "renesas,kzm9g-reference",
-        NULL,
-};
-DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
-        .smp            = smp_ops(sh73a0_smp_ops),
-        .map_io         = sh73a0_map_io,
-        .init_early     = shmobile_init_delay,
-        .init_machine   = kzm_init,
-        .init_late      = shmobile_init_late,
-        .restart        = kzm9g_restart,
-        .dt_compat      = kzm9g_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
deleted file mode 100644
index a1c1dfb6a67a..000000000000
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ /dev/null
@@ -1,1522 +0,0 @@
-/*
- * mackerel board support
- *
- * Copyright (C) 2010 Renesas Solutions Corp.
- * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * based on ap4evb
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/sh_flctl.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/gpio_backlight.h>
-#include <linux/pm_clock.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/sh_clk.h>
-#include <linux/tca6416_keypad.h>
-#include <linux/usb/renesas_usbhs.h>
-#include <linux/dma-mapping.h>
-#include <video/sh_mobile_hdmi.h>
-#include <video/sh_mobile_lcdc.h>
-#include <media/sh_mobile_ceu.h>
-#include <media/soc_camera.h>
-#include <media/soc_camera_platform.h>
-#include <sound/sh_fsi.h>
-#include <sound/simple_card.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include "common.h"
-#include "intc.h"
-#include "irqs.h"
-#include "pm-rmobile.h"
-#include "sh-gpio.h"
-#include "sh7372.h"
-/*
- * Address      Interface               BusWidth        note
- * ------------------------------------------------------------------
- * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
- * 0x0800_0000  user area               -
- * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
- * 0x1400_0000  Ether (LAN9220)         16bit
- * 0x1600_0000  user area               -               cannot use with NAND
- * 0x1800_0000  user area               -
- * 0x1A00_0000  -
- * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
- */
-/*
- * CPU mode
- *
- * SW4                                     | Boot Area| Master   | Remarks
- *  1  | 2   | 3   | 4   | 5   | 6   | 8   |          | Processor|
- * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
- * ON  | ON  | OFF | ON  | ON  | OFF | OFF | External | System   | External ROM
- * ON  | ON  | ON  | ON  | ON  | OFF | OFF | External | System   | ROM Debug
- * ON  | ON  | X   | ON  | OFF | OFF | OFF | Built-in | System   | ROM Debug
- * X   | OFF | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
- * OFF | X   | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
- * X   | X   | X   | OFF | X   | X   | OFF | Built-in | System   | MaskROM
- * OFF | ON  | OFF | X   | X   | OFF | ON  | External | System   | Standalone
- * ON  | OFF | OFF | X   | X   | OFF | ON  | External | Realtime | Standalone
-*/
-/*
- * NOR Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NOR Flash ROM
- *  bit1 | bit1  bit2 | bit1 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    Area 0
- *  OFF  | ON     OFF | OFF  |    Area 4
- */
-/*
- * SMSC 9220
- *
- *  SW1         SMSC 9220
- * -----------------------
- *  ON          access disable
- *  OFF         access enable
- */
-/*
- * NAND Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NAND Flash ROM
- *  bit1 | bit1  bit2 | bit2 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    FCE 0
- *  OFF  | ON     OFF | OFF  |    FCE 1
- */
-/*
- * External interrupt pin settings
- *
- * IRQX  | pin setting        | device             | level
- * ------+--------------------+--------------------+-------
- * IRQ0  | ICR1A.IRQ0SA=0010  | SDHI2 card detect  | Low
- * IRQ6  | ICR1A.IRQ6SA=0011  | Ether(LAN9220)     | High
- * IRQ7  | ICR1A.IRQ7SA=0010  | LCD Touch Panel    | Low
- * IRQ8  | ICR2A.IRQ8SA=0010  | MMC/SD card detect | Low
- * IRQ9  | ICR2A.IRQ9SA=0010  | KEY(TCA6408)       | Low
- * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345)    | High
- * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975)     | High
- */
-/*
- * USB
- *
- * USB0 : CN22 : Function
- * USB1 : CN31 : Function/Host *1
- *
- * J30 (for CN31) *1
- * ----------+---------------+-------------
- * 1-2 short | VBUS 5V       | Host
- * open      | external VBUS | Function
- *
- * CAUTION
- *
- * renesas_usbhs driver can use external interrupt mode
- * (which come from USB-PHY) or autonomy mode (it use own interrupt)
- * for detecting connection/disconnection when Function.
- * USB will be power OFF while it has been disconnecting
- * if external interrupt mode, and it is always power ON if autonomy mode,
- *
- * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
- * because Touchscreen is using IRQ7-PORT40.
- * It is impossible to use IRQ7 demux on this board.
- */
-/*
- * SDHI0 (CN12)
- *
- * SW56 : OFF
- *
- */
-/* MMC /SDHI1 (CN7)
- *
- * I/O voltage : 1.8v
- *
- * Power voltage : 1.8v or 3.3v
- *  J22 : select power voltage *1
- *      1-2 pin : 1.8v
- *      2-3 pin : 3.3v
- *
- * *1
- * Please change J22 depends the card to be used.
- * MMC's OCR field set to support either voltage for the card inserted.
- *
- *      SW1     |       SW33
- *              | bit1 | bit2 | bit3 | bit4
- * -------------+------+------+------+-------
- * MMC0   OFF   |  OFF |   X  |  ON  |  X       (Use MMCIF)
- * SDHI1  OFF   |  ON  |   X  |  OFF |  X       (Use MFD_SH_MOBILE_SDHI)
- *
- */
-/*
- * SDHI2 (CN23)
- *
- * microSD card sloct
- *
- */
-/*
- * FSI - AK4642
- *
- * it needs amixer settings for playing
- *
- * amixer set "Headphone Enable" on
- */
-/* Fixed 3.3V and 1.8V regulators to be used by multiple devices */
-static struct regulator_consumer_supply fixed1v8_power_consumers[] =
-{
-        /*
-         * J22 on mackerel switches mmcif.0 and sdhi.1 between 1.8V and 3.3V
-         * Since we cannot support both voltages, we support the default 1.8V
-         */
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
-};
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
-};
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-/* MTD */
-static struct mtd_partition nor_flash_partitions[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel_ro",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 2,
-        .parts          = nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
-};
-static struct resource nor_flash_resources[] = {
-        [0]     = {
-                .start  = 0x20000000, /* CS0 shadow instead of regular CS0 */
-                .end    = 0x28000000 - 1, /* needed by USB MASK ROM boot */
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device nor_flash_device = {
-        .name           = "physmap-flash",
-        .dev            = {
-                .platform_data  = &nor_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-        .resource       = nor_flash_resources,
-};
-/* SMSC */
-static struct resource smc911x_resources[] = {
-        {
-                .start  = 0x14000000,
-                .end    = 0x16000000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = evt2irq(0x02c0) /* IRQ6A */,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-static struct smsc911x_platform_config smsc911x_info = {
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-static struct platform_device smc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smc911x_resources),
-        .resource       = smc911x_resources,
-        .dev            = {
-                .platform_data = &smsc911x_info,
-        },
-};
-/* MERAM */
-static struct sh_mobile_meram_info mackerel_meram_info = {
-        .addr_mode      = SH_MOBILE_MERAM_MODE1,
-};
-static struct resource meram_resources[] = {
-        [0] = {
-                .name   = "regs",
-                .start  = 0xe8000000,
-                .end    = 0xe807ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "meram",
-                .start  = 0xe8080000,
-                .end    = 0xe81fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device meram_device = {
-        .name           = "sh_mobile_meram",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(meram_resources),
-        .resource       = meram_resources,
-        .dev            = {
-                .platform_data = &mackerel_meram_info,
-        },
-};
-/* LCDC and backlight */
-static struct fb_videomode mackerel_lcdc_modes[] = {
-        {
-                .name           = "WVGA Panel",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 220,
-                .right_margin   = 110,
-                .hsync_len      = 70,
-                .upper_margin   = 20,
-                .lower_margin   = 5,
-                .vsync_len      = 5,
-                .sync           = 0,
-        },
-};
-static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x40,
-        },
-        .icb[1] = {
-                .meram_size     = 0x40,
-        },
-};
-static struct sh_mobile_lcdc_info lcdc_info = {
-        .meram_dev = &mackerel_meram_info,
-        .clock_source = LCDC_CLK_BUS,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_modes = mackerel_lcdc_modes,
-                .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
-                .interface_type         = RGB24,
-                .clock_divider          = 3,
-                .flags                  = 0,
-                .panel_cfg = {
-                        .width          = 152,
-                        .height         = 91,
-                },
-                .meram_cfg = &lcd_meram_cfg,
-        }
-};
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .name   = "LCDC",
-                .start  = 0xfe940000,
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device lcdc_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-        .resource       = lcdc_resources,
-        .dev    = {
-                .platform_data  = &lcdc_info,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-static struct gpio_backlight_platform_data gpio_backlight_data = {
-        .fbdev = &lcdc_device.dev,
-        .gpio = 31,
-        .def_value = 1,
-        .name = "backlight",
-};
-static struct platform_device gpio_backlight_device = {
-        .name = "gpio-backlight",
-        .dev = {
-                .platform_data = &gpio_backlight_data,
-        },
-};
-/* HDMI */
-static struct sh_mobile_hdmi_info hdmi_info = {
-        .flags          = HDMI_SND_SRC_SPDIF,
-};
-static struct resource hdmi_resources[] = {
-        [0] = {
-                .name   = "HDMI",
-                .start  = 0xe6be0000,
-                .end    = 0xe6be00ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
-                .start  = evt2irq(0x17e0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device hdmi_device = {
-        .name           = "sh-mobile-hdmi",
-        .num_resources  = ARRAY_SIZE(hdmi_resources),
-        .resource       = hdmi_resources,
-        .id             = -1,
-        .dev    = {
-                .platform_data  = &hdmi_info,
-        },
-};
-static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x100,
-        },
-        .icb[1] = {
-                .meram_size     = 0x100,
-        },
-};
-static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
-        .meram_dev = &mackerel_meram_info,
-        .clock_source = LCDC_CLK_EXTERNAL,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type = RGB24,
-                .clock_divider = 1,
-                .flags = LCDC_FLAGS_DWPOL,
-                .meram_cfg = &hdmi_meram_cfg,
-                .tx_dev = &hdmi_device,
-        }
-};
-static struct resource hdmi_lcdc_resources[] = {
-        [0] = {
-                .name   = "LCDC1",
-                .start  = 0xfe944000,
-                .end    = 0xfe947fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x1780),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device hdmi_lcdc_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(hdmi_lcdc_resources),
-        .resource       = hdmi_lcdc_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &hdmi_lcdc_info,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-static struct asoc_simple_card_info fsi2_hdmi_info = {
-        .name           = "HDMI",
-        .card           = "FSI2B-HDMI",
-        .codec          = "sh-mobile-hdmi",
-        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_CBS_CFS,
-        .cpu_dai = {
-                .name   = "fsib-dai",
-        },
-        .codec_dai = {
-                .name   = "sh_mobile_hdmi-hifi",
-        },
-};
-static struct platform_device fsi_hdmi_device = {
-        .name   = "asoc-simple-card",
-        .id     = 1,
-        .dev    = {
-                .platform_data  = &fsi2_hdmi_info,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .dma_mask = &fsi_hdmi_device.dev.coherent_dma_mask,
-        },
-};
-static void __init hdmi_init_pm_clock(void)
-{
-        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
-        int ret;
-        long rate;
-        if (IS_ERR(hdmi_ick)) {
-                ret = PTR_ERR(hdmi_ick);
-                pr_err("Cannot get HDMI ICK: %d\n", ret);
-                goto out;
-        }
-        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
-        if (ret < 0) {
-                pr_err("Cannot set PLLC2 parent: %d, %d users\n",
-                       ret, sh7372_pllc2_clk.usecount);
-                goto out;
-        }
-        pr_debug("PLLC2 initial frequency %lu\n",
-                 clk_get_rate(&sh7372_pllc2_clk));
-        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
-        if (rate <= 0) {
-                pr_err("Cannot get suitable rate: %ld\n", rate);
-                ret = -EINVAL;
-                goto out;
-        }
-        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
-        if (ret < 0) {
-                pr_err("Cannot set rate %ld: %d\n", rate, ret);
-                goto out;
-        }
-        pr_debug("PLLC2 set frequency %lu\n", rate);
-        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
-        if (ret < 0)
-                pr_err("Cannot set HDMI parent: %d\n", ret);
-out:
-        if (!IS_ERR(hdmi_ick))
-                clk_put(hdmi_ick);
-}
-/* USBHS0 is connected to CN22 which takes a USB Mini-B plug
- *
- * The sh7372 SoC has IRQ7 set aside for USBHS0 hotplug,
- * but on this particular board IRQ7 is already used by
- * the touch screen. This leaves us with software polling.
- */
-#define USBHS0_POLL_INTERVAL (HZ * 5)
-struct usbhs_private {
-        void __iomem *usbphyaddr;
-        void __iomem *usbcrcaddr;
-        struct renesas_usbhs_platform_info info;
-        struct delayed_work work;
-        struct platform_device *pdev;
-};
-#define usbhs_get_priv(pdev)                            \
-        container_of(renesas_usbhs_get_info(pdev),      \
-                     struct usbhs_private, info)
-#define usbhs_is_connected(priv)                        \
-        (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
-static int usbhs_get_vbus(struct platform_device *pdev)
-{
-        return usbhs_is_connected(usbhs_get_priv(pdev));
-}
-static int usbhs_phy_reset(struct platform_device *pdev)
-{
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        /* init phy */
-        __raw_writew(0x8a0a, priv->usbcrcaddr);
-        return 0;
-}
-static int usbhs0_get_id(struct platform_device *pdev)
-{
-        return USBHS_GADGET;
-}
-static void usbhs0_work_function(struct work_struct *work)
-{
-        struct usbhs_private *priv = container_of(work, struct usbhs_private,
-                                                  work.work);
-        renesas_usbhs_call_notify_hotplug(priv->pdev);
-        schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
-}
-static int usbhs0_hardware_init(struct platform_device *pdev)
-{
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        priv->pdev = pdev;
-        INIT_DELAYED_WORK(&priv->work, usbhs0_work_function);
-        schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
-        return 0;
-}
-static int usbhs0_hardware_exit(struct platform_device *pdev)
-{
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        cancel_delayed_work_sync(&priv->work);
-        return 0;
-}
-static struct usbhs_private usbhs0_private = {
-        .usbcrcaddr     = IOMEM(0xe605810c),            /* USBCR2 */
-        .info = {
-                .platform_callback = {
-                        .hardware_init  = usbhs0_hardware_init,
-                        .hardware_exit  = usbhs0_hardware_exit,
-                        .phy_reset      = usbhs_phy_reset,
-                        .get_id         = usbhs0_get_id,
-                        .get_vbus       = usbhs_get_vbus,
-                },
-                .driver_param = {
-                        .buswait_bwait  = 4,
-                        .d0_tx_id       = SHDMA_SLAVE_USB0_TX,
-                        .d1_rx_id       = SHDMA_SLAVE_USB0_RX,
-                },
-        },
-};
-static struct resource usbhs0_resources[] = {
-        [0] = {
-                .name   = "USBHS0",
-                .start  = 0xe6890000,
-                .end    = 0xe68900e6 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x1ca0) /* USB0_USB0I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usbhs0_device = {
-        .name   = "renesas_usbhs",
-        .id     = 0,
-        .dev = {
-                .platform_data          = &usbhs0_private.info,
-        },
-        .num_resources  = ARRAY_SIZE(usbhs0_resources),
-        .resource       = usbhs0_resources,
-};
-/* USBHS1 is connected to CN31 which takes a USB Mini-AB plug
- *
- * Use J30 to select between Host and Function. This setting
- * can however not be detected by software. Hotplug of USBHS1
- * is provided via IRQ8.
- *
- * Current USB1 works as "USB Host".
- *  - set J30 "short"
- *
- * If you want to use it as "USB gadget",
- *  - J30 "open"
- *  - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
- *  - add .get_vbus = usbhs_get_vbus in usbhs1_private
- *  - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices.
- */
-#define IRQ8 evt2irq(0x0300)
-#define USB_PHY_MODE            (1 << 4)
-#define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
-#define USB_PHY_ON              (1 << 1)
-#define USB_PHY_OFF             (1 << 0)
-#define USB_PHY_INT_CLR         (USB_PHY_ON | USB_PHY_OFF)
-static irqreturn_t usbhs1_interrupt(int irq, void *data)
-{
-        struct platform_device *pdev = data;
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        dev_dbg(&pdev->dev, "%s\n", __func__);
-        renesas_usbhs_call_notify_hotplug(pdev);
-        /* clear status */
-        __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
-                     priv->usbphyaddr);
-        return IRQ_HANDLED;
-}
-static int usbhs1_hardware_init(struct platform_device *pdev)
-{
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        int ret;
-        /* clear interrupt status */
-        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
-        ret = request_irq(IRQ8, usbhs1_interrupt, IRQF_TRIGGER_HIGH,
-                          dev_name(&pdev->dev), pdev);
-        if (ret) {
-                dev_err(&pdev->dev, "request_irq err\n");
-                return ret;
-        }
-        /* enable USB phy interrupt */
-        __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
-        return 0;
-}
-static int usbhs1_hardware_exit(struct platform_device *pdev)
-{
-        struct usbhs_private *priv = usbhs_get_priv(pdev);
-        /* clear interrupt status */
-        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
-        free_irq(IRQ8, pdev);
-        return 0;
-}
-static int usbhs1_get_id(struct platform_device *pdev)
-{
-        return USBHS_HOST;
-}
-static u32 usbhs1_pipe_cfg[] = {
-        USB_ENDPOINT_XFER_CONTROL,
-        USB_ENDPOINT_XFER_ISOC,
-        USB_ENDPOINT_XFER_ISOC,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_INT,
-        USB_ENDPOINT_XFER_INT,
-        USB_ENDPOINT_XFER_INT,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-        USB_ENDPOINT_XFER_BULK,
-};
-static struct usbhs_private usbhs1_private = {
-        .usbphyaddr     = IOMEM(0xe60581e2),    /* USBPHY1INTAP */
-        .usbcrcaddr     = IOMEM(0xe6058130),    /* USBCR4 */
-        .info = {
-                .platform_callback = {
-                        .hardware_init  = usbhs1_hardware_init,
-                        .hardware_exit  = usbhs1_hardware_exit,
-                        .get_id         = usbhs1_get_id,
-                        .phy_reset      = usbhs_phy_reset,
-                },
-                .driver_param = {
-                        .buswait_bwait  = 4,
-                        .has_otg        = 1,
-                        .pipe_type      = usbhs1_pipe_cfg,
-                        .pipe_size      = ARRAY_SIZE(usbhs1_pipe_cfg),
-                        .d0_tx_id       = SHDMA_SLAVE_USB1_TX,
-                        .d1_rx_id       = SHDMA_SLAVE_USB1_RX,
-                },
-        },
-};
-static struct resource usbhs1_resources[] = {
-        [0] = {
-                .name   = "USBHS1",
-                .start  = 0xe68b0000,
-                .end    = 0xe68b00e6 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usbhs1_device = {
-        .name   = "renesas_usbhs",
-        .id     = 1,
-        .dev = {
-                .platform_data          = &usbhs1_private.info,
-                .dma_mask               = &usbhs1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(usbhs1_resources),
-        .resource       = usbhs1_resources,
-};
-/* LED */
-static struct gpio_led mackerel_leds[] = {
-        {
-                .name           = "led0",
-                .gpio           = 0,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name           = "led1",
-                .gpio           = 1,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name           = "led2",
-                .gpio           = 2,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name           = "led3",
-                .gpio           = 159,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        }
-};
-static struct gpio_led_platform_data mackerel_leds_pdata = {
-        .leds = mackerel_leds,
-        .num_leds = ARRAY_SIZE(mackerel_leds),
-};
-static struct platform_device leds_device = {
-        .name = "leds-gpio",
-        .id = 0,
-        .dev = {
-                .platform_data  = &mackerel_leds_pdata,
-        },
-};
-/* FSI */
-#define IRQ_FSI evt2irq(0x1840)
-static struct sh_fsi_platform_info fsi_info = {
-        .port_a = {
-                .tx_id = SHDMA_SLAVE_FSIA_TX,
-                .rx_id = SHDMA_SLAVE_FSIA_RX,
-        },
-        .port_b = {
-                .flags = SH_FSI_CLK_CPG |
-                         SH_FSI_FMT_SPDIF,
-        }
-};
-static struct resource fsi_resources[] = {
-        [0] = {
-                /* we need 0xFE1F0000 to access DMA
-                 * instead of 0xFE3C0000 */
-                .name   = "FSI",
-                .start  = 0xFE1F0000,
-                .end    = 0xFE1F0400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_FSI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device fsi_device = {
-        .name           = "sh_fsi2",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(fsi_resources),
-        .resource       = fsi_resources,
-        .dev    = {
-                .platform_data  = &fsi_info,
-        },
-};
-static struct asoc_simple_card_info fsi2_ak4643_info = {
-        .name           = "AK4643",
-        .card           = "FSI2A-AK4643",
-        .codec          = "ak4642-codec.0-0013",
-        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_dai = {
-                .name   = "fsia-dai",
-        },
-        .codec_dai = {
-                .name   = "ak4642-hifi",
-                .sysclk = 11289600,
-        },
-};
-static struct platform_device fsi_ak4643_device = {
-        .name   = "asoc-simple-card",
-        .dev    = {
-                .platform_data  = &fsi2_ak4643_info,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .dma_mask = &fsi_ak4643_device.dev.coherent_dma_mask,
-        },
-};
-/* FLCTL */
-static struct mtd_partition nand_partition_info[] = {
-        {
-                .name   = "system",
-                .offset = 0,
-                .size   = 128 * 1024 * 1024,
-        },
-        {
-                .name   = "userdata",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 256 * 1024 * 1024,
-        },
-        {
-                .name   = "cache",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 128 * 1024 * 1024,
-        },
-};
-static struct resource nand_flash_resources[] = {
-        [0] = {
-                .start  = 0xe6a30000,
-                .end    = 0xe6a3009b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0d80), /* flstei: status error irq */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct sh_flctl_platform_data nand_flash_data = {
-        .parts          = nand_partition_info,
-        .nr_parts       = ARRAY_SIZE(nand_partition_info),
-        .flcmncr_val    = CLK_16B_12L_4H | TYPESEL_SET
-                        | SHBUSSEL | SEL_16BIT | SNAND_E,
-        .use_holden     = 1,
-};
-static struct platform_device nand_flash_device = {
-        .name           = "sh_flctl",
-        .resource       = nand_flash_resources,
-        .num_resources  = ARRAY_SIZE(nand_flash_resources),
-        .dev            = {
-                .platform_data = &nand_flash_data,
-        },
-};
-/* SDHI0 */
-static struct sh_mobile_sdhi_info sdhi0_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_flags     = TMIO_MMC_USE_GPIO_CD,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-        .cd_gpio        = 172,
-};
-static struct resource sdhi0_resources[] = {
-        {
-                .name   = "SDHI0",
-                .start  = 0xe6850000,
-                .end    = 0xe68500ff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
-                .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
-                .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi0_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi0_resources),
-        .resource       = sdhi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &sdhi0_info,
-        },
-};
-#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
-/* SDHI1 */
-/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
-static struct sh_mobile_sdhi_info sdhi1_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
-        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_NEEDS_POLL,
-        .cd_gpio        = 41,
-};
-static struct resource sdhi1_resources[] = {
-        {
-                .name   = "SDHI1",
-                .start  = 0xe6860000,
-                .end    = 0xe68600ff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
-                .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
-                .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi1_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi1_resources),
-        .resource       = sdhi1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sdhi1_info,
-        },
-};
-#endif
-/* SDHI2 */
-/*
- * The card detect pin of the top SD/MMC slot (CN23) is active low and is
- * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
- */
-static struct sh_mobile_sdhi_info sdhi2_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI2_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI2_RX,
-        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_NEEDS_POLL,
-        .cd_gpio        = 162,
-};
-static struct resource sdhi2_resources[] = {
-        {
-                .name   = "SDHI2",
-                .start  = 0xe6870000,
-                .end    = 0xe68700ff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
-                .start  = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
-                .start  = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi2_device = {
-        .name   = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi2_resources),
-        .resource       = sdhi2_resources,
-        .id             = 2,
-        .dev    = {
-                .platform_data  = &sdhi2_info,
-        },
-};
-/* SH_MMCIF */
-#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
-static struct resource sh_mmcif_resources[] = {
-        [0] = {
-                .name   = "MMCIF",
-                .start  = 0xE6BD0000,
-                .end    = 0xE6BD00FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* MMC ERR */
-                .start  = evt2irq(0x1ac0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* MMC NOR */
-                .start  = evt2irq(0x1ae0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct sh_mmcif_plat_data sh_mmcif_plat = {
-        .sup_pclk       = 0,
-        .caps           = MMC_CAP_4_BIT_DATA |
-                          MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_NEEDS_POLL,
-        .use_cd_gpio    = true,
-        /* card detect pin for SD/MMC slot (CN7) */
-        .cd_gpio        = 41,
-        .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
-        .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
-};
-static struct platform_device sh_mmcif_device = {
-        .name           = "sh_mmcif",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = NULL,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &sh_mmcif_plat,
-        },
-        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
-        .resource       = sh_mmcif_resources,
-};
-#endif
-static int mackerel_camera_add(struct soc_camera_device *icd);
-static void mackerel_camera_del(struct soc_camera_device *icd);
-static int camera_set_capture(struct soc_camera_platform_info *info,
-                              int enable)
-{
-        return 0; /* camera sensor always enabled */
-}
-static struct soc_camera_platform_info camera_info = {
-        .format_name = "UYVY",
-        .format_depth = 16,
-        .format = {
-                .code = MEDIA_BUS_FMT_UYVY8_2X8,
-                .colorspace = V4L2_COLORSPACE_SMPTE170M,
-                .field = V4L2_FIELD_NONE,
-                .width = 640,
-                .height = 480,
-        },
-        .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
-        V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
-        V4L2_MBUS_DATA_ACTIVE_HIGH,
-        .mbus_type = V4L2_MBUS_PARALLEL,
-        .set_capture = camera_set_capture,
-};
-static struct soc_camera_link camera_link = {
-        .bus_id         = 0,
-        .add_device     = mackerel_camera_add,
-        .del_device     = mackerel_camera_del,
-        .module_name    = "soc_camera_platform",
-        .priv           = &camera_info,
-};
-static struct platform_device *camera_device;
-static void mackerel_camera_release(struct device *dev)
-{
-        soc_camera_platform_release(&camera_device);
-}
-static int mackerel_camera_add(struct soc_camera_device *icd)
-{
-        return soc_camera_platform_add(icd, &camera_device, &camera_link,
-                                       mackerel_camera_release, 0);
-}
-static void mackerel_camera_del(struct soc_camera_device *icd)
-{
-        soc_camera_platform_del(icd, camera_device, &camera_link);
-}
-static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
-        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
-        .max_width = 8188,
-        .max_height = 8188,
-};
-static struct resource ceu_resources[] = {
-        [0] = {
-                .name   = "CEU",
-                .start  = 0xfe910000,
-                .end    = 0xfe91009f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x880),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* place holder for contiguous memory */
-        },
-};
-static struct platform_device ceu_device = {
-        .name           = "sh_mobile_ceu",
-        .id             = 0, /* "ceu0" clock */
-        .num_resources  = ARRAY_SIZE(ceu_resources),
-        .resource       = ceu_resources,
-        .dev            = {
-                .platform_data          = &sh_mobile_ceu_info,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct platform_device mackerel_camera = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &camera_link,
-        },
-};
-static struct platform_device *mackerel_devices[] __initdata = {
-        &nor_flash_device,
-        &smc911x_device,
-        &lcdc_device,
-        &gpio_backlight_device,
-        &usbhs0_device,
-        &usbhs1_device,
-        &leds_device,
-        &fsi_device,
-        &fsi_ak4643_device,
-        &fsi_hdmi_device,
-        &nand_flash_device,
-        &sdhi0_device,
-#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
-        &sdhi1_device,
-#else
-        &sh_mmcif_device,
-#endif
-        &sdhi2_device,
-        &ceu_device,
-        &mackerel_camera,
-        &hdmi_device,
-        &hdmi_lcdc_device,
-        &meram_device,
-};
-/* Keypad Initialization */
-#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
-{                                                               \
-        .type           = ev_type,                              \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-}
-#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
-static struct tca6416_button mackerel_gpio_keys[] = {
-        KEYPAD_BUTTON_LOW(KEY_HOME),
-        KEYPAD_BUTTON_LOW(KEY_MENU),
-        KEYPAD_BUTTON_LOW(KEY_BACK),
-        KEYPAD_BUTTON_LOW(KEY_POWER),
-};
-static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
-        .buttons        = mackerel_gpio_keys,
-        .nbuttons       = ARRAY_SIZE(mackerel_gpio_keys),
-        .rep            = 1,
-        .use_polling    = 0,
-        .pinmask        = 0x000F,
-};
-/* I2C */
-#define IRQ7 evt2irq(0x02e0)
-#define IRQ9 evt2irq(0x0320)
-static struct i2c_board_info i2c0_devices[] = {
-        {
-                I2C_BOARD_INFO("ak4643", 0x13),
-        },
-        /* Keypad */
-        {
-                I2C_BOARD_INFO("tca6408-keys", 0x20),
-                .platform_data = &mackerel_tca6416_keys_info,
-                .irq = IRQ9,
-        },
-        /* Touchscreen */
-        {
-                I2C_BOARD_INFO("st1232-ts", 0x55),
-                .irq = IRQ7,
-        },
-};
-#define IRQ21 evt2irq(0x32a0)
-static struct i2c_board_info i2c1_devices[] = {
-        /* Accelerometer */
-        {
-                I2C_BOARD_INFO("adxl34x", 0x53),
-                .irq = IRQ21,
-        },
-};
-static unsigned long pin_pulldown_conf[] = {
-        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0),
-};
-static const struct pinctrl_map mackerel_pinctrl_map[] = {
-        /* ADXL34X */
-        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
-                                  "intc_irq21", "intc"),
-        /* CEU */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
-                                  "ceu_data_0_7", "ceu"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
-                                  "ceu_clk_0", "ceu"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
-                                  "ceu_sync", "ceu"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
-                                  "ceu_field", "ceu"),
-        /* FLCTL */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
-                                  "flctl_data", "flctl"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
-                                  "flctl_ce0", "flctl"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
-                                  "flctl_ctrl", "flctl"),
-        /* FSIA (AK4643) */
-        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
-                                  "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
-                                  "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
-                                  "fsia_data_out", "fsia"),
-        /* FSIB (HDMI) */
-        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
-                                  "fsib_mclk_in", "fsib"),
-        /* HDMI */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
-                                  "hdmi", "hdmi"),
-        /* LCDC */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
-                                  "lcd_data24", "lcd"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
-                                  "lcd_sync", "lcd"),
-        /* SCIFA0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
-                                  "scifa0_data", "scifa0"),
-        /* SCIFA2 (GT-720F GPS module) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
-                                  "scifa2_data", "scifa2"),
-        /* SDHI0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_data4", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_ctrl", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_wp", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "intc_irq26_1", "intc"),
-        /* SDHI1 */
-#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_data4", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_ctrl", "sdhi1"),
-#else
-        /* MMCIF */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_data8_0", "mmc0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_ctrl_0", "mmc0"),
-#endif
-        /* SDHI2 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
-                                  "sdhi2_data4", "sdhi2"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
-                                  "sdhi2_ctrl", "sdhi2"),
-        /* SMSC911X */
-        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
-                                  "bsc_cs5a", "bsc"),
-        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
-                                  "intc_irq6_0", "intc"),
-        /* ST1232 */
-        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
-                                  "intc_irq7_0", "intc"),
-        /* TCA6416 */
-        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
-                                  "intc_irq9_0", "intc"),
-        /* USBHS0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
-                                  "usb0_vbus", "usb0"),
-        PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
-                                      "usb0_vbus", pin_pulldown_conf),
-        /* USBHS1 */
-        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
-                                  "usb1_vbus", "usb1"),
-        PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
-                                      "usb1_vbus", pin_pulldown_conf),
-        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
-                                  "usb1_otg_id_0", "usb1"),
-};
-#define GPIO_PORT9CR    IOMEM(0xE6051009)
-#define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define SRCR4           IOMEM(0xe61580bc)
-#define USCCR1          IOMEM(0xE6058144)
-static void __init mackerel_init(void)
-{
-        static struct pm_domain_device domain_devices[] __initdata = {
-                { "A4LC", &lcdc_device, },
-                { "A4LC", &hdmi_lcdc_device, },
-                { "A4LC", &meram_device, },
-                { "A4MP", &fsi_device, },
-                { "A3SP", &usbhs0_device, },
-                { "A3SP", &usbhs1_device, },
-                { "A3SP", &nand_flash_device, },
-                { "A3SP", &sdhi0_device, },
-#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
-                { "A3SP", &sdhi1_device, },
-#else
-                { "A3SP", &sh_mmcif_device, },
-#endif
-                { "A3SP", &sdhi2_device, },
-                { "A4R", &ceu_device, },
-        };
-        u32 srcr4;
-        struct clk *clk;
-        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
-                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
-        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
-                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-        pinctrl_register_mappings(mackerel_pinctrl_map,
-                                  ARRAY_SIZE(mackerel_pinctrl_map));
-        sh7372_pinmux_init();
-        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        /* FSI2 port A (ak4643) */
-        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-        gpio_request(9,  NULL);
-        gpio_request(10, NULL);
-        gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
-        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
-        intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
-        /* FSI2 port B (HDMI) */
-        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
-        /* set SPU2 clock to 119.6 MHz */
-        clk = clk_get(NULL, "spu_clk");
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, clk_round_rate(clk, 119600000));
-                clk_put(clk);
-        }
-        /* Keypad */
-        irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
-        /* Touchscreen */
-        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
-        /* Accelerometer */
-        irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
-        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-        srcr4 = __raw_readl(SRCR4);
-        __raw_writel(srcr4 | (1 << 13), SRCR4);
-        udelay(50);
-        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
-        i2c_register_board_info(0, i2c0_devices,
-                                ARRAY_SIZE(i2c0_devices));
-        i2c_register_board_info(1, i2c1_devices,
-                                ARRAY_SIZE(i2c1_devices));
-        sh7372_add_standard_devices();
-        platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
-        rmobile_add_devices_to_domains(domain_devices,
-                                       ARRAY_SIZE(domain_devices));
-        hdmi_init_pm_clock();
-        sh7372_pm_init();
-        pm_clk_add(&fsi_device.dev, "spu2");
-        pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
-}
-static const char *mackerel_boards_compat_dt[] __initdata = {
-        "renesas,mackerel",
-        NULL,
-};
-DT_MACHINE_START(MACKEREL_DT, "mackerel")
-        .map_io         = sh7372_map_io,
-        .init_early     = sh7372_add_early_devices,
-        .init_irq       = sh7372_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = mackerel_init,
-        .init_late      = sh7372_pm_init_late,
-        .init_time      = sh7372_earlytimer_init,
-        .dt_compat  = mackerel_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
deleted file mode 100644
index 1cf44dc6d718..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * r8a73a4 clock framework support
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include "common.h"
-#include "clock.h"
-#define CPG_BASE 0xe6150000
-#define CPG_LEN 0x270
-#define SMSTPCR2 0xe6150138
-#define SMSTPCR3 0xe615013c
-#define SMSTPCR4 0xe6150140
-#define SMSTPCR5 0xe6150144
-#define FRQCRA          0xE6150000
-#define FRQCRB          0xE6150004
-#define FRQCRC          0xE61500E0
-#define VCLKCR1         0xE6150008
-#define VCLKCR2         0xE615000C
-#define VCLKCR3         0xE615001C
-#define VCLKCR4         0xE6150014
-#define VCLKCR5         0xE6150034
-#define ZBCKCR          0xE6150010
-#define SD0CKCR         0xE6150074
-#define SD1CKCR         0xE6150078
-#define SD2CKCR         0xE615007C
-#define MMC0CKCR        0xE6150240
-#define MMC1CKCR        0xE6150244
-#define FSIACKCR        0xE6150018
-#define FSIBCKCR        0xE6150090
-#define MPCKCR          0xe6150080
-#define SPUVCKCR        0xE6150094
-#define HSICKCR         0xE615026C
-#define M4CKCR          0xE6150098
-#define PLLECR          0xE61500D0
-#define PLL0CR          0xE61500D8
-#define PLL1CR          0xE6150028
-#define PLL2CR          0xE615002C
-#define PLL2SCR         0xE61501F4
-#define PLL2HCR         0xE61501E4
-#define CKSCR           0xE61500C0
-#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
-static struct clk_mapping cpg_mapping = {
-        .phys   = CPG_BASE,
-        .len    = CPG_LEN,
-};
-static struct clk extalr_clk = {
-        .rate   = 32768,
-        .mapping        = &cpg_mapping,
-};
-static struct clk extal1_clk = {
-        .rate   = 26000000,
-        .mapping        = &cpg_mapping,
-};
-static struct clk extal2_clk = {
-        .rate   = 48000000,
-        .mapping        = &cpg_mapping,
-};
-static struct sh_clk_ops followparent_clk_ops = {
-        .recalc = followparent_recalc,
-};
-static struct clk main_clk = {
-        /* .parent will be set r8a73a4_clock_init */
-        .ops    = &followparent_clk_ops,
-};
-SH_CLK_RATIO(div2,      1, 2);
-SH_CLK_RATIO(div4,      1, 4);
-SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
-SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
-SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
-SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
-/* External FSIACK/FSIBCK clock */
-static struct clk fsiack_clk = {
-};
-static struct clk fsibck_clk = {
-};
-/*
- *              PLL clocks
- */
-static struct clk *pll_parent_main[] = {
-        [0] = &main_clk,
-        [1] = &main_div2_clk
-};
-static struct clk *pll_parent_main_extal[8] = {
-        [0] = &main_div2_clk,
-        [1] = &extal2_div2_clk,
-        [3] = &extal2_div4_clk,
-        [4] = &main_clk,
-        [5] = &extal2_clk,
-};
-static unsigned long pll_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
-                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
-        return clk->parent->rate * mult;
-}
-static int pll_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 val;
-        int i, ret;
-        if (!clk->parent_table || !clk->parent_num)
-                return -EINVAL;
-        /* Search the parent */
-        for (i = 0; i < clk->parent_num; i++)
-                if (clk->parent_table[i] == parent)
-                        break;
-        if (i == clk->parent_num)
-                return -ENODEV;
-        ret = clk_reparent(clk, parent);
-        if (ret < 0)
-                return ret;
-        val = ioread32(clk->mapped_reg) &
-                ~(((1 << clk->src_width) - 1) << clk->src_shift);
-        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
-        return 0;
-}
-static struct sh_clk_ops pll_clk_ops = {
-        .recalc         = pll_recalc,
-        .set_parent     = pll_set_parent,
-};
-#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
-        static struct clk name = {                      \
-                .ops            = &pll_clk_ops,         \
-                .flags          = CLK_ENABLE_ON_INIT,   \
-                .parent         = p,                    \
-                .parent_table   = pt,                   \
-                .parent_num     = ARRAY_SIZE(pt),       \
-                .src_width      = w,                    \
-                .src_shift      = s,                    \
-                .enable_reg     = (void __iomem *)reg,  \
-                .enable_bit     = e,                    \
-                .mapping        = &cpg_mapping,         \
-        }
-PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
-PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
-PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
-PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
-PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
-SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
-static atomic_t frqcr_lock;
-/* Several clocks need to access FRQCRB, have to lock */
-static bool frqcr_kick_check(struct clk *clk)
-{
-        return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
-}
-static int frqcr_kick_do(struct clk *clk)
-{
-        int i;
-        /* set KICK bit in FRQCRB to update hardware setting, check success */
-        iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
-        for (i = 1000; i; i--)
-                if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
-                        cpu_relax();
-                else
-                        return 0;
-        return -ETIMEDOUT;
-}
-static int zclk_set_rate(struct clk *clk, unsigned long rate)
-{
-        void __iomem *frqcrc;
-        int ret;
-        unsigned long step, p_rate;
-        u32 val;
-        if (!clk->parent || !__clk_get(clk->parent))
-                return -ENODEV;
-        if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
-                ret = -EBUSY;
-                goto done;
-        }
-        /*
-         * Users are supposed to first call clk_set_rate() only with
-         * clk_round_rate() results. So, we don't fix wrong rates here, but
-         * guard against them anyway
-         */
-        p_rate = clk_get_rate(clk->parent);
-        if (rate == p_rate) {
-                val = 0;
-        } else {
-                step = DIV_ROUND_CLOSEST(p_rate, 32);
-                if (rate > p_rate || rate < step) {
-                        ret = -EINVAL;
-                        goto done;
-                }
-                val = 32 - rate / step;
-        }
-        frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
-        iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
-                  (val << clk->enable_bit), frqcrc);
-        ret = frqcr_kick_do(clk);
-done:
-        atomic_dec(&frqcr_lock);
-        __clk_put(clk->parent);
-        return ret;
-}
-static long zclk_round_rate(struct clk *clk, unsigned long rate)
-{
-        /*
-         * theoretical rate = parent rate * multiplier / 32,
-         * where 1 <= multiplier <= 32. Therefore we should do
-         * multiplier = rate * 32 / parent rate
-         * rounded rate = parent rate * multiplier / 32.
-         * However, multiplication before division won't fit in 32 bits, so
-         * we sacrifice some precision by first dividing and then multiplying.
-         * To find the nearest divisor we calculate both and pick up the best
-         * one. This avoids 64-bit arithmetics.
-         */
-        unsigned long step, mul_min, mul_max, rate_min, rate_max;
-        rate_max = clk_get_rate(clk->parent);
-        /* output freq <= parent */
-        if (rate >= rate_max)
-                return rate_max;
-        step = DIV_ROUND_CLOSEST(rate_max, 32);
-        /* output freq >= parent / 32 */
-        if (step >= rate)
-                return step;
-        mul_min = rate / step;
-        mul_max = DIV_ROUND_UP(rate, step);
-        rate_min = step * mul_min;
-        if (mul_max == mul_min)
-                return rate_min;
-        rate_max = step * mul_max;
-        if (rate_max - rate <  rate - rate_min)
-                return rate_max;
-        return rate_min;
-}
-static unsigned long zclk_recalc(struct clk *clk)
-{
-        void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
-        unsigned int max = clk->div_mask + 1;
-        unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
-                             clk->div_mask);
-        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
-                (max - val);
-}
-static struct sh_clk_ops zclk_ops = {
-        .recalc = zclk_recalc,
-        .set_rate = zclk_set_rate,
-        .round_rate = zclk_round_rate,
-};
-static struct clk z_clk = {
-        .parent = &pll0_clk,
-        .div_mask = 0x1f,
-        .enable_bit = 8,
-        /* We'll need to access FRQCRB and FRQCRC */
-        .enable_reg = (void __iomem *)FRQCRB,
-        .ops = &zclk_ops,
-};
-/*
- * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
- * switching is only available in auto-DVFS mode
- */
-SH_FIXED_RATIO_CLK(pll0_div2_clk,       pll0_clk,               div2);
-static struct clk z2_clk = {
-        .parent = &pll0_div2_clk,
-        .div_mask = 0x1f,
-        .enable_bit = 0,
-        /* We'll need to access FRQCRB and FRQCRC */
-        .enable_reg = (void __iomem *)FRQCRB,
-        .ops = &zclk_ops,
-};
-static struct clk *main_clks[] = {
-        &extalr_clk,
-        &extal1_clk,
-        &extal1_div2_clk,
-        &extal2_clk,
-        &extal2_div2_clk,
-        &extal2_div4_clk,
-        &main_clk,
-        &main_div2_clk,
-        &fsiack_clk,
-        &fsibck_clk,
-        &pll0_clk,
-        &pll1_clk,
-        &pll1_div2_clk,
-        &pll2_clk,
-        &pll2s_clk,
-        &pll2h_clk,
-        &z_clk,
-        &pll0_div2_clk,
-        &z2_clk,
-};
-/* DIV4 */
-static void div4_kick(struct clk *clk)
-{
-        if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
-                frqcr_kick_do(clk);
-        atomic_dec(&frqcr_lock);
-}
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors       = divisors,
-        .nr_divisors    = ARRAY_SIZE(divisors),
-};
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick           = div4_kick,
-};
-enum {
-        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
-        DIV4_ZX, DIV4_ZS, DIV4_HP,
-        DIV4_NR };
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
-        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
-        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
-        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
-        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
-        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
-        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
-        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
-};
-enum {
-        DIV6_ZB,
-        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
-        DIV6_MMC0, DIV6_MMC1,
-        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
-        DIV6_FSIA, DIV6_FSIB,
-        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
-        DIV6_NR };
-static struct clk *div6_parents[8] = {
-        [0] = &pll1_div2_clk,
-        [1] = &pll2s_clk,
-        [3] = &extal2_clk,
-        [4] = &main_div2_clk,
-        [6] = &extalr_clk,
-};
-static struct clk *fsia_parents[4] = {
-        [0] = &pll1_div2_clk,
-        [1] = &pll2s_clk,
-        [2] = &fsiack_clk,
-};
-static struct clk *fsib_parents[4] = {
-        [0] = &pll1_div2_clk,
-        [1] = &pll2s_clk,
-        [2] = &fsibck_clk,
-};
-static struct clk *mp_parents[4] = {
-        [0] = &pll1_div2_clk,
-        [1] = &pll2s_clk,
-        [2] = &extal2_clk,
-        [3] = &extal2_clk,
-};
-static struct clk *m4_parents[2] = {
-        [0] = &pll2s_clk,
-};
-static struct clk *hsi_parents[4] = {
-        [0] = &pll2h_clk,
-        [1] = &pll1_div2_clk,
-        [3] = &pll2s_clk,
-};
-/*** FIXME ***
- * SH_CLK_DIV6_EXT() macro doesn't care .mapping
- * but, it is necessary on R-Car (= ioremap() base CPG)
- * The difference between
- * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
- * is only .mapping
- */
-#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
-                            _num_parents, _src_shift, _src_width)       \
-{                                                                       \
-        .enable_reg     = (void __iomem *)_reg,                         \
-        .enable_bit     = 0, /* unused */                               \
-        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
-        .div_mask       = SH_CLK_DIV6_MSK,                              \
-        .parent_table   = _parents,                                     \
-        .parent_num     = _num_parents,                                 \
-        .src_shift      = _src_shift,                                   \
-        .src_width      = _src_width,                                   \
-        .mapping        = &cpg_mapping,                                 \
-}
-static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
-                                div6_parents, 2, 7, 1),
-        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
-                                div6_parents, 2, 6, 2),
-        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
-                                div6_parents, 2, 6, 2),
-        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
-                                div6_parents, 2, 6, 2),
-        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
-                                div6_parents, 2, 6, 2),
-        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
-                                div6_parents, 2, 6, 2),
-        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
-                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
-        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
-                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
-        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
-                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
-        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
-                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
-        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
-                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
-        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
-                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
-        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
-                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
-        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
-                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
-        /* pll2s will be selected always for M4 */
-        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
-                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
-        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
-                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
-        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
-                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
-};
-/* MSTP */
-enum {
-        MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-        MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
-        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
-        MSTP411, MSTP410, MSTP409,
-        MSTP522, MSTP515,
-        MSTP_NR
-};
-static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
-        [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC */
-        [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 0, 0), /* IIC2 */
-        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
-        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
-        [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
-        [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
-        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
-        [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 16, 0), /* IIC6 */
-        [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 17, 0), /* IIC7 */
-        [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 18, 0), /* IIC0 */
-        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 23, 0), /* IIC1 */
-        [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
-        [MSTP409] = SH_CLK_MSTP32(&main_div2_clk,       SMSTPCR4, 9, 0), /* IIC5 */
-        [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 10, 0), /* IIC4 */
-        [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 11, 0), /* IIC3 */
-        [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
-        [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR5, 15, 0), /* IIC8 */
-};
-static struct clk_lookup lookups[] = {
-        /* main clock */
-        CLKDEV_CON_ID("extal1",                 &extal1_clk),
-        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
-        CLKDEV_CON_ID("extal2",                 &extal2_clk),
-        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
-        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
-        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
-        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
-        /* pll clock */
-        CLKDEV_CON_ID("pll1",                   &pll1_clk),
-        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
-        CLKDEV_CON_ID("pll2",                   &pll2_clk),
-        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
-        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
-        /* CPU clock */
-        CLKDEV_DEV_ID("cpu0",                   &z_clk),
-        /* DIV6 */
-        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
-        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
-        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
-        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
-        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
-        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
-        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
-        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
-        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
-        /* MSTP */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
-        CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
-        CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
-        CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
-        CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
-        CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
-        CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
-        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
-        CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
-        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
-        CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
-        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
-        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
-        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
-        CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
-        CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
-        CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
-        CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
-        CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]),
-        CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
-        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
-        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
-        CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
-        /* for DT */
-        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
-};
-void __init r8a73a4_clock_init(void)
-{
-        void __iomem *reg;
-        int k, ret = 0;
-        u32 ckscr;
-        atomic_set(&frqcr_lock, -1);
-        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
-        BUG_ON(!reg);
-        ckscr = ioread32(reg);
-        iounmap(reg);
-        switch ((ckscr >> 28) & 0x3) {
-        case 0:
-                main_clk.parent = &extal1_clk;
-                break;
-        case 1:
-                main_clk.parent = &extal1_div2_clk;
-                break;
-        case 2:
-                main_clk.parent = &extal2_clk;
-                break;
-        case 3:
-                main_clk.parent = &extal2_div2_clk;
-                break;
-        }
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-        if (!ret)
-                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup r8a73a4 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
deleted file mode 100644
index 3bc92f46060e..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * SH7372 clock framework support
- *
- * Copyright (C) 2010 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include "clock.h"
-#include "common.h"
-/* SH7372 registers */
-#define FRQCRA          IOMEM(0xe6150000)
-#define FRQCRB          IOMEM(0xe6150004)
-#define FRQCRC          IOMEM(0xe61500e0)
-#define FRQCRD          IOMEM(0xe61500e4)
-#define VCLKCR1         IOMEM(0xe6150008)
-#define VCLKCR2         IOMEM(0xe615000c)
-#define VCLKCR3         IOMEM(0xe615001c)
-#define FMSICKCR        IOMEM(0xe6150010)
-#define FMSOCKCR        IOMEM(0xe6150014)
-#define FSIACKCR        IOMEM(0xe6150018)
-#define FSIBCKCR        IOMEM(0xe6150090)
-#define SUBCKCR         IOMEM(0xe6150080)
-#define SPUCKCR         IOMEM(0xe6150084)
-#define VOUCKCR         IOMEM(0xe6150088)
-#define HDMICKCR        IOMEM(0xe6150094)
-#define DSITCKCR        IOMEM(0xe6150060)
-#define DSI0PCKCR       IOMEM(0xe6150064)
-#define DSI1PCKCR       IOMEM(0xe6150098)
-#define PLLC01CR        IOMEM(0xe6150028)
-#define PLLC2CR         IOMEM(0xe615002c)
-#define RMSTPCR0        IOMEM(0xe6150110)
-#define RMSTPCR1        IOMEM(0xe6150114)
-#define RMSTPCR2        IOMEM(0xe6150118)
-#define RMSTPCR3        IOMEM(0xe615011c)
-#define RMSTPCR4        IOMEM(0xe6150120)
-#define SMSTPCR0        IOMEM(0xe6150130)
-#define SMSTPCR1        IOMEM(0xe6150134)
-#define SMSTPCR2        IOMEM(0xe6150138)
-#define SMSTPCR3        IOMEM(0xe615013c)
-#define SMSTPCR4        IOMEM(0xe6150140)
-#define FSIDIVA         0xFE1F8000
-#define FSIDIVB         0xFE1F8008
-/* Platforms must set frequency on their DV_CLKI pin */
-struct clk sh7372_dv_clki_clk = {
-};
-/* Fixed 32 KHz root clock from EXTALR pin */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-/*
- * 26MHz default rate for the EXTAL1 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7372_extal1_clk = {
-        .rate           = 26000000,
-};
-/*
- * 48MHz default rate for the EXTAL2 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7372_extal2_clk = {
-        .rate           = 48000000,
-};
-SH_CLK_RATIO(div2, 1, 2);
-SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk,    sh7372_dv_clki_clk,     div2);
-SH_FIXED_RATIO_CLK(extal1_div2_clk,             sh7372_extal1_clk,      div2);
-SH_FIXED_RATIO_CLK(extal2_div2_clk,             sh7372_extal2_clk,      div2);
-SH_FIXED_RATIO_CLK(extal2_div4_clk,             extal2_div2_clk,        div2);
-/* PLLC0 and PLLC1 */
-static unsigned long pllc01_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (__raw_readl(PLLC01CR) & (1 << 14))
-                mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static struct sh_clk_ops pllc01_clk_ops = {
-        .recalc         = pllc01_recalc,
-};
-static struct clk pllc0_clk = {
-        .ops            = &pllc01_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extal1_div2_clk,
-        .enable_reg     = (void __iomem *)FRQCRC,
-};
-static struct clk pllc1_clk = {
-        .ops            = &pllc01_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extal1_div2_clk,
-        .enable_reg     = (void __iomem *)FRQCRA,
-};
-/* Divide PLLC1 by two */
-SH_FIXED_RATIO_CLK(pllc1_div2_clk,      pllc1_clk,      div2);
-/* PLLC2 */
-/* Indices are important - they are the actual src selecting values */
-static struct clk *pllc2_parent[] = {
-        [0] = &extal1_div2_clk,
-        [1] = &extal2_div2_clk,
-        [2] = &sh7372_dv_clki_div2_clk,
-};
-/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
-static struct cpufreq_frequency_table pllc2_freq_table[29];
-static void pllc2_table_rebuild(struct clk *clk)
-{
-        int i;
-        /* Initialise PLLC2 frequency table */
-        for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
-                pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
-                pllc2_freq_table[i].driver_data = i;
-        }
-        /* This is a special entry - switching PLL off makes it a repeater */
-        pllc2_freq_table[i].frequency = clk->parent->rate;
-        pllc2_freq_table[i].driver_data = i;
-        pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
-        pllc2_freq_table[i].driver_data = i;
-}
-static unsigned long pllc2_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        pllc2_table_rebuild(clk);
-        /*
-         * If the PLL is off, mult == 1, clk->rate will be updated in
-         * pllc2_enable().
-         */
-        if (__raw_readl(PLLC2CR) & (1 << 31))
-                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static long pllc2_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_rate_table_round(clk, clk->freq_table, rate);
-}
-static int pllc2_enable(struct clk *clk)
-{
-        int i;
-        __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
-        for (i = 0; i < 100; i++)
-                if (__raw_readl(PLLC2CR) & 0x80000000) {
-                        clk->rate = pllc2_recalc(clk);
-                        return 0;
-                }
-        pr_err("%s(): timeout!\n", __func__);
-        return -ETIMEDOUT;
-}
-static void pllc2_disable(struct clk *clk)
-{
-        __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
-}
-static int pllc2_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long value;
-        int idx;
-        idx = clk_rate_table_find(clk, clk->freq_table, rate);
-        if (idx < 0)
-                return idx;
-        if (rate == clk->parent->rate)
-                return -EINVAL;
-        value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
-        __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
-        clk->rate = clk->freq_table[idx].frequency;
-        return 0;
-}
-static int pllc2_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 value;
-        int ret, i;
-        if (!clk->parent_table || !clk->parent_num)
-                return -EINVAL;
-        /* Search the parent */
-        for (i = 0; i < clk->parent_num; i++)
-                if (clk->parent_table[i] == parent)
-                        break;
-        if (i == clk->parent_num)
-                return -ENODEV;
-        ret = clk_reparent(clk, parent);
-        if (ret < 0)
-                return ret;
-        value = __raw_readl(PLLC2CR) & ~(3 << 6);
-        __raw_writel(value | (i << 6), PLLC2CR);
-        /* Rebiuld the frequency table */
-        pllc2_table_rebuild(clk);
-        return 0;
-}
-static struct sh_clk_ops pllc2_clk_ops = {
-        .recalc         = pllc2_recalc,
-        .round_rate     = pllc2_round_rate,
-        .set_rate       = pllc2_set_rate,
-        .enable         = pllc2_enable,
-        .disable        = pllc2_disable,
-        .set_parent     = pllc2_set_parent,
-};
-struct clk sh7372_pllc2_clk = {
-        .ops            = &pllc2_clk_ops,
-        .parent         = &extal1_div2_clk,
-        .freq_table     = pllc2_freq_table,
-        .nr_freqs       = ARRAY_SIZE(pllc2_freq_table) - 1,
-        .parent_table   = pllc2_parent,
-        .parent_num     = ARRAY_SIZE(pllc2_parent),
-};
-/* External input clock (pin name: FSIACK/FSIBCK ) */
-static struct clk fsiack_clk = {
-};
-static struct clk fsibck_clk = {
-};
-static struct clk *main_clks[] = {
-        &sh7372_dv_clki_clk,
-        &r_clk,
-        &sh7372_extal1_clk,
-        &sh7372_extal2_clk,
-        &sh7372_dv_clki_div2_clk,
-        &extal1_div2_clk,
-        &extal2_div2_clk,
-        &extal2_div4_clk,
-        &pllc0_clk,
-        &pllc1_clk,
-        &pllc1_div2_clk,
-        &sh7372_pllc2_clk,
-        &fsiack_clk,
-        &fsibck_clk,
-};
-static void div4_kick(struct clk *clk)
-{
-        unsigned long value;
-        /* set KICK bit in FRQCRB to update hardware setting */
-        value = __raw_readl(FRQCRB);
-        value |= (1 << 31);
-        __raw_writel(value, FRQCRB);
-}
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
-                          24, 32, 36, 48, 0, 72, 96, 0 };
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick = div4_kick,
-};
-enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
-       DIV4_ZX, DIV4_HP,
-       DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
-       DIV4_DDRP, DIV4_NR };
-#define DIV4(_reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
-        [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
-        [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
-        [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
-        [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
-        [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
-        [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
-        [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
-        [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
-};
-enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
-       DIV6_SUB, DIV6_SPU,
-       DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
-       DIV6_NR };
-static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
-        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
-        [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
-        [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
-        [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
-        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
-        [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
-        [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
-        [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
-        [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
-};
-enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
-/* Indices are important - they are the actual src selecting values */
-static struct clk *hdmi_parent[] = {
-        [0] = &pllc1_div2_clk,
-        [1] = &sh7372_pllc2_clk,
-        [2] = &sh7372_dv_clki_clk,
-        [3] = NULL,     /* pllc2_div4 not implemented yet */
-};
-static struct clk *fsiackcr_parent[] = {
-        [0] = &pllc1_div2_clk,
-        [1] = &sh7372_pllc2_clk,
-        [2] = &fsiack_clk, /* external input for FSI A */
-        [3] = NULL,     /* setting prohibited */
-};
-static struct clk *fsibckcr_parent[] = {
-        [0] = &pllc1_div2_clk,
-        [1] = &sh7372_pllc2_clk,
-        [2] = &fsibck_clk, /* external input for FSI B */
-        [3] = NULL,     /* setting prohibited */
-};
-static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
-        [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
-                                      hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
-        [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
-                                      fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
-        [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
-                                      fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
-};
-/* FSI DIV */
-enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
-static struct clk fsidivs[] = {
-        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
-        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
-};
-enum { MSTP001, MSTP000,
-       MSTP131, MSTP130,
-       MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
-       MSTP118, MSTP117, MSTP116, MSTP113,
-       MSTP106, MSTP101, MSTP100,
-       MSTP223,
-       MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
-       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
-       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
-       MSTP405, MSTP404, MSTP403, MSTP400,
-       MSTP_NR };
-#define MSTP(_parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
-static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
-        [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
-        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
-        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
-        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
-        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
-        [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
-        [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
-        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
-        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
-        [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
-        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
-        [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
-        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
-        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
-        [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
-        [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
-        [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
-        [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
-        [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
-        [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
-        [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
-        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
-        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
-        [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
-        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
-        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
-        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
-        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
-        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
-        [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
-        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
-        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
-        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
-        [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
-        [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
-        [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
-        [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
-        [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
-        [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
-        [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
-        [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
-        [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
-        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
-        [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
-};
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
-        CLKDEV_CON_ID("r_clk", &r_clk),
-        CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
-        CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
-        CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
-        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
-        CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
-        CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
-        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
-        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
-        CLKDEV_CON_ID("fsiack", &fsiack_clk),
-        CLKDEV_CON_ID("fsibck", &fsibck_clk),
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
-        CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
-        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
-        CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
-        CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
-        CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
-        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
-        CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
-        CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
-        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
-        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
-        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
-        CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
-        /* DIV6 clocks */
-        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
-        CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
-        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
-        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
-        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
-        CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
-        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
-        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
-        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
-        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
-        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
-        CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
-        CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
-        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
-        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
-        CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
-        CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
-        CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
-        CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
-        CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
-        CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
-        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
-        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
-        CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
-        CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
-        CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
-        CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
-        CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
-        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
-        CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
-        CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
-        CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
-        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
-        CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
-        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
-        /* ICK */
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
-        CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
-                      &div6_reparent_clks[DIV6_HDMI]),
-        CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
-        CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
-        CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
-        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
-        CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
-        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.4", &mstp_clks[MSTP405]), /* CMT4 */
-        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.3", &mstp_clks[MSTP404]), /* CMT3 */
-        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.2", &mstp_clks[MSTP400]), /* CMT2 */
-        CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
-        CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
-        CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
-        CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
-};
-void __init sh7372_clock_init(void)
-{
-        int k, ret = 0;
-        /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
-        __raw_writel(0xe4ef8087, RMSTPCR0);
-        __raw_writel(0xffffffff, RMSTPCR1);
-        __raw_writel(0x37c7f7ff, RMSTPCR2);
-        __raw_writel(0xffffffff, RMSTPCR3);
-        __raw_writel(0xffe0fffd, RMSTPCR4);
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-        if (!ret)
-                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        if (!ret)
-                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup sh7372 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 34f056fc3756..68c2d06d0eaa 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -45,14 +45,3 @@ int __init shmobile_clk_init(void)
        return 0;
 }
-int __clk_get(struct clk *clk)
-{
-        return 1;
-}
-EXPORT_SYMBOL(__clk_get);
-void __clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(__clk_put);
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 309025efd4cf..afc60bad6fd6 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -21,10 +21,7 @@ extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
 extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
 struct clk;
 extern int shmobile_clk_init(void);
-extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
-struct cpuidle_driver;
-extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 #ifdef CONFIG_SUSPEND
 int shmobile_suspend_init(void);
@@ -34,12 +31,6 @@ static inline int shmobile_suspend_init(void) { return 0; }
 static inline void shmobile_smp_apmu_suspend_init(void) { }
 #endif
-#ifdef CONFIG_CPU_IDLE
-int shmobile_cpuidle_init(void);
-#else
-static inline int shmobile_cpuidle_init(void) { return 0; }
-#endif
 #ifdef CONFIG_CPU_FREQ
 int shmobile_cpufreq_init(void);
 #else
@@ -51,7 +42,6 @@ extern void __iomem *shmobile_scu_base;
 static inline void __init shmobile_init_late(void)
 {
        shmobile_suspend_init();
-        shmobile_cpuidle_init();
        shmobile_cpufreq_init();
 }
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
deleted file mode 100644
index 0afeb5c7061c..000000000000
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * CPUIdle support code for SH-Mobile ARM
- *
- *  Copyright (C) 2011 Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/pm.h>
-#include <linux/cpuidle.h>
-#include <linux/suspend.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <asm/cpuidle.h>
-#include <asm/io.h>
-static struct cpuidle_driver shmobile_cpuidle_default_driver = {
-        .name                   = "shmobile_cpuidle",
-        .owner                  = THIS_MODULE,
-        .states[0]              = ARM_CPUIDLE_WFI_STATE,
-        .safe_state_index       = 0, /* C1 */
-        .state_count            = 1,
-};
-static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver;
-void __init shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
-{
-        cpuidle_drv = drv;
-}
-int __init shmobile_cpuidle_init(void)
-{
-        return cpuidle_register(cpuidle_drv, NULL);
-}
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
deleted file mode 100644
index 1a1c00ca39a2..000000000000
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * ARM Interrupt demux handler using INTC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/entry-macro-multi.S>
-#define INTCA_BASE      0xe6980000
-#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
-#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
-#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
-#define INTLVLB_OFFS    0x00000034 /* previous priority level */
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =INTCA_BASE
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        /* The single INTFLGA read access below results in the following:
-         *
-         * 1. INTLVLB is updated with old priority value from INTLVLA
-         * 2. Highest priority interrupt is accepted
-         * 3. INTLVLA is updated to contain priority of accepted interrupt
-         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
-         */
-        ldr     \irqnr, [\base, #INTFLGA_OFFS]
-        /* Restore INTLVLA with the value saved in INTLVLB.
-         * This is required to support interrupt priorities properly.
-         */
-        ldrb    \tmp, [\base, #INTLVLB_OFFS]
-        strb    \tmp, [\base, #INTLVLA_OFFS]
-        /* Handle invalid vector number case */
-        cmp     \irqnr, #0
-        beq     1000f
-        /* Convert vector to irq number, same as the evt2irq() macro */
-        lsr     \irqnr, \irqnr, #0x5
-        subs    \irqnr, \irqnr, #16
-1000:
-        .endm
-        .macro  test_for_ipi, irqnr, irqstat, base, tmp
-        .endm
-        arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h
deleted file mode 100644
index 36d0163a857a..000000000000
--- a/arch/arm/mach-shmobile/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
deleted file mode 100644
index 9f134dfeffdc..000000000000
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-LIST "partner-jet-setup.txt"
-LIST "(C) Copyright 2010 Renesas Solutions Corp"
-LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
-LIST "RWT Setting"
-EW 0xE6020004, 0xA500
-EW 0xE6030004, 0xA500
-LIST "GPIO Setting"
-EB 0xE6051013, 0xA2
-LIST "CPG"
-ED 0xE61500C0, 0x00000002
-WAIT 1, 0xFE40009C
-LIST "FRQCR"
-ED 0xE6150000, 0x2D1305C3
-ED 0xE61500E0, 0x9E40358E
-ED 0xE6150004, 0x80331050
-WAIT 1, 0xFE40009C
-ED 0xE61500E4, 0x00002000
-WAIT 1, 0xFE40009C
-LIST "PLL"
-ED 0xE6150028, 0x00004000
-WAIT 1, 0xFE40009C
-ED 0xE615002C, 0x93000040
-WAIT 1, 0xFE40009C
-LIST "SUB/USBClk"
-ED 0xE6150080, 0x00000180
-LIST "BSC"
-ED 0xFEC10000, 0x00E0001B
-LIST "SBSC1"
-ED 0xFE400354, 0x01AD8000
-ED 0xFE400354, 0x01AD8001
-WAIT 5, 0xFE40009C
-ED 0xFE400008, 0xBCC90151
-ED 0xFE400040, 0x41774113
-ED 0xFE400044, 0x2712E229
-ED 0xFE400048, 0x20C18505
-ED 0xFE40004C, 0x00110209
-ED 0xFE400010, 0x00000087
-WAIT 30, 0xFE40009C
-ED 0xFE400084, 0x0000003F
-EB 0xFE500000, 0x00
-WAIT 5, 0xFE40009C
-ED 0xFE400084, 0x0000FF0A
-EB 0xFE500000, 0x00
-WAIT 1, 0xFE40009C
-ED 0xFE400084, 0x00002201
-EB 0xFE500000, 0x00
-ED 0xFE400084, 0x00000302
-EB 0xFE500000, 0x00
-EB 0xFE5C0000, 0x00
-ED 0xFE400008, 0xBCC90159
-ED 0xFE40008C, 0x88800004
-ED 0xFE400094, 0x00000004
-ED 0xFE400028, 0xA55A0032
-ED 0xFE40002C, 0xA55A000C
-ED 0xFE400020, 0xA55A2048
-ED 0xFE400008, 0xBCC90959
-LIST "Change CPGA setting"
-ED 0xE61500E0, 0x9E40352E
-ED 0xE6150004, 0x80331050
-WAIT 1, 0xFE40009C
-ED 0xFE400354, 0x01AD8002
-LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0xe1
-EW 0xE6C40000, 0x0000
-EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h
deleted file mode 100644
index 15d3a9efdec2..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef MMC_MACKEREL_H
-#define MMC_MACKEREL_H
-#define PORT0CR      (void __iomem *)0xe6051000
-#define PORT1CR      (void __iomem *)0xe6051001
-#define PORT2CR      (void __iomem *)0xe6051002
-#define PORT159CR    (void __iomem *)0xe605009f
-#define PORTR031_000DR (void __iomem *)0xe6055000
-#define PORTL159_128DR (void __iomem *)0xe6054010
-static inline void mmc_init_progress(void)
-{
-       /* Initialise LEDS0-3
-        * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control)
-        * value:     0x10 - enable output
-        */
-       __raw_writeb(0x10, PORT0CR);
-       __raw_writeb(0x10, PORT1CR);
-       __raw_writeb(0x10, PORT2CR);
-       __raw_writeb(0x10, PORT159CR);
-}
-static inline void mmc_update_progress(int n)
-{
-        unsigned a = 0, b = 0;
-        if (n < 3)
-                a = 1 << n;
-        else
-                b = 1 << 31;
-        __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a,
-                     PORTR031_000DR);
-        __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b,
-                     PORTL159_128DR);
-}
-#endif /* MMC_MACKEREL_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
deleted file mode 100644
index e979b8fc1da2..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef MMC_H
-#define MMC_H
-/**************************************************
- *
- *              board specific settings
- *
- **************************************************/
-#ifdef CONFIG_MACH_MACKEREL
-#include "mach/mmc-mackerel.h"
-#else
-#error "unsupported board."
-#endif
-#endif /* MMC_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h b/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h
deleted file mode 100644
index 4a81b01f1e8f..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef SDHI_SH7372_H
-#define SDHI_SH7372_H
-#define SDGENCNTA       0xfe40009c
-/* The countdown of SDGENCNTA is controlled by
- * ZB3D2CLK which runs at 149.5MHz.
- * That is 149.5ticks/us. Approximate this as 150ticks/us.
- */
-static void udelay(int us)
-{
-        __raw_writel(us * 150, SDGENCNTA);
-        while(__raw_readl(SDGENCNTA)) ;
-}
-static void msleep(int ms)
-{
-        udelay(ms * 1000);
-}
-#endif
diff --git a/arch/arm/mach-shmobile/include/mach/sdhi.h b/arch/arm/mach-shmobile/include/mach/sdhi.h
deleted file mode 100644
index 0ec9e69f2c3b..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sdhi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef SDHI_H
-#define SDHI_H
-/**************************************************
- *
- *              CPU specific settings
- *
- **************************************************/
-#ifdef CONFIG_ARCH_SH7372
-#include "mach/sdhi-sh7372.h"
-#else
-#error "unsupported CPU."
-#endif
-#endif /* SDHI_H */
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
deleted file mode 100644
index 540eaff08f34..000000000000
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-#include <asm/system_misc.h>
-static inline void arch_reset(char mode, const char *cmd)
-{
-        soft_restart(0);
-}
-#endif
diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h
deleted file mode 100644
index f1aee56781e7..000000000000
--- a/arch/arm/mach-shmobile/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __ASM_MACH_UNCOMPRESS_H
-#define __ASM_MACH_UNCOMPRESS_H
-/*
- * This does not append a newline
- */
-static void putc(int c)
-{
-}
-static inline void flush(void)
-{
-}
-static void arch_decomp_setup(void)
-{
-}
-#endif /* __ASM_MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 727cc78ac8ec..175ee05465da 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -9,10 +9,7 @@
 *
 **************************************************/
-#ifdef CONFIG_MACH_MACKEREL
+#ifdef CONFIG_MACH_KZM9G
-#define MEMORY_START    0x40000000
-#include "mach/head-mackerel.txt"
-#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
 #define MEMORY_START    0x43000000
 #include "mach/head-kzm9g.txt"
 #else
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
deleted file mode 100644
index 1ccf49cb485f..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * sh7372 processor support - INTC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "intc.h"
-#include "irqs.h"
-enum {
-        UNUSED_INTCA = 0,
-        /* interrupt sources INTCA */
-        DIRC,
-        CRYPT_STD,
-        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
-        AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
-        MFI_MFIM, MFI_MFIS,
-        BBIF1, BBIF2,
-        USBHSDMAC0_USHDMI,
-        _3DG_SGX540,
-        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
-        KEYSC_KEY,
-        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
-        MSIOF2, MSIOF1,
-        SCIFA4, SCIFA5, SCIFB,
-        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
-        SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
-        IRREM,
-        IRDA,
-        TPU0,
-        TTI20,
-        DDM,
-        SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
-        RWDT0,
-        DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
-        DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
-        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
-        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
-        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
-        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
-        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
-        HDMI,
-        SPU2_SPU0, SPU2_SPU1,
-        FSI, FMSI,
-        MIPI_HSI,
-        IPMMU_IPMMUD,
-        CEC_1, CEC_2,
-        AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
-        MFIS2,
-        CPORTR2S,
-        CMT14, CMT15,
-        MMC_MMC_ERR, MMC_MMC_NOR,
-        IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
-        IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
-        USB0_USB0I1, USB0_USB0I0,
-        USB1_USB1I1, USB1_USB1I0,
-        USBHSDMAC1_USHDMI,
-        /* interrupt groups INTCA */
-        DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
-        AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
-};
-static struct intc_vect intca_vectors[] __initdata = {
-        INTC_VECT(DIRC, 0x0560),
-        INTC_VECT(CRYPT_STD, 0x0700),
-        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
-        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
-        INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
-        INTC_VECT(AP_ARM_COMMRX, 0x0860),
-        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
-        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
-        INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
-        INTC_VECT(_3DG_SGX540, 0x0a60),
-        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
-        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
-        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
-        INTC_VECT(KEYSC_KEY, 0x0be0),
-        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
-        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
-        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
-        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
-        INTC_VECT(SCIFB, 0x0d60),
-        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
-        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
-        INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
-        INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
-        INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
-        INTC_VECT(IRREM, 0x0f60),
-        INTC_VECT(IRDA, 0x0480),
-        INTC_VECT(TPU0, 0x04a0),
-        INTC_VECT(TTI20, 0x1100),
-        INTC_VECT(DDM, 0x1140),
-        INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
-        INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
-        INTC_VECT(RWDT0, 0x1280),
-        INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
-        INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
-        INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
-        INTC_VECT(DMAC1_2_DADERR, 0x20c0),
-        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
-        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
-        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
-        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
-        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
-        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
-        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
-        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
-        INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
-        INTC_VECT(SHWYSTAT_COM, 0x1340),
-        INTC_VECT(HDMI, 0x17e0),
-        INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
-        INTC_VECT(FSI, 0x1840),
-        INTC_VECT(FMSI, 0x1860),
-        INTC_VECT(MIPI_HSI, 0x18e0),
-        INTC_VECT(IPMMU_IPMMUD, 0x1920),
-        INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
-        INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
-        INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
-        INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
-        INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
-        INTC_VECT(MFIS2, 0x1a00),
-        INTC_VECT(CPORTR2S, 0x1a20),
-        INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
-        INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
-        INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
-        INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
-        INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
-        INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
-        INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
-        INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
-        INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
-};
-static struct intc_group intca_groups[] __initdata = {
-        INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
-                   DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
-        INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
-                   DMAC1_2_DEI5, DMAC1_2_DADERR),
-        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
-                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
-        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
-                   DMAC2_2_DEI5, DMAC2_2_DADERR),
-        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
-                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
-        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
-                   DMAC3_2_DEI5, DMAC3_2_DADERR),
-        INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
-        INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
-                   AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
-        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
-        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
-                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
-        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
-        INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
-                   SDHI0_SDHI0I2, SDHI0_SDHI0I3),
-        INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
-                   SDHI1_SDHI1I2),
-        INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
-                   SDHI2_SDHI2I2, SDHI2_SDHI2I3),
-        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
-};
-static struct intc_mask_reg intca_mask_registers[] __initdata = {
-        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
-          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
-            AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
-        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
-          { 0, CRYPT_STD, DIRC, 0,
-            DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
-        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
-          { 0, 0, 0, 0,
-            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
-        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
-          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
-            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
-        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
-          { DDM, 0, 0, 0,
-            0, 0, 0, 0 } },
-        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
-          { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
-            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
-        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
-          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
-            0, 0, MSIOF2, 0 } },
-        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
-            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
-        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
-            TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
-        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
-          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
-            CMT2, 0, 0, _3DG_SGX540 } },
-        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
-          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
-            0, 0, 0, 0 } },
-        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
-          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
-            0, 0, IRREM, 0 } },
-        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
-          { 0, 0, TPU0, 0,
-            0, 0, 0, 0 } },
-        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
-            0, CMT3, 0, RWDT0 } },
-        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
-          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
-            0, 0, 0, 0 } },
-        { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
-          { 0, 0, 0, 0,
-            0, 0, 0, HDMI } },
-        { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
-          { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
-            0, 0, 0, MIPI_HSI } },
-        { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
-          { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
-            AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
-            AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
-        { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
-          { MFIS2, CPORTR2S, CMT14, CMT15,
-            0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
-        { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
-          { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
-            IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
-        { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
-          { 0, 0, 0, 0,
-            USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
-        { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
-          { USBHSDMAC1_USHDMI, 0, 0, 0,
-            0, 0, 0, 0 } },
-};
-static struct intc_prio_reg intca_prio_registers[] __initdata = {
-        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
-        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
-        { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
-                                              CMT1_CMT11, AP_ARM1 } },
-        { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
-                                              CMT1_CMT12, 0 } },
-        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
-                                              MFI_MFIM, 0 } },
-        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
-                                              _3DG_SGX540, CMT1_CMT10 } },
-        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
-                                              SCIFA2, SCIFA3 } },
-        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
-                                              FLCTL, SDHI0 } },
-        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
-                                              0/* MSU */, IIC1 } },
-        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
-                                              0/* MSUG */, TTI20 } },
-        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
-        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
-        { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
-        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
-        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
-        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
-        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
-        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
-        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
-        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
-                                               CEC_1, CEC_2 } },
-        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
-        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
-                                               CMT14, CMT15 } },
-        { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
-                                               MMC_MMC_ERR, MMC_MMC_NOR } },
-        { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
-                                               IIC4_WAITI4, IIC4_DTEI4 } },
-        { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
-                                               IIC3_WAITI3, IIC3_DTEI3 } },
-        { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
-                                               0/*TXI*/, 0/*TEI*/} },
-        { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
-                                               USB1_USB1I1, USB1_USB1I0 } },
-        { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
-};
-static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
-                         intca_vectors, intca_groups,
-                         intca_mask_registers, intca_prio_registers,
-                         NULL);
-INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
-                 INTC_VECT, "sh7372-intca-irq-lo");
-INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
-                 INTC_VECT, "sh7372-intca-irq-hi");
-enum {
-        UNUSED_INTCS = 0,
-        ENABLED_INTCS,
-        /* interrupt sources INTCS */
-        /* IRQ0S - IRQ31S */
-        VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
-        RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
-        CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
-        /* MFI */
-        /* BBIF2 */
-        VPU,
-        TSIF1,
-        /* 3DG */
-        _2DDMAC,
-        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
-        IPMMU_IPMMUR, IPMMU_IPMMUR2,
-        RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
-        /* KEYSC */
-        /* TTI20 */
-        MSIOF,
-        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
-        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
-        CMT0,
-        TSIF0,
-        /* CMT2 */
-        LMB,
-        CTI,
-        /* RWDT0 */
-        ICB,
-        JPU_JPEG,
-        LCDC,
-        LCRC,
-        RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
-        RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
-        ISP,
-        LCDC1,
-        CSIRX,
-        DSITX_DSITX0,
-        DSITX_DSITX1,
-        /* SPU2 */
-        /* FSI */
-        /* FMSI */
-        /* HDMI */
-        TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
-        CMT4,
-        DSITX1_DSITX1_0,
-        DSITX1_DSITX1_1,
-        MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
-        CPORTS2R,
-        /* CEC */
-        JPU6E,
-        /* interrupt groups INTCS */
-        RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
-        RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
-};
-static struct intc_vect intcs_vectors[] = {
-        /* IRQ0S - IRQ31S */
-        INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
-        INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
-        INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
-        INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
-        INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
-        INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
-        /* MFI */
-        /* BBIF2 */
-        INTCS_VECT(VPU, 0x980),
-        INTCS_VECT(TSIF1, 0x9a0),
-        /* 3DG */
-        INTCS_VECT(_2DDMAC, 0xa00),
-        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
-        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
-        INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
-        INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
-        INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
-        /* KEYSC */
-        /* TTI20 */
-        INTCS_VECT(MSIOF, 0x0d20),
-        INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
-        INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
-        INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
-        INTCS_VECT(TMU_TUNI2, 0xec0),
-        INTCS_VECT(CMT0, 0xf00),
-        INTCS_VECT(TSIF0, 0xf20),
-        /* CMT2 */
-        INTCS_VECT(LMB, 0xf60),
-        INTCS_VECT(CTI, 0x400),
-        /* RWDT0 */
-        INTCS_VECT(ICB, 0x480),
-        INTCS_VECT(JPU_JPEG, 0x560),
-        INTCS_VECT(LCDC, 0x580),
-        INTCS_VECT(LCRC, 0x5a0),
-        INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
-        INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
-        INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
-        INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
-        INTCS_VECT(ISP, 0x1720),
-        INTCS_VECT(LCDC1, 0x1780),
-        INTCS_VECT(CSIRX, 0x17a0),
-        INTCS_VECT(DSITX_DSITX0, 0x17c0),
-        INTCS_VECT(DSITX_DSITX1, 0x17e0),
-        /* SPU2 */
-        /* FSI */
-        /* FMSI */
-        /* HDMI */
-        INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
-        INTCS_VECT(TMU1_TUNI2, 0x1940),
-        INTCS_VECT(CMT4, 0x1980),
-        INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
-        INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
-        INTCS_VECT(MFIS2_INTCS, 0x1a00),
-        INTCS_VECT(CPORTS2R, 0x1a20),
-        /* CEC */
-        INTCS_VECT(JPU6E, 0x1a80),
-};
-static struct intc_group intcs_groups[] __initdata = {
-        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
-                   RTDMAC_1_DEI2, RTDMAC_1_DEI3),
-        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
-        INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
-        INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
-        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
-        INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
-        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
-        INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
-                   RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
-        INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
-                   RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
-        INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
-        INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
-};
-static struct intc_mask_reg intcs_mask_registers[] = {
-        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
-          { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
-            VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
-        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
-          { 0, 0, 0, VPU,
-            0, 0, 0, 0 } },
-        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
-          { 0, 0, 0, _2DDMAC,
-            0, 0, 0, ICB } },
-        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
-          { 0, 0, 0, CTI,
-            JPU_JPEG, 0, LCRC, LCDC } },
-        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
-          { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
-            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
-        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
-          { 0, 0, MSIOF, 0,
-            0, 0, 0, 0 } },
-        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
-          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
-            0, 0, 0, 0 } },
-        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
-          { 0, 0, 0, CMT0,
-            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
-        { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
-          { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
-            0, 0, 0, 0 } },
-        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
-          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
-            0, TSIF1, LMB, TSIF0 } },
-        { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
-          { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
-            RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
-        { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
-          { 0, ISP, 0, 0,
-            LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
-        { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
-          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
-        { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
-          { MFIS2_INTCS, CPORTS2R, 0, 0,
-            JPU6E, 0, 0, 0 } },
-};
-/* Priority is needed for INTCA to receive the INTCS interrupt */
-static struct intc_prio_reg intcs_prio_registers[] = {
-        { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
-        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
-        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
-        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
-        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
-                                              TMU_TUNI2, TSIF1 } },
-        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
-        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
-        { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
-        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
-        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
-        { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
-        { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
-        { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
-        { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
-        { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
-        { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
-                                               DSITX1_DSITX1_1, 0 } },
-        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
-                                               0, 0 } },
-        { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
-};
-static struct resource intcs_resources[] __initdata = {
-        [0] = {
-                .start  = 0xffd20000,
-                .end    = 0xffd201ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xffd50000,
-                .end    = 0xffd501ff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct intc_desc intcs_desc __initdata = {
-        .name = "sh7372-intcs",
-        .force_enable = ENABLED_INTCS,
-        .skip_syscore_suspend = true,
-        .resource = intcs_resources,
-        .num_resources = ARRAY_SIZE(intcs_resources),
-        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
-                           intcs_prio_registers, NULL, NULL),
-};
-static void intcs_demux(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *reg = (void *)irq_get_handler_data(irq);
-        unsigned int evtcodeas = ioread32(reg);
-        generic_handle_irq(intcs_evt2irq(evtcodeas));
-}
-static void __iomem *intcs_ffd2;
-static void __iomem *intcs_ffd5;
-void __init sh7372_init_irq(void)
-{
-        void __iomem *intevtsa;
-        int n;
-        intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
-        intevtsa = intcs_ffd2 + 0x100;
-        intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
-        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_lo_desc);
-        register_intc_controller(&intca_irq_pins_hi_desc);
-        register_intc_controller(&intcs_desc);
-        /* setup dummy cascade chip for INTCS */
-        n = evt2irq(0xf80);
-        irq_alloc_desc_at(n, numa_node_id());
-        irq_set_chip_and_handler_name(n, &dummy_irq_chip,
-                                      handle_level_irq, "level");
-        set_irq_flags(n, IRQF_VALID); /* yuck */
-        /* demux using INTEVTSA */
-        irq_set_handler_data(n, (void *)intevtsa);
-        irq_set_chained_handler(n, intcs_demux);
-        /* unmask INTCS in INTAMASK */
-        iowrite16(0, intcs_ffd2 + 0x104);
-}
-static unsigned short ffd2[0x200];
-static unsigned short ffd5[0x100];
-void sh7372_intcs_suspend(void)
-{
-        int k;
-        for (k = 0x00; k <= 0x30; k += 4)
-                ffd2[k] = __raw_readw(intcs_ffd2 + k);
-        for (k = 0x80; k <= 0xb0; k += 4)
-                ffd2[k] = __raw_readb(intcs_ffd2 + k);
-        for (k = 0x180; k <= 0x188; k += 4)
-                ffd2[k] = __raw_readb(intcs_ffd2 + k);
-        for (k = 0x00; k <= 0x3c; k += 4)
-                ffd5[k] = __raw_readw(intcs_ffd5 + k);
-        for (k = 0x80; k <= 0x9c; k += 4)
-                ffd5[k] = __raw_readb(intcs_ffd5 + k);
-}
-void sh7372_intcs_resume(void)
-{
-        int k;
-        for (k = 0x00; k <= 0x30; k += 4)
-                __raw_writew(ffd2[k], intcs_ffd2 + k);
-        for (k = 0x80; k <= 0xb0; k += 4)
-                __raw_writeb(ffd2[k], intcs_ffd2 + k);
-        for (k = 0x180; k <= 0x188; k += 4)
-                __raw_writeb(ffd2[k], intcs_ffd2 + k);
-        for (k = 0x00; k <= 0x3c; k += 4)
-                __raw_writew(ffd5[k], intcs_ffd5 + k);
-        for (k = 0x80; k <= 0x9c; k += 4)
-                __raw_writeb(ffd5[k], intcs_ffd5 + k);
-}
-#define E694_BASE IOMEM(0xe6940000)
-#define E695_BASE IOMEM(0xe6950000)
-static unsigned short e694[0x200];
-static unsigned short e695[0x200];
-void sh7372_intca_suspend(void)
-{
-        int k;
-        for (k = 0x00; k <= 0x38; k += 4)
-                e694[k] = __raw_readw(E694_BASE + k);
-        for (k = 0x80; k <= 0xb4; k += 4)
-                e694[k] = __raw_readb(E694_BASE + k);
-        for (k = 0x180; k <= 0x1b4; k += 4)
-                e694[k] = __raw_readb(E694_BASE + k);
-        for (k = 0x00; k <= 0x50; k += 4)
-                e695[k] = __raw_readw(E695_BASE + k);
-        for (k = 0x80; k <= 0xa8; k += 4)
-                e695[k] = __raw_readb(E695_BASE + k);
-        for (k = 0x180; k <= 0x1a8; k += 4)
-                e695[k] = __raw_readb(E695_BASE + k);
-}
-void sh7372_intca_resume(void)
-{
-        int k;
-        for (k = 0x00; k <= 0x38; k += 4)
-                __raw_writew(e694[k], E694_BASE + k);
-        for (k = 0x80; k <= 0xb4; k += 4)
-                __raw_writeb(e694[k], E694_BASE + k);
-        for (k = 0x180; k <= 0x1b4; k += 4)
-                __raw_writeb(e694[k], E694_BASE + k);
-        for (k = 0x00; k <= 0x50; k += 4)
-                __raw_writew(e695[k], E695_BASE + k);
-        for (k = 0x80; k <= 0xa8; k += 4)
-                __raw_writeb(e695[k], E695_BASE + k);
-        for (k = 0x180; k <= 0x1a8; k += 4)
-                __raw_writeb(e695[k], E695_BASE + k);
-}
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
deleted file mode 100644
index 80e8d95e54d3..000000000000
--- a/arch/arm/mach-shmobile/pm-r8a7790.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * r8a7790 Power management support
- *
- * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/kernel.h>
-#include <linux/smp.h>
-#include <asm/io.h>
-#include "common.h"
-#include "pm-rcar.h"
-#include "r8a7790.h"
-/* RST */
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA7BAR          0x0030
-#define CA15RESCNT      0x0040
-#define CA7RESCNT       0x0044
-/* On-chip RAM */
-#define MERAM          0xe8080000
-/* SYSC */
-#define SYSCIER 0x0c
-#define SYSCIMR 0x10
-#if defined(CONFIG_SMP)
-static void __init r8a7790_sysc_init(void)
-{
-        void __iomem *base = rcar_sysc_init(0xe6180000);
-        /* enable all interrupt sources, but do not use interrupt handler */
-        iowrite32(0x0131000e, base + SYSCIER);
-        iowrite32(0, base + SYSCIMR);
-}
-#else /* CONFIG_SMP */
-static inline void r8a7790_sysc_init(void) {}
-#endif /* CONFIG_SMP */
-void __init r8a7790_pm_init(void)
-{
-        void __iomem *p;
-        u32 bar;
-        static int once;
-        if (once++)
-                return;
-        /* MERAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(MERAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (MERAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar, p + CA7BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA7BAR);
-        /* de-assert reset for all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
-                       p + CA7RESCNT);
-        iounmap(p);
-        r8a7790_sysc_init();
-        shmobile_smp_apmu_suspend_init();
-}
diff --git a/arch/arm/mach-shmobile/pm-r8a7791.c b/arch/arm/mach-shmobile/pm-r8a7791.c
deleted file mode 100644
index 25f107bb3657..000000000000
--- a/arch/arm/mach-shmobile/pm-r8a7791.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * r8a7791 Power management support
- *
- * Copyright (C) 2014  Renesas Electronics Corporation
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/kernel.h>
-#include <linux/smp.h>
-#include <asm/io.h>
-#include "common.h"
-#include "pm-rcar.h"
-#include "r8a7791.h"
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA15RESCNT      0x0040
-#define RAM             0xe6300000
-/* SYSC */
-#define SYSCIER 0x0c
-#define SYSCIMR 0x10
-#if defined(CONFIG_SMP)
-static void __init r8a7791_sysc_init(void)
-{
-        void __iomem *base = rcar_sysc_init(0xe6180000);
-        /* enable all interrupt sources, but do not use interrupt handler */
-        iowrite32(0x0131000e, base + SYSCIER);
-        iowrite32(0, base + SYSCIMR);
-}
-#else /* CONFIG_SMP */
-static inline void r8a7791_sysc_init(void) {}
-#endif /* CONFIG_SMP */
-void __init r8a7791_pm_init(void)
-{
-        void __iomem *p;
-        u32 bar;
-        static int once;
-        if (once++)
-                return;
-        /* RAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(RAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (RAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-        /* enable clocks to all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        iounmap(p);
-        r8a7791_sysc_init();
-        shmobile_smp_apmu_suspend_init();
-}
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
new file mode 100644
index 000000000000..6815781ad116
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -0,0 +1,115 @@
+/*
+ * R-Car Generation 2 Power management support
+ *
+ * Copyright (C) 2013 - 2015  Renesas Electronics Corporation
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+#include <asm/io.h>
+#include "common.h"
+#include "pm-rcar.h"
+#include "rcar-gen2.h"
+/* RST */
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA7BAR          0x0030
+#define CA15RESCNT      0x0040
+#define CA7RESCNT       0x0044
+/* On-chip RAM */
+#define MERAM           0xe8080000
+#define RAM             0xe6300000
+/* SYSC */
+#define SYSCIER 0x0c
+#define SYSCIMR 0x10
+#if defined(CONFIG_SMP)
+static void __init rcar_gen2_sysc_init(u32 syscier)
+{
+        void __iomem *base = rcar_sysc_init(0xe6180000);
+        /* enable all interrupt sources, but do not use interrupt handler */
+        iowrite32(syscier, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
+}
+#else /* CONFIG_SMP */
+static inline void rcar_gen2_sysc_init(u32 syscier) {}
+#endif /* CONFIG_SMP */
+void __init rcar_gen2_pm_init(void)
+{
+        void __iomem *p;
+        u32 bar;
+        static int once;
+        struct device_node *np, *cpus;
+        bool has_a7 = false;
+        bool has_a15 = false;
+        phys_addr_t boot_vector_addr = 0;
+        u32 syscier = 0;
+        if (once++)
+                return;
+        cpus = of_find_node_by_path("/cpus");
+        if (!cpus)
+                return;
+        for_each_child_of_node(cpus, np) {
+                if (of_device_is_compatible(np, "arm,cortex-a15"))
+                        has_a15 = true;
+                else if (of_device_is_compatible(np, "arm,cortex-a7"))
+                        has_a7 = true;
+        }
+        if (of_machine_is_compatible("renesas,r8a7790")) {
+                boot_vector_addr = MERAM;
+                syscier = 0x013111ef;
+        } else if (of_machine_is_compatible("renesas,r8a7791")) {
+                boot_vector_addr = RAM;
+                syscier = 0x00111003;
+        }
+        /* RAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (boot_vector_addr >> 8) & 0xfffffc00;
+        if (has_a15) {
+                writel_relaxed(bar, p + CA15BAR);
+                writel_relaxed(bar | 0x10, p + CA15BAR);
+                /* de-assert reset for CA15 CPUs */
+                writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
+                                0xa5a50000, p + CA15RESCNT);
+        }
+        if (has_a7) {
+                writel_relaxed(bar, p + CA7BAR);
+                writel_relaxed(bar | 0x10, p + CA7BAR);
+                /* de-assert reset for CA7 CPUs */
+                writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
+                                0x5a5a0000, p + CA7RESCNT);
+        }
+        iounmap(p);
+        rcar_gen2_sysc_init(syscier);
+        shmobile_smp_apmu_suspend_init();
+}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
deleted file mode 100644
index c0293ae4b013..000000000000
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/*
- * sh7372 Power management support
- *
- *  Copyright (C) 2011 Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/pm.h>
-#include <linux/suspend.h>
-#include <linux/cpuidle.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/pm_clock.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/bitrev.h>
-#include <linux/console.h>
-#include <asm/cpuidle.h>
-#include <asm/io.h>
-#include <asm/tlbflush.h>
-#include <asm/suspend.h>
-#include "common.h"
-#include "pm-rmobile.h"
-#include "sh7372.h"
-/* DBG */
-#define DBGREG1 IOMEM(0xe6100020)
-#define DBGREG9 IOMEM(0xe6100040)
-/* CPGA */
-#define SYSTBCR IOMEM(0xe6150024)
-#define MSTPSR0 IOMEM(0xe6150030)
-#define MSTPSR1 IOMEM(0xe6150038)
-#define MSTPSR2 IOMEM(0xe6150040)
-#define MSTPSR3 IOMEM(0xe6150048)
-#define MSTPSR4 IOMEM(0xe615004c)
-#define PLLC01STPCR IOMEM(0xe61500c8)
-/* SYSC */
-#define SYSC_BASE IOMEM(0xe6180000)
-#define SBAR IOMEM(0xe6180020)
-#define WUPRMSK IOMEM(0xe6180028)
-#define WUPSMSK IOMEM(0xe618002c)
-#define WUPSMSK2 IOMEM(0xe6180048)
-#define WUPSFAC IOMEM(0xe6180098)
-#define IRQCR IOMEM(0xe618022c)
-#define IRQCR2 IOMEM(0xe6180238)
-#define IRQCR3 IOMEM(0xe6180244)
-#define IRQCR4 IOMEM(0xe6180248)
-#define PDNSEL IOMEM(0xe6180254)
-/* INTC */
-#define ICR1A IOMEM(0xe6900000)
-#define ICR2A IOMEM(0xe6900004)
-#define ICR3A IOMEM(0xe6900008)
-#define ICR4A IOMEM(0xe690000c)
-#define INTMSK00A IOMEM(0xe6900040)
-#define INTMSK10A IOMEM(0xe6900044)
-#define INTMSK20A IOMEM(0xe6900048)
-#define INTMSK30A IOMEM(0xe690004c)
-/* MFIS */
-/* FIXME: pointing where? */
-#define SMFRAM 0xe6a70000
-/* AP-System Core */
-#define APARMBAREA IOMEM(0xe6f10020)
-#ifdef CONFIG_PM
-#define PM_DOMAIN_ON_OFF_LATENCY_NS     250000
-static int sh7372_a4r_pd_suspend(void)
-{
-        sh7372_intcs_suspend();
-        __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
-        return 0;
-}
-static bool a4s_suspend_ready;
-static int sh7372_a4s_pd_suspend(void)
-{
-        /*
-         * The A4S domain contains the CPU core and therefore it should
-         * only be turned off if the CPU is not in use.  This may happen
-         * during system suspend, when SYSC is going to be used for generating
-         * resume signals and a4s_suspend_ready is set to let
-         * sh7372_enter_suspend() know that it can turn A4S off.
-         */
-        a4s_suspend_ready = true;
-        return -EBUSY;
-}
-static void sh7372_a4s_pd_resume(void)
-{
-        a4s_suspend_ready = false;
-}
-static int sh7372_a3sp_pd_suspend(void)
-{
-        /*
-         * Serial consoles make use of SCIF hardware located in A3SP,
-         * keep such power domain on if "no_console_suspend" is set.
-         */
-        return console_suspend_enabled ? 0 : -EBUSY;
-}
-static struct rmobile_pm_domain sh7372_pm_domains[] = {
-        {
-                .genpd.name = "A4LC",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 1,
-        },
-        {
-                .genpd.name = "A4MP",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 2,
-        },
-        {
-                .genpd.name = "D4",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 3,
-        },
-        {
-                .genpd.name = "A4R",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 5,
-                .suspend = sh7372_a4r_pd_suspend,
-                .resume = sh7372_intcs_resume,
-        },
-        {
-                .genpd.name = "A3RV",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 6,
-        },
-        {
-                .genpd.name = "A3RI",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 8,
-        },
-        {
-                .genpd.name = "A4S",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 10,
-                .gov = &pm_domain_always_on_gov,
-                .no_debug = true,
-                .suspend = sh7372_a4s_pd_suspend,
-                .resume = sh7372_a4s_pd_resume,
-        },
-        {
-                .genpd.name = "A3SP",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 11,
-                .gov = &pm_domain_always_on_gov,
-                .no_debug = true,
-                .suspend = sh7372_a3sp_pd_suspend,
-        },
-        {
-                .genpd.name = "A3SG",
-                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-                .base = SYSC_BASE,
-                .bit_shift = 13,
-        },
-};
-void __init sh7372_init_pm_domains(void)
-{
-        rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
-        pm_genpd_add_subdomain_names("A4LC", "A3RV");
-        pm_genpd_add_subdomain_names("A4R", "A4LC");
-        pm_genpd_add_subdomain_names("A4S", "A3SG");
-        pm_genpd_add_subdomain_names("A4S", "A3SP");
-}
-#endif /* CONFIG_PM */
-#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
-static void sh7372_set_reset_vector(unsigned long address)
-{
-        /* set reset vector, translate 4k */
-        __raw_writel(address, SBAR);
-        __raw_writel(0, APARMBAREA);
-}
-static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
-{
-        if (pllc0_on)
-                __raw_writel(0, PLLC01STPCR);
-        else
-                __raw_writel(1 << 28, PLLC01STPCR);
-        __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
-        cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
-        __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
-         /* disable reset vector translation */
-        __raw_writel(0, SBAR);
-}
-static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
-{
-        unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
-        unsigned long msk, msk2;
-        /* check active clocks to determine potential wakeup sources */
-        mstpsr0 = __raw_readl(MSTPSR0);
-        if ((mstpsr0 & 0x00000003) != 0x00000003) {
-                pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
-                return 0;
-        }
-        mstpsr1 = __raw_readl(MSTPSR1);
-        if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
-                pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
-                return 0;
-        }
-        mstpsr2 = __raw_readl(MSTPSR2);
-        if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
-                pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
-                return 0;
-        }
-        mstpsr3 = __raw_readl(MSTPSR3);
-        if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
-                pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
-                return 0;
-        }
-        mstpsr4 = __raw_readl(MSTPSR4);
-        if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
-                pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
-                return 0;
-        }
-        msk = 0;
-        msk2 = 0;
-        /* make bitmaps of limited number of wakeup sources */
-        if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
-                msk |= 1 << 31;
-        if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
-                msk |= 1 << 21;
-        if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
-                msk |= 1 << 2;
-        if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
-                msk |= 1 << 1;
-        if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
-                msk |= 1 << 1;
-        if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
-                msk |= 1 << 1;
-        if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
-                msk2 |= 1 << 17;
-        *mskp = msk;
-        *msk2p = msk2;
-        return 1;
-}
-static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
-{
-        u16 tmp, irqcr1, irqcr2;
-        int k;
-        irqcr1 = 0;
-        irqcr2 = 0;
-        /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
-        for (k = 0; k <= 7; k++) {
-                tmp = (icr >> ((7 - k) * 4)) & 0xf;
-                irqcr1 |= (tmp & 0x03) << (k * 2);
-                irqcr2 |= (tmp >> 2) << (k * 2);
-        }
-        *irqcr1p = irqcr1;
-        *irqcr2p = irqcr2;
-}
-static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
-{
-        u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
-        unsigned long tmp;
-        /* read IRQ0A -> IRQ15A mask */
-        tmp = bitrev8(__raw_readb(INTMSK00A));
-        tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
-        /* setup WUPSMSK from clocks and external IRQ mask */
-        msk = (~msk & 0xc030000f) | (tmp << 4);
-        __raw_writel(msk, WUPSMSK);
-        /* propage level/edge trigger for external IRQ 0->15 */
-        sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
-        sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
-        __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
-        __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
-        /* read IRQ16A -> IRQ31A mask */
-        tmp = bitrev8(__raw_readb(INTMSK20A));
-        tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
-        /* setup WUPSMSK2 from clocks and external IRQ mask */
-        msk2 = (~msk2 & 0x00030000) | tmp;
-        __raw_writel(msk2, WUPSMSK2);
-        /* propage level/edge trigger for external IRQ 16->31 */
-        sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
-        sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
-        __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
-        __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
-}
-static void sh7372_enter_a3sm_common(int pllc0_on)
-{
-        /* use INTCA together with SYSC for wakeup */
-        sh7372_setup_sysc(1 << 0, 0);
-        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
-        sh7372_enter_sysc(pllc0_on, 1 << 12);
-}
-static void sh7372_enter_a4s_common(int pllc0_on)
-{
-        sh7372_intca_suspend();
-        sh7372_set_reset_vector(SMFRAM);
-        sh7372_enter_sysc(pllc0_on, 1 << 10);
-        sh7372_intca_resume();
-}
-static void sh7372_pm_setup_smfram(void)
-{
-        /* pass physical address of cpu_resume() to assembly resume code */
-        sh7372_cpu_resume = virt_to_phys(cpu_resume);
-        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
-}
-#else
-static inline void sh7372_pm_setup_smfram(void) {}
-#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
-#ifdef CONFIG_CPU_IDLE
-static int sh7372_do_idle_core_standby(unsigned long unused)
-{
-        cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
-        return 0;
-}
-static int sh7372_enter_core_standby(struct cpuidle_device *dev,
-                                     struct cpuidle_driver *drv, int index)
-{
-        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
-        /* enter sleep mode with SYSTBCR to 0x10 */
-        __raw_writel(0x10, SYSTBCR);
-        cpu_suspend(0, sh7372_do_idle_core_standby);
-        __raw_writel(0, SYSTBCR);
-         /* disable reset vector translation */
-        __raw_writel(0, SBAR);
-        return 1;
-}
-static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
-                                    struct cpuidle_driver *drv, int index)
-{
-        sh7372_enter_a3sm_common(1);
-        return 2;
-}
-static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
-                                     struct cpuidle_driver *drv, int index)
-{
-        sh7372_enter_a3sm_common(0);
-        return 3;
-}
-static int sh7372_enter_a4s(struct cpuidle_device *dev,
-                            struct cpuidle_driver *drv, int index)
-{
-        unsigned long msk, msk2;
-        if (!sh7372_sysc_valid(&msk, &msk2))
-                return sh7372_enter_a3sm_pll_off(dev, drv, index);
-        sh7372_setup_sysc(msk, msk2);
-        sh7372_enter_a4s_common(0);
-        return 4;
-}
-static struct cpuidle_driver sh7372_cpuidle_driver = {
-        .name                   = "sh7372_cpuidle",
-        .owner                  = THIS_MODULE,
-        .state_count            = 5,
-        .safe_state_index       = 0, /* C1 */
-        .states[0] = ARM_CPUIDLE_WFI_STATE,
-        .states[1] = {
-                .name = "C2",
-                .desc = "Core Standby Mode",
-                .exit_latency = 10,
-                .target_residency = 20 + 10,
-                .enter = sh7372_enter_core_standby,
-        },
-        .states[2] = {
-                .name = "C3",
-                .desc = "A3SM PLL ON",
-                .exit_latency = 20,
-                .target_residency = 30 + 20,
-                .enter = sh7372_enter_a3sm_pll_on,
-        },
-        .states[3] = {
-                .name = "C4",
-                .desc = "A3SM PLL OFF",
-                .exit_latency = 120,
-                .target_residency = 30 + 120,
-                .enter = sh7372_enter_a3sm_pll_off,
-        },
-        .states[4] = {
-                .name = "C5",
-                .desc = "A4S PLL OFF",
-                .exit_latency = 240,
-                .target_residency = 30 + 240,
-                .enter = sh7372_enter_a4s,
-                .disabled = true,
-        },
-};
-static void __init sh7372_cpuidle_init(void)
-{
-        shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
-}
-#else
-static void __init sh7372_cpuidle_init(void) {}
-#endif
-#ifdef CONFIG_SUSPEND
-static int sh7372_enter_suspend(suspend_state_t suspend_state)
-{
-        unsigned long msk, msk2;
-        /* check active clocks to determine potential wakeup sources */
-        if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
-                /* convert INTC mask/sense to SYSC mask/sense */
-                sh7372_setup_sysc(msk, msk2);
-                /* enter A4S sleep with PLLC0 off */
-                pr_debug("entering A4S\n");
-                sh7372_enter_a4s_common(0);
-                return 0;
-        }
-        /* default to enter A3SM sleep with PLLC0 off */
-        pr_debug("entering A3SM\n");
-        sh7372_enter_a3sm_common(0);
-        return 0;
-}
-/**
- * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
- * @notifier: Unused.
- * @pm_event: Event being handled.
- * @unused: Unused.
- */
-static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
-                                 unsigned long pm_event, void *unused)
-{
-        switch (pm_event) {
-        case PM_SUSPEND_PREPARE:
-                /*
-                 * This is necessary, because the A4R domain has to be "on"
-                 * when suspend_device_irqs() and resume_device_irqs() are
-                 * executed during system suspend and resume, respectively, so
-                 * that those functions don't crash while accessing the INTCS.
-                 */
-                pm_genpd_name_poweron("A4R");
-                break;
-        case PM_POST_SUSPEND:
-                pm_genpd_poweroff_unused();
-                break;
-        }
-        return NOTIFY_DONE;
-}
-static void sh7372_suspend_init(void)
-{
-        shmobile_suspend_ops.enter = sh7372_enter_suspend;
-        pm_notifier(sh7372_pm_notifier_fn, 0);
-}
-#else
-static void sh7372_suspend_init(void) {}
-#endif
-void __init sh7372_pm_init(void)
-{
-        /* enable DBG hardware block to kick SYSC */
-        __raw_writel(0x0000a500, DBGREG9);
-        __raw_writel(0x0000a501, DBGREG9);
-        __raw_writel(0x00000000, DBGREG1);
-        /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
-        __raw_writel(0, PDNSEL);
-        sh7372_pm_setup_smfram();
-        sh7372_suspend_init();
-        sh7372_cpuidle_init();
-}
-void __init sh7372_pm_init_late(void)
-{
-        shmobile_init_late();
-        pm_genpd_name_attach_cpuidle("A4S", 4);
-}
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
deleted file mode 100644
index 70dcd847a86e..000000000000
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __ASM_R8A73A4_H__
-#define __ASM_R8A73A4_H__
-/* DMA slave IDs */
-enum {
-        SHDMA_SLAVE_INVALID,
-        SHDMA_SLAVE_MMCIF0_TX,
-        SHDMA_SLAVE_MMCIF0_RX,
-        SHDMA_SLAVE_MMCIF1_TX,
-        SHDMA_SLAVE_MMCIF1_RX,
-};
-void r8a73a4_add_standard_devices(void);
-void r8a73a4_clock_init(void);
-void r8a73a4_pinmux_init(void);
-#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index bf73a850aaed..1a46d026052c 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
-void r8a7790_pm_init(void);
 extern struct smp_operations r8a7790_smp_ops;
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index 6cf11eb69d10..7ca0b7d0f59b 100644
--- a/arch/arm/mach-shmobile/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7791_H__
 #define __ASM_R8A7791_H__
-void r8a7791_pm_init(void);
 extern struct smp_operations r8a7791_smp_ops;
 #endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h
index ce53cb5f53a1..8a66b4aae035 100644
--- a/arch/arm/mach-shmobile/rcar-gen2.h
+++ b/arch/arm/mach-shmobile/rcar-gen2.h
@@ -5,5 +5,6 @@ void rcar_gen2_timer_init(void);
 #define MD(nr) BIT(nr)
 u32 rcar_gen2_read_mode_pins(void);
 void rcar_gen2_reserve(void);
+void rcar_gen2_pm_init(void);
 #endif /* __ASM_RCAR_GEN2_H__ */
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
new file mode 100644
index 000000000000..384e6e934b87
--- /dev/null
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -0,0 +1,147 @@
+/*
+ * R-Car Generation 2 da9063/da9210 regulator quirk
+ *
+ * The r8a7790/lager and r8a7791/koelsch development boards have da9063 and
+ * da9210 regulators.  Both regulators have their interrupt request lines tied
+ * to the same interrupt pin (IRQ2) on the SoC.
+ *
+ * After cold boot or da9063-induced restart, both the da9063 and da9210 seem
+ * to assert their interrupt request lines.  Hence as soon as one driver
+ * requests this irq, it gets stuck in an interrupt storm, as it only manages
+ * to deassert its own interrupt request line, and the other driver hasn't
+ * installed an interrupt handler yet.
+ *
+ * To handle this, install a quirk that masks the interrupts in both the
+ * da9063 and da9210.  This quirk has to run after the i2c master driver has
+ * been initialized, but before the i2c slave drivers are initialized.
+ *
+ * Copyright (C) 2015 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/mfd/da9063/registers.h>
+#define IRQC_BASE               0xe61c0000
+#define IRQC_MONITOR            0x104   /* IRQn Signal Level Monitor Register */
+#define REGULATOR_IRQ_MASK      BIT(2)  /* IRQ2, active low */
+static void __iomem *irqc;
+static const u8 da9063_mask_regs[] = {
+        DA9063_REG_IRQ_MASK_A,
+        DA9063_REG_IRQ_MASK_B,
+        DA9063_REG_IRQ_MASK_C,
+        DA9063_REG_IRQ_MASK_D,
+};
+/* DA9210 System Control and Event Registers */
+#define DA9210_REG_MASK_A               0x54
+#define DA9210_REG_MASK_B               0x55
+static const u8 da9210_mask_regs[] = {
+        DA9210_REG_MASK_A,
+        DA9210_REG_MASK_B,
+};
+static void da9xxx_mask_irqs(struct i2c_client *client, const u8 regs[],
+                             unsigned int nregs)
+{
+        unsigned int i;
+        dev_info(&client->dev, "Masking %s interrupt sources\n", client->name);
+        for (i = 0; i < nregs; i++) {
+                int error = i2c_smbus_write_byte_data(client, regs[i], ~0);
+                if (error) {
+                        dev_err(&client->dev, "i2c error %d\n", error);
+                        return;
+                }
+        }
+}
+static int regulator_quirk_notify(struct notifier_block *nb,
+                                  unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct i2c_client *client;
+        u32 mon;
+        mon = ioread32(irqc + IRQC_MONITOR);
+        dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
+        if (mon & REGULATOR_IRQ_MASK)
+                goto remove;
+        if (action != BUS_NOTIFY_ADD_DEVICE || dev->type == &i2c_adapter_type)
+                return 0;
+        client = to_i2c_client(dev);
+        dev_dbg(dev, "Detected %s\n", client->name);
+        if ((client->addr == 0x58 && !strcmp(client->name, "da9063")))
+                da9xxx_mask_irqs(client, da9063_mask_regs,
+                                 ARRAY_SIZE(da9063_mask_regs));
+        else if (client->addr == 0x68 && !strcmp(client->name, "da9210"))
+                da9xxx_mask_irqs(client, da9210_mask_regs,
+                                 ARRAY_SIZE(da9210_mask_regs));
+        mon = ioread32(irqc + IRQC_MONITOR);
+        if (mon & REGULATOR_IRQ_MASK)
+                goto remove;
+        return 0;
+remove:
+        dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
+        bus_unregister_notifier(&i2c_bus_type, nb);
+        iounmap(irqc);
+        return 0;
+}
+static struct notifier_block regulator_quirk_nb = {
+        .notifier_call = regulator_quirk_notify
+};
+static int __init rcar_gen2_regulator_quirk(void)
+{
+        u32 mon;
+        if (!of_machine_is_compatible("renesas,koelsch") &&
+            !of_machine_is_compatible("renesas,lager"))
+                return -ENODEV;
+        irqc = ioremap(IRQC_BASE, PAGE_SIZE);
+        if (!irqc)
+                return -ENOMEM;
+        mon = ioread32(irqc + IRQC_MONITOR);
+        if (mon & REGULATOR_IRQ_MASK) {
+                pr_debug("%s: IRQ2 is not asserted, not installing quirk\n",
+                         __func__);
+                iounmap(irqc);
+                return 0;
+        }
+        pr_info("IRQ2 is asserted, installing da9063/da9210 regulator quirk\n");
+        bus_register_notifier(&i2c_bus_type, &regulator_quirk_nb);
+        return 0;
+}
+arch_initcall(rcar_gen2_regulator_quirk);
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c27682291cbf..446cee611902 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -13,280 +13,12 @@
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
-#include <linux/irq.h>
-#include <linux/kernel.h>
+#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <linux/platform_data/irq-renesas-irqc.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_dma.h>
-#include <linux/sh_timer.h>
 #include <asm/mach/arch.h>
 #include "common.h"
-#include "dma-register.h"
-#include "irqs.h"
-#include "r8a73a4.h"
-static const struct resource pfc_resources[] = {
-        DEFINE_RES_MEM(0xe6050000, 0x9000),
-};
-void __init r8a73a4_pinmux_init(void)
-{
-        platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
-                                        ARRAY_SIZE(pfc_resources));
-}
-#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq)   \
-static struct plat_sci_port scif##index##_platform_data = {     \
-        .type           = scif_type,                            \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
-        .scscr          = _scscr,                               \
-};                                                              \
-                                                                \
-static struct resource scif##index##_resources[] = {            \
-        DEFINE_RES_MEM(baseaddr, 0x100),                        \
-        DEFINE_RES_IRQ(irq),                                    \
-}
-#define R8A73A4_SCIFA(index, baseaddr, irq)     \
-        R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
-                     index, baseaddr, irq)
-#define R8A73A4_SCIFB(index, baseaddr, irq)     \
-        R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
-                     index, baseaddr, irq)
-R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
-R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
-R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
-R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
-R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
-R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
-#define r8a73a4_register_scif(index)                                           \
-        platform_device_register_resndata(NULL, "sh-sci", index,               \
-                                          scif##index##_resources,             \
-                                          ARRAY_SIZE(scif##index##_resources), \
-                                          &scif##index##_platform_data,        \
-                                          sizeof(scif##index##_platform_data))
-static const struct renesas_irqc_config irqc0_data = {
-        .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
-};
-static const struct resource irqc0_resources[] = {
-        DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
-        DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
-        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
-        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
-        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
-        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
-        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
-        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
-        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
-        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
-        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
-        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
-        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
-        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
-        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
-        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
-        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
-        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
-        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
-        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
-        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
-        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
-        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
-        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
-        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
-        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
-        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
-        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
-        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
-        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
-        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
-        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
-        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
-};
-static const struct renesas_irqc_config irqc1_data = {
-        .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
-};
-static const struct resource irqc1_resources[] = {
-        DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
-        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
-        DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
-        DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
-        DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
-        DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
-        DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
-        DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
-        DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
-        DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
-        DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
-        DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
-        DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
-        DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
-        DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
-        DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
-        DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
-        DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
-        DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
-        DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
-        DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
-        DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
-        DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
-        DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
-        DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
-        DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
-        DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
-};
-#define r8a73a4_register_irqc(idx)                                      \
-        platform_device_register_resndata(NULL, "renesas_irqc",         \
-                                          idx, irqc##idx##_resources,   \
-                                          ARRAY_SIZE(irqc##idx##_resources), \
-                                          &irqc##idx##_data,            \
-                                          sizeof(struct renesas_irqc_config))
-/* Thermal0 -> Thermal2 */
-static const struct resource thermal0_resources[] = {
-        DEFINE_RES_MEM(0xe61f0000, 0x14),
-        DEFINE_RES_MEM(0xe61f0100, 0x38),
-        DEFINE_RES_MEM(0xe61f0200, 0x38),
-        DEFINE_RES_MEM(0xe61f0300, 0x38),
-        DEFINE_RES_IRQ(gic_spi(69)),
-};
-#define r8a73a4_register_thermal()                                      \
-        platform_device_register_simple("rcar_thermal", -1,             \
-                                        thermal0_resources,             \
-                                        ARRAY_SIZE(thermal0_resources))
-static struct sh_timer_config cmt1_platform_data = {
-        .channels_mask = 0xff,
-};
-static struct resource cmt1_resources[] = {
-        DEFINE_RES_MEM(0xe6130000, 0x1004),
-        DEFINE_RES_IRQ(gic_spi(120)),
-};
-#define r8a73a4_register_cmt(idx)                                       \
-        platform_device_register_resndata(NULL, "sh-cmt-48-gen2",       \
-                                          idx, cmt##idx##_resources,    \
-                                          ARRAY_SIZE(cmt##idx##_resources), \
-                                          &cmt##idx##_platform_data,    \
-                                          sizeof(struct sh_timer_config))
-/* DMA */
-static const struct sh_dmae_slave_config dma_slaves[] = {
-        {
-                .slave_id       = SHDMA_SLAVE_MMCIF0_TX,
-                .addr           = 0xee200034,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xd1,
-        }, {
-                .slave_id       = SHDMA_SLAVE_MMCIF0_RX,
-                .addr           = 0xee200034,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xd2,
-        }, {
-                .slave_id       = SHDMA_SLAVE_MMCIF1_TX,
-                .addr           = 0xee220034,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xe1,
-        }, {
-                .slave_id       = SHDMA_SLAVE_MMCIF1_RX,
-                .addr           = 0xee220034,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xe2,
-        },
-};
-#define DMAE_CHANNEL(a, b)                              \
-        {                                               \
-                .offset         = (a) - 0x20,           \
-                .dmars          = (a) - 0x20 + 0x40,    \
-                .chclr_bit      = (b),                  \
-                .chclr_offset   = 0x80 - 0x20,          \
-        }
-static const struct sh_dmae_channel dma_channels[] = {
-        DMAE_CHANNEL(0x8000, 0),
-        DMAE_CHANNEL(0x8080, 1),
-        DMAE_CHANNEL(0x8100, 2),
-        DMAE_CHANNEL(0x8180, 3),
-        DMAE_CHANNEL(0x8200, 4),
-        DMAE_CHANNEL(0x8280, 5),
-        DMAE_CHANNEL(0x8300, 6),
-        DMAE_CHANNEL(0x8380, 7),
-        DMAE_CHANNEL(0x8400, 8),
-        DMAE_CHANNEL(0x8480, 9),
-        DMAE_CHANNEL(0x8500, 10),
-        DMAE_CHANNEL(0x8580, 11),
-        DMAE_CHANNEL(0x8600, 12),
-        DMAE_CHANNEL(0x8680, 13),
-        DMAE_CHANNEL(0x8700, 14),
-        DMAE_CHANNEL(0x8780, 15),
-        DMAE_CHANNEL(0x8800, 16),
-        DMAE_CHANNEL(0x8880, 17),
-        DMAE_CHANNEL(0x8900, 18),
-        DMAE_CHANNEL(0x8980, 19),
-};
-static const struct sh_dmae_pdata dma_pdata = {
-        .slave          = dma_slaves,
-        .slave_num      = ARRAY_SIZE(dma_slaves),
-        .channel        = dma_channels,
-        .channel_num    = ARRAY_SIZE(dma_channels),
-        .ts_low_shift   = TS_LOW_SHIFT,
-        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
-        .ts_high_shift  = TS_HI_SHIFT,
-        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
-        .ts_shift       = dma_ts_shift,
-        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
-        .dmaor_init     = DMAOR_DME,
-        .chclr_present  = 1,
-        .chclr_bitwise  = 1,
-};
-static struct resource dma_resources[] = {
-        DEFINE_RES_MEM(0xe6700020, 0x89e0),
-        DEFINE_RES_IRQ(gic_spi(220)),
-        {
-                /* IRQ for channels 0-19 */
-                .start  = gic_spi(200),
-                .end    = gic_spi(219),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-#define r8a73a4_register_dmac()                                                 \
-        platform_device_register_resndata(NULL, "sh-dma-engine", 0,             \
-                                dma_resources, ARRAY_SIZE(dma_resources),       \
-                                &dma_pdata, sizeof(dma_pdata))
-void __init r8a73a4_add_standard_devices(void)
-{
-        r8a73a4_register_cmt(1);
-        r8a73a4_register_scif(0);
-        r8a73a4_register_scif(1);
-        r8a73a4_register_scif(2);
-        r8a73a4_register_scif(3);
-        r8a73a4_register_scif(4);
-        r8a73a4_register_scif(5);
-        r8a73a4_register_irqc(0);
-        r8a73a4_register_irqc(1);
-        r8a73a4_register_thermal();
-        r8a73a4_register_dmac();
-}
-#ifdef CONFIG_USE_OF
 static const char *r8a73a4_boards_compat_dt[] __initdata = {
        "renesas,r8a73a4",
@@ -298,4 +30,3 @@ DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
        .init_late      = shmobile_init_late,
        .dt_compat      = r8a73a4_boards_compat_dt,
 MACHINE_END
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index dd64caf79216..9832e48396a4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -842,13 +842,6 @@ static void __init r8a7740_generic_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-#define RESCNT2 IOMEM(0xe6188020)
-static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
-{
-        /* Do soft power on reset */
-        writel(1 << 31, RESCNT2);
-}
 static const char *r8a7740_boards_compat_dt[] __initdata = {
        "renesas,r8a7740",
        NULL,
@@ -861,7 +854,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
        .init_machine   = r8a7740_generic_init,
        .init_late      = shmobile_init_late,
        .dt_compat      = r8a7740_boards_compat_dt,
-        .restart        = r8a7740_restart,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index cef8895a9b82..c49aa094fe17 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -15,6 +15,7 @@
 * GNU General Public License for more details.
 */
+#include <linux/clk/shmobile.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
@@ -41,6 +42,21 @@
 #include "irqs.h"
 #include "r8a7778.h"
+#define MODEMR 0xffcc0020
+#ifdef CONFIG_COMMON_CLK
+static void __init r8a7778_timer_init(void)
+{
+        u32 mode;
+        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+        r8a7778_clocks_init(mode);
+}
+#endif
 /* SCIF */
 #define R8A7778_SCIF(index, baseaddr, irq)                      \
 static struct plat_sci_port scif##index##_platform_data = {     \
@@ -608,6 +624,9 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
        .init_early     = shmobile_init_delay,
        .init_irq       = r8a7778_init_irq_dt,
        .init_late      = shmobile_init_late,
+#ifdef CONFIG_COMMON_CLK
+        .init_time      = r8a7778_timer_init,
+#endif
        .dt_compat      = r8a7778_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index d1fa625e61f5..5d13595aa027 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -21,6 +21,7 @@
 #include <linux/dma-contiguous.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/memblock.h>
 #include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <asm/mach/arch.h>
@@ -50,9 +51,7 @@ u32 rcar_gen2_read_mode_pins(void)
 void __init rcar_gen2_timer_init(void)
 {
-#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
        u32 mode = rcar_gen2_read_mode_pins();
-#endif
 #ifdef CONFIG_ARM_ARCH_TIMER
        void __iomem *base;
        int extal_mhz = 0;
@@ -128,9 +127,7 @@ void __init rcar_gen2_timer_init(void)
        iounmap(base);
 #endif /* CONFIG_ARM_ARCH_TIMER */
-#ifdef CONFIG_COMMON_CLK
        rcar_gen2_clocks_init(mode);
-#endif
 #ifdef CONFIG_ARCH_SHMOBILE_MULTI
        clocksource_of_init();
 #endif
@@ -199,7 +196,7 @@ void __init rcar_gen2_reserve(void)
        of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
 #ifdef CONFIG_DMA_CMA
-        if (mrc.size)
+        if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size))
                dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
                                            &rcar_gen2_dma_contiguous, true);
 #endif
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
deleted file mode 100644
index 458a2cfad417..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ /dev/null
@@ -1,1016 +0,0 @@
-/*
- * sh7372 processor support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/uio_driver.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_dma.h>
-#include <linux/sh_timer.h>
-#include <linux/pm_domain.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_data/sh_ipmmu.h>
-#include <asm/mach/map.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#include "dma-register.h"
-#include "intc.h"
-#include "irqs.h"
-#include "pm-rmobile.h"
-#include "sh7372.h"
-static struct map_desc sh7372_io_desc[] __initdata = {
-        /* create a 1:1 identity mapping for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-void __init sh7372_map_io(void)
-{
-        debug_ll_io_init();
-        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
-}
-/* PFC */
-static struct resource sh7372_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe6058027,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device sh7372_pfc_device = {
-        .name           = "pfc-sh7372",
-        .id             = -1,
-        .resource       = sh7372_pfc_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
-};
-void __init sh7372_pinmux_init(void)
-{
-        platform_device_register(&sh7372_pfc_device);
-}
-/* SCIF */
-#define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
-static struct plat_sci_port scif##index##_platform_data = {     \
-        .type           = scif_type,                            \
-        .flags          = UPF_BOOT_AUTOCONF,                    \
-        .scscr          = SCSCR_RE | SCSCR_TE,                  \
-};                                                              \
-                                                                \
-static struct resource scif##index##_resources[] = {            \
-        DEFINE_RES_MEM(baseaddr, 0x100),                        \
-        DEFINE_RES_IRQ(irq),                                    \
-};                                                              \
-                                                                \
-static struct platform_device scif##index##_device = {          \
-        .name           = "sh-sci",                             \
-        .id             = index,                                \
-        .resource       = scif##index##_resources,              \
-        .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
-        .dev            = {                                     \
-                .platform_data  = &scif##index##_platform_data, \
-        },                                                      \
-}
-SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
-SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
-SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
-SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
-SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
-SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
-SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
-/* CMT */
-static struct sh_timer_config cmt2_platform_data = {
-        .channels_mask = 0x20,
-};
-static struct resource cmt2_resources[] = {
-        DEFINE_RES_MEM(0xe6130000, 0x50),
-        DEFINE_RES_IRQ(evt2irq(0x0b80)),
-};
-static struct platform_device cmt2_device = {
-        .name           = "sh-cmt-32-fast",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &cmt2_platform_data,
-        },
-        .resource       = cmt2_resources,
-        .num_resources  = ARRAY_SIZE(cmt2_resources),
-};
-/* TMU */
-static struct sh_timer_config tmu0_platform_data = {
-        .channels_mask = 7,
-};
-static struct resource tmu0_resources[] = {
-        DEFINE_RES_MEM(0xfff60000, 0x2c),
-        DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
-        DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
-        DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
-};
-static struct platform_device tmu0_device = {
-        .name           = "sh-tmu",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &tmu0_platform_data,
-        },
-        .resource       = tmu0_resources,
-        .num_resources  = ARRAY_SIZE(tmu0_resources),
-};
-/* I2C */
-static struct resource iic0_resources[] = {
-        [0] = {
-                .name   = "IIC0",
-                .start  = 0xFFF20000,
-                .end    = 0xFFF20425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
-                .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device iic0_device = {
-        .name           = "i2c-sh_mobile",
-        .id             = 0, /* "i2c0" clock */
-        .num_resources  = ARRAY_SIZE(iic0_resources),
-        .resource       = iic0_resources,
-};
-static struct resource iic1_resources[] = {
-        [0] = {
-                .name   = "IIC1",
-                .start  = 0xE6C20000,
-                .end    = 0xE6C20425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x780), /* IIC1_ALI1 */
-                .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device iic1_device = {
-        .name           = "i2c-sh_mobile",
-        .id             = 1, /* "i2c1" clock */
-        .num_resources  = ARRAY_SIZE(iic1_resources),
-        .resource       = iic1_resources,
-};
-/* DMA */
-static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
-        {
-                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
-                .addr           = 0xe6c40020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x21,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
-                .addr           = 0xe6c40024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x22,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
-                .addr           = 0xe6c50020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x25,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
-                .addr           = 0xe6c50024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x26,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
-                .addr           = 0xe6c60020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x29,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
-                .addr           = 0xe6c60024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x2a,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
-                .addr           = 0xe6c70020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x2d,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
-                .addr           = 0xe6c70024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x2e,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
-                .addr           = 0xe6c80020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x39,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
-                .addr           = 0xe6c80024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x3a,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF5_TX,
-                .addr           = 0xe6cb0020,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x35,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF5_RX,
-                .addr           = 0xe6cb0024,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x36,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF6_TX,
-                .addr           = 0xe6c30040,
-                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x3d,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SCIF6_RX,
-                .addr           = 0xe6c30060,
-                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
-                .mid_rid        = 0x3e,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
-                .addr           = 0xe6a30050,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0x83,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
-                .addr           = 0xe6a30050,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0x83,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
-                .addr           = 0xe6a30060,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0x87,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
-                .addr           = 0xe6a30060,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0x87,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
-                .addr           = 0xe6850030,
-                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xc1,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
-                .addr           = 0xe6850030,
-                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xc2,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
-                .addr           = 0xe6860030,
-                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xc9,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
-                .addr           = 0xe6860030,
-                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xca,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI2_TX,
-                .addr           = 0xe6870030,
-                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xcd,
-        }, {
-                .slave_id       = SHDMA_SLAVE_SDHI2_RX,
-                .addr           = 0xe6870030,
-                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
-                .mid_rid        = 0xce,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FSIA_TX,
-                .addr           = 0xfe1f0024,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xb1,
-        }, {
-                .slave_id       = SHDMA_SLAVE_FSIA_RX,
-                .addr           = 0xfe1f0020,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xb2,
-        }, {
-                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
-                .addr           = 0xe6bd0034,
-                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xd1,
-        }, {
-                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
-                .addr           = 0xe6bd0034,
-                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
-                .mid_rid        = 0xd2,
-        },
-};
-#define SH7372_CHCLR (0x220 - 0x20)
-static const struct sh_dmae_channel sh7372_dmae_channels[] = {
-        {
-                .offset = 0,
-                .dmars = 0,
-                .dmars_bit = 0,
-                .chclr_offset = SH7372_CHCLR + 0,
-        }, {
-                .offset = 0x10,
-                .dmars = 0,
-                .dmars_bit = 8,
-                .chclr_offset = SH7372_CHCLR + 0x10,
-        }, {
-                .offset = 0x20,
-                .dmars = 4,
-                .dmars_bit = 0,
-                .chclr_offset = SH7372_CHCLR + 0x20,
-        }, {
-                .offset = 0x30,
-                .dmars = 4,
-                .dmars_bit = 8,
-                .chclr_offset = SH7372_CHCLR + 0x30,
-        }, {
-                .offset = 0x50,
-                .dmars = 8,
-                .dmars_bit = 0,
-                .chclr_offset = SH7372_CHCLR + 0x50,
-        }, {
-                .offset = 0x60,
-                .dmars = 8,
-                .dmars_bit = 8,
-                .chclr_offset = SH7372_CHCLR + 0x60,
-        }
-};
-static struct sh_dmae_pdata dma_platform_data = {
-        .slave          = sh7372_dmae_slaves,
-        .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
-        .channel        = sh7372_dmae_channels,
-        .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
-        .ts_low_shift   = TS_LOW_SHIFT,
-        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
-        .ts_high_shift  = TS_HI_SHIFT,
-        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
-        .ts_shift       = dma_ts_shift,
-        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
-        .dmaor_init     = DMAOR_DME,
-        .chclr_present  = 1,
-};
-/* Resource order important! */
-static struct resource sh7372_dmae0_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xfe008020,
-                .end    = 0xfe00828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xfe009000,
-                .end    = 0xfe00900b,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "error_irq",
-                .start  = evt2irq(0x20c0),
-                .end    = evt2irq(0x20c0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                /* IRQ for channels 0-5 */
-                .start  = evt2irq(0x2000),
-                .end    = evt2irq(0x20a0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-/* Resource order important! */
-static struct resource sh7372_dmae1_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xfe018020,
-                .end    = 0xfe01828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xfe019000,
-                .end    = 0xfe01900b,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "error_irq",
-                .start  = evt2irq(0x21c0),
-                .end    = evt2irq(0x21c0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                /* IRQ for channels 0-5 */
-                .start  = evt2irq(0x2100),
-                .end    = evt2irq(0x21a0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-/* Resource order important! */
-static struct resource sh7372_dmae2_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xfe028020,
-                .end    = 0xfe02828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xfe029000,
-                .end    = 0xfe02900b,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "error_irq",
-                .start  = evt2irq(0x22c0),
-                .end    = evt2irq(0x22c0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                /* IRQ for channels 0-5 */
-                .start  = evt2irq(0x2200),
-                .end    = evt2irq(0x22a0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device dma0_device = {
-        .name           = "sh-dma-engine",
-        .id             = 0,
-        .resource       = sh7372_dmae0_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
-        .dev            = {
-                .platform_data  = &dma_platform_data,
-        },
-};
-static struct platform_device dma1_device = {
-        .name           = "sh-dma-engine",
-        .id             = 1,
-        .resource       = sh7372_dmae1_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
-        .dev            = {
-                .platform_data  = &dma_platform_data,
-        },
-};
-static struct platform_device dma2_device = {
-        .name           = "sh-dma-engine",
-        .id             = 2,
-        .resource       = sh7372_dmae2_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
-        .dev            = {
-                .platform_data  = &dma_platform_data,
-        },
-};
-/*
- * USB-DMAC
- */
-static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
-        {
-                .offset = 0,
-        }, {
-                .offset = 0x20,
-        },
-};
-/* USB DMAC0 */
-static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
-        {
-                .slave_id       = SHDMA_SLAVE_USB0_TX,
-                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
-        }, {
-                .slave_id       = SHDMA_SLAVE_USB0_RX,
-                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
-        },
-};
-static struct sh_dmae_pdata usb_dma0_platform_data = {
-        .slave          = sh7372_usb_dmae0_slaves,
-        .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
-        .channel        = sh7372_usb_dmae_channels,
-        .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
-        .ts_low_shift   = USBTS_LOW_SHIFT,
-        .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
-        .ts_high_shift  = USBTS_HI_SHIFT,
-        .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
-        .ts_shift       = dma_usbts_shift,
-        .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
-        .dmaor_init     = DMAOR_DME,
-        .chcr_offset    = 0x14,
-        .chcr_ie_bit    = 1 << 5,
-        .dmaor_is_32bit = 1,
-        .needs_tend_set = 1,
-        .no_dmars       = 1,
-        .slave_only     = 1,
-};
-static struct resource sh7372_usb_dmae0_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xe68a0020,
-                .end    = 0xe68a0064 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* VCR/SWR/DMICR */
-                .start  = 0xe68a0000,
-                .end    = 0xe68a0014 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* IRQ for channels */
-                .start  = evt2irq(0x0a00),
-                .end    = evt2irq(0x0a00),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usb_dma0_device = {
-        .name           = "sh-dma-engine",
-        .id             = 3,
-        .resource       = sh7372_usb_dmae0_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
-        .dev            = {
-                .platform_data  = &usb_dma0_platform_data,
-        },
-};
-/* USB DMAC1 */
-static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
-        {
-                .slave_id       = SHDMA_SLAVE_USB1_TX,
-                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
-        }, {
-                .slave_id       = SHDMA_SLAVE_USB1_RX,
-                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
-        },
-};
-static struct sh_dmae_pdata usb_dma1_platform_data = {
-        .slave          = sh7372_usb_dmae1_slaves,
-        .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
-        .channel        = sh7372_usb_dmae_channels,
-        .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
-        .ts_low_shift   = USBTS_LOW_SHIFT,
-        .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
-        .ts_high_shift  = USBTS_HI_SHIFT,
-        .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
-        .ts_shift       = dma_usbts_shift,
-        .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
-        .dmaor_init     = DMAOR_DME,
-        .chcr_offset    = 0x14,
-        .chcr_ie_bit    = 1 << 5,
-        .dmaor_is_32bit = 1,
-        .needs_tend_set = 1,
-        .no_dmars       = 1,
-        .slave_only     = 1,
-};
-static struct resource sh7372_usb_dmae1_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xe68c0020,
-                .end    = 0xe68c0064 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* VCR/SWR/DMICR */
-                .start  = 0xe68c0000,
-                .end    = 0xe68c0014 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* IRQ for channels */
-                .start  = evt2irq(0x1d00),
-                .end    = evt2irq(0x1d00),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usb_dma1_device = {
-        .name           = "sh-dma-engine",
-        .id             = 4,
-        .resource       = sh7372_usb_dmae1_resources,
-        .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
-        .dev            = {
-                .platform_data  = &usb_dma1_platform_data,
-        },
-};
-/* VPU */
-static struct uio_info vpu_platform_data = {
-        .name = "VPU5HG",
-        .version = "0",
-        .irq = intcs_evt2irq(0x980),
-};
-static struct resource vpu_resources[] = {
-        [0] = {
-                .name   = "VPU",
-                .start  = 0xfe900000,
-                .end    = 0xfe900157,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device vpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &vpu_platform_data,
-        },
-        .resource       = vpu_resources,
-        .num_resources  = ARRAY_SIZE(vpu_resources),
-};
-/* VEU0 */
-static struct uio_info veu0_platform_data = {
-        .name = "VEU0",
-        .version = "0",
-        .irq = intcs_evt2irq(0x700),
-};
-static struct resource veu0_resources[] = {
-        [0] = {
-                .name   = "VEU0",
-                .start  = 0xfe920000,
-                .end    = 0xfe9200cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &veu0_platform_data,
-        },
-        .resource       = veu0_resources,
-        .num_resources  = ARRAY_SIZE(veu0_resources),
-};
-/* VEU1 */
-static struct uio_info veu1_platform_data = {
-        .name = "VEU1",
-        .version = "0",
-        .irq = intcs_evt2irq(0x720),
-};
-static struct resource veu1_resources[] = {
-        [0] = {
-                .name   = "VEU1",
-                .start  = 0xfe924000,
-                .end    = 0xfe9240cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &veu1_platform_data,
-        },
-        .resource       = veu1_resources,
-        .num_resources  = ARRAY_SIZE(veu1_resources),
-};
-/* VEU2 */
-static struct uio_info veu2_platform_data = {
-        .name = "VEU2",
-        .version = "0",
-        .irq = intcs_evt2irq(0x740),
-};
-static struct resource veu2_resources[] = {
-        [0] = {
-                .name   = "VEU2",
-                .start  = 0xfe928000,
-                .end    = 0xfe928307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu2_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 3,
-        .dev = {
-                .platform_data  = &veu2_platform_data,
-        },
-        .resource       = veu2_resources,
-        .num_resources  = ARRAY_SIZE(veu2_resources),
-};
-/* VEU3 */
-static struct uio_info veu3_platform_data = {
-        .name = "VEU3",
-        .version = "0",
-        .irq = intcs_evt2irq(0x760),
-};
-static struct resource veu3_resources[] = {
-        [0] = {
-                .name   = "VEU3",
-                .start  = 0xfe92c000,
-                .end    = 0xfe92c307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu3_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 4,
-        .dev = {
-                .platform_data  = &veu3_platform_data,
-        },
-        .resource       = veu3_resources,
-        .num_resources  = ARRAY_SIZE(veu3_resources),
-};
-/* JPU */
-static struct uio_info jpu_platform_data = {
-        .name = "JPU",
-        .version = "0",
-        .irq = intcs_evt2irq(0x560),
-};
-static struct resource jpu_resources[] = {
-        [0] = {
-                .name   = "JPU",
-                .start  = 0xfe980000,
-                .end    = 0xfe9902d3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device jpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 5,
-        .dev = {
-                .platform_data  = &jpu_platform_data,
-        },
-        .resource       = jpu_resources,
-        .num_resources  = ARRAY_SIZE(jpu_resources),
-};
-/* SPU2DSP0 */
-static struct uio_info spu0_platform_data = {
-        .name = "SPU2DSP0",
-        .version = "0",
-        .irq = evt2irq(0x1800),
-};
-static struct resource spu0_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP0",
-                .start  = 0xfe200000,
-                .end    = 0xfe2fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device spu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 6,
-        .dev = {
-                .platform_data  = &spu0_platform_data,
-        },
-        .resource       = spu0_resources,
-        .num_resources  = ARRAY_SIZE(spu0_resources),
-};
-/* SPU2DSP1 */
-static struct uio_info spu1_platform_data = {
-        .name = "SPU2DSP1",
-        .version = "0",
-        .irq = evt2irq(0x1820),
-};
-static struct resource spu1_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP1",
-                .start  = 0xfe300000,
-                .end    = 0xfe3fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device spu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 7,
-        .dev = {
-                .platform_data  = &spu1_platform_data,
-        },
-        .resource       = spu1_resources,
-        .num_resources  = ARRAY_SIZE(spu1_resources),
-};
-/* IPMMUI (an IPMMU module for ICB/LMB) */
-static struct resource ipmmu_resources[] = {
-        [0] = {
-                .name   = "IPMMUI",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static const char * const ipmmu_dev_names[] = {
-        "sh_mobile_lcdc_fb.0",
-        "sh_mobile_lcdc_fb.1",
-        "sh_mobile_ceu.0",
-        "uio_pdrv_genirq.0",
-        "uio_pdrv_genirq.1",
-        "uio_pdrv_genirq.2",
-        "uio_pdrv_genirq.3",
-        "uio_pdrv_genirq.4",
-        "uio_pdrv_genirq.5",
-};
-static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
-        .dev_names = ipmmu_dev_names,
-        .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
-};
-static struct platform_device ipmmu_device = {
-        .name           = "ipmmu",
-        .id             = -1,
-        .dev = {
-                .platform_data = &ipmmu_platform_data,
-        },
-        .resource       = ipmmu_resources,
-        .num_resources  = ARRAY_SIZE(ipmmu_resources),
-};
-static struct platform_device *sh7372_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
-        &scif2_device,
-        &scif3_device,
-        &scif4_device,
-        &scif5_device,
-        &scif6_device,
-        &cmt2_device,
-        &tmu0_device,
-        &ipmmu_device,
-};
-static struct platform_device *sh7372_late_devices[] __initdata = {
-        &iic0_device,
-        &iic1_device,
-        &dma0_device,
-        &dma1_device,
-        &dma2_device,
-        &usb_dma0_device,
-        &usb_dma1_device,
-        &vpu_device,
-        &veu0_device,
-        &veu1_device,
-        &veu2_device,
-        &veu3_device,
-        &jpu_device,
-        &spu0_device,
-        &spu1_device,
-};
-void __init sh7372_add_standard_devices(void)
-{
-        static struct pm_domain_device domain_devices[] __initdata = {
-                { "A3RV", &vpu_device, },
-                { "A4MP", &spu0_device, },
-                { "A4MP", &spu1_device, },
-                { "A3SP", &scif0_device, },
-                { "A3SP", &scif1_device, },
-                { "A3SP", &scif2_device, },
-                { "A3SP", &scif3_device, },
-                { "A3SP", &scif4_device, },
-                { "A3SP", &scif5_device, },
-                { "A3SP", &scif6_device, },
-                { "A3SP", &iic1_device, },
-                { "A3SP", &dma0_device, },
-                { "A3SP", &dma1_device, },
-                { "A3SP", &dma2_device, },
-                { "A3SP", &usb_dma0_device, },
-                { "A3SP", &usb_dma1_device, },
-                { "A4R", &iic0_device, },
-                { "A4R", &veu0_device, },
-                { "A4R", &veu1_device, },
-                { "A4R", &veu2_device, },
-                { "A4R", &veu3_device, },
-                { "A4R", &jpu_device, },
-                { "A4R", &tmu0_device, },
-        };
-        sh7372_init_pm_domains();
-        platform_add_devices(sh7372_early_devices,
-                            ARRAY_SIZE(sh7372_early_devices));
-        platform_add_devices(sh7372_late_devices,
-                            ARRAY_SIZE(sh7372_late_devices));
-        rmobile_add_devices_to_domains(domain_devices,
-                                       ARRAY_SIZE(domain_devices));
-}
-void __init sh7372_earlytimer_init(void)
-{
-        sh7372_clock_init();
-        shmobile_earlytimer_init();
-}
-void __init sh7372_add_early_devices(void)
-{
-        early_platform_add_devices(sh7372_early_devices,
-                                   ARRAY_SIZE(sh7372_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-#ifdef CONFIG_USE_OF
-void __init sh7372_add_early_devices_dt(void)
-{
-        shmobile_init_delay();
-        sh7372_add_early_devices();
-}
-void __init sh7372_add_standard_devices_dt(void)
-{
-        /* clocks are setup late during boot in the case of DT */
-        sh7372_clock_init();
-        platform_add_devices(sh7372_early_devices,
-                            ARRAY_SIZE(sh7372_early_devices));
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char *sh7372_boards_compat_dt[] __initdata = {
-        "renesas,sh7372",
-        NULL,
-};
-DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
-        .map_io         = sh7372_map_io,
-        .init_early     = sh7372_add_early_devices_dt,
-        .init_irq       = sh7372_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = sh7372_add_standard_devices_dt,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = sh7372_boards_compat_dt,
-MACHINE_END
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index faea74a2151b..fb2ab7590af8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -30,6 +30,7 @@
 #include <linux/platform_data/sh_ipmmu.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -784,22 +785,15 @@ void __init sh73a0_add_early_devices(void)
 #ifdef CONFIG_USE_OF
-void __init sh73a0_add_standard_devices_dt(void)
+static void __init sh73a0_generic_init(void)
 {
-        /* clocks are setup late during boot in the case of DT */
+#ifdef CONFIG_CACHE_L2X0
-#ifndef CONFIG_COMMON_CLK
+        /* Shared attribute override enable, 64K*8way */
-        sh73a0_clock_init();
+        l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 #endif
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-#define RESCNT2 IOMEM(0xe6188020)
-static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
-{
-        /* Do soft power on reset */
-        writel((1 << 31), RESCNT2);
-}
 static const char *sh73a0_boards_compat_dt[] __initdata = {
        "renesas,sh73a0",
        NULL,
@@ -809,9 +803,8 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
        .smp            = smp_ops(sh73a0_smp_ops),
        .map_io         = sh73a0_map_io,
        .init_early     = shmobile_init_delay,
-        .init_machine   = sh73a0_add_standard_devices_dt,
+        .init_machine   = sh73a0_generic_init,
        .init_late      = shmobile_init_late,
-        .restart        = sh73a0_restart,
        .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sh7372.h b/arch/arm/mach-shmobile/sh7372.h
deleted file mode 100644
index 4ad960d5075b..000000000000
--- a/arch/arm/mach-shmobile/sh7372.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2010 Renesas Solutions Corp.
- *
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_SH7372_H__
-#define __ASM_SH7372_H__
-/* DMA slave IDs */
-enum {
-        SHDMA_SLAVE_INVALID,
-        SHDMA_SLAVE_SCIF0_TX,
-        SHDMA_SLAVE_SCIF0_RX,
-        SHDMA_SLAVE_SCIF1_TX,
-        SHDMA_SLAVE_SCIF1_RX,
-        SHDMA_SLAVE_SCIF2_TX,
-        SHDMA_SLAVE_SCIF2_RX,
-        SHDMA_SLAVE_SCIF3_TX,
-        SHDMA_SLAVE_SCIF3_RX,
-        SHDMA_SLAVE_SCIF4_TX,
-        SHDMA_SLAVE_SCIF4_RX,
-        SHDMA_SLAVE_SCIF5_TX,
-        SHDMA_SLAVE_SCIF5_RX,
-        SHDMA_SLAVE_SCIF6_TX,
-        SHDMA_SLAVE_SCIF6_RX,
-        SHDMA_SLAVE_FLCTL0_TX,
-        SHDMA_SLAVE_FLCTL0_RX,
-        SHDMA_SLAVE_FLCTL1_TX,
-        SHDMA_SLAVE_FLCTL1_RX,
-        SHDMA_SLAVE_SDHI0_RX,
-        SHDMA_SLAVE_SDHI0_TX,
-        SHDMA_SLAVE_SDHI1_RX,
-        SHDMA_SLAVE_SDHI1_TX,
-        SHDMA_SLAVE_SDHI2_RX,
-        SHDMA_SLAVE_SDHI2_TX,
-        SHDMA_SLAVE_FSIA_RX,
-        SHDMA_SLAVE_FSIA_TX,
-        SHDMA_SLAVE_MMCIF_RX,
-        SHDMA_SLAVE_MMCIF_TX,
-        SHDMA_SLAVE_USB0_TX,
-        SHDMA_SLAVE_USB0_RX,
-        SHDMA_SLAVE_USB1_TX,
-        SHDMA_SLAVE_USB1_RX,
-};
-extern struct clk sh7372_extal1_clk;
-extern struct clk sh7372_extal2_clk;
-extern struct clk sh7372_dv_clki_clk;
-extern struct clk sh7372_dv_clki_div2_clk;
-extern struct clk sh7372_pllc2_clk;
-extern void sh7372_init_irq(void);
-extern void sh7372_map_io(void);
-extern void sh7372_earlytimer_init(void);
-extern void sh7372_add_early_devices(void);
-extern void sh7372_add_standard_devices(void);
-extern void sh7372_add_early_devices_dt(void);
-extern void sh7372_add_standard_devices_dt(void);
-extern void sh7372_clock_init(void);
-extern void sh7372_pinmux_init(void);
-extern void sh7372_pm_init(void);
-extern void sh7372_resume_core_standby_sysc(void);
-extern int  sh7372_do_idle_sysc(unsigned long sleep_mode);
-extern void sh7372_intcs_suspend(void);
-extern void sh7372_intcs_resume(void);
-extern void sh7372_intca_suspend(void);
-extern void sh7372_intca_resume(void);
-extern unsigned long sh7372_cpu_resume;
-#ifdef CONFIG_PM
-extern void __init sh7372_init_pm_domains(void);
-#else
-static inline void sh7372_init_pm_domains(void) {}
-#endif
-extern void __init sh7372_pm_init_late(void);
-#endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h
index f037c64b14fc..5a80f18b4fa0 100644
--- a/arch/arm/mach-shmobile/sh73a0.h
+++ b/arch/arm/mach-shmobile/sh73a0.h
@@ -77,7 +77,6 @@ extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
 extern void sh73a0_add_standard_devices(void);
-extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
deleted file mode 100644
index 146b8de16432..000000000000
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * sh7372 lowlevel sleep code for "Core Standby Mode"
- *
- * Copyright (C) 2011 Magnus Damm
- *
- * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
- *
- * Based on mach-omap2/sleep34xx.S
- *
- * (C) Copyright 2007 Texas Instruments
- * Karthik Dasu <karthik-dp@ti.com>
- *
- * (C) Copyright 2004 Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/memory.h>
-#include <asm/assembler.h>
-#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
-        .align  12
-        .text
-        .global sh7372_resume_core_standby_sysc
-sh7372_resume_core_standby_sysc:
-        ldr     pc, 1f
-        .align  2
-        .globl  sh7372_cpu_resume
-sh7372_cpu_resume:
-1:      .space  4
-#define SPDCR 0xe6180008
-        /* A3SM & A4S power down */
-        .global sh7372_do_idle_sysc
-sh7372_do_idle_sysc:
-        mov     r8, r0 /* sleep mode passed in r0 */
-        /*
-         * Clear the SCTLR.C bit to prevent further data cache
-         * allocation. Clearing SCTLR.C would make all the data accesses
-         * strongly ordered and would not hit the cache.
-         */
-        mrc     p15, 0, r0, c1, c0, 0
-        bic     r0, r0, #(1 << 2)       @ Disable the C bit
-        mcr     p15, 0, r0, c1, c0, 0
-        isb
-        /*
-         * Clean and invalidate data cache again.
-         */
-        ldr     r1, kernel_flush
-        blx     r1
-        /* disable L2 cache in the aux control register */
-        mrc     p15, 0, r10, c1, c0, 1
-        bic     r10, r10, #2
-        mcr     p15, 0, r10, c1, c0, 1
-        isb
-        /*
-         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
-         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
-         * This sequence switches back to ARM.  Note that .align may insert a
-         * nop: bx pc needs to be word-aligned in order to work.
-         */
- THUMB( .thumb          )
- THUMB( .align          )
- THUMB( bx      pc      )
- THUMB( nop             )
-        .arm
-        /* Data memory barrier and Data sync barrier */
-        dsb
-        dmb
-        /* SYSC power down */
-        ldr     r0, =SPDCR
-        str     r8, [r0]
-1:
-        b      1b
-        .align  2
-kernel_flush:
-        .word v7_flush_dcache_all
-#endif
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 9fc280e24ef4..01f792fcb220 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -124,19 +124,12 @@ static int r8a7779_cpu_kill(unsigned int cpu)
        return 0;
 }
-static int r8a7779_cpu_disable(unsigned int cpu)
-{
-        /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
-        return cpu == 0 ? -EPERM : 0;
-}
 #endif /* CONFIG_HOTPLUG_CPU */
 struct smp_operations r8a7779_smp_ops  __initdata = {
        .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
        .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
-        .cpu_disable            = r8a7779_cpu_disable,
        .cpu_die                = shmobile_smp_scu_cpu_die,
        .cpu_kill               = r8a7779_cpu_kill,
 #endif
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 9c3da1345b8b..930f45cbc08a 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -23,6 +23,7 @@
 #include "common.h"
 #include "platsmp-apmu.h"
 #include "pm-rcar.h"
+#include "rcar-gen2.h"
 #include "r8a7790.h"
 static struct rcar_sysc_ch r8a7790_ca15_scu = {
@@ -37,11 +38,11 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
 static struct rcar_apmu_config r8a7790_apmu_config[] = {
        {
-                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
                .cpus = { 0, 1, 2, 3 },
        },
        {
-                .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6151000, 0x188),
                .cpus = { 0x100, 0x0101, 0x102, 0x103 },
        }
 };
@@ -54,7 +55,7 @@ static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
                                       ARRAY_SIZE(r8a7790_apmu_config));
        /* turn on power to SCU */
-        r8a7790_pm_init();
+        rcar_gen2_pm_init();
        rcar_sysc_power_up(&r8a7790_ca15_scu);
        rcar_sysc_power_up(&r8a7790_ca7_scu);
 }
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 7e49e0a52e32..5e2d1db79afa 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -27,7 +27,7 @@
 static struct rcar_apmu_config r8a7791_apmu_config[] = {
        {
-                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
                .cpus = { 0, 1 },
        }
 };
@@ -39,7 +39,7 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
                                       r8a7791_apmu_config,
                                       ARRAY_SIZE(r8a7791_apmu_config));
-        r8a7791_pm_init();
+        rcar_gen2_pm_init();
 }
 static int r8a7791_smp_boot_secondary(unsigned int cpu,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index c16dbfe9836c..2106d6b76a06 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -33,7 +33,7 @@
 #define SH73A0_SCU_BASE 0xf0000000
-#ifdef CONFIG_HAVE_ARM_TWD
+#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 4be537977040..10f9389572da 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -54,7 +54,7 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 config ARCH_VEXPRESS_DCSCB
        bool "Dual Cluster System Control Block (DCSCB) support"
        depends on MCPM
-        select ARM_CCI
+        select ARM_CCI400_PORT_CTRL
        help
          Support for the Dual Cluster System Configuration Block (DCSCB).
          This is needed to provide CPU and cluster power management
@@ -72,7 +72,7 @@ config ARCH_VEXPRESS_SPC
 config ARCH_VEXPRESS_TC2_PM
        bool "Versatile Express TC2 power management"
        depends on MCPM
-        select ARM_CCI
+        select ARM_CCI400_PORT_CTRL
        select ARCH_VEXPRESS_SPC
        select ARM_CPU_SUSPEND
        help
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 30b993399ed7..5cedcf572104 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/spinlock.h>
 #include <linux/errno.h>
 #include <linux/of_address.h>
 #include <linux/vexpress.h>
@@ -36,163 +35,102 @@
 #define KFC_CFG_W       0x2c
 #define DCS_CFG_R       0x30
-/*
- * We can't use regular spinlocks. In the switcher case, it is possible
- * for an outbound CPU to call power_down() while its inbound counterpart
- * is already live using the same logical CPU number which trips lockdep
- * debugging.
- */
-static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 static void __iomem *dcscb_base;
-static int dcscb_use_count[4][2];
 static int dcscb_allcpus_mask[2];
-static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
+static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
 {
        unsigned int rst_hold, cpumask = (1 << cpu);
-        unsigned int all_mask;
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
-        if (cpu >= 4 || cluster >= 2)
+        if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
                return -EINVAL;
-        all_mask = dcscb_allcpus_mask[cluster];
+        rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+        rst_hold &= ~(cpumask | (cpumask << 4));
+        writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        return 0;
+}
-        /*
+static int dcscb_cluster_powerup(unsigned int cluster)
-         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+{
-         * variant exists, we need to disable IRQs manually here.
+        unsigned int rst_hold;
-         */
-        local_irq_disable();
-        arch_spin_lock(&dcscb_lock);
-        dcscb_use_count[cpu][cluster]++;
-        if (dcscb_use_count[cpu][cluster] == 1) {
-                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
-                if (rst_hold & (1 << 8)) {
-                        /* remove cluster reset and add individual CPU's reset */
-                        rst_hold &= ~(1 << 8);
-                        rst_hold |= all_mask;
-                }
-                rst_hold &= ~(cpumask | (cpumask << 4));
-                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
-        } else if (dcscb_use_count[cpu][cluster] != 2) {
-                /*
-                 * The only possible values are:
-                 * 0 = CPU down
-                 * 1 = CPU (still) up
-                 * 2 = CPU requested to be up before it had a chance
-                 *     to actually make itself down.
-                 * Any other value is a bug.
-                 */
-                BUG();
-        }
-        arch_spin_unlock(&dcscb_lock);
+        pr_debug("%s: cluster %u\n", __func__, cluster);
-        local_irq_enable();
+        if (cluster >= 2)
+                return -EINVAL;
+        /* remove cluster reset and add individual CPU's reset */
+        rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+        rst_hold &= ~(1 << 8);
+        rst_hold |= dcscb_allcpus_mask[cluster];
+        writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
        return 0;
 }
-static void dcscb_power_down(void)
+static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
 {
-        unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
+        unsigned int rst_hold;
-        bool last_man = false, skip_wfi = false;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        cpumask = (1 << cpu);
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
-        BUG_ON(cpu >= 4 || cluster >= 2);
+        BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
-        all_mask = dcscb_allcpus_mask[cluster];
-        __mcpm_cpu_going_down(cpu, cluster);
-        arch_spin_lock(&dcscb_lock);
-        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
-        dcscb_use_count[cpu][cluster]--;
-        if (dcscb_use_count[cpu][cluster] == 0) {
-                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
-                rst_hold |= cpumask;
-                if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
-                        rst_hold |= (1 << 8);
-                        last_man = true;
-                }
-                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
-        } else if (dcscb_use_count[cpu][cluster] == 1) {
-                /*
-                 * A power_up request went ahead of us.
-                 * Even if we do not want to shut this CPU down,
-                 * the caller expects a certain state as if the WFI
-                 * was aborted.  So let's continue with cache cleaning.
-                 */
-                skip_wfi = true;
-        } else
-                BUG();
-        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
-                arch_spin_unlock(&dcscb_lock);
-                /* Flush all cache levels for this cluster. */
-                v7_exit_coherency_flush(all);
-                /*
-                 * A full outer cache flush could be needed at this point
-                 * on platforms with such a cache, depending on where the
-                 * outer cache sits. In some cases the notion of a "last
-                 * cluster standing" would need to be implemented if the
-                 * outer cache is shared across clusters. In any case, when
-                 * the outer cache needs flushing, there is no concurrent
-                 * access to the cache controller to worry about and no
-                 * special locking besides what is already provided by the
-                 * MCPM state machinery is needed.
-                 */
-                /*
-                 * Disable cluster-level coherency by masking
-                 * incoming snoops and DVM messages:
-                 */
-                cci_disable_port_by_cpu(mpidr);
-                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
-        } else {
-                arch_spin_unlock(&dcscb_lock);
-                /* Disable and flush the local CPU cache. */
-                v7_exit_coherency_flush(louis);
-        }
-        __mcpm_cpu_down(cpu, cluster);
+        rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+        rst_hold |= (1 << cpu);
+        writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+}
-        /* Now we are prepared for power-down, do it: */
+static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
-        dsb();
+{
-        if (!skip_wfi)
+        unsigned int rst_hold;
-                wfi();
-        /* Not dead at this point?  Let our caller cope. */
+        pr_debug("%s: cluster %u\n", __func__, cluster);
+        BUG_ON(cluster >= 2);
+        rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+        rst_hold |= (1 << 8);
+        writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
 }
-static const struct mcpm_platform_ops dcscb_power_ops = {
+static void dcscb_cpu_cache_disable(void)
-        .power_up       = dcscb_power_up,
+{
-        .power_down     = dcscb_power_down,
+        /* Disable and flush the local CPU cache. */
-};
+        v7_exit_coherency_flush(louis);
+}
-static void __init dcscb_usage_count_init(void)
+static void dcscb_cluster_cache_disable(void)
 {
-        unsigned int mpidr, cpu, cluster;
+        /* Flush all cache levels for this cluster. */
+        v7_exit_coherency_flush(all);
-        mpidr = read_cpuid_mpidr();
+        /*
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+         * A full outer cache flush could be needed at this point
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+         * on platforms with such a cache, depending on where the
+         * outer cache sits. In some cases the notion of a "last
+         * cluster standing" would need to be implemented if the
+         * outer cache is shared across clusters. In any case, when
+         * the outer cache needs flushing, there is no concurrent
+         * access to the cache controller to worry about and no
+         * special locking besides what is already provided by the
+         * MCPM state machinery is needed.
+         */
-        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        /*
-        BUG_ON(cpu >= 4 || cluster >= 2);
+         * Disable cluster-level coherency by masking
-        dcscb_use_count[cpu][cluster] = 1;
+         * incoming snoops and DVM messages:
+         */
+        cci_disable_port_by_cpu(read_cpuid_mpidr());
 }
+static const struct mcpm_platform_ops dcscb_power_ops = {
+        .cpu_powerup            = dcscb_cpu_powerup,
+        .cluster_powerup        = dcscb_cluster_powerup,
+        .cpu_powerdown_prepare  = dcscb_cpu_powerdown_prepare,
+        .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
+        .cpu_cache_disable      = dcscb_cpu_cache_disable,
+        .cluster_cache_disable  = dcscb_cluster_cache_disable,
+};
 extern void dcscb_power_up_setup(unsigned int affinity_level);
 static int __init dcscb_init(void)
@@ -213,7 +151,6 @@ static int __init dcscb_init(void)
        cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
        dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
        dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
-        dcscb_usage_count_init();
        ret = mcpm_platform_register(&dcscb_power_ops);
        if (!ret)
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 2fb78b4648cb..b3328cd46c33 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/spinlock.h>
 #include <linux/errno.h>
 #include <linux/irqchip/arm-gic.h>
@@ -44,101 +43,36 @@
 static void __iomem *scc;
-/*
- * We can't use regular spinlocks. In the switcher case, it is possible
- * for an outbound CPU to call power_down() after its inbound counterpart
- * is already live using the same logical CPU number which trips lockdep
- * debugging.
- */
-static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 #define TC2_CLUSTERS                    2
 #define TC2_MAX_CPUS_PER_CLUSTER        3
 static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
-/* Keep per-cpu usage count to cope with unordered up/down requests */
+static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
-static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
-#define tc2_cluster_unused(cluster) \
-        (!tc2_pm_use_count[0][cluster] && \
-         !tc2_pm_use_count[1][cluster] && \
-         !tc2_pm_use_count[2][cluster])
-static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
 {
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
                return -EINVAL;
+        ve_spc_set_resume_addr(cluster, cpu,
-        /*
+                               virt_to_phys(mcpm_entry_point));
-         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+        ve_spc_cpu_wakeup_irq(cluster, cpu, true);
-         * variant exists, we need to disable IRQs manually here.
-         */
-        local_irq_disable();
-        arch_spin_lock(&tc2_pm_lock);
-        if (tc2_cluster_unused(cluster))
-                ve_spc_powerdown(cluster, false);
-        tc2_pm_use_count[cpu][cluster]++;
-        if (tc2_pm_use_count[cpu][cluster] == 1) {
-                ve_spc_set_resume_addr(cluster, cpu,
-                                       virt_to_phys(mcpm_entry_point));
-                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
-        } else if (tc2_pm_use_count[cpu][cluster] != 2) {
-                /*
-                 * The only possible values are:
-                 * 0 = CPU down
-                 * 1 = CPU (still) up
-                 * 2 = CPU requested to be up before it had a chance
-                 *     to actually make itself down.
-                 * Any other value is a bug.
-                 */
-                BUG();
-        }
-        arch_spin_unlock(&tc2_pm_lock);
-        local_irq_enable();
        return 0;
 }
-static void tc2_pm_down(u64 residency)
+static int tc2_pm_cluster_powerup(unsigned int cluster)
 {
-        unsigned int mpidr, cpu, cluster;
+        pr_debug("%s: cluster %u\n", __func__, cluster);
-        bool last_man = false, skip_wfi = false;
+        if (cluster >= TC2_CLUSTERS)
+                return -EINVAL;
-        mpidr = read_cpuid_mpidr();
+        ve_spc_powerdown(cluster, false);
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        return 0;
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+}
+static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
+{
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+        ve_spc_cpu_wakeup_irq(cluster, cpu, true);
-        __mcpm_cpu_going_down(cpu, cluster);
-        arch_spin_lock(&tc2_pm_lock);
-        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
-        tc2_pm_use_count[cpu][cluster]--;
-        if (tc2_pm_use_count[cpu][cluster] == 0) {
-                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
-                if (tc2_cluster_unused(cluster)) {
-                        ve_spc_powerdown(cluster, true);
-                        ve_spc_global_wakeup_irq(true);
-                        last_man = true;
-                }
-        } else if (tc2_pm_use_count[cpu][cluster] == 1) {
-                /*
-                 * A power_up request went ahead of us.
-                 * Even if we do not want to shut this CPU down,
-                 * the caller expects a certain state as if the WFI
-                 * was aborted.  So let's continue with cache cleaning.
-                 */
-                skip_wfi = true;
-        } else
-                BUG();
        /*
         * If the CPU is committed to power down, make sure
         * the power controller will be in charge of waking it
@@ -146,55 +80,38 @@ static void tc2_pm_down(u64 residency)
         * to the CPU by disabling the GIC CPU IF to prevent wfi
         * from completing execution behind power controller back
         */
-        if (!skip_wfi)
+        gic_cpu_if_down();
-                gic_cpu_if_down();
+}
-        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
-                arch_spin_unlock(&tc2_pm_lock);
-                if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
-                        /*
-                         * On the Cortex-A15 we need to disable
-                         * L2 prefetching before flushing the cache.
-                         */
-                        asm volatile(
-                        "mcr    p15, 1, %0, c15, c0, 3 \n\t"
-                        "isb    \n\t"
-                        "dsb    "
-                        : : "r" (0x400) );
-                }
-                v7_exit_coherency_flush(all);
-                cci_disable_port_by_cpu(mpidr);
-                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
-        } else {
-                /*
-                 * If last man then undo any setup done previously.
-                 */
-                if (last_man) {
-                        ve_spc_powerdown(cluster, false);
-                        ve_spc_global_wakeup_irq(false);
-                }
-                arch_spin_unlock(&tc2_pm_lock);
-                v7_exit_coherency_flush(louis);
-        }
-        __mcpm_cpu_down(cpu, cluster);
-        /* Now we are prepared for power-down, do it: */
+static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)
-        if (!skip_wfi)
+{
-                wfi();
+        pr_debug("%s: cluster %u\n", __func__, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS);
+        ve_spc_powerdown(cluster, true);
+        ve_spc_global_wakeup_irq(true);
+}
-        /* Not dead at this point?  Let our caller cope. */
+static void tc2_pm_cpu_cache_disable(void)
+{
+        v7_exit_coherency_flush(louis);
 }
-static void tc2_pm_power_down(void)
+static void tc2_pm_cluster_cache_disable(void)
 {
-        tc2_pm_down(0);
+        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
+                /*
+                 * On the Cortex-A15 we need to disable
+                 * L2 prefetching before flushing the cache.
+                 */
+                asm volatile(
+                "mcr    p15, 1, %0, c15, c0, 3 \n\t"
+                "isb    \n\t"
+                "dsb    "
+                : : "r" (0x400) );
+        }
+        v7_exit_coherency_flush(all);
+        cci_disable_port_by_cpu(read_cpuid_mpidr());
 }
 static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
@@ -217,27 +134,21 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
        for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
+                pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
+                         __func__, cpu, cluster,
+                         readl_relaxed(scc + RESET_CTRL));
                /*
-                 * Only examine the hardware state if the target CPU has
+                 * We need the CPU to reach WFI, but the power
-                 * caught up at least as far as tc2_pm_down():
+                 * controller may put the cluster in reset and
+                 * power it off as soon as that happens, before
+                 * we have a chance to see STANDBYWFI.
+                 *
+                 * So we need to check for both conditions:
                 */
-                if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) {
+                if (tc2_core_in_reset(cpu, cluster) ||
-                        pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
+                    ve_spc_cpu_in_wfi(cpu, cluster))
-                                 __func__, cpu, cluster,
+                        return 0; /* success: the CPU is halted */
-                                 readl_relaxed(scc + RESET_CTRL));
-                        /*
-                         * We need the CPU to reach WFI, but the power
-                         * controller may put the cluster in reset and
-                         * power it off as soon as that happens, before
-                         * we have a chance to see STANDBYWFI.
-                         *
-                         * So we need to check for both conditions:
-                         */
-                        if (tc2_core_in_reset(cpu, cluster) ||
-                            ve_spc_cpu_in_wfi(cpu, cluster))
-                                return 0; /* success: the CPU is halted */
-                }
                /* Otherwise, wait and retry: */
                msleep(POLL_MSEC);
@@ -246,72 +157,40 @@ static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
        return -ETIMEDOUT; /* timeout */
 }
-static void tc2_pm_suspend(u64 residency)
+static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
 {
-        unsigned int mpidr, cpu, cluster;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
        ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
-        tc2_pm_down(residency);
 }
-static void tc2_pm_powered_up(void)
+static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
 {
-        unsigned int mpidr, cpu, cluster;
-        unsigned long flags;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
-        local_irq_save(flags);
-        arch_spin_lock(&tc2_pm_lock);
-        if (tc2_cluster_unused(cluster)) {
-                ve_spc_powerdown(cluster, false);
-                ve_spc_global_wakeup_irq(false);
-        }
-        if (!tc2_pm_use_count[cpu][cluster])
-                tc2_pm_use_count[cpu][cluster] = 1;
        ve_spc_cpu_wakeup_irq(cluster, cpu, false);
        ve_spc_set_resume_addr(cluster, cpu, 0);
+}
-        arch_spin_unlock(&tc2_pm_lock);
+static void tc2_pm_cluster_is_up(unsigned int cluster)
-        local_irq_restore(flags);
+{
+        pr_debug("%s: cluster %u\n", __func__, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS);
+        ve_spc_powerdown(cluster, false);
+        ve_spc_global_wakeup_irq(false);
 }
 static const struct mcpm_platform_ops tc2_pm_power_ops = {
-        .power_up               = tc2_pm_power_up,
+        .cpu_powerup            = tc2_pm_cpu_powerup,
-        .power_down             = tc2_pm_power_down,
+        .cluster_powerup        = tc2_pm_cluster_powerup,
+        .cpu_suspend_prepare    = tc2_pm_cpu_suspend_prepare,
+        .cpu_powerdown_prepare  = tc2_pm_cpu_powerdown_prepare,
+        .cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare,
+        .cpu_cache_disable      = tc2_pm_cpu_cache_disable,
+        .cluster_cache_disable  = tc2_pm_cluster_cache_disable,
        .wait_for_powerdown     = tc2_pm_wait_for_powerdown,
-        .suspend                = tc2_pm_suspend,
+        .cpu_is_up              = tc2_pm_cpu_is_up,
-        .powered_up             = tc2_pm_powered_up,
+        .cluster_is_up          = tc2_pm_cluster_is_up,
 };
-static bool __init tc2_pm_usage_count_init(void)
-{
-        unsigned int mpidr, cpu, cluster;
-        mpidr = read_cpuid_mpidr();
-        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
-        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
-                pr_err("%s: boot CPU is out of bound!\n", __func__);
-                return false;
-        }
-        tc2_pm_use_count[cpu][cluster] = 1;
-        return true;
-}
 /*
 * Enable cluster-level coherency, in preparation for turning on the MMU.
 */
@@ -323,23 +202,9 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
 "       b       cci_enable_port_for_self ");
 }
-static void __init tc2_cache_off(void)
-{
-        pr_info("TC2: disabling cache during MCPM loopback test\n");
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
-                /* disable L2 prefetching on the Cortex-A15 */
-                asm volatile(
-                "mcr    p15, 1, %0, c15, c0, 3 \n\t"
-                "isb    \n\t"
-                "dsb    "
-                : : "r" (0x400) );
-        }
-        v7_exit_coherency_flush(all);
-        cci_disable_port_by_cpu(read_cpuid_mpidr());
-}
 static int __init tc2_pm_init(void)
 {
+        unsigned int mpidr, cpu, cluster;
        int ret, irq;
        u32 a15_cluster_id, a7_cluster_id, sys_info;
        struct device_node *np;
@@ -379,14 +244,20 @@ static int __init tc2_pm_init(void)
        if (!cci_probed())
                return -ENODEV;
-        if (!tc2_pm_usage_count_init())
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
+                pr_err("%s: boot CPU is out of bound!\n", __func__);
                return -EINVAL;
+        }
        ret = mcpm_platform_register(&tc2_pm_power_ops);
        if (!ret) {
                mcpm_sync_init(tc2_pm_power_up_setup);
                /* test if we can (re)enable the CCI on our own */
-                BUG_ON(mcpm_loopback(tc2_cache_off) != 0);
+                BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0);
                pr_info("TC2 power management initialized\n");
        }
        return ret;
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index e17d871b934c..7f415ce74591 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -43,7 +43,11 @@ extern unsigned long s3c_irqwake_eintmask;
 /* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
 extern unsigned long s3c_irqwake_intallow;
+#ifdef CONFIG_PM_SLEEP
 extern unsigned long s3c_irqwake_eintallow;
+#else
+#define s3c_irqwake_eintallow 0
+#endif
 /* per-cpu sleep functions */
@@ -58,16 +62,20 @@ extern unsigned long s3c_pm_flags;
 extern int s3c2410_cpu_suspend(unsigned long);
-#ifdef CONFIG_SAMSUNG_PM
+#ifdef CONFIG_PM_SLEEP
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
-extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
 extern void s3c_cpu_resume(void);
 #else
 #define s3c_irq_wake NULL
-#define s3c_irqext_wake NULL
 #define s3c_cpu_resume NULL
 #endif
+#ifdef CONFIG_SAMSUNG_PM
+extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
+#else
+#define s3c_irqext_wake NULL
+#endif
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 /**
 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
index 39609601f407..64e15da33b42 100644
--- a/arch/arm/plat-samsung/pm-debug.c
+++ b/arch/arm/plat-samsung/pm-debug.c
@@ -23,6 +23,7 @@
 #include <plat/pm-common.h>
 #ifdef CONFIG_SAMSUNG_ATAGS
+#include <plat/pm.h>
 #include <mach/pm-core.h>
 #else
 static inline void s3c_pm_debug_init_uart(void) {}
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index f8c0f9797dcf..82777c649774 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -65,26 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state)
        return 0;
 }
-/* s3c2410_pm_show_resume_irqs
- *
- * print any IRQs asserted at resume time (ie, we woke from)
-*/
-static void __maybe_unused s3c_pm_show_resume_irqs(int start,
-                                                   unsigned long which,
-                                                   unsigned long mask)
-{
-        int i;
-        which &= ~mask;
-        for (i = 0; i <= 31; i++) {
-                if (which & (1L<<i)) {
-                        S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
-                }
-        }
-}
 void (*pm_cpu_prep)(void);
 int (*pm_cpu_sleep)(unsigned long);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index a10297da122b..2ed1b8a922ed 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -526,7 +526,6 @@ ag5evm			MACH_AG5EVM		AG5EVM			3189
 ics_if_voip             MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
 wlf_cragg_6410          MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
 trimslice               MACH_TRIMSLICE          TRIMSLICE               3209
-mackerel                MACH_MACKEREL           MACKEREL                3211
 kaen                    MACH_KAEN               KAEN                    3217
 nokia_rm680             MACH_NOKIA_RM680        NOKIA_RM680             3220
 msm8960_sim             MACH_MSM8960_SIM        MSM8960_SIM             3230