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-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts58
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts50
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi449
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts53
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts2
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/mach-tegra/Makefile.boot3
8 files changed, 617 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000000..a2d6d6541f83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903";
12 reg = <0x1a>;
13 interrupt-parent = <&gpio>;
14 interrupts = <187 0x04>;
15
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 micdet-cfg = <0>;
20 micdet-delay = <100>;
21 gpio-cfg = <0xffffffff
22 0xffffffff
23 0
24 0xffffffff
25 0xffffffff>;
26 };
27 };
28
29 backlight {
30 compatible = "pwm-backlight";
31 pwms = <&pwm 0 5000000>;
32
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <6>;
35 };
36
37 sound {
38 compatible = "ad,tegra-audio-wm8903-medcom-wide",
39 "nvidia,tegra-audio-wm8903";
40 nvidia,model = "Avionic Design Medcom-Wide";
41
42 nvidia,audio-routing =
43 "Headphone Jack", "HPOUTR",
44 "Headphone Jack", "HPOUTL",
45 "Int Spk", "ROP",
46 "Int Spk", "RON",
47 "Int Spk", "LOP",
48 "Int Spk", "LON",
49 "Mic Jack", "MICBIAS",
50 "IN1L", "Mic Jack";
51
52 nvidia,i2s-controller = <&tegra_i2s1>;
53 nvidia,audio-codec = <&wm8903>;
54
55 nvidia,spkr-en-gpios = <&wm8903 2 0>;
56 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
57 };
58};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 000000000000..331a3ef24d59
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903";
12 reg = <0x1a>;
13 interrupt-parent = <&gpio>;
14 interrupts = <187 0x04>;
15
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 micdet-cfg = <0>;
20 micdet-delay = <100>;
21 gpio-cfg = <0xffffffff
22 0xffffffff
23 0
24 0xffffffff
25 0xffffffff>;
26 };
27 };
28
29 sound {
30 compatible = "ad,tegra-audio-plutux",
31 "nvidia,tegra-audio-wm8903";
32 nvidia,model = "Avionic Design Plutux";
33
34 nvidia,audio-routing =
35 "Headphone Jack", "HPOUTR",
36 "Headphone Jack", "HPOUTL",
37 "Int Spk", "ROP",
38 "Int Spk", "RON",
39 "Int Spk", "LOP",
40 "Int Spk", "LON",
41 "Mic Jack", "MICBIAS",
42 "IN1L", "Mic Jack";
43
44 nvidia,i2s-controller = <&tegra_i2s1>;
45 nvidia,audio-codec = <&wm8903>;
46
47 nvidia,spkr-en-gpios = <&wm8903 2 0>;
48 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
49 };
50};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000000..f18cec9f6a77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
1/include/ "tegra20.dtsi"
2
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 pinmux {
12 pinctrl-names = "default";
13 pinctrl-0 = <&state_default>;
14
15 state_default: pinmux {
16 ata {
17 nvidia,pins = "ata";
18 nvidia,function = "ide";
19 };
20 atb {
21 nvidia,pins = "atb", "gma", "gme";
22 nvidia,function = "sdio4";
23 };
24 atc {
25 nvidia,pins = "atc";
26 nvidia,function = "nand";
27 };
28 atd {
29 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
30 "spia", "spib", "spic";
31 nvidia,function = "gmi";
32 };
33 cdev1 {
34 nvidia,pins = "cdev1";
35 nvidia,function = "plla_out";
36 };
37 cdev2 {
38 nvidia,pins = "cdev2";
39 nvidia,function = "pllp_out4";
40 };
41 crtp {
42 nvidia,pins = "crtp";
43 nvidia,function = "crt";
44 };
45 csus {
46 nvidia,pins = "csus";
47 nvidia,function = "vi_sensor_clk";
48 };
49 dap1 {
50 nvidia,pins = "dap1";
51 nvidia,function = "dap1";
52 };
53 dap2 {
54 nvidia,pins = "dap2";
55 nvidia,function = "dap2";
56 };
57 dap3 {
58 nvidia,pins = "dap3";
59 nvidia,function = "dap3";
60 };
61 dap4 {
62 nvidia,pins = "dap4";
63 nvidia,function = "dap4";
64 };
65 ddc {
66 nvidia,pins = "ddc";
67 nvidia,function = "i2c2";
68 };
69 dta {
70 nvidia,pins = "dta", "dtd";
71 nvidia,function = "sdio2";
72 };
73 dtb {
74 nvidia,pins = "dtb", "dtc", "dte";
75 nvidia,function = "rsvd1";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gmc {
82 nvidia,pins = "gmc";
83 nvidia,function = "uartd";
84 };
85 gpu7 {
86 nvidia,pins = "gpu7";
87 nvidia,function = "rtck";
88 };
89 gpv {
90 nvidia,pins = "gpv", "slxa", "slxk";
91 nvidia,function = "pcie";
92 };
93 hdint {
94 nvidia,pins = "hdint", "pta";
95 nvidia,function = "hdmi";
96 };
97 i2cp {
98 nvidia,pins = "i2cp";
99 nvidia,function = "i2cp";
100 };
101 irrx {
102 nvidia,pins = "irrx", "irtx";
103 nvidia,function = "uarta";
104 };
105 kbca {
106 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
107 "kbce", "kbcf";
108 nvidia,function = "kbc";
109 };
110 lcsn {
111 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
112 "ld3", "ld4", "ld5", "ld6", "ld7",
113 "ld8", "ld9", "ld10", "ld11", "ld12",
114 "ld13", "ld14", "ld15", "ld16", "ld17",
115 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
116 "lhs", "lm0", "lm1", "lpp", "lpw0",
117 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
118 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
119 "lvs";
120 nvidia,function = "displaya";
121 };
122 owc {
123 nvidia,pins = "owc", "spdi", "spdo", "uac";
124 nvidia,function = "rsvd2";
125 };
126 pmc {
127 nvidia,pins = "pmc";
128 nvidia,function = "pwr_on";
129 };
130 rm {
131 nvidia,pins = "rm";
132 nvidia,function = "i2c1";
133 };
134 sdb {
135 nvidia,pins = "sdb", "sdc", "sdd";
136 nvidia,function = "pwm";
137 };
138 sdio1 {
139 nvidia,pins = "sdio1";
140 nvidia,function = "sdio1";
141 };
142 slxc {
143 nvidia,pins = "slxc", "slxd";
144 nvidia,function = "spdif";
145 };
146 spid {
147 nvidia,pins = "spid", "spie", "spif";
148 nvidia,function = "spi1";
149 };
150 spig {
151 nvidia,pins = "spig", "spih";
152 nvidia,function = "spi2_alt";
153 };
154 uaa {
155 nvidia,pins = "uaa", "uab", "uda";
156 nvidia,function = "ulpi";
157 };
158 uad {
159 nvidia,pins = "uad";
160 nvidia,function = "irda";
161 };
162 uca {
163 nvidia,pins = "uca", "ucb";
164 nvidia,function = "uartc";
165 };
166 conf_ata {
167 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
168 "cdev1", "cdev2", "dap1", "dtb", "gma",
169 "gmb", "gmc", "gmd", "gme", "gpu7",
170 "gpv", "i2cp", "pta", "rm", "slxa",
171 "slxk", "spia", "spib", "uac";
172 nvidia,pull = <0>;
173 nvidia,tristate = <0>;
174 };
175 conf_ck32 {
176 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
177 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
178 nvidia,pull = <0>;
179 };
180 conf_csus {
181 nvidia,pins = "csus", "spid", "spif";
182 nvidia,pull = <1>;
183 nvidia,tristate = <1>;
184 };
185 conf_crtp {
186 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
187 "dtc", "dte", "dtf", "gpu", "sdio1",
188 "slxc", "slxd", "spdi", "spdo", "spig",
189 "uda";
190 nvidia,pull = <0>;
191 nvidia,tristate = <1>;
192 };
193 conf_ddc {
194 nvidia,pins = "ddc", "dta", "dtd", "kbca",
195 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
196 "sdc";
197 nvidia,pull = <2>;
198 nvidia,tristate = <0>;
199 };
200 conf_hdint {
201 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
202 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
203 "lvp0", "owc", "sdb";
204 nvidia,tristate = <1>;
205 };
206 conf_irrx {
207 nvidia,pins = "irrx", "irtx", "sdd", "spic",
208 "spie", "spih", "uaa", "uab", "uad",
209 "uca", "ucb";
210 nvidia,pull = <2>;
211 nvidia,tristate = <1>;
212 };
213 conf_lc {
214 nvidia,pins = "lc", "ls";
215 nvidia,pull = <2>;
216 };
217 conf_ld0 {
218 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
219 "ld5", "ld6", "ld7", "ld8", "ld9",
220 "ld10", "ld11", "ld12", "ld13", "ld14",
221 "ld15", "ld16", "ld17", "ldi", "lhp0",
222 "lhp1", "lhp2", "lhs", "lm0", "lpp",
223 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
224 "lvs", "pmc";
225 nvidia,tristate = <0>;
226 };
227 conf_ld17_0 {
228 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
229 "ld23_22";
230 nvidia,pull = <1>;
231 };
232 };
233 };
234
235 i2s@70002800 {
236 status = "okay";
237 };
238
239 serial@70006300 {
240 clock-frequency = <216000000>;
241 status = "okay";
242 };
243
244 i2c@7000c000 {
245 clock-frequency = <400000>;
246 status = "okay";
247 };
248
249 i2c@7000d000 {
250 clock-frequency = <400000>;
251 status = "okay";
252
253 pmic: tps6586x@34 {
254 compatible = "ti,tps6586x";
255 reg = <0x34>;
256 interrupts = <0 86 0x4>;
257
258 ti,system-power-controller;
259
260 #gpio-cells = <2>;
261 gpio-controller;
262
263 sys-supply = <&vdd_5v0_reg>;
264 vin-sm0-supply = <&sys_reg>;
265 vin-sm1-supply = <&sys_reg>;
266 vin-sm2-supply = <&sys_reg>;
267 vinldo01-supply = <&sm2_reg>;
268 vinldo23-supply = <&sm2_reg>;
269 vinldo4-supply = <&sm2_reg>;
270 vinldo678-supply = <&sm2_reg>;
271 vinldo9-supply = <&sm2_reg>;
272
273 regulators {
274 #address-cells = <1>;
275 #size-cells = <0>;
276
277 sys_reg: regulator@0 {
278 reg = <0>;
279 regulator-compatible = "sys";
280 regulator-name = "vdd_sys";
281 regulator-always-on;
282 };
283
284 regulator@1 {
285 reg = <1>;
286 regulator-compatible = "sm0";
287 regulator-name = "vdd_sys_sm0,vdd_core";
288 regulator-min-microvolt = <1200000>;
289 regulator-max-microvolt = <1200000>;
290 regulator-always-on;
291 };
292
293 regulator@2 {
294 reg = <2>;
295 regulator-compatible = "sm1";
296 regulator-name = "vdd_sys_sm1,vdd_cpu";
297 regulator-min-microvolt = <1000000>;
298 regulator-max-microvolt = <1000000>;
299 regulator-always-on;
300 };
301
302 sm2_reg: regulator@3 {
303 reg = <3>;
304 regulator-compatible = "sm2";
305 regulator-name = "vdd_sys_sm2,vin_ldo*";
306 regulator-min-microvolt = <3700000>;
307 regulator-max-microvolt = <3700000>;
308 regulator-always-on;
309 };
310
311 regulator@4 {
312 reg = <4>;
313 regulator-compatible = "ldo0";
314 regulator-name = "vdd_ldo0,vddio_pex_clk";
315 regulator-min-microvolt = <3300000>;
316 regulator-max-microvolt = <3300000>;
317 };
318
319 regulator@5 {
320 reg = <5>;
321 regulator-compatible = "ldo1";
322 regulator-name = "vdd_ldo1,avdd_pll*";
323 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>;
325 regulator-always-on;
326 };
327
328 regulator@6 {
329 reg = <6>;
330 regulator-compatible = "ldo2";
331 regulator-name = "vdd_ldo2,vdd_rtc";
332 regulator-min-microvolt = <1200000>;
333 regulator-max-microvolt = <1200000>;
334 };
335
336 regulator@7 {
337 reg = <7>;
338 regulator-compatible = "ldo3";
339 regulator-name = "vdd_ldo3,avdd_usb*";
340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>;
342 regulator-always-on;
343 };
344
345 regulator@8 {
346 reg = <8>;
347 regulator-compatible = "ldo4";
348 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <1800000>;
351 regulator-always-on;
352 };
353
354 regulator@9 {
355 reg = <9>;
356 regulator-compatible = "ldo5";
357 regulator-name = "vdd_ldo5,vcore_mmc";
358 regulator-min-microvolt = <2850000>;
359 regulator-max-microvolt = <2850000>;
360 };
361
362 regulator@10 {
363 reg = <10>;
364 regulator-compatible = "ldo6";
365 regulator-name = "vdd_ldo6,avdd_vdac";
366 /*
367 * According to the Tegra 2 Automotive
368 * DataSheet, a typical value for this
369 * would be 2.8V, but the PMIC only
370 * supports 2.85V.
371 */
372 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>;
374 };
375
376 regulator@11 {
377 reg = <11>;
378 regulator-compatible = "ldo7";
379 regulator-name = "vdd_ldo7,avdd_hdmi";
380 regulator-min-microvolt = <3300000>;
381 regulator-max-microvolt = <3300000>;
382 };
383
384 regulator@12 {
385 reg = <12>;
386 regulator-compatible = "ldo8";
387 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 };
391
392 regulator@13 {
393 reg = <13>;
394 regulator-compatible = "ldo9";
395 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
396 /*
397 * According to the Tegra 2 Automotive
398 * DataSheet, a typical value for this
399 * would be 2.8V, but the PMIC only
400 * supports 2.85V.
401 */
402 regulator-min-microvolt = <2850000>;
403 regulator-max-microvolt = <2850000>;
404 regulator-always-on;
405 };
406
407 regulator@14 {
408 reg = <14>;
409 regulator-compatible = "ldo_rtc";
410 regulator-name = "vdd_rtc_out";
411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 regulator-always-on;
414 };
415 };
416 };
417 };
418
419 pmc {
420 nvidia,invert-interrupt;
421 };
422
423 usb@c5008000 {
424 status = "okay";
425 };
426
427 sdhci@c8000600 {
428 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
429 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
430 bus-width = <4>;
431 status = "okay";
432 };
433
434 regulators {
435 compatible = "simple-bus";
436
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 vdd_5v0_reg: regulator@0 {
441 compatible = "regulator-fixed";
442 reg = <0>;
443 regulator-name = "vdd_5v0";
444 regulator-min-microvolt = <5000000>;
445 regulator-max-microvolt = <5000000>;
446 regulator-always-on;
447 };
448 };
449};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 000000000000..9aff31b0fe4a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 clock-frequency = <400000>;
11 status = "okay";
12
13 wm8903: wm8903@1a {
14 compatible = "wlf,wm8903";
15 reg = <0x1a>;
16 interrupt-parent = <&gpio>;
17 interrupts = <187 0x04>;
18
19 gpio-controller;
20 #gpio-cells = <2>;
21
22 micdet-cfg = <0>;
23 micdet-delay = <100>;
24 gpio-cfg = <0xffffffff
25 0xffffffff
26 0
27 0xffffffff
28 0xffffffff>;
29 };
30 };
31
32 sound {
33 compatible = "ad,tegra-audio-wm8903-tec",
34 "nvidia,tegra-audio-wm8903";
35 nvidia,model = "Avionic Design TEC";
36
37 nvidia,audio-routing =
38 "Headphone Jack", "HPOUTR",
39 "Headphone Jack", "HPOUTL",
40 "Int Spk", "ROP",
41 "Int Spk", "RON",
42 "Int Spk", "LOP",
43 "Int Spk", "LON",
44 "Mic Jack", "MICBIAS",
45 "IN1L", "Mic Jack";
46
47 nvidia,i2s-controller = <&tegra_i2s1>;
48 nvidia,audio-codec = <&wm8903>;
49
50 nvidia,spkr-en-gpios = <&wm8903 2 0>;
51 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
52 };
53};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 4ae1e5dcfa62..c636d002d6d8 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -267,6 +267,8 @@
267 reg = <0x3c>; 267 reg = <0x3c>;
268 interrupts = <0 86 0x4>; 268 interrupts = <0 86 0x4>;
269 269
270 maxim,system-power-controller;
271
270 mbatt-supply = <&usb0_vbus_reg>; 272 mbatt-supply = <&usb0_vbus_reg>;
271 in-v1-supply = <&mbatt_reg>; 273 in-v1-supply = <&mbatt_reg>;
272 in-v2-supply = <&mbatt_reg>; 274 in-v2-supply = <&mbatt_reg>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904e..67a6cd910b96 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 pwm { 126 pwm: pwm {
127 compatible = "nvidia,tegra20-pwm"; 127 compatible = "nvidia,tegra20-pwm";
128 reg = <0x7000a000 0x100>; 128 reg = <0x7000a000 0x100>;
129 #pwm-cells = <2>; 129 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14efb..b1497c7d7d68 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
117 status = "disabled"; 117 status = "disabled";
118 }; 118 };
119 119
120 pwm { 120 pwm: pwm {
121 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 121 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
122 reg = <0x7000a000 0x100>; 122 reg = <0x7000a000 0x100>;
123 #pwm-cells = <2>; 123 #pwm-cells = <2>;
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 6e3520725b06..54c16aade475 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,8 +3,11 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
4 4
5dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb 5dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
6dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb
6dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb 7dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
8dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb
7dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb 9dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
10dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb
8dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb 11dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
9dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb 12dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
10dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb 13dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 10:26:18 -0500