1272 files changed, 28215 insertions, 38284 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e04c7793f47e..dedf02b6f322 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -4,6 +4,7 @@ config ARM
        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
        select ARCH_HAVE_CUSTOM_GPIO_H
+        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
        select ARCH_WANT_IPC_PARSE_VERSION
        select BUILDTIME_EXTABLE_SORT if MMU
        select CPU_PM if (SUSPEND || CPU_IDLE)
@@ -36,7 +37,6 @@ config ARM
        select HAVE_GENERIC_HARDIRQS
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
        select HAVE_IDE if PCI || ISA || PCMCIA
-        select HAVE_IRQ_WORK
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZMA
        select HAVE_KERNEL_LZO
@@ -49,6 +49,7 @@ config ARM
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_UID16
+        select HAVE_VIRT_TO_BUS
        select KTIME_SCALAR
        select PERF_USE_VMALLOC
        select RTC_LIB
@@ -56,6 +57,8 @@ config ARM
        select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
        select MODULES_USE_ELF_REL
        select CLONE_BACKWARDS
+        select OLD_SIGSUSPEND3
+        select OLD_SIGACTION
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -75,6 +78,27 @@ config ARM_DMA_USE_IOMMU
        select ARM_HAS_SG_CHAIN
        select NEED_SG_DMA_LENGTH
+if ARM_DMA_USE_IOMMU
+config ARM_DMA_IOMMU_ALIGNMENT
+        int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
+        range 4 9
+        default 8
+        help
+          DMA mapping framework by default aligns all buffers to the smallest
+          PAGE_SIZE order which is greater than or equal to the requested buffer
+          size. This works well for buffers up to a few hundreds kilobytes, but
+          for larger buffers it just a waste of address space. Drivers which has
+          relatively small addressing window (like 64Mib) might run out of
+          virtual space with just a few allocations.
+          With this parameter you can specify the maximum PAGE_SIZE order for
+          DMA IOMMU buffers. Larger buffers will be aligned only to this
+          specified order. The order is expressed as a power of two multiplied
+          by the PAGE_SIZE.
+endif
 config HAVE_PWM
        bool
@@ -261,7 +285,8 @@ config MMU
 #
 choice
        prompt "ARM system type"
-        default ARCH_MULTIPLATFORM
+        default ARCH_VERSATILE if !MMU
+        default ARCH_MULTIPLATFORM if MMU
 config ARCH_MULTIPLATFORM
        bool "Allow multiple platforms to be selected"
@@ -344,10 +369,10 @@ config ARCH_BCM2835
        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
        select CLKDEV_LOOKUP
+        select CLKSRC_OF
        select COMMON_CLK
        select CPU_V6
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select MULTI_IRQ_HANDLER
        select PINCTRL
        select PINCTRL_BCM2835
@@ -393,6 +418,7 @@ config ARCH_GEMINI
 config ARCH_SIRF
        bool "CSR SiRF"
        select ARCH_REQUIRE_GPIOLIB
+        select AUTO_ZRELADDR
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
@@ -640,11 +666,12 @@ config ARCH_LPC32XX
 config ARCH_TEGRA
        bool "NVIDIA Tegra"
        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
+        select CLKSRC_OF
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
@@ -698,6 +725,7 @@ config ARCH_SHMOBILE
        select MULTI_IRQ_HANDLER
        select NEED_MACH_MEMORY_H
        select NO_IOPORT
+        select PINCTRL
        select PM_GENERIC_DOMAINS if PM
        select SPARSE_IRQ
        help
@@ -744,7 +772,6 @@ config ARCH_S3C24XX
        select ARCH_HAS_CPUFREQ
        select ARCH_USES_GETTIMEOFFSET
        select CLKDEV_LOOKUP
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -787,7 +814,6 @@ config ARCH_S5P64X0
        select CLKSRC_MMIO
        select CPU_V6
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -802,7 +828,6 @@ config ARCH_S5PC100
        select ARCH_USES_GETTIMEOFFSET
        select CLKDEV_LOOKUP
        select CPU_V7
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -820,7 +845,6 @@ config ARCH_S5PV210
        select CLKSRC_MMIO
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -838,7 +862,6 @@ config ARCH_EXYNOS
        select CLKDEV_LOOKUP
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -873,7 +896,6 @@ config ARCH_U300
        select COMMON_CLK
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_TCM
        select SPARSE_IRQ
        help
@@ -899,10 +921,12 @@ config ARCH_NOMADIK
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select ARM_VIC
+        select CLKSRC_NOMADIK_MTU
        select COMMON_CLK
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
        select MIGHT_HAVE_CACHE_L2X0
+        select USE_OF
        select PINCTRL
        select PINCTRL_STN8815
        select SPARSE_IRQ
@@ -937,33 +961,24 @@ config ARCH_DAVINCI
        help
          Support for TI's DaVinci platform.
-config ARCH_OMAP
+config ARCH_OMAP1
-        bool "TI OMAP"
+        bool "TI OMAP1"
        depends on MMU
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
-        select ARCH_REQUIRE_GPIOLIB
+        select ARCH_OMAP
-        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        help
-          Support for TI's OMAP platform (OMAP1/2/3/4).
-config ARCH_VT8500_SINGLE
-        bool "VIA/WonderMedia 85xx"
-        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
-        select COMMON_CLK
+        select CLKSRC_MMIO
-        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
+        select GENERIC_IRQ_CHIP
        select HAVE_CLK
-        select MULTI_IRQ_HANDLER
+        select HAVE_IDE
-        select SPARSE_IRQ
+        select IRQ_DOMAIN
-        select USE_OF
+        select NEED_MACH_IO_H if PCCARD
+        select NEED_MACH_MEMORY_H
        help
-          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+          Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 endchoice
@@ -1086,17 +1101,12 @@ source "arch/arm/mach-realview/Kconfig"
 source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
-source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/plat-spear/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
-if ARCH_S3C24XX
-source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2440/Kconfig"
-endif
 if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
@@ -1127,6 +1137,8 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
+source "arch/arm/mach-virt/Kconfig"
 source "arch/arm/mach-vt8500/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
@@ -1450,6 +1462,10 @@ config ISA_DMA
        bool
        select ISA_DMA_API
+config ARCH_NO_VIRT_TO_BUS
+        def_bool y
+        depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
 # Select ISA DMA interface
 config ISA_DMA_API
        bool
@@ -1531,7 +1547,6 @@ config SMP
 config SMP_ON_UP
        bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        depends on SMP && !XIP_KERNEL
        default y
        help
@@ -1572,9 +1587,10 @@ config HAVE_ARM_SCU
        help
          This option enables support for the ARM system coherency unit
-config ARM_ARCH_TIMER
+config HAVE_ARM_ARCH_TIMER
        bool "Architected timer support"
        depends on CPU_V7
+        select ARM_ARCH_TIMER
        help
          This option enables support for the ARM architected timer
@@ -1620,6 +1636,16 @@ config HOTPLUG_CPU
          Say Y here to experiment with turning CPUs off and on.  CPUs
          can be controlled through /sys/devices/system/cpu.
+config ARM_PSCI
+        bool "Support for the ARM Power State Coordination Interface (PSCI)"
+        depends on CPU_V7
+        help
+          Say Y here if you want Linux to communicate with system firmware
+          implementing the PSCI specification for CPU-centric power
+          management operations described in ARM document number ARM DEN
+          0022A ("Power State Coordination Interface System Software on
+          ARM processors").
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP
@@ -1637,7 +1663,7 @@ config ARCH_NR_GPIO
        default 355 if ARCH_U8500
        default 264 if MACH_H4700
        default 512 if SOC_OMAP5
-        default 288 if ARCH_VT8500
+        default 288 if ARCH_VT8500 || ARCH_SUNXI
        default 0
        help
          Maximum number of GPIOs in the system.
@@ -1650,11 +1676,13 @@ config HZ
        int
        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
                ARCH_S5PV210 || ARCH_EXYNOS4
-        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
        default AT91_TIMER_HZ if ARCH_AT91
        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
        default 100
+config SCHED_HRTICK
+        def_bool HIGH_RES_TIMERS
 config THUMB2_KERNEL
        bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
@@ -1720,7 +1748,7 @@ config AEABI
 config OABI_COMPAT
        bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
-        depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
+        depends on AEABI && !THUMB2_KERNEL
        default y
        help
          This option preserves the old syscall interface along with the
@@ -1844,7 +1872,6 @@ config SECCOMP
 config CC_STACKPROTECTOR
        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        help
          This option turns on the -fstack-protector GCC feature. This
          feature puts, at the beginning of functions, a canary value on
@@ -1861,7 +1888,7 @@ config XEN_DOM0
 config XEN
        bool "Xen guest support on ARM (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && ARM && OF
+        depends on ARM && OF
        depends on CPU_V7 && !CPU_V6
        help
          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
@@ -1930,7 +1957,7 @@ config ZBOOT_ROM
 choice
        prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
-        depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
+        depends on ZBOOT_ROM && ARCH_SH7372
        default ZBOOT_ROM_NONE
        help
          Include experimental SD/MMC loading code in the ROM-able zImage.
@@ -1959,7 +1986,7 @@ endchoice
 config ARM_APPENDED_DTB
        bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
-        depends on OF && !ZBOOT_ROM && EXPERIMENTAL
+        depends on OF && !ZBOOT_ROM
        help
          With this option, the boot code will look for a device tree binary
          (DTB) appended to zImage
@@ -2077,7 +2104,7 @@ config XIP_PHYS_ADDR
 config KEXEC
        bool "Kexec system call (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
+        depends on (!SMP || HOTPLUG_CPU)
        help
          kexec is a system call that implements the ability to shutdown your
          current kernel, and to start another kernel.  It is like a reboot
@@ -2099,7 +2126,6 @@ config ATAGS_PROC
 config CRASH_DUMP
        bool "Build kdump crash kernel (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
        help
          Generate crash dump after being started by kexec. This should
          be normally only set in special crash dump kernels which are
@@ -2166,7 +2192,7 @@ config CPU_FREQ_S3C
 config CPU_FREQ_S3C24XX
        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
+        depends on ARCH_S3C24XX && CPU_FREQ
        select CPU_FREQ_S3C
        help
          This enables the CPUfreq driver for the Samsung S3C24XX family
@@ -2178,7 +2204,7 @@ config CPU_FREQ_S3C24XX
 config CPU_FREQ_S3C24XX_PLL
        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
-        depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
+        depends on CPU_FREQ_S3C24XX
        help
          Compile in support for changing the PLL frequency from the
          S3C24XX series CPUfreq driver. The PLL takes time to settle
@@ -2241,7 +2267,7 @@ config FPE_NWFPE_XP
 config FPE_FASTFPE
        bool "FastFPE math emulation (EXPERIMENTAL)"
-        depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
+        depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
        ---help---
          Say Y here to include the FAST floating point emulator in the kernel.
          This is an experimental much faster emulator which now also has full
@@ -2323,3 +2349,5 @@ source "security/Kconfig"
 source "crypto/Kconfig"
 source "lib/Kconfig"
+source "arch/arm/kvm/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 661030d6bc6c..acddddac7ee4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -32,7 +32,7 @@ config FRAME_POINTER
 config ARM_UNWIND
        bool "Enable stack unwinding support (EXPERIMENTAL)"
-        depends on AEABI && EXPERIMENTAL
+        depends on AEABI
        default y
        help
          This option enables stack unwinding support in the kernel
@@ -205,12 +205,19 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX28.
-        config DEBUG_IMX31_IMX35_UART
+        config DEBUG_IMX31_UART
-                bool "i.MX31 and i.MX35 Debug UART"
+                bool "i.MX31 Debug UART"
-                depends on SOC_IMX31 || SOC_IMX35
+                depends on SOC_IMX31
                help
                  Say Y here if you want kernel low-level debugging support
-                  on i.MX31 or i.MX35.
+                  on i.MX31.
+        config DEBUG_IMX35_UART
+                bool "i.MX35 Debug UART"
+                depends on SOC_IMX35
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX35.
        config DEBUG_IMX51_UART
                bool "i.MX51 Debug UART"
@@ -219,12 +226,12 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX51.
-        config DEBUG_IMX50_IMX53_UART
+        config DEBUG_IMX53_UART
-                bool "i.MX50 and i.MX53 Debug UART"
+                bool "i.MX53 Debug UART"
-                depends on SOC_IMX50 || SOC_IMX53
+                depends on SOC_IMX53
                help
                  Say Y here if you want kernel low-level debugging support
-                  on i.MX50 or i.MX53.
+                  on i.MX53.
        config DEBUG_IMX6Q_UART
                bool "i.MX6Q Debug UART"
@@ -291,6 +298,13 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on MVEBU based platforms.
+        config DEBUG_OMAP2PLUS_UART
+                bool "Kernel low-level debugging messages via OMAP2PLUS UART"
+                depends on ARCH_OMAP2PLUS
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on OMAP2PLUS based platforms.
        config DEBUG_PICOXCELL_UART
                depends on ARCH_PICOXCELL
                bool "Use PicoXcell UART for low-level debug"
@@ -386,6 +400,20 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on Tegra based platforms.
+        config DEBUG_SIRFPRIMA2_UART1
+                bool "Kernel low-level debugging messages via SiRFprimaII UART1"
+                depends on ARCH_PRIMA2
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the uart1 port on SiRFprimaII devices.
+        config DEBUG_SIRFMARCO_UART1
+                bool "Kernel low-level debugging messages via SiRFmarco UART1"
+                depends on ARCH_MARCO
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the uart1 port on SiRFmarco devices.
        config DEBUG_VEXPRESS_UART0_DETECT
                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -412,6 +440,13 @@ choice
                  of the tiles using the RS1 memory map, including all new A-class
                  core tiles, FPGA-based SMMs and software models.
+        config DEBUG_VT8500_UART0
+                bool "Use UART0 on VIA/Wondermedia SoCs"
+                depends on ARCH_VT8500
+                help
+                  This option selects UART0 on VIA/Wondermedia System-on-a-chip
+                  devices, including VT8500, WM8505, WM8650 and WM8850.
        config DEBUG_LL_UART_NONE
                bool "No low-level debugging UART"
                depends on !ARCH_MULTIPLATFORM
@@ -450,17 +485,70 @@ choice
 endchoice
-config DEBUG_IMX6Q_UART_PORT
+config DEBUG_IMX_UART_PORT
-        int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART
+        int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
-        range 1 5
+                                                DEBUG_IMX25_UART || \
+                                                DEBUG_IMX21_IMX27_UART || \
+                                                DEBUG_IMX31_UART || \
+                                                DEBUG_IMX35_UART || \
+                                                DEBUG_IMX51_UART || \
+                                                DEBUG_IMX50_IMX53_UART || \
+                                                DEBUG_IMX6Q_UART
        default 1
-        depends on SOC_IMX6Q
        help
          Choose UART port on which kernel low-level debug messages
          should be output.
 choice
        prompt "Low-level debug console UART"
+        depends on DEBUG_OMAP2PLUS_UART
+        config DEBUG_OMAP2UART1
+                bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
+                help
+                  This covers at least h4, 2430sdp, 3430sdp, 3630sdp,
+                  omap3 torpedo and 3530 lv som.
+        config DEBUG_OMAP2UART2
+                bool "OMAP2/3/4 UART2"
+        config DEBUG_OMAP2UART3
+                bool "OMAP2 UART3 (n8x0)"
+        config DEBUG_OMAP3UART3
+                bool "OMAP3 UART3 (most omap3 boards)"
+                help
+                  This covers at least cm_t3x, beagle, crane, devkit8000,
+                  igep00x0, ldp, n900, n9(50), pandora, overo, touchbook,
+                  and 3517evm.
+        config DEBUG_OMAP4UART3
+                bool "OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)"
+        config DEBUG_OMAP3UART4
+                bool "OMAP36XX UART4"
+        config DEBUG_OMAP4UART4
+                bool "OMAP4/5 UART4"
+        config DEBUG_TI81XXUART1
+                bool "TI81XX UART1 (ti8148evm)"
+        config DEBUG_TI81XXUART2
+                bool "TI81XX UART2"
+        config DEBUG_TI81XXUART3
+                bool "TI81XX UART3 (ti8168evm)"
+        config DEBUG_AM33XXUART1
+                bool "AM33XX UART1"
+        config DEBUG_ZOOM_UART
+                bool "Zoom2/3 UART"
+endchoice
+choice
+        prompt "Low-level debug console UART"
        depends on DEBUG_LL && DEBUG_TEGRA_UART
        config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -495,17 +583,20 @@ config DEBUG_LL_INCLUDE
        default "debug/imx.S" if DEBUG_IMX1_UART || \
                                 DEBUG_IMX25_UART || \
                                 DEBUG_IMX21_IMX27_UART || \
-                                 DEBUG_IMX31_IMX35_UART || \
+                                 DEBUG_IMX31_UART || \
+                                 DEBUG_IMX35_UART || \
                                 DEBUG_IMX51_UART || \
-                                 DEBUG_IMX50_IMX53_UART ||\
+                                 DEBUG_IMX53_UART ||\
                                 DEBUG_IMX6Q_UART
        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+        default "debug/vt8500.S" if DEBUG_VT8500_UART0
        default "debug/tegra.S" if DEBUG_TEGRA_UART
        default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
        default "mach/debug-macro.S"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30c443c406f3..ee4605f400b0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_PRIMA2)		+= prima2
 machine-$(CONFIG_ARCH_PXA)              += pxa
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
 machine-$(CONFIG_ARCH_RPC)              += rpc
-machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
@@ -194,6 +194,7 @@ machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
 machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
 machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
 machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
+machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
@@ -204,7 +205,7 @@ plat-$(CONFIG_ARCH_S3C64XX)	+= samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
 plat-$(CONFIG_PLAT_ORION)       += orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
-plat-$(CONFIG_PLAT_S3C24XX)     += s3c24xx samsung
+plat-$(CONFIG_PLAT_S3C24XX)     += samsung
 plat-$(CONFIG_PLAT_S5P)         += samsung
 plat-$(CONFIG_PLAT_SPEAR)       += spear
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
@@ -252,6 +253,7 @@ core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
 core-$(CONFIG_XEN)              += arch/arm/xen/
+core-$(CONFIG_KVM_ARM_HOST)     += arch/arm/kvm/
 # If we have a machine-specific directory, then include it in the build.
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index abfce280f57b..71768b8a1ab9 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -68,8 +68,8 @@ else
 endif
 check_for_multiple_loadaddr = \
-if [ $(words $(UIMAGE_LOADADDR)) -gt 1 ]; then \
+if [ $(words $(UIMAGE_LOADADDR)) -ne 1 ]; then \
-        echo 'multiple load addresses: $(UIMAGE_LOADADDR)'; \
+        echo 'multiple (or no) load addresses: $(UIMAGE_LOADADDR)'; \
        echo 'This is incompatible with uImages'; \
        echo 'Specify LOADADDR on the commandline to build an uImage'; \
        false; \
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 9deb56a702ce..24b0475cb8bf 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -13,8 +13,6 @@ extern void error(char *);
 #define STATIC static
 #define STATIC_RW_DATA  /* non-static please */
-#define ARCH_HAS_DECOMP_WDOG
 /* Diagnostic functions */
 #ifdef DEBUG
 #  define Assert(cond,msg) {if(!(cond)) error(msg);}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ebb44fe826a..9c6255884cbb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
        kirkwood-dockstar.dtb \
        kirkwood-dreamplug.dtb \
        kirkwood-goflexnet.dtb \
+        kirkwood-guruplug-server-plus.dtb \
        kirkwood-ib62x0.dtb \
        kirkwood-iconnect.dtb \
        kirkwood-iomega_ix2_200.dtb \
@@ -73,15 +74,26 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
        kirkwood-ts219-6281.dtb \
        kirkwood-ts219-6282.dtb \
        kirkwood-openblocks_a6.dtb
+dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
        msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
        armada-370-mirabox.dtb \
+        armada-370-rd.dtb \
        armada-xp-db.dtb \
+        armada-xp-gp.dtb \
        armada-xp-openblocks-ax3-4.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
+dtb-$(CONFIG_ARCH_MXC) += \
+        imx25-karo-tx25.dtb \
+        imx25-pdk.dtb \
+        imx27-apf27.dtb \
+        imx27-pdk.dtb \
+        imx31-bug.dtb \
+        imx51-apf51.dtb \
+        imx51-babbage.dtb \
        imx53-ard.dtb \
        imx53-evk.dtb \
+        imx53-mba53.dtb \
        imx53-qsb.dtb \
        imx53-smd.dtb \
        imx6q-arm2.dtb \
@@ -95,11 +107,13 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx28-apf28dev.dtb \
        imx28-apx4devkit.dtb \
        imx28-cfa10036.dtb \
+        imx28-cfa10037.dtb \
        imx28-cfa10049.dtb \
        imx28-evk.dtb \
        imx28-m28evk.dtb \
        imx28-sps1.dtb \
        imx28-tx28.dtb
+dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap3-beagle.dtb \
        omap3-beagle-xm.dtb \
@@ -124,6 +138,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
        r8a7740-armadillo800eva.dtb \
        sh73a0-kzm9g.dtb \
        sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+        socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
        spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
@@ -132,8 +148,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
        spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
+        sun4i-a10-hackberry.dtb \
        sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+        tegra20-iris-512.dtb \
        tegra20-medcom-wide.dtb \
        tegra20-paz00.dtb \
        tegra20-plutux.dtb \
@@ -142,8 +160,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-trimslice.dtb \
        tegra20-ventana.dtb \
        tegra20-whistler.dtb \
+        tegra30-beaver.dtb \
        tegra30-cardhu-a02.dtb \
-        tegra30-cardhu-a04.dtb
+        tegra30-cardhu-a04.dtb \
+        tegra114-dalmore.dtb \
+        tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
        vexpress-v2p-ca9.dtb \
        vexpress-v2p-ca15-tc1.dtb \
@@ -151,7 +172,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
        xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
        wm8505-ref.dtb \
-        wm8650-mid.dtb
+        wm8650-mid.dtb \
+        wm8850-w70v2.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
 targets += dtbs
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c2f14e875eb6..0957645b73af 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -385,5 +385,19 @@
                                mac-address = [ 00 00 00 00 00 00 ];
                        };
                };
+                ocmcram: ocmcram@40300000 {
+                        compatible = "ti,am3352-ocmcram";
+                        reg = <0x40300000 0x10000>;
+                        ti,hwmods = "ocmcram";
+                        ti,no_idle_on_suspend;
+                };
+                wkup_m3: wkup_m3@44d00000 {
+                        compatible = "ti,am3353-wkup-m3";
+                        reg = <0x44d00000 0x4000        /* M3 UMEM */
+                               0x44d80000 0x2000>;      /* M3 DMEM */
+                        ti,hwmods = "wkup_m3";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 74d92cd29d87..5160210f74da 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -78,6 +78,10 @@
                                        bus-width = <4>;
                                };
                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 9b82facb2561..e34b280ce6ec 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -59,5 +59,40 @@
                        phy = <&phy1>;
                        phy-mode = "rgmii-id";
                };
+                mvsdio@d00d4000 {
+                        pinctrl-0 = <&sdio_pins1>;
+                        pinctrl-names = "default";
+                        /*
+                         * This device is disabled by default, because
+                         * using the SD card connector requires
+                         * changing the default CON40 connector
+                         * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
+                         * different connector
+                         * "DB-88F6710_MPP_RGMII_SD_Jumper".
+                         */
+                        status = "disabled";
+                        /* No CD or WP GPIOs */
+                };
+                usb@d0050000 {
+                        status = "okay";
+                };
+                usb@d0051000 {
+                        status = "okay";
+                };
+                spi0: spi@d0010600 {
+                        status = "okay";
+                        spi-flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mx25l25635e";
+                                reg = <0>; /* Chip select 0 */
+                                spi-max-frequency = <50000000>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 3b4071336599..dd0c57dd9f30 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -52,5 +52,23 @@
                        phy = <&phy1>;
                        phy-mode = "rgmii-id";
                };
+                mvsdio@d00d4000 {
+                        pinctrl-0 = <&sdio_pins2>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /*
+                         * No CD or WP GPIOs: SDIO interface used for
+                         * Wifi/Bluetooth chip
+                         */
+                };
+                usb@d0050000 {
+                        status = "okay";
+                };
+                usb@d0051000 {
+                        status = "okay";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
new file mode 100644
index 000000000000..f8e4855bc9a5
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -0,0 +1,68 @@
+/*
+ * Device Tree file for Marvell Armada 370 Reference Design board
+ * (RD-88F6710-A1)
+ *
+ *  Copied from arch/arm/boot/dts/armada-370-db.dts
+ *
+ *  Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "armada-370.dtsi"
+/ {
+        model = "Marvell Armada 370 Reference Design";
+        compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                sata@d00a0000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+                mdio {
+                        phy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+                ethernet@d0070000 {
+                        status = "okay";
+                        phy = <&phy0>;
+                        phy-mode = "sgmii";
+                };
+                ethernet@d0074000 {
+                        status = "okay";
+                        phy = <&phy1>;
+                        phy-mode = "rgmii-id";
+                };
+                mvsdio@d00d4000 {
+                        pinctrl-0 = <&sdio_pins1>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 4c0abe85405f..6f1acc75e155 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -68,8 +68,9 @@
                timer@d0020300 {
                               compatible = "marvell,armada-370-xp-timer";
-                               reg = <0xd0020300 0x30>;
+                               reg = <0xd0020300 0x30>,
-                               interrupts = <37>, <38>, <39>, <40>;
+                               <0xd0021040 0x30>;
+                               interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
                               clocks = <&coreclk 2>;
                };
@@ -131,6 +132,56 @@
                        clocks = <&coreclk 0>;
                        status = "disabled";
                };
+                rtc@10300 {
+                        compatible = "marvell,orion-rtc";
+                        reg = <0xd0010300 0x20>;
+                        interrupts = <50>;
+                };
+                mvsdio@d00d4000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0xd00d4000 0x200>;
+                        interrupts = <54>;
+                        clocks = <&gateclk 17>;
+                        status = "disabled";
+                };
+                usb@d0050000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xd0050000 0x500>;
+                        interrupts = <45>;
+                        status = "disabled";
+                };
+                usb@d0051000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xd0051000 0x500>;
+                        interrupts = <46>;
+                        status = "disabled";
+                };
+                spi0: spi@d0010600 {
+                        compatible = "marvell,orion-spi";
+                        reg = <0xd0010600 0x28>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <30>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                spi1: spi@d0010680 {
+                        compatible = "marvell,orion-spi";
+                        reg = <0xd0010680 0x28>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        interrupts = <92>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 636cf7d4009e..8188d138020e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -47,6 +47,18 @@
                pinctrl {
                        compatible = "marvell,mv88f6710-pinctrl";
                        reg = <0xd0018000 0x38>;
+                        sdio_pins1: sdio-pins1 {
+                              marvell,pins = "mpp9",  "mpp11", "mpp12",
+                                             "mpp13", "mpp14", "mpp15";
+                              marvell,function = "sd0";
+                        };
+                        sdio_pins2: sdio-pins2 {
+                              marvell,pins = "mpp47", "mpp48", "mpp49",
+                                             "mpp50", "mpp51", "mpp52";
+                              marvell,function = "sd0";
+                        };
                };
                gpio0: gpio@d0018100 {
@@ -132,5 +144,14 @@
                                dmacap,memset;
                        };
                };
+                usb@d0050000 {
+                        clocks = <&coreclk 0>;
+                };
+                usb@d0051000 {
+                        clocks = <&coreclk 0>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 8e53b25b5508..e83505e4c236 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -90,5 +90,36 @@
                        phy = <&phy3>;
                        phy-mode = "sgmii";
                };
+                mvsdio@d00d4000 {
+                        pinctrl-0 = <&sdio_pins>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                };
+                usb@d0050000 {
+                        status = "okay";
+                };
+                usb@d0051000 {
+                        status = "okay";
+                };
+                usb@d0052000 {
+                        status = "okay";
+                };
+                spi0: spi@d0010600 {
+                        status = "okay";
+                        spi-flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "m25p64";
+                                reg = <0>; /* Chip select 0 */
+                                spi-max-frequency = <20000000>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
new file mode 100644
index 000000000000..1c8afe2ffebc
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -0,0 +1,113 @@
+/*
+ * Device Tree file for Marvell Armada XP development board
+ * (DB-MV784MP-GP)
+ *
+ * Copyright (C) 2013 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "armada-xp-mv78460.dtsi"
+/ {
+        model = "Marvell Armada XP Development Board DB-MV784MP-GP";
+        compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                /*
+                 * 4 GB of plug-in RAM modules by default but only 3GB
+                 * are visible, the amount of memory available can be
+                 * changed by the bootloader according the size of the
+                 * module actually plugged
+                 */
+                reg = <0x00000000 0xC0000000>;
+        };
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012100 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012200 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012300 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                sata@d00a0000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+                mdio {
+                        phy0: ethernet-phy@0 {
+                                reg = <16>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                reg = <17>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                reg = <18>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                reg = <19>;
+                        };
+                };
+                ethernet@d0070000 {
+                        status = "okay";
+                        phy = <&phy0>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0074000 {
+                        status = "okay";
+                        phy = <&phy1>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0030000 {
+                        status = "okay";
+                        phy = <&phy2>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0034000 {
+                        status = "okay";
+                        phy = <&phy3>;
+                        phy-mode = "rgmii-id";
+                };
+                spi0: spi@d0010600 {
+                        status = "okay";
+                        spi-flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "n25q128a13";
+                                reg = <0>; /* Chip select 0 */
+                                spi-max-frequency = <108000000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index e041f42ed711..f56c40599f5b 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -47,6 +47,12 @@
                pinctrl {
                        compatible = "marvell,mv78230-pinctrl";
                        reg = <0xd0018000 0x38>;
+                        sdio_pins: sdio-pins {
+                                marvell,pins = "mpp30", "mpp31", "mpp32",
+                                               "mpp33", "mpp34", "mpp35";
+                                marvell,function = "sd0";
+                        };
                };
                gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 9e23bd8c9536..f8f2b787d2b0 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -48,6 +48,12 @@
                pinctrl {
                        compatible = "marvell,mv78260-pinctrl";
                        reg = <0xd0018000 0x38>;
+                        sdio_pins: sdio-pins {
+                                marvell,pins = "mpp30", "mpp31", "mpp32",
+                                               "mpp33", "mpp34", "mpp35";
+                                marvell,function = "sd0";
+                        };
                };
                gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 965966110e38..936c25dc32b0 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -63,6 +63,12 @@
                pinctrl {
                        compatible = "marvell,mv78460-pinctrl";
                        reg = <0xd0018000 0x38>;
+                        sdio_pins: sdio-pins {
+                                marvell,pins = "mpp30", "mpp31", "mpp32",
+                                               "mpp33", "mpp34", "mpp35";
+                                marvell,function = "sd0";
+                        };
                };
                gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index b42652fd3d8c..3818a82176a2 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -66,6 +66,18 @@
                        };
                };
+                gpio_keys {
+                        compatible = "gpio-keys";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        button@1 {
+                                label = "Init Button";
+                                linux,code = <116>;
+                                gpios = <&gpio1 28 0>;
+                        };
+                };
                mdio {
                        phy0: ethernet-phy@0 {
                                reg = <0>;
@@ -121,5 +133,11 @@
                        nr-ports = <2>;
                        status = "okay";
                };
+                usb@d0050000 {
+                        status = "okay";
+                };
+                usb@d0051000 {
+                        status = "okay";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 2e37ef101c90..1443949c165e 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -30,7 +30,7 @@
        };
        mpic: interrupt-controller@d0020000 {
-              reg = <0xd0020a00 0x1d0>,
+              reg = <0xd0020a00 0x2d0>,
                    <0xd0021070 0x58>;
        };
@@ -134,5 +134,22 @@
                                dmacap,memset;
                        };
                };
+                usb@d0050000 {
+                        clocks = <&gateclk 18>;
+                };
+                usb@d0051000 {
+                        clocks = <&gateclk 19>;
+                };
+                usb@d0052000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xd0052000 0x500>;
+                        interrupts = <47>;
+                        clocks = <&gateclk 20>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 222047f1ece9..b0268a5f4b4e 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -29,6 +29,9 @@
                gpio3 = &pioD;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+                ssc2 = &ssc2;
        };
        cpus {
                cpu@0 {
@@ -88,6 +91,52 @@
                                interrupts = <20 4 0 21 4 0 22 4 0>;
                        };
+                        mmc0: mmc@fffb4000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfffb4000 0x4000>;
+                                interrupts = <10 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        ssc0: ssc@fffd0000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffd0000 0x4000>;
+                                interrupts = <14 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disable";
+                        };
+                        ssc1: ssc@fffd4000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffd4000 0x4000>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disable";
+                        };
+                        ssc2: ssc@fffd8000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffd8000 0x4000>;
+                                interrupts = <16 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+                                status = "disable";
+                        };
+                        macb0: ethernet@fffbc000 {
+                                compatible = "cdns,at91rm9200-emac", "cdns,emac";
+                                reg = <0xfffbc000 0x4000>;
+                                interrupts = <24 4 3>;
+                                phy-mode = "rmii";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb_rmii>;
+                                status = "disabled";
+                        };
                        pinctrl@fffff400 {
                                #address-cells = <1>;
                                #size-cells = <1>;
@@ -207,6 +256,115 @@
                                        };
                                };
+                                macb {
+                                        pinctrl_macb_rmii: macb_rmii-0 {
+                                                atmel,pins =
+                                                        <0 7 0x1 0x0    /* PA7 periph A */
+                                                         0 8 0x1 0x0    /* PA8 periph A */
+                                                         0 9 0x1 0x0    /* PA9 periph A */
+                                                         0 10 0x1 0x0   /* PA10 periph A */
+                                                         0 11 0x1 0x0   /* PA11 periph A */
+                                                         0 12 0x1 0x0   /* PA12 periph A */
+                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         0 16 0x1 0x0>; /* PA16 periph A */
+                                        };
+                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                                atmel,pins =
+                                                        <1 12 0x2 0x0   /* PB12 periph B */
+                                                         1 13 0x2 0x0   /* PB13 periph B */
+                                                         1 14 0x2 0x0   /* PB14 periph B */
+                                                         1 15 0x2 0x0   /* PB15 periph B */
+                                                         1 16 0x2 0x0   /* PB16 periph B */
+                                                         1 17 0x2 0x0   /* PB17 periph B */
+                                                         1 18 0x2 0x0   /* PB18 periph B */
+                                                         1 19 0x2 0x0>; /* PB19 periph B */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_clk: mmc0_clk-0 {
+                                                atmel,pins =
+                                                        <0 27 0x1 0x0>; /* PA27 periph A */
+                                        };
+                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                         0 29 0x1 0x1>; /* PA29 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <1 3 0x2 0x1    /* PB3 periph B with pullup */
+                                                         1 4 0x2 0x1    /* PB4 periph B with pullup */
+                                                         1 5 0x2 0x1>;  /* PB5 periph B with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 8 0x2 0x1    /* PA8 periph B with pullup */
+                                                         0 9 0x2 0x1>;  /* PA9 periph B with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 10 0x2 0x1   /* PA10 periph B with pullup */
+                                                         0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                         0 12 0x2 0x1>; /* PA12 periph B with pullup */
+                                        };
+                                };
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx-0 {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A */
+                                                         1 1 0x1 0x0    /* PB1 periph A */
+                                                         1 2 0x1 0x0>;  /* PB2 periph A */
+                                        };
+                                        pinctrl_ssc0_rx: ssc0_rx-0 {
+                                                atmel,pins =
+                                                        <1 3 0x1 0x0    /* PB3 periph A */
+                                                         1 4 0x1 0x0    /* PB4 periph A */
+                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                        };
+                                };
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx-0 {
+                                                atmel,pins =
+                                                        <1 6 0x1 0x0    /* PB6 periph A */
+                                                         1 7 0x1 0x0    /* PB7 periph A */
+                                                         1 8 0x1 0x0>;  /* PB8 periph A */
+                                        };
+                                        pinctrl_ssc1_rx: ssc1_rx-0 {
+                                                atmel,pins =
+                                                        <1 9 0x1 0x0    /* PB9 periph A */
+                                                         1 10 0x1 0x0   /* PB10 periph A */
+                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                        };
+                                };
+                                ssc2 {
+                                        pinctrl_ssc2_tx: ssc2_tx-0 {
+                                                atmel,pins =
+                                                        <1 12 0x1 0x0   /* PB12 periph A */
+                                                         1 13 0x1 0x0   /* PB13 periph A */
+                                                         1 14 0x1 0x0>; /* PB14 periph A */
+                                        };
+                                        pinctrl_ssc2_rx: ssc2_rx-0 {
+                                                atmel,pins =
+                                                        <1 15 0x1 0x0   /* PB15 periph A */
+                                                         1 16 0x1 0x0   /* PB16 periph A */
+                                                         1 17 0x1 0x0>; /* PB17 periph A */
+                                        };
+                                };
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 8aa48931e0a2..e586d85f8e23 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -44,6 +44,11 @@
                                status = "okay";
                        };
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
                        usb1: gadget@fffb0000 {
                                atmel,vbus-gpio = <&pioD 4 0>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 80e29c605d4e..7750f98dd764 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -324,8 +324,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x4000>;
                                interrupts = <5 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -335,8 +333,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x4000>;
                                interrupts = <6 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -346,8 +342,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x4000>;
                                interrupts = <7 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -357,8 +351,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8028000 0x4000>;
                                interrupts = <8 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
@@ -390,8 +382,9 @@
                        reg = < 0x40000000 0x10000000
                                0xffffe000 0x00000600
                                0xffffe600 0x00000200
-                                0x00100000 0x00100000
+                                0x00108000 0x00018000
                               >;
+                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 0376bf4fd66b..d400f8de4387 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -71,7 +71,10 @@
                nand0: nand@40000000 {
                        nand-bus-width = <8>;
-                        nand-ecc-mode = "soft";
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;
+                        atmel,pmecc-cap = <2>;
+                        atmel,pmecc-sector-size = <512>;
                        nand-on-flash-bbt;
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8ecca6948d81..aa98e641931f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -197,9 +197,9 @@
                                };
                                usart3 {
-                                        pinctrl_uart3: usart3-0 {
+                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <2 23 0x2 0x1   /* PC22 periph B with pullup */
+                                                        <2 22 0x2 0x1   /* PC22 periph B with pullup */
                                                         2 23 0x2 0x0>; /* PC23 periph B */
                                        };
@@ -402,8 +402,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x200>;
                                interrupts = <5 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -413,8 +411,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x200>;
                                interrupts = <6 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -424,8 +420,6 @@
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x200>;
                                interrupts = <7 4 5>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -518,7 +512,11 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x40000000 0x10000000
+                               0xffffe000 0x600         /* PMECC Registers */
+                               0xffffe600 0x200         /* PMECC Error Location Registers */
+                               0x00108000 0x18000       /* PMECC looup table in ROM code  */
                              >;
+                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 31e7be23703d..4027ac7e4502 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -26,7 +26,10 @@
        ahb {
                nand0: nand@40000000 {
                        nand-bus-width = <8>;
-                        nand-ecc-mode = "soft";
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;        /* Enable PMECC */
+                        atmel,pmecc-cap = <2>;
+                        atmel,pmecc-sector-size = <512>;
                        nand-on-flash-bbt;
                        status = "okay";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 9b72054a0bc0..aafda174a605 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,5 +1,4 @@
 /dts-v1/;
-/memreserve/ 0x0c000000 0x04000000;
 /include/ "bcm2835.dtsi"
 / {
@@ -25,3 +24,18 @@
                brcm,function = <7>; /* alt3 */
        };
 };
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+&i2c1 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+&sdhci {
+        status = "okay";
+        bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 8917550fd1bb..4bf2a8774aa7 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -63,5 +63,49 @@
                        interrupt-controller;
                        #interrupt-cells = <2>;
                };
+                i2c0: i2c@20205000 {
+                        compatible = "brcm,bcm2835-i2c";
+                        reg = <0x7e205000 0x1000>;
+                        interrupts = <2 21>;
+                        clocks = <&clk_i2c>;
+                        status = "disabled";
+                };
+                i2c1: i2c@20804000 {
+                        compatible = "brcm,bcm2835-i2c";
+                        reg = <0x7e804000 0x1000>;
+                        interrupts = <2 21>;
+                        clocks = <&clk_i2c>;
+                        status = "disabled";
+                };
+                sdhci: sdhci {
+                        compatible = "brcm,bcm2835-sdhci";
+                        reg = <0x7e300000 0x100>;
+                        interrupts = <2 30>;
+                        clocks = <&clk_mmc>;
+                        status = "disabled";
+                };
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk_mmc: mmc {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <100000000>;
+                };
+                clk_i2c: i2c {
+                        compatible = "fixed-clock";
+                        reg = <1>;
+                        #clock-cells = <0>;
+                        clock-frequency = <150000000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 37dc5a3243b8..f712fb607a42 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -15,6 +15,9 @@
        model = "DA850/AM1808/OMAP-L138 EVM";
        soc {
+                pmx_core: pinmux@1c14120 {
+                        status = "okay";
+                };
                serial0: serial@1c42000 {
                        status = "okay";
                };
@@ -24,5 +27,22 @@
                serial2: serial@1d0d000 {
                        status = "okay";
                };
+                rtc0: rtc@1c23000 {
+                        status = "okay";
+                };
+                i2c0: i2c@1c22000 {
+                        status = "okay";
+                        clock-frequency = <100000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+                };
+                wdt: wdt@1c21000 {
+                        status = "okay";
+                };
+        };
+        nand_cs3@62000000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&nand_cs3_pins>;
        };
 };
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 640ab75c20db..3ec1bda64356 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -28,14 +28,47 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x01c00000 0x400000>;
+                interrupt-parent = <&intc>;
+                pmx_core: pinmux@1c14120 {
+                        compatible = "pinctrl-single";
+                        reg = <0x14120 0x50>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,bit-per-mux;
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <0xffffffff>;
+                        status = "disabled";
+                        nand_cs3_pins: pinmux_nand_pins {
+                                pinctrl-single,bits = <
+                                        /* EMA_OE, EMA_WE */
+                                        0x1c 0x00110000  0x00ff0000
+                                        /* EMA_CS[4],EMA_CS[3]*/
+                                        0x1c 0x00000110  0x00000ff0
+                                        /*
+                                         * EMA_D[0], EMA_D[1], EMA_D[2],
+                                         * EMA_D[3], EMA_D[4], EMA_D[5],
+                                         * EMA_D[6], EMA_D[7]
+                                         */
+                                        0x24 0x11111111  0xffffffff
+                                        /* EMA_A[1], EMA_A[2] */
+                                        0x30 0x01100000  0x0ff00000
+                                >;
+                        };
+                        i2c0_pins: pinmux_i2c0_pins {
+                                pinctrl-single,bits = <
+                                        /* I2C0_SDA,I2C0_SCL */
+                                        0x10 0x00002200 0x0000ff00
+                                >;
+                        };
+                };
                serial0: serial@1c42000 {
                        compatible = "ns16550a";
                        reg = <0x42000 0x100>;
                        clock-frequency = <150000000>;
                        reg-shift = <2>;
                        interrupts = <25>;
-                        interrupt-parent = <&intc>;
                        status = "disabled";
                };
                serial1: serial@1d0c000 {
@@ -44,7 +77,6 @@
                        clock-frequency = <150000000>;
                        reg-shift = <2>;
                        interrupts = <53>;
-                        interrupt-parent = <&intc>;
                        status = "disabled";
                };
                serial2: serial@1d0d000 {
@@ -53,8 +85,40 @@
                        clock-frequency = <150000000>;
                        reg-shift = <2>;
                        interrupts = <61>;
-                        interrupt-parent = <&intc>;
                        status = "disabled";
                };
+                rtc0: rtc@1c23000 {
+                        compatible = "ti,da830-rtc";
+                        reg = <0x23000 0x1000>;
+                        interrupts = <19
+                                      19>;
+                        status = "disabled";
+                };
+                i2c0: i2c@1c22000 {
+                        compatible = "ti,davinci-i2c";
+                        reg = <0x22000 0x1000>;
+                        interrupts = <15>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                wdt: wdt@1c21000 {
+                        compatible = "ti,davinci-wdt";
+                        reg = <0x21000 0x1000>;
+                        status = "disabled";
+                };
+        };
+        nand_cs3@62000000 {
+                compatible = "ti,davinci-nand";
+                reg = <0x62000000 0x807ff
+                       0x68000000 0x8000>;
+                ti,davinci-chipselect = <1>;
+                ti,davinci-mask-ale = <0>;
+                ti,davinci-mask-cle = <0>;
+                ti,davinci-mask-chipsel = <0>;
+                ti,davinci-ecc-mode = "hw";
+                ti,davinci-ecc-bits = <4>;
+                ti,davinci-nand-use-bbt;
+                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 63f2fbcfe819..69140ba99f46 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -170,10 +170,9 @@
                        gpio-bank = <8>;
                };
-                pinctrl@80157000 {
+                pinctrl {
-                        // This is actually the PRCMU base address
+                        compatible = "stericsson,nmk-pinctrl";
-                        reg = <0x80157000 0x2000>;
+                        prcm = <&prcmu>;
-                        compatible = "stericsson,nmk_pinctrl";
                };
                usb@a03e0000 {
@@ -190,9 +189,10 @@
                        interrupts = <0 25 0x4>;
                };
-                prcmu@80157000 {
+                prcmu: prcmu@80157000 {
                        compatible = "stericsson,db8500-prcmu";
                        reg = <0x80157000 0x1000>;
+                        reg-names = "prcmu";
                        interrupts = <0 47 0x4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index cdee96fca6e2..7e3065abd751 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -17,12 +17,33 @@
        leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_gpio_18>;
+                pinctrl-names = "default";
                power {
                        label = "Power";
                        gpios = <&gpio0 18 1>;
                        linux,default-trigger = "default-on";
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 1 0>;
+                };
+        };
 };
 &uart0 { status = "okay"; };
@@ -47,9 +68,14 @@
 };
 &pinctrl {
-        pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>;
+        pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>;
        pinctrl-names = "default";
+        pmx_gpio_1: pmx-gpio-1 {
+                marvell,pins = "mpp1";
+                marvell,function = "gpio";
+        };
        pmx_gpio_12: pmx-gpio-12 {
                marvell,pins = "mpp12";
                marvell,function = "gpio";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 42eac1ff3cc8..67dbe20868a2 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -55,7 +55,7 @@
                        reg = <0x12000 0x100>;
                        reg-shift = <2>;
                        interrupts = <7>;
-                        clock-frequency = <166666667>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
@@ -64,7 +64,7 @@
                        reg = <0x12100 0x100>;
                        reg-shift = <2>;
                        interrupts = <8>;
-                        clock-frequency = <166666667>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
@@ -73,7 +73,7 @@
                        reg = <0x12000 0x100>;
                        reg-shift = <2>;
                        interrupts = <9>;
-                        clock-frequency = <166666667>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
@@ -82,7 +82,7 @@
                        reg = <0x12100 0x100>;
                        reg-shift = <2>;
                        interrupts = <10>;
-                        clock-frequency = <166666667>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
@@ -93,6 +93,7 @@
                        reg = <0xd0400 0x20>;
                        ngpios = <32>;
                        interrupt-controller;
+                        #interrupt-cells = <2>;
                        interrupts = <12>, <13>, <14>, <60>;
                };
@@ -103,6 +104,7 @@
                        reg = <0xd0420 0x20>;
                        ngpios = <32>;
                        interrupt-controller;
+                        #interrupt-cells = <2>;
                        interrupts = <61>;
                };
@@ -154,6 +156,22 @@
                        status = "disabled";
                };
+                ehci0: usb-host@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <24>;
+                        clocks = <&gate_clk 0>;
+                        status = "okay";
+                };
+                ehci1: usb-host@51000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x51000 0x1000>;
+                        interrupts = <25>;
+                        clocks = <&gate_clk 1>;
+                        status = "okay";
+                };
                sdio0: sdio@92000 {
                        compatible = "marvell,dove-sdhci";
                        reg = <0x92000 0x100>;
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 297e3baba71c..b9b3241f173b 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -21,6 +21,6 @@
        };
        chosen {
-                bootargs = "console=ttyS1,115200n81";
+                bootargs = "console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096";
        };
 };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index eb504a6c0f4a..c8a8c08b48dd 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -15,11 +15,18 @@
        interrupt-parent = <&gic>;
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                        reg = <0>;
                };
                cpu@1 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                        reg = <1>;
                };
        };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index e31bfc4a6f09..2feffc70814c 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -48,13 +48,13 @@
        };
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
        };
        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>;
@@ -66,7 +66,7 @@
        };
        pinctrl_2: pinctrl@03860000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x03860000 0x1000>;
        };
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 8e6115adcd97..099cec79e2ae 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -661,7 +661,7 @@
                sd4_bus8: sd4-bus-width8 {
                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <3>;
+                        samsung,pin-function = <4>;
                        samsung,pin-pud = <4>;
                        samsung,pin-drv = <3>;
                };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 179a62e46c9d..9a8780694909 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -37,13 +37,13 @@
        };
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
        };
        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>;
@@ -55,14 +55,14 @@
        };
        pinctrl_2: pinctrl@03860000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x03860000 0x1000>;
                interrupt-parent = <&combiner>;
                interrupts = <10 0>;
        };
        pinctrl_3: pinctrl@106E0000 {
-                compatible = "samsung,pinctrl-exynos4x12";
+                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x106E0000 0x1000>;
                interrupts = <0 72 0>;
        };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index e05b18f3c33d..1b8d4106d338 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -49,6 +49,11 @@
                        compatible = "samsung,s524ad0xd1";
                        reg = <0x51>;
                };
+                wm8994: wm8994@1a {
+                         compatible = "wlf,wm8994";
+                         reg = <0x1a>;
+                };
        };
        i2c@121D0000 {
@@ -146,6 +151,7 @@
                        reg = <0>;
                        bus-width = <4>;
                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        disable-wp;
                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
@@ -204,4 +210,25 @@
                samsung,mfc-r = <0x43000000 0x800000>;
                samsung,mfc-l = <0x51000000 0x800000>;
        };
+        i2s0: i2s@03830000 {
+                gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>,
+                        <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
+                        <&gpz 6 2 0 0>;
+        };
+        i2s1: i2s@12D60000 {
+                status = "disabled";
+        };
+        i2s2: i2s@12D70000 {
+                status = "disabled";
+        };
+        sound {
+                compatible = "samsung,smdk-wm8994";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&wm8994>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 3acf594ea60b..b1ac73e21c80 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -211,8 +211,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
                interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                dmas = <&pdma0 5
-                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                        &pdma0 4>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -221,8 +222,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d30000 0x100>;
                interrupts = <0 67 0>;
-                tx-dma-channel = <&pdma1 5>; /* preliminary */
+                dmas = <&pdma1 5
-                rx-dma-channel = <&pdma1 4>; /* preliminary */
+                        &pdma1 4>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -231,8 +233,9 @@
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d40000 0x100>;
                interrupts = <0 68 0>;
-                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                dmas = <&pdma0 7
-                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                        &pdma0 6>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
        };
@@ -269,6 +272,35 @@
                #size-cells = <0>;
        };
+        i2s0: i2s@03830000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x03830000 0x100>;
+                dmas = <&pdma0 10
+                        &pdma0 9
+                        &pdma0 8>;
+                dma-names = "tx", "rx", "tx-sec";
+                samsung,supports-6ch;
+                samsung,supports-rstclr;
+                samsung,supports-secdai;
+                samsung,idma-addr = <0x03000000>;
+        };
+        i2s1: i2s@12D60000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x12D60000 0x100>;
+                dmas = <&pdma1 12
+                        &pdma1 11>;
+                dma-names = "tx", "rx";
+        };
+        i2s2: i2s@12D70000 {
+                compatible = "samsung,i2s-v5";
+                reg = <0x12D70000 0x100>;
+                dmas = <&pdma0 12
+                        &pdma0 11>;
+                dma-names = "tx", "rx";
+        };
        amba {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -280,24 +312,36 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121A0000 0x1000>;
                        interrupts = <0 34 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
                pdma1: pdma@121B0000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121B0000 0x1000>;
                        interrupts = <0 35 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                };
                mdma0: mdma@10800000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x10800000 0x1000>;
                        interrupts = <0 33 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
                };
                mdma1: mdma@11C10000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x11C10000 0x1000>;
                        interrupts = <0 124 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
                };
        };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 024269de8ee5..5f3562ad6746 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -86,7 +86,7 @@
        };
        pinctrl {
-                compatible = "samsung,pinctrl-exynos5440";
+                compatible = "samsung,exynos5440-pinctrl";
                reg = <0xE0000 0x1000>;
                interrupt-controller;
                #interrupt-cells = <2>;
@@ -154,6 +154,6 @@
        rtc {
                compatible = "samsung,s3c6410-rtc";
                reg = <0x130000 0x1000>;
-                interrupts = <0 16 0>, <0 17 0>;
+                interrupts = <0 17 0>, <0 16 0>;
        };
 };
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 5927a8df5625..6aad34ad9517 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -37,6 +37,16 @@
                        next-level-cache = <&L2>;
                        clocks = <&a9pll>;
                        clock-names = "cpu";
+                        operating-points = <
+                                /* kHz    ignored */
+                                 1300000  1000000
+                                 1200000  1000000
+                                 1100000  1000000
+                                  800000  1000000
+                                  400000  1000000
+                                  200000  1000000
+                        >;
+                        clock-latency = <100000>;
                };
                cpu@901 {
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 65415c598a5e..56afcf41aae0 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -391,7 +391,9 @@
                        };
                        lradc@80050000 {
+                                compatible = "fsl,imx23-lradc";
                                reg = <0x80050000 0x2000>;
+                                interrupts = <36 37 38 39 40 41 42 43 44>;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index d81f8a0b9794..1a9d0491cdce 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -19,26 +19,18 @@
        memory {
                reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
        };
+};
-        soc {
+&uart1 {
-                aips@43f00000 {
+        status = "okay";
-                        uart1: serial@43f90000 {
+};
-                                status = "okay";
-                        };
-                };
-                spba@50000000 {
+&fec {
-                        fec: ethernet@50038000 {
+        phy-mode = "rmii";
-                                status = "okay";
+        status = "okay";
-                                phy-mode = "rmii";
+};
-                        };
-                };
-                emi@80000000 {
+&nfc {
-                        nand@bb000000 {
+        nand-on-flash-bbt;
-                                nand-on-flash-bbt;
+        status = "okay";
-                                status = "okay";
-                        };
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
new file mode 100644
index 000000000000..a02a860afd18
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx25.dtsi"
+/ {
+        model = "Freescale i.MX25 Product Development Kit";
+        compatible = "fsl,imx25-pdk", "fsl,imx25";
+        memory {
+                reg = <0x80000000 0x4000000>;
+        };
+};
+&uart1 {
+        status = "okay";
+};
+&fec {
+        phy-mode = "rmii";
+        status = "okay";
+};
+&nfc {
+        nand-on-flash-bbt;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index e1b13ebc96d6..94f33059158a 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -499,7 +499,7 @@
                        reg = <0x80000000 0x3b002000>;
                        ranges;
-                        nand@bb000000 {
+                        nfc: nand@bb000000 {
                                #address-cells = <1>;
                                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index c0327c054de2..b464c807d8d9 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -32,58 +32,54 @@
                        clock-frequency = <0>;
                };
        };
+};
-        soc {
+&uart1 {
-                aipi@10000000 {
+        status = "okay";
-                        serial@1000a000 {
+};
-                                status = "okay";
-                        };
-                        ethernet@1002b000 {
+&fec {
-                                status = "okay";
+        status = "okay";
-                        };
+};
-                };
-                nand@d8000000 {
+&nfc {
-                        status = "okay";
+        status = "okay";
-                        nand-bus-width = <16>;
+        nand-bus-width = <16>;
-                        nand-ecc-mode = "hw";
+        nand-ecc-mode = "hw";
-                        nand-on-flash-bbt;
+        nand-on-flash-bbt;
-                        partition@0 {
+        partition@0 {
-                                label = "u-boot";
+                label = "u-boot";
-                                reg = <0x0 0x100000>;
+                reg = <0x0 0x100000>;
-                        };
+        };
-                        partition@100000 {
+        partition@100000 {
-                                label = "env";
+                label = "env";
-                                reg = <0x100000 0x80000>;
+                reg = <0x100000 0x80000>;
-                        };
+        };
-                        partition@180000 {
+        partition@180000 {
-                                label = "env2";
+                label = "env2";
-                                reg = <0x180000 0x80000>;
+                reg = <0x180000 0x80000>;
-                        };
+        };
-                        partition@200000 {
+        partition@200000 {
-                                label = "firmware";
+                label = "firmware";
-                                reg = <0x200000 0x80000>;
+                reg = <0x200000 0x80000>;
-                        };
+        };
-                        partition@280000 {
+        partition@280000 {
-                                label = "dtb";
+                label = "dtb";
-                                reg = <0x280000 0x80000>;
+                reg = <0x280000 0x80000>;
-                        };
+        };
-                        partition@300000 {
+        partition@300000 {
-                                label = "kernel";
+                label = "kernel";
-                                reg = <0x300000 0x500000>;
+                reg = <0x300000 0x500000>;
-                        };
+        };
-                        partition@800000 {
+        partition@800000 {
-                                label = "rootfs";
+                label = "rootfs";
-                                reg = <0x800000 0xf800000>;
+                reg = <0x800000 0xf800000>;
-                        };
-                };
        };
 };
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-pdk.dts
index fa04c7b18bcb..41cd1105608e 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -13,25 +13,19 @@
 /include/ "imx27.dtsi"
 / {
-        model = "mx27_3ds";
+        model = "Freescale i.MX27 Product Development Kit";
-        compatible = "freescale,imx27-3ds", "fsl,imx27";
+        compatible = "fsl,imx27-pdk", "fsl,imx27";
        memory {
                reg = <0x0 0x0>;
        };
+};
-        soc {
+&uart1 {
-                aipi@10000000 { /* aipi1 */
+        fsl,uart-has-rtscts;
-                        uart1: serial@1000a000 {
+        status = "okay";
-                                fsl,uart-has-rtscts;
+};
-                                status = "okay";
-                        };
-                };
-                aipi@10020000 { /* aipi2 */
+&fec {
-                        ethernet@1002b000 {
+        status = "okay";
-                                status = "okay";
-                        };
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
new file mode 100644
index 000000000000..c2ef3a3d655e
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+/ {
+        model = "Crystalfontz CFA-10037 Board";
+        compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10037>;
+                                hog_pins_cfa10037: hog-10037@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio2 21 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index bdc80a4453dd..a0d3e9f1738e 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -23,69 +23,120 @@
                apbh@80000000 {
                        pinctrl@80018000 {
                                pinctrl-names = "default", "default";
-                                pinctrl-1 = <&hog_pins_cfa10049>;
+                                pinctrl-1 = <&hog_pins_cfa10049
+                                        &hog_pins_cfa10049_pullup>;
                                hog_pins_cfa10049: hog-10049@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x1153 /* MX28_PAD_LCD_D22__GPIO_1_21 */
                                                0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
                                                0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
                                                0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
+                                                0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
                                        >;
                                        fsl,drive-strength = <0>;
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <0>;
                                };
-                                spi3_pins_cfa10049: spi3-cfa10049@0 {
+                                hog_pins_cfa10049_pullup: hog-10049-pullup@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
-                                                0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
+                                                0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
-                                                0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
+                                                0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
-                                                0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
+                                                0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
-                                                0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+                                                0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
-                                                0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
                                        >;
-                                        fsl,drive-strength = <1>;
+                                        fsl,drive-strength = <0>;
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <1>;
                                };
-                        };
-                        ssp3: ssp@80016000 {
+                                spi2_pins_cfa10049: spi2-cfa10049@0 {
-                                compatible = "fsl,imx28-spi";
+                                        reg = <0>;
-                                pinctrl-names = "default";
+                                        fsl,pinmux-ids = <
-                                pinctrl-0 = <&spi3_pins_cfa10049>;
+                                                0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
-                                status = "okay";
+                                                0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
+                                                0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
-                                gpio5: gpio5@0 {
+                                spi3_pins_cfa10049: spi3-cfa10049@0 {
-                                        compatible = "fairchild,74hc595";
-                                        gpio-controller;
-                                        #gpio-cells = <2>;
                                        reg = <0>;
-                                        registers-number = <2>;
+                                        fsl,pinmux-ids = <
-                                        spi-max-frequency = <100000>;
+                                                0x0183 /* MX28_PAD_GPMI_RDN__GPIO_0_24 */
+                                                0x01c3 /* MX28_PAD_GPMI_RESETN__GPIO_0_28 */
+                                                0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
+                                                0x01a3 /* MX28_PAD_GPMI_ALE__GPIO_0_26 */
+                                                0x01b3 /* MX28_PAD_GPMI_CLE__GPIO_0_27 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
                                };
-                                gpio6: gpio6@1 {
+                                lcdif_18bit_pins_cfa10049: lcdif-18bit@0 {
-                                        compatible = "fairchild,74hc595";
+                                        reg = <0>;
-                                        gpio-controller;
+                                        fsl,pinmux-ids = <
-                                        #gpio-cells = <2>;
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
-                                        reg = <1>;
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
-                                        registers-number = <4>;
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
-                                        spi-max-frequency = <100000>;
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
                                };
-                                dac0: dh2228@2 {
+                                lcdif_pins_cfa10049: lcdif-evk@0 {
-                                        compatible = "rohm,dh2228fv";
+                                        reg = <0>;
-                                        reg = <2>;
+                                        fsl,pinmux-ids = <
-                                        spi-max-frequency = <100000>;
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
                                };
                        };
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10049
+                                             &lcdif_pins_cfa10049>;
+                                status = "okay";
+                        };
                };
                apbx@80040000 {
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
                        i2c1: i2c@8005a000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c1_pins_a>;
@@ -113,6 +164,19 @@
                                i2c@3 {
                                        reg = <3>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pca9555: pca9555@20 {
+                                                compatible = "nxp,pca9555";
+                                                interrupt-parent = <&gpio2>;
+                                                interrupts = <19 0x2>;
+                                                gpio-controller;
+                                                #gpio-cells = <2>;
+                                                interrupt-controller;
+                                                #interrupt-cells = <2>;
+                                                reg = <0x20>;
+                                        };
                                };
                        };
@@ -153,4 +217,92 @@
                        status = "okay";
                };
        };
+        spi2 {
+                compatible = "spi-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_pins_cfa10049>;
+                status = "okay";
+                gpio-sck = <&gpio2 16 0>;
+                gpio-mosi = <&gpio2 17 0>;
+                gpio-miso = <&gpio2 18 0>;
+                cs-gpios = <&gpio3 23 0>;
+                num-chipselects = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                hx8357: hx8357@0 {
+                        compatible = "himax,hx8357b", "himax,hx8357";
+                        reg = <0>;
+                        spi-max-frequency = <100000>;
+                        spi-cpol;
+                        spi-cpha;
+                        gpios-reset = <&gpio3 30 0>;
+                        im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>;
+                };
+        };
+        spi3 {
+                compatible = "spi-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi3_pins_cfa10049>;
+                status = "okay";
+                gpio-sck = <&gpio0 24 0>;
+                gpio-mosi = <&gpio0 28 0>;
+                cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>;
+                num-chipselects = <3>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                gpio5: gpio5@0 {
+                        compatible = "fairchild,74hc595";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        reg = <0>;
+                        registers-number = <2>;
+                        spi-max-frequency = <100000>;
+                };
+                gpio6: gpio6@1 {
+                        compatible = "fairchild,74hc595";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        reg = <1>;
+                        registers-number = <4>;
+                        spi-max-frequency = <100000>;
+                };
+                dac0: dh2228@2 {
+                        compatible = "rohm,dh2228fv";
+                        reg = <2>;
+                        spi-max-frequency = <100000>;
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                rotary_button {
+                        label = "rotary_button";
+                        gpios = <&gpio3 26 1>;
+                        debounce-interval = <10>;
+                        linux,code = <28>;
+                };
+        };
+        rotary {
+                compatible = "rotary-encoder";
+                gpios = <&gpio3 24 1>, <&gpio3 25 1>;
+                linux,axis = <1>; /* REL_Y */
+                rotary-encoder,relative-axis;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 3bab6b00c52d..6ce3d17c3a29 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -177,6 +177,7 @@
                        lradc@80050000 {
                                status = "okay";
+                                fsl,lradc-touchscreen-wires = <4>;
                        };
                        duart: serial@80074000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 13b7053d799e..7ba49662b9bc 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -502,6 +502,16 @@
                                        fsl,pull-up = <0>;
                                };
+                                pwm3_pins_b: pwm3@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                pwm4_pins_a: pwm4@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 7f67402328d3..9ac6f6ba1d64 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -19,13 +19,9 @@
        memory {
                reg = <0x80000000 0x8000000>; /* 128M */
        };
+};
-        soc {
+&uart5 {
-                aips@43f00000 { /* AIPS1 */
+        fsl,uart-has-rtscts;
-                        uart5: serial@43fb4000 {
+        status = "okay";
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index eef7099f3e3c..454c2d175402 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -45,6 +45,8 @@
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x43f90000 0x4000>;
                                interrupts = <45>;
+                                clocks = <&clks 10>, <&clks 30>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -52,12 +54,16 @@
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x43f94000 0x4000>;
                                interrupts = <32>;
+                                clocks = <&clks 10>, <&clks 31>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
                        uart4: serial@43fb0000 {
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x43fb0000 0x4000>;
+                                clocks = <&clks 10>, <&clks 49>;
+                                clock-names = "ipg", "per";
                                interrupts = <46>;
                                status = "disabled";
                        };
@@ -66,6 +72,8 @@
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x43fb4000 0x4000>;
                                interrupts = <47>;
+                                clocks = <&clks 10>, <&clks 50>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
                };
@@ -81,8 +89,17 @@
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x5000c000 0x4000>;
                                interrupts = <18>;
+                                clocks = <&clks 10>, <&clks 48>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
+                        clks: ccm@53f80000{
+                                compatible = "fsl,imx31-ccm";
+                                reg = <0x53f80000 0x4000>;
+                                interrupts = <0 31 0x04 0 53 0x04>;
+                                #clock-cells = <1>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
new file mode 100644
index 000000000000..92d3a66a69e2
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2012 Armadeus Systems - <support@armadeus.com>
+ * Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
+ *
+ * Based on mx51-babbage.dts
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx51.dtsi"
+/ {
+        model = "Armadeus Systems APF51 module";
+        compatible = "armadeus,imx51-apf51", "fsl,imx51";
+        memory {
+                reg = <0x90000000 0x20000000>;
+        };
+        clocks {
+                ckih1 {
+                        clock-frequency = <0>;
+                };
+                osc {
+                        clock-frequency = <33554432>;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_2>;
+        phy-mode = "mii";
+        phy-reset-gpios = <&gpio3 0 0>;
+        phy-reset-duration = <1>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_2>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 567e7ee72f91..aab6e43219af 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,239 +21,20 @@
                reg = <0x90000000 0x20000000>;
        };
-        soc {
+        display@di0 {
-                display@di0 {
+                compatible = "fsl,imx-parallel-display";
-                        compatible = "fsl,imx-parallel-display";
+                crtcs = <&ipu 0>;
-                        crtcs = <&ipu 0>;
+                interface-pix-fmt = "rgb24";
-                        interface-pix-fmt = "rgb24";
+                pinctrl-names = "default";
-                        pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp1_1>;
-                        pinctrl-0 = <&pinctrl_ipu_disp1_1>;
+        };
-                };
-                display@di1 {
-                        compatible = "fsl,imx-parallel-display";
-                        crtcs = <&ipu 1>;
-                        interface-pix-fmt = "rgb565";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
-                };
-                aips@70000000 { /* aips-1 */
-                        spba@70000000 {
-                                esdhc@70004000 { /* ESDHC1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
-                                        fsl,cd-controller;
-                                        fsl,wp-controller;
-                                        status = "okay";
-                                };
-                                esdhc@70008000 { /* ESDHC2 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
-                                        cd-gpios = <&gpio1 6 0>;
-                                        wp-gpios = <&gpio1 5 0>;
-                                        status = "okay";
-                                };
-                                uart3: serial@7000c000 {
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_uart3_1>;
-                                        fsl,uart-has-rtscts;
-                                        status = "okay";
-                                };
-                                ecspi@70010000 { /* ECSPI1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
-                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
-                                        status = "okay";
-                                        pmic: mc13892@0 {
-                                                #address-cells = <1>;
-                                                #size-cells = <0>;
-                                                compatible = "fsl,mc13892";
-                                                spi-max-frequency = <6000000>;
-                                                reg = <0>;
-                                                interrupt-parent = <&gpio1>;
-                                                interrupts = <8 0x4>;
-                                                regulators {
-                                                        sw1_reg: sw1 {
-                                                                regulator-min-microvolt = <600000>;
-                                                                regulator-max-microvolt = <1375000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        sw2_reg: sw2 {
-                                                                regulator-min-microvolt = <900000>;
-                                                                regulator-max-microvolt = <1850000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        sw3_reg: sw3 {
-                                                                regulator-min-microvolt = <1100000>;
-                                                                regulator-max-microvolt = <1850000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        sw4_reg: sw4 {
-                                                                regulator-min-microvolt = <1100000>;
-                                                                regulator-max-microvolt = <1850000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        vpll_reg: vpll {
-                                                                regulator-min-microvolt = <1050000>;
-                                                                regulator-max-microvolt = <1800000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        vdig_reg: vdig {
-                                                                regulator-min-microvolt = <1650000>;
-                                                                regulator-max-microvolt = <1650000>;
-                                                                regulator-boot-on;
-                                                        };
-                                                        vsd_reg: vsd {
-                                                                regulator-min-microvolt = <1800000>;
-                                                                regulator-max-microvolt = <3150000>;
-                                                        };
-                                                        vusb2_reg: vusb2 {
-                                                                regulator-min-microvolt = <2400000>;
-                                                                regulator-max-microvolt = <2775000>;
-                                                                regulator-boot-on;
-                                                                regulator-always-on;
-                                                        };
-                                                        vvideo_reg: vvideo {
-                                                                regulator-min-microvolt = <2775000>;
-                                                                regulator-max-microvolt = <2775000>;
-                                                        };
-                                                        vaudio_reg: vaudio {
-                                                                regulator-min-microvolt = <2300000>;
-                                                                regulator-max-microvolt = <3000000>;
-                                                        };
-                                                        vcam_reg: vcam {
-                                                                regulator-min-microvolt = <2500000>;
-                                                                regulator-max-microvolt = <3000000>;
-                                                        };
-                                                        vgen1_reg: vgen1 {
-                                                                regulator-min-microvolt = <1200000>;
-                                                                regulator-max-microvolt = <1200000>;
-                                                        };
-                                                        vgen2_reg: vgen2 {
-                                                                regulator-min-microvolt = <1200000>;
-                                                                regulator-max-microvolt = <3150000>;
-                                                                regulator-always-on;
-                                                        };
-                                                        vgen3_reg: vgen3 {
-                                                                regulator-min-microvolt = <1800000>;
-                                                                regulator-max-microvolt = <2900000>;
-                                                                regulator-always-on;
-                                                        };
-                                                };
-                                        };
-                                        flash: at45db321d@1 {
-                                                #address-cells = <1>;
-                                                #size-cells = <1>;
-                                                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
-                                                spi-max-frequency = <25000000>;
-                                                reg = <1>;
-                                                partition@0 {
-                                                        label = "U-Boot";
-                                                        reg = <0x0 0x40000>;
-                                                        read-only;
-                                                };
-                                                partition@40000 {
-                                                        label = "Kernel";
-                                                        reg = <0x40000 0x3c0000>;
-                                                };
-                                        };
-                                };
-                                ssi2: ssi@70014000 {
-                                        fsl,mode = "i2s-slave";
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@73fa8000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
-                                                        697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
-                                                        737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
-                                                        740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
-                                                        121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
-                                                        402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
-                                                        405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
-                                                >;
-                                        };
-                                };
-                        };
-                        uart1: serial@73fbc000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart1_1>;
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-                        uart2: serial@73fc0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart2_1>;
-                                status = "okay";
-                        };
-                };
-                aips@80000000 { /* aips-2 */
-                        i2c@83fc4000 { /* I2C2 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c2_1>;
-                                status = "okay";
-                                sgtl5000: codec@0a {
-                                        compatible = "fsl,sgtl5000";
-                                        reg = <0x0a>;
-                                        clock-frequency = <26000000>;
-                                        VDDA-supply = <&vdig_reg>;
-                                        VDDIO-supply = <&vvideo_reg>;
-                                };
-                        };
-                        audmux@83fd0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_audmux_1>;
-                                status = "okay";
-                        };
-                        ethernet@83fec000 {
+        display@di1 {
-                                pinctrl-names = "default";
+                compatible = "fsl,imx-parallel-display";
-                                pinctrl-0 = <&pinctrl_fec_1>;
+                crtcs = <&ipu 1>;
-                                phy-mode = "mii";
+                interface-pix-fmt = "rgb565";
-                                status = "okay";
+                pinctrl-names = "default";
-                        };
+                pinctrl-0 = <&pinctrl_ipu_disp2_1>;
-                };
        };
        gpio-keys {
@@ -281,3 +62,236 @@
                mux-ext-port = <3>;
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        fsl,cd-controller;
+        fsl,wp-controller;
+        status = "okay";
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        cd-gpios = <&gpio1 6 0>;
+        wp-gpios = <&gpio1 5 0>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
+        status = "okay";
+        pmic: mc13892@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13892";
+                spi-max-frequency = <6000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <8 0x4>;
+                regulators {
+                        sw1_reg: sw1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1375000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3_reg: sw3 {
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vpll_reg: vpll {
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vdig_reg: vdig {
+                                regulator-min-microvolt = <1650000>;
+                                regulator-max-microvolt = <1650000>;
+                                regulator-boot-on;
+                        };
+                        vsd_reg: vsd {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3150000>;
+                        };
+                        vusb2_reg: vusb2 {
+                                regulator-min-microvolt = <2400000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vvideo_reg: vvideo {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                        };
+                        vaudio_reg: vaudio {
+                                regulator-min-microvolt = <2300000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                        vcam_reg: vcam {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3150000>;
+                                regulator-always-on;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <2900000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+        flash: at45db321d@1 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+                spi-max-frequency = <25000000>;
+                reg = <1>;
+                partition@0 {
+                        label = "U-Boot";
+                        reg = <0x0 0x40000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "Kernel";
+                        reg = <0x40000 0x3c0000>;
+                };
+        };
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
+                                697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
+                                737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
+                                740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
+                                121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
+                                402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+                                405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_1>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clock-frequency = <26000000>;
+                VDDA-supply = <&vdig_reg>;
+                VDDIO-supply = <&vvideo_reg>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "mii";
+        status = "okay";
+};
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp_1>;
+        linux,keymap = <0x00000067      /* KEY_UP */
+                        0x0001006c      /* KEY_DOWN */
+                        0x00020072      /* KEY_VOLUMEDOWN */
+                        0x00030066      /* KEY_HOME */
+                        0x0100006a      /* KEY_RIGHT */
+                        0x01010069      /* KEY_LEFT */
+                        0x0102001c      /* KEY_ENTER */
+                        0x01030073      /* KEY_VOLUMEUP */
+                        0x02000040      /* KEY_F6 */
+                        0x02010042      /* KEY_F8 */
+                        0x02020043      /* KEY_F9 */
+                        0x02030044      /* KEY_F10 */
+                        0x0300003b      /* KEY_F1 */
+                        0x0301003c      /* KEY_F2 */
+                        0x0302003d      /* KEY_F3 */
+                        0x03030074>;    /* KEY_POWER */
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1f5d45eff45e..fcf035bf7c5a 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -221,6 +221,14 @@
                                #interrupt-cells = <2>;
                        };
+                        kpp: kpp@73f94000 {
+                                compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
+                                reg = <0x73f94000 0x4000>;
+                                interrupts = <60>;
+                                clocks = <&clks 0>;
+                                status = "disabled";
+                        };
                        wdog1: wdog@73f98000 {
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f98000 0x4000>;
@@ -273,6 +281,29 @@
                                                        260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
                                                >;
                                        };
+                                        pinctrl_fec_2: fecgrp-2 {
+                                                fsl,pins = <
+                                                        589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
+                                                        592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
+                                                        594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
+                                                        596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
+                                                        598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
+                                                        602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
+                                                        604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
+                                                        609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
+                                                        618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
+                                                        623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
+                                                        628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
+                                                        634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
+                                                        639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
+                                                        644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
+                                                        649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
+                                                        653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
+                                                        657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
+                                                        662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
+                                                >;
+                                        };
                                };
                                ecspi1 {
@@ -409,6 +440,28 @@
                                                        49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
                                                >;
                                        };
+                                        pinctrl_uart3_2: uart3grp-2 {
+                                                fsl,pins = <
+                                                        434 0x1c5       /* MX51_PAD_UART3_RXD__UART3_RXD */
+                                                        430 0x1c5       /* MX51_PAD_UART3_TXD__UART3_TXD */
+                                                >;
+                                        };
+                                };
+                                kpp {
+                                        pinctrl_kpp_1: kppgrp-1 {
+                                                fsl,pins = <
+                                                        438 0xe0        /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
+                                                        439 0xe0        /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
+                                                        440 0xe0        /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
+                                                        441 0xe0        /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
+                                                        442 0xe8        /* MX51_PAD_KEY_COL0__KEY_COL0 */
+                                                        444 0xe8        /* MX51_PAD_KEY_COL1__KEY_COL1 */
+                                                        446 0xe8        /* MX51_PAD_KEY_COL2__KEY_COL2 */
+                                                        448 0xe8        /* MX51_PAD_KEY_COL3__KEY_COL3 */
+                                                >;
+                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4be76f223526..e049fd0319e8 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -21,72 +21,6 @@
                reg = <0x70000000 0x40000000>;
        };
-        soc {
-                aips@50000000 { /* AIPS1 */
-                        spba@50000000 {
-                                esdhc@50004000 { /* ESDHC1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc1_2>;
-                                        cd-gpios = <&gpio1 1 0>;
-                                        wp-gpios = <&gpio1 9 0>;
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@53fa8000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
-                                                        1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
-                                                        486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
-                                                        739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
-                                                        218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
-                                                        226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
-                                                        233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
-                                                        241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
-                                                        429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
-                                                        435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
-                                                        441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
-                                                        448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
-                                                        456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
-                                                        464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
-                                                        471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
-                                                        477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
-                                                        492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
-                                                        500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
-                                                        508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
-                                                        516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
-                                                        524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
-                                                        532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
-                                                        540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
-                                                        548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
-                                                        637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
-                                                        642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
-                                                        647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
-                                                        652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
-                                                        657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
-                                                        662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
-                                                        667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
-                                                        611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
-                                                        616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
-                                                        607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
-                                                >;
-                                        };
-                                };
-                        };
-                        uart1: serial@53fbc000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart1_2>;
-                                status = "okay";
-                        };
-                };
-        };
        eim-cs1@f4000000 {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -162,3 +96,63 @@
                };
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        cd-gpios = <&gpio1 1 0>;
+        wp-gpios = <&gpio1 9 0>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
+                                1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
+                                486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
+                                739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
+                                218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+                                226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+                                233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+                                241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+                                429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+                                435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+                                441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+                                448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+                                456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+                                464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+                                471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+                                477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+                                492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+                                500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+                                508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+                                516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+                                524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+                                532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+                                540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+                                548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+                                637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+                                642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+                                647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+                                652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+                                657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+                                662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+                                667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+                                611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+                                616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+                                607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index a124d1e25258..85a89b52f9b8 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -21,107 +21,6 @@
                reg = <0x70000000 0x80000000>;
        };
-        soc {
-                aips@50000000 { /* AIPS1 */
-                        spba@50000000 {
-                                esdhc@50004000 { /* ESDHC1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
-                                        cd-gpios = <&gpio3 13 0>;
-                                        wp-gpios = <&gpio3 14 0>;
-                                        status = "okay";
-                                };
-                                ecspi@50010000 { /* ECSPI1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
-                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
-                                        status = "okay";
-                                        flash: at45db321d@1 {
-                                                #address-cells = <1>;
-                                                #size-cells = <1>;
-                                                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
-                                                spi-max-frequency = <25000000>;
-                                                reg = <1>;
-                                                partition@0 {
-                                                        label = "U-Boot";
-                                                        reg = <0x0 0x40000>;
-                                                        read-only;
-                                                };
-                                                partition@40000 {
-                                                        label = "Kernel";
-                                                        reg = <0x40000 0x3c0000>;
-                                                };
-                                        };
-                                };
-                                esdhc@50020000 { /* ESDHC3 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
-                                        cd-gpios = <&gpio3 11 0>;
-                                        wp-gpios = <&gpio3 12 0>;
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@53fa8000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
-                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
-                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
-                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
-                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                                        705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
-                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
-                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
-                                                >;
-                                        };
-                                };
-                        };
-                        uart1: serial@53fbc000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart1_1>;
-                                status = "okay";
-                        };
-                };
-                aips@60000000 { /* AIPS2 */
-                        i2c@63fc4000 { /* I2C2 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c2_1>;
-                                status = "okay";
-                                pmic: mc13892@08 {
-                                        compatible = "fsl,mc13892", "fsl,mc13xxx";
-                                        reg = <0x08>;
-                                };
-                                codec: sgtl5000@0a {
-                                        compatible = "fsl,sgtl5000";
-                                        reg = <0x0a>;
-                                };
-                        };
-                        ethernet@63fec000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_fec_1>;
-                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio7 6 0>;
-                                status = "okay";
-                        };
-                };
-        };
        leds {
                compatible = "gpio-leds";
@@ -132,3 +31,96 @@
                };
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio3 13 0>;
+        wp-gpios = <&gpio3 14 0>;
+        status = "okay";
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
+        status = "okay";
+        flash: at45db321d@1 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+                spi-max-frequency = <25000000>;
+                reg = <1>;
+                partition@0 {
+                        label = "U-Boot";
+                        reg = <0x0 0x40000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "Kernel";
+                        reg = <0x40000 0x3c0000>;
+                };
+        };
+};
+&esdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        cd-gpios = <&gpio3 11 0>;
+        wp-gpios = <&gpio3 12 0>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
+                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_1>;
+        status = "okay";
+        pmic: mc13892@08 {
+                compatible = "fsl,mc13892", "fsl,mc13xxx";
+                reg = <0x08>;
+        };
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio7 6 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
new file mode 100644
index 000000000000..e54fffd48369
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx53-tqma53.dtsi"
+/ {
+        model = "TQ MBa53 starter kit";
+        compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
+};
+&iomuxc {
+        lvds1 {
+                pinctrl_lvds1_1: lvds1-grp1 {
+                        fsl,pins = <730 0x10000         /* LVDS0_TX3 */
+                                    732 0x10000         /* LVDS0_CLK */
+                                    734 0x10000         /* LVDS0_TX2 */
+                                    736 0x10000         /* LVDS0_TX1 */
+                                    738 0x10000>;       /* LVDS0_TX0 */
+                };
+                pinctrl_lvds1_2: lvds1-grp2 {
+                        fsl,pins = <720 0x10000         /* LVDS1_TX3 */
+                                    722 0x10000         /* LVDS1_TX2 */
+                                    724 0x10000         /* LVDS1_CLK */
+                                    726 0x10000         /* LVDS1_TX1 */
+                                    728 0x10000>;       /* LVDS1_TX0 */
+                };
+        };
+        disp1 {
+                pinctrl_disp1_1: disp1-grp1 {
+                        fsl,pins = <689 0x10000         /* DISP1_DRDY   */
+                                    482 0x10000         /* DISP1_HSYNC  */
+                                    489 0x10000         /* DISP1_VSYNC  */
+                                    684 0x10000         /* DISP1_DAT_0  */
+                                    515 0x10000         /* DISP1_DAT_22 */
+                                    523 0x10000         /* DISP1_DAT_23 */
+                                    543 0x10000         /* DISP1_DAT_21 */
+                                    553 0x10000         /* DISP1_DAT_20 */
+                                    558 0x10000         /* DISP1_DAT_19 */
+                                    564 0x10000         /* DISP1_DAT_18 */
+                                    570 0x10000         /* DISP1_DAT_17 */
+                                    575 0x10000         /* DISP1_DAT_16 */
+                                    580 0x10000         /* DISP1_DAT_15 */
+                                    585 0x10000         /* DISP1_DAT_14 */
+                                    590 0x10000         /* DISP1_DAT_13 */
+                                    595 0x10000         /* DISP1_DAT_12 */
+                                    628 0x10000         /* DISP1_DAT_11 */
+                                    634 0x10000         /* DISP1_DAT_10 */
+                                    639 0x10000         /* DISP1_DAT_9  */
+                                    644 0x10000         /* DISP1_DAT_8  */
+                                    649 0x10000         /* DISP1_DAT_7  */
+                                    654 0x10000         /* DISP1_DAT_6  */
+                                    659 0x10000         /* DISP1_DAT_5  */
+                                    664 0x10000         /* DISP1_DAT_4  */
+                                    669 0x10000         /* DISP1_DAT_3  */
+                                    674 0x10000         /* DISP1_DAT_2  */
+                                    679 0x10000         /* DISP1_DAT_1  */
+                                    684 0x10000>;       /* DISP1_DAT_0  */
+                };
+        };
+};
+&cspi {
+        status = "okay";
+};
+&i2c2 {
+        codec: sgtl5000@a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+        };
+        expander: pca9554@20 {
+                compatible = "pca9554";
+                reg = <0x20>;
+                interrupts = <109>;
+        };
+        sensor2: lm75@49 {
+                compatible = "lm75";
+                reg = <0x49>;
+        };
+};
+&fec {
+        status = "okay";
+};
+&esdhc2 {
+        status = "okay";
+};
+&uart3 {
+        status = "okay";
+};
+&ecspi1 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
+&uart2 {
+        status = "okay";
+};
+&can1 {
+        status = "okay";
+};
+&can2 {
+        status = "okay";
+};
+&i2c3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index b0075537195b..05cc5620436b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,200 +21,6 @@
                reg = <0x70000000 0x40000000>;
        };
-        soc {
-                aips@50000000 { /* AIPS1 */
-                        spba@50000000 {
-                                esdhc@50004000 { /* ESDHC1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
-                                        cd-gpios = <&gpio3 13 0>;
-                                        status = "okay";
-                                };
-                                ssi2: ssi@50014000 {
-                                        fsl,mode = "i2s-slave";
-                                        status = "okay";
-                                };
-                                esdhc@50020000 { /* ESDHC3 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
-                                        cd-gpios = <&gpio3 11 0>;
-                                        wp-gpios = <&gpio3 12 0>;
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@53fa8000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
-                                                        1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
-                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
-                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
-                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
-                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
-                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
-                                                        1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
-                                                >;
-                                        };
-                                        led_pin_gpio7_7: led_gpio7_7@0 {
-                                                fsl,pins = <
-                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
-                                                >;
-                                        };
-                                };
-                        };
-                        uart1: serial@53fbc000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart1_1>;
-                                status = "okay";
-                        };
-                };
-                aips@60000000 { /* AIPS2 */
-                        i2c@63fc4000 { /* I2C2 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c2_1>;
-                                status = "okay";
-                                sgtl5000: codec@0a {
-                                        compatible = "fsl,sgtl5000";
-                                        reg = <0x0a>;
-                                        VDDA-supply = <&reg_3p2v>;
-                                        VDDIO-supply = <&reg_3p2v>;
-                                };
-                        };
-                        i2c@63fc8000 { /* I2C1 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c1_1>;
-                                status = "okay";
-                                accelerometer: mma8450@1c {
-                                        compatible = "fsl,mma8450";
-                                        reg = <0x1c>;
-                                };
-                                pmic: dialog@48 {
-                                        compatible = "dlg,da9053-aa", "dlg,da9052";
-                                        reg = <0x48>;
-                                        interrupt-parent = <&gpio7>;
-                                        interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
-                                        regulators {
-                                                buck1_reg: buck1 {
-                                                        regulator-min-microvolt = <500000>;
-                                                        regulator-max-microvolt = <2075000>;
-                                                        regulator-always-on;
-                                                };
-                                                buck2_reg: buck2 {
-                                                        regulator-min-microvolt = <500000>;
-                                                        regulator-max-microvolt = <2075000>;
-                                                        regulator-always-on;
-                                                };
-                                                buck3_reg: buck3 {
-                                                        regulator-min-microvolt = <925000>;
-                                                        regulator-max-microvolt = <2500000>;
-                                                        regulator-always-on;
-                                                };
-                                                buck4_reg: buck4 {
-                                                        regulator-min-microvolt = <925000>;
-                                                        regulator-max-microvolt = <2500000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo1_reg: ldo1 {
-                                                        regulator-min-microvolt = <600000>;
-                                                        regulator-max-microvolt = <1800000>;
-                                                        regulator-boot-on;
-                                                        regulator-always-on;
-                                                };
-                                                ldo2_reg: ldo2 {
-                                                        regulator-min-microvolt = <600000>;
-                                                        regulator-max-microvolt = <1800000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo3_reg: ldo3 {
-                                                        regulator-min-microvolt = <600000>;
-                                                        regulator-max-microvolt = <1800000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo4_reg: ldo4 {
-                                                        regulator-min-microvolt = <1725000>;
-                                                        regulator-max-microvolt = <3300000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo5_reg: ldo5 {
-                                                        regulator-min-microvolt = <1725000>;
-                                                        regulator-max-microvolt = <3300000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo6_reg: ldo6 {
-                                                        regulator-min-microvolt = <1200000>;
-                                                        regulator-max-microvolt = <3600000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo7_reg: ldo7 {
-                                                        regulator-min-microvolt = <1200000>;
-                                                        regulator-max-microvolt = <3600000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo8_reg: ldo8 {
-                                                        regulator-min-microvolt = <1200000>;
-                                                        regulator-max-microvolt = <3600000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo9_reg: ldo9 {
-                                                        regulator-min-microvolt = <1200000>;
-                                                        regulator-max-microvolt = <3600000>;
-                                                        regulator-always-on;
-                                                };
-                                                ldo10_reg: ldo10 {
-                                                        regulator-min-microvolt = <1250000>;
-                                                        regulator-max-microvolt = <3650000>;
-                                                        regulator-always-on;
-                                                };
-                                        };
-                                };
-                        };
-                        audmux@63fd0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_audmux_1>;
-                                status = "okay";
-                        };
-                        ethernet@63fec000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_fec_1>;
-                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio7 6 0>;
-                                status = "okay";
-                        };
-                };
-        };
        gpio-keys {
                compatible = "gpio-keys";
@@ -276,3 +82,189 @@
                mux-ext-port = <5>;
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio3 13 0>;
+        status = "okay";
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&esdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        cd-gpios = <&gpio3 11 0>;
+        wp-gpios = <&gpio3 12 0>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+                                1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
+                                982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
+                        >;
+                };
+                led_pin_gpio7_7: led_gpio7_7@0 {
+                        fsl,pins = <
+                                873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_1>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_1>;
+        status = "okay";
+        accelerometer: mma8450@1c {
+                compatible = "fsl,mma8450";
+                reg = <0x1c>;
+        };
+        pmic: dialog@48 {
+                compatible = "dlg,da9053-aa", "dlg,da9052";
+                reg = <0x48>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
+                regulators {
+                        buck1_reg: buck1 {
+                                regulator-min-microvolt = <500000>;
+                                regulator-max-microvolt = <2075000>;
+                                regulator-always-on;
+                        };
+                        buck2_reg: buck2 {
+                                regulator-min-microvolt = <500000>;
+                                regulator-max-microvolt = <2075000>;
+                                regulator-always-on;
+                        };
+                        buck3_reg: buck3 {
+                                regulator-min-microvolt = <925000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+                        buck4_reg: buck4 {
+                                regulator-min-microvolt = <925000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+                        ldo1_reg: ldo1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo2_reg: ldo2 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo3_reg: ldo3 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo4_reg: ldo4 {
+                                regulator-min-microvolt = <1725000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        ldo5_reg: ldo5 {
+                                regulator-min-microvolt = <1725000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        ldo6_reg: ldo6 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3600000>;
+                                regulator-always-on;
+                        };
+                        ldo7_reg: ldo7 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3600000>;
+                                regulator-always-on;
+                        };
+                        ldo8_reg: ldo8 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3600000>;
+                                regulator-always-on;
+                        };
+                        ldo9_reg: ldo9 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3600000>;
+                                regulator-always-on;
+                        };
+                        ldo10_reg: ldo10 {
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <3650000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio7 6 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 06c68580c842..995554c324b8 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -21,157 +21,6 @@
                reg = <0x70000000 0x40000000>;
        };
-        soc {
-                aips@50000000 { /* AIPS1 */
-                        spba@50000000 {
-                                esdhc@50004000 { /* ESDHC1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
-                                        cd-gpios = <&gpio3 13 0>;
-                                        wp-gpios = <&gpio4 11 0>;
-                                        status = "okay";
-                                };
-                                esdhc@50008000 { /* ESDHC2 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
-                                        non-removable;
-                                        status = "okay";
-                                };
-                                uart3: serial@5000c000 {
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_uart3_1>;
-                                        fsl,uart-has-rtscts;
-                                        status = "okay";
-                                };
-                                ecspi@50010000 { /* ECSPI1 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
-                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
-                                        status = "okay";
-                                        zigbee: mc1323@0 {
-                                                compatible = "fsl,mc1323";
-                                                spi-max-frequency = <8000000>;
-                                                reg = <0>;
-                                        };
-                                        flash: m25p32@1 {
-                                                #address-cells = <1>;
-                                                #size-cells = <1>;
-                                                compatible = "st,m25p32", "st,m25p";
-                                                spi-max-frequency = <20000000>;
-                                                reg = <1>;
-                                                partition@0 {
-                                                        label = "U-Boot";
-                                                        reg = <0x0 0x40000>;
-                                                        read-only;
-                                                };
-                                                partition@40000 {
-                                                        label = "Kernel";
-                                                        reg = <0x40000 0x3c0000>;
-                                                };
-                                        };
-                                };
-                                esdhc@50020000 { /* ESDHC3 */
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
-                                        non-removable;
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@53fa8000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
-                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
-                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
-                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
-                                                        43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
-                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
-                                                >;
-                                        };
-                                };
-                        };
-                        uart1: serial@53fbc000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart1_1>;
-                                status = "okay";
-                        };
-                        uart2: serial@53fc0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart2_1>;
-                                status = "okay";
-                        };
-                };
-                aips@60000000 { /* AIPS2 */
-                        i2c@63fc4000 { /* I2C2 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c2_1>;
-                                status = "okay";
-                                codec: sgtl5000@0a {
-                                        compatible = "fsl,sgtl5000";
-                                        reg = <0x0a>;
-                                };
-                                magnetometer: mag3110@0e {
-                                        compatible = "fsl,mag3110";
-                                        reg = <0x0e>;
-                                };
-                                touchkey: mpr121@5a {
-                                        compatible = "fsl,mpr121";
-                                        reg = <0x5a>;
-                                };
-                        };
-                        i2c@63fc8000 { /* I2C1 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c1_1>;
-                                status = "okay";
-                                accelerometer: mma8450@1c {
-                                        compatible = "fsl,mma8450";
-                                        reg = <0x1c>;
-                                };
-                                camera: ov5642@3c {
-                                        compatible = "ovti,ov5642";
-                                        reg = <0x3c>;
-                                };
-                                pmic: dialog@48 {
-                                        compatible = "dialog,da9053", "dialog,da9052";
-                                        reg = <0x48>;
-                                };
-                        };
-                        ethernet@63fec000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_fec_1>;
-                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio7 6 0>;
-                                status = "okay";
-                        };
-                };
-        };
        gpio-keys {
                compatible = "gpio-keys";
@@ -188,3 +37,146 @@
                };
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio3 13 0>;
+        wp-gpios = <&gpio4 11 0>;
+        status = "okay";
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        non-removable;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
+        status = "okay";
+        zigbee: mc1323@0 {
+                compatible = "fsl,mc1323";
+                spi-max-frequency = <8000000>;
+                reg = <0>;
+        };
+        flash: m25p32@1 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p32", "st,m25p";
+                spi-max-frequency = <20000000>;
+                reg = <1>;
+                partition@0 {
+                        label = "U-Boot";
+                        reg = <0x0 0x40000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "Kernel";
+                        reg = <0x40000 0x3c0000>;
+                };
+        };
+};
+&esdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        non-removable;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
+                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_1>;
+        status = "okay";
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+        };
+        magnetometer: mag3110@0e {
+                compatible = "fsl,mag3110";
+                reg = <0x0e>;
+        };
+        touchkey: mpr121@5a {
+                compatible = "fsl,mpr121";
+                reg = <0x5a>;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_1>;
+        status = "okay";
+        accelerometer: mma8450@1c {
+                compatible = "fsl,mma8450";
+                reg = <0x1c>;
+        };
+        camera: ov5642@3c {
+                compatible = "ovti,ov5642";
+                reg = <0x3c>;
+        };
+        pmic: dialog@48 {
+                compatible = "dialog,da9053", "dialog,da9052";
+                reg = <0x48>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio7 6 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
new file mode 100644
index 000000000000..8278ec5ec222
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "imx53.dtsi"
+/ {
+        model = "TQ TQMa53";
+        compatible = "tq,tqma53", "fsl,imx53";
+        memory {
+                reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        wp-gpios = <&gpio1 2 0>;
+        cd-gpios = <&gpio1 4 0>;
+        status = "disabled";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_2>;
+        status = "disabled";
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        fsl,spi-num-chipselects = <4>;
+        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
+                   <&gpio3 24 0>, <&gpio3 25 0>;
+        status = "disabled";
+};
+&esdhc3 { /* EMMC */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        vmmc-supply = <&reg_3p3v>;
+        non-removable;
+        bus-width = <8>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        i2s {
+                pinctrl_i2s_1: i2s-grp1 {
+                        fsl,pins = <
+                                 1   0x10000    /* I2S_MCLK */
+                                 10  0x10000    /* I2S_SCLK */
+                                 17  0x10000    /* I2S_DOUT */
+                                 23  0x10000    /* I2S_LRCLK*/
+                                 30  0x10000    /* I2S_DIN  */
+                        >;
+                };
+        };
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                 610  0x10000   /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
+                                 711  0x10000   /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
+                                 873  0x10000   /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
+                                 878  0x10000   /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
+                                 922  0x10000   /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
+                                 928  0x10000   /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
+                                 982  0x10000   /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
+                                 989  0x10000   /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
+                                 1069 0x10000   /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
+                                 1093 0x10000   /* MX53_PAD_GPIO_3__GPIO1_3 */
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "disabled";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_2>;
+        status = "disabled";
+};
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "disabled";
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_1>;
+        status = "disabled";
+};
+&cspi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi_1>;
+        fsl,spi-num-chipselects = <3>;
+        cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
+                   <&gpio1 21 0>;
+        status = "disabled";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_1>;
+        status = "okay";
+        pmic: mc34708@8 {
+                compatible = "fsl,mc34708";
+                reg = <0x8>;
+                fsl,mc13xxx-uses-rtc;
+                interrupt-parent = <&gpio2>;
+                interrupts = <6 8>; /* PDATA_DATA6, low active */
+        };
+        sensor1: lm75@48 {
+                compatible = "lm75";
+                reg = <0x48>;
+        };
+        eeprom: 24c64@50 {
+                compatible = "at,24c64";
+                pagesize = <32>;
+                reg = <0x50>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index edc3f1eb6699..d05aa215c7f9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -274,6 +274,44 @@
                                        };
                                };
+                                csi {
+                                        pinctrl_csi_1: csigrp-1 {
+                                                fsl,pins = <
+                                                        286 0x1d5       /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
+                                                        291 0x1d5       /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
+                                                        280 0x1d5       /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
+                                                        276 0x1d5       /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
+                                                        409 0x1d5       /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
+                                                        402 0x1d5       /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
+                                                        395 0x1d5       /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
+                                                        388 0x1d5       /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
+                                                        381 0x1d5       /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
+                                                        374 0x1d5       /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
+                                                        367 0x1d5       /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
+                                                        360 0x1d5       /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
+                                                        352 0x1d5       /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
+                                                        344 0x1d5       /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
+                                                        336 0x1d5       /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
+                                                        328 0x1d5       /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
+                                                        320 0x1d5       /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
+                                                        312 0x1d5       /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
+                                                        304 0x1d5       /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
+                                                        296 0x1d5       /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
+                                                        276 0x1d5       /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
+                                                >;
+                                        };
+                                };
+                                cspi {
+                                        pinctrl_cspi_1: cspigrp-1 {
+                                                fsl,pins = <
+                                                        998  0x1d5      /* MX53_PAD_SD1_DATA0__CSPI_MISO */
+                                                        1008 0x1d5      /* MX53_PAD_SD1_CMD__CSPI_MOSI */
+                                                        1022 0x1d5      /* MX53_PAD_SD1_CLK__CSPI_SCLK */
+                                                >;
+                                        };
+                                };
                                ecspi1 {
                                        pinctrl_ecspi1_1: ecspi1grp-1 {
                                                fsl,pins = <
@@ -349,6 +387,13 @@
                                                        853 0x80000000  /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
                                                >;
                                        };
+                                        pinctrl_can1_2: can1grp-2 {
+                                                fsl,pins = <
+                                                        37  0x80000000  /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
+                                                        44  0x80000000  /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
+                                                >;
+                                        };
                                };
                                can2 {
@@ -387,6 +432,14 @@
                                        };
                                };
+                                owire {
+                                        pinctrl_owire_1: owiregrp-1 {
+                                                fsl,pins = <
+                                                                1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
+                                                >;
+                                        };
+                                };
                                uart1 {
                                        pinctrl_uart1_1: uart1grp-1 {
                                                fsl,pins = <
@@ -421,6 +474,14 @@
                                                        880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
                                                >;
                                        };
+                                        pinctrl_uart3_2: uart3grp-2 {
+                                                fsl,pins = <
+                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+                                                >;
+                                        };
                                };
                                uart4 {
@@ -570,6 +631,13 @@
                                status = "disabled";
                        };
+                        owire: owire@63fa4000 {
+                                compatible = "fsl,imx53-owire", "fsl,imx21-owire";
+                                reg = <0x63fa4000 0x4000>;
+                                clocks = <&clks 159>;
+                                status = "disabled";
+                        };
                        ecspi2: ecspi@63fac000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
new file mode 100644
index 000000000000..63fafe2a606c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/include/ "imx6qdl.dtsi"
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        soc {
+                aips1: aips-bus@02000000 {
+                        pxp: pxp@020f0000 {
+                                reg = <0x020f0000 0x4000>;
+                                interrupts = <0 98 0x04>;
+                        };
+                        epdc: epdc@020f4000 {
+                                reg = <0x020f4000 0x4000>;
+                                interrupts = <0 97 0x04>;
+                        };
+                        lcdif: lcdif@020f8000 {
+                                reg = <0x020f8000 0x4000>;
+                                interrupts = <0 39 0x04>;
+                        };
+                };
+                aips2: aips-bus@02100000 {
+                        i2c4: i2c@021f8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx1-i2c";
+                                reg = <0x021f8000 0x4000>;
+                                interrupts = <0 35 0x04>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 5bfa02a3f85c..53eb241fa5ad 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -21,71 +21,6 @@
                reg = <0x10000000 0x80000000>;
        };
-        soc {
-                gpmi-nand@00112000 {
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
-                        status = "disabled"; /* gpmi nand conflicts with SD */
-                };
-                aips-bus@02000000 { /* AIPS1 */
-                        iomuxc@020e0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
-                                                >;
-                                        };
-                                };
-                                arm2 {
-                                        pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
-                                                fsl,pins = <
-                                                        1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
-                                                        1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
-                                                >;
-                                        };
-                                };
-                        };
-                };
-                aips-bus@02100000 { /* AIPS2 */
-                        ethernet@02188000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_enet_2>;
-                                phy-mode = "rgmii";
-                                status = "okay";
-                        };
-                        usdhc@02198000 { /* uSDHC3 */
-                                cd-gpios = <&gpio6 11 0>;
-                                wp-gpios = <&gpio6 14 0>;
-                                vmmc-supply = <&reg_3p3v>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc3_1
-                                             &pinctrl_usdhc3_arm2>;
-                                status = "okay";
-                        };
-                        usdhc@0219c000 { /* uSDHC4 */
-                                non-removable;
-                                vmmc-supply = <&reg_3p3v>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc4_1>;
-                                status = "okay";
-                        };
-                        uart4: serial@021f0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart4_1>;
-                                status = "okay";
-                        };
-                };
-        };
        regulators {
                compatible = "simple-bus";
@@ -108,3 +43,62 @@
                };
        };
 };
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        status = "disabled"; /* gpmi nand conflicts with SD */
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+                        >;
+                };
+        };
+        arm2 {
+                pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
+                        fsl,pins = <
+                                1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+                                1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+                        >;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_2>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+&usdhc3 {
+        cd-gpios = <&gpio6 11 0>;
+        wp-gpios = <&gpio6 14 0>;
+        vmmc-supply = <&reg_3p3v>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1
+                     &pinctrl_usdhc3_arm2>;
+        status = "okay";
+};
+&usdhc4 {
+        non-removable;
+        vmmc-supply = <&reg_3p3v>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4_1>;
+        status = "okay";
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 826e4ad1477e..656d489122fe 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,45 +20,39 @@
        memory {
                reg = <0x10000000 0x80000000>;
        };
+};
-        soc {
+&iomuxc {
-                aips-bus@02000000 { /* AIPS1 */
+        pinctrl-names = "default";
-                        iomuxc@020e0000 {
+        pinctrl-0 = <&pinctrl_hog>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
+        hog {
-                                        pinctrl_hog: hoggrp {
+                pinctrl_hog: hoggrp {
-                                                fsl,pins = <
+                        fsl,pins = <
-                                                        1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
+                                1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
-                                                        13   0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
+                                13   0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
-                                                >;
+                        >;
-                                        };
-                                };
-                        };
                };
+        };
+};
-                aips-bus@02100000 { /* AIPS2 */
+&uart4 {
-                        uart4: serial@021f0000 {
+        pinctrl-names = "default";
-                                pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
-                                pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "okay";
-                                status = "okay";
+};
-                        };
-                        ethernet@02188000 {
+&fec {
-                                pinctrl-names = "default";
+        pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_enet_2>;
+        pinctrl-0 = <&pinctrl_enet_2>;
-                                phy-mode = "rgmii";
+        phy-mode = "rgmii";
-                                status = "okay";
+        status = "okay";
-                        };
+};
-                        usdhc@02198000 { /* uSDHC3 */
+&usdhc3 {
-                                pinctrl-names = "default";
+        pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc3_1>;
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
-                                cd-gpios = <&gpio6 15 0>;
+        cd-gpios = <&gpio6 15 0>;
-                                wp-gpios = <&gpio1 13 0>;
+        wp-gpios = <&gpio1 13 0>;
-                                status = "okay";
+        status = "okay";
-                        };
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d152328285a1..2ce355cd05e5 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -21,118 +21,6 @@
                reg = <0x10000000 0x40000000>;
        };
-        soc {
-                aips-bus@02000000 { /* AIPS1 */
-                        spba-bus@02000000 {
-                                ecspi@02008000 { /* eCSPI1 */
-                                        fsl,spi-num-chipselects = <1>;
-                                        cs-gpios = <&gpio3 19 0>;
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
-                                        status = "okay";
-                                        flash: m25p80@0 {
-                                                compatible = "sst,sst25vf016b";
-                                                spi-max-frequency = <20000000>;
-                                                reg = <0>;
-                                        };
-                                };
-                                ssi1: ssi@02028000 {
-                                        fsl,mode = "i2s-slave";
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@020e0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
-                                                        1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
-                                                        121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-                                                        144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-                                                        152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
-                                                        1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
-                                                        1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
-                                                        953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
-                                                >;
-                                        };
-                                };
-                        };
-                };
-                aips-bus@02100000 { /* AIPS2 */
-                        usb@02184000 { /* USB OTG */
-                                vbus-supply = <&reg_usb_otg_vbus>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usbotg_1>;
-                                disable-over-current;
-                                status = "okay";
-                        };
-                        usb@02184200 { /* USB1 */
-                                status = "okay";
-                        };
-                        ethernet@02188000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_enet_1>;
-                                phy-mode = "rgmii";
-                                phy-reset-gpios = <&gpio3 23 0>;
-                                status = "okay";
-                        };
-                        usdhc@02198000 { /* uSDHC3 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc3_2>;
-                                cd-gpios = <&gpio7 0 0>;
-                                wp-gpios = <&gpio7 1 0>;
-                                vmmc-supply = <&reg_3p3v>;
-                                status = "okay";
-                        };
-                        usdhc@0219c000 { /* uSDHC4 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc4_2>;
-                                cd-gpios = <&gpio2 6 0>;
-                                wp-gpios = <&gpio2 7 0>;
-                                vmmc-supply = <&reg_3p3v>;
-                                status = "okay";
-                        };
-                        audmux@021d8000 {
-                                status = "okay";
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_audmux_1>;
-                        };
-                        uart2: serial@021e8000 {
-                                status = "okay";
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart2_1>;
-                        };
-                        i2c@021a0000 { /* I2C1 */
-                                status = "okay";
-                                clock-frequency = <100000>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_i2c1_1>;
-                                codec: sgtl5000@0a {
-                                        compatible = "fsl,sgtl5000";
-                                        reg = <0x0a>;
-                                        clocks = <&clks 169>;
-                                        VDDA-supply = <&reg_2p5v>;
-                                        VDDIO-supply = <&reg_3p3v>;
-                                };
-                        };
-                };
-        };
        regulators {
                compatible = "simple-bus";
@@ -176,3 +64,107 @@
                mux-ext-port = <4>;
        };
 };
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        status = "okay";
+        flash: m25p80@0 {
+                compatible = "sst,sst25vf016b";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+                                1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+                                121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+                                1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+                                1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+                                953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                        >;
+                };
+        };
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg_1>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        cd-gpios = <&gpio7 0 0>;
+        wp-gpios = <&gpio7 1 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4_2>;
+        cd-gpios = <&gpio2 6 0>;
+        wp-gpios = <&gpio2 7 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&audmux {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+};
+&uart2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+};
+&i2c1 {
+        status = "okay";
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_1>;
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 169>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index a42402562b7b..2dea304a7980 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -21,61 +21,6 @@
                reg = <0x10000000 0x40000000>;
        };
-        soc {
-                aips-bus@02000000 { /* AIPS1 */
-                        spba-bus@02000000 {
-                                uart1: serial@02020000 {
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_uart1_1>;
-                                        status = "okay";
-                                };
-                        };
-                        iomuxc@020e0000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_hog>;
-                                hog {
-                                        pinctrl_hog: hoggrp {
-                                                fsl,pins = <
-                                                        1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
-                                                        1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
-                                                        1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
-                                                        1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
-                                                        1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
-                                                        1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
-                                                >;
-                                        };
-                                };
-                        };
-                };
-                aips-bus@02100000 { /* AIPS2 */
-                        ethernet@02188000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_enet_1>;
-                                phy-mode = "rgmii";
-                                status = "okay";
-                        };
-                        usdhc@02194000 { /* uSDHC2 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc2_1>;
-                                cd-gpios = <&gpio2 2 0>;
-                                wp-gpios = <&gpio2 3 0>;
-                                status = "okay";
-                        };
-                        usdhc@02198000 { /* uSDHC3 */
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_usdhc3_1>;
-                                cd-gpios = <&gpio2 0 0>;
-                                wp-gpios = <&gpio2 1 0>;
-                                status = "okay";
-                        };
-                };
-        };
        gpio-keys {
                compatible = "gpio-keys";
@@ -92,3 +37,50 @@
                };
        };
 };
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
+                                1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
+                                1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+                                1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+                                1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+                                1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+                        >;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        cd-gpios = <&gpio2 2 0>;
+        wp-gpios = <&gpio2 3 0>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio2 0 0>;
+        wp-gpios = <&gpio2 1 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d6265ca97119..cba021eb035e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -1,33 +1,16 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
 *
- * The code contained herein is licensed under the GNU General Public
+ * This program is free software; you can redistribute it and/or modify
- * License. You may obtain a copy of the GNU General Public License
+ * it under the terms of the GNU General Public License version 2 as
- * Version 2 or later at the following locations:
+ * published by the Free Software Foundation.
 *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
 */
-/include/ "skeleton.dtsi"
+/include/ "imx6qdl.dtsi"
 / {
-        aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
-                gpio0 = &gpio1;
-                gpio1 = &gpio2;
-                gpio2 = &gpio3;
-                gpio3 = &gpio4;
-                gpio4 = &gpio5;
-                gpio5 = &gpio6;
-                gpio6 = &gpio7;
-        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -38,12 +21,19 @@
                        next-level-cache = <&L2>;
                        operating-points = <
                                /* kHz    uV */
-                                792000  1100000
+                                1200000 1275000
+                                996000  1250000
+                                792000  1150000
                                396000  950000
-                                198000  850000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
-                        cpu0-supply = <&reg_cpu>;
+                        clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+                                 <&clks 17>, <&clks 170>;
+                        clock-names = "arm", "pll2_pfd2_396m", "step",
+                                      "pll1_sw", "pll1_sys";
+                        arm-supply = <&reg_arm>;
+                        pu-supply = <&reg_pu>;
+                        soc-supply = <&reg_soc>;
                };
                cpu@1 {
@@ -65,142 +55,9 @@
                };
        };
-        intc: interrupt-controller@00a01000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                interrupt-controller;
-                reg = <0x00a01000 0x1000>,
-                      <0x00a00100 0x100>;
-        };
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                ckil {
-                        compatible = "fsl,imx-ckil", "fixed-clock";
-                        clock-frequency = <32768>;
-                };
-                ckih1 {
-                        compatible = "fsl,imx-ckih1", "fixed-clock";
-                        clock-frequency = <0>;
-                };
-                osc {
-                        compatible = "fsl,imx-osc", "fixed-clock";
-                        clock-frequency = <24000000>;
-                };
-        };
        soc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
-                dma-apbh@00110000 {
-                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
-                        reg = <0x00110000 0x2000>;
-                        clocks = <&clks 106>;
-                };
-                nfc: gpmi-nand@00112000 {
-                        compatible = "fsl,imx6q-gpmi-nand";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-                        reg-names = "gpmi-nand", "bch";
-                        interrupts = <0 13 0x04>, <0 15 0x04>;
-                        interrupt-names = "gpmi-dma", "bch";
-                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
-                                 <&clks 150>, <&clks 149>;
-                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
-                                      "gpmi_bch_apb", "per1_bch";
-                        fsl,gpmi-dma-channel = <0>;
-                        status = "disabled";
-                };
-                timer@00a00600 {
-                        compatible = "arm,cortex-a9-twd-timer";
-                        reg = <0x00a00600 0x20>;
-                        interrupts = <1 13 0xf01>;
-                };
-                L2: l2-cache@00a02000 {
-                        compatible = "arm,pl310-cache";
-                        reg = <0x00a02000 0x1000>;
-                        interrupts = <0 92 0x04>;
-                        cache-unified;
-                        cache-level = <2>;
-                };
                aips-bus@02000000 { /* AIPS1 */
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x02000000 0x100000>;
-                        ranges;
                        spba-bus@02000000 {
-                                compatible = "fsl,spba-bus", "simple-bus";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0x02000000 0x40000>;
-                                ranges;
-                                spdif: spdif@02004000 {
-                                        reg = <0x02004000 0x4000>;
-                                        interrupts = <0 52 0x04>;
-                                };
-                                ecspi1: ecspi@02008000 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
-                                        reg = <0x02008000 0x4000>;
-                                        interrupts = <0 31 0x04>;
-                                        clocks = <&clks 112>, <&clks 112>;
-                                        clock-names = "ipg", "per";
-                                        status = "disabled";
-                                };
-                                ecspi2: ecspi@0200c000 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
-                                        reg = <0x0200c000 0x4000>;
-                                        interrupts = <0 32 0x04>;
-                                        clocks = <&clks 113>, <&clks 113>;
-                                        clock-names = "ipg", "per";
-                                        status = "disabled";
-                                };
-                                ecspi3: ecspi@02010000 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
-                                        reg = <0x02010000 0x4000>;
-                                        interrupts = <0 33 0x04>;
-                                        clocks = <&clks 114>, <&clks 114>;
-                                        clock-names = "ipg", "per";
-                                        status = "disabled";
-                                };
-                                ecspi4: ecspi@02014000 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
-                                        reg = <0x02014000 0x4000>;
-                                        interrupts = <0 34 0x04>;
-                                        clocks = <&clks 115>, <&clks 115>;
-                                        clock-names = "ipg", "per";
-                                        status = "disabled";
-                                };
                                ecspi5: ecspi@02018000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
@@ -211,361 +68,6 @@
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
-                                uart1: serial@02020000 {
-                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-                                        reg = <0x02020000 0x4000>;
-                                        interrupts = <0 26 0x04>;
-                                        clocks = <&clks 160>, <&clks 161>;
-                                        clock-names = "ipg", "per";
-                                        status = "disabled";
-                                };
-                                esai: esai@02024000 {
-                                        reg = <0x02024000 0x4000>;
-                                        interrupts = <0 51 0x04>;
-                                };
-                                ssi1: ssi@02028000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
-                                        reg = <0x02028000 0x4000>;
-                                        interrupts = <0 46 0x04>;
-                                        clocks = <&clks 178>;
-                                        fsl,fifo-depth = <15>;
-                                        fsl,ssi-dma-events = <38 37>;
-                                        status = "disabled";
-                                };
-                                ssi2: ssi@0202c000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
-                                        reg = <0x0202c000 0x4000>;
-                                        interrupts = <0 47 0x04>;
-                                        clocks = <&clks 179>;
-                                        fsl,fifo-depth = <15>;
-                                        fsl,ssi-dma-events = <42 41>;
-                                        status = "disabled";
-                                };
-                                ssi3: ssi@02030000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
-                                        reg = <0x02030000 0x4000>;
-                                        interrupts = <0 48 0x04>;
-                                        clocks = <&clks 180>;
-                                        fsl,fifo-depth = <15>;
-                                        fsl,ssi-dma-events = <46 45>;
-                                        status = "disabled";
-                                };
-                                asrc: asrc@02034000 {
-                                        reg = <0x02034000 0x4000>;
-                                        interrupts = <0 50 0x04>;
-                                };
-                                spba@0203c000 {
-                                        reg = <0x0203c000 0x4000>;
-                                };
-                        };
-                        vpu: vpu@02040000 {
-                                reg = <0x02040000 0x3c000>;
-                                interrupts = <0 3 0x04 0 12 0x04>;
-                        };
-                        aipstz@0207c000 { /* AIPSTZ1 */
-                                reg = <0x0207c000 0x4000>;
-                        };
-                        pwm1: pwm@02080000 {
-                                #pwm-cells = <2>;
-                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
-                                reg = <0x02080000 0x4000>;
-                                interrupts = <0 83 0x04>;
-                                clocks = <&clks 62>, <&clks 145>;
-                                clock-names = "ipg", "per";
-                        };
-                        pwm2: pwm@02084000 {
-                                #pwm-cells = <2>;
-                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
-                                reg = <0x02084000 0x4000>;
-                                interrupts = <0 84 0x04>;
-                                clocks = <&clks 62>, <&clks 146>;
-                                clock-names = "ipg", "per";
-                        };
-                        pwm3: pwm@02088000 {
-                                #pwm-cells = <2>;
-                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
-                                reg = <0x02088000 0x4000>;
-                                interrupts = <0 85 0x04>;
-                                clocks = <&clks 62>, <&clks 147>;
-                                clock-names = "ipg", "per";
-                        };
-                        pwm4: pwm@0208c000 {
-                                #pwm-cells = <2>;
-                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
-                                reg = <0x0208c000 0x4000>;
-                                interrupts = <0 86 0x04>;
-                                clocks = <&clks 62>, <&clks 148>;
-                                clock-names = "ipg", "per";
-                        };
-                        can1: flexcan@02090000 {
-                                reg = <0x02090000 0x4000>;
-                                interrupts = <0 110 0x04>;
-                        };
-                        can2: flexcan@02094000 {
-                                reg = <0x02094000 0x4000>;
-                                interrupts = <0 111 0x04>;
-                        };
-                        gpt: gpt@02098000 {
-                                compatible = "fsl,imx6q-gpt";
-                                reg = <0x02098000 0x4000>;
-                                interrupts = <0 55 0x04>;
-                        };
-                        gpio1: gpio@0209c000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x0209c000 0x4000>;
-                                interrupts = <0 66 0x04 0 67 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio2: gpio@020a0000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020a0000 0x4000>;
-                                interrupts = <0 68 0x04 0 69 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio3: gpio@020a4000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020a4000 0x4000>;
-                                interrupts = <0 70 0x04 0 71 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio4: gpio@020a8000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020a8000 0x4000>;
-                                interrupts = <0 72 0x04 0 73 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio5: gpio@020ac000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020ac000 0x4000>;
-                                interrupts = <0 74 0x04 0 75 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio6: gpio@020b0000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020b0000 0x4000>;
-                                interrupts = <0 76 0x04 0 77 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        gpio7: gpio@020b4000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
-                                reg = <0x020b4000 0x4000>;
-                                interrupts = <0 78 0x04 0 79 0x04>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        kpp: kpp@020b8000 {
-                                reg = <0x020b8000 0x4000>;
-                                interrupts = <0 82 0x04>;
-                        };
-                        wdog1: wdog@020bc000 {
-                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
-                                reg = <0x020bc000 0x4000>;
-                                interrupts = <0 80 0x04>;
-                                clocks = <&clks 0>;
-                        };
-                        wdog2: wdog@020c0000 {
-                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
-                                reg = <0x020c0000 0x4000>;
-                                interrupts = <0 81 0x04>;
-                                clocks = <&clks 0>;
-                                status = "disabled";
-                        };
-                        clks: ccm@020c4000 {
-                                compatible = "fsl,imx6q-ccm";
-                                reg = <0x020c4000 0x4000>;
-                                interrupts = <0 87 0x04 0 88 0x04>;
-                                #clock-cells = <1>;
-                        };
-                        anatop: anatop@020c8000 {
-                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
-                                reg = <0x020c8000 0x1000>;
-                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
-                                regulator-1p1@110 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vdd1p1";
-                                        regulator-min-microvolt = <800000>;
-                                        regulator-max-microvolt = <1375000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x110>;
-                                        anatop-vol-bit-shift = <8>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <4>;
-                                        anatop-min-voltage = <800000>;
-                                        anatop-max-voltage = <1375000>;
-                                };
-                                regulator-3p0@120 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vdd3p0";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <3150000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x120>;
-                                        anatop-vol-bit-shift = <8>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <0>;
-                                        anatop-min-voltage = <2625000>;
-                                        anatop-max-voltage = <3400000>;
-                                };
-                                regulator-2p5@130 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vdd2p5";
-                                        regulator-min-microvolt = <2000000>;
-                                        regulator-max-microvolt = <2750000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x130>;
-                                        anatop-vol-bit-shift = <8>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <0>;
-                                        anatop-min-voltage = <2000000>;
-                                        anatop-max-voltage = <2750000>;
-                                };
-                                reg_cpu: regulator-vddcore@140 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "cpu";
-                                        regulator-min-microvolt = <725000>;
-                                        regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x140>;
-                                        anatop-vol-bit-shift = <0>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <1>;
-                                        anatop-min-voltage = <725000>;
-                                        anatop-max-voltage = <1450000>;
-                                };
-                                regulator-vddpu@140 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vddpu";
-                                        regulator-min-microvolt = <725000>;
-                                        regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x140>;
-                                        anatop-vol-bit-shift = <9>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <1>;
-                                        anatop-min-voltage = <725000>;
-                                        anatop-max-voltage = <1450000>;
-                                };
-                                regulator-vddsoc@140 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vddsoc";
-                                        regulator-min-microvolt = <725000>;
-                                        regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
-                                        anatop-reg-offset = <0x140>;
-                                        anatop-vol-bit-shift = <18>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <1>;
-                                        anatop-min-voltage = <725000>;
-                                        anatop-max-voltage = <1450000>;
-                                };
-                        };
-                        usbphy1: usbphy@020c9000 {
-                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
-                                reg = <0x020c9000 0x1000>;
-                                interrupts = <0 44 0x04>;
-                                clocks = <&clks 182>;
-                        };
-                        usbphy2: usbphy@020ca000 {
-                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
-                                reg = <0x020ca000 0x1000>;
-                                interrupts = <0 45 0x04>;
-                                clocks = <&clks 183>;
-                        };
-                        snvs@020cc000 {
-                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
-                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
-                                        reg = <0x34 0x58>;
-                                        interrupts = <0 19 0x04 0 20 0x04>;
-                                };
-                        };
-                        epit1: epit@020d0000 { /* EPIT1 */
-                                reg = <0x020d0000 0x4000>;
-                                interrupts = <0 56 0x04>;
-                        };
-                        epit2: epit@020d4000 { /* EPIT2 */
-                                reg = <0x020d4000 0x4000>;
-                                interrupts = <0 57 0x04>;
-                        };
-                        src: src@020d8000 {
-                                compatible = "fsl,imx6q-src";
-                                reg = <0x020d8000 0x4000>;
-                                interrupts = <0 91 0x04 0 96 0x04>;
-                        };
-                        gpc: gpc@020dc000 {
-                                compatible = "fsl,imx6q-gpc";
-                                reg = <0x020dc000 0x4000>;
-                                interrupts = <0 89 0x04 0 90 0x04>;
-                        };
-                        gpr: iomuxc-gpr@020e0000 {
-                                compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
-                                reg = <0x020e0000 0x38>;
                        };
                        iomuxc: iomuxc@020e0000 {
@@ -780,272 +282,6 @@
                                        };
                                };
                        };
-                        dcic1: dcic@020e4000 {
-                                reg = <0x020e4000 0x4000>;
-                                interrupts = <0 124 0x04>;
-                        };
-                        dcic2: dcic@020e8000 {
-                                reg = <0x020e8000 0x4000>;
-                                interrupts = <0 125 0x04>;
-                        };
-                        sdma: sdma@020ec000 {
-                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
-                                reg = <0x020ec000 0x4000>;
-                                interrupts = <0 2 0x04>;
-                                clocks = <&clks 155>, <&clks 155>;
-                                clock-names = "ipg", "ahb";
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
-                        };
-                };
-                aips-bus@02100000 { /* AIPS2 */
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x02100000 0x100000>;
-                        ranges;
-                        caam@02100000 {
-                                reg = <0x02100000 0x40000>;
-                                interrupts = <0 105 0x04 0 106 0x04>;
-                        };
-                        aipstz@0217c000 { /* AIPSTZ2 */
-                                reg = <0x0217c000 0x4000>;
-                        };
-                        usbotg: usb@02184000 {
-                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
-                                reg = <0x02184000 0x200>;
-                                interrupts = <0 43 0x04>;
-                                clocks = <&clks 162>;
-                                fsl,usbphy = <&usbphy1>;
-                                fsl,usbmisc = <&usbmisc 0>;
-                                status = "disabled";
-                        };
-                        usbh1: usb@02184200 {
-                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
-                                reg = <0x02184200 0x200>;
-                                interrupts = <0 40 0x04>;
-                                clocks = <&clks 162>;
-                                fsl,usbphy = <&usbphy2>;
-                                fsl,usbmisc = <&usbmisc 1>;
-                                status = "disabled";
-                        };
-                        usbh2: usb@02184400 {
-                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
-                                reg = <0x02184400 0x200>;
-                                interrupts = <0 41 0x04>;
-                                clocks = <&clks 162>;
-                                fsl,usbmisc = <&usbmisc 2>;
-                                status = "disabled";
-                        };
-                        usbh3: usb@02184600 {
-                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
-                                reg = <0x02184600 0x200>;
-                                interrupts = <0 42 0x04>;
-                                clocks = <&clks 162>;
-                                fsl,usbmisc = <&usbmisc 3>;
-                                status = "disabled";
-                        };
-                        usbmisc: usbmisc: usbmisc@02184800 {
-                                #index-cells = <1>;
-                                compatible = "fsl,imx6q-usbmisc";
-                                reg = <0x02184800 0x200>;
-                                clocks = <&clks 162>;
-                        };
-                        fec: ethernet@02188000 {
-                                compatible = "fsl,imx6q-fec";
-                                reg = <0x02188000 0x4000>;
-                                interrupts = <0 118 0x04 0 119 0x04>;
-                                clocks = <&clks 117>, <&clks 117>, <&clks 177>;
-                                clock-names = "ipg", "ahb", "ptp";
-                                status = "disabled";
-                        };
-                        mlb@0218c000 {
-                                reg = <0x0218c000 0x4000>;
-                                interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
-                        };
-                        usdhc1: usdhc@02190000 {
-                                compatible = "fsl,imx6q-usdhc";
-                                reg = <0x02190000 0x4000>;
-                                interrupts = <0 22 0x04>;
-                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
-                        usdhc2: usdhc@02194000 {
-                                compatible = "fsl,imx6q-usdhc";
-                                reg = <0x02194000 0x4000>;
-                                interrupts = <0 23 0x04>;
-                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
-                        usdhc3: usdhc@02198000 {
-                                compatible = "fsl,imx6q-usdhc";
-                                reg = <0x02198000 0x4000>;
-                                interrupts = <0 24 0x04>;
-                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
-                        usdhc4: usdhc@0219c000 {
-                                compatible = "fsl,imx6q-usdhc";
-                                reg = <0x0219c000 0x4000>;
-                                interrupts = <0 25 0x04>;
-                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
-                        i2c1: i2c@021a0000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
-                                reg = <0x021a0000 0x4000>;
-                                interrupts = <0 36 0x04>;
-                                clocks = <&clks 125>;
-                                status = "disabled";
-                        };
-                        i2c2: i2c@021a4000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
-                                reg = <0x021a4000 0x4000>;
-                                interrupts = <0 37 0x04>;
-                                clocks = <&clks 126>;
-                                status = "disabled";
-                        };
-                        i2c3: i2c@021a8000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
-                                reg = <0x021a8000 0x4000>;
-                                interrupts = <0 38 0x04>;
-                                clocks = <&clks 127>;
-                                status = "disabled";
-                        };
-                        romcp@021ac000 {
-                                reg = <0x021ac000 0x4000>;
-                        };
-                        mmdc0: mmdc@021b0000 { /* MMDC0 */
-                                compatible = "fsl,imx6q-mmdc";
-                                reg = <0x021b0000 0x4000>;
-                        };
-                        mmdc1: mmdc@021b4000 { /* MMDC1 */
-                                reg = <0x021b4000 0x4000>;
-                        };
-                        weim@021b8000 {
-                                reg = <0x021b8000 0x4000>;
-                                interrupts = <0 14 0x04>;
-                        };
-                        ocotp@021bc000 {
-                                reg = <0x021bc000 0x4000>;
-                        };
-                        ocotp@021c0000 {
-                                reg = <0x021c0000 0x4000>;
-                                interrupts = <0 21 0x04>;
-                        };
-                        tzasc@021d0000 { /* TZASC1 */
-                                reg = <0x021d0000 0x4000>;
-                                interrupts = <0 108 0x04>;
-                        };
-                        tzasc@021d4000 { /* TZASC2 */
-                                reg = <0x021d4000 0x4000>;
-                                interrupts = <0 109 0x04>;
-                        };
-                        audmux: audmux@021d8000 {
-                                compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
-                                reg = <0x021d8000 0x4000>;
-                                status = "disabled";
-                        };
-                        mipi@021dc000 { /* MIPI-CSI */
-                                reg = <0x021dc000 0x4000>;
-                        };
-                        mipi@021e0000 { /* MIPI-DSI */
-                                reg = <0x021e0000 0x4000>;
-                        };
-                        vdoa@021e4000 {
-                                reg = <0x021e4000 0x4000>;
-                                interrupts = <0 18 0x04>;
-                        };
-                        uart2: serial@021e8000 {
-                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-                                reg = <0x021e8000 0x4000>;
-                                interrupts = <0 27 0x04>;
-                                clocks = <&clks 160>, <&clks 161>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                        uart3: serial@021ec000 {
-                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-                                reg = <0x021ec000 0x4000>;
-                                interrupts = <0 28 0x04>;
-                                clocks = <&clks 160>, <&clks 161>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                        uart4: serial@021f0000 {
-                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-                                reg = <0x021f0000 0x4000>;
-                                interrupts = <0 29 0x04>;
-                                clocks = <&clks 160>, <&clks 161>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                        uart5: serial@021f4000 {
-                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
-                                reg = <0x021f4000 0x4000>;
-                                interrupts = <0 30 0x04>;
-                                clocks = <&clks 160>, <&clks 161>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                };
-                ipu1: ipu@02400000 {
-                        #crtc-cells = <1>;
-                        compatible = "fsl,imx6q-ipu";
-                        reg = <0x02400000 0x400000>;
-                        interrupts = <0 6 0x4 0 5 0x4>;
-                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
-                        clock-names = "bus", "di0", "di1";
                };
                ipu2: ipu@02800000 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
new file mode 100644
index 000000000000..06ec460b4581
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -0,0 +1,800 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
+                gpio6 = &gpio7;
+        };
+        intc: interrupt-controller@00a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-controller;
+                reg = <0x00a01000 0x1000>,
+                      <0x00a00100 0x100>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fsl,imx-ckil", "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                ckih1 {
+                        compatible = "fsl,imx-ckih1", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                dma-apbh@00110000 {
+                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+                        reg = <0x00110000 0x2000>;
+                        clocks = <&clks 106>;
+                };
+                gpmi: gpmi-nand@00112000 {
+                        compatible = "fsl,imx6q-gpmi-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                        reg-names = "gpmi-nand", "bch";
+                        interrupts = <0 13 0x04>, <0 15 0x04>;
+                        interrupt-names = "gpmi-dma", "bch";
+                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+                                 <&clks 150>, <&clks 149>;
+                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                      "gpmi_bch_apb", "per1_bch";
+                        fsl,gpmi-dma-channel = <0>;
+                        status = "disabled";
+                };
+                timer@00a00600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x00a00600 0x20>;
+                        interrupts = <1 13 0xf01>;
+                };
+                L2: l2-cache@00a02000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a02000 0x1000>;
+                        interrupts = <0 92 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                aips-bus@02000000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02000000 0x100000>;
+                        ranges;
+                        spba-bus@02000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x02000000 0x40000>;
+                                ranges;
+                                spdif: spdif@02004000 {
+                                        reg = <0x02004000 0x4000>;
+                                        interrupts = <0 52 0x04>;
+                                };
+                                ecspi1: ecspi@02008000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02008000 0x4000>;
+                                        interrupts = <0 31 0x04>;
+                                        clocks = <&clks 112>, <&clks 112>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi2: ecspi@0200c000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x0200c000 0x4000>;
+                                        interrupts = <0 32 0x04>;
+                                        clocks = <&clks 113>, <&clks 113>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi3: ecspi@02010000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02010000 0x4000>;
+                                        interrupts = <0 33 0x04>;
+                                        clocks = <&clks 114>, <&clks 114>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi4: ecspi@02014000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02014000 0x4000>;
+                                        interrupts = <0 34 0x04>;
+                                        clocks = <&clks 115>, <&clks 115>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                uart1: serial@02020000 {
+                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                        reg = <0x02020000 0x4000>;
+                                        interrupts = <0 26 0x04>;
+                                        clocks = <&clks 160>, <&clks 161>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                esai: esai@02024000 {
+                                        reg = <0x02024000 0x4000>;
+                                        interrupts = <0 51 0x04>;
+                                };
+                                ssi1: ssi@02028000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        reg = <0x02028000 0x4000>;
+                                        interrupts = <0 46 0x04>;
+                                        clocks = <&clks 178>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <38 37>;
+                                        status = "disabled";
+                                };
+                                ssi2: ssi@0202c000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        reg = <0x0202c000 0x4000>;
+                                        interrupts = <0 47 0x04>;
+                                        clocks = <&clks 179>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <42 41>;
+                                        status = "disabled";
+                                };
+                                ssi3: ssi@02030000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        reg = <0x02030000 0x4000>;
+                                        interrupts = <0 48 0x04>;
+                                        clocks = <&clks 180>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <46 45>;
+                                        status = "disabled";
+                                };
+                                asrc: asrc@02034000 {
+                                        reg = <0x02034000 0x4000>;
+                                        interrupts = <0 50 0x04>;
+                                };
+                                spba@0203c000 {
+                                        reg = <0x0203c000 0x4000>;
+                                };
+                        };
+                        vpu: vpu@02040000 {
+                                reg = <0x02040000 0x3c000>;
+                                interrupts = <0 3 0x04 0 12 0x04>;
+                        };
+                        aipstz@0207c000 { /* AIPSTZ1 */
+                                reg = <0x0207c000 0x4000>;
+                        };
+                        pwm1: pwm@02080000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                                reg = <0x02080000 0x4000>;
+                                interrupts = <0 83 0x04>;
+                                clocks = <&clks 62>, <&clks 145>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm2: pwm@02084000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                                reg = <0x02084000 0x4000>;
+                                interrupts = <0 84 0x04>;
+                                clocks = <&clks 62>, <&clks 146>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm3: pwm@02088000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                                reg = <0x02088000 0x4000>;
+                                interrupts = <0 85 0x04>;
+                                clocks = <&clks 62>, <&clks 147>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm4: pwm@0208c000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+                                reg = <0x0208c000 0x4000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks 62>, <&clks 148>;
+                                clock-names = "ipg", "per";
+                        };
+                        can1: flexcan@02090000 {
+                                reg = <0x02090000 0x4000>;
+                                interrupts = <0 110 0x04>;
+                        };
+                        can2: flexcan@02094000 {
+                                reg = <0x02094000 0x4000>;
+                                interrupts = <0 111 0x04>;
+                        };
+                        gpt: gpt@02098000 {
+                                compatible = "fsl,imx6q-gpt";
+                                reg = <0x02098000 0x4000>;
+                                interrupts = <0 55 0x04>;
+                        };
+                        gpio1: gpio@0209c000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x0209c000 0x4000>;
+                                interrupts = <0 66 0x04 0 67 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio@020a0000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a0000 0x4000>;
+                                interrupts = <0 68 0x04 0 69 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio3: gpio@020a4000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a4000 0x4000>;
+                                interrupts = <0 70 0x04 0 71 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio4: gpio@020a8000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a8000 0x4000>;
+                                interrupts = <0 72 0x04 0 73 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio5: gpio@020ac000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020ac000 0x4000>;
+                                interrupts = <0 74 0x04 0 75 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio6: gpio@020b0000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020b0000 0x4000>;
+                                interrupts = <0 76 0x04 0 77 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio7: gpio@020b4000 {
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+                                reg = <0x020b4000 0x4000>;
+                                interrupts = <0 78 0x04 0 79 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        kpp: kpp@020b8000 {
+                                reg = <0x020b8000 0x4000>;
+                                interrupts = <0 82 0x04>;
+                        };
+                        wdog1: wdog@020bc000 {
+                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                                reg = <0x020bc000 0x4000>;
+                                interrupts = <0 80 0x04>;
+                                clocks = <&clks 0>;
+                        };
+                        wdog2: wdog@020c0000 {
+                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+                                reg = <0x020c0000 0x4000>;
+                                interrupts = <0 81 0x04>;
+                                clocks = <&clks 0>;
+                                status = "disabled";
+                        };
+                        clks: ccm@020c4000 {
+                                compatible = "fsl,imx6q-ccm";
+                                reg = <0x020c4000 0x4000>;
+                                interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
+                                reg = <0x020c8000 0x1000>;
+                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+                                regulator-1p1@110 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p1";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1375000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x110>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <4>;
+                                        anatop-min-voltage = <800000>;
+                                        anatop-max-voltage = <1375000>;
+                                };
+                                regulator-3p0@120 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd3p0";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <3150000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x120>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2625000>;
+                                        anatop-max-voltage = <3400000>;
+                                };
+                                regulator-2p5@130 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd2p5";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x130>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2000000>;
+                                        anatop-max-voltage = <2750000>;
+                                };
+                                reg_arm: regulator-vddcore@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "cpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <0>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <24>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                                reg_pu: regulator-vddpu@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <9>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <26>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                                reg_soc: regulator-vddsoc@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddsoc";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <18>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <28>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                        };
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020c9000 0x1000>;
+                                interrupts = <0 44 0x04>;
+                                clocks = <&clks 182>;
+                        };
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020ca000 0x1000>;
+                                interrupts = <0 45 0x04>;
+                                clocks = <&clks 183>;
+                        };
+                        snvs@020cc000 {
+                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x020cc000 0x4000>;
+                                snvs-rtc-lp@34 {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        reg = <0x34 0x58>;
+                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                };
+                        };
+                        epit1: epit@020d0000 { /* EPIT1 */
+                                reg = <0x020d0000 0x4000>;
+                                interrupts = <0 56 0x04>;
+                        };
+                        epit2: epit@020d4000 { /* EPIT2 */
+                                reg = <0x020d4000 0x4000>;
+                                interrupts = <0 57 0x04>;
+                        };
+                        src: src@020d8000 {
+                                compatible = "fsl,imx6q-src";
+                                reg = <0x020d8000 0x4000>;
+                                interrupts = <0 91 0x04 0 96 0x04>;
+                        };
+                        gpc: gpc@020dc000 {
+                                compatible = "fsl,imx6q-gpc";
+                                reg = <0x020dc000 0x4000>;
+                                interrupts = <0 89 0x04 0 90 0x04>;
+                        };
+                        gpr: iomuxc-gpr@020e0000 {
+                                compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                                reg = <0x020e0000 0x38>;
+                        };
+                        dcic1: dcic@020e4000 {
+                                reg = <0x020e4000 0x4000>;
+                                interrupts = <0 124 0x04>;
+                        };
+                        dcic2: dcic@020e8000 {
+                                reg = <0x020e8000 0x4000>;
+                                interrupts = <0 125 0x04>;
+                        };
+                        sdma: sdma@020ec000 {
+                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+                                reg = <0x020ec000 0x4000>;
+                                interrupts = <0 2 0x04>;
+                                clocks = <&clks 155>, <&clks 155>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+                        };
+                };
+                aips-bus@02100000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02100000 0x100000>;
+                        ranges;
+                        caam@02100000 {
+                                reg = <0x02100000 0x40000>;
+                                interrupts = <0 105 0x04 0 106 0x04>;
+                        };
+                        aipstz@0217c000 { /* AIPSTZ2 */
+                                reg = <0x0217c000 0x4000>;
+                        };
+                        usbotg: usb@02184000 {
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+                        usbh1: usb@02184200 {
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+                        usbh2: usb@02184400 {
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 41 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 2>;
+                                status = "disabled";
+                        };
+                        usbh3: usb@02184600 {
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184600 0x200>;
+                                interrupts = <0 42 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 3>;
+                                status = "disabled";
+                        };
+                        usbmisc: usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks 162>;
+                        };
+                        fec: ethernet@02188000 {
+                                compatible = "fsl,imx6q-fec";
+                                reg = <0x02188000 0x4000>;
+                                interrupts = <0 118 0x04 0 119 0x04>;
+                                clocks = <&clks 117>, <&clks 117>, <&clks 190>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                        mlb@0218c000 {
+                                reg = <0x0218c000 0x4000>;
+                                interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
+                        };
+                        usdhc1: usdhc@02190000 {
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02190000 0x4000>;
+                                interrupts = <0 22 0x04>;
+                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc2: usdhc@02194000 {
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02194000 0x4000>;
+                                interrupts = <0 23 0x04>;
+                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc3: usdhc@02198000 {
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x02198000 0x4000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc4: usdhc@0219c000 {
+                                compatible = "fsl,imx6q-usdhc";
+                                reg = <0x0219c000 0x4000>;
+                                interrupts = <0 25 0x04>;
+                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@021a0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a0000 0x4000>;
+                                interrupts = <0 36 0x04>;
+                                clocks = <&clks 125>;
+                                status = "disabled";
+                        };
+                        i2c2: i2c@021a4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a4000 0x4000>;
+                                interrupts = <0 37 0x04>;
+                                clocks = <&clks 126>;
+                                status = "disabled";
+                        };
+                        i2c3: i2c@021a8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a8000 0x4000>;
+                                interrupts = <0 38 0x04>;
+                                clocks = <&clks 127>;
+                                status = "disabled";
+                        };
+                        romcp@021ac000 {
+                                reg = <0x021ac000 0x4000>;
+                        };
+                        mmdc0: mmdc@021b0000 { /* MMDC0 */
+                                compatible = "fsl,imx6q-mmdc";
+                                reg = <0x021b0000 0x4000>;
+                        };
+                        mmdc1: mmdc@021b4000 { /* MMDC1 */
+                                reg = <0x021b4000 0x4000>;
+                        };
+                        weim@021b8000 {
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <0 14 0x04>;
+                        };
+                        ocotp@021bc000 {
+                                compatible = "fsl,imx6q-ocotp";
+                                reg = <0x021bc000 0x4000>;
+                        };
+                        ocotp@021c0000 {
+                                reg = <0x021c0000 0x4000>;
+                                interrupts = <0 21 0x04>;
+                        };
+                        tzasc@021d0000 { /* TZASC1 */
+                                reg = <0x021d0000 0x4000>;
+                                interrupts = <0 108 0x04>;
+                        };
+                        tzasc@021d4000 { /* TZASC2 */
+                                reg = <0x021d4000 0x4000>;
+                                interrupts = <0 109 0x04>;
+                        };
+                        audmux: audmux@021d8000 {
+                                compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+                                reg = <0x021d8000 0x4000>;
+                                status = "disabled";
+                        };
+                        mipi@021dc000 { /* MIPI-CSI */
+                                reg = <0x021dc000 0x4000>;
+                        };
+                        mipi@021e0000 { /* MIPI-DSI */
+                                reg = <0x021e0000 0x4000>;
+                        };
+                        vdoa@021e4000 {
+                                reg = <0x021e4000 0x4000>;
+                                interrupts = <0 18 0x04>;
+                        };
+                        uart2: serial@021e8000 {
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021e8000 0x4000>;
+                                interrupts = <0 27 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart3: serial@021ec000 {
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021ec000 0x4000>;
+                                interrupts = <0 28 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart4: serial@021f0000 {
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021f0000 0x4000>;
+                                interrupts = <0 29 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart5: serial@021f4000 {
+                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+                                reg = <0x021f4000 0x4000>;
+                                interrupts = <0 30 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+                ipu1: ipu@02400000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx6q-ipu";
+                        reg = <0x02400000 0x400000>;
+                        interrupts = <0 6 0x4 0 5 0x4>;
+                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
+                        clock-names = "bus", "di0", "di1";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 4ccea2130a6c..192cf76fbf93 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -5,6 +5,12 @@
                        compatible = "marvell,88f6282-pinctrl";
                        reg = <0x10000 0x20>;
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                                        "mpp4", "mpp5", "mpp18", "mpp19";
+                                marvell,function = "nand";
+                        };
                        pmx_sata0: pmx-sata0 {
                                marvell,pins = "mpp5", "mpp21", "mpp23";
                                marvell,function = "sata0";
@@ -21,6 +27,12 @@
                                marvell,pins = "mpp8", "mpp9";
                                marvell,function = "twsi0";
                        };
+                        pmx_twsi1: pmx-twsi1 {
+                                marvell,pins = "mpp36", "mpp37";
+                                marvell,function = "twsi1";
+                        };
                        pmx_uart0: pmx-uart0 {
                                marvell,pins = "mpp10", "mpp11";
                                marvell,function = "uart0";
@@ -30,6 +42,11 @@
                                marvell,pins = "mpp13", "mpp14";
                                marvell,function = "uart1";
                        };
+                        pmx_sdio: pmx-sdio {
+                                marvell,pins = "mpp12", "mpp13", "mpp14",
+                                               "mpp15", "mpp16", "mpp17";
+                                marvell,function = "sdio";
+                        };
                };
                i2c@11100 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index f2d386c95b07..ef2d8c705709 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -74,6 +74,13 @@
                        status = "okay";
                        nr-ports = <1>;
                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                };
        };
        gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
new file mode 100644
index 000000000000..9555a86297c2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -0,0 +1,94 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+/ {
+        model = "Globalscale Technologies Guruplug Server Plus";
+        compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+                                      &pmx_led_wmode_r &pmx_led_wmode_g >;
+                        pinctrl-names = "default";
+                        pmx_led_health_r: pmx-led-health-r {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_health_g: pmx-led-health-g {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wmode_r: pmx-led-wmode-r {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wmode_g: pmx-led-wmode-g {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x00100000 0x00400000>;
+                        };
+                        partition@500000 {
+                                label = "data";
+                                reg = <0x00500000 0x1fb00000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                health-r {
+                        label = "guruplug:red:health";
+                        gpios = <&gpio1 14 1>;
+                };
+                health-g {
+                        label = "guruplug:green:health";
+                        gpios = <&gpio1 15 1>;
+                };
+                wmode-r {
+                        label = "guruplug:red:wmode";
+                        gpios = <&gpio1 16 1>;
+                };
+                wmode-g {
+                        label = "guruplug:green:wmode";
+                        gpios = <&gpio1 17 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 262c65403760..662dfd81b1ce 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -20,12 +20,11 @@
                pinctrl: pinctrl@10000 {
                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                      &pmx_led_health &pmx_sdio
+                                      &pmx_led_health
                                      &pmx_sata0 &pmx_sata1
                                      &pmx_led_user1o
                                      &pmx_led_user1g &pmx_led_user0o
                                      &pmx_led_user0g &pmx_led_misc
-                                      &pmx_sdio_cd
                                    >;
                        pinctrl-names = "default";
@@ -133,6 +132,14 @@
                        status = "okay";
                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        cd-gpios = <&gpio1 15 0>;
+                        /* No WP GPIO */
+                };
        };
        gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 77d21abfcdf7..e8e7ecef1650 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -76,4 +76,10 @@
                        gpios = <&gpio0 12 0>;
                };
        };
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 31 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 5509f9659546..3a178cf708d7 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -16,6 +16,105 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_led_esata_green
+                                      &pmx_led_esata_red
+                                      &pmx_led_usb_green
+                                      &pmx_led_usb_red
+                                      &pmx_usb_power_off
+                                      &pmx_led_sys_green
+                                      &pmx_led_sys_red
+                                      &pmx_btn_reset
+                                      &pmx_btn_copy
+                                      &pmx_led_copy_green
+                                      &pmx_led_copy_red
+                                      &pmx_led_hdd_green
+                                      &pmx_led_hdd_red
+                                      &pmx_unknown
+                                      &pmx_btn_power
+                                      &pmx_pwr_off >;
+                        pinctrl-names = "default";
+                        pmx_led_esata_green: pmx-led-esata-green {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_esata_red: pmx-led-esata-red {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_usb_green: pmx-led-usb-green {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_usb_red: pmx-led-usb-red {
+                                marvell,pins = "mpp16";
+                                marvell,function = "gpio";
+                        };
+                        pmx_usb_power_off: pmx-usb-power-off {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_green: pmx-led-sys-green {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_red: pmx-led-sys-red {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_reset: pmx-btn-reset {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_copy: pmx-btn-copy {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_copy_green: pmx-led-copy-green {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_copy_red: pmx-led-copy-red {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_hdd_green: pmx-led-hdd-green {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_hdd_red: pmx-led-hdd-red {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_unknown: pmx-unknown {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_power: pmx-btn-power {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_pwr_off: pmx-pwr-off {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
@@ -29,6 +128,11 @@
                i2c@11000 {
                        status = "okay";
+                        adt7476: adt7476a@2e {
+                                compatible = "adt7476";
+                                reg = <0x2e>;
+                        };
                };
                nand@3000000 {
@@ -141,4 +245,26 @@
                        gpios = <&gpio1 8 0>;
                };
        };
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio1 16 0>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb0_power_off: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power Off";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 21 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 49d3d74d4d38..ede7fe0d7a87 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -75,6 +75,122 @@
                                reg = <0x30>;
                        };
                };
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_nand &pmx_uart0
+                                &pmx_uart1 &pmx_twsi1
+                                &pmx_dip_sw0 &pmx_dip_sw1
+                                &pmx_dip_sw2 &pmx_dip_sw3
+                                &pmx_gpio_0 &pmx_gpio_1
+                                &pmx_gpio_2 &pmx_gpio_3
+                                &pmx_gpio_4 &pmx_gpio_5
+                                &pmx_gpio_6 &pmx_gpio_7
+                                &pmx_led_red &pmx_led_green
+                                &pmx_led_yellow >;
+                        pinctrl-names = "default";
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11", "mpp15",
+                                        "mpp16";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14", "mpp8",
+                                        "mpp9";
+                                marvell,function = "uart1";
+                        };
+                        pmx_sysrst: pmx-sysrst {
+                                marvell,pins = "mpp6";
+                                marvell,function = "sysrst";
+                        };
+                        pmx_dip_sw0: pmx-dip-sw0 {
+                                marvell,pins = "mpp20";
+                                marvell,function = "gpio";
+                        };
+                        pmx_dip_sw1: pmx-dip-sw1 {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_dip_sw2: pmx-dip-sw2 {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+                        pmx_dip_sw3: pmx-dip-sw3 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_0: pmx-gpio-0 {
+                                marvell,pins = "mpp24";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_1: pmx-gpio-1 {
+                                marvell,pins = "mpp25";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_2: pmx-gpio-2 {
+                                marvell,pins = "mpp26";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_3: pmx-gpio-3 {
+                                marvell,pins = "mpp27";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_4: pmx-gpio-4 {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_5: pmx-gpio-5 {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_6: pmx-gpio-6 {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_7: pmx-gpio-7 {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_init: pmx-init {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_usb_oc: pmx-usb-oc {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red: pmx-led-red {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_green: pmx-led-green {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_yellow: pmx-led-yellow {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                };
        };
        gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index cd15452a52a6..842ff95d60df 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6282.dtsi"
 / {
        model = "Univeral Scientific Industrial Co. Topkick-1281P2";
@@ -16,6 +17,96 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        /*
+                         * GPIO LED layout
+                         *
+                         *       /-SYS_LED(2)
+                         *       |
+                         *       |   /-DISK_LED
+                         *       |   |
+                         *       |   |   /-WLAN_LED(2)
+                         *       |   |   |
+                         * [SW] [*] [*] [*]
+                         */
+                        /*
+                         * Switch positions
+                         *
+                         *     /-SW_LEFT(2)
+                         *     |
+                         *     |   /-SW_IDLE
+                         *     |   |
+                         *     |   |   /-SW_RIGHT
+                         *     |   |   |
+                         * PS [L] [I] [R] LEDS
+                         */
+                        pinctrl-0 = < &pmx_led_disk_yellow
+                                      &pmx_sata0_pwr_enable
+                                      &pmx_led_sys_red
+                                      &pmx_led_sys_blue
+                                      &pmx_led_wifi_green
+                                      &pmx_sw_left
+                                      &pmx_sw_right
+                                      &pmx_sw_idle
+                                      &pmx_sw_left2
+                                      &pmx_led_wifi_yellow
+                                      &pmx_uart0
+                                      &pmx_nand
+                                      &pmx_twsi0 >;
+                        pinctrl-names = "default";
+                        pmx_led_disk_yellow: pmx-led-disk-yellow {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sata0_pwr_enable: pmx-sata0-pwr-enable {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_red: pmx-led-sys-red {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_blue: pmx-led-sys-blue {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wifi_green: pmx-led-wifi-green {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sw_left: pmx-sw-left {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sw_right: pmx-sw-right {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sw_idle: pmx-sw-idle {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sw_left2: pmx-sw-left2 {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wifi_yellow: pmx-led-wifi-yellow {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "ok";
@@ -54,6 +145,17 @@
                        status = "okay";
                        nr-ports = <1>;
                };
+                i2c@11000 {
+                        status = "ok";
+                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                };
        };
        gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index d6ab442b7011..2c738d9dc82a 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -193,5 +193,13 @@
                        clocks = <&gate_clk 17>;
                        status = "okay";
                };
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
new file mode 100644
index 000000000000..5130aeacfca5
--- /dev/null
+++ b/arch/arm/boot/dts/marco-evb.dts
@@ -0,0 +1,54 @@
+/*
+ * DTS file for CSR SiRFmarco Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "marco.dtsi"
+/ {
+        model = "CSR SiRFmarco Evaluation Board";
+        compatible = "sirf,marco-cb", "sirf,marco";
+        memory {
+                reg = <0x40000000 0x60000000>;
+        };
+        axi {
+                peri-iobg {
+                        uart1: uart@cc060000 {
+                                status = "okay";
+                        };
+                        uart2: uart@cc070000 {
+                                status = "okay";
+                        };
+                        i2c0: i2c@cc0e0000 {
+                              status = "okay";
+                              fpga-cpld@4d {
+                                      compatible = "sirf,fpga-cpld";
+                                      reg = <0x4d>;
+                              };
+                        };
+                        spi1: spi@cc170000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                                spi@0 {
+                                        compatible = "spidev";
+                                        reg = <0>;
+                                        spi-max-frequency = <1000000>;
+                                };
+                        };
+                        pci-iobg {
+                                sd0: sdhci@cd000000 {
+                                        bus-width = <8>;
+                                        status = "okay";
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
new file mode 100644
index 000000000000..1579c3491ccd
--- /dev/null
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -0,0 +1,756 @@
+/*
+ * DTS file for CSR SiRFmarco SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,marco";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0xa0000000>;
+                l2-cache-controller@c0030000 {
+                        compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
+                        reg = <0xc0030000 0x1000>;
+                        interrupts = <0 59 0>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <1 1 1>;
+                        arm,filter-ranges = <0x40000000 0x80000000>;
+                };
+                gic: interrupt-controller@c0011000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0xc0011000 0x1000>,
+                              <0xc0010100 0x0100>;
+                };
+                rstc-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc2000000 0xc2000000 0x1000000>;
+                        reset-controller@c2000000 {
+                                compatible = "sirf,marco-rstc";
+                                reg = <0xc2000000 0x10000>;
+                        };
+                };
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc3000000 0xc3000000 0x1000000>;
+                        clock-controller@c3000000 {
+                                compatible = "sirf,marco-clkc";
+                                reg = <0xc3000000 0x1000>;
+                                interrupts = <0 3 0>;
+                        };
+                        rsc-controller@c3010000 {
+                                compatible = "sirf,marco-rsc";
+                                reg = <0xc3010000 0x1000>;
+                        };
+                };
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc4000000 0xc4000000 0x1000000>;
+                        memory-controller@c4000000 {
+                                compatible = "sirf,marco-memc";
+                                reg = <0xc4000000 0x10000>;
+                                interrupts = <0 27 0>;
+                        };
+                };
+                disp-iobg0 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc5000000 0xc5000000 0x1000000>;
+                        display0@c5000000 {
+                                compatible = "sirf,marco-lcd";
+                                reg = <0xc5000000 0x10000>;
+                                interrupts = <0 30 0>;
+                        };
+                        vpp0@c5010000 {
+                                compatible = "sirf,marco-vpp";
+                                reg = <0xc5010000 0x10000>;
+                                interrupts = <0 31 0>;
+                        };
+                };
+                disp-iobg1 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc6000000 0xc6000000 0x1000000>;
+                        display1@c6000000 {
+                                compatible = "sirf,marco-lcd";
+                                reg = <0xc6000000 0x10000>;
+                                interrupts = <0 62 0>;
+                        };
+                        vpp1@c6010000 {
+                                compatible = "sirf,marco-vpp";
+                                reg = <0xc6010000 0x10000>;
+                                interrupts = <0 63 0>;
+                        };
+                };
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc8000000 0xc8000000 0x1000000>;
+                        graphics@c8000000 {
+                                compatible = "powervr,sgx540";
+                                reg = <0xc8000000 0x1000000>;
+                                interrupts = <0 6 0>;
+                        };
+                };
+                multimedia-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xc9000000 0xc9000000 0x1000000>;
+                        multimedia@a0000000 {
+                                compatible = "sirf,marco-video-codec";
+                                reg = <0xc9000000 0x1000000>;
+                                interrupts = <0 5 0>;
+                        };
+                };
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xca000000 0xca000000 0x2000000>;
+                        dspif@ca000000 {
+                                compatible = "sirf,marco-dspif";
+                                reg = <0xca000000 0x10000>;
+                                interrupts = <0 9 0>;
+                        };
+                        gps@ca010000 {
+                                compatible = "sirf,marco-gps";
+                                reg = <0xca010000 0x10000>;
+                                interrupts = <0 7 0>;
+                        };
+                        dsp@cb000000 {
+                                compatible = "sirf,marco-dsp";
+                                reg = <0xcb000000 0x1000000>;
+                                interrupts = <0 8 0>;
+                        };
+                };
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xcc000000 0xcc000000 0x2000000>;
+                        timer@cc020000 {
+                                compatible = "sirf,marco-tick";
+                                reg = <0xcc020000 0x1000>;
+                                interrupts = <0 0 0>,
+                                           <0 1 0>,
+                                           <0 2 0>,
+                                           <0 49 0>,
+                                           <0 50 0>,
+                                           <0 51 0>;
+                        };
+                        nand@cc030000 {
+                                compatible = "sirf,marco-nand";
+                                reg = <0xcc030000 0x10000>;
+                                interrupts = <0 41 0>;
+                        };
+                        audio@cc040000 {
+                                compatible = "sirf,marco-audio";
+                                reg = <0xcc040000 0x10000>;
+                                interrupts = <0 35 0>;
+                        };
+                        uart0: uart@cc050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,marco-uart";
+                                reg = <0xcc050000 0x1000>;
+                                interrupts = <0 17 0>;
+                                fifosize = <128>;
+                                status = "disabled";
+                        };
+                        uart1: uart@cc060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,marco-uart";
+                                reg = <0xcc060000 0x1000>;
+                                interrupts = <0 18 0>;
+                                fifosize = <32>;
+                                status = "disabled";
+                        };
+                        uart2: uart@cc070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,marco-uart";
+                                reg = <0xcc070000 0x1000>;
+                                interrupts = <0 19 0>;
+                                fifosize = <128>;
+                                status = "disabled";
+                        };
+                        uart3: uart@cc190000 {
+                                cell-index = <3>;
+                                compatible = "sirf,marco-uart";
+                                reg = <0xcc190000 0x1000>;
+                                interrupts = <0 66 0>;
+                                fifosize = <128>;
+                                status = "disabled";
+                        };
+                        uart4: uart@cc1a0000 {
+                                cell-index = <4>;
+                                compatible = "sirf,marco-uart";
+                                reg = <0xcc1a0000 0x1000>;
+                                interrupts = <0 69 0>;
+                                fifosize = <128>;
+                                status = "disabled";
+                        };
+                        usp0: usp@cc080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,marco-usp";
+                                reg = <0xcc080000 0x10000>;
+                                interrupts = <0 20 0>;
+                                status = "disabled";
+                        };
+                        usp1: usp@cc090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,marco-usp";
+                                reg = <0xcc090000 0x10000>;
+                                interrupts = <0 21 0>;
+                                status = "disabled";
+                        };
+                        usp2: usp@cc0a0000 {
+                                cell-index = <2>;
+                                compatible = "sirf,marco-usp";
+                                reg = <0xcc0a0000 0x10000>;
+                                interrupts = <0 22 0>;
+                                status = "disabled";
+                        };
+                        dmac0: dma-controller@cc0b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,marco-dmac";
+                                reg = <0xcc0b0000 0x10000>;
+                                interrupts = <0 12 0>;
+                        };
+                        dmac1: dma-controller@cc160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,marco-dmac";
+                                reg = <0xcc160000 0x10000>;
+                                interrupts = <0 13 0>;
+                        };
+                        vip@cc0c0000 {
+                                compatible = "sirf,marco-vip";
+                                reg = <0xcc0c0000 0x10000>;
+                        };
+                        spi0: spi@cc0d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,marco-spi";
+                                reg = <0xcc0d0000 0x10000>;
+                                interrupts = <0 15 0>;
+                                sirf,spi-num-chipselects = <1>;
+                                cs-gpios = <&gpio 0 0>;
+                                sirf,spi-dma-rx-channel = <25>;
+                                sirf,spi-dma-tx-channel = <20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        spi1: spi@cc170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,marco-spi";
+                                reg = <0xcc170000 0x10000>;
+                                interrupts = <0 16 0>;
+                                sirf,spi-num-chipselects = <1>;
+                                cs-gpios = <&gpio 0 0>;
+                                sirf,spi-dma-rx-channel = <12>;
+                                sirf,spi-dma-tx-channel = <13>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@cc0e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,marco-i2c";
+                                reg = <0xcc0e0000 0x10000>;
+                                interrupts = <0 24 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@cc0f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,marco-i2c";
+                                reg = <0xcc0f0000 0x10000>;
+                                interrupts = <0 25 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        tsc@cc110000 {
+                                compatible = "sirf,marco-tsc";
+                                reg = <0xcc110000 0x10000>;
+                                interrupts = <0 33 0>;
+                        };
+                        gpio: pinctrl@cc120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,marco-pinctrl";
+                                reg = <0xcc120000 0x10000>;
+                                interrupts = <0 43 0>,
+                                           <0 44 0>,
+                                           <0 45 0>,
+                                           <0 46 0>,
+                                           <0 47 0>;
+                                gpio-controller;
+                                interrupt-controller;
+                                lcd_16pins_a: lcd0_0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0_1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0_2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0_0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0_0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1_0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2_0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2_1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0_0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1_0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0_0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1_0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0_0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1_0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2_0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3_0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                gps_pins_a: gps_0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip_0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0_0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1_0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2_0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3_0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc4_pins_a: sdmmc4_0 {
+                                        sdmmc4 {
+                                                sirf,pins = "sdmmc4grp";
+                                                sirf,function = "sdmmc4";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5_0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s_0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                ac97_pins_a: ac97_0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand_0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0_0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1_0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usp2_pins_a: usp2_0 {
+                                        usp2 {
+                                                sirf,pins = "usp2grp";
+                                                sirf,function = "usp2";
+                                        };
+                                };
+                                usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
+                                        usb0_utmi_drvbus {
+                                                sirf,pins = "usb0_utmi_drvbusgrp";
+                                                sirf,function = "usb0_utmi_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst_0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count_0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst_0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst_0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+                        pwm@cc130000 {
+                                compatible = "sirf,marco-pwm";
+                                reg = <0xcc130000 0x10000>;
+                        };
+                        efusesys@cc140000 {
+                                compatible = "sirf,marco-efuse";
+                                reg = <0xcc140000 0x10000>;
+                        };
+                        pulsec@cc150000 {
+                                compatible = "sirf,marco-pulsec";
+                                reg = <0xcc150000 0x10000>;
+                                interrupts = <0 48 0>;
+                        };
+                        pci-iobg {
+                                compatible = "sirf,marco-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0xcd000000 0xcd000000 0x1000000>;
+                                sd0: sdhci@cd000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd000000 0x100000>;
+                                        interrupts = <0 38 0>;
+                                        status = "disabled";
+                                };
+                                sd1: sdhci@cd100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd100000 0x100000>;
+                                        interrupts = <0 38 0>;
+                                        status = "disabled";
+                                };
+                                sd2: sdhci@cd200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd200000 0x100000>;
+                                        interrupts = <0 23 0>;
+                                        status = "disabled";
+                                };
+                                sd3: sdhci@cd300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd300000 0x100000>;
+                                        interrupts = <0 23 0>;
+                                        status = "disabled";
+                                };
+                                sd4: sdhci@cd400000 {
+                                        cell-index = <4>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd400000 0x100000>;
+                                        interrupts = <0 39 0>;
+                                        status = "disabled";
+                                };
+                                sd5: sdhci@cd500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,marco-sdhc";
+                                        reg = <0xcd500000 0x100000>;
+                                        interrupts = <0 39 0>;
+                                        status = "disabled";
+                                };
+                                pci-copy@cd900000 {
+                                        compatible = "sirf,marco-pcicp";
+                                        reg = <0xcd900000 0x100000>;
+                                        interrupts = <0 40 0>;
+                                };
+                                rom-interface@cda00000 {
+                                        compatible = "sirf,marco-romif";
+                                        reg = <0xcda00000 0x100000>;
+                                };
+                        };
+                };
+                rtc-iobg {
+                        compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xc1000000 0x10000>;
+                        gpsrtc@1000 {
+                                compatible = "sirf,marco-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <0 55 0>,
+                                           <0 56 0>,
+                                           <0 57 0>;
+                        };
+                        sysrtc@2000 {
+                                compatible = "sirf,marco-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <0 52 0>,
+                                           <0 53 0>,
+                                           <0 54 0>;
+                        };
+                        pwrc@3000 {
+                                compatible = "sirf,marco-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <0 32 0>;
+                        };
+                };
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xce000000 0xce000000 0x1000000>;
+                        usb0: usb@ce000000 {
+                                compatible = "chipidea,ci13611a-marco";
+                                reg = <0xce000000 0x10000>;
+                                interrupts = <0 10 0>;
+                        };
+                        usb1: usb@ce010000 {
+                                compatible = "chipidea,ci13611a-marco";
+                                reg = <0xce010000 0x10000>;
+                                interrupts = <0 11 0>;
+                        };
+                        security@ce020000 {
+                                compatible = "sirf,marco-security";
+                                reg = <0xce020000 0x10000>;
+                                interrupts = <0 42 0>;
+                        };
+                };
+                can-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xd0000000 0xd0000000 0x1000000>;
+                        can0: can@d0000000 {
+                                compatible = "sirf,marco-can";
+                                reg = <0xd0000000 0x10000>;
+                        };
+                        can1: can@d0010000 {
+                                compatible = "sirf,marco-can";
+                                reg = <0xd0010000 0x10000>;
+                        };
+                };
+                lvds-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xd1000000 0xd1000000 0x1000000>;
+                        lvds@d1000000 {
+                                compatible = "sirf,marco-lvds";
+                                reg = <0xd1000000 0x10000>;
+                                interrupts = <0 64 0>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index c9b4f27d191e..7f70a39459f6 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -29,6 +29,164 @@
                        };
                        twsi1: i2c@d4011000 {
                                status = "okay";
+                                pmic: max8925@3c {
+                                        compatible = "maxium,max8925";
+                                        reg = <0x3c>;
+                                        interrupts = <1>;
+                                        interrupt-parent = <&intcmux4>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <1>;
+                                        maxim,tsc-irq = <0>;
+                                        regulators {
+                                                SDV1 {
+                                                        regulator-min-microvolt = <637500>;
+                                                        regulator-max-microvolt = <1425000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                SDV2 {
+                                                        regulator-min-microvolt = <650000>;
+                                                        regulator-max-microvolt = <2225000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                SDV3 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO1 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO2 {
+                                                        regulator-min-microvolt = <650000>;
+                                                        regulator-max-microvolt = <2250000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO3 {
+                                                        regulator-min-microvolt = <650000>;
+                                                        regulator-max-microvolt = <2250000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO4 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO5 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO6 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO7 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO8 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO9 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO10 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                };
+                                                LDO11 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO12 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO13 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO14 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO15 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO16 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO17 {
+                                                        regulator-min-microvolt = <650000>;
+                                                        regulator-max-microvolt = <2250000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO18 {
+                                                        regulator-min-microvolt = <650000>;
+                                                        regulator-max-microvolt = <2250000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO19 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO20 {
+                                                        regulator-min-microvolt = <750000>;
+                                                        regulator-max-microvolt = <3900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                        };
+                                        backlight {
+                                                maxim,max8925-dual-string = <0>;
+                                        };
+                                        charger {
+                                                batt-detect = <0>;
+                                                topoff-threshold = <1>;
+                                                fast-charge = <7>;
+                                                no-temp-support = <0>;
+                                                no-insert-detect = <0>;
+                                        };
+                                };
                        };
                        rtc: rtc@d4010000 {
                                status = "okay";
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 0514fb41627e..1429ac05b36d 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -46,7 +46,7 @@
                                mrvl,intc-nr-irqs = <64>;
                        };
-                        intcmux4@d4282150 {
+                        intcmux4: interrupt-controller@d4282150 {
                                compatible = "mrvl,mmp2-mux-intc";
                                interrupts = <4>;
                                interrupt-controller;
@@ -201,6 +201,8 @@
                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                mrvl,i2c-fast-mode;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 055fca542120..3329719a9412 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -58,10 +58,11 @@
                        #size-cells = <1>;
                        ranges = <0x88000000 0x88000000 0x40000>;
-                        clock-controller@88000000 {
+                        clks: clock-controller@88000000 {
                                compatible = "sirf,prima2-clkc";
                                reg = <0x88000000 0x1000>;
                                interrupts = <3>;
+                                #clock-cells = <1>;
                        };
                        reset-controller@88010000 {
@@ -85,6 +86,7 @@
                                compatible = "sirf,prima2-memc";
                                reg = <0x90000000 0x10000>;
                                interrupts = <27>;
+                                clocks = <&clks 5>;
                        };
                };
@@ -104,6 +106,7 @@
                                compatible = "sirf,prima2-vpp";
                                reg = <0x90020000 0x10000>;
                                interrupts = <31>;
+                                clocks = <&clks 35>;
                        };
                };
@@ -117,6 +120,7 @@
                                compatible = "powervr,sgx531";
                                reg = <0x98000000 0x8000000>;
                                interrupts = <6>;
+                                clocks = <&clks 32>;
                        };
                };
@@ -130,6 +134,7 @@
                                compatible = "sirf,prima2-video-codec";
                                reg = <0xa0000000 0x8000000>;
                                interrupts = <5>;
+                                clocks = <&clks 33>;
                        };
                };
@@ -149,12 +154,14 @@
                                compatible = "sirf,prima2-gps";
                                reg = <0xa8010000 0x10000>;
                                interrupts = <7>;
+                                clocks = <&clks 9>;
                        };
                        dsp@a9000000 {
                                compatible = "sirf,prima2-dsp";
                                reg = <0xa9000000 0x1000000>;
                                interrupts = <8>;
+                                clocks = <&clks 8>;
                        };
                };
@@ -174,12 +181,14 @@
                                compatible = "sirf,prima2-nand";
                                reg = <0xb0030000 0x10000>;
                                interrupts = <41>;
+                                clocks = <&clks 26>;
                        };
                        audio@b0040000 {
                                compatible = "sirf,prima2-audio";
                                reg = <0xb0040000 0x10000>;
                                interrupts = <35>;
+                                clocks = <&clks 27>;
                        };
                        uart0: uart@b0050000 {
@@ -187,6 +196,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0050000 0x10000>;
                                interrupts = <17>;
+                                clocks = <&clks 13>;
                        };
                        uart1: uart@b0060000 {
@@ -194,6 +204,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0060000 0x10000>;
                                interrupts = <18>;
+                                clocks = <&clks 14>;
                        };
                        uart2: uart@b0070000 {
@@ -201,6 +212,7 @@
                                compatible = "sirf,prima2-uart";
                                reg = <0xb0070000 0x10000>;
                                interrupts = <19>;
+                                clocks = <&clks 15>;
                        };
                        usp0: usp@b0080000 {
@@ -208,6 +220,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb0080000 0x10000>;
                                interrupts = <20>;
+                                clocks = <&clks 28>;
                        };
                        usp1: usp@b0090000 {
@@ -215,6 +228,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb0090000 0x10000>;
                                interrupts = <21>;
+                                clocks = <&clks 29>;
                        };
                        usp2: usp@b00a0000 {
@@ -222,6 +236,7 @@
                                compatible = "sirf,prima2-usp";
                                reg = <0xb00a0000 0x10000>;
                                interrupts = <22>;
+                                clocks = <&clks 30>;
                        };
                        dmac0: dma-controller@b00b0000 {
@@ -229,6 +244,7 @@
                                compatible = "sirf,prima2-dmac";
                                reg = <0xb00b0000 0x10000>;
                                interrupts = <12>;
+                                clocks = <&clks 24>;
                        };
                        dmac1: dma-controller@b0160000 {
@@ -236,11 +252,13 @@
                                compatible = "sirf,prima2-dmac";
                                reg = <0xb0160000 0x10000>;
                                interrupts = <13>;
+                                clocks = <&clks 25>;
                        };
                        vip@b00C0000 {
                                compatible = "sirf,prima2-vip";
                                reg = <0xb00C0000 0x10000>;
+                                clocks = <&clks 31>;
                        };
                        spi0: spi@b00d0000 {
@@ -248,6 +266,7 @@
                                compatible = "sirf,prima2-spi";
                                reg = <0xb00d0000 0x10000>;
                                interrupts = <15>;
+                                clocks = <&clks 19>;
                        };
                        spi1: spi@b0170000 {
@@ -255,6 +274,7 @@
                                compatible = "sirf,prima2-spi";
                                reg = <0xb0170000 0x10000>;
                                interrupts = <16>;
+                                clocks = <&clks 20>;
                        };
                        i2c0: i2c@b00e0000 {
@@ -262,6 +282,7 @@
                                compatible = "sirf,prima2-i2c";
                                reg = <0xb00e0000 0x10000>;
                                interrupts = <24>;
+                                clocks = <&clks 17>;
                        };
                        i2c1: i2c@b00f0000 {
@@ -269,12 +290,14 @@
                                compatible = "sirf,prima2-i2c";
                                reg = <0xb00f0000 0x10000>;
                                interrupts = <25>;
+                                clocks = <&clks 18>;
                        };
                        tsc@b0110000 {
                                compatible = "sirf,prima2-tsc";
                                reg = <0xb0110000 0x10000>;
                                interrupts = <33>;
+                                clocks = <&clks 16>;
                        };
                        gpio: pinctrl@b0120000 {
@@ -507,17 +530,20 @@
                        pwm@b0130000 {
                                compatible = "sirf,prima2-pwm";
                                reg = <0xb0130000 0x10000>;
+                                clocks = <&clks 21>;
                        };
                        efusesys@b0140000 {
                                compatible = "sirf,prima2-efuse";
                                reg = <0xb0140000 0x10000>;
+                                clocks = <&clks 22>;
                        };
                        pulsec@b0150000 {
                                compatible = "sirf,prima2-pulsec";
                                reg = <0xb0150000 0x10000>;
                                interrupts = <48>;
+                                clocks = <&clks 23>;
                        };
                        pci-iobg {
@@ -616,12 +642,14 @@
                                compatible = "chipidea,ci13611a-prima2";
                                reg = <0xb8000000 0x10000>;
                                interrupts = <10>;
+                                clocks = <&clks 40>;
                        };
                        usb1: usb@b00f0000 {
                                compatible = "chipidea,ci13611a-prima2";
                                reg = <0xb8010000 0x10000>;
                                interrupts = <11>;
+                                clocks = <&clks 41>;
                        };
                        sata@b00f0000 {
@@ -634,6 +662,7 @@
                                compatible = "sirf,prima2-security";
                                reg = <0xb8030000 0x10000>;
                                interrupts = <42>;
+                                clocks = <&clks 7>;
                        };
                };
        };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index a7505a95a3b7..93da655b2598 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -9,12 +9,16 @@
 */
 /dts-v1/;
-/include/ "skeleton.dtsi"
+/include/ "r8a7740.dtsi"
 / {
        model = "armadillo 800 eva";
        compatible = "renesas,armadillo800eva";
+        chosen {
+                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
+        };
        memory {
                device_type = "memory";
                reg = <0x40000000 0x20000000>;
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
index 286f0caef013..8acf51e0cdae 100644
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -9,12 +9,16 @@
 */
 /dts-v1/;
-/include/ "skeleton.dtsi"
+/include/ "sh7372.dtsi"
 / {
        model = "Mackerel (AP4 EVM 2nd)";
        compatible = "renesas,mackerel";
+        chosen {
+                bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
+        };
        memory {
                device_type = "memory";
                reg = <0x40000000 0x10000000>;
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index bcb911951978..7c4071e7790c 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -9,12 +9,16 @@
 */
 /dts-v1/;
-/include/ "skeleton.dtsi"
+/include/ "sh73a0.dtsi"
 / {
        model = "KZM-A9-GT";
        compatible = "renesas,kzm9g", "renesas,sh73a0";
+        chosen {
+                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
+        };
        memory {
                device_type = "memory";
                reg = <0x41000000 0x1e800000>;
diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi
new file mode 100644
index 000000000000..d4bb0125b2b2
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-reference.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "sh73a0.dtsi"
+/ {
+        compatible = "renesas,sh73a0";
+        mmcif: mmcif@0x10010000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0xe6bd0000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 140 0x4
+                              0 141 0x4>;
+                reg-io-width = <4>;
+        };
+};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
new file mode 100644
index 000000000000..8a59465d0231
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -0,0 +1,100 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "renesas,sh73a0";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        gic: interrupt-controller@f0001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xf0001000 0x1000>,
+                      <0xf0000100 0x100>;
+        };
+        i2c0: i2c@0xe6820000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6820000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 167 0x4
+                              0 168 0x4
+                              0 169 0x4
+                              0 170 0x4>;
+        };
+        i2c1: i2c@0xe6822000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6822000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 51 0x4
+                              0 52 0x4
+                              0 53 0x4
+                              0 54 0x4>;
+        };
+        i2c2: i2c@0xe6824000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6824000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 171 0x4
+                              0 172 0x4
+                              0 173 0x4
+                              0 174 0x4>;
+        };
+        i2c3: i2c@0xe6826000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6826000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 183 0x4
+                              0 184 0x4
+                              0 185 0x4
+                              0 186 0x4>;
+        };
+        i2c4: i2c@0xe6828000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6828000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 187 0x4
+                              0 188 0x4
+                              0 189 0x4
+                              0 190 0x4>;
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 19aec421bb26..936d2306e7e1 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -25,6 +25,10 @@
                ethernet0 = &gmac0;
                serial0 = &uart0;
                serial1 = &uart1;
+                timer0 = &timer0;
+                timer1 = &timer1;
+                timer2 = &timer2;
+                timer3 = &timer3;
        };
        cpus {
@@ -98,47 +102,41 @@
                        interrupts = <1 13 0xf04>;
                };
-                timer0: timer@ffc08000 {
+                timer0: timer0@ffc08000 {
                        compatible = "snps,dw-apb-timer-sp";
                        interrupts = <0 167 4>;
-                        clock-frequency = <200000000>;
                        reg = <0xffc08000 0x1000>;
                };
-                timer1: timer@ffc09000 {
+                timer1: timer1@ffc09000 {
                        compatible = "snps,dw-apb-timer-sp";
                        interrupts = <0 168 4>;
-                        clock-frequency = <200000000>;
                        reg = <0xffc09000 0x1000>;
                };
-                timer2: timer@ffd00000 {
+                timer2: timer2@ffd00000 {
                        compatible = "snps,dw-apb-timer-osc";
                        interrupts = <0 169 4>;
-                        clock-frequency = <200000000>;
                        reg = <0xffd00000 0x1000>;
                };
-                timer3: timer@ffd01000 {
+                timer3: timer3@ffd01000 {
                        compatible = "snps,dw-apb-timer-osc";
                        interrupts = <0 170 4>;
-                        clock-frequency = <200000000>;
                        reg = <0xffd01000 0x1000>;
                };
-                uart0: uart@ffc02000 {
+                uart0: serial0@ffc02000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0xffc02000 0x1000>;
-                        clock-frequency = <7372800>;
                        interrupts = <0 162 4>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
                };
-                uart1: uart@ffc03000 {
+                uart1: serial1@ffc03000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0xffc03000 0x1000>;
-                        clock-frequency = <7372800>;
                        interrupts = <0 163 4>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index ab7e4a94299f..3ae8a83a0875 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -20,7 +20,7 @@
 / {
        model = "Altera SOCFPGA Cyclone V";
-        compatible = "altr,socfpga-cyclone5";
+        compatible = "altr,socfpga-cyclone5", "altr,socfpga";
        chosen {
                bootargs = "console=ttyS0,57600";
@@ -29,6 +29,36 @@
        memory {
                name = "memory";
                device_type = "memory";
-                reg = <0x0 0x10000000>; /* 256MB */
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+        soc {
+                timer0@ffc08000 {
+                        clock-frequency = <100000000>;
+                };
+                timer1@ffc09000 {
+                        clock-frequency = <100000000>;
+                };
+                timer2@ffd00000 {
+                        clock-frequency = <25000000>;
+                };
+                timer3@ffd01000 {
+                        clock-frequency = <25000000>;
+                };
+                serial0@ffc02000 {
+                        clock-frequency = <100000000>;
+                };
+                serial1@ffc03000 {
+                        clock-frequency = <100000000>;
+                };
+                sysmgr@ffd08000 {
+                        cpu1-start-addr = <0xffd080c4>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
new file mode 100644
index 000000000000..1036eba40bbf
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -0,0 +1,64 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+/include/ "socfpga.dtsi"
+/ {
+        model = "Altera SOCFPGA VT";
+        compatible = "altr,socfpga-vt", "altr,socfpga";
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1 GB */
+        };
+        soc {
+                timer0@ffc08000 {
+                        clock-frequency = <7000000>;
+                };
+                timer1@ffc09000 {
+                        clock-frequency = <7000000>;
+                };
+                timer2@ffd00000 {
+                        clock-frequency = <7000000>;
+                };
+                timer3@ffd01000 {
+                        clock-frequency = <7000000>;
+                };
+                serial0@ffc02000 {
+                        clock-frequency = <7372800>;
+                };
+                serial1@ffc03000 {
+                        clock-frequency = <7372800>;
+                };
+                sysmgr@ffd08000 {
+                        cpu1-start-addr = <0xffd08010>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
new file mode 100644
index 000000000000..b28fbf3408e3
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -0,0 +1,30 @@
+/*
+ * Device Tree for the ST-Ericsson Nomadik S8815 board
+ * Produced by Calao Systems
+ */
+/dts-v1/;
+/include/ "ste-nomadik-stn8815.dtsi"
+/ {
+        model = "Calao Systems USB-S8815";
+        compatible = "calaosystems,usb-s8815";
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
+        };
+        /* Custom board node with GPIO pins to active etc */
+        usb-s8815 {
+                /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
+                ethernet-gpio {
+                        gpios = <&gpio3 19 0x1>;
+                        interrupts = <19 0x1>;
+                        interrupt-parent = <&gpio3>;
+                };
+                /* This will bias the MMC/SD card detect line */
+                mmcsd-gpio {
+                        gpios = <&gpio3 16 0x1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
new file mode 100644
index 000000000000..4a4aab395141
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -0,0 +1,256 @@
+/*
+ * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
+ */
+/include/ "skeleton.dtsi"
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0x00000000 0x04000000>,
+                    <0x08000000 0x04000000>;
+        };
+        L2: l2-cache {
+                compatible = "arm,l210-cache";
+                reg = <0x10210000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <30>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        mtu0 {
+                /* Nomadik system timer */
+                reg = <0x101e2000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <4>;
+        };
+        mtu1 {
+                /* Secondary timer */
+                reg = <0x101e3000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <5>;
+        };
+        gpio0: gpio@101e4000 {
+                compatible = "st,nomadik-gpio";
+                reg =  <0x101e4000 0x80>;
+                interrupt-parent = <&vica>;
+                interrupts = <6>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-bank = <0>;
+        };
+        gpio1: gpio@101e5000 {
+                compatible = "st,nomadik-gpio";
+                reg =  <0x101e5000 0x80>;
+                interrupt-parent = <&vica>;
+                interrupts = <7>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-bank = <1>;
+        };
+        gpio2: gpio@101e6000 {
+                compatible = "st,nomadik-gpio";
+                reg =  <0x101e6000 0x80>;
+                interrupt-parent = <&vica>;
+                interrupts = <8>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-bank = <2>;
+        };
+        gpio3: gpio@101e7000 {
+                compatible = "st,nomadik-gpio";
+                reg =  <0x101e7000 0x80>;
+                interrupt-parent = <&vica>;
+                interrupts = <9>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-bank = <3>;
+        };
+        pinctrl {
+                compatible = "stericsson,nmk-pinctrl-stn8815";
+        };
+        /* A NAND flash of 128 MiB */
+        fsmc: flash@40000000 {
+                compatible = "stericsson,fsmc-nand";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x10100000 0x1000>,      /* FSMC Register*/
+                        <0x40000000 0x2000>,    /* NAND Base DATA */
+                        <0x41000000 0x2000>,    /* NAND Base ADDR */
+                        <0x40800000 0x2000>;    /* NAND Base CMD */
+                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                status = "okay";
+                partition@0 {
+                label = "X-Loader(NAND)";
+                        reg = <0x0 0x40000>;
+                };
+                partition@40000 {
+                        label = "MemInit(NAND)";
+                        reg = <0x40000 0x40000>;
+                };
+                partition@80000 {
+                        label = "BootLoader(NAND)";
+                        reg = <0x80000 0x200000>;
+                };
+                partition@280000 {
+                        label = "Kernel zImage(NAND)";
+                        reg = <0x280000 0x300000>;
+                };
+                partition@580000 {
+                        label = "Root Filesystem(NAND)";
+                        reg = <0x580000 0x1600000>;
+                };
+                partition@1b80000 {
+                        label = "User Filesystem(NAND)";
+                        reg = <0x1b80000 0x6480000>;
+                };
+        };
+        external-bus@34000000 {
+                compatible = "simple-bus";
+                reg = <0x34000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x34000000 0x1000000>;
+                ethernet@300 {
+                        compatible = "smsc,lan91c111";
+                        reg = <0x300 0x0fd00>;
+                };
+        };
+        /* I2C0 connected to the STw4811 power management chip */
+        i2c0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpio1 31 0>, /* sda */
+                        <&gpio1 30 0>; /* scl */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                stw4811@2d {
+                           compatible = "st,stw4811";
+                           reg = <0x2d>;
+                };
+        };
+        /* I2C1 connected to various sensors */
+        i2c1 {
+                compatible = "i2c-gpio";
+                gpios = <&gpio1 22 0>, /* sda */
+                        <&gpio1 21 0>; /* scl */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                camera@2d {
+                           compatible = "st,camera";
+                           reg = <0x10>;
+                };
+                stw5095@1a {
+                           compatible = "st,stw5095";
+                           reg = <0x1a>;
+                };
+                lis3lv02dl@1d {
+                           compatible = "st,lis3lv02dl";
+                           reg = <0x1d>;
+                };
+        };
+        /* I2C2 connected to the USB portions of the STw4811 only */
+        i2c2 {
+                compatible = "i2c-gpio";
+                gpios = <&gpio2 10 0>, /* sda */
+                        <&gpio2 9 0>; /* scl */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                stw4811@2d {
+                           compatible = "st,stw4811-usb";
+                           reg = <0x2d>;
+                };
+        };
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                vica: intc@0x10140000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x10140000 0x20>;
+                };
+                vicb: intc@0x10140020 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x10140020 0x20>;
+                };
+                uart0: uart@101fd000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101fd000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <12>;
+                };
+                uart1: uart@101fb000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101fb000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <17>;
+                };
+                uart2: uart@101f2000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x101f2000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <28>;
+                        status = "disabled";
+                };
+                rng: rng@101b0000 {
+                        compatible = "arm,primecell";
+                        reg = <0x101b0000 0x1000>;
+                };
+                rtc: rtc@101e8000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0x101e8000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <10>;
+                };
+                mmcsd: sdi@101f6000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x101f6000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <22>;
+                        max-frequency = <48000000>;
+                        bus-width = <4>;
+                        mmc-cap-mmc-highspeed;
+                        mmc-cap-sd-highspeed;
+                        cd-gpios = <&gpio3 15 0x1>;
+                        cd-inverted;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
new file mode 100644
index 000000000000..f84549ad791e
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+/ {
+        model = "Miniand Hackberry";
+        compatible = "miniand,hackberry", "allwinner,sun4i-a10";
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc {
+                uart0: uart@01c28000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e61fdd47bd01..f99f60dadf5d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,4 +16,34 @@
        memory {
                reg = <0x40000000 0x80000000>;
        };
+        soc {
+                pinctrl@01c20800 {
+                        compatible = "allwinner,sun4i-a10-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart0_pins_b: uart0@1 {
+                                allwinner,pins = "PF2", "PF4";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PA10", "PA11";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 498a091a4ea2..4a1e45d4aace 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -24,6 +24,8 @@
        soc {
                uart1: uart@01c28400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_pins_b>;
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 59a2d265a98e..e1121890fb29 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,4 +17,27 @@
        memory {
                reg = <0x40000000 0x20000000>;
        };
+        soc {
+                pinctrl@01c20800 {
+                        compatible = "allwinner,sun5i-a13-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PE10", "PE11";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart1_pins_b: uart1@1 {
+                                allwinner,pins = "PG3", "PG4";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
new file mode 100644
index 000000000000..a30aca62658a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/include/ "tegra114.dtsi"
+/ {
+        model = "NVIDIA Tegra114 Dalmore evaluation board";
+        compatible = "nvidia,dalmore", "nvidia,tegra114";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        serial@70006300 {
+                status = "okay";
+                clock-frequency = <408000000>;
+        };
+        pmc {
+                nvidia,invert-interrupt;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
new file mode 100644
index 000000000000..9bea8f57aa47
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/include/ "tegra114.dtsi"
+/ {
+        model = "NVIDIA Tegra114 Pluto evaluation board";
+        compatible = "nvidia,pluto", "nvidia,tegra114";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        serial@70006300 {
+                status = "okay";
+                clock-frequency = <408000000>;
+        };
+        pmc {
+                nvidia,invert-interrupt;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
new file mode 100644
index 000000000000..1dfaf2874c57
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -0,0 +1,153 @@
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "nvidia,tegra114";
+        interrupt-parent = <&gic>;
+        gic: interrupt-controller {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x50041000 0x1000>,
+                      <0x50042000 0x1000>,
+                      <0x50044000 0x2000>,
+                      <0x50046000 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+        timer@60005000 {
+                compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+                reg = <0x60005000 0x400>;
+                interrupts = <0 0 0x04
+                              0 1 0x04
+                              0 41 0x04
+                              0 42 0x04
+                              0 121 0x04
+                              0 122 0x04>;
+        };
+        tegra_car: clock {
+                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
+        ahb: ahb {
+                compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
+                reg = <0x6000c004 0x14c>;
+        };
+        gpio: gpio {
+                compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+                reg = <0x6000d000 0x1000>;
+                interrupts = <0 32 0x04
+                              0 33 0x04
+                              0 34 0x04
+                              0 35 0x04
+                              0 55 0x04
+                              0 87 0x04
+                              0 89 0x04
+                              0 125 0x04>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+        pinmux: pinmux {
+                compatible = "nvidia,tegra114-pinmux";
+                reg = <0x70000868 0x148         /* Pad control registers */
+                       0x70003000 0x40c>;       /* Mux registers */
+        };
+        serial@70006000 {
+                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+                reg = <0x70006000 0x40>;
+                reg-shift = <2>;
+                interrupts = <0 36 0x04>;
+                status = "disabled";
+        };
+        serial@70006040 {
+                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+                reg = <0x70006040 0x40>;
+                reg-shift = <2>;
+                interrupts = <0 37 0x04>;
+                status = "disabled";
+        };
+        serial@70006200 {
+                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+                reg = <0x70006200 0x100>;
+                reg-shift = <2>;
+                interrupts = <0 46 0x04>;
+                status = "disabled";
+        };
+        serial@70006300 {
+                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+                reg = <0x70006300 0x100>;
+                reg-shift = <2>;
+                interrupts = <0 90 0x04>;
+                status = "disabled";
+        };
+        rtc {
+                compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+                reg = <0x7000e000 0x100>;
+                interrupts = <0 2 0x04>;
+        };
+        pmc {
+                compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+        iommu {
+                compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
+                reg = <0x7000f010 0x02c
+                       0x7000f1f0 0x010
+                       0x7000f228 0x074>;
+                nvidia,#asids = <4>;
+                dma-window = <0 0x40000000>;
+                nvidia,swgroups = <0x18659fe>;
+                nvidia,ahb = <&ahb>;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <3>;
+                };
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
new file mode 100644
index 000000000000..444162090042
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -0,0 +1,491 @@
+/include/ "tegra20.dtsi"
+/ {
+        model = "Toradex Colibri T20 512MB";
+        compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        host1x {
+                hdmi {
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&i2c_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        audio_refclk {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        crt {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        displaya {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+                                        "ld4", "ld5", "ld6", "ld7", "ld8",
+                                        "ld9", "ld10", "ld11", "ld12", "ld13",
+                                        "ld14", "ld15", "ld16", "ld17",
+                                        "lhs", "lpw0", "lpw2", "lsc0",
+                                        "lsc1", "lsck", "lsda", "lspi", "lvs";
+                                nvidia,function = "displaya";
+                                nvidia,tristate = <1>;
+                        };
+                        gpio_dte {
+                                nvidia,pins = "dte";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        gpio_gmi {
+                                nvidia,pins = "ata", "atc", "atd", "ate",
+                                        "dap1", "dap2", "dap4", "gpu", "irrx",
+                                        "irtx", "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        gpio_pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        gpio_uac {
+                                nvidia,pins = "uac";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        hdint {
+                                nvidia,pins = "hdint";
+                                nvidia,function = "hdmi";
+                                nvidia,tristate = <1>;
+                        };
+                        i2c1 {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        i2c3 {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        i2cddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        irda {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        nand {
+                                nvidia,pins = "kbca", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "nand";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        owc {
+                                nvidia,pins = "owc";
+                                nvidia,function = "owr";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                                nvidia,tristate = <0>;
+                        };
+                        pwm {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                                nvidia,tristate = <1>;
+                        };
+                        sdio4 {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        spi1 {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        spi4 {
+                                nvidia,pins = "slxa", "slxc", "slxd", "slxk";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        uarta {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        uartd {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        ulpi {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        ulpi_refclk {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        usb_gpio {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        vi {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,function = "vi";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        vi_sc {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                };
+        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+        i2c_ddc: i2c@7000c400 {
+                clock-frequency = <100000>;
+        };
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1275000>;
+                                        regulator-max-microvolt = <1275000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO0 is not connected to anything */
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                /* LDO3 is not connected to anything */
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo5_reg: regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                hdmi_vdd_reg: regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                hdmi_pll_reg: regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+                temperature-sensor@4c {
+                        compatible = "national,lm95245";
+                        reg = <0x4c>;
+                };
+        };
+        memory-controller@7000f400 {
+                emc-table@83250 {
+                        reg = <83250>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = <83250>;
+                        nvidia,emc-registers =   <0x00000005 0x00000011
+                                0x00000004 0x00000002 0x00000004 0x00000004
+                                0x00000001 0x0000000a 0x00000002 0x00000002
+                                0x00000001 0x00000001 0x00000003 0x00000004
+                                0x00000003 0x00000009 0x0000000c 0x0000025f
+                                0x00000000 0x00000003 0x00000003 0x00000002
+                                0x00000002 0x00000001 0x00000008 0x000000c8
+                                0x00000003 0x00000005 0x00000003 0x0000000c
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0x00520006
+                                0x00000010 0x00000008 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000>;
+                };
+                emc-table@133200 {
+                        reg = <133200>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = <133200>;
+                        nvidia,emc-registers =   <0x00000008 0x00000019
+                                0x00000006 0x00000002 0x00000004 0x00000004
+                                0x00000001 0x0000000a 0x00000002 0x00000002
+                                0x00000002 0x00000001 0x00000003 0x00000004
+                                0x00000003 0x00000009 0x0000000c 0x0000039f
+                                0x00000000 0x00000003 0x00000003 0x00000002
+                                0x00000002 0x00000001 0x00000008 0x000000c8
+                                0x00000003 0x00000007 0x00000003 0x0000000c
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0x00510006
+                                0x00000010 0x00000008 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000>;
+                };
+                emc-table@166500 {
+                        reg = <166500>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = <166500>;
+                        nvidia,emc-registers =   <0x0000000a 0x00000021
+                                0x00000008 0x00000003 0x00000004 0x00000004
+                                0x00000002 0x0000000a 0x00000003 0x00000003
+                                0x00000002 0x00000001 0x00000003 0x00000004
+                                0x00000003 0x00000009 0x0000000c 0x000004df
+                                0x00000000 0x00000003 0x00000003 0x00000003
+                                0x00000003 0x00000001 0x00000009 0x000000c8
+                                0x00000003 0x00000009 0x00000004 0x0000000c
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0x004f0006
+                                0x00000010 0x00000008 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000>;
+                };
+                emc-table@333000 {
+                        reg = <333000>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = <333000>;
+                        nvidia,emc-registers =   <0x00000014 0x00000041
+                                0x0000000f 0x00000005 0x00000004 0x00000005
+                                0x00000003 0x0000000a 0x00000005 0x00000005
+                                0x00000004 0x00000001 0x00000003 0x00000004
+                                0x00000003 0x00000009 0x0000000c 0x000009ff
+                                0x00000000 0x00000003 0x00000003 0x00000005
+                                0x00000005 0x00000001 0x0000000e 0x000000c8
+                                0x00000003 0x00000011 0x00000006 0x0000000c
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0x00380006
+                                0x00000010 0x00000008 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000>;
+                };
+        };
+        ac97: ac97 {
+                status = "okay";
+                nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+        };
+        usb@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+        };
+        sound {
+                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+                                 "nvidia,tegra-audio-wm9712";
+                nvidia,model = "Colibri T20 AC97 Audio";
+                nvidia,audio-routing =
+                        "Headphone", "HPOUTL",
+                        "Headphone", "HPOUTR",
+                        "LineIn", "LINEINL",
+                        "LineIn", "LINEINR",
+                        "Mic", "MIC1";
+                nvidia,ac97-controller = <&ac97>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v0_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        reg = <100>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "internal_usb";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        gpio = <&gpio 217 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 43eb72af8948..61d027f03617 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -3,7 +3,7 @@
 /include/ "tegra20.dtsi"
 / {
-        model = "NVIDIA Tegra2 Harmony evaluation board";
+        model = "NVIDIA Tegra20 Harmony evaluation board";
        compatible = "nvidia,harmony", "nvidia,tegra20";
        memory {
@@ -252,7 +252,6 @@
        serial@70006300 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        i2c@7000c000 {
@@ -432,6 +431,10 @@
                status = "okay";
        };
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
        sdhci@c8000200 {
                status = "okay";
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
@@ -448,6 +451,123 @@
                bus-width = <8>;
        };
+        kbc {
+                status = "okay";
+                nvidia,debounce-delay-ms = <2>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <0x00020011      /* KEY_W */
+                                0x0003001F      /* KEY_S */
+                                0x0004001E      /* KEY_A */
+                                0x0005002C      /* KEY_Z */
+                                0x000701D0      /* KEY_FN */
+                                0x0107008B      /* KEY_MENU */
+                                0x02060038      /* KEY_LEFTALT */
+                                0x02070064      /* KEY_RIGHTALT */
+                                0x03000006      /* KEY_5 */
+                                0x03010005      /* KEY_4 */
+                                0x03020013      /* KEY_R */
+                                0x03030012      /* KEY_E */
+                                0x03040021      /* KEY_F */
+                                0x03050020      /* KEY_D */
+                                0x0306002D      /* KEY_X */
+                                0x04000008      /* KEY_7 */
+                                0x04010007      /* KEY_6 */
+                                0x04020014      /* KEY_T */
+                                0x04030023      /* KEY_H */
+                                0x04040022      /* KEY_G */
+                                0x0405002F      /* KEY_V */
+                                0x0406002E      /* KEY_C */
+                                0x04070039      /* KEY_SPACE */
+                                0x0500000A      /* KEY_9 */
+                                0x05010009      /* KEY_8 */
+                                0x05020016      /* KEY_U */
+                                0x05030015      /* KEY_Y */
+                                0x05040024      /* KEY_J */
+                                0x05050031      /* KEY_N */
+                                0x05060030      /* KEY_B */
+                                0x0507002B      /* KEY_BACKSLASH */
+                                0x0600000C      /* KEY_MINUS */
+                                0x0601000B      /* KEY_0 */
+                                0x06020018      /* KEY_O */
+                                0x06030017      /* KEY_I */
+                                0x06040026      /* KEY_L */
+                                0x06050025      /* KEY_K */
+                                0x06060033      /* KEY_COMMA */
+                                0x06070032      /* KEY_M */
+                                0x0701000D      /* KEY_EQUAL */
+                                0x0702001B      /* KEY_RIGHTBRACE */
+                                0x0703001C      /* KEY_ENTER */
+                                0x0707008B      /* KEY_MENU */
+                                0x0804002A      /* KEY_LEFTSHIFT */
+                                0x08050036      /* KEY_RIGHTSHIFT */
+                                0x0905001D      /* KEY_LEFTCTRL */
+                                0x09070061      /* KEY_RIGHTCTRL */
+                                0x0B00001A      /* KEY_LEFTBRACE */
+                                0x0B010019      /* KEY_P */
+                                0x0B020028      /* KEY_APOSTROPHE */
+                                0x0B030027      /* KEY_SEMICOLON */
+                                0x0B040035      /* KEY_SLASH */
+                                0x0B050034      /* KEY_DOT */
+                                0x0C000044      /* KEY_F10 */
+                                0x0C010043      /* KEY_F9 */
+                                0x0C02000E      /* KEY_BACKSPACE */
+                                0x0C030004      /* KEY_3 */
+                                0x0C040003      /* KEY_2 */
+                                0x0C050067      /* KEY_UP */
+                                0x0C0600D2      /* KEY_PRINT */
+                                0x0C070077      /* KEY_PAUSE */
+                                0x0D00006E      /* KEY_INSERT */
+                                0x0D01006F      /* KEY_DELETE */
+                                0x0D030068      /* KEY_PAGEUP */
+                                0x0D04006D      /* KEY_PAGEDOWN */
+                                0x0D05006A      /* KEY_RIGHT */
+                                0x0D06006C      /* KEY_DOWN */
+                                0x0D070069      /* KEY_LEFT */
+                                0x0E000057      /* KEY_F11 */
+                                0x0E010058      /* KEY_F12 */
+                                0x0E020042      /* KEY_F8 */
+                                0x0E030010      /* KEY_Q */
+                                0x0E04003E      /* KEY_F4 */
+                                0x0E05003D      /* KEY_F3 */
+                                0x0E060002      /* KEY_1 */
+                                0x0E070041      /* KEY_F7 */
+                                0x0F000001      /* KEY_ESC */
+                                0x0F010029      /* KEY_GRAVE */
+                                0x0F02003F      /* KEY_F5 */
+                                0x0F03000F      /* KEY_TAB */
+                                0x0F04003B      /* KEY_F1 */
+                                0x0F05003C      /* KEY_F2 */
+                                0x0F06003A      /* KEY_CAPSLOCK */
+                                0x0F070040      /* KEY_F6 */
+                                0x14000047      /* KEY_KP7 */
+                                0x15000049      /* KEY_KP9 */
+                                0x15010048      /* KEY_KP8 */
+                                0x1502004B      /* KEY_KP4 */
+                                0x1504004F      /* KEY_KP1 */
+                                0x1601004E      /* KEY_KPSLASH */
+                                0x1602004D      /* KEY_KP6 */
+                                0x1603004C      /* KEY_KP5 */
+                                0x16040051      /* KEY_KP3 */
+                                0x16050050      /* KEY_KP2 */
+                                0x16070052      /* KEY_KP0 */
+                                0x1B010037      /* KEY_KPASTERISK */
+                                0x1B03004A      /* KEY_KPMINUS */
+                                0x1B04004E      /* KEY_KPPLUS */
+                                0x1B050053      /* KEY_KPDOT */
+                                0x1C050073      /* KEY_VOLUMEUP */
+                                0x1D030066      /* KEY_HOME */
+                                0x1D04006B      /* KEY_END */
+                                0x1D0500E1      /* KEY_BRIGHTNESSUP */
+                                0x1D060072      /* KEY_VOLUMEDOWN */
+                                0x1D0700E0      /* KEY_BRIGHTNESSDOWN */
+                                0x1E000045      /* KEY_NUMLOCK */
+                                0x1E010046      /* KEY_SCROLLLOCK */
+                                0x1E020071      /* KEY_MUTE */
+                                0x1F0400D6>;    /* KEY_QUESTION */
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
new file mode 100644
index 000000000000..52f1103907d7
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+/include/ "tegra20-colibri-512.dtsi"
+/ {
+        model = "Toradex Colibri T20 512MB on Iris";
+        compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+        host1x {
+                hdmi {
+                        status = "okay";
+                };
+        };
+        pinmux {
+                state_default: pinmux {
+                        hdint {
+                                nvidia,tristate = <0>;
+                        };
+                        i2cddc {
+                                nvidia,tristate = <0>;
+                        };
+                        sdio4 {
+                                nvidia,tristate = <0>;
+                        };
+                        uarta {
+                                nvidia,tristate = <0>;
+                        };
+                        uartd {
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+        usb@c5000000 {
+                status = "okay";
+                dr_mode = "otg";
+        };
+        usb@c5008000 {
+                status = "okay";
+        };
+        serial@70006000 {
+                status = "okay";
+        };
+        serial@70006300 {
+                status = "okay";
+        };
+        i2c_ddc: i2c@7000c400 {
+                status = "okay";
+        };
+        sdhci@c8000600 {
+                status = "okay";
+                bus-width = <4>;
+                vmmc-supply = <&vcc_sd_reg>;
+                vqmmc-supply = <&vcc_sd_reg>;
+        };
+        regulators {
+                regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_host_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        gpio = <&gpio 178 0>;
+                };
+                vcc_sd_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vcc_sd";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 6a93d1404c76..54d6fce00a59 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -10,6 +10,18 @@
                reg = <0x00000000 0x20000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -232,12 +244,10 @@
        serial@70006000 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        serial@70006200 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        i2c@7000c000 {
@@ -252,9 +262,9 @@
                };
        };
-        i2c@7000c400 {
+        hdmi_ddc: i2c@7000c400 {
                status = "okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
        };
        nvec {
@@ -266,6 +276,8 @@
                clock-frequency = <80000>;
                request-gpios = <&gpio 170 0>; /* gpio PV2 */
                slave-addr = <138>;
+                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clock-names = "div-clk", "fast-clk";
        };
        i2c@7000d000 {
@@ -367,13 +379,13 @@
                                        regulator-max-microvolt = <1800000>;
                                };
-                                ldo7 {
+                                hdmi_vdd_reg: ldo7 {
                                        regulator-name = "+3.3vs_ldo7,avdd_hdmi";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                ldo8 {
+                                hdmi_pll_reg: ldo8 {
                                        regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
@@ -418,6 +430,10 @@
                status = "okay";
        };
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        };
        sdhci@c8000000 {
                status = "okay";
                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 420459825b46..37b3a57ec0f1 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -10,6 +10,18 @@
                reg = <0x00000000 0x40000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -291,7 +303,6 @@
        serial@70006300 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        i2c@7000c000 {
@@ -345,7 +356,7 @@
                pinctrl-1 = <&state_i2cmux_pta>;
                pinctrl-2 = <&state_i2cmux_idle>;
-                i2c@0 {
+                hdmi_ddc: i2c@0 {
                        reg = <0>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -463,13 +474,13 @@
                                        regulator-max-microvolt = <1800000>;
                                };
-                                ldo7 {
+                                hdmi_vdd_reg: ldo7 {
                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                ldo8 {
+                                hdmi_pll_reg: ldo8 {
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
@@ -561,6 +572,10 @@
                status = "okay";
        };
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
        sdhci@c8000000 {
                status = "okay";
                power-gpios = <&gpio 86 0>; /* gpio PK6 */
@@ -600,6 +615,145 @@
                };
        };
+        kbc {
+                status = "okay";
+                nvidia,debounce-delay-ms = <32>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,ghost-filter;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <0x00020011      /* KEY_W */
+                                0x0003001F      /* KEY_S */
+                                0x0004001E      /* KEY_A */
+                                0x0005002C      /* KEY_Z */
+                                0x000701d0      /* KEY_FN */
+                                0x0107007D      /* KEY_LEFTMETA */
+                                0x02060064      /* KEY_RIGHTALT */
+                                0x02070038      /* KEY_LEFTALT */
+                                0x03000006      /* KEY_5 */
+                                0x03010005      /* KEY_4 */
+                                0x03020013      /* KEY_R */
+                                0x03030012      /* KEY_E */
+                                0x03040021      /* KEY_F */
+                                0x03050020      /* KEY_D */
+                                0x0306002D      /* KEY_X */
+                                0x04000008      /* KEY_7 */
+                                0x04010007      /* KEY_6 */
+                                0x04020014      /* KEY_T */
+                                0x04030023      /* KEY_H */
+                                0x04040022      /* KEY_G */
+                                0x0405002F      /* KEY_V */
+                                0x0406002E      /* KEY_C */
+                                0x04070039      /* KEY_SPACE */
+                                0x0500000A      /* KEY_9 */
+                                0x05010009      /* KEY_8 */
+                                0x05020016      /* KEY_U */
+                                0x05030015      /* KEY_Y */
+                                0x05040024      /* KEY_J */
+                                0x05050031      /* KEY_N */
+                                0x05060030      /* KEY_B */
+                                0x0507002B      /* KEY_BACKSLASH */
+                                0x0600000C      /* KEY_MINUS */
+                                0x0601000B      /* KEY_0 */
+                                0x06020018      /* KEY_O */
+                                0x06030017      /* KEY_I */
+                                0x06040026      /* KEY_L */
+                                0x06050025      /* KEY_K */
+                                0x06060033      /* KEY_COMMA */
+                                0x06070032      /* KEY_M */
+                                0x0701000D      /* KEY_EQUAL */
+                                0x0702001B      /* KEY_RIGHTBRACE */
+                                0x0703001C      /* KEY_ENTER */
+                                0x0707008B      /* KEY_MENU */
+                                0x08040036      /* KEY_RIGHTSHIFT */
+                                0x0805002A      /* KEY_LEFTSHIFT */
+                                0x09050061      /* KEY_RIGHTCTRL */
+                                0x0907001D      /* KEY_LEFTCTRL */
+                                0x0B00001A      /* KEY_LEFTBRACE */
+                                0x0B010019      /* KEY_P */
+                                0x0B020028      /* KEY_APOSTROPHE */
+                                0x0B030027      /* KEY_SEMICOLON */
+                                0x0B040035      /* KEY_SLASH */
+                                0x0B050034      /* KEY_DOT */
+                                0x0C000044      /* KEY_F10 */
+                                0x0C010043      /* KEY_F9 */
+                                0x0C02000E      /* KEY_BACKSPACE */
+                                0x0C030004      /* KEY_3 */
+                                0x0C040003      /* KEY_2 */
+                                0x0C050067      /* KEY_UP */
+                                0x0C0600D2      /* KEY_PRINT */
+                                0x0C070077      /* KEY_PAUSE */
+                                0x0D00006E      /* KEY_INSERT */
+                                0x0D01006F      /* KEY_DELETE */
+                                0x0D030068      /* KEY_PAGEUP  */
+                                0x0D04006D      /* KEY_PAGEDOWN */
+                                0x0D05006A      /* KEY_RIGHT */
+                                0x0D06006C      /* KEY_DOWN */
+                                0x0D070069      /* KEY_LEFT */
+                                0x0E000057      /* KEY_F11 */
+                                0x0E010058      /* KEY_F12 */
+                                0x0E020042      /* KEY_F8 */
+                                0x0E030010      /* KEY_Q */
+                                0x0E04003E      /* KEY_F4 */
+                                0x0E05003D      /* KEY_F3 */
+                                0x0E060002      /* KEY_1 */
+                                0x0E070041      /* KEY_F7 */
+                                0x0F000001      /* KEY_ESC */
+                                0x0F010029      /* KEY_GRAVE */
+                                0x0F02003F      /* KEY_F5 */
+                                0x0F03000F      /* KEY_TAB */
+                                0x0F04003B      /* KEY_F1 */
+                                0x0F05003C      /* KEY_F2 */
+                                0x0F06003A      /* KEY_CAPSLOCK */
+                                0x0F070040      /* KEY_F6 */
+                                /* Software Handled Function Keys */
+                                0x14000047      /* KEY_KP7 */
+                                0x15000049      /* KEY_KP9 */
+                                0x15010048      /* KEY_KP8 */
+                                0x1502004B      /* KEY_KP4 */
+                                0x1504004F      /* KEY_KP1 */
+                                0x1601004E      /* KEY_KPSLASH */
+                                0x1602004D      /* KEY_KP6 */
+                                0x1603004C      /* KEY_KP5 */
+                                0x16040051      /* KEY_KP3 */
+                                0x16050050      /* KEY_KP2 */
+                                0x16070052      /* KEY_KP0 */
+                                0x1B010037      /* KEY_KPASTERISK */
+                                0x1B03004A      /* KEY_KPMINUS */
+                                0x1B04004E      /* KEY_KPPLUS */
+                                0x1B050053      /* KEY_KPDOT */
+                                0x1C050073      /* KEY_VOLUMEUP */
+                                0x1D030066      /* KEY_HOME */
+                                0x1D04006B      /* KEY_END */
+                                0x1D0500E0      /* KEY_BRIGHTNESSDOWN */
+                                0x1D060072      /* KEY_VOLUMEDOWN */
+                                0x1D0700E1      /* KEY_BRIGHTNESSUP */
+                                0x1E000045      /* KEY_NUMLOCK */
+                                0x1E010046      /* KEY_SCROLLLOCK */
+                                0x1E020071      /* KEY_MUTE */
+                                0x1F04008A>;    /* KEY_HELP */
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index a239ccdfaa52..4766abae7a72 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -276,7 +276,6 @@
        };
        serial@70006300 {
-                clock-frequency = <216000000>;
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index b70b4cb754c8..5d79e4fc49a6 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -249,6 +249,11 @@
                                        "ld23_22";
                                nvidia,pull = <1>;
                        };
+                        conf_spif {
+                                nvidia,pins = "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
                };
        };
@@ -258,7 +263,6 @@
        serial@70006000 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        dvi_ddc: i2c@7000c000 {
@@ -310,6 +314,10 @@
                status = "okay";
        };
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        };
        sdhci@c8000000 {
                status = "okay";
                bus-width = <4>;
@@ -322,6 +330,11 @@
                bus-width = <4>;
        };
+        poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio 191 1>; /* gpio PX7, active low */
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index adc47547eaae..425c89000c20 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -3,13 +3,25 @@
 /include/ "tegra20.dtsi"
 / {
-        model = "NVIDIA Tegra2 Ventana evaluation board";
+        model = "NVIDIA Tegra20 Ventana evaluation board";
        compatible = "nvidia,ventana", "nvidia,tegra20";
        memory {
                reg = <0x00000000 0x40000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -288,7 +300,6 @@
        serial@70006300 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        i2c@7000c000 {
@@ -320,7 +331,7 @@
        i2c@7000c400 {
                status = "okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
        };
        i2cmux {
@@ -335,7 +346,7 @@
                pinctrl-1 = <&state_i2cmux_pta>;
                pinctrl-2 = <&state_i2cmux_idle>;
-                i2c@0 {
+                hdmi_ddc: i2c@0 {
                        reg = <0>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -446,13 +457,13 @@
                                        regulator-max-microvolt = <1800000>;
                                };
-                                ldo7 {
+                                hdmi_vdd_reg: ldo7 {
                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                ldo8 {
+                                hdmi_pll_reg: ldo8 {
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
@@ -497,6 +508,10 @@
                status = "okay";
        };
+        usb-phy@c5004400 {
+                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        };
        sdhci@c8000000 {
                status = "okay";
                power-gpios = <&gpio 86 0>; /* gpio PK6 */
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 20d576ecd555..ea57c0f6dcce 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -3,7 +3,7 @@
 /include/ "tegra20.dtsi"
 / {
-        model = "NVIDIA Tegra2 Whistler evaluation board";
+        model = "NVIDIA Tegra20 Whistler evaluation board";
        compatible = "nvidia,whistler", "nvidia,tegra20";
        memory {
@@ -255,7 +255,6 @@
        serial@70006000 {
                status = "okay";
-                clock-frequency = <216000000>;
        };
        hdmi_ddc: i2c@7000c400 {
@@ -520,6 +519,18 @@
                bus-width = <8>;
        };
+        kbc {
+                status = "okay";
+                nvidia,debounce-delay-ms = <20>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2>;
+                nvidia,kbc-col-pins = <16 17>;
+                linux,keymap = <0x00000074      /* KEY_POWER */
+                                0x01000066      /* KEY_HOME */
+                                0x0101009E      /* KEY_BACK */
+                                0x0201008B>;    /* KEY_MENU */
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index b8effa1cbda7..9a428931d042 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,11 +4,20 @@
        compatible = "nvidia,tegra20";
        interrupt-parent = <&intc>;
+        aliases {
+                serial0 = &uarta;
+                serial1 = &uartb;
+                serial2 = &uartc;
+                serial3 = &uartd;
+                serial4 = &uarte;
+        };
        host1x {
                compatible = "nvidia,tegra20-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
+                clocks = <&tegra_car 28>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -19,41 +28,49 @@
                        compatible = "nvidia,tegra20-mpe";
                        reg = <0x54040000 0x00040000>;
                        interrupts = <0 68 0x04>;
+                        clocks = <&tegra_car 60>;
                };
                vi {
                        compatible = "nvidia,tegra20-vi";
                        reg = <0x54080000 0x00040000>;
                        interrupts = <0 69 0x04>;
+                        clocks = <&tegra_car 100>;
                };
                epp {
                        compatible = "nvidia,tegra20-epp";
                        reg = <0x540c0000 0x00040000>;
                        interrupts = <0 70 0x04>;
+                        clocks = <&tegra_car 19>;
                };
                isp {
                        compatible = "nvidia,tegra20-isp";
                        reg = <0x54100000 0x00040000>;
                        interrupts = <0 71 0x04>;
+                        clocks = <&tegra_car 23>;
                };
                gr2d {
                        compatible = "nvidia,tegra20-gr2d";
                        reg = <0x54140000 0x00040000>;
                        interrupts = <0 72 0x04>;
+                        clocks = <&tegra_car 21>;
                };
                gr3d {
                        compatible = "nvidia,tegra20-gr3d";
                        reg = <0x54180000 0x00040000>;
+                        clocks = <&tegra_car 24>;
                };
                dc@54200000 {
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <0 73 0x04>;
+                        clocks = <&tegra_car 27>, <&tegra_car 121>;
+                        clock-names = "disp1", "parent";
                        rgb {
                                status = "disabled";
@@ -64,6 +81,8 @@
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54240000 0x00040000>;
                        interrupts = <0 74 0x04>;
+                        clocks = <&tegra_car 26>, <&tegra_car 121>;
+                        clock-names = "disp2", "parent";
                        rgb {
                                status = "disabled";
@@ -74,6 +93,8 @@
                        compatible = "nvidia,tegra20-hdmi";
                        reg = <0x54280000 0x00040000>;
                        interrupts = <0 75 0x04>;
+                        clocks = <&tegra_car 51>, <&tegra_car 117>;
+                        clock-names = "hdmi", "parent";
                        status = "disabled";
                };
@@ -81,12 +102,14 @@
                        compatible = "nvidia,tegra20-tvo";
                        reg = <0x542c0000 0x00040000>;
                        interrupts = <0 76 0x04>;
+                        clocks = <&tegra_car 102>;
                        status = "disabled";
                };
                dsi {
                        compatible = "nvidia,tegra20-dsi";
                        reg = <0x54300000 0x00040000>;
+                        clocks = <&tegra_car 48>;
                        status = "disabled";
                };
        };
@@ -97,15 +120,6 @@
                interrupts = <1 13 0x304>;
        };
-        cache-controller@50043000 {
-                compatible = "arm,pl310-cache";
-                reg = <0x50043000 0x1000>;
-                arm,data-latency = <5 5 2>;
-                arm,tag-latency = <4 4 2>;
-                cache-unified;
-                cache-level = <2>;
-        };
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -114,6 +128,15 @@
                #interrupt-cells = <3>;
        };
+        cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <5 5 2>;
+                arm,tag-latency = <4 4 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
        timer@60005000 {
                compatible = "nvidia,tegra20-timer";
                reg = <0x60005000 0x60>;
@@ -123,6 +146,12 @@
                              0 42 0x04>;
        };
+        tegra_car: clock {
+                compatible = "nvidia,tegra20-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
        apbdma: dma {
                compatible = "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1200>;
@@ -142,6 +171,7 @@
                              0 117 0x04
                              0 118 0x04
                              0 119 0x04>;
+                clocks = <&tegra_car 34>;
        };
        ahb {
@@ -177,12 +207,22 @@
                compatible = "nvidia,tegra20-das";
                reg = <0x70000c00 0x80>;
        };
+        
+        tegra_ac97: ac97 {
+                compatible = "nvidia,tegra20-ac97";
+                reg = <0x70002000 0x200>;
+                interrupts = <0 81 0x04>;
+                nvidia,dma-request-selector = <&apbdma 12>;
+                clocks = <&tegra_car 3>;
+                status = "disabled";
+        };
        tegra_i2s1: i2s@70002800 {
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002800 0x200>;
                interrupts = <0 13 0x04>;
                nvidia,dma-request-selector = <&apbdma 2>;
+                clocks = <&tegra_car 11>;
                status = "disabled";
        };
@@ -191,46 +231,64 @@
                reg = <0x70002a00 0x200>;
                interrupts = <0 3 0x04>;
                nvidia,dma-request-selector = <&apbdma 1>;
+                clocks = <&tegra_car 18>;
                status = "disabled";
        };
-        serial@70006000 {
+        /*
+         * There are two serial driver i.e. 8250 based simple serial
+         * driver and APB DMA based serial driver for higher baudrate
+         * and performace. To enable the 8250 based driver, the compatible
+         * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
+         * driver, the comptible is "nvidia,tegra20-hsuart".
+         */
+        uarta: serial@70006000 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
+                nvidia,dma-request-selector = <&apbdma 8>;
+                clocks = <&tegra_car 6>;
                status = "disabled";
        };
-        serial@70006040 {
+        uartb: serial@70006040 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
+                nvidia,dma-request-selector = <&apbdma 9>;
+                clocks = <&tegra_car 96>;
                status = "disabled";
        };
-        serial@70006200 {
+        uartc: serial@70006200 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
+                nvidia,dma-request-selector = <&apbdma 10>;
+                clocks = <&tegra_car 55>;
                status = "disabled";
        };
-        serial@70006300 {
+        uartd: serial@70006300 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
+                nvidia,dma-request-selector = <&apbdma 19>;
+                clocks = <&tegra_car 65>;
                status = "disabled";
        };
-        serial@70006400 {
+        uarte: serial@70006400 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
                interrupts = <0 91 0x04>;
+                nvidia,dma-request-selector = <&apbdma 20>;
+                clocks = <&tegra_car 66>;
                status = "disabled";
        };
@@ -238,6 +296,7 @@
                compatible = "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
+                clocks = <&tegra_car 17>;
        };
        rtc {
@@ -252,6 +311,8 @@
                interrupts = <0 38 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 12>, <&tegra_car 124>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -262,6 +323,7 @@
                nvidia,dma-request-selector = <&apbdma 11>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 43>;
                status = "disabled";
        };
@@ -271,6 +333,8 @@
                interrupts = <0 84 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 54>, <&tegra_car 124>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -280,6 +344,8 @@
                interrupts = <0 92 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -289,6 +355,8 @@
                interrupts = <0 53 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 47>, <&tegra_car 124>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -299,6 +367,7 @@
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 41>;
                status = "disabled";
        };
@@ -309,6 +378,7 @@
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 44>;
                status = "disabled";
        };
@@ -319,6 +389,7 @@
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 46>;
                status = "disabled";
        };
@@ -329,6 +400,15 @@
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 68>;
+                status = "disabled";
+        };
+        kbc {
+                compatible = "nvidia,tegra20-kbc";
+                reg = <0x7000e200 0x100>;
+                interrupts = <0 85 0x04>;
+                clocks = <&tegra_car 36>;
                status = "disabled";
        };
@@ -344,7 +424,7 @@
                interrupts = <0 77 0x04>;
        };
-        gart {
+        iommu {
                compatible = "nvidia,tegra20-gart";
                reg = <0x7000f024 0x00000018    /* controller registers */
                       0x58000000 0x02000000>;  /* GART aperture */
@@ -357,12 +437,40 @@
                #size-cells = <0>;
        };
+        phy1: usb-phy@c5000400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5000400 0x3c00>;
+                phy_type = "utmi";
+                nvidia,has-legacy-mode;
+                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
+        phy2: usb-phy@c5004400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5004400 0x3c00>;
+                phy_type = "ulpi";
+                clocks = <&tegra_car 94>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
+        phy3: usb-phy@c5008400 {
+                compatible = "nvidia,tegra20-usb-phy";
+                reg = <0xc5008400 0x3C00>;
+                phy_type = "utmi";
+                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                clock-names = "phy", "pll_u";
+        };
        usb@c5000000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5000000 0x4000>;
                interrupts = <0 20 0x04>;
                phy_type = "utmi";
                nvidia,has-legacy-mode;
+                clocks = <&tegra_car 22>;
+                nvidia,needs-double-reset;
+                nvidia,phy = <&phy1>;
                status = "disabled";
        };
@@ -371,6 +479,8 @@
                reg = <0xc5004000 0x4000>;
                interrupts = <0 21 0x04>;
                phy_type = "ulpi";
+                clocks = <&tegra_car 58>;
+                nvidia,phy = <&phy2>;
                status = "disabled";
        };
@@ -379,6 +489,8 @@
                reg = <0xc5008000 0x4000>;
                interrupts = <0 97 0x04>;
                phy_type = "utmi";
+                clocks = <&tegra_car 59>;
+                nvidia,phy = <&phy3>;
                status = "disabled";
        };
@@ -386,6 +498,7 @@
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
                interrupts = <0 14 0x04>;
+                clocks = <&tegra_car 14>;
                status = "disabled";
        };
@@ -393,6 +506,7 @@
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
                interrupts = <0 15 0x04>;
+                clocks = <&tegra_car 9>;
                status = "disabled";
        };
@@ -400,6 +514,7 @@
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
                interrupts = <0 19 0x04>;
+                clocks = <&tegra_car 69>;
                status = "disabled";
        };
@@ -407,9 +522,27 @@
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
                interrupts = <0 31 0x04>;
+                clocks = <&tegra_car 15>;
                status = "disabled";
        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
        pmu {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 56 0x04
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
new file mode 100644
index 000000000000..8ff2ff20e4a3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -0,0 +1,373 @@
+/dts-v1/;
+/include/ "tegra30.dtsi"
+/ {
+        model = "NVIDIA Tegra30 Beaver evaluation board";
+        compatible = "nvidia,beaver", "nvidia,tegra30";
+        memory {
+                reg = <0x80000000 0x80000000>;
+        };
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins =   "sdmmc3_cmd_pa7",
+                                                "sdmmc3_dat0_pb7",
+                                                "sdmmc3_dat1_pb6",
+                                                "sdmmc3_dat2_pb5",
+                                                "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins =   "dap2_fs_pa2",
+                                                "dap2_sclk_pa3",
+                                                "dap2_din_pa4",
+                                                "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <0>;
+                                nvidia,pull-down-strength = <46>;
+                                nvidia,pull-up-strength = <42>;
+                                nvidia,slew-rate-rising = <1>;
+                                nvidia,slew-rate-falling = <1>;
+                        };
+                };
+        };
+        serial@70006000 {
+                status = "okay";
+        };
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                tps62361 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
+                pmic: tps65911@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+                        interrupts = <0 86 0x4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        vcc1-supply = <&vdd_5v_in_reg>;
+                        vcc2-supply = <&vdd_5v_in_reg>;
+                        vcc3-supply = <&vio_reg>;
+                        vcc4-supply = <&vdd_5v_in_reg>;
+                        vcc5-supply = <&vdd_5v_in_reg>;
+                        vcc6-supply = <&vdd2_reg>;
+                        vcc7-supply = <&vdd_5v_in_reg>;
+                        vccio-supply = <&vdd_5v_in_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                vdd1_reg: vdd1 {
+                                        regulator-name = "vddio_ddr_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                vdd2_reg: vdd2 {
+                                        regulator-name = "vdd_1v5_gen";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                };
+                                vddctrl_reg: vddctrl {
+                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                vio_reg: vio {
+                                        regulator-name = "vdd_1v8_gen";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo1_reg: ldo1 {
+                                        regulator-name = "vdd_pexa,vdd_pexb";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                ldo2_reg: ldo2 {
+                                        regulator-name = "vdd_sata,avdd_plle";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                /* LDO3 is not connected to anything */
+                                ldo4_reg: ldo4 {
+                                        regulator-name = "vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo5_reg: ldo5 {
+                                        regulator-name = "vddio_sdmmc,avdd_vdac";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                ldo6_reg: ldo6 {
+                                        regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                ldo7_reg: ldo7 {
+                                        regulator-name = "vdd_pllm,x,u,a_p_c_s";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo8_reg: ldo8 {
+                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@1 {
+                        compatible = "winbond,w25q32";
+                        reg = <1>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+        pmc {
+                status = "okay";
+                nvidia,invert-interrupt;
+        };
+        sdhci@78000000 {
+                status = "okay";
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                bus-width = <4>;
+        };
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v_in_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v_in";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                chargepump_5v_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "chargepump_5v";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        enable-active-high;
+                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                };
+                ddr_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+                        vin-supply = <&vdd_5v_in_reg>;
+                };
+                vdd_5v_sata_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_5v_sata";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        vin-supply = <&vdd_5v_in_reg>;
+                };
+                usb1_vbus_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v_in_reg>;
+                };
+                usb3_vbus_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v_in_reg>;
+                };
+                sys_3v3_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "sys_3v3,vdd_3v3_alw";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+                        vin-supply = <&vdd_5v_in_reg>;
+                };
+                sys_3v3_pexs_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "sys_3v3_pexs";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index bdb2a660f376..17499272a4ef 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -106,12 +106,25 @@
                                nvidia,slew-rate-rising = <1>;
                                nvidia,slew-rate-falling = <1>;
                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins =   "uart3_txd_pw6",
+                                                "uart3_cts_n_pa1",
+                                                "uart3_rts_n_pc0",
+                                                "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
                };
        };
        serial@70006000 {
                status = "okay";
-                clock-frequency = <408000000>;
+        };
+        serial@70006200 {
+                compatible = "nvidia,tegra30-hsuart";
+                status = "okay";
        };
        i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 529fdb82dfdb..767803e1fd55 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,11 +4,20 @@
        compatible = "nvidia,tegra30";
        interrupt-parent = <&intc>;
+        aliases {
+                serial0 = &uarta;
+                serial1 = &uartb;
+                serial2 = &uartc;
+                serial3 = &uartd;
+                serial4 = &uarte;
+        };
        host1x {
                compatible = "nvidia,tegra30-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
+                clocks = <&tegra_car 28>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -19,41 +28,50 @@
                        compatible = "nvidia,tegra30-mpe";
                        reg = <0x54040000 0x00040000>;
                        interrupts = <0 68 0x04>;
+                        clocks = <&tegra_car 60>;
                };
                vi {
                        compatible = "nvidia,tegra30-vi";
                        reg = <0x54080000 0x00040000>;
                        interrupts = <0 69 0x04>;
+                        clocks = <&tegra_car 164>;
                };
                epp {
                        compatible = "nvidia,tegra30-epp";
                        reg = <0x540c0000 0x00040000>;
                        interrupts = <0 70 0x04>;
+                        clocks = <&tegra_car 19>;
                };
                isp {
                        compatible = "nvidia,tegra30-isp";
                        reg = <0x54100000 0x00040000>;
                        interrupts = <0 71 0x04>;
+                        clocks = <&tegra_car 23>;
                };
                gr2d {
                        compatible = "nvidia,tegra30-gr2d";
                        reg = <0x54140000 0x00040000>;
                        interrupts = <0 72 0x04>;
+                        clocks = <&tegra_car 21>;
                };
                gr3d {
                        compatible = "nvidia,tegra30-gr3d";
                        reg = <0x54180000 0x00040000>;
+                        clocks = <&tegra_car 24 &tegra_car 98>;
+                        clock-names = "3d", "3d2";
                };
                dc@54200000 {
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <0 73 0x04>;
+                        clocks = <&tegra_car 27>, <&tegra_car 179>;
+                        clock-names = "disp1", "parent";
                        rgb {
                                status = "disabled";
@@ -64,6 +82,8 @@
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54240000 0x00040000>;
                        interrupts = <0 74 0x04>;
+                        clocks = <&tegra_car 26>, <&tegra_car 179>;
+                        clock-names = "disp2", "parent";
                        rgb {
                                status = "disabled";
@@ -74,6 +94,8 @@
                        compatible = "nvidia,tegra30-hdmi";
                        reg = <0x54280000 0x00040000>;
                        interrupts = <0 75 0x04>;
+                        clocks = <&tegra_car 51>, <&tegra_car 189>;
+                        clock-names = "hdmi", "parent";
                        status = "disabled";
                };
@@ -81,12 +103,14 @@
                        compatible = "nvidia,tegra30-tvo";
                        reg = <0x542c0000 0x00040000>;
                        interrupts = <0 76 0x04>;
+                        clocks = <&tegra_car 169>;
                        status = "disabled";
                };
                dsi {
                        compatible = "nvidia,tegra30-dsi";
                        reg = <0x54300000 0x00040000>;
+                        clocks = <&tegra_car 48>;
                        status = "disabled";
                };
        };
@@ -97,15 +121,6 @@
                interrupts = <1 13 0xf04>;
        };
-        cache-controller@50043000 {
-                compatible = "arm,pl310-cache";
-                reg = <0x50043000 0x1000>;
-                arm,data-latency = <6 6 2>;
-                arm,tag-latency = <5 5 2>;
-                cache-unified;
-                cache-level = <2>;
-        };
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -114,6 +129,15 @@
                #interrupt-cells = <3>;
        };
+        cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <6 6 2>;
+                arm,tag-latency = <5 5 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
        timer@60005000 {
                compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                reg = <0x60005000 0x400>;
@@ -125,6 +149,12 @@
                              0 122 0x04>;
        };
+        tegra_car: clock {
+                compatible = "nvidia,tegra30-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
        apbdma: dma {
                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1400>;
@@ -160,6 +190,7 @@
                              0 141 0x04
                              0 142 0x04
                              0 143 0x04>;
+                clocks = <&tegra_car 34>;
        };
        ahb: ahb {
@@ -168,7 +199,7 @@
        };
        gpio: gpio {
-                compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+                compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
                interrupts = <0 32 0x04
                              0 33 0x04
@@ -190,43 +221,61 @@
                       0x70003000 0x3e4>; /* Mux registers */
        };
-        serial@70006000 {
+        /*
+         * There are two serial driver i.e. 8250 based simple serial
+         * driver and APB DMA based serial driver for higher baudrate
+         * and performace. To enable the 8250 based driver, the compatible
+         * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
+         * the APB DMA based serial driver, the comptible is
+         * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+         */
+        uarta: serial@70006000 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
+                nvidia,dma-request-selector = <&apbdma 8>;
+                clocks = <&tegra_car 6>;
                status = "disabled";
        };
-        serial@70006040 {
+        uartb: serial@70006040 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
+                nvidia,dma-request-selector = <&apbdma 9>;
+                clocks = <&tegra_car 160>;
                status = "disabled";
        };
-        serial@70006200 {
+        uartc: serial@70006200 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
+                nvidia,dma-request-selector = <&apbdma 10>;
+                clocks = <&tegra_car 55>;
                status = "disabled";
        };
-        serial@70006300 {
+        uartd: serial@70006300 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
+                nvidia,dma-request-selector = <&apbdma 19>;
+                clocks = <&tegra_car 65>;
                status = "disabled";
        };
-        serial@70006400 {
+        uarte: serial@70006400 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
                interrupts = <0 91 0x04>;
+                nvidia,dma-request-selector = <&apbdma 20>;
+                clocks = <&tegra_car 66>;
                status = "disabled";
        };
@@ -234,6 +283,7 @@
                compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
+                clocks = <&tegra_car 17>;
        };
        rtc {
@@ -248,6 +298,8 @@
                interrupts = <0 38 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 12>, <&tegra_car 182>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -257,6 +309,8 @@
                interrupts = <0 84 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 54>, <&tegra_car 182>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -266,6 +320,8 @@
                interrupts = <0 92 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 67>, <&tegra_car 182>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -275,6 +331,8 @@
                interrupts = <0 120 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 103>, <&tegra_car 182>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -284,6 +342,8 @@
                interrupts = <0 53 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 47>, <&tegra_car 182>;
+                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -294,6 +354,7 @@
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 41>;
                status = "disabled";
        };
@@ -304,6 +365,7 @@
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 44>;
                status = "disabled";
        };
@@ -314,6 +376,7 @@
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 46>;
                status = "disabled";
        };
@@ -324,6 +387,7 @@
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 68>;
                status = "disabled";
        };
@@ -334,6 +398,7 @@
                nvidia,dma-request-selector = <&apbdma 27>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 104>;
                status = "disabled";
        };
@@ -344,6 +409,15 @@
                nvidia,dma-request-selector = <&apbdma 28>;
                #address-cells = <1>;
                #size-cells = <0>;
+                clocks = <&tegra_car 105>;
+                status = "disabled";
+        };
+        kbc {
+                compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
+                reg = <0x7000e200 0x100>;
+                interrupts = <0 85 0x04>;
+                clocks = <&tegra_car 36>;
                status = "disabled";
        };
@@ -361,7 +435,7 @@
                interrupts = <0 77 0x04>;
        };
-        smmu {
+        iommu {
                compatible = "nvidia,tegra30-smmu";
                reg = <0x7000f010 0x02c
                       0x7000f1f0 0x010
@@ -377,7 +451,13 @@
                       0x70080200 0x100>;
                interrupts = <0 103 0x04>;
                nvidia,dma-request-selector = <&apbdma 1>;
+                clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+                         <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
+                         <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
+                         <&tegra_car 110>, <&tegra_car 162>;
+                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif_in";
                ranges;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -386,6 +466,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080300 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car 30>;
                        status = "disabled";
                };
@@ -393,6 +474,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080400 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car 11>;
                        status = "disabled";
                };
@@ -400,6 +482,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080500 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car 18>;
                        status = "disabled";
                };
@@ -407,6 +490,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080600 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car 101>;
                        status = "disabled";
                };
@@ -414,6 +498,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080700 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car 102>;
                        status = "disabled";
                };
        };
@@ -422,6 +507,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000000 0x200>;
                interrupts = <0 14 0x04>;
+                clocks = <&tegra_car 14>;
                status = "disabled";
        };
@@ -429,6 +515,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000200 0x200>;
                interrupts = <0 15 0x04>;
+                clocks = <&tegra_car 9>;
                status = "disabled";
        };
@@ -436,6 +523,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000400 0x200>;
                interrupts = <0 19 0x04>;
+                clocks = <&tegra_car 69>;
                status = "disabled";
        };
@@ -443,9 +531,39 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000600 0x200>;
                interrupts = <0 31 0x04>;
+                clocks = <&tegra_car 15>;
                status = "disabled";
        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                };
+        };
        pmu {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 144 0x04
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index a3d37ec2655d..73187173117c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -70,7 +70,7 @@
                compatible = "arm,sp805", "arm,primecell";
                status = "disabled";
                reg = <0 0x2b060000 0 0x1000>;
-                interrupts = <98>;
+                interrupts = <0 98 4>;
                clocks = <&oscclk7>;
                clock-names = "apb_pclk";
        };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index cf8071ad22d5..dfe371ec2749 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -72,7 +72,7 @@
        wdt@2a490000 {
                compatible = "arm,sp805", "arm,primecell";
                reg = <0 0x2a490000 0 0x1000>;
-                interrupts = <98>;
+                interrupts = <0 98 4>;
                clocks = <&oscclk6a>, <&oscclk6a>;
                clock-names = "wdogclk", "apb_pclk";
        };
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index d8645e990b21..cf31ced46602 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -45,6 +45,38 @@
                                        compatible = "fixed-clock";
                                        clock-frequency = <24000000>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <3>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <4>;
+                                };
                        };
                };
@@ -83,28 +115,28 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                uart@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart2>;
                };
                uart@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart3>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 330f833ac3b0..e74a1c0fb9a2 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -59,6 +59,54 @@
                                        compatible = "fixed-clock";
                                        clock-frequency = <24000000>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <3>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <4>;
+                                };
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <22>;
+                                };
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <23>;
+                                };
                        };
                };
@@ -96,42 +144,42 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                uart@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart2>;
                };
                uart@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart3>;
                };
                uart@d8370000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8370000 0x1040>;
                        interrupts = <31>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart4>;
                };
                uart@d8380000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8380000 0x1040>;
                        interrupts = <30>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart5>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 83b9467559bb..db3c0a12e052 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -75,6 +75,22 @@
                                        reg = <0x204>;
                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <1>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <2>;
+                                };
                                arm: arm {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
@@ -128,14 +144,14 @@
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart0>;
                };
                uart@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
-                        clocks = <&ref24>;
+                        clocks = <&clkuart1>;
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
new file mode 100644
index 000000000000..fcc660c89540
--- /dev/null
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -0,0 +1,47 @@
+/*
+ * wm8850-w70v2.dts
+ *  - Device tree file for Wondermedia WM8850 Tablet
+ *  - 'W70-V2' mainboard
+ *  - HongLianYing 'HLY070ML268-21A' 7" LCD panel
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "wm8850.dtsi"
+/ {
+        model = "Wondermedia WM8850-W70v2 Tablet";
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 50000 1>;        /* duty inverted */
+                brightness-levels = <0 40 60 80 100 130 190 255>;
+                default-brightness-level = <5>;
+        };
+};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
new file mode 100644
index 000000000000..e8cbfdc87bba
--- /dev/null
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -0,0 +1,224 @@
+/*
+ * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "wm,wm8850";
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8650-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <24>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <25>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <26>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <27>;
+                                };
+                                clkpwm: pwm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <17>;
+                                };
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x330>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <0>;
+                                };
+                        };
+                };
+                fb@d8051700 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8051700 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+                pwm: pwm@d8220000 {
+                        #pwm-cells = <3>;
+                        compatible = "via,vt8500-pwm";
+                        reg = <0xd8220000 0x100>;
+                        clocks = <&clkpwm>;
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8008d00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8008d00 0x200>;
+                        interrupts = <26>;
+                };
+                uart0: uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&clkuart0>;
+                };
+                uart1: uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&clkuart1>;
+                };
+                uart2: uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&clkuart2>;
+                };
+                uart3: uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&clkuart3>;
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 401c1262d4ed..5914b5654591 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -44,14 +44,14 @@
                        compatible = "xlnx,xuartps";
                        reg = <0xE0000000 0x1000>;
                        interrupts = <0 27 4>;
-                        clock = <50000000>;
+                        clocks = <&uart_clk 0>;
                };
                uart1: uart@e0001000 {
                        compatible = "xlnx,xuartps";
                        reg = <0xE0001000 0x1000>;
                        interrupts = <0 50 4>;
-                        clock = <50000000>;
+                        clocks = <&uart_clk 1>;
                };
                slcr: slcr@f8000000 {
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 45ceeb0e93e0..9353184d730d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,26 +1,3 @@
-config ARM_GIC
-        bool
-        select IRQ_DOMAIN
-        select MULTI_IRQ_HANDLER
-config GIC_NON_BANKED
-        bool
-config ARM_VIC
-        bool
-        select IRQ_DOMAIN
-        select MULTI_IRQ_HANDLER
-config ARM_VIC_NR
-        int
-        default 4 if ARCH_S5PV210
-        default 3 if ARCH_S5PC100
-        default 2
-        depends on ARM_VIC
-        help
-          The maximum number of VICs available in the system, for
-          power management.
 config ICST
        bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58f1b82..dc8dd0de5c0f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,8 +2,6 @@
 # Makefile for the linux kernel.
 #
-obj-$(CONFIG_ARM_GIC)           += gic.o
-obj-$(CONFIG_ARM_VIC)           += vic.o
 obj-$(CONFIG_ICST)              += icst.o
 obj-$(CONFIG_SA1111)            += sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
deleted file mode 100644
index 36ae03a3f5d1..000000000000
--- a/arch/arm/common/gic.c
+++ /dev/null
@@ -1,811 +0,0 @@
-/*
- *  linux/arch/arm/common/gic.c
- *
- *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Interrupt architecture for the GIC:
- *
- * o There is one Interrupt Distributor, which receives interrupts
- *   from system devices and sends them to the Interrupt Controllers.
- *
- * o There is one CPU Interface per CPU, which sends interrupts sent
- *   by the Distributor, and interrupts generated locally, to the
- *   associated CPU. The base address of the CPU interface is usually
- *   aliased so that the same address points to different chips depending
- *   on the CPU it is accessed from.
- *
- * Note that IRQs 0-31 are special - they are local to each CPU.
- * As such, the enable set/clear, pending set/clear and active bit
- * registers are banked per-cpu for these sources.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/smp.h>
-#include <linux/cpu_pm.h>
-#include <linux/cpumask.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/slab.h>
-#include <asm/irq.h>
-#include <asm/exception.h>
-#include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
-#include <asm/hardware/gic.h>
-union gic_base {
-        void __iomem *common_base;
-        void __percpu __iomem **percpu_base;
-};
-struct gic_chip_data {
-        union gic_base dist_base;
-        union gic_base cpu_base;
-#ifdef CONFIG_CPU_PM
-        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
-        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-        u32 __percpu *saved_ppi_enable;
-        u32 __percpu *saved_ppi_conf;
-#endif
-        struct irq_domain *domain;
-        unsigned int gic_irqs;
-#ifdef CONFIG_GIC_NON_BANKED
-        void __iomem *(*get_base)(union gic_base *);
-#endif
-};
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
-/*
- * The GIC mapping of CPU interfaces does not necessarily match
- * the logical CPU numbering.  Let's use a mapping as returned
- * by the GIC itself.
- */
-#define NR_GIC_CPU_IF 8
-static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
-        .irq_eoi        = NULL,
-        .irq_mask       = NULL,
-        .irq_unmask     = NULL,
-        .irq_retrigger  = NULL,
-        .irq_set_type   = NULL,
-        .irq_set_wake   = NULL,
-};
-#ifndef MAX_GIC_NR
-#define MAX_GIC_NR      1
-#endif
-static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
-#ifdef CONFIG_GIC_NON_BANKED
-static void __iomem *gic_get_percpu_base(union gic_base *base)
-{
-        return *__this_cpu_ptr(base->percpu_base);
-}
-static void __iomem *gic_get_common_base(union gic_base *base)
-{
-        return base->common_base;
-}
-static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
-{
-        return data->get_base(&data->dist_base);
-}
-static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
-{
-        return data->get_base(&data->cpu_base);
-}
-static inline void gic_set_base_accessor(struct gic_chip_data *data,
-                                         void __iomem *(*f)(union gic_base *))
-{
-        data->get_base = f;
-}
-#else
-#define gic_data_dist_base(d)   ((d)->dist_base.common_base)
-#define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
-#define gic_set_base_accessor(d,f)
-#endif
-static inline void __iomem *gic_dist_base(struct irq_data *d)
-{
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data_dist_base(gic_data);
-}
-static inline void __iomem *gic_cpu_base(struct irq_data *d)
-{
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data_cpu_base(gic_data);
-}
-static inline unsigned int gic_irq(struct irq_data *d)
-{
-        return d->hwirq;
-}
-/*
- * Routines to acknowledge, disable and enable interrupts
- */
-static void gic_mask_irq(struct irq_data *d)
-{
-        u32 mask = 1 << (gic_irq(d) % 32);
-        raw_spin_lock(&irq_controller_lock);
-        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
-        if (gic_arch_extn.irq_mask)
-                gic_arch_extn.irq_mask(d);
-        raw_spin_unlock(&irq_controller_lock);
-}
-static void gic_unmask_irq(struct irq_data *d)
-{
-        u32 mask = 1 << (gic_irq(d) % 32);
-        raw_spin_lock(&irq_controller_lock);
-        if (gic_arch_extn.irq_unmask)
-                gic_arch_extn.irq_unmask(d);
-        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
-        raw_spin_unlock(&irq_controller_lock);
-}
-static void gic_eoi_irq(struct irq_data *d)
-{
-        if (gic_arch_extn.irq_eoi) {
-                raw_spin_lock(&irq_controller_lock);
-                gic_arch_extn.irq_eoi(d);
-                raw_spin_unlock(&irq_controller_lock);
-        }
-        writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-}
-static int gic_set_type(struct irq_data *d, unsigned int type)
-{
-        void __iomem *base = gic_dist_base(d);
-        unsigned int gicirq = gic_irq(d);
-        u32 enablemask = 1 << (gicirq % 32);
-        u32 enableoff = (gicirq / 32) * 4;
-        u32 confmask = 0x2 << ((gicirq % 16) * 2);
-        u32 confoff = (gicirq / 16) * 4;
-        bool enabled = false;
-        u32 val;
-        /* Interrupt configuration for SGIs can't be changed */
-        if (gicirq < 16)
-                return -EINVAL;
-        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
-                return -EINVAL;
-        raw_spin_lock(&irq_controller_lock);
-        if (gic_arch_extn.irq_set_type)
-                gic_arch_extn.irq_set_type(d, type);
-        val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
-        if (type == IRQ_TYPE_LEVEL_HIGH)
-                val &= ~confmask;
-        else if (type == IRQ_TYPE_EDGE_RISING)
-                val |= confmask;
-        /*
-         * As recommended by the spec, disable the interrupt before changing
-         * the configuration
-         */
-        if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
-                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
-                enabled = true;
-        }
-        writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
-        if (enabled)
-                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
-        raw_spin_unlock(&irq_controller_lock);
-        return 0;
-}
-static int gic_retrigger(struct irq_data *d)
-{
-        if (gic_arch_extn.irq_retrigger)
-                return gic_arch_extn.irq_retrigger(d);
-        return -ENXIO;
-}
-#ifdef CONFIG_SMP
-static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
-                            bool force)
-{
-        void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-        unsigned int shift = (gic_irq(d) % 4) * 8;
-        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
-        u32 val, mask, bit;
-        if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
-                return -EINVAL;
-        mask = 0xff << shift;
-        bit = gic_cpu_map[cpu] << shift;
-        raw_spin_lock(&irq_controller_lock);
-        val = readl_relaxed(reg) & ~mask;
-        writel_relaxed(val | bit, reg);
-        raw_spin_unlock(&irq_controller_lock);
-        return IRQ_SET_MASK_OK;
-}
-#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
-        int ret = -ENXIO;
-        if (gic_arch_extn.irq_set_wake)
-                ret = gic_arch_extn.irq_set_wake(d, on);
-        return ret;
-}
-#else
-#define gic_set_wake    NULL
-#endif
-asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
-{
-        u32 irqstat, irqnr;
-        struct gic_chip_data *gic = &gic_data[0];
-        void __iomem *cpu_base = gic_data_cpu_base(gic);
-        do {
-                irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
-                irqnr = irqstat & ~0x1c00;
-                if (likely(irqnr > 15 && irqnr < 1021)) {
-                        irqnr = irq_find_mapping(gic->domain, irqnr);
-                        handle_IRQ(irqnr, regs);
-                        continue;
-                }
-                if (irqnr < 16) {
-                        writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
-#ifdef CONFIG_SMP
-                        handle_IPI(irqnr, regs);
-#endif
-                        continue;
-                }
-                break;
-        } while (1);
-}
-static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct gic_chip_data *chip_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        unsigned int cascade_irq, gic_irq;
-        unsigned long status;
-        chained_irq_enter(chip, desc);
-        raw_spin_lock(&irq_controller_lock);
-        status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
-        raw_spin_unlock(&irq_controller_lock);
-        gic_irq = (status & 0x3ff);
-        if (gic_irq == 1023)
-                goto out;
-        cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
-        if (unlikely(gic_irq < 32 || gic_irq > 1020))
-                do_bad_IRQ(cascade_irq, desc);
-        else
-                generic_handle_irq(cascade_irq);
- out:
-        chained_irq_exit(chip, desc);
-}
-static struct irq_chip gic_chip = {
-        .name                   = "GIC",
-        .irq_mask               = gic_mask_irq,
-        .irq_unmask             = gic_unmask_irq,
-        .irq_eoi                = gic_eoi_irq,
-        .irq_set_type           = gic_set_type,
-        .irq_retrigger          = gic_retrigger,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = gic_set_affinity,
-#endif
-        .irq_set_wake           = gic_set_wake,
-};
-void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
-{
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
-                BUG();
-        irq_set_chained_handler(irq, gic_handle_cascade_irq);
-}
-static void __init gic_dist_init(struct gic_chip_data *gic)
-{
-        unsigned int i;
-        u32 cpumask;
-        unsigned int gic_irqs = gic->gic_irqs;
-        void __iomem *base = gic_data_dist_base(gic);
-        writel_relaxed(0, base + GIC_DIST_CTRL);
-        /*
-         * Set all global interrupts to be level triggered, active low.
-         */
-        for (i = 32; i < gic_irqs; i += 16)
-                writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
-        /*
-         * Set all global interrupts to this CPU only.
-         */
-        cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
-        for (i = 32; i < gic_irqs; i += 4)
-                writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
-        /*
-         * Set priority on all global interrupts.
-         */
-        for (i = 32; i < gic_irqs; i += 4)
-                writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
-        /*
-         * Disable all interrupts.  Leave the PPI and SGIs alone
-         * as these enables are banked registers.
-         */
-        for (i = 32; i < gic_irqs; i += 32)
-                writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
-        writel_relaxed(1, base + GIC_DIST_CTRL);
-}
-static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
-{
-        void __iomem *dist_base = gic_data_dist_base(gic);
-        void __iomem *base = gic_data_cpu_base(gic);
-        unsigned int cpu_mask, cpu = smp_processor_id();
-        int i;
-        /*
-         * Get what the GIC says our CPU mask is.
-         */
-        BUG_ON(cpu >= NR_GIC_CPU_IF);
-        cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
-        gic_cpu_map[cpu] = cpu_mask;
-        /*
-         * Clear our mask from the other map entries in case they're
-         * still undefined.
-         */
-        for (i = 0; i < NR_GIC_CPU_IF; i++)
-                if (i != cpu)
-                        gic_cpu_map[i] &= ~cpu_mask;
-        /*
-         * Deal with the banked PPI and SGI interrupts - disable all
-         * PPI interrupts, ensure all SGI interrupts are enabled.
-         */
-        writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-        writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-        /*
-         * Set priority on PPI and SGI interrupts
-         */
-        for (i = 0; i < 32; i += 4)
-                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
-        writel_relaxed(1, base + GIC_CPU_CTRL);
-}
-#ifdef CONFIG_CPU_PM
-/*
- * Saves the GIC distributor registers during suspend or idle.  Must be called
- * with interrupts disabled but before powering down the GIC.  After calling
- * this function, no interrupts will be delivered by the GIC, and another
- * platform-specific wakeup source must be enabled.
- */
-static void gic_dist_save(unsigned int gic_nr)
-{
-        unsigned int gic_irqs;
-        void __iomem *dist_base;
-        int i;
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        if (!dist_base)
-                return;
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
-                gic_data[gic_nr].saved_spi_conf[i] =
-                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-                gic_data[gic_nr].saved_spi_target[i] =
-                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
-                gic_data[gic_nr].saved_spi_enable[i] =
-                        readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
-}
-/*
- * Restores the GIC distributor registers during resume or when coming out of
- * idle.  Must be called before enabling interrupts.  If a level interrupt
- * that occured while the GIC was suspended is still present, it will be
- * handled normally, but any edge interrupts that occured will not be seen by
- * the GIC and need to be handled by the platform-specific wakeup source.
- */
-static void gic_dist_restore(unsigned int gic_nr)
-{
-        unsigned int gic_irqs;
-        unsigned int i;
-        void __iomem *dist_base;
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        if (!dist_base)
-                return;
-        writel_relaxed(0, dist_base + GIC_DIST_CTRL);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
-                writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
-                        dist_base + GIC_DIST_CONFIG + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-                writel_relaxed(0xa0a0a0a0,
-                        dist_base + GIC_DIST_PRI + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
-                        dist_base + GIC_DIST_TARGET + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
-                writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
-                        dist_base + GIC_DIST_ENABLE_SET + i * 4);
-        writel_relaxed(1, dist_base + GIC_DIST_CTRL);
-}
-static void gic_cpu_save(unsigned int gic_nr)
-{
-        int i;
-        u32 *ptr;
-        void __iomem *dist_base;
-        void __iomem *cpu_base;
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-        if (!dist_base || !cpu_base)
-                return;
-        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
-        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
-                ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
-        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
-        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
-                ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
-}
-static void gic_cpu_restore(unsigned int gic_nr)
-{
-        int i;
-        u32 *ptr;
-        void __iomem *dist_base;
-        void __iomem *cpu_base;
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
-        if (!dist_base || !cpu_base)
-                return;
-        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
-        for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
-                writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
-        ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
-        for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
-                writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
-        for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
-                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
-        writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
-        writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
-}
-static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
-{
-        int i;
-        for (i = 0; i < MAX_GIC_NR; i++) {
-#ifdef CONFIG_GIC_NON_BANKED
-                /* Skip over unused GICs */
-                if (!gic_data[i].get_base)
-                        continue;
-#endif
-                switch (cmd) {
-                case CPU_PM_ENTER:
-                        gic_cpu_save(i);
-                        break;
-                case CPU_PM_ENTER_FAILED:
-                case CPU_PM_EXIT:
-                        gic_cpu_restore(i);
-                        break;
-                case CPU_CLUSTER_PM_ENTER:
-                        gic_dist_save(i);
-                        break;
-                case CPU_CLUSTER_PM_ENTER_FAILED:
-                case CPU_CLUSTER_PM_EXIT:
-                        gic_dist_restore(i);
-                        break;
-                }
-        }
-        return NOTIFY_OK;
-}
-static struct notifier_block gic_notifier_block = {
-        .notifier_call = gic_notifier,
-};
-static void __init gic_pm_init(struct gic_chip_data *gic)
-{
-        gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
-                sizeof(u32));
-        BUG_ON(!gic->saved_ppi_enable);
-        gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
-                sizeof(u32));
-        BUG_ON(!gic->saved_ppi_conf);
-        if (gic == &gic_data[0])
-                cpu_pm_register_notifier(&gic_notifier_block);
-}
-#else
-static void __init gic_pm_init(struct gic_chip_data *gic)
-{
-}
-#endif
-static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                                irq_hw_number_t hw)
-{
-        if (hw < 32) {
-                irq_set_percpu_devid(irq);
-                irq_set_chip_and_handler(irq, &gic_chip,
-                                         handle_percpu_devid_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
-        } else {
-                irq_set_chip_and_handler(irq, &gic_chip,
-                                         handle_fasteoi_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-        irq_set_chip_data(irq, d->host_data);
-        return 0;
-}
-static int gic_irq_domain_xlate(struct irq_domain *d,
-                                struct device_node *controller,
-                                const u32 *intspec, unsigned int intsize,
-                                unsigned long *out_hwirq, unsigned int *out_type)
-{
-        if (d->of_node != controller)
-                return -EINVAL;
-        if (intsize < 3)
-                return -EINVAL;
-        /* Get the interrupt number and add 16 to skip over SGIs */
-        *out_hwirq = intspec[1] + 16;
-        /* For SPIs, we need to add 16 more to get the GIC irq ID number */
-        if (!intspec[0])
-                *out_hwirq += 16;
-        *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
-        return 0;
-}
-const struct irq_domain_ops gic_irq_domain_ops = {
-        .map = gic_irq_domain_map,
-        .xlate = gic_irq_domain_xlate,
-};
-void __init gic_init_bases(unsigned int gic_nr, int irq_start,
-                           void __iomem *dist_base, void __iomem *cpu_base,
-                           u32 percpu_offset, struct device_node *node)
-{
-        irq_hw_number_t hwirq_base;
-        struct gic_chip_data *gic;
-        int gic_irqs, irq_base, i;
-        BUG_ON(gic_nr >= MAX_GIC_NR);
-        gic = &gic_data[gic_nr];
-#ifdef CONFIG_GIC_NON_BANKED
-        if (percpu_offset) { /* Frankein-GIC without banked registers... */
-                unsigned int cpu;
-                gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
-                gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
-                if (WARN_ON(!gic->dist_base.percpu_base ||
-                            !gic->cpu_base.percpu_base)) {
-                        free_percpu(gic->dist_base.percpu_base);
-                        free_percpu(gic->cpu_base.percpu_base);
-                        return;
-                }
-                for_each_possible_cpu(cpu) {
-                        unsigned long offset = percpu_offset * cpu_logical_map(cpu);
-                        *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
-                        *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
-                }
-                gic_set_base_accessor(gic, gic_get_percpu_base);
-        } else
-#endif
-        {                       /* Normal, sane GIC... */
-                WARN(percpu_offset,
-                     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
-                     percpu_offset);
-                gic->dist_base.common_base = dist_base;
-                gic->cpu_base.common_base = cpu_base;
-                gic_set_base_accessor(gic, gic_get_common_base);
-        }
-        /*
-         * Initialize the CPU interface map to all CPUs.
-         * It will be refined as each CPU probes its ID.
-         */
-        for (i = 0; i < NR_GIC_CPU_IF; i++)
-                gic_cpu_map[i] = 0xff;
-        /*
-         * For primary GICs, skip over SGIs.
-         * For secondary GICs, skip over PPIs, too.
-         */
-        if (gic_nr == 0 && (irq_start & 31) > 0) {
-                hwirq_base = 16;
-                if (irq_start != -1)
-                        irq_start = (irq_start & ~31) + 16;
-        } else {
-                hwirq_base = 32;
-        }
-        /*
-         * Find out how many interrupts are supported.
-         * The GIC only supports up to 1020 interrupt sources.
-         */
-        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
-        gic_irqs = (gic_irqs + 1) * 32;
-        if (gic_irqs > 1020)
-                gic_irqs = 1020;
-        gic->gic_irqs = gic_irqs;
-        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-        irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
-        if (IS_ERR_VALUE(irq_base)) {
-                WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-                     irq_start);
-                irq_base = irq_start;
-        }
-        gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
-                                    hwirq_base, &gic_irq_domain_ops, gic);
-        if (WARN_ON(!gic->domain))
-                return;
-        gic_chip.flags |= gic_arch_extn.flags;
-        gic_dist_init(gic);
-        gic_cpu_init(gic);
-        gic_pm_init(gic);
-}
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
-        BUG_ON(gic_nr >= MAX_GIC_NR);
-        gic_cpu_init(&gic_data[gic_nr]);
-}
-#ifdef CONFIG_SMP
-void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
-{
-        int cpu;
-        unsigned long map = 0;
-        /* Convert our logical CPU mask into a physical one. */
-        for_each_cpu(cpu, mask)
-                map |= gic_cpu_map[cpu];
-        /*
-         * Ensure that stores to Normal memory are visible to the
-         * other CPUs before issuing the IPI.
-         */
-        dsb();
-        /* this always happens on GIC0 */
-        writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
-}
-#endif
-#ifdef CONFIG_OF
-static int gic_cnt __initdata = 0;
-int __init gic_of_init(struct device_node *node, struct device_node *parent)
-{
-        void __iomem *cpu_base;
-        void __iomem *dist_base;
-        u32 percpu_offset;
-        int irq;
-        if (WARN_ON(!node))
-                return -ENODEV;
-        dist_base = of_iomap(node, 0);
-        WARN(!dist_base, "unable to map gic dist registers\n");
-        cpu_base = of_iomap(node, 1);
-        WARN(!cpu_base, "unable to map gic cpu registers\n");
-        if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
-                percpu_offset = 0;
-        gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
-        if (parent) {
-                irq = irq_of_parse_and_map(node, 0);
-                gic_cascade_irq(gic_cnt, irq);
-        }
-        gic_cnt++;
-        return 0;
-}
-#endif
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
deleted file mode 100644
index 8f324b99416e..000000000000
--- a/arch/arm/common/vic.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- *  linux/arch/arm/common/vic.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/syscore_ops.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-#include <asm/hardware/vic.h>
-/**
- * struct vic_device - VIC PM device
- * @irq: The IRQ number for the base of the VIC.
- * @base: The register base for the VIC.
- * @valid_sources: A bitmask of valid interrupts
- * @resume_sources: A bitmask of interrupts for resume.
- * @resume_irqs: The IRQs enabled for resume.
- * @int_select: Save for VIC_INT_SELECT.
- * @int_enable: Save for VIC_INT_ENABLE.
- * @soft_int: Save for VIC_INT_SOFT.
- * @protect: Save for VIC_PROTECT.
- * @domain: The IRQ domain for the VIC.
- */
-struct vic_device {
-        void __iomem    *base;
-        int             irq;
-        u32             valid_sources;
-        u32             resume_sources;
-        u32             resume_irqs;
-        u32             int_select;
-        u32             int_enable;
-        u32             soft_int;
-        u32             protect;
-        struct irq_domain *domain;
-};
-/* we cannot allocate memory when VICs are initially registered */
-static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
-static int vic_id;
-/**
- * vic_init2 - common initialisation code
- * @base: Base of the VIC.
- *
- * Common initialisation code for registration
- * and resume.
-*/
-static void vic_init2(void __iomem *base)
-{
-        int i;
-        for (i = 0; i < 16; i++) {
-                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                writel(VIC_VECT_CNTL_ENABLE | i, reg);
-        }
-        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-}
-#ifdef CONFIG_PM
-static void resume_one_vic(struct vic_device *vic)
-{
-        void __iomem *base = vic->base;
-        printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
-        /* re-initialise static settings */
-        vic_init2(base);
-        writel(vic->int_select, base + VIC_INT_SELECT);
-        writel(vic->protect, base + VIC_PROTECT);
-        /* set the enabled ints and then clear the non-enabled */
-        writel(vic->int_enable, base + VIC_INT_ENABLE);
-        writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
-        /* and the same for the soft-int register */
-        writel(vic->soft_int, base + VIC_INT_SOFT);
-        writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
-}
-static void vic_resume(void)
-{
-        int id;
-        for (id = vic_id - 1; id >= 0; id--)
-                resume_one_vic(vic_devices + id);
-}
-static void suspend_one_vic(struct vic_device *vic)
-{
-        void __iomem *base = vic->base;
-        printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
-        vic->int_select = readl(base + VIC_INT_SELECT);
-        vic->int_enable = readl(base + VIC_INT_ENABLE);
-        vic->soft_int = readl(base + VIC_INT_SOFT);
-        vic->protect = readl(base + VIC_PROTECT);
-        /* set the interrupts (if any) that are used for
-         * resuming the system */
-        writel(vic->resume_irqs, base + VIC_INT_ENABLE);
-        writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
-}
-static int vic_suspend(void)
-{
-        int id;
-        for (id = 0; id < vic_id; id++)
-                suspend_one_vic(vic_devices + id);
-        return 0;
-}
-struct syscore_ops vic_syscore_ops = {
-        .suspend        = vic_suspend,
-        .resume         = vic_resume,
-};
-/**
- * vic_pm_init - initicall to register VIC pm
- *
- * This is called via late_initcall() to register
- * the resources for the VICs due to the early
- * nature of the VIC's registration.
-*/
-static int __init vic_pm_init(void)
-{
-        if (vic_id > 0)
-                register_syscore_ops(&vic_syscore_ops);
-        return 0;
-}
-late_initcall(vic_pm_init);
-#endif /* CONFIG_PM */
-static struct irq_chip vic_chip;
-static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
-                             irq_hw_number_t hwirq)
-{
-        struct vic_device *v = d->host_data;
-        /* Skip invalid IRQs, only register handlers for the real ones */
-        if (!(v->valid_sources & (1 << hwirq)))
-                return -ENOTSUPP;
-        irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
-        irq_set_chip_data(irq, v->base);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        return 0;
-}
-static struct irq_domain_ops vic_irqdomain_ops = {
-        .map = vic_irqdomain_map,
-        .xlate = irq_domain_xlate_onetwocell,
-};
-/**
- * vic_register() - Register a VIC.
- * @base: The base address of the VIC.
- * @irq: The base IRQ for the VIC.
- * @valid_sources: bitmask of valid interrupts
- * @resume_sources: bitmask of interrupts allowed for resume sources.
- * @node: The device tree node associated with the VIC.
- *
- * Register the VIC with the system device tree so that it can be notified
- * of suspend and resume requests and ensure that the correct actions are
- * taken to re-instate the settings on resume.
- *
- * This also configures the IRQ domain for the VIC.
- */
-static void __init vic_register(void __iomem *base, unsigned int irq,
-                                u32 valid_sources, u32 resume_sources,
-                                struct device_node *node)
-{
-        struct vic_device *v;
-        int i;
-        if (vic_id >= ARRAY_SIZE(vic_devices)) {
-                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-                return;
-        }
-        v = &vic_devices[vic_id];
-        v->base = base;
-        v->valid_sources = valid_sources;
-        v->resume_sources = resume_sources;
-        v->irq = irq;
-        vic_id++;
-        v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
-                                          &vic_irqdomain_ops, v);
-        /* create an IRQ mapping for each valid IRQ */
-        for (i = 0; i < fls(valid_sources); i++)
-                if (valid_sources & (1 << i))
-                        irq_create_mapping(v->domain, i);
-}
-static void vic_ack_irq(struct irq_data *d)
-{
-        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->hwirq;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-        /* moreover, clear the soft-triggered, in case it was the reason */
-        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-}
-static void vic_mask_irq(struct irq_data *d)
-{
-        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->hwirq;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-}
-static void vic_unmask_irq(struct irq_data *d)
-{
-        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->hwirq;
-        writel(1 << irq, base + VIC_INT_ENABLE);
-}
-#if defined(CONFIG_PM)
-static struct vic_device *vic_from_irq(unsigned int irq)
-{
-        struct vic_device *v = vic_devices;
-        unsigned int base_irq = irq & ~31;
-        int id;
-        for (id = 0; id < vic_id; id++, v++) {
-                if (v->irq == base_irq)
-                        return v;
-        }
-        return NULL;
-}
-static int vic_set_wake(struct irq_data *d, unsigned int on)
-{
-        struct vic_device *v = vic_from_irq(d->irq);
-        unsigned int off = d->hwirq;
-        u32 bit = 1 << off;
-        if (!v)
-                return -EINVAL;
-        if (!(bit & v->resume_sources))
-                return -EINVAL;
-        if (on)
-                v->resume_irqs |= bit;
-        else
-                v->resume_irqs &= ~bit;
-        return 0;
-}
-#else
-#define vic_set_wake NULL
-#endif /* CONFIG_PM */
-static struct irq_chip vic_chip = {
-        .name           = "VIC",
-        .irq_ack        = vic_ack_irq,
-        .irq_mask       = vic_mask_irq,
-        .irq_unmask     = vic_unmask_irq,
-        .irq_set_wake   = vic_set_wake,
-};
-static void __init vic_disable(void __iomem *base)
-{
-        writel(0, base + VIC_INT_SELECT);
-        writel(0, base + VIC_INT_ENABLE);
-        writel(~0, base + VIC_INT_ENABLE_CLEAR);
-        writel(0, base + VIC_ITCR);
-        writel(~0, base + VIC_INT_SOFT_CLEAR);
-}
-static void __init vic_clear_interrupts(void __iomem *base)
-{
-        unsigned int i;
-        writel(0, base + VIC_PL190_VECT_ADDR);
-        for (i = 0; i < 19; i++) {
-                unsigned int value;
-                value = readl(base + VIC_PL190_VECT_ADDR);
-                writel(value, base + VIC_PL190_VECT_ADDR);
-        }
-}
-/*
- * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
- * The original cell has 32 interrupts, while the modified one has 64,
- * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
- * the probe function is called twice, with base set to offset 000
- *  and 020 within the page. We call this "second block".
- */
-static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
-                               u32 vic_sources, struct device_node *node)
-{
-        unsigned int i;
-        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
-        /* Disable all interrupts initially. */
-        vic_disable(base);
-        /*
-         * Make sure we clear all existing interrupts. The vector registers
-         * in this cell are after the second block of general registers,
-         * so we can address them using standard offsets, but only from
-         * the second base address, which is 0x20 in the page
-         */
-        if (vic_2nd_block) {
-                vic_clear_interrupts(base);
-                /* ST has 16 vectors as well, but we don't enable them by now */
-                for (i = 0; i < 16; i++) {
-                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                        writel(0, reg);
-                }
-                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-        }
-        vic_register(base, irq_start, vic_sources, 0, node);
-}
-void __init __vic_init(void __iomem *base, int irq_start,
-                              u32 vic_sources, u32 resume_sources,
-                              struct device_node *node)
-{
-        unsigned int i;
-        u32 cellid = 0;
-        enum amba_vendor vendor;
-        /* Identify which VIC cell this one is, by reading the ID */
-        for (i = 0; i < 4; i++) {
-                void __iomem *addr;
-                addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
-                cellid |= (readl(addr) & 0xff) << (8 * i);
-        }
-        vendor = (cellid >> 12) & 0xff;
-        printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
-               base, cellid, vendor);
-        switch(vendor) {
-        case AMBA_VENDOR_ST:
-                vic_init_st(base, irq_start, vic_sources, node);
-                return;
-        default:
-                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
-                /* fall through */
-        case AMBA_VENDOR_ARM:
-                break;
-        }
-        /* Disable all interrupts initially. */
-        vic_disable(base);
-        /* Make sure we clear all existing interrupts */
-        vic_clear_interrupts(base);
-        vic_init2(base);
-        vic_register(base, irq_start, vic_sources, resume_sources, node);
-}
-/**
- * vic_init() - initialise a vectored interrupt controller
- * @base: iomem base address
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
-                     u32 vic_sources, u32 resume_sources)
-{
-        __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
-}
-#ifdef CONFIG_OF
-int __init vic_of_init(struct device_node *node, struct device_node *parent)
-{
-        void __iomem *regs;
-        if (WARN(parent, "non-root VICs are not supported"))
-                return -EINVAL;
-        regs = of_iomap(node, 0);
-        if (WARN_ON(!regs))
-                return -EIO;
-        /*
-         * Passing 0 as first IRQ makes the simple domain allocate descriptors
-         */
-        __vic_init(regs, 0, ~0, ~0, node);
-        return 0;
-}
-#endif /* CONFIG OF */
-/*
- * Handle each interrupt in a single VIC.  Returns non-zero if we've
- * handled at least one interrupt.  This reads the status register
- * before handling each interrupt, which is necessary given that
- * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
- */
-static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
-{
-        u32 stat, irq;
-        int handled = 0;
-        while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
-                irq = ffs(stat) - 1;
-                handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
-                handled = 1;
-        }
-        return handled;
-}
-/*
- * Keep iterating over all registered VIC's until there are no pending
- * interrupts.
- */
-asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
-{
-        int i, handled;
-        do {
-                for (i = 0, handled = 0; i < vic_id; ++i)
-                        handled |= handle_one_vic(&vic_devices[i], regs);
-        } while (handled);
-}
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 2e1a82577207..0b98100d2ae7 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -34,12 +34,11 @@ CONFIG_AEABI=y
 CONFIG_FORCE_MAX_ZONEORDER=13
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"
+CONFIG_ARM_APPENDED_DTB=y
-CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -91,14 +90,11 @@ CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
-# CONFIG_RC_CORE is not set
+CONFIG_MEDIA_CAMERA_SUPPORT=y
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-# CONFIG_V4L_USB_DRIVERS is not set
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_MT9T112=y
 CONFIG_VIDEO_SH_MOBILE_CEU=y
-# CONFIG_RADIO_ADAPTERS is not set
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FB_SH_MOBILE_HDMI=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index c5212f43eee6..36fed66bd4b5 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
 CONFIG_MACH_USB_A9263=y
-CONFIG_MACH_NEOCORE926=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 74e27f0ff6ad..af472e4ed451 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -1,11 +1,10 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
@@ -30,13 +29,10 @@ CONFIG_EMBEDDED=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_JUMP_LABEL=y
-# CONFIG_BLOCK is not set
 CONFIG_ARCH_BCM2835=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_COMPACTION=y
 CONFIG_KSM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_CLEANCACHE=y
 CONFIG_SECCOMP=y
 CONFIG_CC_STACKPROTECTOR=y
@@ -45,6 +41,11 @@ CONFIG_CRASH_DUMP=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
@@ -53,20 +54,42 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_BCM2835=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM2835=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
+CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
+CONFIG_EXT2_FS_XATTR=y
-# CONFIG_INOTIFY_USER is not set
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFSD=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index f29223954af8..9aaad36a1728 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -36,6 +36,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
 CONFIG_CPU_FREQ_GOV_POWERSAVE=m
 CONFIG_CPU_FREQ_GOV_ONDEMAND=m
 CONFIG_CPU_IDLE=y
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -45,6 +46,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 CONFIG_NETFILTER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_RAM=y
@@ -81,6 +84,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
+CONFIG_PINCTRL_SINGLE=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 4ea7c95719d2..3edc78a40b66 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -33,6 +33,7 @@ CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -42,6 +43,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 CONFIG_NETFILTER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=m
 CONFIG_MTD_PARTITIONS=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 0b7ee92c5713..3fe8dae8d32d 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -1,26 +1,24 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_DOVE=y
 CONFIG_MACH_DOVE_DB=y
 CONFIG_MACH_CM_A510=y
 CONFIG_MACH_DOVE_DT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_HIGHMEM=y
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -32,8 +30,9 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -57,7 +56,6 @@ CONFIG_ATA=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
@@ -68,10 +66,7 @@ CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -81,13 +76,11 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_NEW_LEDS=y
@@ -104,6 +97,7 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -112,24 +106,20 @@ CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
@@ -138,7 +128,6 @@ CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_BLOWFISH=y
 CONFIG_CRYPTO_TEA=y
 CONFIG_CRYPTO_TWOFISH=y
@@ -147,5 +136,4 @@ CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_MV_CESA=y
 CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
 CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index ebbfb27e0e74..02c657af4005 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -61,6 +61,7 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -127,6 +128,8 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_VIDEO_MX2=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_CODA=y
 CONFIG_FB=y
 CONFIG_FB_IMX=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 69667133321f..e36b01025321 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MULTI_V6=y
 CONFIG_ARCH_MULTI_V7=y
+CONFIG_MACH_IMX31_DT=y
 CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_PCM037=y
@@ -32,7 +33,6 @@ CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
-CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
@@ -59,6 +59,7 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
+CONFIG_NETFILTER=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -151,6 +152,7 @@ CONFIG_MFD_MC13XXX_I2C=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_ANATOP=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
@@ -159,6 +161,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_DRM=y
 CONFIG_VIDEO_MX3=y
 CONFIG_FB=y
 CONFIG_LCD_PLATFORM=y
@@ -197,9 +200,14 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_SNVS=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
+CONFIG_STAGING=y
+CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_IPUV3_CORE=y
+CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 93f3794ba5cb..13482ea58b09 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -56,6 +56,7 @@ CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_KIRKWOOD=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
index fa83db1ef0eb..57ad3d47de70 100644
--- a/arch/arm/configs/kota2_defconfig
+++ b/arch/arm/configs/kota2_defconfig
@@ -21,7 +21,7 @@ CONFIG_ARCH_SHMOBILE=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KOTA2=y
-CONFIG_MEMORY_SIZE=0x1e0000000
+CONFIG_MEMORY_SIZE=0x1e000000
 # CONFIG_SH_TIMER_TMU is not set
 # CONFIG_SWP_EMULATE is not set
 CONFIG_CPU_BPREDICT_DISABLE=y
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 8c49df66cac3..6c37f4a98eb8 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -32,11 +32,9 @@ CONFIG_FORCE_MAX_ZONEORDER=13
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
-CONFIG_CMDLINE="console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
-CONFIG_CMDLINE_FORCE=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index afbae287436b..670c3b60f936 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -39,7 +39,7 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_KEXEC=y
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -85,6 +85,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DUMMY=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 2098ce155542..7594b3aff259 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -23,8 +23,9 @@ CONFIG_AEABI=y
 CONFIG_FORCE_MAX_ZONEORDER=15
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m"
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_KEXEC=y
+CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM=y
 CONFIG_PM_RUNTIME=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 728a43c446f8..afb17d630d44 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -83,7 +83,6 @@ CONFIG_USB=y
 CONFIG_USB_RCAR_PHY=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
-CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2eeff1e64b6e..e31d442343c8 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -8,6 +8,7 @@ CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SUNXI=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
+CONFIG_ARCH_ZYNQ=y
 CONFIG_ARM_ERRATA_754322=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
@@ -39,7 +40,6 @@ CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index b5bc96cb65a7..2ec8119cff73 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -14,16 +14,20 @@ CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
 CONFIG_SMP=y
-# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 # CONFIG_COMPACTION is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_INET=y
+CONFIG_BT=y
+CONFIG_BT_MRVL=y
+CONFIG_BT_MRVL_SDIO=y
+CONFIG_CFG80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
@@ -31,14 +35,34 @@ CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_MVNETA=y
 CONFIG_MARVELL_PHY=y
+CONFIG_MWIFIEX=y
+CONFIG_MWIFIEX_SDIO=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_SPI=y
+CONFIG_SPI_ORION=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_M25P80=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_MMC=y
+CONFIG_MMC_MVSDIO=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_S35390A=y
+CONFIG_RTC_DRV_MV=y
 CONFIG_DMADEVICES=y
 CONFIG_MV_XOR=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 7bf535104e26..fbbc5bb022d5 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_TASKSTATS=y
 CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_XACCT=y
@@ -8,7 +10,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
 # CONFIG_NET_NS is not set
 CONFIG_PERF_EVENTS=y
@@ -24,8 +25,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_ARCH_MXS=y
 CONFIG_MACH_MXS_DT=y
 # CONFIG_ARM_THUMB is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 CONFIG_AUTO_ZRELADDR=y
@@ -46,25 +45,34 @@ CONFIG_SYN_COOKIES=y
 CONFIG_CAN=m
 CONFIG_CAN_RAW=m
 CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
 CONFIG_CAN_FLEXCAN=m
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
-# CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_M25P80
+CONFIG_MTD_M25P80=y
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MTD_SST25L=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_UBI=y
+# CONFIG_BLK_DEV is not set
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_ENC28J60=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC95XX=y
-# CONFIG_NETDEV_1000 is not set
+CONFIG_SMSC_PHY=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_MICREL_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=m
@@ -91,21 +99,6 @@ CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-CONFIG_DISPLAY_SUPPORT=m
-# CONFIG_HID_SUPPORT is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_ARM=y
-CONFIG_SND_SOC=y
-CONFIG_SND_MXS_SOC=y
-CONFIG_SND_SOC_MXS_SGTL5000=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
@@ -117,13 +110,16 @@ CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
 CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_MXS_SOC=y
+CONFIG_SND_SOC_MXS_SGTL5000=y
 CONFIG_USB=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_MXS_PHY=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_NEW_LEDS=y
@@ -147,16 +143,23 @@ CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_IIO=y
 CONFIG_PWM=y
 CONFIG_PWM_MXS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
 CONFIG_FSCACHE_STATS=y
 CONFIG_CACHEFILES=m
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
@@ -170,17 +173,12 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_UNUSED_SYMBOLS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
-CONFIG_DETECT_HUNG_TASK=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_CRC32C=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC_ITU_T=m
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 82ce8d738fa1..b16bae2c9a60 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -20,9 +20,10 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_ARCH_VEXPRESS_CA9X4=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
@@ -52,6 +53,11 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
 CONFIG_BT=m
 CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_H4=y
@@ -64,6 +70,7 @@ CONFIG_MAC80211=m
 CONFIG_MAC80211_RC_PID=y
 CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_CMA=y
 CONFIG_CONNECTOR=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -83,6 +90,9 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SENSORS_LIS3LV02D=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_LIS3_I2C=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -108,6 +118,7 @@ CONFIG_USB_KC2190=y
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_MATRIX=m
 CONFIG_KEYBOARD_TWL4030=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
@@ -121,6 +132,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
@@ -131,14 +144,17 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
 CONFIG_W1=y
 CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_LM75=m
 CONFIG_WATCHDOG=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
 CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
 CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65910=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
@@ -150,6 +166,7 @@ CONFIG_OMAP2_DSS_SDI=y
 CONFIG_OMAP2_DSS_DSI=y
 CONFIG_FB_OMAP2=m
 CONFIG_PANEL_GENERIC_DPI=m
+CONFIG_PANEL_TFP410=m
 CONFIG_PANEL_SHARP_LS037V7DW01=m
 CONFIG_PANEL_NEC_NL8048HL11_01B=m
 CONFIG_PANEL_TAAL=m
@@ -194,11 +211,23 @@ CONFIG_USB_ZERO=m
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_SDIO_UART=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_TWL92330=y
 CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_DRV_OMAP=y
 CONFIG_DMADEVICES=y
 CONFIG_DMA_OMAP=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 6a936c7c078a..002a1ceadceb 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
 CONFIG_ARCH_SIRF=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 191118caa5c0..3bb7771d3c19 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -42,6 +42,14 @@ CONFIG_SMC91X=y
 # CONFIG_SERIO is not set
 CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_FB=y
+CONFIG_MMP_DISP=y
+CONFIG_MMP_DISP_CONTROLLER=y
+CONFIG_MMP_SPI=y
+CONFIG_MMP_PANEL_TPOHVGA=y
+CONFIG_MMP_FB=y
+CONFIG_LOGO=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index caa07db90cf5..e319b2c56f11 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -73,7 +73,6 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=m
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index a7827fd0616f..aba4881d20e5 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -38,6 +38,7 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_AUTO_ZRELADDR=y
+CONFIG_KEXEC=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -106,12 +107,14 @@ CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -127,6 +130,8 @@ CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
@@ -186,6 +191,7 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_TPS6586X=y
 CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 231dca604737..426270fe080d 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -66,9 +66,9 @@ CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
-CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY is not set
-CONFIG_AB8500_BM=y
+# CONFIG_AB8500_BM is not set
-CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
+# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_MFD_STMPE=y
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
index e59b1d505d6c..19d6cd6f29f9 100644
--- a/arch/arm/crypto/aes-armv4.S
+++ b/arch/arm/crypto/aes-armv4.S
@@ -34,8 +34,9 @@
 @ A little glue here to select the correct code below for the ARM CPU
 @ that is being targetted.
+#include <linux/linkage.h>
 .text
-.code   32
 .type   AES_Te,%object
 .align  5
@@ -145,10 +146,8 @@ AES_Te:
 @ void AES_encrypt(const unsigned char *in, unsigned char *out,
 @                const AES_KEY *key) {
-.global AES_encrypt
-.type   AES_encrypt,%function
 .align  5
-AES_encrypt:
+ENTRY(AES_encrypt)
        sub     r3,pc,#8                @ AES_encrypt
        stmdb   sp!,{r1,r4-r12,lr}
        mov     r12,r0          @ inp
@@ -239,15 +238,8 @@ AES_encrypt:
        strb    r6,[r12,#14]
        strb    r3,[r12,#15]
 #endif
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(AES_encrypt)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   AES_encrypt,.-AES_encrypt
 .type   _armv4_AES_encrypt,%function
 .align  2
@@ -386,10 +378,8 @@ _armv4_AES_encrypt:
        ldr     pc,[sp],#4              @ pop and return
 .size   _armv4_AES_encrypt,.-_armv4_AES_encrypt
-.global private_AES_set_encrypt_key
-.type   private_AES_set_encrypt_key,%function
 .align  5
-private_AES_set_encrypt_key:
+ENTRY(private_AES_set_encrypt_key)
 _armv4_AES_set_encrypt_key:
        sub     r3,pc,#8                @ AES_set_encrypt_key
        teq     r0,#0
@@ -658,15 +648,11 @@ _armv4_AES_set_encrypt_key:
 .Ldone: mov     r0,#0
        ldmia   sp!,{r4-r12,lr}
-.Labrt: tst     lr,#1
+.Labrt: mov     pc,lr
-        moveq   pc,lr                   @ be binary compatible with V4, yet
+ENDPROC(private_AES_set_encrypt_key)
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-.size   private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
-.global private_AES_set_decrypt_key
-.type   private_AES_set_decrypt_key,%function
 .align  5
-private_AES_set_decrypt_key:
+ENTRY(private_AES_set_decrypt_key)
        str     lr,[sp,#-4]!            @ push lr
 #if 0
        @ kernel does both of these in setkey so optimise this bit out by
@@ -748,15 +734,8 @@ private_AES_set_decrypt_key:
        bne     .Lmix
        mov     r0,#0
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(private_AES_set_decrypt_key)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
 .type   AES_Td,%object
 .align  5
@@ -862,10 +841,8 @@ AES_Td:
 @ void AES_decrypt(const unsigned char *in, unsigned char *out,
 @                const AES_KEY *key) {
-.global AES_decrypt
-.type   AES_decrypt,%function
 .align  5
-AES_decrypt:
+ENTRY(AES_decrypt)
        sub     r3,pc,#8                @ AES_decrypt
        stmdb   sp!,{r1,r4-r12,lr}
        mov     r12,r0          @ inp
@@ -956,15 +933,8 @@ AES_decrypt:
        strb    r6,[r12,#14]
        strb    r3,[r12,#15]
 #endif
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
+ENDPROC(AES_decrypt)
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
-.size   AES_decrypt,.-AES_decrypt
 .type   _armv4_AES_decrypt,%function
 .align  2
@@ -1064,7 +1034,9 @@ _armv4_AES_decrypt:
        and     r9,lr,r1,lsr#8
        ldrb    r7,[r10,r7]             @ Td4[s1>>0]
-        ldrb    r1,[r10,r1,lsr#24]      @ Td4[s1>>24]
+ ARM(   ldrb    r1,[r10,r1,lsr#24]  )   @ Td4[s1>>24]
+ THUMB( add     r1,r10,r1,lsr#24    )   @ Td4[s1>>24]
+ THUMB( ldrb    r1,[r1]             )
        ldrb    r8,[r10,r8]             @ Td4[s1>>16]
        eor     r0,r7,r0,lsl#24
        ldrb    r9,[r10,r9]             @ Td4[s1>>8]
@@ -1077,7 +1049,9 @@ _armv4_AES_decrypt:
        ldrb    r8,[r10,r8]             @ Td4[s2>>0]
        and     r9,lr,r2,lsr#16
-        ldrb    r2,[r10,r2,lsr#24]      @ Td4[s2>>24]
+ ARM(   ldrb    r2,[r10,r2,lsr#24]  )   @ Td4[s2>>24]
+ THUMB( add     r2,r10,r2,lsr#24    )   @ Td4[s2>>24]
+ THUMB( ldrb    r2,[r2]             )
        eor     r0,r0,r7,lsl#8
        ldrb    r9,[r10,r9]             @ Td4[s2>>16]
        eor     r1,r8,r1,lsl#16
@@ -1090,7 +1064,9 @@ _armv4_AES_decrypt:
        and     r9,lr,r3                @ i2
        ldrb    r9,[r10,r9]             @ Td4[s3>>0]
-        ldrb    r3,[r10,r3,lsr#24]      @ Td4[s3>>24]
+ ARM(   ldrb    r3,[r10,r3,lsr#24]  )   @ Td4[s3>>24]
+ THUMB( add     r3,r10,r3,lsr#24    )   @ Td4[s3>>24]
+ THUMB( ldrb    r3,[r3]             )
        eor     r0,r0,r7,lsl#16
        ldr     r7,[r11,#0]
        eor     r1,r1,r8,lsl#8
diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
index 7050ab133b9d..92c6eed7aac9 100644
--- a/arch/arm/crypto/sha1-armv4-large.S
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -51,13 +51,12 @@
 @ Profiler-assisted and platform-specific optimization resulted in 10%
 @ improvement on Cortex A8 core and 12.2 cycles per byte.
-.text
+#include <linux/linkage.h>
-.global sha1_block_data_order
+.text
-.type   sha1_block_data_order,%function
 .align  2
-sha1_block_data_order:
+ENTRY(sha1_block_data_order)
        stmdb   sp!,{r4-r12,lr}
        add     r2,r1,r2,lsl#6  @ r2 to point at the end of r1
        ldmia   r0,{r3,r4,r5,r6,r7}
@@ -194,7 +193,7 @@ sha1_block_data_order:
        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
        str     r9,[r14,#-4]!
        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
-        teq     r14,sp
+        cmp     r14,sp
        bne     .L_00_15                @ [((11+4)*5+2)*3]
 #if __ARM_ARCH__<7
        ldrb    r10,[r1,#2]
@@ -374,7 +373,9 @@ sha1_block_data_order:
                                                @ F_xx_xx
        add     r3,r3,r9                        @ E+=X[i]
        add     r3,r3,r10                       @ E+=F_20_39(B,C,D)
-        teq     r14,sp                  @ preserve carry
+ ARM(   teq     r14,sp          )       @ preserve carry
+ THUMB( mov     r11,sp          )
+ THUMB( teq     r14,r11         )       @ preserve carry
        bne     .L_20_39_or_60_79       @ [+((12+3)*5+2)*4]
        bcs     .L_done                 @ [+((12+3)*5+2)*4], spare 300 bytes
@@ -466,7 +467,7 @@ sha1_block_data_order:
        add     r3,r3,r9                        @ E+=X[i]
        add     r3,r3,r10                       @ E+=F_40_59(B,C,D)
        add     r3,r3,r11,ror#2
-        teq     r14,sp
+        cmp     r14,sp
        bne     .L_40_59                @ [+((12+5)*5+2)*4]
        ldr     r8,.LK_60_79
@@ -485,19 +486,12 @@ sha1_block_data_order:
        teq     r1,r2
        bne     .Lloop                  @ [+18], total 1307
-#if __ARM_ARCH__>=5
        ldmia   sp!,{r4-r12,pc}
-#else
-        ldmia   sp!,{r4-r12,lr}
-        tst     lr,#1
-        moveq   pc,lr                   @ be binary compatible with V4, yet
-        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
-#endif
 .align  2
 .LK_00_19:      .word   0x5a827999
 .LK_20_39:      .word   0x6ed9eba1
 .LK_40_59:      .word   0x8f1bbcdc
 .LK_60_79:      .word   0xca62c1d6
-.size   sha1_block_data_order,.-sha1_block_data_order
+ENDPROC(sha1_block_data_order)
 .asciz  "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
 .align  2
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index d40229d9a1c9..7ade91d8cc6f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,13 +1,115 @@
 #ifndef __ASMARM_ARCH_TIMER_H
 #define __ASMARM_ARCH_TIMER_H
+#include <asm/barrier.h>
 #include <asm/errno.h>
 #include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <clocksource/arm_arch_timer.h>
 #ifdef CONFIG_ARM_ARCH_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
-struct timecounter *arch_timer_get_timecounter(void);
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
+{
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                        break;
+                }
+        }
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+                        break;
+                }
+        }
+        isb();
+}
+static inline u32 arch_timer_reg_read(const int access, const int reg)
+{
+        u32 val = 0;
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                        break;
+                }
+        }
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+                        break;
+                }
+        }
+        return val;
+}
+static inline u32 arch_timer_get_cntfrq(void)
+{
+        u32 val;
+        asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+        return val;
+}
+static inline u64 arch_counter_get_cntpct(void)
+{
+        u64 cval;
+        isb();
+        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+        return cval;
+}
+static inline u64 arch_counter_get_cntvct(void)
+{
+        u64 cval;
+        isb();
+        asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+        return cval;
+}
+static inline void __cpuinit arch_counter_set_user_access(void)
+{
+        u32 cntkctl;
+        asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
+        /* disable user access to everything */
+        cntkctl &= ~((3 << 8) | (7 << 0));
+        asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
+}
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -18,11 +120,6 @@ static inline int arch_timer_sched_clock_init(void)
 {
        return -ENXIO;
 }
-static inline struct timecounter *arch_timer_get_timecounter(void)
-{
-        return NULL;
-}
 #endif
 #endif
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index eb87200aa4b5..05ee9eebad6b 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -246,18 +246,14 @@
 *
 * This macro is intended for forcing the CPU into SVC mode at boot time.
 * you cannot return to the original mode.
- *
- * Beware, it also clobers LR.
 */
 .macro safe_svcmode_maskall reg:req
 #if __LINUX_ARM_ARCH__ >= 6
        mrs     \reg , cpsr
-        mov     lr , \reg
+        eor     \reg, \reg, #HYP_MODE
-        and     lr , lr , #MODE_MASK
+        tst     \reg, #MODE_MASK
-        cmp     lr , #HYP_MODE
-        orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT
        bic     \reg , \reg , #MODE_MASK
-        orr     \reg , \reg , #SVC_MODE
+        orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
 THUMB(  orr     \reg , \reg , #PSR_T_BIT        )
        bne     1f
        orr     \reg, \reg, #PSR_A_BIT
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 574269ed2232..7652712d1d14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -38,6 +38,24 @@
 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
        ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
+#define ARM_CPU_IMP_ARM                 0x41
+#define ARM_CPU_IMP_INTEL               0x69
+#define ARM_CPU_PART_ARM1136            0xB360
+#define ARM_CPU_PART_ARM1156            0xB560
+#define ARM_CPU_PART_ARM1176            0xB760
+#define ARM_CPU_PART_ARM11MPCORE        0xB020
+#define ARM_CPU_PART_CORTEX_A8          0xC080
+#define ARM_CPU_PART_CORTEX_A9          0xC090
+#define ARM_CPU_PART_CORTEX_A5          0xC050
+#define ARM_CPU_PART_CORTEX_A15         0xC0F0
+#define ARM_CPU_PART_CORTEX_A7          0xC070
+#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
+#define ARM_CPU_XSCALE_ARCH_V1          0x2000
+#define ARM_CPU_XSCALE_ARCH_V2          0x4000
+#define ARM_CPU_XSCALE_ARCH_V3          0x6000
 extern unsigned int processor_id;
 #ifdef CONFIG_CPU_CP15
@@ -97,6 +115,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
 #endif /* ifdef CONFIG_CPU_CP15 / else */
+static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
+{
+        return (read_cpuid_id() & 0xFF000000) >> 24;
+}
+static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
+{
+        return read_cpuid_id() & 0xFFF0;
+}
+static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
+{
+        return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
+}
 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 {
        return read_cpuid(CPUID_CACHETYPE);
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index f2e5cad3f306..2381199acb7d 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,6 +2,7 @@
 #define __ASMARM_CTI_H
 #include        <asm/io.h>
+#include        <asm/hardware/coresight.h>
 /* The registers' definition is from section 3.2 of
 * Embedded Cross Trigger Revision: r0p0
@@ -35,11 +36,6 @@
 #define         LOCKACCESS              0xFB0
 #define         LOCKSTATUS              0xFB4
-/* write this value to LOCKACCESS will unlock the module, and
- * other value will lock the module
- */
-#define         LOCKCODE                0xC5ACCE55
 /**
 * struct cti - cross trigger interface struct
 * @base: mapped virtual address for the cti base
@@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
 */
 static inline void cti_unlock(struct cti *cti)
 {
-        __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 /**
@@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
 */
 static inline void cti_lock(struct cti *cti)
 {
-        __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 #endif
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index ab98fdd083bd..720799fd3a81 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,6 +24,7 @@ extern struct arm_delay_ops {
        void (*delay)(unsigned long);
        void (*const_udelay)(unsigned long);
        void (*udelay)(unsigned long);
+        bool const_clock;
 } arm_delay_ops;
 #define __delay(n)              arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index b69c0d3285f8..dc662fca9230 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -27,4 +27,10 @@ struct pdev_archdata {
 #endif
 };
+#ifdef CONFIG_ARM_DMA_USE_IOMMU
+#define to_dma_iommu_mapping(dev) ((dev)->archdata.mapping)
+#else
+#define to_dma_iommu_mapping(dev) NULL
+#endif
 #endif
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index 799b09409fad..a8c56acc8c98 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -7,6 +7,7 @@
 #include <linux/scatterlist.h>
 #include <linux/dma-debug.h>
 #include <linux/kmemcheck.h>
+#include <linux/kref.h>
 struct dma_iommu_mapping {
        /* iommu specific data */
@@ -29,6 +30,7 @@ void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
 int arm_iommu_attach_device(struct device *dev,
                                        struct dma_iommu_mapping *mapping);
+void arm_iommu_detach_device(struct device *dev);
 #endif /* __KERNEL__ */
 #endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 5694a0d6576b..58b8c6a0ab1f 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -105,7 +105,7 @@ extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
 */
 extern void __set_dma_addr(unsigned int chan, void *addr);
 #define set_dma_addr(chan, addr)                                \
-        __set_dma_addr(chan, bus_to_virt(addr))
+        __set_dma_addr(chan, (void *)__bus_to_virt(addr))
 /* Set the DMA byte count for this channel
 *
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793b8f5a..0cf7a6b842ff 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -36,7 +36,7 @@
 /* CoreSight Component Registers */
 #define CSCR_CLASS      0xff4
-#define UNLOCK_MAGIC    0xc5acce55
+#define CS_LAR_KEY      0xc5acce55
 /* ETM control register, "ETM Architecture", 3.3.1 */
 #define ETMR_CTRL               0
@@ -147,11 +147,11 @@
 #define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etm_unlock(t) \
-        do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etb_unlock(t) \
-        do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 #endif /* __ASM_HARDWARE_CORESIGHT_H */
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
deleted file mode 100644
index 4b1ce6cd477f..000000000000
--- a/arch/arm/include/asm/hardware/gic.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/gic.h
- *
- *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_HARDWARE_GIC_H
-#define __ASM_ARM_HARDWARE_GIC_H
-#include <linux/compiler.h>
-#define GIC_CPU_CTRL                    0x00
-#define GIC_CPU_PRIMASK                 0x04
-#define GIC_CPU_BINPOINT                0x08
-#define GIC_CPU_INTACK                  0x0c
-#define GIC_CPU_EOI                     0x10
-#define GIC_CPU_RUNNINGPRI              0x14
-#define GIC_CPU_HIGHPRI                 0x18
-#define GIC_DIST_CTRL                   0x000
-#define GIC_DIST_CTR                    0x004
-#define GIC_DIST_ENABLE_SET             0x100
-#define GIC_DIST_ENABLE_CLEAR           0x180
-#define GIC_DIST_PENDING_SET            0x200
-#define GIC_DIST_PENDING_CLEAR          0x280
-#define GIC_DIST_ACTIVE_BIT             0x300
-#define GIC_DIST_PRI                    0x400
-#define GIC_DIST_TARGET                 0x800
-#define GIC_DIST_CONFIG                 0xc00
-#define GIC_DIST_SOFTINT                0xf00
-#ifndef __ASSEMBLY__
-#include <linux/irqdomain.h>
-struct device_node;
-extern struct irq_chip gic_arch_extn;
-void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
-                    u32 offset, struct device_node *);
-int gic_of_init(struct device_node *node, struct device_node *parent);
-void gic_secondary_init(unsigned int);
-void gic_handle_irq(struct pt_regs *regs);
-void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
-void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-static inline void gic_init(unsigned int nr, int start,
-                            void __iomem *dist , void __iomem *cpu)
-{
-        gic_init_bases(nr, start, dist, cpu, 0, NULL);
-}
-#endif
-#endif
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
deleted file mode 100644
index 4eea2107214b..000000000000
--- a/arch/arm/include/asm/hardware/pl080.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* arch/arm/include/asm/hardware/pl080.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ARM PrimeCell PL080 DMA controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* Note, there are some Samsung updates to this controller block which
- * make it not entierly compatible with the PL080 specification from
- * ARM. When in doubt, check the Samsung documentation first.
- *
- * The Samsung defines are PL080S, and add an extra control register,
- * the ability to move more than 2^11 counts of data and some extra
- * OneNAND features.
-*/
-#ifndef ASM_PL080_H
-#define ASM_PL080_H
-#define PL080_INT_STATUS                        (0x00)
-#define PL080_TC_STATUS                         (0x04)
-#define PL080_TC_CLEAR                          (0x08)
-#define PL080_ERR_STATUS                        (0x0C)
-#define PL080_ERR_CLEAR                         (0x10)
-#define PL080_RAW_TC_STATUS                     (0x14)
-#define PL080_RAW_ERR_STATUS                    (0x18)
-#define PL080_EN_CHAN                           (0x1c)
-#define PL080_SOFT_BREQ                         (0x20)
-#define PL080_SOFT_SREQ                         (0x24)
-#define PL080_SOFT_LBREQ                        (0x28)
-#define PL080_SOFT_LSREQ                        (0x2C)
-#define PL080_CONFIG                            (0x30)
-#define PL080_CONFIG_M2_BE                      (1 << 2)
-#define PL080_CONFIG_M1_BE                      (1 << 1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
-#define PL080_SYNC                              (0x34)
-/* Per channel configuration registers */
-#define PL080_Cx_STRIDE                         (0x20)
-#define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
-#define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
-#define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
-#define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
-#define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
-#define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
-#define PL080_CH_SRC_ADDR                       (0x00)
-#define PL080_CH_DST_ADDR                       (0x04)
-#define PL080_CH_LLI                            (0x08)
-#define PL080_CH_CONTROL                        (0x0C)
-#define PL080_CH_CONFIG                         (0x10)
-#define PL080S_CH_CONTROL2                      (0x10)
-#define PL080S_CH_CONFIG                        (0x14)
-#define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
-#define PL080_LLI_ADDR_SHIFT                    (2)
-#define PL080_LLI_LM_AHB2                       (1 << 0)
-#define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
-#define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
-#define PL080_CONTROL_PROT_SHIFT                (28)
-#define PL080_CONTROL_PROT_CACHE                (1 << 30)
-#define PL080_CONTROL_PROT_BUFF                 (1 << 29)
-#define PL080_CONTROL_PROT_SYS                  (1 << 28)
-#define PL080_CONTROL_DST_INCR                  (1 << 27)
-#define PL080_CONTROL_SRC_INCR                  (1 << 26)
-#define PL080_CONTROL_DST_AHB2                  (1 << 25)
-#define PL080_CONTROL_SRC_AHB2                  (1 << 24)
-#define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
-#define PL080_CONTROL_DWIDTH_SHIFT              (21)
-#define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
-#define PL080_CONTROL_SWIDTH_SHIFT              (18)
-#define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
-#define PL080_CONTROL_DB_SIZE_SHIFT             (15)
-#define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
-#define PL080_CONTROL_SB_SIZE_SHIFT             (12)
-#define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
-#define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
-#define PL080_BSIZE_1                           (0x0)
-#define PL080_BSIZE_4                           (0x1)
-#define PL080_BSIZE_8                           (0x2)
-#define PL080_BSIZE_16                          (0x3)
-#define PL080_BSIZE_32                          (0x4)
-#define PL080_BSIZE_64                          (0x5)
-#define PL080_BSIZE_128                         (0x6)
-#define PL080_BSIZE_256                         (0x7)
-#define PL080_WIDTH_8BIT                        (0x0)
-#define PL080_WIDTH_16BIT                       (0x1)
-#define PL080_WIDTH_32BIT                       (0x2)
-#define PL080N_CONFIG_ITPROT                    (1 << 20)
-#define PL080N_CONFIG_SECPROT                   (1 << 19)
-#define PL080_CONFIG_HALT                       (1 << 18)
-#define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
-#define PL080_CONFIG_LOCK                       (1 << 16)
-#define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
-#define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
-#define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
-#define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
-#define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
-#define PL080_CONFIG_DST_SEL_SHIFT              (6)
-#define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
-#define PL080_CONFIG_SRC_SEL_SHIFT              (1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
-#define PL080_FLOW_MEM2MEM                      (0x0)
-#define PL080_FLOW_MEM2PER                      (0x1)
-#define PL080_FLOW_PER2MEM                      (0x2)
-#define PL080_FLOW_SRC2DST                      (0x3)
-#define PL080_FLOW_SRC2DST_DST                  (0x4)
-#define PL080_FLOW_MEM2PER_PER                  (0x5)
-#define PL080_FLOW_PER2MEM_PER                  (0x6)
-#define PL080_FLOW_SRC2DST_SRC                  (0x7)
-/* DMA linked list chain structure */
-struct pl080_lli {
-        u32     src_addr;
-        u32     dst_addr;
-        u32     next_lli;
-        u32     control0;
-};
-struct pl080s_lli {
-        u32     src_addr;
-        u32     dst_addr;
-        u32     next_lli;
-        u32     control0;
-        u32     control1;
-};
-#endif /* ASM_PL080_H */
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
deleted file mode 100644
index 6636430dd0e6..000000000000
--- a/arch/arm/include/asm/hardware/sp810.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/sp810.h
- *
- * ARM PrimeXsys System Controller SP810 header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARM_SP810_H
-#define __ASM_ARM_SP810_H
-#include <linux/io.h>
-/* sysctl registers offset */
-#define SCCTRL                  0x000
-#define SCSYSSTAT               0x004
-#define SCIMCTRL                0x008
-#define SCIMSTAT                0x00C
-#define SCXTALCTRL              0x010
-#define SCPLLCTRL               0x014
-#define SCPLLFCTRL              0x018
-#define SCPERCTRL0              0x01C
-#define SCPERCTRL1              0x020
-#define SCPEREN                 0x024
-#define SCPERDIS                0x028
-#define SCPERCLKEN              0x02C
-#define SCPERSTAT               0x030
-#define SCSYSID0                0xEE0
-#define SCSYSID1                0xEE4
-#define SCSYSID2                0xEE8
-#define SCSYSID3                0xEEC
-#define SCITCR                  0xF00
-#define SCITIR0                 0xF04
-#define SCITIR1                 0xF08
-#define SCITOR                  0xF0C
-#define SCCNTCTRL               0xF10
-#define SCCNTDATA               0xF14
-#define SCCNTSTEP               0xF18
-#define SCPERIPHID0             0xFE0
-#define SCPERIPHID1             0xFE4
-#define SCPERIPHID2             0xFE8
-#define SCPERIPHID3             0xFEC
-#define SCPCELLID0              0xFF0
-#define SCPCELLID1              0xFF4
-#define SCPCELLID2              0xFF8
-#define SCPCELLID3              0xFFC
-#define SCCTRL_TIMERENnSEL_SHIFT(n)     (15 + ((n) * 2))
-static inline void sysctl_soft_reset(void __iomem *base)
-{
-        /* switch to slow mode */
-        writel(0x2, base + SCCTRL);
-        /* writing any value to SCSYSSTAT reg will reset system */
-        writel(0, base + SCSYSSTAT);
-}
-#endif  /* __ASM_ARM_SP810_H */
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
deleted file mode 100644
index 2bebad36fc83..000000000000
--- a/arch/arm/include/asm/hardware/vic.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/vic.h
- *
- *  Copyright (c) ARM Limited 2003.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_HARDWARE_VIC_H
-#define __ASM_ARM_HARDWARE_VIC_H
-#define VIC_IRQ_STATUS                  0x00
-#define VIC_FIQ_STATUS                  0x04
-#define VIC_RAW_STATUS                  0x08
-#define VIC_INT_SELECT                  0x0c    /* 1 = FIQ, 0 = IRQ */
-#define VIC_INT_ENABLE                  0x10    /* 1 = enable, 0 = disable */
-#define VIC_INT_ENABLE_CLEAR            0x14
-#define VIC_INT_SOFT                    0x18
-#define VIC_INT_SOFT_CLEAR              0x1c
-#define VIC_PROTECT                     0x20
-#define VIC_PL190_VECT_ADDR             0x30    /* PL190 only */
-#define VIC_PL190_DEF_VECT_ADDR         0x34    /* PL190 only */
-#define VIC_VECT_ADDR0                  0x100   /* 0 to 15 (0..31 PL192) */
-#define VIC_VECT_CNTL0                  0x200   /* 0 to 15 (0..31 PL192) */
-#define VIC_ITCR                        0x300   /* VIC test control register */
-#define VIC_VECT_CNTL_ENABLE            (1 << 5)
-#define VIC_PL192_VECT_ADDR             0xF00
-#ifndef __ASSEMBLY__
-#include <linux/compiler.h>
-#include <linux/types.h>
-struct device_node;
-struct pt_regs;
-void __vic_init(void __iomem *base, int irq_start, u32 vic_sources,
-                u32 resume_sources, struct device_node *node);
-void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-int vic_of_init(struct device_node *node, struct device_node *parent);
-void vic_handle_irq(struct pt_regs *regs);
-#endif /* __ASSEMBLY__ */
-#endif
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 01169dd723f1..eef55ea9ef00 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DSCR_HDBGEN         (1 << 14)
 #define ARM_DSCR_MDBGEN         (1 << 15)
+/* OSLSR os lock model bits */
+#define ARM_OSLSR_OSLM0         (1 << 0)
 /* opcode2 numbers for the co-processor instructions. */
 #define ARM_OP2_BVR             4
 #define ARM_OP2_BCR             5
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index bf863edb517d..1a66f907e5cc 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -8,6 +8,7 @@
 #define __idmap __section(.idmap.text) noinline notrace
 extern pgd_t *idmap_pgd;
+extern pgd_t *hyp_pgd;
 void setup_mm_for_reboot(void);
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
new file mode 100644
index 000000000000..68cb9e1dfb81
--- /dev/null
+++ b/arch/arm/include/asm/kvm_arch_timer.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
+#define __ASM_ARM_KVM_ARCH_TIMER_H
+#include <linux/clocksource.h>
+#include <linux/hrtimer.h>
+#include <linux/workqueue.h>
+struct arch_timer_kvm {
+#ifdef CONFIG_KVM_ARM_TIMER
+        /* Is the timer enabled */
+        bool                    enabled;
+        /* Virtual offset */
+        cycle_t                 cntvoff;
+#endif
+};
+struct arch_timer_cpu {
+#ifdef CONFIG_KVM_ARM_TIMER
+        /* Registers: control register, timer value */
+        u32                             cntv_ctl;       /* Saved/restored */
+        cycle_t                         cntv_cval;      /* Saved/restored */
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* Background timer used when the guest is not running */
+        struct hrtimer                  timer;
+        /* Work queued with the above timer expires */
+        struct work_struct              expired;
+        /* Background timer active */
+        bool                            armed;
+        /* Timer IRQ */
+        const struct kvm_irq_level      *irq;
+#endif
+};
+#ifdef CONFIG_KVM_ARM_TIMER
+int kvm_timer_hyp_init(void);
+int kvm_timer_init(struct kvm *kvm);
+void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
+void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
+void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
+void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
+#else
+static inline int kvm_timer_hyp_init(void)
+{
+        return 0;
+};
+static inline int kvm_timer_init(struct kvm *kvm)
+{
+        return 0;
+}
+static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
+static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
+#endif
+#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
new file mode 100644
index 000000000000..7c3d813e15df
--- /dev/null
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_ARM_H__
+#define __ARM_KVM_ARM_H__
+#include <linux/types.h>
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_TGE         (1 << 27)
+#define HCR_TVM         (1 << 26)
+#define HCR_TTLB        (1 << 25)
+#define HCR_TPU         (1 << 24)
+#define HCR_TPC         (1 << 23)
+#define HCR_TSW         (1 << 22)
+#define HCR_TAC         (1 << 21)
+#define HCR_TIDCP       (1 << 20)
+#define HCR_TSC         (1 << 19)
+#define HCR_TID3        (1 << 18)
+#define HCR_TID2        (1 << 17)
+#define HCR_TID1        (1 << 16)
+#define HCR_TID0        (1 << 15)
+#define HCR_TWE         (1 << 14)
+#define HCR_TWI         (1 << 13)
+#define HCR_DC          (1 << 12)
+#define HCR_BSU         (3 << 10)
+#define HCR_BSU_IS      (1 << 10)
+#define HCR_FB          (1 << 9)
+#define HCR_VA          (1 << 8)
+#define HCR_VI          (1 << 7)
+#define HCR_VF          (1 << 6)
+#define HCR_AMO         (1 << 5)
+#define HCR_IMO         (1 << 4)
+#define HCR_FMO         (1 << 3)
+#define HCR_PTW         (1 << 2)
+#define HCR_SWIO        (1 << 1)
+#define HCR_VM          1
+/*
+ * The bits we set in HCR:
+ * TAC:         Trap ACTLR
+ * TSC:         Trap SMC
+ * TSW:         Trap cache operations by set/way
+ * TWI:         Trap WFI
+ * TIDCP:       Trap L2CTLR/L2ECTLR
+ * BSU_IS:      Upgrade barriers to the inner shareable domain
+ * FB:          Force broadcast of all maintainance operations
+ * AMO:         Override CPSR.A and enable signaling with VA
+ * IMO:         Override CPSR.I and enable signaling with VI
+ * FMO:         Override CPSR.F and enable signaling with VF
+ * SWIO:        Turn set/way invalidates into set/way clean+invalidate
+ */
+#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
+                        HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
+                        HCR_SWIO | HCR_TIDCP)
+#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
+/* System Control Register (SCTLR) bits */
+#define SCTLR_TE        (1 << 30)
+#define SCTLR_EE        (1 << 25)
+#define SCTLR_V         (1 << 13)
+/* Hyp System Control Register (HSCTLR) bits */
+#define HSCTLR_TE       (1 << 30)
+#define HSCTLR_EE       (1 << 25)
+#define HSCTLR_FI       (1 << 21)
+#define HSCTLR_WXN      (1 << 19)
+#define HSCTLR_I        (1 << 12)
+#define HSCTLR_C        (1 << 2)
+#define HSCTLR_A        (1 << 1)
+#define HSCTLR_M        1
+#define HSCTLR_MASK     (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
+                         HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
+/* TTBCR and HTCR Registers bits */
+#define TTBCR_EAE       (1 << 31)
+#define TTBCR_IMP       (1 << 30)
+#define TTBCR_SH1       (3 << 28)
+#define TTBCR_ORGN1     (3 << 26)
+#define TTBCR_IRGN1     (3 << 24)
+#define TTBCR_EPD1      (1 << 23)
+#define TTBCR_A1        (1 << 22)
+#define TTBCR_T1SZ      (3 << 16)
+#define TTBCR_SH0       (3 << 12)
+#define TTBCR_ORGN0     (3 << 10)
+#define TTBCR_IRGN0     (3 << 8)
+#define TTBCR_EPD0      (1 << 7)
+#define TTBCR_T0SZ      3
+#define HTCR_MASK       (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
+/* Hyp System Trap Register */
+#define HSTR_T(x)       (1 << x)
+#define HSTR_TTEE       (1 << 16)
+#define HSTR_TJDBX      (1 << 17)
+/* Hyp Coprocessor Trap Register */
+#define HCPTR_TCP(x)    (1 << x)
+#define HCPTR_TCP_MASK  (0x3fff)
+#define HCPTR_TASE      (1 << 15)
+#define HCPTR_TTA       (1 << 20)
+#define HCPTR_TCPAC     (1 << 31)
+/* Hyp Debug Configuration Register bits */
+#define HDCR_TDRA       (1 << 11)
+#define HDCR_TDOSA      (1 << 10)
+#define HDCR_TDA        (1 << 9)
+#define HDCR_TDE        (1 << 8)
+#define HDCR_HPME       (1 << 7)
+#define HDCR_TPM        (1 << 6)
+#define HDCR_TPMCR      (1 << 5)
+#define HDCR_HPMN_MASK  (0x1F)
+/*
+ * The architecture supports 40-bit IPA as input to the 2nd stage translations
+ * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
+ * space.
+ */
+#define KVM_PHYS_SHIFT  (40)
+#define KVM_PHYS_SIZE   (1ULL << KVM_PHYS_SHIFT)
+#define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1ULL)
+#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
+#define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
+#define S2_PGD_SIZE     (1 << S2_PGD_ORDER)
+/* Virtualization Translation Control Register (VTCR) bits */
+#define VTCR_SH0        (3 << 12)
+#define VTCR_ORGN0      (3 << 10)
+#define VTCR_IRGN0      (3 << 8)
+#define VTCR_SL0        (3 << 6)
+#define VTCR_S          (1 << 4)
+#define VTCR_T0SZ       (0xf)
+#define VTCR_MASK       (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
+                         VTCR_S | VTCR_T0SZ)
+#define VTCR_HTCR_SH    (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
+#define VTCR_SL_L2      (0 << 6)        /* Starting-level: 2 */
+#define VTCR_SL_L1      (1 << 6)        /* Starting-level: 1 */
+#define KVM_VTCR_SL0    VTCR_SL_L1
+/* stage-2 input address range defined as 2^(32-T0SZ) */
+#define KVM_T0SZ        (32 - KVM_PHYS_SHIFT)
+#define KVM_VTCR_T0SZ   (KVM_T0SZ & VTCR_T0SZ)
+#define KVM_VTCR_S      ((KVM_VTCR_T0SZ << 1) & VTCR_S)
+/* Virtualization Translation Table Base Register (VTTBR) bits */
+#if KVM_VTCR_SL0 == VTCR_SL_L2  /* see ARM DDI 0406C: B4-1720 */
+#define VTTBR_X         (14 - KVM_T0SZ)
+#else
+#define VTTBR_X         (5 - KVM_T0SZ)
+#endif
+#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
+#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
+/* Hyp Syndrome Register (HSR) bits */
+#define HSR_EC_SHIFT    (26)
+#define HSR_EC          (0x3fU << HSR_EC_SHIFT)
+#define HSR_IL          (1U << 25)
+#define HSR_ISS         (HSR_IL - 1)
+#define HSR_ISV_SHIFT   (24)
+#define HSR_ISV         (1U << HSR_ISV_SHIFT)
+#define HSR_SRT_SHIFT   (16)
+#define HSR_SRT_MASK    (0xf << HSR_SRT_SHIFT)
+#define HSR_FSC         (0x3f)
+#define HSR_FSC_TYPE    (0x3c)
+#define HSR_SSE         (1 << 21)
+#define HSR_WNR         (1 << 6)
+#define HSR_CV_SHIFT    (24)
+#define HSR_CV          (1U << HSR_CV_SHIFT)
+#define HSR_COND_SHIFT  (20)
+#define HSR_COND        (0xfU << HSR_COND_SHIFT)
+#define FSC_FAULT       (0x04)
+#define FSC_PERM        (0x0c)
+/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
+#define HPFAR_MASK      (~0xf)
+#define HSR_EC_UNKNOWN  (0x00)
+#define HSR_EC_WFI      (0x01)
+#define HSR_EC_CP15_32  (0x03)
+#define HSR_EC_CP15_64  (0x04)
+#define HSR_EC_CP14_MR  (0x05)
+#define HSR_EC_CP14_LS  (0x06)
+#define HSR_EC_CP_0_13  (0x07)
+#define HSR_EC_CP10_ID  (0x08)
+#define HSR_EC_JAZELLE  (0x09)
+#define HSR_EC_BXJ      (0x0A)
+#define HSR_EC_CP14_64  (0x0C)
+#define HSR_EC_SVC_HYP  (0x11)
+#define HSR_EC_HVC      (0x12)
+#define HSR_EC_SMC      (0x13)
+#define HSR_EC_IABT     (0x20)
+#define HSR_EC_IABT_HYP (0x21)
+#define HSR_EC_DABT     (0x24)
+#define HSR_EC_DABT_HYP (0x25)
+#define HSR_HVC_IMM_MASK        ((1UL << 16) - 1)
+#endif /* __ARM_KVM_ARM_H__ */
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..e4956f4e23e1
--- /dev/null
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_ASM_H__
+#define __ARM_KVM_ASM_H__
+/* 0 is reserved as an invalid value. */
+#define c0_MPIDR        1       /* MultiProcessor ID Register */
+#define c0_CSSELR       2       /* Cache Size Selection Register */
+#define c1_SCTLR        3       /* System Control Register */
+#define c1_ACTLR        4       /* Auxilliary Control Register */
+#define c1_CPACR        5       /* Coprocessor Access Control */
+#define c2_TTBR0        6       /* Translation Table Base Register 0 */
+#define c2_TTBR0_high   7       /* TTBR0 top 32 bits */
+#define c2_TTBR1        8       /* Translation Table Base Register 1 */
+#define c2_TTBR1_high   9       /* TTBR1 top 32 bits */
+#define c2_TTBCR        10      /* Translation Table Base Control R. */
+#define c3_DACR         11      /* Domain Access Control Register */
+#define c5_DFSR         12      /* Data Fault Status Register */
+#define c5_IFSR         13      /* Instruction Fault Status Register */
+#define c5_ADFSR        14      /* Auxilary Data Fault Status R */
+#define c5_AIFSR        15      /* Auxilary Instrunction Fault Status R */
+#define c6_DFAR         16      /* Data Fault Address Register */
+#define c6_IFAR         17      /* Instruction Fault Address Register */
+#define c9_L2CTLR       18      /* Cortex A15 L2 Control Register */
+#define c10_PRRR        19      /* Primary Region Remap Register */
+#define c10_NMRR        20      /* Normal Memory Remap Register */
+#define c12_VBAR        21      /* Vector Base Address Register */
+#define c13_CID         22      /* Context ID Register */
+#define c13_TID_URW     23      /* Thread ID, User R/W */
+#define c13_TID_URO     24      /* Thread ID, User R/O */
+#define c13_TID_PRIV    25      /* Thread ID, Privileged */
+#define c14_CNTKCTL     26      /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    27      /* Number of regs (incl. invalid) */
+#define ARM_EXCEPTION_RESET       0
+#define ARM_EXCEPTION_UNDEFINED   1
+#define ARM_EXCEPTION_SOFTWARE    2
+#define ARM_EXCEPTION_PREF_ABORT  3
+#define ARM_EXCEPTION_DATA_ABORT  4
+#define ARM_EXCEPTION_IRQ         5
+#define ARM_EXCEPTION_FIQ         6
+#define ARM_EXCEPTION_HVC         7
+#ifndef __ASSEMBLY__
+struct kvm;
+struct kvm_vcpu;
+extern char __kvm_hyp_init[];
+extern char __kvm_hyp_init_end[];
+extern char __kvm_hyp_exit[];
+extern char __kvm_hyp_exit_end[];
+extern char __kvm_hyp_vector[];
+extern char __kvm_hyp_code_start[];
+extern char __kvm_hyp_code_end[];
+extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
+extern void __kvm_flush_vm_context(void);
+extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
+extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+#endif
+#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h
new file mode 100644
index 000000000000..4917c2f7e459
--- /dev/null
+++ b/arch/arm/include/asm/kvm_coproc.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Rusty Russell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_COPROC_H__
+#define __ARM_KVM_COPROC_H__
+#include <linux/kvm_host.h>
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
+struct kvm_coproc_target_table {
+        unsigned target;
+        const struct coproc_reg *table;
+        size_t num;
+};
+void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table);
+int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
+unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+void kvm_coproc_table_init(void);
+struct kvm_one_reg;
+int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
+#endif /* __ARM_KVM_COPROC_H__ */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
new file mode 100644
index 000000000000..fd611996bfb5
--- /dev/null
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_EMULATE_H__
+#define __ARM_KVM_EMULATE_H__
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu);
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
+void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
+void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
+static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
+{
+        return 1;
+}
+static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
+{
+        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc;
+}
+static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu)
+{
+        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr;
+}
+static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
+{
+        *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+}
+static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
+        return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
+}
+static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
+        return cpsr_mode > USR_MODE;;
+}
+static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
+{
+        return reg == 15;
+}
+#endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
new file mode 100644
index 000000000000..d1736a53b12d
--- /dev/null
+++ b/arch/arm/include/asm/kvm_host.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_HOST_H__
+#define __ARM_KVM_HOST_H__
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+#include <asm/fpstate.h>
+#include <asm/kvm_arch_timer.h>
+#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#define KVM_USER_MEM_SLOTS 32
+#define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+#define KVM_HAVE_ONE_REG
+#define KVM_VCPU_MAX_FEATURES 1
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)  0
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
+#include <asm/kvm_vgic.h>
+struct kvm_vcpu;
+u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
+struct kvm_arch {
+        /* VTTBR value associated with below pgd and vmid */
+        u64    vttbr;
+        /* Timer */
+        struct arch_timer_kvm   timer;
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* The VMID generation used for the virt. memory system */
+        u64    vmid_gen;
+        u32    vmid;
+        /* Stage-2 page table */
+        pgd_t *pgd;
+        /* Interrupt controller */
+        struct vgic_dist        vgic;
+};
+#define KVM_NR_MEM_OBJS     40
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+        int nobjs;
+        void *objects[KVM_NR_MEM_OBJS];
+};
+struct kvm_vcpu_arch {
+        struct kvm_regs regs;
+        int target; /* Processor target */
+        DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
+        /* System control coprocessor (cp15) */
+        u32 cp15[NR_CP15_REGS];
+        /* The CPU type we expose to the VM */
+        u32 midr;
+        /* Exception Information */
+        u32 hsr;                /* Hyp Syndrome Register */
+        u32 hxfar;              /* Hyp Data/Inst Fault Address Register */
+        u32 hpfar;              /* Hyp IPA Fault Address Register */
+        /* Floating point registers (VFP and Advanced SIMD/NEON) */
+        struct vfp_hard_struct vfp_guest;
+        struct vfp_hard_struct *vfp_host;
+        /* VGIC state */
+        struct vgic_cpu vgic_cpu;
+        struct arch_timer_cpu timer_cpu;
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* dcache set/way operation pending */
+        int last_pcpu;
+        cpumask_t require_dcache_flush;
+        /* Don't run the guest on this vcpu */
+        bool pause;
+        /* IO related fields */
+        struct kvm_decode mmio_decode;
+        /* Interrupt related fields */
+        u32 irq_lines;          /* IRQ and FIQ levels */
+        /* Hyp exception information */
+        u32 hyp_pc;             /* PC when exception was taken from Hyp mode */
+        /* Cache some mmu pages needed inside spinlock regions */
+        struct kvm_mmu_memory_cache mmu_page_cache;
+        /* Detect first run of a vcpu */
+        bool has_run_once;
+};
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+struct kvm_vcpu_stat {
+        u32 halt_wakeup;
+};
+struct kvm_vcpu_init;
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+struct kvm_one_reg;
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+u64 kvm_call_hyp(void *hypfn, ...);
+void force_vm_exit(const cpumask_t *mask);
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+struct kvm;
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+/* We do not have shadow page tables, hence the empty hooks */
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
+struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
+int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
+struct kvm_one_reg;
+int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h
new file mode 100644
index 000000000000..adcc0d7d3175
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmio.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_MMIO_H__
+#define __ARM_KVM_MMIO_H__
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+struct kvm_decode {
+        unsigned long rt;
+        bool sign_extend;
+};
+/*
+ * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
+ * which is an anonymous type. Use our own type instead.
+ */
+struct kvm_exit_mmio {
+        phys_addr_t     phys_addr;
+        u8              data[8];
+        u32             len;
+        bool            is_write;
+};
+static inline void kvm_prepare_mmio(struct kvm_run *run,
+                                    struct kvm_exit_mmio *mmio)
+{
+        run->mmio.phys_addr     = mmio->phys_addr;
+        run->mmio.len           = mmio->len;
+        run->mmio.is_write      = mmio->is_write;
+        memcpy(run->mmio.data, mmio->data, mmio->len);
+        run->exit_reason        = KVM_EXIT_MMIO;
+}
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa);
+#endif  /* __ARM_KVM_MMIO_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
new file mode 100644
index 000000000000..421a20b34874
--- /dev/null
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_MMU_H__
+#define __ARM_KVM_MMU_H__
+int create_hyp_mappings(void *from, void *to);
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+void free_hyp_pmds(void);
+int kvm_alloc_stage2_pgd(struct kvm *kvm);
+void kvm_free_stage2_pgd(struct kvm *kvm);
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size);
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+phys_addr_t kvm_mmu_get_httbr(void);
+int kvm_mmu_init(void);
+void kvm_clear_hyp_idmap(void);
+static inline bool kvm_is_write_fault(unsigned long hsr)
+{
+        unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
+        if (hsr_ec == HSR_EC_IABT)
+                return false;
+        else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
+                return false;
+        else
+                return true;
+}
+#endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h
new file mode 100644
index 000000000000..9a83d98bf170
--- /dev/null
+++ b/arch/arm/include/asm/kvm_psci.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ARM_KVM_PSCI_H__
+#define __ARM_KVM_PSCI_H__
+bool kvm_psci_call(struct kvm_vcpu *vcpu);
+#endif /* __ARM_KVM_PSCI_H__ */
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
new file mode 100644
index 000000000000..ab97207d9cd3
--- /dev/null
+++ b/arch/arm/include/asm/kvm_vgic.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_KVM_VGIC_H
+#define __ASM_ARM_KVM_VGIC_H
+#include <linux/kernel.h>
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <linux/irqreturn.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/irqchip/arm-gic.h>
+#define VGIC_NR_IRQS            128
+#define VGIC_NR_SGIS            16
+#define VGIC_NR_PPIS            16
+#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
+#define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
+#define VGIC_MAX_CPUS           KVM_MAX_VCPUS
+#define VGIC_MAX_LRS            (1 << 6)
+/* Sanity checks... */
+#if (VGIC_MAX_CPUS > 8)
+#error  Invalid number of CPU interfaces
+#endif
+#if (VGIC_NR_IRQS & 31)
+#error "VGIC_NR_IRQS must be a multiple of 32"
+#endif
+#if (VGIC_NR_IRQS > 1024)
+#error "VGIC_NR_IRQS must be <= 1024"
+#endif
+/*
+ * The GIC distributor registers describing interrupts have two parts:
+ * - 32 per-CPU interrupts (SGI + PPI)
+ * - a bunch of shared interrupts (SPI)
+ */
+struct vgic_bitmap {
+        union {
+                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
+                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
+        } percpu[VGIC_MAX_CPUS];
+        union {
+                u32 reg[VGIC_NR_SHARED_IRQS / 32];
+                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
+        } shared;
+};
+struct vgic_bytemap {
+        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
+        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
+};
+struct vgic_dist {
+#ifdef CONFIG_KVM_ARM_VGIC
+        spinlock_t              lock;
+        bool                    ready;
+        /* Virtual control interface mapping */
+        void __iomem            *vctrl_base;
+        /* Distributor and vcpu interface mapping in the guest */
+        phys_addr_t             vgic_dist_base;
+        phys_addr_t             vgic_cpu_base;
+        /* Distributor enabled */
+        u32                     enabled;
+        /* Interrupt enabled (one bit per IRQ) */
+        struct vgic_bitmap      irq_enabled;
+        /* Interrupt 'pin' level */
+        struct vgic_bitmap      irq_state;
+        /* Level-triggered interrupt in progress */
+        struct vgic_bitmap      irq_active;
+        /* Interrupt priority. Not used yet. */
+        struct vgic_bytemap     irq_priority;
+        /* Level/edge triggered */
+        struct vgic_bitmap      irq_cfg;
+        /* Source CPU per SGI and target CPU */
+        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
+        /* Target CPU for each IRQ */
+        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
+        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
+        /* Bitmap indicating which CPU has something pending */
+        unsigned long           irq_pending_on_cpu;
+#endif
+};
+struct vgic_cpu {
+#ifdef CONFIG_KVM_ARM_VGIC
+        /* per IRQ to LR mapping */
+        u8              vgic_irq_lr_map[VGIC_NR_IRQS];
+        /* Pending interrupts on this VCPU */
+        DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
+        DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
+        /* Bitmap of used/free list registers */
+        DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
+        /* Number of list registers on this CPU */
+        int             nr_lr;
+        /* CPU vif control registers for world switch */
+        u32             vgic_hcr;
+        u32             vgic_vmcr;
+        u32             vgic_misr;      /* Saved only */
+        u32             vgic_eisr[2];   /* Saved only */
+        u32             vgic_elrsr[2];  /* Saved only */
+        u32             vgic_apr;
+        u32             vgic_lr[VGIC_MAX_LRS];
+#endif
+};
+#define LR_EMPTY        0xff
+struct kvm;
+struct kvm_vcpu;
+struct kvm_run;
+struct kvm_exit_mmio;
+#ifdef CONFIG_KVM_ARM_VGIC
+int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
+int kvm_vgic_hyp_init(void);
+int kvm_vgic_init(struct kvm *kvm);
+int kvm_vgic_create(struct kvm *kvm);
+int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
+int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
+                        bool level);
+int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
+bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                      struct kvm_exit_mmio *mmio);
+#define irqchip_in_kernel(k)    (!!((k)->arch.vgic.vctrl_base))
+#define vgic_initialized(k)     ((k)->arch.vgic.ready)
+#else
+static inline int kvm_vgic_hyp_init(void)
+{
+        return 0;
+}
+static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
+{
+        return 0;
+}
+static inline int kvm_vgic_init(struct kvm *kvm)
+{
+        return 0;
+}
+static inline int kvm_vgic_create(struct kvm *kvm)
+{
+        return 0;
+}
+static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
+static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
+static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
+                                      unsigned int irq_num, bool level)
+{
+        return 0;
+}
+static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                                    struct kvm_exit_mmio *mmio)
+{
+        return false;
+}
+static inline int irqchip_in_kernel(struct kvm *kvm)
+{
+        return 0;
+}
+static inline bool vgic_initialized(struct kvm *kvm)
+{
+        return true;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 917d4fcfd9b4..308ad7d6f98b 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -12,7 +12,6 @@
 struct tag;
 struct meminfo;
-struct sys_timer;
 struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
@@ -48,7 +47,7 @@ struct machine_desc {
        void                    (*map_io)(void);/* IO mapping function  */
        void                    (*init_early)(void);
        void                    (*init_irq)(void);
-        struct sys_timer        *timer;         /* system tick timer    */
+        void                    (*init_time)(void);
        void                    (*init_machine)(void);
        void                    (*init_late)(void);
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 15cb035309f7..18c883023339 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -22,6 +22,7 @@ extern int show_fiq_list(struct seq_file *, int);
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
 #endif
 /*
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index db9fedb57f2c..5cf2e979b4be 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -23,6 +23,7 @@ struct hw_pci {
 #endif
        struct pci_ops  *ops;
        int             nr_controllers;
+        void            **private_data;
        int             (*setup)(int nr, struct pci_sys_data *);
        struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
        void            (*preinit)(void);
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index 6ca945f534ab..90c12e1e695c 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -10,36 +10,6 @@
 #ifndef __ASM_ARM_MACH_TIME_H
 #define __ASM_ARM_MACH_TIME_H
-/*
- * This is our kernel timer structure.
- *
- * - init
- *   Initialise the kernels jiffy timer source, claim interrupt
- *   using setup_irq.  This is called early on during initialisation
- *   while interrupts are still disabled on the local CPU.
- * - suspend
- *   Suspend the kernel jiffy timer source, if necessary.  This
- *   is called with interrupts disabled, after all normal devices
- *   have been suspended.  If no action is required, set this to
- *   NULL.
- * - resume
- *   Resume the kernel jiffy timer source, if necessary.  This
- *   is called with interrupts disabled before any normal devices
- *   are resumed.  If no action is required, set this to NULL.
- * - offset
- *   Return the timer offset in microseconds since the last timer
- *   interrupt.  Note: this must take account of any unprocessed
- *   timer interrupt which may be pending.
- */
-struct sys_timer {
-        void                    (*init)(void);
-        void                    (*suspend)(void);
-        void                    (*resume)(void);
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-        unsigned long           (*offset)(void);
-#endif
-};
 extern void timer_tick(void);
 struct timespec;
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 73cf03aa981e..57870ab313c5 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -36,23 +36,23 @@
 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
 */
 #define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
-#define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
+#define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
-#define TASK_UNMAPPED_BASE      (UL(CONFIG_PAGE_OFFSET) / 3)
+#define TASK_UNMAPPED_BASE      ALIGN(TASK_SIZE / 3, SZ_16M)
 /*
 * The maximum size of a 26-bit user space task.
 */
-#define TASK_SIZE_26            UL(0x04000000)
+#define TASK_SIZE_26            (UL(1) << 26)
 /*
 * The module space lives between the addresses given by TASK_SIZE
 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
 */
 #ifndef CONFIG_THUMB2_KERNEL
-#define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
+#define MODULES_VADDR           (PAGE_OFFSET - SZ_16M)
 #else
 /* smaller range for Thumb-2 symbols relocation (2^24)*/
-#define MODULES_VADDR           (PAGE_OFFSET - 8*1024*1024)
+#define MODULES_VADDR           (PAGE_OFFSET - SZ_8M)
 #endif
 #if TASK_SIZE > MODULES_VADDR
@@ -245,6 +245,7 @@ static inline void *phys_to_virt(phys_addr_t x)
 #define __bus_to_pfn(x) __phys_to_pfn(x)
 #endif
+#ifdef CONFIG_VIRT_TO_BUS
 static inline __deprecated unsigned long virt_to_bus(void *x)
 {
        return __virt_to_bus((unsigned long)x);
@@ -254,6 +255,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 {
        return (void *)__bus_to_virt(x);
 }
+#endif
 /*
 * Conversion between a struct page and a physical address.
diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h
new file mode 100644
index 000000000000..bc3a9174417c
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-sec.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+#ifndef __ASM_ARM_OPCODES_SEC_H
+#define __ASM_ARM_OPCODES_SEC_H
+#include <asm/opcodes.h>
+#define __SMC(imm4) __inst_arm_thumb32(                                 \
+        0xE1600070 | (((imm4) & 0xF) << 0),                             \
+        0xF7F08000 | (((imm4) & 0xF) << 16)                             \
+)
+#endif /* __ASM_ARM_OPCODES_SEC_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 74e211a6fb24..e796c598513b 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -10,6 +10,7 @@
 #define __ASM_ARM_OPCODES_H
 #ifndef __ASSEMBLY__
+#include <linux/linkage.h>
 extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 #endif
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 53426c66352a..12f71a190422 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -92,6 +92,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
 static inline void outer_flush_all(void) { }
 static inline void outer_inv_all(void) { }
 static inline void outer_disable(void) { }
+static inline void outer_resume(void) { }
 #endif
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d7952824c5c4..18f5cef82ad5 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -32,6 +32,9 @@
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
 #define PMD_BIT4                (_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
+#define PMD_APTABLE_SHIFT       (61)
+#define PMD_APTABLE             (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
+#define PMD_PXNTABLE            (_AT(pgdval_t, 1) << 59)
 /*
 *   - section
@@ -41,9 +44,11 @@
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
+#define PMD_SECT_PXN            (_AT(pmdval_t, 1) << 53)
 #define PMD_SECT_XN             (_AT(pmdval_t, 1) << 54)
 #define PMD_SECT_AP_WRITE       (_AT(pmdval_t, 0))
 #define PMD_SECT_AP_READ        (_AT(pmdval_t, 0))
+#define PMD_SECT_AP1            (_AT(pmdval_t, 1) << 6)
 #define PMD_SECT_TEX(x)         (_AT(pmdval_t, 0))
 /*
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index a3f37929940a..6ef8afd1b64c 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -104,11 +104,29 @@
 */
 #define L_PGD_SWAPPER           (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
+/*
+ * 2nd stage PTE definitions for LPAE.
+ */
+#define L_PTE_S2_MT_UNCACHED     (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_MT_WRITEBACK    (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
+#define L_PTE_S2_RDONLY          (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_RDWR            (_AT(pteval_t, 2) << 6)   /* HAP[2:1] */
+/*
+ * Hyp-mode PL2 PTE definitions for LPAE.
+ */
+#define L_PTE_HYP               L_PTE_USER
 #ifndef __ASSEMBLY__
 #define pud_none(pud)           (!pud_val(pud))
 #define pud_bad(pud)            (!(pud_val(pud) & 2))
 #define pud_present(pud)        (pud_val(pud))
+#define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                                 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                                 PMD_TYPE_SECT)
 #define pud_clear(pudp)                 \
        do {                            \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9c82f988c0e3..80d6fc4dbe4a 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
 extern pgprot_t         pgprot_user;
 extern pgprot_t         pgprot_kernel;
+extern pgprot_t         pgprot_hyp_device;
+extern pgprot_t         pgprot_s2;
+extern pgprot_t         pgprot_s2_device;
 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
@@ -82,6 +85,10 @@ extern pgprot_t		pgprot_kernel;
 #define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
 #define PAGE_KERNEL             _MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC        pgprot_kernel
+#define PAGE_HYP                _MOD_PROT(pgprot_kernel, L_PTE_HYP)
+#define PAGE_HYP_DEVICE         _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
+#define PAGE_S2                 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE          _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
 #define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
@@ -240,7 +247,8 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | L_PTE_NONE;
+        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
+                L_PTE_NONE | L_PTE_VALID;
        pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
        return pte;
 }
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
new file mode 100644
index 000000000000..ce0dbe7c1625
--- /dev/null
+++ b/arch/arm/include/asm/psci.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+#ifndef __ASM_ARM_PSCI_H
+#define __ASM_ARM_PSCI_H
+#define PSCI_POWER_STATE_TYPE_STANDBY           0
+#define PSCI_POWER_STATE_TYPE_POWER_DOWN        1
+struct psci_power_state {
+        u16     id;
+        u8      type;
+        u8      affinity_level;
+};
+struct psci_operations {
+        int (*cpu_suspend)(struct psci_power_state state,
+                           unsigned long entry_point);
+        int (*cpu_off)(struct psci_power_state state);
+        int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
+        int (*migrate)(unsigned long cpuid);
+};
+extern struct psci_operations psci_ops;
+#endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h
index 9a0ea6ab988f..c0eb412aff04 100644
--- a/arch/arm/include/asm/signal.h
+++ b/arch/arm/include/asm/signal.h
@@ -16,23 +16,7 @@ typedef struct {
        unsigned long sig[_NSIG_WORDS];
 } sigset_t;
-struct old_sigaction {
+#define __ARCH_HAS_SA_RESTORER
-        __sighandler_t sa_handler;
-        old_sigset_t sa_mask;
-        unsigned long sa_flags;
-        __sigrestore_t sa_restorer;
-};
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        __sigrestore_t sa_restorer;
-        sigset_t sa_mask;               /* mask last for extensibility */
-};
-struct k_sigaction {
-        struct sigaction sa;
-};
 #include <asm/sigcontext.h>
 #endif
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d005ffaa..18d169373612 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -6,9 +6,32 @@
 #define SCU_PM_POWEROFF 3
 #ifndef __ASSEMBLER__
+#include <asm/cputype.h>
+static inline bool scu_a9_has_base(void)
+{
+        return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
+}
+static inline unsigned long scu_a9_get_base(void)
+{
+        unsigned long pa;
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
+        return pa;
+}
 unsigned int scu_get_core_count(void __iomem *);
-void scu_enable(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+#ifdef CONFIG_SMP
+void scu_enable(void __iomem *scu_base);
+#else
+static inline void scu_enable(void __iomem *scu_base) {}
+#endif
 #endif
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index b4ca707d0a69..6220e9fdf4c7 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
-        unsigned long tmp;
-        u32 slock;
        smp_mb();
+        lock->tickets.owner++;
-        __asm__ __volatile__(
-"       mov     %1, #1\n"
-"1:     ldrex   %0, [%2]\n"
-"       uadd16  %0, %0, %1\n"
-"       strex   %1, %0, [%2]\n"
-"       teq     %1, #0\n"
-"       bne     1b"
-        : "=&r" (slock), "=&r" (tmp)
-        : "r" (&lock->slock)
-        : "cc");
        dsb_sev();
 }
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 21a2700d2957..e4ddfb39ca34 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -26,8 +26,6 @@
 #define __ARCH_WANT_SYS_NICE
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 #define __ARCH_WANT_SYS_OLD_MMAP
 #define __ARCH_WANT_SYS_OLD_SELECT
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 86164df86cb4..50af92bac737 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -24,9 +24,9 @@
 /*
 * Flag indicating that the kernel was not entered in the same mode on every
 * CPU.  The zImage loader stashes this value in an SPSR, so we need an
- * architecturally defined flag bit here (the N flag, as it happens)
+ * architecturally defined flag bit here.
 */
-#define BOOT_CPU_MODE_MISMATCH (1<<31)
+#define BOOT_CPU_MODE_MISMATCH  PSR_N_BIT
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
index 94b4e9020b02..5c27696de14f 100644
--- a/arch/arm/include/asm/xen/events.h
+++ b/arch/arm/include/asm/xen/events.h
@@ -15,4 +15,26 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
        return raw_irqs_disabled_flags(regs->ARM_cpsr);
 }
+/*
+ * We cannot use xchg because it does not support 8-byte
+ * values. However it is safe to use {ldr,dtd}exd directly because all
+ * platforms which Xen can run on support those instructions.
+ */
+static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
+{
+        xen_ulong_t oldval;
+        unsigned int tmp;
+        wmb();
+        asm volatile("@ xchg_xen_ulong\n"
+                "1:     ldrexd  %0, %H0, [%3]\n"
+                "       strexd  %1, %2, %H2, [%3]\n"
+                "       teq     %1, #0\n"
+                "       bne     1b"
+                : "=&r" (oldval), "=&r" (tmp)
+                : "r" (val), "r" (ptr)
+                : "memory", "cc");
+        return oldval;
+}
 #endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index c6b9096cef95..30cdacb675af 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,6 +1,7 @@
 #ifndef _ASM_ARM_XEN_PAGE_H
 #define _ASM_ARM_XEN_PAGE_H
+#include <asm/mach/map.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -86,4 +87,7 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
 {
        return __set_phys_to_machine(pfn, mfn);
 }
+#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
new file mode 100644
index 000000000000..91d38e38a0b4
--- /dev/null
+++ b/arch/arm/include/debug/imx-uart.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DEBUG_IMX_UART_H
+#define __DEBUG_IMX_UART_H
+#define IMX1_UART1_BASE_ADDR    0x00206000
+#define IMX1_UART2_BASE_ADDR    0x00207000
+#define IMX1_UART_BASE_ADDR(n)  IMX1_UART##n##_BASE_ADDR
+#define IMX1_UART_BASE(n)       IMX1_UART_BASE_ADDR(n)
+#define IMX21_UART1_BASE_ADDR   0x1000a000
+#define IMX21_UART2_BASE_ADDR   0x1000b000
+#define IMX21_UART3_BASE_ADDR   0x1000c000
+#define IMX21_UART4_BASE_ADDR   0x1000d000
+#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
+#define IMX21_UART_BASE(n)      IMX21_UART_BASE_ADDR(n)
+#define IMX25_UART1_BASE_ADDR   0x43f90000
+#define IMX25_UART2_BASE_ADDR   0x43f94000
+#define IMX25_UART3_BASE_ADDR   0x5000c000
+#define IMX25_UART4_BASE_ADDR   0x50008000
+#define IMX25_UART5_BASE_ADDR   0x5002c000
+#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
+#define IMX25_UART_BASE(n)      IMX25_UART_BASE_ADDR(n)
+#define IMX31_UART1_BASE_ADDR   0x43f90000
+#define IMX31_UART2_BASE_ADDR   0x43f94000
+#define IMX31_UART3_BASE_ADDR   0x5000c000
+#define IMX31_UART4_BASE_ADDR   0x43fb0000
+#define IMX31_UART5_BASE_ADDR   0x43fb4000
+#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
+#define IMX31_UART_BASE(n)      IMX31_UART_BASE_ADDR(n)
+#define IMX35_UART1_BASE_ADDR   0x43f90000
+#define IMX35_UART2_BASE_ADDR   0x43f94000
+#define IMX35_UART3_BASE_ADDR   0x5000c000
+#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
+#define IMX35_UART_BASE(n)      IMX35_UART_BASE_ADDR(n)
+#define IMX51_UART1_BASE_ADDR   0x73fbc000
+#define IMX51_UART2_BASE_ADDR   0x73fc0000
+#define IMX51_UART3_BASE_ADDR   0x7000c000
+#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
+#define IMX51_UART_BASE(n)      IMX51_UART_BASE_ADDR(n)
+#define IMX53_UART1_BASE_ADDR   0x53fbc000
+#define IMX53_UART2_BASE_ADDR   0x53fc0000
+#define IMX53_UART3_BASE_ADDR   0x5000c000
+#define IMX53_UART4_BASE_ADDR   0x53ff0000
+#define IMX53_UART5_BASE_ADDR   0x63f90000
+#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
+#define IMX53_UART_BASE(n)      IMX53_UART_BASE_ADDR(n)
+#define IMX6Q_UART1_BASE_ADDR   0x02020000
+#define IMX6Q_UART2_BASE_ADDR   0x021e8000
+#define IMX6Q_UART3_BASE_ADDR   0x021ec000
+#define IMX6Q_UART4_BASE_ADDR   0x021f0000
+#define IMX6Q_UART5_BASE_ADDR   0x021f4000
+#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
+#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
+#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
+#ifdef CONFIG_DEBUG_IMX1_UART
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX1)
+#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX21)
+#elif defined(CONFIG_DEBUG_IMX25_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX25)
+#elif defined(CONFIG_DEBUG_IMX31_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX31)
+#elif defined(CONFIG_DEBUG_IMX35_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX35)
+#elif defined(CONFIG_DEBUG_IMX51_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX51)
+#elif defined(CONFIG_DEBUG_IMX53_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX53)
+#elif defined(CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6Q)
+#endif
+#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index 0c4e17d4d359..619d8cc1ac12 100644
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -10,35 +10,8 @@
 * published by the Free Software Foundation.
 *
 */
-#define IMX6Q_UART1_BASE_ADDR   0x02020000
-#define IMX6Q_UART2_BASE_ADDR   0x021e8000
-#define IMX6Q_UART3_BASE_ADDR   0x021ec000
-#define IMX6Q_UART4_BASE_ADDR   0x021f0000
-#define IMX6Q_UART5_BASE_ADDR   0x021f4000
-/*
+#include "imx-uart.h"
- * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
- * of IMX6Q_UART##n##_BASE_ADDR.
- */
-#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
-#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
-#define IMX6Q_DEBUG_UART_BASE   IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
-#ifdef CONFIG_DEBUG_IMX1_UART
-#define UART_PADDR      0x00206000
-#elif defined (CONFIG_DEBUG_IMX25_UART)
-#define UART_PADDR      0x43f90000
-#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
-#define UART_PADDR      0x1000a000
-#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
-#define UART_PADDR      0x43f90000
-#elif defined (CONFIG_DEBUG_IMX51_UART)
-#define UART_PADDR      0x73fbc000
-#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
-#define UART_PADDR      0x53fbc000
-#elif defined (CONFIG_DEBUG_IMX6Q_UART)
-#define UART_PADDR      IMX6Q_DEBUG_UART_BASE
-#endif
 /*
 * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/include/debug/omap2plus.S
index cfaed13d0040..6d867aef18eb 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/omap2plus.S
@@ -1,5 +1,4 @@
-/* arch/arm/mach-omap2/include/mach/debug-macro.S
+/*
- *
 * Debugging macro include header
 *
 *  Copyright (C) 1994-1999 Russell King
@@ -13,7 +12,49 @@
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
+/* OMAP2 serial ports */
+#define OMAP2_UART1_BASE        0x4806a000
+#define OMAP2_UART2_BASE        0x4806c000
+#define OMAP2_UART3_BASE        0x4806e000
+/* OMAP3 serial ports */
+#define OMAP3_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP3_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP3_UART3_BASE        0x49020000
+#define OMAP3_UART4_BASE        0x49042000      /* Only on 36xx */
+#define OMAP3_UART4_AM35XX_BASE 0x4809E000      /* Only on AM35xx */
+/* OMAP4 serial ports */
+#define OMAP4_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP4_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP4_UART3_BASE        0x48020000
+#define OMAP4_UART4_BASE        0x4806e000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE       0x48020000
+#define TI81XX_UART2_BASE       0x48022000
+#define TI81XX_UART3_BASE       0x48024000
+/* AM3505/3517 UART4 */
+#define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE       0x44E09000
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE        OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE        OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE        0x48066000
+#define OMAP5_UART6_BASE        0x48068000
+/* External port on Zoom2/3 */
+#define ZOOM_UART_BASE          0x10000000
+#define ZOOM_UART_VIRT          0xfa400000
+#define OMAP_PORT_SHIFT         2
+#define ZOOM_PORT_SHIFT         1
 #define UART_OFFSET(addr)       ((addr) & 0x00ffffff)
@@ -23,12 +64,6 @@ omap_uart_virt:	.word	0
 omap_uart_lsr:  .word   0
                .popsection
-                /*
-                 * Note that this code won't work if the bootloader passes
-                 * a wrong machine ID number in r1. To debug, just hardcode
-                 * the desired UART phys and virt addresses temporarily into
-                 * the omap_uart_phys and omap_uart_virt above.
-                 */
                .macro  addruart, rp, rv, tmp
                /* Use omap_uart_phys/virt if already configured */
@@ -43,74 +78,64 @@ omap_uart_lsr:	.word	0
                cmpne   \rv, #0
                bne     100f                    @ already configured
-                /* Check the debug UART configuration set in uncompress.h */
-                mov     \rp, pc
-                ldr     \rv, =OMAP_UART_INFO_OFS
-                and     \rp, \rp, #0xff000000
-                ldr     \rp, [\rp, \rv]
-                /* Select the UART to use based on the UART1 scratchpad value */
-                cmp     \rp, #0                 @ no port configured?
-                beq     21f                     @ if none, try to use UART1
-                cmp     \rp, #OMAP2UART1        @ OMAP2/3/4UART1
-                beq     21f                     @ configure OMAP2/3/4UART1
-                cmp     \rp, #OMAP2UART2        @ OMAP2/3/4UART2
-                beq     22f                     @ configure OMAP2/3/4UART2
-                cmp     \rp, #OMAP2UART3        @ only on 24xx
-                beq     23f                     @ configure OMAP2UART3
-                cmp     \rp, #OMAP3UART3        @ only on 34xx
-                beq     33f                     @ configure OMAP3UART3
-                cmp     \rp, #OMAP4UART3        @ only on 44xx/54xx
-                beq     43f                     @ configure OMAP4/5UART3
-                cmp     \rp, #OMAP3UART4        @ only on 36xx
-                beq     34f                     @ configure OMAP3UART4
-                cmp     \rp, #OMAP4UART4        @ only on 44xx/54xx
-                beq     44f                     @ configure OMAP4/5UART4
-                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
-                beq     81f                     @ configure UART1
-                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
-                beq     82f                     @ configure UART2
-                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
-                beq     83f                     @ configure UART3
-                cmp     \rp, #AM33XXUART1       @ AM33XX UART offsets different
-                beq     84f                     @ configure UART1
-                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
-                beq     95f                     @ configure ZOOM_UART
                /* Configure the UART offset from the phys/virt base */
-21:             mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
+#ifdef CONFIG_DEBUG_OMAP2UART1
+                mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
                b       98f
-22:             mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART2
+                mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
                b       98f
-23:             mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP2UART3
+                mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
                b       98f
-33:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART3
+                mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
                add     \rp, \rp, #0x00fb0000
                add     \rp, \rp, #0x00006000           @ OMAP3_UART3_BASE
                b       98f
-34:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_OMAP4UART3
+                mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
+                b       98f
+#endif
+#ifdef CONFIG_DEBUG_OMAP3UART4
+                mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
                add     \rp, \rp, #0x00fb0000
                add     \rp, \rp, #0x00028000           @ OMAP3_UART4_BASE
                b       98f
-43:             mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
+#endif
-                b       98f
+#ifdef CONFIG_DEBUG_OMAP4UART4
-44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
+                mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                b       98f
-81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART1
+                mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                b       98f
-82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART2
+                mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                b       98f
-83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
+#endif
+#ifdef CONFIG_DEBUG_TI81XXUART3
+                mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                b       98f
-84:             ldr     \rp, =AM33XX_UART1_BASE
+#endif
+#ifdef CONFIG_DEBUG_AM33XXUART1
+                ldr     \rp, =AM33XX_UART1_BASE
                and     \rp, \rp, #0x00ffffff
                b       97f
-95:             ldr     \rp, =ZOOM_UART_BASE
+#endif
+#ifdef CONFIG_DEBUG_ZOOM_UART
+                ldr     \rp, =ZOOM_UART_BASE
                str     \rp, [\tmp, #0]         @ omap_uart_phys
                ldr     \rp, =ZOOM_UART_VIRT
                str     \rp, [\tmp, #4]         @ omap_uart_virt
                mov     \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
                str     \rp, [\tmp, #8]         @ omap_uart_lsr
+#endif
                b       10b
                /* AM33XX: Store both phys and virt address for the uart */
diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/include/debug/vt8500.S
index ca292f29d4a3..0e0ca0869da7 100644
--- a/arch/arm/mach-vt8500/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/vt8500.S
@@ -1,20 +1,24 @@
-/*
+/* 
- * arch/arm/mach-vt8500/include/mach/debug-macro.S
+ * Debugging macro include header
 *
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
+ *    Moved from arch/arm/mach-vt8500/include/mach/debug-macro.S
- * Debugging macro include header
+ *    Minor changes for readability.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
- *
+ */
-*/
+#define DEBUG_LL_PHYS_BASE              0xD8000000
+#define DEBUG_LL_VIRT_BASE              0xF8000000
+#define DEBUG_LL_UART_OFFSET            0x00200000
+#if defined(CONFIG_DEBUG_VT8500_UART0)
        .macro  addruart, rp, rv, tmp
-        mov     \rp,      #0x00200000
+        mov     \rp,      #DEBUG_LL_UART_OFFSET
-        orr     \rv, \rp, #0xf8000000
+        orr     \rv, \rp, #DEBUG_LL_VIRT_BASE
-        orr     \rp, \rp, #0xd8000000
+        orr     \rp, \rp, #DEBUG_LL_PHYS_BASE
        .endm
        .macro  senduart,rd,rx
@@ -29,3 +33,5 @@
        .macro  waituart,rd,rx
        .endm
+#endif
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..023bfeb367bf
--- /dev/null
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+#define KVM_REG_SIZE(id)                                                \
+        (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
+#define KVM_ARM_SVC_sp          svc_regs[0]
+#define KVM_ARM_SVC_lr          svc_regs[1]
+#define KVM_ARM_SVC_spsr        svc_regs[2]
+#define KVM_ARM_ABT_sp          abt_regs[0]
+#define KVM_ARM_ABT_lr          abt_regs[1]
+#define KVM_ARM_ABT_spsr        abt_regs[2]
+#define KVM_ARM_UND_sp          und_regs[0]
+#define KVM_ARM_UND_lr          und_regs[1]
+#define KVM_ARM_UND_spsr        und_regs[2]
+#define KVM_ARM_IRQ_sp          irq_regs[0]
+#define KVM_ARM_IRQ_lr          irq_regs[1]
+#define KVM_ARM_IRQ_spsr        irq_regs[2]
+/* Valid only for fiq_regs in struct kvm_regs */
+#define KVM_ARM_FIQ_r8          fiq_regs[0]
+#define KVM_ARM_FIQ_r9          fiq_regs[1]
+#define KVM_ARM_FIQ_r10         fiq_regs[2]
+#define KVM_ARM_FIQ_fp          fiq_regs[3]
+#define KVM_ARM_FIQ_ip          fiq_regs[4]
+#define KVM_ARM_FIQ_sp          fiq_regs[5]
+#define KVM_ARM_FIQ_lr          fiq_regs[6]
+#define KVM_ARM_FIQ_spsr        fiq_regs[7]
+struct kvm_regs {
+        struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
+        __u32 svc_regs[3];      /* SP_svc, LR_svc, SPSR_svc */
+        __u32 abt_regs[3];      /* SP_abt, LR_abt, SPSR_abt */
+        __u32 und_regs[3];      /* SP_und, LR_und, SPSR_und */
+        __u32 irq_regs[3];      /* SP_irq, LR_irq, SPSR_irq */
+        __u32 fiq_regs[8];      /* R8_fiq - R14_fiq, SPSR_fiq */
+};
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_CORTEX_A15       0
+#define KVM_ARM_NUM_TARGETS             1
+/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
+#define KVM_ARM_DEVICE_TYPE_SHIFT       0
+#define KVM_ARM_DEVICE_TYPE_MASK        (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
+#define KVM_ARM_DEVICE_ID_SHIFT         16
+#define KVM_ARM_DEVICE_ID_MASK          (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
+/* Supported device IDs */
+#define KVM_ARM_DEVICE_VGIC_V2          0
+/* Supported VGIC address types  */
+#define KVM_VGIC_V2_ADDR_TYPE_DIST      0
+#define KVM_VGIC_V2_ADDR_TYPE_CPU       1
+#define KVM_VGIC_V2_DIST_SIZE           0x1000
+#define KVM_VGIC_V2_CPU_SIZE            0x2000
+#define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
+struct kvm_vcpu_init {
+        __u32 target;
+        __u32 features[7];
+};
+struct kvm_sregs {
+};
+struct kvm_fpu {
+};
+struct kvm_guest_debug_arch {
+};
+struct kvm_debug_exit_arch {
+};
+struct kvm_sync_regs {
+};
+struct kvm_arch_memory_slot {
+};
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT        16
+#define KVM_REG_ARM_32_OPC2_MASK        0x0000000000000007
+#define KVM_REG_ARM_32_OPC2_SHIFT       0
+#define KVM_REG_ARM_OPC1_MASK           0x0000000000000078
+#define KVM_REG_ARM_OPC1_SHIFT          3
+#define KVM_REG_ARM_CRM_MASK            0x0000000000000780
+#define KVM_REG_ARM_CRM_SHIFT           7
+#define KVM_REG_ARM_32_CRN_MASK         0x0000000000007800
+#define KVM_REG_ARM_32_CRN_SHIFT        11
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / 4)
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT      8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
+/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
+#define KVM_REG_ARM_VFP                 (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_VFP_MASK            0x000000000000FFFF
+#define KVM_REG_ARM_VFP_BASE_REG        0x0
+#define KVM_REG_ARM_VFP_FPSID           0x1000
+#define KVM_REG_ARM_VFP_FPSCR           0x1001
+#define KVM_REG_ARM_VFP_MVFR1           0x1006
+#define KVM_REG_ARM_VFP_MVFR0           0x1007
+#define KVM_REG_ARM_VFP_FPEXC           0x1008
+#define KVM_REG_ARM_VFP_FPINST          0x1009
+#define KVM_REG_ARM_VFP_FPINST2         0x100A
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT          24
+#define KVM_ARM_IRQ_TYPE_MASK           0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT          16
+#define KVM_ARM_IRQ_VCPU_MASK           0xff
+#define KVM_ARM_IRQ_NUM_SHIFT           0
+#define KVM_ARM_IRQ_NUM_MASK            0xffff
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU            0
+#define KVM_ARM_IRQ_TYPE_SPI            1
+#define KVM_ARM_IRQ_TYPE_PPI            2
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ             0
+#define KVM_ARM_IRQ_CPU_FIQ             1
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX             127
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE                0x95c1ba5e
+#define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
+#define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
+#define KVM_PSCI_RET_SUCCESS            0
+#define KVM_PSCI_RET_NI                 ((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL              ((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED             ((unsigned long)-3)
+#endif /* __ARM_KVM_H__ */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5bbec7b8183e..5f3338eacad2 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -82,5 +82,6 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
+obj-$(CONFIG_ARM_PSCI)          += psci.o
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index c8ef20747ee7..d957a51435d8 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -9,516 +9,53 @@
 * published by the Free Software Foundation.
 */
 #include <linux/init.h>
-#include <linux/kernel.h>
+#include <linux/types.h>
-#include <linux/delay.h>
+#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/smp.h>
-#include <linux/cpu.h>
-#include <linux/jiffies.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/of_irq.h>
-#include <linux/io.h>
-#include <asm/cputype.h>
 #include <asm/delay.h>
-#include <asm/localtimer.h>
-#include <asm/arch_timer.h>
-#include <asm/system_info.h>
 #include <asm/sched_clock.h>
-static unsigned long arch_timer_rate;
+#include <clocksource/arm_arch_timer.h>
-enum ppi_nr {
+static unsigned long arch_timer_read_counter_long(void)
-        PHYS_SECURE_PPI,
-        PHYS_NONSECURE_PPI,
-        VIRT_PPI,
-        HYP_PPI,
-        MAX_TIMER_PPI
-};
-static int arch_timer_ppi[MAX_TIMER_PPI];
-static struct clock_event_device __percpu **arch_timer_evt;
-static struct delay_timer arch_delay_timer;
-static bool arch_timer_use_virtual = true;
-/*
- * Architected system timer support.
- */
-#define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
-#define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
-#define ARCH_TIMER_CTRL_IT_STAT         (1 << 2)
-#define ARCH_TIMER_REG_CTRL             0
-#define ARCH_TIMER_REG_FREQ             1
-#define ARCH_TIMER_REG_TVAL             2
-#define ARCH_TIMER_PHYS_ACCESS          0
-#define ARCH_TIMER_VIRT_ACCESS          1
-/*
- * These register accessors are marked inline so the compiler can
- * nicely work out which register we want, and chuck away the rest of
- * the code. At least it does so with a recent GCC (4.6.3).
- */
-static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
-{
-        if (access == ARCH_TIMER_PHYS_ACCESS) {
-                switch (reg) {
-                case ARCH_TIMER_REG_CTRL:
-                        asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
-                        break;
-                case ARCH_TIMER_REG_TVAL:
-                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
-                        break;
-                }
-        }
-        if (access == ARCH_TIMER_VIRT_ACCESS) {
-                switch (reg) {
-                case ARCH_TIMER_REG_CTRL:
-                        asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
-                        break;
-                case ARCH_TIMER_REG_TVAL:
-                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
-                        break;
-                }
-        }
-        isb();
-}
-static inline u32 arch_timer_reg_read(const int access, const int reg)
-{
-        u32 val = 0;
-        if (access == ARCH_TIMER_PHYS_ACCESS) {
-                switch (reg) {
-                case ARCH_TIMER_REG_CTRL:
-                        asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
-                        break;
-                case ARCH_TIMER_REG_TVAL:
-                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
-                        break;
-                case ARCH_TIMER_REG_FREQ:
-                        asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-                        break;
-                }
-        }
-        if (access == ARCH_TIMER_VIRT_ACCESS) {
-                switch (reg) {
-                case ARCH_TIMER_REG_CTRL:
-                        asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
-                        break;
-                case ARCH_TIMER_REG_TVAL:
-                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
-                        break;
-                }
-        }
-        return val;
-}
-static inline cycle_t arch_timer_counter_read(const int access)
-{
-        cycle_t cval = 0;
-        if (access == ARCH_TIMER_PHYS_ACCESS)
-                asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-        if (access == ARCH_TIMER_VIRT_ACCESS)
-                asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
-        return cval;
-}
-static inline cycle_t arch_counter_get_cntpct(void)
-{
-        return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
-}
-static inline cycle_t arch_counter_get_cntvct(void)
-{
-        return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
-}
-static irqreturn_t inline timer_handler(const int access,
-                                        struct clock_event_device *evt)
-{
-        unsigned long ctrl;
-        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
-        if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
-                ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
-                evt->event_handler(evt);
-                return IRQ_HANDLED;
-        }
-        return IRQ_NONE;
-}
-static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
-}
-static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
-}
-static inline void timer_set_mode(const int access, int mode)
-{
-        unsigned long ctrl;
-        switch (mode) {
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
-                ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
-                break;
-        default:
-                break;
-        }
-}
-static void arch_timer_set_mode_virt(enum clock_event_mode mode,
-                                     struct clock_event_device *clk)
-{
-        timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
-}
-static void arch_timer_set_mode_phys(enum clock_event_mode mode,
-                                     struct clock_event_device *clk)
-{
-        timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
-}
-static inline void set_next_event(const int access, unsigned long evt)
-{
-        unsigned long ctrl;
-        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
-        ctrl |= ARCH_TIMER_CTRL_ENABLE;
-        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
-        arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
-        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
-}
-static int arch_timer_set_next_event_virt(unsigned long evt,
-                                          struct clock_event_device *unused)
-{
-        set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
-        return 0;
-}
-static int arch_timer_set_next_event_phys(unsigned long evt,
-                                          struct clock_event_device *unused)
-{
-        set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
-        return 0;
-}
-static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
-{
-        clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
-        clk->name = "arch_sys_timer";
-        clk->rating = 450;
-        if (arch_timer_use_virtual) {
-                clk->irq = arch_timer_ppi[VIRT_PPI];
-                clk->set_mode = arch_timer_set_mode_virt;
-                clk->set_next_event = arch_timer_set_next_event_virt;
-        } else {
-                clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
-                clk->set_mode = arch_timer_set_mode_phys;
-                clk->set_next_event = arch_timer_set_next_event_phys;
-        }
-        clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
-        clockevents_config_and_register(clk, arch_timer_rate,
-                                        0xf, 0x7fffffff);
-        *__this_cpu_ptr(arch_timer_evt) = clk;
-        if (arch_timer_use_virtual)
-                enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
-        else {
-                enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
-                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
-                        enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
-        }
-        return 0;
-}
-/* Is the optional system timer available? */
-static int local_timer_is_architected(void)
-{
-        return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
-               ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
-}
-static int arch_timer_available(void)
-{
-        unsigned long freq;
-        if (!local_timer_is_architected())
-                return -ENXIO;
-        if (arch_timer_rate == 0) {
-                freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
-                                           ARCH_TIMER_REG_FREQ);
-                /* Check the timer frequency. */
-                if (freq == 0) {
-                        pr_warn("Architected timer frequency not available\n");
-                        return -EINVAL;
-                }
-                arch_timer_rate = freq;
-        }
-        pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
-                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
-                     arch_timer_use_virtual ? "virt" : "phys");
-        return 0;
-}
-static u32 notrace arch_counter_get_cntpct32(void)
-{
-        cycle_t cnt = arch_counter_get_cntpct();
-        /*
-         * The sched_clock infrastructure only knows about counters
-         * with at most 32bits. Forget about the upper 24 bits for the
-         * time being...
-         */
-        return (u32)cnt;
-}
-static u32 notrace arch_counter_get_cntvct32(void)
-{
-        cycle_t cnt = arch_counter_get_cntvct();
-        /*
-         * The sched_clock infrastructure only knows about counters
-         * with at most 32bits. Forget about the upper 24 bits for the
-         * time being...
-         */
-        return (u32)cnt;
-}
-static cycle_t arch_counter_read(struct clocksource *cs)
-{
-        /*
-         * Always use the physical counter for the clocksource.
-         * CNTHCTL.PL1PCTEN must be set to 1.
-         */
-        return arch_counter_get_cntpct();
-}
-static unsigned long arch_timer_read_current_timer(void)
 {
-        return arch_counter_get_cntpct();
+        return arch_timer_read_counter();
 }
-static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+static u32 arch_timer_read_counter_u32(void)
 {
-        /*
+        return arch_timer_read_counter();
-         * Always use the physical counter for the clocksource.
-         * CNTHCTL.PL1PCTEN must be set to 1.
-         */
-        return arch_counter_get_cntpct();
 }
-static struct clocksource clocksource_counter = {
+static struct delay_timer arch_delay_timer;
-        .name   = "arch_sys_counter",
-        .rating = 400,
-        .read   = arch_counter_read,
-        .mask   = CLOCKSOURCE_MASK(56),
-        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-static struct cyclecounter cyclecounter = {
-        .read   = arch_counter_read_cc,
-        .mask   = CLOCKSOURCE_MASK(56),
-};
-static struct timecounter timecounter;
-struct timecounter *arch_timer_get_timecounter(void)
-{
-        return &timecounter;
-}
-static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
-{
-        pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
-                 clk->irq, smp_processor_id());
-        if (arch_timer_use_virtual)
-                disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
-        else {
-                disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
-                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
-                        disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
-        }
-        clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
-}
-static struct local_timer_ops arch_timer_ops __cpuinitdata = {
-        .setup  = arch_timer_setup,
-        .stop   = arch_timer_stop,
-};
-static struct clock_event_device arch_timer_global_evt;
-static int __init arch_timer_register(void)
+static void __init arch_timer_delay_timer_register(void)
 {
-        int err;
-        int ppi;
-        err = arch_timer_available();
-        if (err)
-                goto out;
-        arch_timer_evt = alloc_percpu(struct clock_event_device *);
-        if (!arch_timer_evt) {
-                err = -ENOMEM;
-                goto out;
-        }
-        clocksource_register_hz(&clocksource_counter, arch_timer_rate);
-        cyclecounter.mult = clocksource_counter.mult;
-        cyclecounter.shift = clocksource_counter.shift;
-        timecounter_init(&timecounter, &cyclecounter,
-                         arch_counter_get_cntpct());
-        if (arch_timer_use_virtual) {
-                ppi = arch_timer_ppi[VIRT_PPI];
-                err = request_percpu_irq(ppi, arch_timer_handler_virt,
-                                         "arch_timer", arch_timer_evt);
-        } else {
-                ppi = arch_timer_ppi[PHYS_SECURE_PPI];
-                err = request_percpu_irq(ppi, arch_timer_handler_phys,
-                                         "arch_timer", arch_timer_evt);
-                if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
-                        ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
-                        err = request_percpu_irq(ppi, arch_timer_handler_phys,
-                                                 "arch_timer", arch_timer_evt);
-                        if (err)
-                                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
-                                                arch_timer_evt);
-                }
-        }
-        if (err) {
-                pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                       ppi, err);
-                goto out_free;
-        }
-        err = local_timer_register(&arch_timer_ops);
-        if (err) {
-                /*
-                 * We couldn't register as a local timer (could be
-                 * because we're on a UP platform, or because some
-                 * other local timer is already present...). Try as a
-                 * global timer instead.
-                 */
-                arch_timer_global_evt.cpumask = cpumask_of(0);
-                err = arch_timer_setup(&arch_timer_global_evt);
-        }
-        if (err)
-                goto out_free_irq;
        /* Use the architected timer for the delay loop. */
-        arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+        arch_delay_timer.read_current_timer = arch_timer_read_counter_long;
-        arch_delay_timer.freq = arch_timer_rate;
+        arch_delay_timer.freq = arch_timer_get_rate();
        register_current_timer_delay(&arch_delay_timer);
-        return 0;
-out_free_irq:
-        if (arch_timer_use_virtual)
-                free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
-        else {
-                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
-                                arch_timer_evt);
-                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
-                        free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
-                                        arch_timer_evt);
-        }
-out_free:
-        free_percpu(arch_timer_evt);
-out:
-        return err;
 }
-static const struct of_device_id arch_timer_of_match[] __initconst = {
-        { .compatible   = "arm,armv7-timer",    },
-        {},
-};
 int __init arch_timer_of_register(void)
 {
-        struct device_node *np;
+        int ret;
-        u32 freq;
-        int i;
-        np = of_find_matching_node(NULL, arch_timer_of_match);
-        if (!np) {
-                pr_err("arch_timer: can't find DT node\n");
-                return -ENODEV;
-        }
-        /* Try to determine the frequency from the device tree or CNTFRQ */
-        if (!of_property_read_u32(np, "clock-frequency", &freq))
-                arch_timer_rate = freq;
-        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
-                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-        /*
+        ret = arch_timer_init();
-         * If no interrupt provided for virtual timer, we'll have to
+        if (ret)
-         * stick to the physical timer. It'd better be accessible...
+                return ret;
-         */
-        if (!arch_timer_ppi[VIRT_PPI]) {
-                arch_timer_use_virtual = false;
-                if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+        arch_timer_delay_timer_register();
-                    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
-                        pr_warn("arch_timer: No interrupt available, giving up\n");
-                        return -EINVAL;
-                }
-        }
-        return arch_timer_register();
+        return 0;
 }
 int __init arch_timer_sched_clock_init(void)
 {
-        u32 (*cnt32)(void);
+        if (arch_timer_get_rate() == 0)
-        int err;
+                return -ENXIO;
-        err = arch_timer_available();
-        if (err)
-                return err;
-        if (arch_timer_use_virtual)
-                cnt32 = arch_counter_get_cntvct32;
-        else
-                cnt32 = arch_counter_get_cntpct32;
-        setup_sched_clock(cnt32, 32, arch_timer_rate);
+        setup_sched_clock(arch_timer_read_counter_u32,
+                          32, arch_timer_get_rate());
        return 0;
 }
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index c985b481192c..5ce738b43508 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -13,6 +13,9 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#ifdef CONFIG_KVM_ARM_HOST
+#include <linux/kvm_host.h>
+#endif
 #include <asm/cacheflush.h>
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
@@ -146,5 +149,45 @@ int main(void)
  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
  DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
+#ifdef CONFIG_KVM_ARM_HOST
+  DEFINE(VCPU_KVM,              offsetof(struct kvm_vcpu, kvm));
+  DEFINE(VCPU_MIDR,             offsetof(struct kvm_vcpu, arch.midr));
+  DEFINE(VCPU_CP15,             offsetof(struct kvm_vcpu, arch.cp15));
+  DEFINE(VCPU_VFP_GUEST,        offsetof(struct kvm_vcpu, arch.vfp_guest));
+  DEFINE(VCPU_VFP_HOST,         offsetof(struct kvm_vcpu, arch.vfp_host));
+  DEFINE(VCPU_REGS,             offsetof(struct kvm_vcpu, arch.regs));
+  DEFINE(VCPU_USR_REGS,         offsetof(struct kvm_vcpu, arch.regs.usr_regs));
+  DEFINE(VCPU_SVC_REGS,         offsetof(struct kvm_vcpu, arch.regs.svc_regs));
+  DEFINE(VCPU_ABT_REGS,         offsetof(struct kvm_vcpu, arch.regs.abt_regs));
+  DEFINE(VCPU_UND_REGS,         offsetof(struct kvm_vcpu, arch.regs.und_regs));
+  DEFINE(VCPU_IRQ_REGS,         offsetof(struct kvm_vcpu, arch.regs.irq_regs));
+  DEFINE(VCPU_FIQ_REGS,         offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
+  DEFINE(VCPU_PC,               offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
+  DEFINE(VCPU_CPSR,             offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
+  DEFINE(VCPU_IRQ_LINES,        offsetof(struct kvm_vcpu, arch.irq_lines));
+  DEFINE(VCPU_HSR,              offsetof(struct kvm_vcpu, arch.hsr));
+  DEFINE(VCPU_HxFAR,            offsetof(struct kvm_vcpu, arch.hxfar));
+  DEFINE(VCPU_HPFAR,            offsetof(struct kvm_vcpu, arch.hpfar));
+  DEFINE(VCPU_HYP_PC,           offsetof(struct kvm_vcpu, arch.hyp_pc));
+#ifdef CONFIG_KVM_ARM_VGIC
+  DEFINE(VCPU_VGIC_CPU,         offsetof(struct kvm_vcpu, arch.vgic_cpu));
+  DEFINE(VGIC_CPU_HCR,          offsetof(struct vgic_cpu, vgic_hcr));
+  DEFINE(VGIC_CPU_VMCR,         offsetof(struct vgic_cpu, vgic_vmcr));
+  DEFINE(VGIC_CPU_MISR,         offsetof(struct vgic_cpu, vgic_misr));
+  DEFINE(VGIC_CPU_EISR,         offsetof(struct vgic_cpu, vgic_eisr));
+  DEFINE(VGIC_CPU_ELRSR,        offsetof(struct vgic_cpu, vgic_elrsr));
+  DEFINE(VGIC_CPU_APR,          offsetof(struct vgic_cpu, vgic_apr));
+  DEFINE(VGIC_CPU_LR,           offsetof(struct vgic_cpu, vgic_lr));
+  DEFINE(VGIC_CPU_NR_LR,        offsetof(struct vgic_cpu, nr_lr));
+#ifdef CONFIG_KVM_ARM_TIMER
+  DEFINE(VCPU_TIMER_CNTV_CTL,   offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
+  DEFINE(VCPU_TIMER_CNTV_CVAL,  offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
+  DEFINE(KVM_TIMER_CNTVOFF,     offsetof(struct kvm, arch.timer.cntvoff));
+  DEFINE(KVM_TIMER_ENABLED,     offsetof(struct kvm, arch.timer.enabled));
+#endif
+  DEFINE(KVM_VGIC_VCTRL,        offsetof(struct kvm, arch.vgic.vctrl_base));
+#endif
+  DEFINE(KVM_VTTBR,             offsetof(struct kvm, arch.vttbr));
+#endif
  return 0; 
 }
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 379cf3292390..a1f73b502ef0 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -413,7 +413,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return irq;
 }
-static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
 {
        int ret;
        struct pci_host_bridge_window *window;
@@ -445,7 +445,7 @@ static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
        return 0;
 }
-static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
        int ret;
@@ -464,6 +464,9 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                sys->map_irq = hw->map_irq;
                INIT_LIST_HEAD(&sys->resources);
+                if (hw->private_data)
+                        sys->private_data = hw->private_data[nr];
                ret = hw->setup(nr, sys);
                if (ret > 0) {
@@ -493,7 +496,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
        }
 }
-void __init pci_common_init(struct hw_pci *hw)
+void pci_common_init(struct hw_pci *hw)
 {
        struct pci_sys_data *sys;
        LIST_HEAD(head);
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index a4fda4e7a372..0cc57611fc4f 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -195,7 +195,7 @@
                CALL(sys_getcwd)
                CALL(sys_capget)
 /* 185 */       CALL(sys_capset)
-                CALL(sys_sigaltstack_wrapper)
+                CALL(sys_sigaltstack)
                CALL(sys_sendfile)
                CALL(sys_ni_syscall)            /* getpmsg */
                CALL(sys_ni_syscall)            /* putpmsg */
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index a6c301e90a3b..3248cde504ed 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -514,11 +514,6 @@ sys_rt_sigreturn_wrapper:
                b       sys_rt_sigreturn
 ENDPROC(sys_rt_sigreturn_wrapper)
-sys_sigaltstack_wrapper:
-                ldr     r2, [sp, #S_OFF + S_SP]
-                b       do_sigaltstack
-ENDPROC(sys_sigaltstack_wrapper)
 sys_statfs64_wrapper:
                teq     r1, #88
                moveq   r1, #84
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 5ff2e77782b1..5eae53e7a2e1 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -28,6 +28,7 @@
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/smp.h>
+#include <linux/cpu_pm.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -35,6 +36,7 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/kdebug.h>
 #include <asm/traps.h>
+#include <asm/hardware/coresight.h>
 /* Breakpoint currently in use for each BRP. */
 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
@@ -49,6 +51,9 @@ static int core_num_wrps;
 /* Debug architecture version. */
 static u8 debug_arch;
+/* Does debug architecture support OS Save and Restore? */
+static bool has_ossr;
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
@@ -903,6 +908,23 @@ static struct undef_hook debug_reg_hook = {
        .fn             = debug_reg_trap,
 };
+/* Does this core support OS Save and Restore? */
+static bool core_has_os_save_restore(void)
+{
+        u32 oslsr;
+        switch (get_debug_arch()) {
+        case ARM_DEBUG_ARCH_V7_1:
+                return true;
+        case ARM_DEBUG_ARCH_V7_ECP14:
+                ARM_DBG_READ(c1, c1, 4, oslsr);
+                if (oslsr & ARM_OSLSR_OSLM0)
+                        return true;
+        default:
+                return false;
+        }
+}
 static void reset_ctrl_regs(void *unused)
 {
        int i, raw_num_brps, err = 0, cpu = smp_processor_id();
@@ -930,11 +952,7 @@ static void reset_ctrl_regs(void *unused)
                if ((val & 0x1) == 0)
                        err = -EPERM;
-                /*
+                if (!has_ossr)
-                 * Check whether we implement OS save and restore.
-                 */
-                ARM_DBG_READ(c1, c1, 4, val);
-                if ((val & 0x9) == 0)
                        goto clear_vcr;
                break;
        case ARM_DEBUG_ARCH_V7_1:
@@ -955,9 +973,9 @@ static void reset_ctrl_regs(void *unused)
        /*
         * Unconditionally clear the OS lock by writing a value
-         * other than 0xC5ACCE55 to the access register.
+         * other than CS_LAR_KEY to the access register.
         */
-        ARM_DBG_WRITE(c1, c0, 4, 0);
+        ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY);
        isb();
        /*
@@ -1015,6 +1033,30 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
        .notifier_call = dbg_reset_notify,
 };
+#ifdef CONFIG_CPU_PM
+static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
+                             void *v)
+{
+        if (action == CPU_PM_EXIT)
+                reset_ctrl_regs(NULL);
+        return NOTIFY_OK;
+}
+static struct notifier_block __cpuinitdata dbg_cpu_pm_nb = {
+        .notifier_call = dbg_cpu_pm_notify,
+};
+static void __init pm_init(void)
+{
+        cpu_pm_register_notifier(&dbg_cpu_pm_nb);
+}
+#else
+static inline void pm_init(void)
+{
+}
+#endif
 static int __init arch_hw_breakpoint_init(void)
 {
        debug_arch = get_debug_arch();
@@ -1024,6 +1066,8 @@ static int __init arch_hw_breakpoint_init(void)
                return 0;
        }
+        has_ossr = core_has_os_save_restore();
        /* Determine how many BRPs/WRPs are available. */
        core_num_brps = get_num_brps();
        core_num_wrps = get_num_wrps();
@@ -1062,8 +1106,9 @@ static int __init arch_hw_breakpoint_init(void)
        hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
                        TRAP_HWBKPT, "breakpoint debug exception");
-        /* Register hotplug notifier. */
+        /* Register hotplug and PM notifiers. */
        register_cpu_notifier(&dbg_reset_nb);
+        pm_init();
        return 0;
 }
 arch_initcall(arch_hw_breakpoint_init);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 896165096d6a..8e4ef4c83a74 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -117,6 +117,16 @@ void __init init_IRQ(void)
        machine_desc->init_irq();
 }
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
+{
+        if (handle_arch_irq)
+                return;
+        handle_arch_irq = handle_irq;
+}
+#endif
 #ifdef CONFIG_SPARSE_IRQ
 int __init arch_probe_nr_irqs(void)
 {
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 4dd41fc9e235..170e9f34003f 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -395,7 +395,7 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
 {
        struct kretprobe_instance *ri = NULL;
        struct hlist_head *head, empty_rp;
-        struct hlist_node *node, *tmp;
+        struct hlist_node *tmp;
        unsigned long flags, orig_ret_address = 0;
        unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline;
@@ -415,7 +415,7 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
         *       real return address, and all the rest will point to
         *       kretprobe_trampoline
         */
-        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
+        hlist_for_each_entry_safe(ri, tmp, head, hlist) {
                if (ri->task != current)
                        /* another task is sharing our hash bucket */
                        continue;
@@ -442,7 +442,7 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
        kretprobe_assert(ri, orig_ret_address, trampoline_address);
        kretprobe_hash_unlock(current, &flags);
-        hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
+        hlist_for_each_entry_safe(ri, tmp, &empty_rp, hlist) {
                hlist_del(&ri->hlist);
                kfree(ri);
        }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index f9e8657dd241..31e0eb353cd8 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -149,12 +149,6 @@ again:
 static void
 armpmu_read(struct perf_event *event)
 {
-        struct hw_perf_event *hwc = &event->hw;
-        /* Don't read disabled counters! */
-        if (hwc->idx < 0)
-                return;
        armpmu_event_update(event);
 }
@@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags)
        struct hw_perf_event *hwc = &event->hw;
        int idx = hwc->idx;
-        WARN_ON(idx < 0);
        armpmu_stop(event, PERF_EF_UPDATE);
        hw_events->events[idx] = NULL;
        clear_bit(idx, hw_events->used_mask);
@@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        int mapping, err;
+        int mapping;
        mapping = armpmu->map_event(event);
@@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event)
                local64_set(&hwc->period_left, hwc->sample_period);
        }
-        err = 0;
        if (event->group_leader != event) {
-                err = validate_group(event);
+                if (validate_group(event) != 0);
-                if (err)
                        return -EINVAL;
        }
-        return err;
+        return 0;
 }
 static int armpmu_event_init(struct perf_event *event)
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 5f6620684e25..1f2740e3dbc0 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
        cpu_pmu->free_irq       = cpu_pmu_free_irq;
        /* Ensure the PMU has sane values out of reset. */
-        if (cpu_pmu && cpu_pmu->reset)
+        if (cpu_pmu->reset)
                on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
 }
@@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
 static int probe_current_pmu(struct arm_pmu *pmu)
 {
        int cpu = get_cpu();
-        unsigned long cpuid = read_cpuid_id();
+        unsigned long implementor = read_cpuid_implementor();
-        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+        unsigned long part_number = read_cpuid_part_number();
-        unsigned long part_number = (cpuid & 0xFFF0);
        int ret = -ENODEV;
        pr_info("probing PMU on CPU %d\n", cpu);
        /* ARM Ltd CPUs. */
-        if (0x41 == implementor) {
+        if (implementor == ARM_CPU_IMP_ARM) {
                switch (part_number) {
-                case 0xB360:    /* ARM1136 */
+                case ARM_CPU_PART_ARM1136:
-                case 0xB560:    /* ARM1156 */
+                case ARM_CPU_PART_ARM1156:
-                case 0xB760:    /* ARM1176 */
+                case ARM_CPU_PART_ARM1176:
                        ret = armv6pmu_init(pmu);
                        break;
-                case 0xB020:    /* ARM11mpcore */
+                case ARM_CPU_PART_ARM11MPCORE:
                        ret = armv6mpcore_pmu_init(pmu);
                        break;
-                case 0xC080:    /* Cortex-A8 */
+                case ARM_CPU_PART_CORTEX_A8:
                        ret = armv7_a8_pmu_init(pmu);
                        break;
-                case 0xC090:    /* Cortex-A9 */
+                case ARM_CPU_PART_CORTEX_A9:
                        ret = armv7_a9_pmu_init(pmu);
                        break;
-                case 0xC050:    /* Cortex-A5 */
+                case ARM_CPU_PART_CORTEX_A5:
                        ret = armv7_a5_pmu_init(pmu);
                        break;
-                case 0xC0F0:    /* Cortex-A15 */
+                case ARM_CPU_PART_CORTEX_A15:
                        ret = armv7_a15_pmu_init(pmu);
                        break;
-                case 0xC070:    /* Cortex-A7 */
+                case ARM_CPU_PART_CORTEX_A7:
                        ret = armv7_a7_pmu_init(pmu);
                        break;
                }
        /* Intel CPUs [xscale]. */
-        } else if (0x69 == implementor) {
+        } else if (implementor == ARM_CPU_IMP_INTEL) {
-                part_number = (cpuid >> 13) & 0x7;
+                switch (xscale_cpu_arch_version()) {
-                switch (part_number) {
+                case ARM_CPU_XSCALE_ARCH_V1:
-                case 1:
                        ret = xscale1pmu_init(pmu);
                        break;
-                case 2:
+                case ARM_CPU_XSCALE_ARCH_V2:
                        ret = xscale2pmu_init(pmu);
                        break;
                }
@@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
        }
        if (ret) {
-                pr_info("failed to register PMU devices!");
+                pr_info("failed to probe PMU!");
-                kfree(pmu);
+                goto out_free;
-                return ret;
        }
        cpu_pmu = pmu;
        cpu_pmu->plat_device = pdev;
        cpu_pmu_init(cpu_pmu);
-        armpmu_register(cpu_pmu, PERF_TYPE_RAW);
+        ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
-        return 0;
+        if (!ret)
+                return 0;
+out_free:
+        pr_info("failed to register PMU devices!");
+        kfree(pmu);
+        return ret;
 }
 static struct platform_driver cpu_pmu_driver = {
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 041d0526a288..03664b0e8fa4 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 4fbc757d9cff..8c79a9e70b83 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                /*
                 * The prefetch counters don't differentiate between the I
@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 2b0fe30ec12e..63990c42fac9 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c6dec5fc20aa..047d3e40e470 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -172,14 +172,9 @@ static void default_idle(void)
        local_irq_enable();
 }
-void (*pm_idle)(void) = default_idle;
-EXPORT_SYMBOL(pm_idle);
 /*
- * The idle thread, has rather strange semantics for calling pm_idle,
+ * The idle thread.
- * but this is what x86 does and we need to do the same, so that
+ * We always respect 'hlt_counter' to prevent low power idle.
- * things like cpuidle get called in the same way.  The only difference
- * is that we always respect 'hlt_counter' to prevent low power idle.
 */
 void cpu_idle(void)
 {
@@ -210,10 +205,10 @@ void cpu_idle(void)
                        } else if (!need_resched()) {
                                stop_critical_timings();
                                if (cpuidle_idle_call())
-                                        pm_idle();
+                                        default_idle();
                                start_critical_timings();
                                /*
-                                 * pm_idle functions must always
+                                 * default_idle functions must always
                                 * return with IRQs enabled.
                                 */
                                WARN_ON(irqs_disabled());
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
new file mode 100644
index 000000000000..36531643cc2c
--- /dev/null
+++ b/arch/arm/kernel/psci.c
@@ -0,0 +1,211 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "psci: " fmt
+#include <linux/init.h>
+#include <linux/of.h>
+#include <asm/compiler.h>
+#include <asm/errno.h>
+#include <asm/opcodes-sec.h>
+#include <asm/opcodes-virt.h>
+#include <asm/psci.h>
+struct psci_operations psci_ops;
+static int (*invoke_psci_fn)(u32, u32, u32, u32);
+enum psci_function {
+        PSCI_FN_CPU_SUSPEND,
+        PSCI_FN_CPU_ON,
+        PSCI_FN_CPU_OFF,
+        PSCI_FN_MIGRATE,
+        PSCI_FN_MAX,
+};
+static u32 psci_function_id[PSCI_FN_MAX];
+#define PSCI_RET_SUCCESS                0
+#define PSCI_RET_EOPNOTSUPP             -1
+#define PSCI_RET_EINVAL                 -2
+#define PSCI_RET_EPERM                  -3
+static int psci_to_linux_errno(int errno)
+{
+        switch (errno) {
+        case PSCI_RET_SUCCESS:
+                return 0;
+        case PSCI_RET_EOPNOTSUPP:
+                return -EOPNOTSUPP;
+        case PSCI_RET_EINVAL:
+                return -EINVAL;
+        case PSCI_RET_EPERM:
+                return -EPERM;
+        };
+        return -EINVAL;
+}
+#define PSCI_POWER_STATE_ID_MASK        0xffff
+#define PSCI_POWER_STATE_ID_SHIFT       0
+#define PSCI_POWER_STATE_TYPE_MASK      0x1
+#define PSCI_POWER_STATE_TYPE_SHIFT     16
+#define PSCI_POWER_STATE_AFFL_MASK      0x3
+#define PSCI_POWER_STATE_AFFL_SHIFT     24
+static u32 psci_power_state_pack(struct psci_power_state state)
+{
+        return  ((state.id & PSCI_POWER_STATE_ID_MASK)
+                        << PSCI_POWER_STATE_ID_SHIFT)   |
+                ((state.type & PSCI_POWER_STATE_TYPE_MASK)
+                        << PSCI_POWER_STATE_TYPE_SHIFT) |
+                ((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK)
+                        << PSCI_POWER_STATE_AFFL_SHIFT);
+}
+/*
+ * The following two functions are invoked via the invoke_psci_fn pointer
+ * and will not be inlined, allowing us to piggyback on the AAPCS.
+ */
+static noinline int __invoke_psci_fn_hvc(u32 function_id, u32 arg0, u32 arg1,
+                                         u32 arg2)
+{
+        asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r1")
+                        __asmeq("%2", "r2")
+                        __asmeq("%3", "r3")
+                        __HVC(0)
+                : "+r" (function_id)
+                : "r" (arg0), "r" (arg1), "r" (arg2));
+        return function_id;
+}
+static noinline int __invoke_psci_fn_smc(u32 function_id, u32 arg0, u32 arg1,
+                                         u32 arg2)
+{
+        asm volatile(
+                        __asmeq("%0", "r0")
+                        __asmeq("%1", "r1")
+                        __asmeq("%2", "r2")
+                        __asmeq("%3", "r3")
+                        __SMC(0)
+                : "+r" (function_id)
+                : "r" (arg0), "r" (arg1), "r" (arg2));
+        return function_id;
+}
+static int psci_cpu_suspend(struct psci_power_state state,
+                            unsigned long entry_point)
+{
+        int err;
+        u32 fn, power_state;
+        fn = psci_function_id[PSCI_FN_CPU_SUSPEND];
+        power_state = psci_power_state_pack(state);
+        err = invoke_psci_fn(fn, power_state, entry_point, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_cpu_off(struct psci_power_state state)
+{
+        int err;
+        u32 fn, power_state;
+        fn = psci_function_id[PSCI_FN_CPU_OFF];
+        power_state = psci_power_state_pack(state);
+        err = invoke_psci_fn(fn, power_state, 0, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
+{
+        int err;
+        u32 fn;
+        fn = psci_function_id[PSCI_FN_CPU_ON];
+        err = invoke_psci_fn(fn, cpuid, entry_point, 0);
+        return psci_to_linux_errno(err);
+}
+static int psci_migrate(unsigned long cpuid)
+{
+        int err;
+        u32 fn;
+        fn = psci_function_id[PSCI_FN_MIGRATE];
+        err = invoke_psci_fn(fn, cpuid, 0, 0);
+        return psci_to_linux_errno(err);
+}
+static const struct of_device_id psci_of_match[] __initconst = {
+        { .compatible = "arm,psci",     },
+        {},
+};
+static int __init psci_init(void)
+{
+        struct device_node *np;
+        const char *method;
+        u32 id;
+        np = of_find_matching_node(NULL, psci_of_match);
+        if (!np)
+                return 0;
+        pr_info("probing function IDs from device-tree\n");
+        if (of_property_read_string(np, "method", &method)) {
+                pr_warning("missing \"method\" property\n");
+                goto out_put_node;
+        }
+        if (!strcmp("hvc", method)) {
+                invoke_psci_fn = __invoke_psci_fn_hvc;
+        } else if (!strcmp("smc", method)) {
+                invoke_psci_fn = __invoke_psci_fn_smc;
+        } else {
+                pr_warning("invalid \"method\" property: %s\n", method);
+                goto out_put_node;
+        }
+        if (!of_property_read_u32(np, "cpu_suspend", &id)) {
+                psci_function_id[PSCI_FN_CPU_SUSPEND] = id;
+                psci_ops.cpu_suspend = psci_cpu_suspend;
+        }
+        if (!of_property_read_u32(np, "cpu_off", &id)) {
+                psci_function_id[PSCI_FN_CPU_OFF] = id;
+                psci_ops.cpu_off = psci_cpu_off;
+        }
+        if (!of_property_read_u32(np, "cpu_on", &id)) {
+                psci_function_id[PSCI_FN_CPU_ON] = id;
+                psci_ops.cpu_on = psci_cpu_on;
+        }
+        if (!of_property_read_u32(np, "migrate", &id)) {
+                psci_function_id[PSCI_FN_MIGRATE] = id;
+                psci_ops.migrate = psci_migrate;
+        }
+out_put_node:
+        of_node_put(np);
+        return 0;
+}
+early_initcall(psci_init);
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index fc6692e2b603..bd6f56b9ec21 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -93,11 +93,11 @@ static void notrace update_sched_clock(void)
         * detectable in cyc_to_fixed_sched_clock().
         */
        raw_local_irq_save(flags);
-        cd.epoch_cyc = cyc;
+        cd.epoch_cyc_copy = cyc;
        smp_wmb();
        cd.epoch_ns = ns;
        smp_wmb();
-        cd.epoch_cyc_copy = cyc;
+        cd.epoch_cyc = cyc;
        raw_local_irq_restore(flags);
 }
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 56f72d257ebd..296786bdbb73 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -45,48 +45,6 @@ const unsigned long sigreturn_codes[7] = {
        MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
 };
-/*
- * atomically swap in the new signal mask, and wait for a signal.
- */
-asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
-{
-        sigset_t blocked;
-        siginitset(&blocked, mask);
-        return sigsuspend(&blocked);
-}
-asmlinkage int 
-sys_sigaction(int sig, const struct old_sigaction __user *act,
-              struct old_sigaction __user *oact)
-{
-        struct k_sigaction new_ka, old_ka;
-        int ret;
-        if (act) {
-                old_sigset_t mask;
-                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
-                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
-                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
-                    __get_user(mask, &act->sa_mask))
-                        return -EFAULT;
-                siginitset(&new_ka.sa.sa_mask, mask);
-        }
-        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-        if (!ret && oact) {
-                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
-                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
-                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
-                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
-                        return -EFAULT;
-        }
-        return ret;
-}
 #ifdef CONFIG_CRUNCH
 static int preserve_crunch_context(struct crunch_sigframe __user *frame)
 {
@@ -300,7 +258,7 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
        if (restore_sigframe(regs, &frame->sig))
                goto badframe;
-        if (do_sigaltstack(&frame->sig.uc.uc_stack, NULL, regs->ARM_sp) == -EFAULT)
+        if (restore_altstack(&frame->sig.uc.uc_stack))
                goto badframe;
        return regs->ARM_r0;
@@ -360,18 +318,12 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
 }
 static inline void __user *
-get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
+get_sigframe(struct ksignal *ksig, struct pt_regs *regs, int framesize)
 {
-        unsigned long sp = regs->ARM_sp;
+        unsigned long sp = sigsp(regs->ARM_sp, ksig);
        void __user *frame;
        /*
-         * This is the X/Open sanctioned signal stack switching.
-         */
-        if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp))
-                sp = current->sas_ss_sp + current->sas_ss_size;
-        /*
         * ATPCS B01 mandates 8-byte alignment
         */
        frame = (void __user *)((sp - framesize) & ~7);
@@ -385,11 +337,22 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
        return frame;
 }
+/*
+ * translate the signal
+ */
+static inline int map_sig(int sig)
+{
+        struct thread_info *thread = current_thread_info();
+        if (sig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap)
+                sig = thread->exec_domain->signal_invmap[sig];
+        return sig;
+}
 static int
-setup_return(struct pt_regs *regs, struct k_sigaction *ka,
+setup_return(struct pt_regs *regs, struct ksignal *ksig,
-             unsigned long __user *rc, void __user *frame, int usig)
+             unsigned long __user *rc, void __user *frame)
 {
-        unsigned long handler = (unsigned long)ka->sa.sa_handler;
+        unsigned long handler = (unsigned long)ksig->ka.sa.sa_handler;
        unsigned long retcode;
        int thumb = 0;
        unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
@@ -399,7 +362,7 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
        /*
         * Maybe we need to deliver a 32-bit signal to a 26-bit task.
         */
-        if (ka->sa.sa_flags & SA_THIRTYTWO)
+        if (ksig->ka.sa.sa_flags & SA_THIRTYTWO)
                cpsr = (cpsr & ~MODE_MASK) | USR_MODE;
 #ifdef CONFIG_ARM_THUMB
@@ -421,12 +384,12 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
        }
 #endif
-        if (ka->sa.sa_flags & SA_RESTORER) {
+        if (ksig->ka.sa.sa_flags & SA_RESTORER) {
-                retcode = (unsigned long)ka->sa.sa_restorer;
+                retcode = (unsigned long)ksig->ka.sa.sa_restorer;
        } else {
                unsigned int idx = thumb << 1;
-                if (ka->sa.sa_flags & SA_SIGINFO)
+                if (ksig->ka.sa.sa_flags & SA_SIGINFO)
                        idx += 3;
                if (__put_user(sigreturn_codes[idx],   rc) ||
@@ -451,7 +414,7 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
                }
        }
-        regs->ARM_r0 = usig;
+        regs->ARM_r0 = map_sig(ksig->sig);
        regs->ARM_sp = (unsigned long)frame;
        regs->ARM_lr = retcode;
        regs->ARM_pc = handler;
@@ -461,9 +424,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 }
 static int
-setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *regs)
+setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
 {
-        struct sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
+        struct sigframe __user *frame = get_sigframe(ksig, regs, sizeof(*frame));
        int err = 0;
        if (!frame)
@@ -476,36 +439,29 @@ setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *reg
        err |= setup_sigframe(frame, regs, set);
        if (err == 0)
-                err = setup_return(regs, ka, frame->retcode, frame, usig);
+                err = setup_return(regs, ksig, frame->retcode, frame);
        return err;
 }
 static int
-setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
+setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-               sigset_t *set, struct pt_regs *regs)
 {
-        struct rt_sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
+        struct rt_sigframe __user *frame = get_sigframe(ksig, regs, sizeof(*frame));
-        stack_t stack;
        int err = 0;
        if (!frame)
                return 1;
-        err |= copy_siginfo_to_user(&frame->info, info);
+        err |= copy_siginfo_to_user(&frame->info, &ksig->info);
        __put_user_error(0, &frame->sig.uc.uc_flags, err);
        __put_user_error(NULL, &frame->sig.uc.uc_link, err);
-        memset(&stack, 0, sizeof(stack));
+        err |= __save_altstack(&frame->sig.uc.uc_stack, regs->ARM_sp);
-        stack.ss_sp = (void __user *)current->sas_ss_sp;
-        stack.ss_flags = sas_ss_flags(regs->ARM_sp);
-        stack.ss_size = current->sas_ss_size;
-        err |= __copy_to_user(&frame->sig.uc.uc_stack, &stack, sizeof(stack));
        err |= setup_sigframe(&frame->sig, regs, set);
        if (err == 0)
-                err = setup_return(regs, ka, frame->sig.retcode, frame, usig);
+                err = setup_return(regs, ksig, frame->sig.retcode, frame);
        if (err == 0) {
                /*
@@ -523,40 +479,25 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
 /*
 * OK, we're invoking a handler
 */     
-static void
+static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-handle_signal(unsigned long sig, struct k_sigaction *ka,
-              siginfo_t *info, struct pt_regs *regs)
 {
-        struct thread_info *thread = current_thread_info();
-        struct task_struct *tsk = current;
        sigset_t *oldset = sigmask_to_save();
-        int usig = sig;
        int ret;
        /*
-         * translate the signal
-         */
-        if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap)
-                usig = thread->exec_domain->signal_invmap[usig];
-        /*
         * Set up the stack frame
         */
-        if (ka->sa.sa_flags & SA_SIGINFO)
+        if (ksig->ka.sa.sa_flags & SA_SIGINFO)
-                ret = setup_rt_frame(usig, ka, info, oldset, regs);
+                ret = setup_rt_frame(ksig, oldset, regs);
        else
-                ret = setup_frame(usig, ka, oldset, regs);
+                ret = setup_frame(ksig, oldset, regs);
        /*
         * Check that the resulting registers are actually sane.
         */
        ret |= !valid_user_regs(regs);
-        if (ret != 0) {
+        signal_setup_done(ret, ksig, 0);
-                force_sigsegv(sig, tsk);
-                return;
-        }
-        signal_delivered(sig, info, ka, regs, 0);
 }
 /*
@@ -571,9 +512,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 static int do_signal(struct pt_regs *regs, int syscall)
 {
        unsigned int retval = 0, continue_addr = 0, restart_addr = 0;
-        struct k_sigaction ka;
+        struct ksignal ksig;
-        siginfo_t info;
-        int signr;
        int restart = 0;
        /*
@@ -605,33 +544,32 @@ static int do_signal(struct pt_regs *regs, int syscall)
         * Get the signal to deliver.  When running under ptrace, at this
         * point the debugger may change all our registers ...
         */
-        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        /*
         * Depending on the signal settings we may need to revert the
         * decision to restart the system call.  But skip this if a
         * debugger has chosen to restart at a different PC.
         */
-        if (regs->ARM_pc != restart_addr)
+        if (get_signal(&ksig)) {
-                restart = 0;
+                /* handler */
-        if (signr > 0) {
+                if (unlikely(restart) && regs->ARM_pc == restart_addr) {
-                if (unlikely(restart)) {
                        if (retval == -ERESTARTNOHAND ||
                            retval == -ERESTART_RESTARTBLOCK
                            || (retval == -ERESTARTSYS
-                                && !(ka.sa.sa_flags & SA_RESTART))) {
+                                && !(ksig.ka.sa.sa_flags & SA_RESTART))) {
                                regs->ARM_r0 = -EINTR;
                                regs->ARM_pc = continue_addr;
                        }
                }
+                handle_signal(&ksig, regs);
-                handle_signal(signr, &ka, &info, regs);
+        } else {
-                return 0;
+                /* no handler */
+                restore_saved_sigmask();
+                if (unlikely(restart) && regs->ARM_pc == restart_addr) {
+                        regs->ARM_pc = continue_addr;
+                        return restart;
+                }
        }
+        return 0;
-        restore_saved_sigmask();
-        if (unlikely(restart))
-                regs->ARM_pc = continue_addr;
-        return restart;
 }
 asmlinkage int
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 84f4cbf652e5..1bdfd87c8e41 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -125,18 +125,6 @@ void __init smp_init_cpus(void)
                smp_ops.smp_init_cpus();
 }
-static void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-        if (smp_ops.smp_prepare_cpus)
-                smp_ops.smp_prepare_cpus(max_cpus);
-}
-static void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-        if (smp_ops.smp_secondary_init)
-                smp_ops.smp_secondary_init(cpu);
-}
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        if (smp_ops.smp_boot_secondary)
@@ -154,12 +142,6 @@ static int platform_cpu_kill(unsigned int cpu)
        return 1;
 }
-static void platform_cpu_die(unsigned int cpu)
-{
-        if (smp_ops.cpu_die)
-                smp_ops.cpu_die(cpu);
-}
 static int platform_cpu_disable(unsigned int cpu)
 {
        if (smp_ops.cpu_disable)
@@ -257,7 +239,8 @@ void __ref cpu_die(void)
         * actual CPU shutdown procedure is at least platform (if not
         * CPU) specific.
         */
-        platform_cpu_die(cpu);
+        if (smp_ops.cpu_die)
+                smp_ops.cpu_die(cpu);
        /*
         * Do not return to the idle loop - jump back to the secondary
@@ -324,7 +307,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        /*
         * Give the platform a chance to do its own initialisation.
         */
-        platform_secondary_init(cpu);
+        if (smp_ops.smp_secondary_init)
+                smp_ops.smp_secondary_init(cpu);
        notify_cpu_starting(cpu);
@@ -399,8 +383,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                /*
                 * Initialise the present map, which describes the set of CPUs
                 * actually populated at the present time. A platform should
-                 * re-initialize the map in platform_smp_prepare_cpus() if
+                 * re-initialize the map in the platforms smp_prepare_cpus()
-                 * present != possible (e.g. physical hotplug).
+                 * if present != possible (e.g. physical hotplug).
                 */
                init_cpu_present(cpu_possible_mask);
@@ -408,7 +392,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 * Initialise the SCU if there are more than one CPU
                 * and let them know where to start.
                 */
-                platform_smp_prepare_cpus(max_cpus);
+                if (smp_ops.smp_prepare_cpus)
+                        smp_ops.smp_prepare_cpus(max_cpus);
        }
 }
@@ -416,7 +401,8 @@ static void (*smp_cross_call)(const struct cpumask *, unsigned int);
 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
 {
-        smp_cross_call = fn;
+        if (!smp_cross_call)
+                smp_cross_call = fn;
 }
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -475,19 +461,11 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
 */
 static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
-static void ipi_timer(void)
-{
-        struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
-        evt->event_handler(evt);
-}
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
-static void smp_timer_broadcast(const struct cpumask *mask)
+void tick_broadcast(const struct cpumask *mask)
 {
        smp_cross_call(mask, IPI_TIMER);
 }
-#else
-#define smp_timer_broadcast     NULL
 #endif
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
@@ -530,7 +508,6 @@ static void __cpuinit percpu_timer_setup(void)
        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
        evt->cpumask = cpumask_of(cpu);
-        evt->broadcast = smp_timer_broadcast;
        if (!lt_ops || lt_ops->setup(evt))
                broadcast_timer_setup(evt);
@@ -596,11 +573,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
        case IPI_WAKEUP:
                break;
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
        case IPI_TIMER:
                irq_enter();
-                ipi_timer();
+                tick_receive_broadcast();
                irq_exit();
                break;
+#endif
        case IPI_RESCHEDULE:
                scheduler_ipi();
@@ -693,6 +672,9 @@ static int cpufreq_callback(struct notifier_block *nb,
        if (freq->flags & CPUFREQ_CONST_LOOPS)
                return NOTIFY_OK;
+        if (arm_delay_ops.const_clock)
+                return NOTIFY_OK;
        if (!per_cpu(l_p_j_ref, cpu)) {
                per_cpu(l_p_j_ref, cpu) =
                        per_cpu(cpu_data, cpu).loops_per_jiffy;
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 743a3bfe6a67..5bc1a63284e3 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
        unsigned int val;
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (mode > 3 || mode == 1 || cpu > 3)
                return -EINVAL;
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 49f335d301ba..c092115d903a 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -24,14 +24,12 @@
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
-#include <asm/hardware/gic.h>
 /* set up by the platform code */
 static void __iomem *twd_base;
 static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
-static bool common_setup_called;
 static DEFINE_PER_CPU(bool, percpu_setup_called);
 static struct clock_event_device __percpu **twd_evt;
@@ -239,25 +237,28 @@ static irqreturn_t twd_handler(int irq, void *dev_id)
        return IRQ_NONE;
 }
-static struct clk *twd_get_clock(void)
+static void twd_get_clock(struct device_node *np)
 {
-        struct clk *clk;
        int err;
-        clk = clk_get_sys("smp_twd", NULL);
+        if (np)
-        if (IS_ERR(clk)) {
+                twd_clk = of_clk_get(np, 0);
-                pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
+        else
-                return clk;
+                twd_clk = clk_get_sys("smp_twd", NULL);
+        if (IS_ERR(twd_clk)) {
+                pr_err("smp_twd: clock not found %d\n", (int) PTR_ERR(twd_clk));
+                return;
        }
-        err = clk_prepare_enable(clk);
+        err = clk_prepare_enable(twd_clk);
        if (err) {
                pr_err("smp_twd: clock failed to prepare+enable: %d\n", err);
-                clk_put(clk);
+                clk_put(twd_clk);
-                return ERR_PTR(err);
+                return;
        }
-        return clk;
+        twd_timer_rate = clk_get_rate(twd_clk);
 }
 /*
@@ -280,26 +281,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
        }
        per_cpu(percpu_setup_called, cpu) = true;
-        /*
+        twd_calibrate_rate();
-         * This stuff only need to be done once for the entire TWD cluster
-         * during the runtime of the system.
-         */
-        if (!common_setup_called) {
-                twd_clk = twd_get_clock();
-                /*
-                 * We use IS_ERR_OR_NULL() here, because if the clock stubs
-                 * are active we will get a valid clk reference which is
-                 * however NULL and will return the rate 0. In that case we
-                 * need to calibrate the rate instead.
-                 */
-                if (!IS_ERR_OR_NULL(twd_clk))
-                        twd_timer_rate = clk_get_rate(twd_clk);
-                else
-                        twd_calibrate_rate();
-                common_setup_called = true;
-        }
        /*
         * The following is done once per CPU the first time .setup() is
@@ -330,7 +312,7 @@ static struct local_timer_ops twd_lt_ops __cpuinitdata = {
        .stop   = twd_timer_stop,
 };
-static int __init twd_local_timer_common_register(void)
+static int __init twd_local_timer_common_register(struct device_node *np)
 {
        int err;
@@ -350,6 +332,8 @@ static int __init twd_local_timer_common_register(void)
        if (err)
                goto out_irq;
+        twd_get_clock(np);
        return 0;
 out_irq:
@@ -373,7 +357,7 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
        if (!twd_base)
                return -ENOMEM;
-        return twd_local_timer_common_register();
+        return twd_local_timer_common_register(NULL);
 }
 #ifdef CONFIG_OF
@@ -405,7 +389,7 @@ void __init twd_local_timer_of_register(void)
                goto out;
        }
-        err = twd_local_timer_common_register();
+        err = twd_local_timer_common_register(np);
 out:
        WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 09be0c3c9069..955d92d265e5 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -21,7 +21,6 @@
 #include <linux/timex.h>
 #include <linux/errno.h>
 #include <linux/profile.h>
-#include <linux/syscore_ops.h>
 #include <linux/timer.h>
 #include <linux/irq.h>
@@ -31,11 +30,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-/*
- * Our system timer.
- */
-static struct sys_timer *system_timer;
 #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \
    defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE)
 /* this needs a better home */
@@ -69,16 +63,6 @@ unsigned long profile_pc(struct pt_regs *regs)
 EXPORT_SYMBOL(profile_pc);
 #endif
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-u32 arch_gettimeoffset(void)
-{
-        if (system_timer->offset != NULL)
-                return system_timer->offset() * 1000;
-        return 0;
-}
-#endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
 * Kernel system timer support.
@@ -129,43 +113,8 @@ int __init register_persistent_clock(clock_access_fn read_boot,
        return -EINVAL;
 }
-#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
-static int timer_suspend(void)
-{
-        if (system_timer->suspend)
-                system_timer->suspend();
-        return 0;
-}
-static void timer_resume(void)
-{
-        if (system_timer->resume)
-                system_timer->resume();
-}
-#else
-#define timer_suspend NULL
-#define timer_resume NULL
-#endif
-static struct syscore_ops timer_syscore_ops = {
-        .suspend        = timer_suspend,
-        .resume         = timer_resume,
-};
-static int __init timer_init_syscore_ops(void)
-{
-        register_syscore_ops(&timer_syscore_ops);
-        return 0;
-}
-device_initcall(timer_init_syscore_ops);
 void __init time_init(void)
 {
-        system_timer = machine_desc->timer;
+        machine_desc->init_time();
-        system_timer->init();
        sched_clock_postinit();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index b0179b89a04c..1c089119b2d7 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -296,7 +296,7 @@ static void oops_end(unsigned long flags, struct pt_regs *regs, int signr)
        bust_spinlocks(0);
        die_owner = -1;
-        add_taint(TAINT_DIE);
+        add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
        die_nest_count--;
        if (!die_nest_count)
                /* Nest count reaches zero, release the lock. */
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 11c1785bf63e..b571484e9f03 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -19,7 +19,11 @@
        ALIGN_FUNCTION();                                               \
        VMLINUX_SYMBOL(__idmap_text_start) = .;                         \
        *(.idmap.text)                                                  \
-        VMLINUX_SYMBOL(__idmap_text_end) = .;
+        VMLINUX_SYMBOL(__idmap_text_end) = .;                           \
+        ALIGN_FUNCTION();                                               \
+        VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;                     \
+        *(.hyp.idmap.text)                                              \
+        VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
 #ifdef CONFIG_HOTPLUG_CPU
 #define ARM_CPU_DISCARD(x)
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
new file mode 100644
index 000000000000..49dd64e579c2
--- /dev/null
+++ b/arch/arm/kvm/Kconfig
@@ -0,0 +1,72 @@
+#
+# KVM configuration
+#
+source "virt/kvm/Kconfig"
+menuconfig VIRTUALIZATION
+        bool "Virtualization"
+        ---help---
+          Say Y here to get to see options for using your Linux host to run
+          other operating systems inside virtual machines (guests).
+          This option alone does not add any kernel code.
+          If you say N, all options in this submenu will be skipped and
+          disabled.
+if VIRTUALIZATION
+config KVM
+        bool "Kernel-based Virtual Machine (KVM) support"
+        select PREEMPT_NOTIFIERS
+        select ANON_INODES
+        select KVM_MMIO
+        select KVM_ARM_HOST
+        depends on ARM_VIRT_EXT && ARM_LPAE
+        ---help---
+          Support hosting virtualized guest machines. You will also
+          need to select one or more of the processor modules below.
+          This module provides access to the hardware capabilities through
+          a character device node named /dev/kvm.
+          If unsure, say N.
+config KVM_ARM_HOST
+        bool "KVM host support for ARM cpus."
+        depends on KVM
+        depends on MMU
+        select  MMU_NOTIFIER
+        ---help---
+          Provides host support for ARM processors.
+config KVM_ARM_MAX_VCPUS
+        int "Number maximum supported virtual CPUs per VM"
+        depends on KVM_ARM_HOST
+        default 4
+        help
+          Static number of max supported virtual CPUs per VM.
+          If you choose a high number, the vcpu structures will be quite
+          large, so only choose a reasonable number that you expect to
+          actually use.
+config KVM_ARM_VGIC
+        bool "KVM support for Virtual GIC"
+        depends on KVM_ARM_HOST && OF
+        select HAVE_KVM_IRQCHIP
+        default y
+        ---help---
+          Adds support for a hardware assisted, in-kernel GIC emulation.
+config KVM_ARM_TIMER
+        bool "KVM support for Architected Timers"
+        depends on KVM_ARM_VGIC && ARM_ARCH_TIMER
+        select HAVE_KVM_IRQCHIP
+        default y
+        ---help---
+          Adds support for the Architected Timers in virtual machines
+source drivers/virtio/Kconfig
+endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
new file mode 100644
index 000000000000..fc96ce6f2357
--- /dev/null
+++ b/arch/arm/kvm/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for Kernel-based Virtual Machine module
+#
+plus_virt := $(call as-instr,.arch_extension virt,+virt)
+ifeq ($(plus_virt),+virt)
+        plus_virt_def := -DREQUIRES_VIRT=1
+endif
+ccflags-y += -Ivirt/kvm -Iarch/arm/kvm
+CFLAGS_arm.o := -I. $(plus_virt_def)
+CFLAGS_mmu.o := -I.
+AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
+AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
+kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+obj-y += kvm-arm.o init.o interrupts.o
+obj-y += arm.o guest.o mmu.o emulate.o reset.o
+obj-y += coproc.o coproc_a15.o mmio.o psci.o
+obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
new file mode 100644
index 000000000000..6ac938d46297
--- /dev/null
+++ b/arch/arm/kvm/arch_timer.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/cpu.h>
+#include <linux/of_irq.h>
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <linux/interrupt.h>
+#include <asm/arch_timer.h>
+#include <asm/kvm_vgic.h>
+#include <asm/kvm_arch_timer.h>
+static struct timecounter *timecounter;
+static struct workqueue_struct *wqueue;
+static struct kvm_irq_level timer_irq = {
+        .level  = 1,
+};
+static cycle_t kvm_phys_timer_read(void)
+{
+        return timecounter->cc->read(timecounter->cc);
+}
+static bool timer_is_armed(struct arch_timer_cpu *timer)
+{
+        return timer->armed;
+}
+/* timer_arm: as in "arm the timer", not as in ARM the company */
+static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
+{
+        timer->armed = true;
+        hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
+                      HRTIMER_MODE_ABS);
+}
+static void timer_disarm(struct arch_timer_cpu *timer)
+{
+        if (timer_is_armed(timer)) {
+                hrtimer_cancel(&timer->timer);
+                cancel_work_sync(&timer->expired);
+                timer->armed = false;
+        }
+}
+static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
+{
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+        timer->cntv_ctl |= 1 << 1; /* Mask the interrupt in the guest */
+        kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
+                            vcpu->arch.timer_cpu.irq->irq,
+                            vcpu->arch.timer_cpu.irq->level);
+}
+static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
+{
+        struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
+        /*
+         * We disable the timer in the world switch and let it be
+         * handled by kvm_timer_sync_hwstate(). Getting a timer
+         * interrupt at this point is a sure sign of some major
+         * breakage.
+         */
+        pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
+        return IRQ_HANDLED;
+}
+static void kvm_timer_inject_irq_work(struct work_struct *work)
+{
+        struct kvm_vcpu *vcpu;
+        vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
+        vcpu->arch.timer_cpu.armed = false;
+        kvm_timer_inject_irq(vcpu);
+}
+static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
+{
+        struct arch_timer_cpu *timer;
+        timer = container_of(hrt, struct arch_timer_cpu, timer);
+        queue_work(wqueue, &timer->expired);
+        return HRTIMER_NORESTART;
+}
+/**
+ * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Disarm any pending soft timers, since the world-switch code will write the
+ * virtual timer state back to the physical CPU.
+ */
+void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+        /*
+         * We're about to run this vcpu again, so there is no need to
+         * keep the background timer running, as we're about to
+         * populate the CPU timer again.
+         */
+        timer_disarm(timer);
+}
+/**
+ * kvm_timer_sync_hwstate - sync timer state from cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Check if the virtual timer was armed and either schedule a corresponding
+ * soft timer or inject directly if already expired.
+ */
+void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+        cycle_t cval, now;
+        u64 ns;
+        /* Check if the timer is enabled and unmasked first */
+        if ((timer->cntv_ctl & 3) != 1)
+                return;
+        cval = timer->cntv_cval;
+        now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
+        BUG_ON(timer_is_armed(timer));
+        if (cval <= now) {
+                /*
+                 * Timer has already expired while we were not
+                 * looking. Inject the interrupt and carry on.
+                 */
+                kvm_timer_inject_irq(vcpu);
+                return;
+        }
+        ns = cyclecounter_cyc2ns(timecounter->cc, cval - now);
+        timer_arm(timer, ns);
+}
+void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
+{
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+        INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
+        hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+        timer->timer.function = kvm_timer_expire;
+        timer->irq = &timer_irq;
+}
+static void kvm_timer_init_interrupt(void *info)
+{
+        enable_percpu_irq(timer_irq.irq, 0);
+}
+static int kvm_timer_cpu_notify(struct notifier_block *self,
+                                unsigned long action, void *cpu)
+{
+        switch (action) {
+        case CPU_STARTING:
+        case CPU_STARTING_FROZEN:
+                kvm_timer_init_interrupt(NULL);
+                break;
+        case CPU_DYING:
+        case CPU_DYING_FROZEN:
+                disable_percpu_irq(timer_irq.irq);
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block kvm_timer_cpu_nb = {
+        .notifier_call = kvm_timer_cpu_notify,
+};
+static const struct of_device_id arch_timer_of_match[] = {
+        { .compatible   = "arm,armv7-timer",    },
+        {},
+};
+int kvm_timer_hyp_init(void)
+{
+        struct device_node *np;
+        unsigned int ppi;
+        int err;
+        timecounter = arch_timer_get_timecounter();
+        if (!timecounter)
+                return -ENODEV;
+        np = of_find_matching_node(NULL, arch_timer_of_match);
+        if (!np) {
+                kvm_err("kvm_arch_timer: can't find DT node\n");
+                return -ENODEV;
+        }
+        ppi = irq_of_parse_and_map(np, 2);
+        if (!ppi) {
+                kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
+                err = -EINVAL;
+                goto out;
+        }
+        err = request_percpu_irq(ppi, kvm_arch_timer_handler,
+                                 "kvm guest timer", kvm_get_running_vcpus());
+        if (err) {
+                kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
+                        ppi, err);
+                goto out;
+        }
+        timer_irq.irq = ppi;
+        err = register_cpu_notifier(&kvm_timer_cpu_nb);
+        if (err) {
+                kvm_err("Cannot register timer CPU notifier\n");
+                goto out_free;
+        }
+        wqueue = create_singlethread_workqueue("kvm_arch_timer");
+        if (!wqueue) {
+                err = -ENOMEM;
+                goto out_free;
+        }
+        kvm_info("%s IRQ%d\n", np->name, ppi);
+        on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
+        goto out;
+out_free:
+        free_percpu_irq(ppi, kvm_get_running_vcpus());
+out:
+        of_node_put(np);
+        return err;
+}
+void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
+{
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+        timer_disarm(timer);
+}
+int kvm_timer_init(struct kvm *kvm)
+{
+        if (timecounter && wqueue) {
+                kvm->arch.timer.cntvoff = kvm_phys_timer_read();
+                kvm->arch.timer.enabled = 1;
+        }
+        return 0;
+}
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
new file mode 100644
index 000000000000..5a936988eb24
--- /dev/null
+++ b/arch/arm/kvm/arm.c
@@ -0,0 +1,1169 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/mman.h>
+#include <linux/sched.h>
+#include <linux/kvm.h>
+#include <trace/events/kvm.h>
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+#include <asm/unified.h>
+#include <asm/uaccess.h>
+#include <asm/ptrace.h>
+#include <asm/mman.h>
+#include <asm/cputype.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+#include <asm/virt.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/kvm_psci.h>
+#include <asm/opcodes.h>
+#ifdef REQUIRES_VIRT
+__asm__(".arch_extension        virt");
+#endif
+static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
+static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
+static unsigned long hyp_default_vectors;
+/* Per-CPU variable containing the currently running vcpu. */
+static DEFINE_PER_CPU(struct kvm_vcpu *, kvm_arm_running_vcpu);
+/* The VMID used in the VTTBR */
+static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1);
+static u8 kvm_next_vmid;
+static DEFINE_SPINLOCK(kvm_vmid_lock);
+static bool vgic_present;
+static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu)
+{
+        BUG_ON(preemptible());
+        __get_cpu_var(kvm_arm_running_vcpu) = vcpu;
+}
+/**
+ * kvm_arm_get_running_vcpu - get the vcpu running on the current CPU.
+ * Must be called from non-preemptible context
+ */
+struct kvm_vcpu *kvm_arm_get_running_vcpu(void)
+{
+        BUG_ON(preemptible());
+        return __get_cpu_var(kvm_arm_running_vcpu);
+}
+/**
+ * kvm_arm_get_running_vcpus - get the per-CPU array of currently running vcpus.
+ */
+struct kvm_vcpu __percpu **kvm_get_running_vcpus(void)
+{
+        return &kvm_arm_running_vcpu;
+}
+int kvm_arch_hardware_enable(void *garbage)
+{
+        return 0;
+}
+int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
+}
+void kvm_arch_hardware_disable(void *garbage)
+{
+}
+int kvm_arch_hardware_setup(void)
+{
+        return 0;
+}
+void kvm_arch_hardware_unsetup(void)
+{
+}
+void kvm_arch_check_processor_compat(void *rtn)
+{
+        *(int *)rtn = 0;
+}
+void kvm_arch_sync_events(struct kvm *kvm)
+{
+}
+/**
+ * kvm_arch_init_vm - initializes a VM data structure
+ * @kvm:        pointer to the KVM struct
+ */
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
+{
+        int ret = 0;
+        if (type)
+                return -EINVAL;
+        ret = kvm_alloc_stage2_pgd(kvm);
+        if (ret)
+                goto out_fail_alloc;
+        ret = create_hyp_mappings(kvm, kvm + 1);
+        if (ret)
+                goto out_free_stage2_pgd;
+        /* Mark the initial VMID generation invalid */
+        kvm->arch.vmid_gen = 0;
+        return ret;
+out_free_stage2_pgd:
+        kvm_free_stage2_pgd(kvm);
+out_fail_alloc:
+        return ret;
+}
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+        return VM_FAULT_SIGBUS;
+}
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+}
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        return 0;
+}
+/**
+ * kvm_arch_destroy_vm - destroy the VM data structure
+ * @kvm:        pointer to the KVM struct
+ */
+void kvm_arch_destroy_vm(struct kvm *kvm)
+{
+        int i;
+        kvm_free_stage2_pgd(kvm);
+        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+                if (kvm->vcpus[i]) {
+                        kvm_arch_vcpu_free(kvm->vcpus[i]);
+                        kvm->vcpus[i] = NULL;
+                }
+        }
+}
+int kvm_dev_ioctl_check_extension(long ext)
+{
+        int r;
+        switch (ext) {
+        case KVM_CAP_IRQCHIP:
+                r = vgic_present;
+                break;
+        case KVM_CAP_USER_MEMORY:
+        case KVM_CAP_SYNC_MMU:
+        case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
+        case KVM_CAP_ONE_REG:
+        case KVM_CAP_ARM_PSCI:
+                r = 1;
+                break;
+        case KVM_CAP_COALESCED_MMIO:
+                r = KVM_COALESCED_MMIO_PAGE_OFFSET;
+                break;
+        case KVM_CAP_ARM_SET_DEVICE_ADDR:
+                r = 1;
+        case KVM_CAP_NR_VCPUS:
+                r = num_online_cpus();
+                break;
+        case KVM_CAP_MAX_VCPUS:
+                r = KVM_MAX_VCPUS;
+                break;
+        default:
+                r = 0;
+                break;
+        }
+        return r;
+}
+long kvm_arch_dev_ioctl(struct file *filp,
+                        unsigned int ioctl, unsigned long arg)
+{
+        return -EINVAL;
+}
+int kvm_arch_set_memory_region(struct kvm *kvm,
+                               struct kvm_userspace_memory_region *mem,
+                               struct kvm_memory_slot old,
+                               int user_alloc)
+{
+        return 0;
+}
+int kvm_arch_prepare_memory_region(struct kvm *kvm,
+                                   struct kvm_memory_slot *memslot,
+                                   struct kvm_memory_slot old,
+                                   struct kvm_userspace_memory_region *mem,
+                                   bool user_alloc)
+{
+        return 0;
+}
+void kvm_arch_commit_memory_region(struct kvm *kvm,
+                                   struct kvm_userspace_memory_region *mem,
+                                   struct kvm_memory_slot old,
+                                   bool user_alloc)
+{
+}
+void kvm_arch_flush_shadow_all(struct kvm *kvm)
+{
+}
+void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+                                   struct kvm_memory_slot *slot)
+{
+}
+struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
+{
+        int err;
+        struct kvm_vcpu *vcpu;
+        vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
+        if (!vcpu) {
+                err = -ENOMEM;
+                goto out;
+        }
+        err = kvm_vcpu_init(vcpu, kvm, id);
+        if (err)
+                goto free_vcpu;
+        err = create_hyp_mappings(vcpu, vcpu + 1);
+        if (err)
+                goto vcpu_uninit;
+        return vcpu;
+vcpu_uninit:
+        kvm_vcpu_uninit(vcpu);
+free_vcpu:
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
+out:
+        return ERR_PTR(err);
+}
+int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
+{
+        kvm_mmu_free_memory_caches(vcpu);
+        kvm_timer_vcpu_terminate(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
+}
+void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+        kvm_arch_vcpu_free(vcpu);
+}
+int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+int __attribute_const__ kvm_target_cpu(void)
+{
+        unsigned long implementor = read_cpuid_implementor();
+        unsigned long part_number = read_cpuid_part_number();
+        if (implementor != ARM_CPU_IMP_ARM)
+                return -EINVAL;
+        switch (part_number) {
+        case ARM_CPU_PART_CORTEX_A15:
+                return KVM_ARM_TARGET_CORTEX_A15;
+        default:
+                return -EINVAL;
+        }
+}
+int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
+{
+        int ret;
+        /* Force users to call KVM_ARM_VCPU_INIT */
+        vcpu->arch.target = -1;
+        /* Set up VGIC */
+        ret = kvm_vgic_vcpu_init(vcpu);
+        if (ret)
+                return ret;
+        /* Set up the timer */
+        kvm_timer_vcpu_init(vcpu);
+        return 0;
+}
+void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
+{
+}
+void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
+{
+        vcpu->cpu = cpu;
+        vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state);
+        /*
+         * Check whether this vcpu requires the cache to be flushed on
+         * this physical CPU. This is a consequence of doing dcache
+         * operations by set/way on this vcpu. We do it here to be in
+         * a non-preemptible section.
+         */
+        if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
+                flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
+        kvm_arm_set_running_vcpu(vcpu);
+}
+void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
+{
+        kvm_arm_set_running_vcpu(NULL);
+}
+int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
+                                        struct kvm_guest_debug *dbg)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
+                                    struct kvm_mp_state *mp_state)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
+                                    struct kvm_mp_state *mp_state)
+{
+        return -EINVAL;
+}
+/**
+ * kvm_arch_vcpu_runnable - determine if the vcpu can be scheduled
+ * @v:          The VCPU pointer
+ *
+ * If the guest CPU is not waiting for interrupts or an interrupt line is
+ * asserted, the CPU is by definition runnable.
+ */
+int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
+{
+        return !!v->arch.irq_lines || kvm_vgic_vcpu_pending_irq(v);
+}
+/* Just ensure a guest exit from a particular CPU */
+static void exit_vm_noop(void *info)
+{
+}
+void force_vm_exit(const cpumask_t *mask)
+{
+        smp_call_function_many(mask, exit_vm_noop, NULL, true);
+}
+/**
+ * need_new_vmid_gen - check that the VMID is still valid
+ * @kvm: The VM's VMID to checkt
+ *
+ * return true if there is a new generation of VMIDs being used
+ *
+ * The hardware supports only 256 values with the value zero reserved for the
+ * host, so we check if an assigned value belongs to a previous generation,
+ * which which requires us to assign a new value. If we're the first to use a
+ * VMID for the new generation, we must flush necessary caches and TLBs on all
+ * CPUs.
+ */
+static bool need_new_vmid_gen(struct kvm *kvm)
+{
+        return unlikely(kvm->arch.vmid_gen != atomic64_read(&kvm_vmid_gen));
+}
+/**
+ * update_vttbr - Update the VTTBR with a valid VMID before the guest runs
+ * @kvm The guest that we are about to run
+ *
+ * Called from kvm_arch_vcpu_ioctl_run before entering the guest to ensure the
+ * VM has a valid VMID, otherwise assigns a new one and flushes corresponding
+ * caches and TLBs.
+ */
+static void update_vttbr(struct kvm *kvm)
+{
+        phys_addr_t pgd_phys;
+        u64 vmid;
+        if (!need_new_vmid_gen(kvm))
+                return;
+        spin_lock(&kvm_vmid_lock);
+        /*
+         * We need to re-check the vmid_gen here to ensure that if another vcpu
+         * already allocated a valid vmid for this vm, then this vcpu should
+         * use the same vmid.
+         */
+        if (!need_new_vmid_gen(kvm)) {
+                spin_unlock(&kvm_vmid_lock);
+                return;
+        }
+        /* First user of a new VMID generation? */
+        if (unlikely(kvm_next_vmid == 0)) {
+                atomic64_inc(&kvm_vmid_gen);
+                kvm_next_vmid = 1;
+                /*
+                 * On SMP we know no other CPUs can use this CPU's or each
+                 * other's VMID after force_vm_exit returns since the
+                 * kvm_vmid_lock blocks them from reentry to the guest.
+                 */
+                force_vm_exit(cpu_all_mask);
+                /*
+                 * Now broadcast TLB + ICACHE invalidation over the inner
+                 * shareable domain to make sure all data structures are
+                 * clean.
+                 */
+                kvm_call_hyp(__kvm_flush_vm_context);
+        }
+        kvm->arch.vmid_gen = atomic64_read(&kvm_vmid_gen);
+        kvm->arch.vmid = kvm_next_vmid;
+        kvm_next_vmid++;
+        /* update vttbr to be used with the new vmid */
+        pgd_phys = virt_to_phys(kvm->arch.pgd);
+        vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK;
+        kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK;
+        kvm->arch.vttbr |= vmid;
+        spin_unlock(&kvm_vmid_lock);
+}
+static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* SVC called from Hyp mode should never get here */
+        kvm_debug("SVC called from Hyp mode shouldn't go here\n");
+        BUG();
+        return -EINVAL; /* Squash warning */
+}
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
+                      vcpu->arch.hsr & HSR_HVC_IMM_MASK);
+        if (kvm_psci_call(vcpu))
+                return 1;
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        if (kvm_psci_call(vcpu))
+                return 1;
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* The hypervisor should never cause aborts */
+        kvm_err("Prefetch Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+                vcpu->arch.hxfar, vcpu->arch.hsr);
+        return -EFAULT;
+}
+static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* This is either an error in the ws. code or an external abort */
+        kvm_err("Data Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+                vcpu->arch.hxfar, vcpu->arch.hsr);
+        return -EFAULT;
+}
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+static exit_handle_fn arm_exit_handlers[] = {
+        [HSR_EC_WFI]            = kvm_handle_wfi,
+        [HSR_EC_CP15_32]        = kvm_handle_cp15_32,
+        [HSR_EC_CP15_64]        = kvm_handle_cp15_64,
+        [HSR_EC_CP14_MR]        = kvm_handle_cp14_access,
+        [HSR_EC_CP14_LS]        = kvm_handle_cp14_load_store,
+        [HSR_EC_CP14_64]        = kvm_handle_cp14_access,
+        [HSR_EC_CP_0_13]        = kvm_handle_cp_0_13_access,
+        [HSR_EC_CP10_ID]        = kvm_handle_cp10_id,
+        [HSR_EC_SVC_HYP]        = handle_svc_hyp,
+        [HSR_EC_HVC]            = handle_hvc,
+        [HSR_EC_SMC]            = handle_smc,
+        [HSR_EC_IABT]           = kvm_handle_guest_abort,
+        [HSR_EC_IABT_HYP]       = handle_pabt_hyp,
+        [HSR_EC_DABT]           = kvm_handle_guest_abort,
+        [HSR_EC_DABT_HYP]       = handle_dabt_hyp,
+};
+/*
+ * A conditional instruction is allowed to trap, even though it
+ * wouldn't be executed.  So let's re-implement the hardware, in
+ * software!
+ */
+static bool kvm_condition_valid(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr, cond, insn;
+        /*
+         * Exception Code 0 can only happen if we set HCR.TGE to 1, to
+         * catch undefined instructions, and then we won't get past
+         * the arm_exit_handlers test anyway.
+         */
+        BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0);
+        /* Top two bits non-zero?  Unconditional. */
+        if (vcpu->arch.hsr >> 30)
+                return true;
+        cpsr = *vcpu_cpsr(vcpu);
+        /* Is condition field valid? */
+        if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT)
+                cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT;
+        else {
+                /* This can happen in Thumb mode: examine IT state. */
+                unsigned long it;
+                it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+                /* it == 0 => unconditional. */
+                if (it == 0)
+                        return true;
+                /* The cond for this insn works out as the top 4 bits. */
+                cond = (it >> 4);
+        }
+        /* Shift makes it look like an ARM-mode instruction */
+        insn = cond << 28;
+        return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
+}
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to QEMU.
+ */
+static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                       int exception_index)
+{
+        unsigned long hsr_ec;
+        switch (exception_index) {
+        case ARM_EXCEPTION_IRQ:
+                return 1;
+        case ARM_EXCEPTION_UNDEFINED:
+                kvm_err("Undefined exception in Hyp mode at: %#08x\n",
+                        vcpu->arch.hyp_pc);
+                BUG();
+                panic("KVM: Hypervisor undefined exception!\n");
+        case ARM_EXCEPTION_DATA_ABORT:
+        case ARM_EXCEPTION_PREF_ABORT:
+        case ARM_EXCEPTION_HVC:
+                hsr_ec = (vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT;
+                if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers)
+                    || !arm_exit_handlers[hsr_ec]) {
+                        kvm_err("Unkown exception class: %#08lx, "
+                                "hsr: %#08x\n", hsr_ec,
+                                (unsigned int)vcpu->arch.hsr);
+                        BUG();
+                }
+                /*
+                 * See ARM ARM B1.14.1: "Hyp traps on instructions
+                 * that fail their condition code check"
+                 */
+                if (!kvm_condition_valid(vcpu)) {
+                        bool is_wide = vcpu->arch.hsr & HSR_IL;
+                        kvm_skip_instr(vcpu, is_wide);
+                        return 1;
+                }
+                return arm_exit_handlers[hsr_ec](vcpu, run);
+        default:
+                kvm_pr_unimpl("Unsupported exception type: %d",
+                              exception_index);
+                run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+                return 0;
+        }
+}
+static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
+{
+        if (likely(vcpu->arch.has_run_once))
+                return 0;
+        vcpu->arch.has_run_once = true;
+        /*
+         * Initialize the VGIC before running a vcpu the first time on
+         * this VM.
+         */
+        if (irqchip_in_kernel(vcpu->kvm) &&
+            unlikely(!vgic_initialized(vcpu->kvm))) {
+                int ret = kvm_vgic_init(vcpu->kvm);
+                if (ret)
+                        return ret;
+        }
+        /*
+         * Handle the "start in power-off" case by calling into the
+         * PSCI code.
+         */
+        if (test_and_clear_bit(KVM_ARM_VCPU_POWER_OFF, vcpu->arch.features)) {
+                *vcpu_reg(vcpu, 0) = KVM_PSCI_FN_CPU_OFF;
+                kvm_psci_call(vcpu);
+        }
+        return 0;
+}
+static void vcpu_pause(struct kvm_vcpu *vcpu)
+{
+        wait_queue_head_t *wq = kvm_arch_vcpu_wq(vcpu);
+        wait_event_interruptible(*wq, !vcpu->arch.pause);
+}
+/**
+ * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
+ * @vcpu:       The VCPU pointer
+ * @run:        The kvm_run structure pointer used for userspace state exchange
+ *
+ * This function is called through the VCPU_RUN ioctl called from user space. It
+ * will execute VM code in a loop until the time slice for the process is used
+ * or some emulation is needed from user space in which case the function will
+ * return with return value 0 and with the kvm_run structure filled in with the
+ * required data for the requested emulation.
+ */
+int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        int ret;
+        sigset_t sigsaved;
+        /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
+        if (unlikely(vcpu->arch.target < 0))
+                return -ENOEXEC;
+        ret = kvm_vcpu_first_run_init(vcpu);
+        if (ret)
+                return ret;
+        if (run->exit_reason == KVM_EXIT_MMIO) {
+                ret = kvm_handle_mmio_return(vcpu, vcpu->run);
+                if (ret)
+                        return ret;
+        }
+        if (vcpu->sigset_active)
+                sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
+        ret = 1;
+        run->exit_reason = KVM_EXIT_UNKNOWN;
+        while (ret > 0) {
+                /*
+                 * Check conditions before entering the guest
+                 */
+                cond_resched();
+                update_vttbr(vcpu->kvm);
+                if (vcpu->arch.pause)
+                        vcpu_pause(vcpu);
+                kvm_vgic_flush_hwstate(vcpu);
+                kvm_timer_flush_hwstate(vcpu);
+                local_irq_disable();
+                /*
+                 * Re-check atomic conditions
+                 */
+                if (signal_pending(current)) {
+                        ret = -EINTR;
+                        run->exit_reason = KVM_EXIT_INTR;
+                }
+                if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) {
+                        local_irq_enable();
+                        kvm_timer_sync_hwstate(vcpu);
+                        kvm_vgic_sync_hwstate(vcpu);
+                        continue;
+                }
+                /**************************************************************
+                 * Enter the guest
+                 */
+                trace_kvm_entry(*vcpu_pc(vcpu));
+                kvm_guest_enter();
+                vcpu->mode = IN_GUEST_MODE;
+                ret = kvm_call_hyp(__kvm_vcpu_run, vcpu);
+                vcpu->mode = OUTSIDE_GUEST_MODE;
+                vcpu->arch.last_pcpu = smp_processor_id();
+                kvm_guest_exit();
+                trace_kvm_exit(*vcpu_pc(vcpu));
+                /*
+                 * We may have taken a host interrupt in HYP mode (ie
+                 * while executing the guest). This interrupt is still
+                 * pending, as we haven't serviced it yet!
+                 *
+                 * We're now back in SVC mode, with interrupts
+                 * disabled.  Enabling the interrupts now will have
+                 * the effect of taking the interrupt again, in SVC
+                 * mode this time.
+                 */
+                local_irq_enable();
+                /*
+                 * Back from guest
+                 *************************************************************/
+                kvm_timer_sync_hwstate(vcpu);
+                kvm_vgic_sync_hwstate(vcpu);
+                ret = handle_exit(vcpu, run, ret);
+        }
+        if (vcpu->sigset_active)
+                sigprocmask(SIG_SETMASK, &sigsaved, NULL);
+        return ret;
+}
+static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level)
+{
+        int bit_index;
+        bool set;
+        unsigned long *ptr;
+        if (number == KVM_ARM_IRQ_CPU_IRQ)
+                bit_index = __ffs(HCR_VI);
+        else /* KVM_ARM_IRQ_CPU_FIQ */
+                bit_index = __ffs(HCR_VF);
+        ptr = (unsigned long *)&vcpu->arch.irq_lines;
+        if (level)
+                set = test_and_set_bit(bit_index, ptr);
+        else
+                set = test_and_clear_bit(bit_index, ptr);
+        /*
+         * If we didn't change anything, no need to wake up or kick other CPUs
+         */
+        if (set == level)
+                return 0;
+        /*
+         * The vcpu irq_lines field was updated, wake up sleeping VCPUs and
+         * trigger a world-switch round on the running physical CPU to set the
+         * virtual IRQ/FIQ fields in the HCR appropriately.
+         */
+        kvm_vcpu_kick(vcpu);
+        return 0;
+}
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level)
+{
+        u32 irq = irq_level->irq;
+        unsigned int irq_type, vcpu_idx, irq_num;
+        int nrcpus = atomic_read(&kvm->online_vcpus);
+        struct kvm_vcpu *vcpu = NULL;
+        bool level = irq_level->level;
+        irq_type = (irq >> KVM_ARM_IRQ_TYPE_SHIFT) & KVM_ARM_IRQ_TYPE_MASK;
+        vcpu_idx = (irq >> KVM_ARM_IRQ_VCPU_SHIFT) & KVM_ARM_IRQ_VCPU_MASK;
+        irq_num = (irq >> KVM_ARM_IRQ_NUM_SHIFT) & KVM_ARM_IRQ_NUM_MASK;
+        trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level);
+        switch (irq_type) {
+        case KVM_ARM_IRQ_TYPE_CPU:
+                if (irqchip_in_kernel(kvm))
+                        return -ENXIO;
+                if (vcpu_idx >= nrcpus)
+                        return -EINVAL;
+                vcpu = kvm_get_vcpu(kvm, vcpu_idx);
+                if (!vcpu)
+                        return -EINVAL;
+                if (irq_num > KVM_ARM_IRQ_CPU_FIQ)
+                        return -EINVAL;
+                return vcpu_interrupt_line(vcpu, irq_num, level);
+        case KVM_ARM_IRQ_TYPE_PPI:
+                if (!irqchip_in_kernel(kvm))
+                        return -ENXIO;
+                if (vcpu_idx >= nrcpus)
+                        return -EINVAL;
+                vcpu = kvm_get_vcpu(kvm, vcpu_idx);
+                if (!vcpu)
+                        return -EINVAL;
+                if (irq_num < VGIC_NR_SGIS || irq_num >= VGIC_NR_PRIVATE_IRQS)
+                        return -EINVAL;
+                return kvm_vgic_inject_irq(kvm, vcpu->vcpu_id, irq_num, level);
+        case KVM_ARM_IRQ_TYPE_SPI:
+                if (!irqchip_in_kernel(kvm))
+                        return -ENXIO;
+                if (irq_num < VGIC_NR_PRIVATE_IRQS ||
+                    irq_num > KVM_ARM_IRQ_GIC_MAX)
+                        return -EINVAL;
+                return kvm_vgic_inject_irq(kvm, 0, irq_num, level);
+        }
+        return -EINVAL;
+}
+long kvm_arch_vcpu_ioctl(struct file *filp,
+                         unsigned int ioctl, unsigned long arg)
+{
+        struct kvm_vcpu *vcpu = filp->private_data;
+        void __user *argp = (void __user *)arg;
+        switch (ioctl) {
+        case KVM_ARM_VCPU_INIT: {
+                struct kvm_vcpu_init init;
+                if (copy_from_user(&init, argp, sizeof(init)))
+                        return -EFAULT;
+                return kvm_vcpu_set_target(vcpu, &init);
+        }
+        case KVM_SET_ONE_REG:
+        case KVM_GET_ONE_REG: {
+                struct kvm_one_reg reg;
+                if (copy_from_user(&reg, argp, sizeof(reg)))
+                        return -EFAULT;
+                if (ioctl == KVM_SET_ONE_REG)
+                        return kvm_arm_set_reg(vcpu, &reg);
+                else
+                        return kvm_arm_get_reg(vcpu, &reg);
+        }
+        case KVM_GET_REG_LIST: {
+                struct kvm_reg_list __user *user_list = argp;
+                struct kvm_reg_list reg_list;
+                unsigned n;
+                if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
+                        return -EFAULT;
+                n = reg_list.n;
+                reg_list.n = kvm_arm_num_regs(vcpu);
+                if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
+                        return -EFAULT;
+                if (n < reg_list.n)
+                        return -E2BIG;
+                return kvm_arm_copy_reg_indices(vcpu, user_list->reg);
+        }
+        default:
+                return -EINVAL;
+        }
+}
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
+{
+        return -EINVAL;
+}
+static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm,
+                                        struct kvm_arm_device_addr *dev_addr)
+{
+        unsigned long dev_id, type;
+        dev_id = (dev_addr->id & KVM_ARM_DEVICE_ID_MASK) >>
+                KVM_ARM_DEVICE_ID_SHIFT;
+        type = (dev_addr->id & KVM_ARM_DEVICE_TYPE_MASK) >>
+                KVM_ARM_DEVICE_TYPE_SHIFT;
+        switch (dev_id) {
+        case KVM_ARM_DEVICE_VGIC_V2:
+                if (!vgic_present)
+                        return -ENXIO;
+                return kvm_vgic_set_addr(kvm, type, dev_addr->addr);
+        default:
+                return -ENODEV;
+        }
+}
+long kvm_arch_vm_ioctl(struct file *filp,
+                       unsigned int ioctl, unsigned long arg)
+{
+        struct kvm *kvm = filp->private_data;
+        void __user *argp = (void __user *)arg;
+        switch (ioctl) {
+        case KVM_CREATE_IRQCHIP: {
+                if (vgic_present)
+                        return kvm_vgic_create(kvm);
+                else
+                        return -ENXIO;
+        }
+        case KVM_ARM_SET_DEVICE_ADDR: {
+                struct kvm_arm_device_addr dev_addr;
+                if (copy_from_user(&dev_addr, argp, sizeof(dev_addr)))
+                        return -EFAULT;
+                return kvm_vm_ioctl_set_device_addr(kvm, &dev_addr);
+        }
+        default:
+                return -EINVAL;
+        }
+}
+static void cpu_init_hyp_mode(void *vector)
+{
+        unsigned long long pgd_ptr;
+        unsigned long pgd_low, pgd_high;
+        unsigned long hyp_stack_ptr;
+        unsigned long stack_page;
+        unsigned long vector_ptr;
+        /* Switch from the HYP stub to our own HYP init vector */
+        __hyp_set_vectors((unsigned long)vector);
+        pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+        pgd_low = (pgd_ptr & ((1ULL << 32) - 1));
+        pgd_high = (pgd_ptr >> 32ULL);
+        stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
+        hyp_stack_ptr = stack_page + PAGE_SIZE;
+        vector_ptr = (unsigned long)__kvm_hyp_vector;
+        /*
+         * Call initialization code, and switch to the full blown
+         * HYP code. The init code doesn't need to preserve these registers as
+         * r1-r3 and r12 are already callee save according to the AAPCS.
+         * Note that we slightly misuse the prototype by casing the pgd_low to
+         * a void *.
+         */
+        kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr);
+}
+/**
+ * Inits Hyp-mode on all online CPUs
+ */
+static int init_hyp_mode(void)
+{
+        phys_addr_t init_phys_addr;
+        int cpu;
+        int err = 0;
+        /*
+         * Allocate Hyp PGD and setup Hyp identity mapping
+         */
+        err = kvm_mmu_init();
+        if (err)
+                goto out_err;
+        /*
+         * It is probably enough to obtain the default on one
+         * CPU. It's unlikely to be different on the others.
+         */
+        hyp_default_vectors = __hyp_get_vectors();
+        /*
+         * Allocate stack pages for Hypervisor-mode
+         */
+        for_each_possible_cpu(cpu) {
+                unsigned long stack_page;
+                stack_page = __get_free_page(GFP_KERNEL);
+                if (!stack_page) {
+                        err = -ENOMEM;
+                        goto out_free_stack_pages;
+                }
+                per_cpu(kvm_arm_hyp_stack_page, cpu) = stack_page;
+        }
+        /*
+         * Execute the init code on each CPU.
+         *
+         * Note: The stack is not mapped yet, so don't do anything else than
+         * initializing the hypervisor mode on each CPU using a local stack
+         * space for temporary storage.
+         */
+        init_phys_addr = virt_to_phys(__kvm_hyp_init);
+        for_each_online_cpu(cpu) {
+                smp_call_function_single(cpu, cpu_init_hyp_mode,
+                                         (void *)(long)init_phys_addr, 1);
+        }
+        /*
+         * Unmap the identity mapping
+         */
+        kvm_clear_hyp_idmap();
+        /*
+         * Map the Hyp-code called directly from the host
+         */
+        err = create_hyp_mappings(__kvm_hyp_code_start, __kvm_hyp_code_end);
+        if (err) {
+                kvm_err("Cannot map world-switch code\n");
+                goto out_free_mappings;
+        }
+        /*
+         * Map the Hyp stack pages
+         */
+        for_each_possible_cpu(cpu) {
+                char *stack_page = (char *)per_cpu(kvm_arm_hyp_stack_page, cpu);
+                err = create_hyp_mappings(stack_page, stack_page + PAGE_SIZE);
+                if (err) {
+                        kvm_err("Cannot map hyp stack\n");
+                        goto out_free_mappings;
+                }
+        }
+        /*
+         * Map the host VFP structures
+         */
+        kvm_host_vfp_state = alloc_percpu(struct vfp_hard_struct);
+        if (!kvm_host_vfp_state) {
+                err = -ENOMEM;
+                kvm_err("Cannot allocate host VFP state\n");
+                goto out_free_mappings;
+        }
+        for_each_possible_cpu(cpu) {
+                struct vfp_hard_struct *vfp;
+                vfp = per_cpu_ptr(kvm_host_vfp_state, cpu);
+                err = create_hyp_mappings(vfp, vfp + 1);
+                if (err) {
+                        kvm_err("Cannot map host VFP state: %d\n", err);
+                        goto out_free_vfp;
+                }
+        }
+        /*
+         * Init HYP view of VGIC
+         */
+        err = kvm_vgic_hyp_init();
+        if (err)
+                goto out_free_vfp;
+#ifdef CONFIG_KVM_ARM_VGIC
+                vgic_present = true;
+#endif
+        /*
+         * Init HYP architected timer support
+         */
+        err = kvm_timer_hyp_init();
+        if (err)
+                goto out_free_mappings;
+        kvm_info("Hyp mode initialized successfully\n");
+        return 0;
+out_free_vfp:
+        free_percpu(kvm_host_vfp_state);
+out_free_mappings:
+        free_hyp_pmds();
+out_free_stack_pages:
+        for_each_possible_cpu(cpu)
+                free_page(per_cpu(kvm_arm_hyp_stack_page, cpu));
+out_err:
+        kvm_err("error initializing Hyp mode: %d\n", err);
+        return err;
+}
+/**
+ * Initialize Hyp-mode and memory mappings on all CPUs.
+ */
+int kvm_arch_init(void *opaque)
+{
+        int err;
+        if (!is_hyp_mode_available()) {
+                kvm_err("HYP mode not available\n");
+                return -ENODEV;
+        }
+        if (kvm_target_cpu() < 0) {
+                kvm_err("Target CPU not supported!\n");
+                return -ENODEV;
+        }
+        err = init_hyp_mode();
+        if (err)
+                goto out_err;
+        kvm_coproc_table_init();
+        return 0;
+out_err:
+        return err;
+}
+/* NOP: Compiling as a module not supported */
+void kvm_arch_exit(void)
+{
+}
+static int arm_init(void)
+{
+        int rc = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
+        return rc;
+}
+module_init(arm_init);
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
new file mode 100644
index 000000000000..4ea9a982269c
--- /dev/null
+++ b/arch/arm/kvm/coproc.c
@@ -0,0 +1,1050 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.com.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <linux/uaccess.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <trace/events/kvm.h>
+#include <asm/vfp.h>
+#include "../vfp/vfpinstr.h"
+#include "trace.h"
+#include "coproc.h"
+/******************************************************************************
+ * Co-processor emulation
+ *****************************************************************************/
+/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
+static u32 cache_levels;
+/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
+#define CSSELR_MAX 12
+int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /*
+         * We can get here, if the host has been built without VFPv3 support,
+         * but the guest attempted a floating point operation.
+         */
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+/* See note at ARM ARM B1.14.4 */
+static bool access_dcsw(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *p,
+                        const struct coproc_reg *r)
+{
+        u32 val;
+        int cpu;
+        cpu = get_cpu();
+        if (!p->is_write)
+                return read_from_write_only(vcpu, p);
+        cpumask_setall(&vcpu->arch.require_dcache_flush);
+        cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
+        /* If we were already preempted, take the long way around */
+        if (cpu != vcpu->arch.last_pcpu) {
+                flush_cache_all();
+                goto done;
+        }
+        val = *vcpu_reg(vcpu, p->Rt1);
+        switch (p->CRm) {
+        case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
+        case 14:                /* DCCISW */
+                asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
+                break;
+        case 10:                /* DCCSW */
+                asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
+                break;
+        }
+done:
+        put_cpu();
+        return true;
+}
+/*
+ * We could trap ID_DFR0 and tell the guest we don't support performance
+ * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
+ * NAKed, so it will read the PMCR anyway.
+ *
+ * Therefore we tell the guest we have 0 counters.  Unfortunately, we
+ * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
+ * all PM registers, which doesn't crash the guest kernel at least.
+ */
+static bool pm_fake(struct kvm_vcpu *vcpu,
+                    const struct coproc_params *p,
+                    const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        else
+                return read_zero(vcpu, p);
+}
+#define access_pmcr pm_fake
+#define access_pmcntenset pm_fake
+#define access_pmcntenclr pm_fake
+#define access_pmovsr pm_fake
+#define access_pmselr pm_fake
+#define access_pmceid0 pm_fake
+#define access_pmceid1 pm_fake
+#define access_pmccntr pm_fake
+#define access_pmxevtyper pm_fake
+#define access_pmxevcntr pm_fake
+#define access_pmuserenr pm_fake
+#define access_pmintenset pm_fake
+#define access_pmintenclr pm_fake
+/* Architected CP15 registers.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
+ */
+static const struct coproc_reg cp15_regs[] = {
+        /* CSSELR: swapped by interrupt.S. */
+        { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
+                        NULL, reset_unknown, c0_CSSELR },
+        /* TTBR0/TTBR1: swapped by interrupt.S. */
+        { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
+        { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
+        /* TTBCR: swapped by interrupt.S. */
+        { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_val, c2_TTBCR, 0x00000000 },
+        /* DACR: swapped by interrupt.S. */
+        { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c3_DACR },
+        /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
+        { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c5_DFSR },
+        { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c5_IFSR },
+        { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c5_ADFSR },
+        { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c5_AIFSR },
+        /* DFAR/IFAR: swapped by interrupt.S. */
+        { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c6_DFAR },
+        { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_unknown, c6_IFAR },
+        /*
+         * DC{C,I,CI}SW operations:
+         */
+        { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
+        { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
+        { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
+        /*
+         * Dummy performance monitor implementation.
+         */
+        { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
+        { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
+        { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
+        { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
+        /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
+        { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
+                        NULL, reset_unknown, c10_PRRR},
+        { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
+                        NULL, reset_unknown, c10_NMRR},
+        /* VBAR: swapped by interrupt.S. */
+        { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_val, c12_VBAR, 0x00000000 },
+        /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
+        { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
+                        NULL, reset_val, c13_CID, 0x00000000 },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_unknown, c13_TID_URW },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
+                        NULL, reset_unknown, c13_TID_URO },
+        { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
+                        NULL, reset_unknown, c13_TID_PRIV },
+        /* CNTKCTL: swapped by interrupt.S. */
+        { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
+                        NULL, reset_val, c14_CNTKCTL, 0x00000000 },
+};
+/* Target specific emulation tables */
+static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
+void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
+{
+        target_tables[table->target] = table;
+}
+/* Get specific register table for this target. */
+static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
+{
+        struct kvm_coproc_target_table *table;
+        table = target_tables[target];
+        *num = table->num;
+        return table->table;
+}
+static const struct coproc_reg *find_reg(const struct coproc_params *params,
+                                         const struct coproc_reg table[],
+                                         unsigned int num)
+{
+        unsigned int i;
+        for (i = 0; i < num; i++) {
+                const struct coproc_reg *r = &table[i];
+                if (params->is_64bit != r->is_64)
+                        continue;
+                if (params->CRn != r->CRn)
+                        continue;
+                if (params->CRm != r->CRm)
+                        continue;
+                if (params->Op1 != r->Op1)
+                        continue;
+                if (params->Op2 != r->Op2)
+                        continue;
+                return r;
+        }
+        return NULL;
+}
+static int emulate_cp15(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *params)
+{
+        size_t num;
+        const struct coproc_reg *table, *r;
+        trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
+                                   params->CRm, params->Op2, params->is_write);
+        table = get_target_table(vcpu->arch.target, &num);
+        /* Search target-specific then generic table. */
+        r = find_reg(params, table, num);
+        if (!r)
+                r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
+        if (likely(r)) {
+                /* If we don't have an accessor, we should never get here! */
+                BUG_ON(!r->access);
+                if (likely(r->access(vcpu, params, r))) {
+                        /* Skip instruction, since it was emulated */
+                        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+                        return 1;
+                }
+                /* If access function fails, it should complain. */
+        } else {
+                kvm_err("Unsupported guest CP15 access at: %08x\n",
+                        *vcpu_pc(vcpu));
+                print_cp_instr(params);
+        }
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+/**
+ * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct coproc_params params;
+        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.is_64bit = true;
+        params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
+        params.Op2 = 0;
+        params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
+        params.CRn = 0;
+        return emulate_cp15(vcpu, &params);
+}
+static void reset_coproc_regs(struct kvm_vcpu *vcpu,
+                              const struct coproc_reg *table, size_t num)
+{
+        unsigned long i;
+        for (i = 0; i < num; i++)
+                if (table[i].reset)
+                        table[i].reset(vcpu, &table[i]);
+}
+/**
+ * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct coproc_params params;
+        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.is_64bit = false;
+        params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
+        params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
+        params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
+        params.Rt2 = 0;
+        return emulate_cp15(vcpu, &params);
+}
+/******************************************************************************
+ * Userspace API
+ *****************************************************************************/
+static bool index_to_params(u64 id, struct coproc_params *params)
+{
+        switch (id & KVM_REG_SIZE_MASK) {
+        case KVM_REG_SIZE_U32:
+                /* Any unused index bits means it's not valid. */
+                if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+                           | KVM_REG_ARM_COPROC_MASK
+                           | KVM_REG_ARM_32_CRN_MASK
+                           | KVM_REG_ARM_CRM_MASK
+                           | KVM_REG_ARM_OPC1_MASK
+                           | KVM_REG_ARM_32_OPC2_MASK))
+                        return false;
+                params->is_64bit = false;
+                params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
+                               >> KVM_REG_ARM_32_CRN_SHIFT);
+                params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
+                               >> KVM_REG_ARM_CRM_SHIFT);
+                params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
+                               >> KVM_REG_ARM_OPC1_SHIFT);
+                params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
+                               >> KVM_REG_ARM_32_OPC2_SHIFT);
+                return true;
+        case KVM_REG_SIZE_U64:
+                /* Any unused index bits means it's not valid. */
+                if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+                              | KVM_REG_ARM_COPROC_MASK
+                              | KVM_REG_ARM_CRM_MASK
+                              | KVM_REG_ARM_OPC1_MASK))
+                        return false;
+                params->is_64bit = true;
+                params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
+                               >> KVM_REG_ARM_CRM_SHIFT);
+                params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
+                               >> KVM_REG_ARM_OPC1_SHIFT);
+                params->Op2 = 0;
+                params->CRn = 0;
+                return true;
+        default:
+                return false;
+        }
+}
+/* Decode an index value, and find the cp15 coproc_reg entry. */
+static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
+                                                    u64 id)
+{
+        size_t num;
+        const struct coproc_reg *table, *r;
+        struct coproc_params params;
+        /* We only do cp15 for now. */
+        if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
+                return NULL;
+        if (!index_to_params(id, &params))
+                return NULL;
+        table = get_target_table(vcpu->arch.target, &num);
+        r = find_reg(&params, table, num);
+        if (!r)
+                r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
+        /* Not saved in the cp15 array? */
+        if (r && !r->reg)
+                r = NULL;
+        return r;
+}
+/*
+ * These are the invariant cp15 registers: we let the guest see the host
+ * versions of these, so they're part of the guest state.
+ *
+ * A future CPU may provide a mechanism to present different values to
+ * the guest, or a future kvm may trap them.
+ */
+/* Unfortunately, there's no register-argument for mrc, so generate. */
+#define FUNCTION_FOR32(crn, crm, op1, op2, name)                        \
+        static void get_##name(struct kvm_vcpu *v,                      \
+                               const struct coproc_reg *r)              \
+        {                                                               \
+                u32 val;                                                \
+                                                                        \
+                asm volatile("mrc p15, " __stringify(op1)               \
+                             ", %0, c" __stringify(crn)                 \
+                             ", c" __stringify(crm)                     \
+                             ", " __stringify(op2) "\n" : "=r" (val));  \
+                ((struct coproc_reg *)r)->val = val;                    \
+        }
+FUNCTION_FOR32(0, 0, 0, 0, MIDR)
+FUNCTION_FOR32(0, 0, 0, 1, CTR)
+FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
+FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
+FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
+FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
+FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
+FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
+FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
+FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
+FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
+FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
+FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
+FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
+FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
+FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
+FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
+FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
+FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
+FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
+FUNCTION_FOR32(0, 0, 1, 7, AIDR)
+/* ->val is filled in by kvm_invariant_coproc_table_init() */
+static struct coproc_reg invariant_cp15[] = {
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
+        { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
+        { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
+        { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
+        { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
+};
+static int reg_from_user(void *val, const void __user *uaddr, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+static int reg_to_user(void __user *uaddr, const void *val, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+static int get_invariant_cp15(u64 id, void __user *uaddr)
+{
+        struct coproc_params params;
+        const struct coproc_reg *r;
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+        r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
+        if (!r)
+                return -ENOENT;
+        return reg_to_user(uaddr, &r->val, id);
+}
+static int set_invariant_cp15(u64 id, void __user *uaddr)
+{
+        struct coproc_params params;
+        const struct coproc_reg *r;
+        int err;
+        u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+        r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
+        if (!r)
+                return -ENOENT;
+        err = reg_from_user(&val, uaddr, id);
+        if (err)
+                return err;
+        /* This is what we mean by invariant: you can't change it. */
+        if (r->val != val)
+                return -EINVAL;
+        return 0;
+}
+static bool is_valid_cache(u32 val)
+{
+        u32 level, ctype;
+        if (val >= CSSELR_MAX)
+                return -ENOENT;
+        /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
+        level = (val >> 1);
+        ctype = (cache_levels >> (level * 3)) & 7;
+        switch (ctype) {
+        case 0: /* No cache */
+                return false;
+        case 1: /* Instruction cache only */
+                return (val & 1);
+        case 2: /* Data cache only */
+        case 4: /* Unified cache */
+                return !(val & 1);
+        case 3: /* Separate instruction and data caches */
+                return true;
+        default: /* Reserved: we can't know instruction or data. */
+                return false;
+        }
+}
+/* Which cache CCSIDR represents depends on CSSELR value. */
+static u32 get_ccsidr(u32 csselr)
+{
+        u32 ccsidr;
+        /* Make sure noone else changes CSSELR during this! */
+        local_irq_disable();
+        /* Put value into CSSELR */
+        asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+        isb();
+        /* Read result out of CCSIDR */
+        asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+        local_irq_enable();
+        return ccsidr;
+}
+static int demux_c15_get(u64 id, void __user *uaddr)
+{
+        u32 val;
+        u32 __user *uval = uaddr;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+                return put_user(get_ccsidr(val), uval);
+        default:
+                return -ENOENT;
+        }
+}
+static int demux_c15_set(u64 id, void __user *uaddr)
+{
+        u32 val, newval;
+        u32 __user *uval = uaddr;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+                if (get_user(newval, uval))
+                        return -EFAULT;
+                /* This is also invariant: you can't change it. */
+                if (newval != get_ccsidr(val))
+                        return -EINVAL;
+                return 0;
+        default:
+                return -ENOENT;
+        }
+}
+#ifdef CONFIG_VFPv3
+static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
+                                   KVM_REG_ARM_VFP_FPSCR,
+                                   KVM_REG_ARM_VFP_FPINST,
+                                   KVM_REG_ARM_VFP_FPINST2,
+                                   KVM_REG_ARM_VFP_MVFR0,
+                                   KVM_REG_ARM_VFP_MVFR1,
+                                   KVM_REG_ARM_VFP_FPSID };
+static unsigned int num_fp_regs(void)
+{
+        if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
+                return 32;
+        else
+                return 16;
+}
+static unsigned int num_vfp_regs(void)
+{
+        /* Normal FP regs + control regs. */
+        return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
+}
+static int copy_vfp_regids(u64 __user *uindices)
+{
+        unsigned int i;
+        const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
+        const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
+        for (i = 0; i < num_fp_regs(); i++) {
+                if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
+                             uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
+                if (put_user(u32reg | vfp_sysregs[i], uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return num_vfp_regs();
+}
+static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
+{
+        u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
+        u32 val;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        if (vfpid < num_fp_regs()) {
+                if (KVM_REG_SIZE(id) != 8)
+                        return -ENOENT;
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
+                                   id);
+        }
+        /* FP control registers are all 32 bit. */
+        if (KVM_REG_SIZE(id) != 4)
+                return -ENOENT;
+        switch (vfpid) {
+        case KVM_REG_ARM_VFP_FPEXC:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
+        case KVM_REG_ARM_VFP_FPSCR:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
+        case KVM_REG_ARM_VFP_FPINST:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
+        case KVM_REG_ARM_VFP_FPINST2:
+                return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
+        case KVM_REG_ARM_VFP_MVFR0:
+                val = fmrx(MVFR0);
+                return reg_to_user(uaddr, &val, id);
+        case KVM_REG_ARM_VFP_MVFR1:
+                val = fmrx(MVFR1);
+                return reg_to_user(uaddr, &val, id);
+        case KVM_REG_ARM_VFP_FPSID:
+                val = fmrx(FPSID);
+                return reg_to_user(uaddr, &val, id);
+        default:
+                return -ENOENT;
+        }
+}
+static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
+{
+        u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
+        u32 val;
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+        if (vfpid < num_fp_regs()) {
+                if (KVM_REG_SIZE(id) != 8)
+                        return -ENOENT;
+                return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
+                                     uaddr, id);
+        }
+        /* FP control registers are all 32 bit. */
+        if (KVM_REG_SIZE(id) != 4)
+                return -ENOENT;
+        switch (vfpid) {
+        case KVM_REG_ARM_VFP_FPEXC:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
+        case KVM_REG_ARM_VFP_FPSCR:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
+        case KVM_REG_ARM_VFP_FPINST:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
+        case KVM_REG_ARM_VFP_FPINST2:
+                return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
+        /* These are invariant. */
+        case KVM_REG_ARM_VFP_MVFR0:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(MVFR0))
+                        return -EINVAL;
+                return 0;
+        case KVM_REG_ARM_VFP_MVFR1:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(MVFR1))
+                        return -EINVAL;
+                return 0;
+        case KVM_REG_ARM_VFP_FPSID:
+                if (reg_from_user(&val, uaddr, id))
+                        return -EFAULT;
+                if (val != fmrx(FPSID))
+                        return -EINVAL;
+                return 0;
+        default:
+                return -ENOENT;
+        }
+}
+#else /* !CONFIG_VFPv3 */
+static unsigned int num_vfp_regs(void)
+{
+        return 0;
+}
+static int copy_vfp_regids(u64 __user *uindices)
+{
+        return 0;
+}
+static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
+{
+        return -ENOENT;
+}
+static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
+{
+        return -ENOENT;
+}
+#endif /* !CONFIG_VFPv3 */
+int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct coproc_reg *r;
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_get(reg->id, uaddr);
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
+                return vfp_get_reg(vcpu, reg->id, uaddr);
+        r = index_to_coproc_reg(vcpu, reg->id);
+        if (!r)
+                return get_invariant_cp15(reg->id, uaddr);
+        /* Note: copies two regs if size is 64 bit. */
+        return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
+}
+int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct coproc_reg *r;
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_set(reg->id, uaddr);
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
+                return vfp_set_reg(vcpu, reg->id, uaddr);
+        r = index_to_coproc_reg(vcpu, reg->id);
+        if (!r)
+                return set_invariant_cp15(reg->id, uaddr);
+        /* Note: copies two regs if size is 64 bit */
+        return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
+}
+static unsigned int num_demux_regs(void)
+{
+        unsigned int i, count = 0;
+        for (i = 0; i < CSSELR_MAX; i++)
+                if (is_valid_cache(i))
+                        count++;
+        return count;
+}
+static int write_demux_regids(u64 __user *uindices)
+{
+        u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
+        unsigned int i;
+        val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
+        for (i = 0; i < CSSELR_MAX; i++) {
+                if (!is_valid_cache(i))
+                        continue;
+                if (put_user(val | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return 0;
+}
+static u64 cp15_to_index(const struct coproc_reg *reg)
+{
+        u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
+        if (reg->is_64) {
+                val |= KVM_REG_SIZE_U64;
+                val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
+                val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
+        } else {
+                val |= KVM_REG_SIZE_U32;
+                val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
+                val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
+                val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
+                val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
+        }
+        return val;
+}
+static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
+{
+        if (!*uind)
+                return true;
+        if (put_user(cp15_to_index(reg), *uind))
+                return false;
+        (*uind)++;
+        return true;
+}
+/* Assumed ordered tables, see kvm_coproc_table_init. */
+static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
+{
+        const struct coproc_reg *i1, *i2, *end1, *end2;
+        unsigned int total = 0;
+        size_t num;
+        /* We check for duplicates here, to allow arch-specific overrides. */
+        i1 = get_target_table(vcpu->arch.target, &num);
+        end1 = i1 + num;
+        i2 = cp15_regs;
+        end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
+        BUG_ON(i1 == end1 || i2 == end2);
+        /* Walk carefully, as both tables may refer to the same register. */
+        while (i1 || i2) {
+                int cmp = cmp_reg(i1, i2);
+                /* target-specific overrides generic entry. */
+                if (cmp <= 0) {
+                        /* Ignore registers we trap but don't save. */
+                        if (i1->reg) {
+                                if (!copy_reg_to_user(i1, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                } else {
+                        /* Ignore registers we trap but don't save. */
+                        if (i2->reg) {
+                                if (!copy_reg_to_user(i2, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                }
+                if (cmp <= 0 && ++i1 == end1)
+                        i1 = NULL;
+                if (cmp >= 0 && ++i2 == end2)
+                        i2 = NULL;
+        }
+        return total;
+}
+unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
+{
+        return ARRAY_SIZE(invariant_cp15)
+                + num_demux_regs()
+                + num_vfp_regs()
+                + walk_cp15(vcpu, (u64 __user *)NULL);
+}
+int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        int err;
+        /* Then give them all the invariant registers' indices. */
+        for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
+                if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        err = walk_cp15(vcpu, uindices);
+        if (err < 0)
+                return err;
+        uindices += err;
+        err = copy_vfp_regids(uindices);
+        if (err < 0)
+                return err;
+        uindices += err;
+        return write_demux_regids(uindices);
+}
+void kvm_coproc_table_init(void)
+{
+        unsigned int i;
+        /* Make sure tables are unique and in order. */
+        for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
+                BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
+        /* We abuse the reset function to overwrite the table itself. */
+        for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
+                invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
+        /*
+         * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
+         *
+         *   If software reads the Cache Type fields from Ctype1
+         *   upwards, once it has seen a value of 0b000, no caches
+         *   exist at further-out levels of the hierarchy. So, for
+         *   example, if Ctype3 is the first Cache Type field with a
+         *   value of 0b000, the values of Ctype4 to Ctype7 must be
+         *   ignored.
+         */
+        asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
+        for (i = 0; i < 7; i++)
+                if (((cache_levels >> (i*3)) & 7) == 0)
+                        break;
+        /* Clear all higher bits. */
+        cache_levels &= (1 << (i*3))-1;
+}
+/**
+ * kvm_reset_coprocs - sets cp15 registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architecturally defined reset values.
+ */
+void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
+{
+        size_t num;
+        const struct coproc_reg *table;
+        /* Catch someone adding a register without putting in reset entry. */
+        memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
+        /* Generic chip reset first (so target could override). */
+        reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
+        table = get_target_table(vcpu->arch.target, &num);
+        reset_coproc_regs(vcpu, table, num);
+        for (num = 1; num < NR_CP15_REGS; num++)
+                if (vcpu->arch.cp15[num] == 0x42424242)
+                        panic("Didn't reset vcpu->arch.cp15[%zi]", num);
+}
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
new file mode 100644
index 000000000000..992adfafa2ff
--- /dev/null
+++ b/arch/arm/kvm/coproc.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ARM_KVM_COPROC_LOCAL_H__
+#define __ARM_KVM_COPROC_LOCAL_H__
+struct coproc_params {
+        unsigned long CRn;
+        unsigned long CRm;
+        unsigned long Op1;
+        unsigned long Op2;
+        unsigned long Rt1;
+        unsigned long Rt2;
+        bool is_64bit;
+        bool is_write;
+};
+struct coproc_reg {
+        /* MRC/MCR/MRRC/MCRR instruction which accesses it. */
+        unsigned long CRn;
+        unsigned long CRm;
+        unsigned long Op1;
+        unsigned long Op2;
+        bool is_64;
+        /* Trapped access from guest, if non-NULL. */
+        bool (*access)(struct kvm_vcpu *,
+                       const struct coproc_params *,
+                       const struct coproc_reg *);
+        /* Initialization for vcpu. */
+        void (*reset)(struct kvm_vcpu *, const struct coproc_reg *);
+        /* Index into vcpu->arch.cp15[], or 0 if we don't need to save it. */
+        unsigned long reg;
+        /* Value (usually reset value) */
+        u64 val;
+};
+static inline void print_cp_instr(const struct coproc_params *p)
+{
+        /* Look, we even formatted it for you to paste into the table! */
+        if (p->is_64bit) {
+                kvm_pr_unimpl(" { CRm(%2lu), Op1(%2lu), is64, func_%s },\n",
+                              p->CRm, p->Op1, p->is_write ? "write" : "read");
+        } else {
+                kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32,"
+                              " func_%s },\n",
+                              p->CRn, p->CRm, p->Op1, p->Op2,
+                              p->is_write ? "write" : "read");
+        }
+}
+static inline bool ignore_write(struct kvm_vcpu *vcpu,
+                                const struct coproc_params *p)
+{
+        return true;
+}
+static inline bool read_zero(struct kvm_vcpu *vcpu,
+                             const struct coproc_params *p)
+{
+        *vcpu_reg(vcpu, p->Rt1) = 0;
+        return true;
+}
+static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
+                                      const struct coproc_params *params)
+{
+        kvm_debug("CP15 write to read-only register at: %08x\n",
+                  *vcpu_pc(vcpu));
+        print_cp_instr(params);
+        return false;
+}
+static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
+                                        const struct coproc_params *params)
+{
+        kvm_debug("CP15 read to write-only register at: %08x\n",
+                  *vcpu_pc(vcpu));
+        print_cp_instr(params);
+        return false;
+}
+/* Reset functions */
+static inline void reset_unknown(struct kvm_vcpu *vcpu,
+                                 const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = 0xdecafbad;
+}
+static inline void reset_val(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = r->val;
+}
+static inline void reset_unknown64(struct kvm_vcpu *vcpu,
+                                   const struct coproc_reg *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg + 1 >= ARRAY_SIZE(vcpu->arch.cp15));
+        vcpu->arch.cp15[r->reg] = 0xdecafbad;
+        vcpu->arch.cp15[r->reg+1] = 0xd0c0ffee;
+}
+static inline int cmp_reg(const struct coproc_reg *i1,
+                          const struct coproc_reg *i2)
+{
+        BUG_ON(i1 == i2);
+        if (!i1)
+                return 1;
+        else if (!i2)
+                return -1;
+        if (i1->CRn != i2->CRn)
+                return i1->CRn - i2->CRn;
+        if (i1->CRm != i2->CRm)
+                return i1->CRm - i2->CRm;
+        if (i1->Op1 != i2->Op1)
+                return i1->Op1 - i2->Op1;
+        return i1->Op2 - i2->Op2;
+}
+#define CRn(_x)         .CRn = _x
+#define CRm(_x)         .CRm = _x
+#define Op1(_x)         .Op1 = _x
+#define Op2(_x)         .Op2 = _x
+#define is64            .is_64 = true
+#define is32            .is_64 = false
+#endif /* __ARM_KVM_COPROC_LOCAL_H__ */
diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c
new file mode 100644
index 000000000000..685063a6d0cf
--- /dev/null
+++ b/arch/arm/kvm/coproc_a15.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/kvm_host.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <linux/init.h>
+static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        /*
+         * Compute guest MPIDR:
+         * (Even if we present only one VCPU to the guest on an SMP
+         * host we don't set the U bit in the MPIDR, or vice versa, as
+         * revealing the underlying hardware properties is likely to
+         * be the best choice).
+         */
+        vcpu->arch.cp15[c0_MPIDR] = (read_cpuid_mpidr() & ~MPIDR_LEVEL_MASK)
+                | (vcpu->vcpu_id & MPIDR_LEVEL_MASK);
+}
+#include "coproc.h"
+/* A15 TRM 4.3.28: RO WI */
+static bool access_actlr(struct kvm_vcpu *vcpu,
+                         const struct coproc_params *p,
+                         const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR];
+        return true;
+}
+/* A15 TRM 4.3.60: R/O. */
+static bool access_cbar(struct kvm_vcpu *vcpu,
+                        const struct coproc_params *p,
+                        const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return write_to_read_only(vcpu, p);
+        return read_zero(vcpu, p);
+}
+/* A15 TRM 4.3.48: R/O WI. */
+static bool access_l2ctlr(struct kvm_vcpu *vcpu,
+                          const struct coproc_params *p,
+                          const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR];
+        return true;
+}
+static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        u32 l2ctlr, ncores;
+        asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+        l2ctlr &= ~(3 << 24);
+        ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
+        l2ctlr |= (ncores & 3) << 24;
+        vcpu->arch.cp15[c9_L2CTLR] = l2ctlr;
+}
+static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
+{
+        u32 actlr;
+        /* ACTLR contains SMP bit: make sure you create all cpus first! */
+        asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
+        /* Make the SMP bit consistent with the guest configuration */
+        if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
+                actlr |= 1U << 6;
+        else
+                actlr &= ~(1U << 6);
+        vcpu->arch.cp15[c1_ACTLR] = actlr;
+}
+/* A15 TRM 4.3.49: R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). */
+static bool access_l2ectlr(struct kvm_vcpu *vcpu,
+                           const struct coproc_params *p,
+                           const struct coproc_reg *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        *vcpu_reg(vcpu, p->Rt1) = 0;
+        return true;
+}
+/*
+ * A15-specific CP15 registers.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
+ */
+static const struct coproc_reg a15_regs[] = {
+        /* MPIDR: we use VMPIDR for guest access. */
+        { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
+                        NULL, reset_mpidr, c0_MPIDR },
+        /* SCTLR: swapped by interrupt.S. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
+                        NULL, reset_val, c1_SCTLR, 0x00C50078 },
+        /* ACTLR: trapped by HCR.TAC bit. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
+                        access_actlr, reset_actlr, c1_ACTLR },
+        /* CPACR: swapped by interrupt.S. */
+        { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
+                        NULL, reset_val, c1_CPACR, 0x00000000 },
+        /*
+         * L2CTLR access (guest wants to know #CPUs).
+         */
+        { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
+                        access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
+        { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
+        /* The Configuration Base Address Register. */
+        { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
+};
+static struct kvm_coproc_target_table a15_target_table = {
+        .target = KVM_ARM_TARGET_CORTEX_A15,
+        .table = a15_regs,
+        .num = ARRAY_SIZE(a15_regs),
+};
+static int __init coproc_a15_init(void)
+{
+        unsigned int i;
+        for (i = 1; i < ARRAY_SIZE(a15_regs); i++)
+                BUG_ON(cmp_reg(&a15_regs[i-1],
+                               &a15_regs[i]) >= 0);
+        kvm_register_target_coproc_table(&a15_target_table);
+        return 0;
+}
+late_initcall(coproc_a15_init);
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
new file mode 100644
index 000000000000..d61450ac6665
--- /dev/null
+++ b/arch/arm/kvm/emulate.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_emulate.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+#define VCPU_NR_MODES           6
+#define VCPU_REG_OFFSET_USR     0
+#define VCPU_REG_OFFSET_FIQ     1
+#define VCPU_REG_OFFSET_IRQ     2
+#define VCPU_REG_OFFSET_SVC     3
+#define VCPU_REG_OFFSET_ABT     4
+#define VCPU_REG_OFFSET_UND     5
+#define REG_OFFSET(_reg) \
+        (offsetof(struct kvm_regs, _reg) / sizeof(u32))
+#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
+static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
+        /* USR/SYS Registers */
+        [VCPU_REG_OFFSET_USR] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
+        },
+        /* FIQ Registers */
+        [VCPU_REG_OFFSET_FIQ] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7),
+                REG_OFFSET(fiq_regs[0]), /* r8 */
+                REG_OFFSET(fiq_regs[1]), /* r9 */
+                REG_OFFSET(fiq_regs[2]), /* r10 */
+                REG_OFFSET(fiq_regs[3]), /* r11 */
+                REG_OFFSET(fiq_regs[4]), /* r12 */
+                REG_OFFSET(fiq_regs[5]), /* r13 */
+                REG_OFFSET(fiq_regs[6]), /* r14 */
+        },
+        /* IRQ Registers */
+        [VCPU_REG_OFFSET_IRQ] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(irq_regs[0]), /* r13 */
+                REG_OFFSET(irq_regs[1]), /* r14 */
+        },
+        /* SVC Registers */
+        [VCPU_REG_OFFSET_SVC] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(svc_regs[0]), /* r13 */
+                REG_OFFSET(svc_regs[1]), /* r14 */
+        },
+        /* ABT Registers */
+        [VCPU_REG_OFFSET_ABT] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(abt_regs[0]), /* r13 */
+                REG_OFFSET(abt_regs[1]), /* r14 */
+        },
+        /* UND Registers */
+        [VCPU_REG_OFFSET_UND] = {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(und_regs[0]), /* r13 */
+                REG_OFFSET(und_regs[1]), /* r14 */
+        },
+};
+/*
+ * Return a pointer to the register number valid in the current mode of
+ * the virtual CPU.
+ */
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
+{
+        u32 *reg_array = (u32 *)&vcpu->arch.regs;
+        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        switch (mode) {
+        case USR_MODE...SVC_MODE:
+                mode &= ~MODE32_BIT; /* 0 ... 3 */
+                break;
+        case ABT_MODE:
+                mode = VCPU_REG_OFFSET_ABT;
+                break;
+        case UND_MODE:
+                mode = VCPU_REG_OFFSET_UND;
+                break;
+        case SYSTEM_MODE:
+                mode = VCPU_REG_OFFSET_USR;
+                break;
+        default:
+                BUG();
+        }
+        return reg_array + vcpu_reg_offsets[mode][reg_num];
+}
+/*
+ * Return the SPSR for the current mode of the virtual CPU.
+ */
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
+{
+        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        switch (mode) {
+        case SVC_MODE:
+                return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
+        case ABT_MODE:
+                return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
+        case UND_MODE:
+                return &vcpu->arch.regs.KVM_ARM_UND_spsr;
+        case IRQ_MODE:
+                return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
+        case FIQ_MODE:
+                return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
+        default:
+                BUG();
+        }
+}
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu:       the vcpu pointer
+ * @run:        the kvm_run structure pointer
+ *
+ * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
+ * halt execution of world-switches and schedule other host processes until
+ * there is an incoming IRQ or FIQ to the VM.
+ */
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_wfi(*vcpu_pc(vcpu));
+        kvm_vcpu_block(vcpu);
+        return 1;
+}
+/**
+ * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
+ * @vcpu:       The VCPU pointer
+ *
+ * When exceptions occur while instructions are executed in Thumb IF-THEN
+ * blocks, the ITSTATE field of the CPSR is not advanved (updated), so we have
+ * to do this little bit of work manually. The fields map like this:
+ *
+ * IT[7:0] -> CPSR[26:25],CPSR[15:10]
+ */
+static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
+{
+        unsigned long itbits, cond;
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
+        bool is_arm = !(cpsr & PSR_T_BIT);
+        BUG_ON(is_arm && (cpsr & PSR_IT_MASK));
+        if (!(cpsr & PSR_IT_MASK))
+                return;
+        cond = (cpsr & 0xe000) >> 13;
+        itbits = (cpsr & 0x1c00) >> (10 - 2);
+        itbits |= (cpsr & (0x3 << 25)) >> 25;
+        /* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */
+        if ((itbits & 0x7) == 0)
+                itbits = cond = 0;
+        else
+                itbits = (itbits << 1) & 0x1f;
+        cpsr &= ~PSR_IT_MASK;
+        cpsr |= cond << 13;
+        cpsr |= (itbits & 0x1c) << (10 - 2);
+        cpsr |= (itbits & 0x3) << 25;
+        *vcpu_cpsr(vcpu) = cpsr;
+}
+/**
+ * kvm_skip_instr - skip a trapped instruction and proceed to the next
+ * @vcpu: The vcpu pointer
+ */
+void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+        bool is_thumb;
+        is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_T_BIT);
+        if (is_thumb && !is_wide_instr)
+                *vcpu_pc(vcpu) += 2;
+        else
+                *vcpu_pc(vcpu) += 4;
+        kvm_adjust_itstate(vcpu);
+}
+/******************************************************************************
+ * Inject exceptions into the guest
+ */
+static u32 exc_vector_base(struct kvm_vcpu *vcpu)
+{
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        u32 vbar = vcpu->arch.cp15[c12_VBAR];
+        if (sctlr & SCTLR_V)
+                return 0xffff0000;
+        else /* always have security exceptions */
+                return vbar;
+}
+/**
+ * kvm_inject_undefined - inject an undefined exception into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ *
+ * Modelled after TakeUndefInstrException() pseudocode.
+ */
+void kvm_inject_undefined(struct kvm_vcpu *vcpu)
+{
+        u32 new_lr_value;
+        u32 new_spsr_value;
+        u32 cpsr = *vcpu_cpsr(vcpu);
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        bool is_thumb = (cpsr & PSR_T_BIT);
+        u32 vect_offset = 4;
+        u32 return_offset = (is_thumb) ? 2 : 4;
+        new_spsr_value = cpsr;
+        new_lr_value = *vcpu_pc(vcpu) - return_offset;
+        *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | UND_MODE;
+        *vcpu_cpsr(vcpu) |= PSR_I_BIT;
+        *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
+        if (sctlr & SCTLR_TE)
+                *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+        if (sctlr & SCTLR_EE)
+                *vcpu_cpsr(vcpu) |= PSR_E_BIT;
+        /* Note: These now point to UND banked copies */
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_reg(vcpu, 14) = new_lr_value;
+        /* Branch to exception vector */
+        *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
+}
+/*
+ * Modelled after TakeDataAbortException() and TakePrefetchAbortException
+ * pseudocode.
+ */
+static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
+{
+        u32 new_lr_value;
+        u32 new_spsr_value;
+        u32 cpsr = *vcpu_cpsr(vcpu);
+        u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
+        bool is_thumb = (cpsr & PSR_T_BIT);
+        u32 vect_offset;
+        u32 return_offset = (is_thumb) ? 4 : 0;
+        bool is_lpae;
+        new_spsr_value = cpsr;
+        new_lr_value = *vcpu_pc(vcpu) + return_offset;
+        *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | ABT_MODE;
+        *vcpu_cpsr(vcpu) |= PSR_I_BIT | PSR_A_BIT;
+        *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
+        if (sctlr & SCTLR_TE)
+                *vcpu_cpsr(vcpu) |= PSR_T_BIT;
+        if (sctlr & SCTLR_EE)
+                *vcpu_cpsr(vcpu) |= PSR_E_BIT;
+        /* Note: These now point to ABT banked copies */
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_reg(vcpu, 14) = new_lr_value;
+        if (is_pabt)
+                vect_offset = 12;
+        else
+                vect_offset = 16;
+        /* Branch to exception vector */
+        *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
+        if (is_pabt) {
+                /* Set DFAR and DFSR */
+                vcpu->arch.cp15[c6_IFAR] = addr;
+                is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
+                /* Always give debug fault for now - should give guest a clue */
+                if (is_lpae)
+                        vcpu->arch.cp15[c5_IFSR] = 1 << 9 | 0x22;
+                else
+                        vcpu->arch.cp15[c5_IFSR] = 2;
+        } else { /* !iabt */
+                /* Set DFAR and DFSR */
+                vcpu->arch.cp15[c6_DFAR] = addr;
+                is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
+                /* Always give debug fault for now - should give guest a clue */
+                if (is_lpae)
+                        vcpu->arch.cp15[c5_DFSR] = 1 << 9 | 0x22;
+                else
+                        vcpu->arch.cp15[c5_DFSR] = 2;
+        }
+}
+/**
+ * kvm_inject_dabt - inject a data abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        inject_abt(vcpu, false, addr);
+}
+/**
+ * kvm_inject_pabt - inject a prefetch abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        inject_abt(vcpu, true, addr);
+}
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
new file mode 100644
index 000000000000..2339d9609d36
--- /dev/null
+++ b/arch/arm/kvm/guest.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
+#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+        { NULL }
+};
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+        return 0;
+}
+static u64 core_reg_offset_from_id(u64 id)
+{
+        return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
+static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+        struct kvm_regs *regs = &vcpu->arch.regs;
+        u64 off;
+        if (KVM_REG_SIZE(reg->id) != 4)
+                return -ENOENT;
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+                return -ENOENT;
+        return put_user(((u32 *)regs)[off], uaddr);
+}
+static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        u32 __user *uaddr = (u32 __user *)(long)reg->addr;
+        struct kvm_regs *regs = &vcpu->arch.regs;
+        u64 off, val;
+        if (KVM_REG_SIZE(reg->id) != 4)
+                return -ENOENT;
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
+                return -ENOENT;
+        if (get_user(val, uaddr) != 0)
+                return -EFAULT;
+        if (off == KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr)) {
+                unsigned long mode = val & MODE_MASK;
+                switch (mode) {
+                case USR_MODE:
+                case FIQ_MODE:
+                case IRQ_MODE:
+                case SVC_MODE:
+                case ABT_MODE:
+                case UND_MODE:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        }
+        ((u32 *)regs)[off] = val;
+        return 0;
+}
+int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+static unsigned long num_core_regs(void)
+{
+        return sizeof(struct kvm_regs) / sizeof(u32);
+}
+/**
+ * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
+ *
+ * This is for all registers.
+ */
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
+{
+        return num_core_regs() + kvm_arm_num_coproc_regs(vcpu);
+}
+/**
+ * kvm_arm_copy_reg_indices - get indices of all registers.
+ *
+ * We do core registers right here, then we apppend coproc regs.
+ */
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        const u64 core_reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE;
+        for (i = 0; i < sizeof(struct kvm_regs)/sizeof(u32); i++) {
+                if (put_user(core_reg | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return kvm_arm_copy_coproc_indices(vcpu, uindices);
+}
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
+                return -EINVAL;
+        /* Register group 16 means we want a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return get_core_reg(vcpu, reg);
+        return kvm_arm_coproc_get_reg(vcpu, reg);
+}
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
+                return -EINVAL;
+        /* Register group 16 means we set a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return set_core_reg(vcpu, reg);
+        return kvm_arm_coproc_set_reg(vcpu, reg);
+}
+int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init)
+{
+        unsigned int i;
+        /* We can only do a cortex A15 for now. */
+        if (init->target != kvm_target_cpu())
+                return -EINVAL;
+        vcpu->arch.target = init->target;
+        bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES);
+        /* -ENOENT for unknown features, -EINVAL for invalid combinations. */
+        for (i = 0; i < sizeof(init->features) * 8; i++) {
+                if (test_bit(i, (void *)init->features)) {
+                        if (i >= KVM_VCPU_MAX_FEATURES)
+                                return -ENOENT;
+                        set_bit(i, vcpu->arch.features);
+                }
+        }
+        /* Now we know what it is, we can reset it. */
+        return kvm_reset_vcpu(vcpu);
+}
+int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
+                                  struct kvm_translation *tr)
+{
+        return -EINVAL;
+}
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
new file mode 100644
index 000000000000..9f37a79b880b
--- /dev/null
+++ b/arch/arm/kvm/init.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/linkage.h>
+#include <asm/unified.h>
+#include <asm/asm-offsets.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+/********************************************************************
+ * Hypervisor initialization
+ *   - should be called with:
+ *       r0,r1 = Hypervisor pgd pointer
+ *       r2 = top of Hyp stack (kernel VA)
+ *       r3 = pointer to hyp vectors
+ */
+        .text
+        .pushsection    .hyp.idmap.text,"ax"
+        .align 5
+__kvm_hyp_init:
+        .globl __kvm_hyp_init
+        @ Hyp-mode exception vector
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    .
+        W(b)    __do_hyp_init
+        W(b)    .
+        W(b)    .
+__do_hyp_init:
+        @ Set the HTTBR to point to the hypervisor PGD pointer passed
+        mcrr    p15, 4, r0, r1, c2
+        @ Set the HTCR and VTCR to the same shareability and cacheability
+        @ settings as the non-secure TTBCR and with T0SZ == 0.
+        mrc     p15, 4, r0, c2, c0, 2   @ HTCR
+        ldr     r12, =HTCR_MASK
+        bic     r0, r0, r12
+        mrc     p15, 0, r1, c2, c0, 2   @ TTBCR
+        and     r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
+        orr     r0, r0, r1
+        mcr     p15, 4, r0, c2, c0, 2   @ HTCR
+        mrc     p15, 4, r1, c2, c1, 2   @ VTCR
+        ldr     r12, =VTCR_MASK
+        bic     r1, r1, r12
+        bic     r0, r0, #(~VTCR_HTCR_SH)        @ clear non-reusable HTCR bits
+        orr     r1, r0, r1
+        orr     r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S)
+        mcr     p15, 4, r1, c2, c1, 2   @ VTCR
+        @ Use the same memory attributes for hyp. accesses as the kernel
+        @ (copy MAIRx ro HMAIRx).
+        mrc     p15, 0, r0, c10, c2, 0
+        mcr     p15, 4, r0, c10, c2, 0
+        mrc     p15, 0, r0, c10, c2, 1
+        mcr     p15, 4, r0, c10, c2, 1
+        @ Set the HSCTLR to:
+        @  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
+        @  - Endianness: Kernel config
+        @  - Fast Interrupt Features: Kernel config
+        @  - Write permission implies XN: disabled
+        @  - Instruction cache: enabled
+        @  - Data/Unified cache: enabled
+        @  - Memory alignment checks: enabled
+        @  - MMU: enabled (this code must be run from an identity mapping)
+        mrc     p15, 4, r0, c1, c0, 0   @ HSCR
+        ldr     r12, =HSCTLR_MASK
+        bic     r0, r0, r12
+        mrc     p15, 0, r1, c1, c0, 0   @ SCTLR
+        ldr     r12, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
+        and     r1, r1, r12
+ ARM(   ldr     r12, =(HSCTLR_M | HSCTLR_A)                     )
+ THUMB( ldr     r12, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)         )
+        orr     r1, r1, r12
+        orr     r0, r0, r1
+        isb
+        mcr     p15, 4, r0, c1, c0, 0   @ HSCR
+        isb
+        @ Set stack pointer and return to the kernel
+        mov     sp, r2
+        @ Set HVBAR to point to the HYP vectors
+        mcr     p15, 4, r3, c12, c0, 0  @ HVBAR
+        eret
+        .ltorg
+        .globl __kvm_hyp_init_end
+__kvm_hyp_init_end:
+        .popsection
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
new file mode 100644
index 000000000000..8ca87ab0919d
--- /dev/null
+++ b/arch/arm/kvm/interrupts.S
@@ -0,0 +1,484 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/unified.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/vfpmacros.h>
+#include "interrupts_head.S"
+        .text
+__kvm_hyp_code_start:
+        .globl __kvm_hyp_code_start
+/********************************************************************
+ * Flush per-VMID TLBs
+ *
+ * void __kvm_tlb_flush_vmid(struct kvm *kvm);
+ *
+ * We rely on the hardware to broadcast the TLB invalidation to all CPUs
+ * inside the inner-shareable domain (which is the case for all v7
+ * implementations).  If we come across a non-IS SMP implementation, we'll
+ * have to use an IPI based mechanism. Until then, we stick to the simple
+ * hardware assisted version.
+ */
+ENTRY(__kvm_tlb_flush_vmid)
+        push    {r2, r3}
+        add     r0, r0, #KVM_VTTBR
+        ldrd    r2, r3, [r0]
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        isb
+        mcr     p15, 0, r0, c8, c3, 0   @ TLBIALLIS (rt ignored)
+        dsb
+        isb
+        mov     r2, #0
+        mov     r3, #0
+        mcrr    p15, 6, r2, r3, c2      @ Back to VMID #0
+        isb                             @ Not necessary if followed by eret
+        pop     {r2, r3}
+        bx      lr
+ENDPROC(__kvm_tlb_flush_vmid)
+/********************************************************************
+ * Flush TLBs and instruction caches of all CPUs inside the inner-shareable
+ * domain, for all VMIDs
+ *
+ * void __kvm_flush_vm_context(void);
+ */
+ENTRY(__kvm_flush_vm_context)
+        mov     r0, #0                  @ rn parameter for c15 flushes is SBZ
+        /* Invalidate NS Non-Hyp TLB Inner Shareable (TLBIALLNSNHIS) */
+        mcr     p15, 4, r0, c8, c3, 4
+        /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */
+        mcr     p15, 0, r0, c7, c1, 0
+        dsb
+        isb                             @ Not necessary if followed by eret
+        bx      lr
+ENDPROC(__kvm_flush_vm_context)
+/********************************************************************
+ *  Hypervisor world-switch code
+ *
+ *
+ * int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
+ */
+ENTRY(__kvm_vcpu_run)
+        @ Save the vcpu pointer
+        mcr     p15, 4, vcpu, c13, c0, 2        @ HTPIDR
+        save_host_regs
+        restore_vgic_state
+        restore_timer_state
+        @ Store hardware CP15 state and load guest state
+        read_cp15_state store_to_vcpu = 0
+        write_cp15_state read_from_vcpu = 1
+        @ If the host kernel has not been configured with VFPv3 support,
+        @ then it is safer if we deny guests from using it as well.
+#ifdef CONFIG_VFPv3
+        @ Set FPEXC_EN so the guest doesn't trap floating point instructions
+        VFPFMRX r2, FPEXC               @ VMRS
+        push    {r2}
+        orr     r2, r2, #FPEXC_EN
+        VFPFMXR FPEXC, r2               @ VMSR
+#endif
+        @ Configure Hyp-role
+        configure_hyp_role vmentry
+        @ Trap coprocessor CRx accesses
+        set_hstr vmentry
+        set_hcptr vmentry, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+        set_hdcr vmentry
+        @ Write configured ID register into MIDR alias
+        ldr     r1, [vcpu, #VCPU_MIDR]
+        mcr     p15, 4, r1, c0, c0, 0
+        @ Write guest view of MPIDR into VMPIDR
+        ldr     r1, [vcpu, #CP15_OFFSET(c0_MPIDR)]
+        mcr     p15, 4, r1, c0, c0, 5
+        @ Set up guest memory translation
+        ldr     r1, [vcpu, #VCPU_KVM]
+        add     r1, r1, #KVM_VTTBR
+        ldrd    r2, r3, [r1]
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        @ We're all done, just restore the GPRs and go to the guest
+        restore_guest_regs
+        clrex                           @ Clear exclusive monitor
+        eret
+__kvm_vcpu_return:
+        /*
+         * return convention:
+         * guest r0, r1, r2 saved on the stack
+         * r0: vcpu pointer
+         * r1: exception code
+         */
+        save_guest_regs
+        @ Set VMID == 0
+        mov     r2, #0
+        mov     r3, #0
+        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
+        @ Don't trap coprocessor accesses for host kernel
+        set_hstr vmexit
+        set_hdcr vmexit
+        set_hcptr vmexit, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+#ifdef CONFIG_VFPv3
+        @ Save floating point registers we if let guest use them.
+        tst     r2, #(HCPTR_TCP(10) | HCPTR_TCP(11))
+        bne     after_vfp_restore
+        @ Switch VFP/NEON hardware state to the host's
+        add     r7, vcpu, #VCPU_VFP_GUEST
+        store_vfp_state r7
+        add     r7, vcpu, #VCPU_VFP_HOST
+        ldr     r7, [r7]
+        restore_vfp_state r7
+after_vfp_restore:
+        @ Restore FPEXC_EN which we clobbered on entry
+        pop     {r2}
+        VFPFMXR FPEXC, r2
+#endif
+        @ Reset Hyp-role
+        configure_hyp_role vmexit
+        @ Let host read hardware MIDR
+        mrc     p15, 0, r2, c0, c0, 0
+        mcr     p15, 4, r2, c0, c0, 0
+        @ Back to hardware MPIDR
+        mrc     p15, 0, r2, c0, c0, 5
+        mcr     p15, 4, r2, c0, c0, 5
+        @ Store guest CP15 state and restore host state
+        read_cp15_state store_to_vcpu = 1
+        write_cp15_state read_from_vcpu = 0
+        save_timer_state
+        save_vgic_state
+        restore_host_regs
+        clrex                           @ Clear exclusive monitor
+        mov     r0, r1                  @ Return the return code
+        mov     r1, #0                  @ Clear upper bits in return value
+        bx      lr                      @ return to IOCTL
+/********************************************************************
+ *  Call function in Hyp mode
+ *
+ *
+ * u64 kvm_call_hyp(void *hypfn, ...);
+ *
+ * This is not really a variadic function in the classic C-way and care must
+ * be taken when calling this to ensure parameters are passed in registers
+ * only, since the stack will change between the caller and the callee.
+ *
+ * Call the function with the first argument containing a pointer to the
+ * function you wish to call in Hyp mode, and subsequent arguments will be
+ * passed as r0, r1, and r2 (a maximum of 3 arguments in addition to the
+ * function pointer can be passed).  The function being called must be mapped
+ * in Hyp mode (see init_hyp_mode in arch/arm/kvm/arm.c).  Return values are
+ * passed in r0 and r1.
+ *
+ * The calling convention follows the standard AAPCS:
+ *   r0 - r3: caller save
+ *   r12:     caller save
+ *   rest:    callee save
+ */
+ENTRY(kvm_call_hyp)
+        hvc     #0
+        bx      lr
+/********************************************************************
+ * Hypervisor exception vector and handlers
+ *
+ *
+ * The KVM/ARM Hypervisor ABI is defined as follows:
+ *
+ * Entry to Hyp mode from the host kernel will happen _only_ when an HVC
+ * instruction is issued since all traps are disabled when running the host
+ * kernel as per the Hyp-mode initialization at boot time.
+ *
+ * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc
+ * below) when the HVC instruction is called from SVC mode (i.e. a guest or the
+ * host kernel) and they cause a trap to the vector page + offset 0xc when HVC
+ * instructions are called from within Hyp-mode.
+ *
+ * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
+ *    Switching to Hyp mode is done through a simple HVC #0 instruction. The
+ *    exception vector code will check that the HVC comes from VMID==0 and if
+ *    so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
+ *    - r0 contains a pointer to a HYP function
+ *    - r1, r2, and r3 contain arguments to the above function.
+ *    - The HYP function will be called with its arguments in r0, r1 and r2.
+ *    On HYP function return, we return directly to SVC.
+ *
+ * Note that the above is used to execute code in Hyp-mode from a host-kernel
+ * point of view, and is a different concept from performing a world-switch and
+ * executing guest code SVC mode (with a VMID != 0).
+ */
+/* Handle undef, svc, pabt, or dabt by crashing with a user notice */
+.macro bad_exception exception_code, panic_str
+        push    {r0-r2}
+        mrrc    p15, 6, r0, r1, c2      @ Read VTTBR
+        lsr     r1, r1, #16
+        ands    r1, r1, #0xff
+        beq     99f
+        load_vcpu                       @ Load VCPU pointer
+        .if \exception_code == ARM_EXCEPTION_DATA_ABORT
+        mrc     p15, 4, r2, c5, c2, 0   @ HSR
+        mrc     p15, 4, r1, c6, c0, 0   @ HDFAR
+        str     r2, [vcpu, #VCPU_HSR]
+        str     r1, [vcpu, #VCPU_HxFAR]
+        .endif
+        .if \exception_code == ARM_EXCEPTION_PREF_ABORT
+        mrc     p15, 4, r2, c5, c2, 0   @ HSR
+        mrc     p15, 4, r1, c6, c0, 2   @ HIFAR
+        str     r2, [vcpu, #VCPU_HSR]
+        str     r1, [vcpu, #VCPU_HxFAR]
+        .endif
+        mov     r1, #\exception_code
+        b       __kvm_vcpu_return
+        @ We were in the host already. Let's craft a panic-ing return to SVC.
+99:     mrs     r2, cpsr
+        bic     r2, r2, #MODE_MASK
+        orr     r2, r2, #SVC_MODE
+THUMB(  orr     r2, r2, #PSR_T_BIT      )
+        msr     spsr_cxsf, r2
+        mrs     r1, ELR_hyp
+        ldr     r2, =BSYM(panic)
+        msr     ELR_hyp, r2
+        ldr     r0, =\panic_str
+        eret
+.endm
+        .text
+        .align 5
+__kvm_hyp_vector:
+        .globl __kvm_hyp_vector
+        @ Hyp-mode exception vector
+        W(b)    hyp_reset
+        W(b)    hyp_undef
+        W(b)    hyp_svc
+        W(b)    hyp_pabt
+        W(b)    hyp_dabt
+        W(b)    hyp_hvc
+        W(b)    hyp_irq
+        W(b)    hyp_fiq
+        .align
+hyp_reset:
+        b       hyp_reset
+        .align
+hyp_undef:
+        bad_exception ARM_EXCEPTION_UNDEFINED, und_die_str
+        .align
+hyp_svc:
+        bad_exception ARM_EXCEPTION_HVC, svc_die_str
+        .align
+hyp_pabt:
+        bad_exception ARM_EXCEPTION_PREF_ABORT, pabt_die_str
+        .align
+hyp_dabt:
+        bad_exception ARM_EXCEPTION_DATA_ABORT, dabt_die_str
+        .align
+hyp_hvc:
+        /*
+         * Getting here is either becuase of a trap from a guest or from calling
+         * HVC from the host kernel, which means "switch to Hyp mode".
+         */
+        push    {r0, r1, r2}
+        @ Check syndrome register
+        mrc     p15, 4, r1, c5, c2, 0   @ HSR
+        lsr     r0, r1, #HSR_EC_SHIFT
+#ifdef CONFIG_VFPv3
+        cmp     r0, #HSR_EC_CP_0_13
+        beq     switch_to_guest_vfp
+#endif
+        cmp     r0, #HSR_EC_HVC
+        bne     guest_trap              @ Not HVC instr.
+        /*
+         * Let's check if the HVC came from VMID 0 and allow simple
+         * switch to Hyp mode
+         */
+        mrrc    p15, 6, r0, r2, c2
+        lsr     r2, r2, #16
+        and     r2, r2, #0xff
+        cmp     r2, #0
+        bne     guest_trap              @ Guest called HVC
+host_switch_to_hyp:
+        pop     {r0, r1, r2}
+        push    {lr}
+        mrs     lr, SPSR
+        push    {lr}
+        mov     lr, r0
+        mov     r0, r1
+        mov     r1, r2
+        mov     r2, r3
+THUMB(  orr     lr, #1)
+        blx     lr                      @ Call the HYP function
+        pop     {lr}
+        msr     SPSR_csxf, lr
+        pop     {lr}
+        eret
+guest_trap:
+        load_vcpu                       @ Load VCPU pointer to r0
+        str     r1, [vcpu, #VCPU_HSR]
+        @ Check if we need the fault information
+        lsr     r1, r1, #HSR_EC_SHIFT
+        cmp     r1, #HSR_EC_IABT
+        mrceq   p15, 4, r2, c6, c0, 2   @ HIFAR
+        beq     2f
+        cmp     r1, #HSR_EC_DABT
+        bne     1f
+        mrc     p15, 4, r2, c6, c0, 0   @ HDFAR
+2:      str     r2, [vcpu, #VCPU_HxFAR]
+        /*
+         * B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
+         *
+         * Abort on the stage 2 translation for a memory access from a
+         * Non-secure PL1 or PL0 mode:
+         *
+         * For any Access flag fault or Translation fault, and also for any
+         * Permission fault on the stage 2 translation of a memory access
+         * made as part of a translation table walk for a stage 1 translation,
+         * the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
+         * is UNKNOWN.
+         */
+        /* Check for permission fault, and S1PTW */
+        mrc     p15, 4, r1, c5, c2, 0   @ HSR
+        and     r0, r1, #HSR_FSC_TYPE
+        cmp     r0, #FSC_PERM
+        tsteq   r1, #(1 << 7)           @ S1PTW
+        mrcne   p15, 4, r2, c6, c0, 4   @ HPFAR
+        bne     3f
+        /* Resolve IPA using the xFAR */
+        mcr     p15, 0, r2, c7, c8, 0   @ ATS1CPR
+        isb
+        mrrc    p15, 0, r0, r1, c7      @ PAR
+        tst     r0, #1
+        bne     4f                      @ Failed translation
+        ubfx    r2, r0, #12, #20
+        lsl     r2, r2, #4
+        orr     r2, r2, r1, lsl #24
+3:      load_vcpu                       @ Load VCPU pointer to r0
+        str     r2, [r0, #VCPU_HPFAR]
+1:      mov     r1, #ARM_EXCEPTION_HVC
+        b       __kvm_vcpu_return
+4:      pop     {r0, r1, r2}            @ Failed translation, return to guest
+        eret
+/*
+ * If VFPv3 support is not available, then we will not switch the VFP
+ * registers; however cp10 and cp11 accesses will still trap and fallback
+ * to the regular coprocessor emulation code, which currently will
+ * inject an undefined exception to the guest.
+ */
+#ifdef CONFIG_VFPv3
+switch_to_guest_vfp:
+        load_vcpu                       @ Load VCPU pointer to r0
+        push    {r3-r7}
+        @ NEON/VFP used.  Turn on VFP access.
+        set_hcptr vmexit, (HCPTR_TCP(10) | HCPTR_TCP(11))
+        @ Switch VFP/NEON hardware state to the guest's
+        add     r7, r0, #VCPU_VFP_HOST
+        ldr     r7, [r7]
+        store_vfp_state r7
+        add     r7, r0, #VCPU_VFP_GUEST
+        restore_vfp_state r7
+        pop     {r3-r7}
+        pop     {r0-r2}
+        eret
+#endif
+        .align
+hyp_irq:
+        push    {r0, r1, r2}
+        mov     r1, #ARM_EXCEPTION_IRQ
+        load_vcpu                       @ Load VCPU pointer to r0
+        b       __kvm_vcpu_return
+        .align
+hyp_fiq:
+        b       hyp_fiq
+        .ltorg
+__kvm_hyp_code_end:
+        .globl  __kvm_hyp_code_end
+        .section ".rodata"
+und_die_str:
+        .ascii  "unexpected undefined exception in Hyp mode at: %#08x"
+pabt_die_str:
+        .ascii  "unexpected prefetch abort in Hyp mode at: %#08x"
+dabt_die_str:
+        .ascii  "unexpected data abort in Hyp mode at: %#08x"
+svc_die_str:
+        .ascii  "unexpected HVC/SVC trap in Hyp mode at: %#08x"
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
new file mode 100644
index 000000000000..3c8f2f0b4c5e
--- /dev/null
+++ b/arch/arm/kvm/interrupts_head.S
@@ -0,0 +1,605 @@
+#include <linux/irqchip/arm-gic.h>
+#define VCPU_USR_REG(_reg_nr)   (VCPU_USR_REGS + (_reg_nr * 4))
+#define VCPU_USR_SP             (VCPU_USR_REG(13))
+#define VCPU_USR_LR             (VCPU_USR_REG(14))
+#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4))
+/*
+ * Many of these macros need to access the VCPU structure, which is always
+ * held in r0. These macros should never clobber r1, as it is used to hold the
+ * exception code on the return path (except of course the macro that switches
+ * all the registers before the final jump to the VM).
+ */
+vcpu    .req    r0              @ vcpu pointer always in r0
+/* Clobbers {r2-r6} */
+.macro store_vfp_state vfp_base
+        @ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions
+        VFPFMRX r2, FPEXC
+        @ Make sure VFP is enabled so we can touch the registers.
+        orr     r6, r2, #FPEXC_EN
+        VFPFMXR FPEXC, r6
+        VFPFMRX r3, FPSCR
+        tst     r2, #FPEXC_EX           @ Check for VFP Subarchitecture
+        beq     1f
+        @ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
+        @ we only need to save them if FPEXC_EX is set.
+        VFPFMRX r4, FPINST
+        tst     r2, #FPEXC_FP2V
+        VFPFMRX r5, FPINST2, ne         @ vmrsne
+        bic     r6, r2, #FPEXC_EX       @ FPEXC_EX disable
+        VFPFMXR FPEXC, r6
+1:
+        VFPFSTMIA \vfp_base, r6         @ Save VFP registers
+        stm     \vfp_base, {r2-r5}      @ Save FPEXC, FPSCR, FPINST, FPINST2
+.endm
+/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */
+.macro restore_vfp_state vfp_base
+        VFPFLDMIA \vfp_base, r6         @ Load VFP registers
+        ldm     \vfp_base, {r2-r5}      @ Load FPEXC, FPSCR, FPINST, FPINST2
+        VFPFMXR FPSCR, r3
+        tst     r2, #FPEXC_EX           @ Check for VFP Subarchitecture
+        beq     1f
+        VFPFMXR FPINST, r4
+        tst     r2, #FPEXC_FP2V
+        VFPFMXR FPINST2, r5, ne
+1:
+        VFPFMXR FPEXC, r2       @ FPEXC (last, in case !EN)
+.endm
+/* These are simply for the macros to work - value don't have meaning */
+.equ usr, 0
+.equ svc, 1
+.equ abt, 2
+.equ und, 3
+.equ irq, 4
+.equ fiq, 5
+.macro push_host_regs_mode mode
+        mrs     r2, SP_\mode
+        mrs     r3, LR_\mode
+        mrs     r4, SPSR_\mode
+        push    {r2, r3, r4}
+.endm
+/*
+ * Store all host persistent registers on the stack.
+ * Clobbers all registers, in all modes, except r0 and r1.
+ */
+.macro save_host_regs
+        /* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */
+        mrs     r2, ELR_hyp
+        push    {r2}
+        /* usr regs */
+        push    {r4-r12}        @ r0-r3 are always clobbered
+        mrs     r2, SP_usr
+        mov     r3, lr
+        push    {r2, r3}
+        push_host_regs_mode svc
+        push_host_regs_mode abt
+        push_host_regs_mode und
+        push_host_regs_mode irq
+        /* fiq regs */
+        mrs     r2, r8_fiq
+        mrs     r3, r9_fiq
+        mrs     r4, r10_fiq
+        mrs     r5, r11_fiq
+        mrs     r6, r12_fiq
+        mrs     r7, SP_fiq
+        mrs     r8, LR_fiq
+        mrs     r9, SPSR_fiq
+        push    {r2-r9}
+.endm
+.macro pop_host_regs_mode mode
+        pop     {r2, r3, r4}
+        msr     SP_\mode, r2
+        msr     LR_\mode, r3
+        msr     SPSR_\mode, r4
+.endm
+/*
+ * Restore all host registers from the stack.
+ * Clobbers all registers, in all modes, except r0 and r1.
+ */
+.macro restore_host_regs
+        pop     {r2-r9}
+        msr     r8_fiq, r2
+        msr     r9_fiq, r3
+        msr     r10_fiq, r4
+        msr     r11_fiq, r5
+        msr     r12_fiq, r6
+        msr     SP_fiq, r7
+        msr     LR_fiq, r8
+        msr     SPSR_fiq, r9
+        pop_host_regs_mode irq
+        pop_host_regs_mode und
+        pop_host_regs_mode abt
+        pop_host_regs_mode svc
+        pop     {r2, r3}
+        msr     SP_usr, r2
+        mov     lr, r3
+        pop     {r4-r12}
+        pop     {r2}
+        msr     ELR_hyp, r2
+.endm
+/*
+ * Restore SP, LR and SPSR for a given mode. offset is the offset of
+ * this mode's registers from the VCPU base.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r1, r2, r3, r4.
+ */
+.macro restore_guest_regs_mode mode, offset
+        add     r1, vcpu, \offset
+        ldm     r1, {r2, r3, r4}
+        msr     SP_\mode, r2
+        msr     LR_\mode, r3
+        msr     SPSR_\mode, r4
+.endm
+/*
+ * Restore all guest registers from the vcpu struct.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers *all* registers.
+ */
+.macro restore_guest_regs
+        restore_guest_regs_mode svc, #VCPU_SVC_REGS
+        restore_guest_regs_mode abt, #VCPU_ABT_REGS
+        restore_guest_regs_mode und, #VCPU_UND_REGS
+        restore_guest_regs_mode irq, #VCPU_IRQ_REGS
+        add     r1, vcpu, #VCPU_FIQ_REGS
+        ldm     r1, {r2-r9}
+        msr     r8_fiq, r2
+        msr     r9_fiq, r3
+        msr     r10_fiq, r4
+        msr     r11_fiq, r5
+        msr     r12_fiq, r6
+        msr     SP_fiq, r7
+        msr     LR_fiq, r8
+        msr     SPSR_fiq, r9
+        @ Load return state
+        ldr     r2, [vcpu, #VCPU_PC]
+        ldr     r3, [vcpu, #VCPU_CPSR]
+        msr     ELR_hyp, r2
+        msr     SPSR_cxsf, r3
+        @ Load user registers
+        ldr     r2, [vcpu, #VCPU_USR_SP]
+        ldr     r3, [vcpu, #VCPU_USR_LR]
+        msr     SP_usr, r2
+        mov     lr, r3
+        add     vcpu, vcpu, #(VCPU_USR_REGS)
+        ldm     vcpu, {r0-r12}
+.endm
+/*
+ * Save SP, LR and SPSR for a given mode. offset is the offset of
+ * this mode's registers from the VCPU base.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2, r3, r4, r5.
+ */
+.macro save_guest_regs_mode mode, offset
+        add     r2, vcpu, \offset
+        mrs     r3, SP_\mode
+        mrs     r4, LR_\mode
+        mrs     r5, SPSR_\mode
+        stm     r2, {r3, r4, r5}
+.endm
+/*
+ * Save all guest registers to the vcpu struct
+ * Expects guest's r0, r1, r2 on the stack.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2, r3, r4, r5.
+ */
+.macro save_guest_regs
+        @ Store usr registers
+        add     r2, vcpu, #VCPU_USR_REG(3)
+        stm     r2, {r3-r12}
+        add     r2, vcpu, #VCPU_USR_REG(0)
+        pop     {r3, r4, r5}            @ r0, r1, r2
+        stm     r2, {r3, r4, r5}
+        mrs     r2, SP_usr
+        mov     r3, lr
+        str     r2, [vcpu, #VCPU_USR_SP]
+        str     r3, [vcpu, #VCPU_USR_LR]
+        @ Store return state
+        mrs     r2, ELR_hyp
+        mrs     r3, spsr
+        str     r2, [vcpu, #VCPU_PC]
+        str     r3, [vcpu, #VCPU_CPSR]
+        @ Store other guest registers
+        save_guest_regs_mode svc, #VCPU_SVC_REGS
+        save_guest_regs_mode abt, #VCPU_ABT_REGS
+        save_guest_regs_mode und, #VCPU_UND_REGS
+        save_guest_regs_mode irq, #VCPU_IRQ_REGS
+.endm
+/* Reads cp15 registers from hardware and stores them in memory
+ * @store_to_vcpu: If 0, registers are written in-order to the stack,
+ *                 otherwise to the VCPU struct pointed to by vcpup
+ *
+ * Assumes vcpu pointer in vcpu reg
+ *
+ * Clobbers r2 - r12
+ */
+.macro read_cp15_state store_to_vcpu
+        mrc     p15, 0, r2, c1, c0, 0   @ SCTLR
+        mrc     p15, 0, r3, c1, c0, 2   @ CPACR
+        mrc     p15, 0, r4, c2, c0, 2   @ TTBCR
+        mrc     p15, 0, r5, c3, c0, 0   @ DACR
+        mrrc    p15, 0, r6, r7, c2      @ TTBR 0
+        mrrc    p15, 1, r8, r9, c2      @ TTBR 1
+        mrc     p15, 0, r10, c10, c2, 0 @ PRRR
+        mrc     p15, 0, r11, c10, c2, 1 @ NMRR
+        mrc     p15, 2, r12, c0, c0, 0  @ CSSELR
+        .if \store_to_vcpu == 0
+        push    {r2-r12}                @ Push CP15 registers
+        .else
+        str     r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
+        str     r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
+        str     r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
+        str     r5, [vcpu, #CP15_OFFSET(c3_DACR)]
+        add     r2, vcpu, #CP15_OFFSET(c2_TTBR0)
+        strd    r6, r7, [r2]
+        add     r2, vcpu, #CP15_OFFSET(c2_TTBR1)
+        strd    r8, r9, [r2]
+        str     r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
+        str     r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
+        str     r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
+        .endif
+        mrc     p15, 0, r2, c13, c0, 1  @ CID
+        mrc     p15, 0, r3, c13, c0, 2  @ TID_URW
+        mrc     p15, 0, r4, c13, c0, 3  @ TID_URO
+        mrc     p15, 0, r5, c13, c0, 4  @ TID_PRIV
+        mrc     p15, 0, r6, c5, c0, 0   @ DFSR
+        mrc     p15, 0, r7, c5, c0, 1   @ IFSR
+        mrc     p15, 0, r8, c5, c1, 0   @ ADFSR
+        mrc     p15, 0, r9, c5, c1, 1   @ AIFSR
+        mrc     p15, 0, r10, c6, c0, 0  @ DFAR
+        mrc     p15, 0, r11, c6, c0, 2  @ IFAR
+        mrc     p15, 0, r12, c12, c0, 0 @ VBAR
+        .if \store_to_vcpu == 0
+        push    {r2-r12}                @ Push CP15 registers
+        .else
+        str     r2, [vcpu, #CP15_OFFSET(c13_CID)]
+        str     r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
+        str     r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
+        str     r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
+        str     r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
+        str     r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
+        str     r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
+        str     r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
+        str     r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
+        str     r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
+        str     r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
+        .endif
+        mrc     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        .if \store_to_vcpu == 0
+        push    {r2}
+        .else
+        str     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        .endif
+.endm
+/*
+ * Reads cp15 registers from memory and writes them to hardware
+ * @read_from_vcpu: If 0, registers are read in-order from the stack,
+ *                  otherwise from the VCPU struct pointed to by vcpup
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro write_cp15_state read_from_vcpu
+        .if \read_from_vcpu == 0
+        pop     {r2}
+        .else
+        ldr     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        .endif
+        mcr     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        .if \read_from_vcpu == 0
+        pop     {r2-r12}
+        .else
+        ldr     r2, [vcpu, #CP15_OFFSET(c13_CID)]
+        ldr     r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
+        ldr     r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
+        ldr     r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
+        ldr     r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
+        ldr     r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
+        ldr     r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
+        ldr     r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
+        ldr     r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
+        ldr     r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
+        ldr     r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
+        .endif
+        mcr     p15, 0, r2, c13, c0, 1  @ CID
+        mcr     p15, 0, r3, c13, c0, 2  @ TID_URW
+        mcr     p15, 0, r4, c13, c0, 3  @ TID_URO
+        mcr     p15, 0, r5, c13, c0, 4  @ TID_PRIV
+        mcr     p15, 0, r6, c5, c0, 0   @ DFSR
+        mcr     p15, 0, r7, c5, c0, 1   @ IFSR
+        mcr     p15, 0, r8, c5, c1, 0   @ ADFSR
+        mcr     p15, 0, r9, c5, c1, 1   @ AIFSR
+        mcr     p15, 0, r10, c6, c0, 0  @ DFAR
+        mcr     p15, 0, r11, c6, c0, 2  @ IFAR
+        mcr     p15, 0, r12, c12, c0, 0 @ VBAR
+        .if \read_from_vcpu == 0
+        pop     {r2-r12}
+        .else
+        ldr     r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
+        ldr     r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
+        ldr     r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
+        ldr     r5, [vcpu, #CP15_OFFSET(c3_DACR)]
+        add     r12, vcpu, #CP15_OFFSET(c2_TTBR0)
+        ldrd    r6, r7, [r12]
+        add     r12, vcpu, #CP15_OFFSET(c2_TTBR1)
+        ldrd    r8, r9, [r12]
+        ldr     r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
+        ldr     r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
+        ldr     r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
+        .endif
+        mcr     p15, 0, r2, c1, c0, 0   @ SCTLR
+        mcr     p15, 0, r3, c1, c0, 2   @ CPACR
+        mcr     p15, 0, r4, c2, c0, 2   @ TTBCR
+        mcr     p15, 0, r5, c3, c0, 0   @ DACR
+        mcrr    p15, 0, r6, r7, c2      @ TTBR 0
+        mcrr    p15, 1, r8, r9, c2      @ TTBR 1
+        mcr     p15, 0, r10, c10, c2, 0 @ PRRR
+        mcr     p15, 0, r11, c10, c2, 1 @ NMRR
+        mcr     p15, 2, r12, c0, c0, 0  @ CSSELR
+.endm
+/*
+ * Save the VGIC CPU state into memory
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro save_vgic_state
+#ifdef CONFIG_KVM_ARM_VGIC
+        /* Get VGIC VCTRL base into r2 */
+        ldr     r2, [vcpu, #VCPU_KVM]
+        ldr     r2, [r2, #KVM_VGIC_VCTRL]
+        cmp     r2, #0
+        beq     2f
+        /* Compute the address of struct vgic_cpu */
+        add     r11, vcpu, #VCPU_VGIC_CPU
+        /* Save all interesting registers */
+        ldr     r3, [r2, #GICH_HCR]
+        ldr     r4, [r2, #GICH_VMCR]
+        ldr     r5, [r2, #GICH_MISR]
+        ldr     r6, [r2, #GICH_EISR0]
+        ldr     r7, [r2, #GICH_EISR1]
+        ldr     r8, [r2, #GICH_ELRSR0]
+        ldr     r9, [r2, #GICH_ELRSR1]
+        ldr     r10, [r2, #GICH_APR]
+        str     r3, [r11, #VGIC_CPU_HCR]
+        str     r4, [r11, #VGIC_CPU_VMCR]
+        str     r5, [r11, #VGIC_CPU_MISR]
+        str     r6, [r11, #VGIC_CPU_EISR]
+        str     r7, [r11, #(VGIC_CPU_EISR + 4)]
+        str     r8, [r11, #VGIC_CPU_ELRSR]
+        str     r9, [r11, #(VGIC_CPU_ELRSR + 4)]
+        str     r10, [r11, #VGIC_CPU_APR]
+        /* Clear GICH_HCR */
+        mov     r5, #0
+        str     r5, [r2, #GICH_HCR]
+        /* Save list registers */
+        add     r2, r2, #GICH_LR0
+        add     r3, r11, #VGIC_CPU_LR
+        ldr     r4, [r11, #VGIC_CPU_NR_LR]
+1:      ldr     r6, [r2], #4
+        str     r6, [r3], #4
+        subs    r4, r4, #1
+        bne     1b
+2:
+#endif
+.endm
+/*
+ * Restore the VGIC CPU state from memory
+ *
+ * Assumes vcpu pointer in vcpu reg
+ */
+.macro restore_vgic_state
+#ifdef CONFIG_KVM_ARM_VGIC
+        /* Get VGIC VCTRL base into r2 */
+        ldr     r2, [vcpu, #VCPU_KVM]
+        ldr     r2, [r2, #KVM_VGIC_VCTRL]
+        cmp     r2, #0
+        beq     2f
+        /* Compute the address of struct vgic_cpu */
+        add     r11, vcpu, #VCPU_VGIC_CPU
+        /* We only restore a minimal set of registers */
+        ldr     r3, [r11, #VGIC_CPU_HCR]
+        ldr     r4, [r11, #VGIC_CPU_VMCR]
+        ldr     r8, [r11, #VGIC_CPU_APR]
+        str     r3, [r2, #GICH_HCR]
+        str     r4, [r2, #GICH_VMCR]
+        str     r8, [r2, #GICH_APR]
+        /* Restore list registers */
+        add     r2, r2, #GICH_LR0
+        add     r3, r11, #VGIC_CPU_LR
+        ldr     r4, [r11, #VGIC_CPU_NR_LR]
+1:      ldr     r6, [r3], #4
+        str     r6, [r2], #4
+        subs    r4, r4, #1
+        bne     1b
+2:
+#endif
+.endm
+#define CNTHCTL_PL1PCTEN        (1 << 0)
+#define CNTHCTL_PL1PCEN         (1 << 1)
+/*
+ * Save the timer state onto the VCPU and allow physical timer/counter access
+ * for the host.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ * Clobbers r2-r5
+ */
+.macro save_timer_state
+#ifdef CONFIG_KVM_ARM_TIMER
+        ldr     r4, [vcpu, #VCPU_KVM]
+        ldr     r2, [r4, #KVM_TIMER_ENABLED]
+        cmp     r2, #0
+        beq     1f
+        mrc     p15, 0, r2, c14, c3, 1  @ CNTV_CTL
+        str     r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
+        bic     r2, #1                  @ Clear ENABLE
+        mcr     p15, 0, r2, c14, c3, 1  @ CNTV_CTL
+        isb
+        mrrc    p15, 3, r2, r3, c14     @ CNTV_CVAL
+        ldr     r4, =VCPU_TIMER_CNTV_CVAL
+        add     r5, vcpu, r4
+        strd    r2, r3, [r5]
+1:
+#endif
+        @ Allow physical timer/counter access for the host
+        mrc     p15, 4, r2, c14, c1, 0  @ CNTHCTL
+        orr     r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
+        mcr     p15, 4, r2, c14, c1, 0  @ CNTHCTL
+.endm
+/*
+ * Load the timer state from the VCPU and deny physical timer/counter access
+ * for the host.
+ *
+ * Assumes vcpu pointer in vcpu reg
+ * Clobbers r2-r5
+ */
+.macro restore_timer_state
+        @ Disallow physical timer access for the guest
+        @ Physical counter access is allowed
+        mrc     p15, 4, r2, c14, c1, 0  @ CNTHCTL
+        orr     r2, r2, #CNTHCTL_PL1PCTEN
+        bic     r2, r2, #CNTHCTL_PL1PCEN
+        mcr     p15, 4, r2, c14, c1, 0  @ CNTHCTL
+#ifdef CONFIG_KVM_ARM_TIMER
+        ldr     r4, [vcpu, #VCPU_KVM]
+        ldr     r2, [r4, #KVM_TIMER_ENABLED]
+        cmp     r2, #0
+        beq     1f
+        ldr     r2, [r4, #KVM_TIMER_CNTVOFF]
+        ldr     r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
+        mcrr    p15, 4, r2, r3, c14     @ CNTVOFF
+        ldr     r4, =VCPU_TIMER_CNTV_CVAL
+        add     r5, vcpu, r4
+        ldrd    r2, r3, [r5]
+        mcrr    p15, 3, r2, r3, c14     @ CNTV_CVAL
+        isb
+        ldr     r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
+        and     r2, r2, #3
+        mcr     p15, 0, r2, c14, c3, 1  @ CNTV_CTL
+1:
+#endif
+.endm
+.equ vmentry,   0
+.equ vmexit,    1
+/* Configures the HSTR (Hyp System Trap Register) on entry/return
+ * (hardware reset value is 0) */
+.macro set_hstr operation
+        mrc     p15, 4, r2, c1, c1, 3
+        ldr     r3, =HSTR_T(15)
+        .if \operation == vmentry
+        orr     r2, r2, r3              @ Trap CR{15}
+        .else
+        bic     r2, r2, r3              @ Don't trap any CRx accesses
+        .endif
+        mcr     p15, 4, r2, c1, c1, 3
+.endm
+/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
+ * (hardware reset value is 0). Keep previous value in r2. */
+.macro set_hcptr operation, mask
+        mrc     p15, 4, r2, c1, c1, 2
+        ldr     r3, =\mask
+        .if \operation == vmentry
+        orr     r3, r2, r3              @ Trap coproc-accesses defined in mask
+        .else
+        bic     r3, r2, r3              @ Don't trap defined coproc-accesses
+        .endif
+        mcr     p15, 4, r3, c1, c1, 2
+.endm
+/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return
+ * (hardware reset value is 0) */
+.macro set_hdcr operation
+        mrc     p15, 4, r2, c1, c1, 1
+        ldr     r3, =(HDCR_TPM|HDCR_TPMCR)
+        .if \operation == vmentry
+        orr     r2, r2, r3              @ Trap some perfmon accesses
+        .else
+        bic     r2, r2, r3              @ Don't trap any perfmon accesses
+        .endif
+        mcr     p15, 4, r2, c1, c1, 1
+.endm
+/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
+.macro configure_hyp_role operation
+        mrc     p15, 4, r2, c1, c1, 0   @ HCR
+        bic     r2, r2, #HCR_VIRT_EXCP_MASK
+        ldr     r3, =HCR_GUEST_MASK
+        .if \operation == vmentry
+        orr     r2, r2, r3
+        ldr     r3, [vcpu, #VCPU_IRQ_LINES]
+        orr     r2, r2, r3
+        .else
+        bic     r2, r2, r3
+        .endif
+        mcr     p15, 4, r2, c1, c1, 0
+.endm
+.macro load_vcpu
+        mrc     p15, 4, vcpu, c13, c0, 2        @ HTPIDR
+.endm
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
new file mode 100644
index 000000000000..98a870ff1a5c
--- /dev/null
+++ b/arch/arm/kvm/mmio.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/kvm_host.h>
+#include <asm/kvm_mmio.h>
+#include <asm/kvm_emulate.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+/**
+ * kvm_handle_mmio_return -- Handle MMIO loads after user space emulation
+ * @vcpu: The VCPU pointer
+ * @run:  The VCPU run struct containing the mmio data
+ *
+ * This should only be called after returning from userspace for MMIO load
+ * emulation.
+ */
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        __u32 *dest;
+        unsigned int len;
+        int mask;
+        if (!run->mmio.is_write) {
+                dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt);
+                memset(dest, 0, sizeof(int));
+                len = run->mmio.len;
+                if (len > 4)
+                        return -EINVAL;
+                memcpy(dest, run->mmio.data, len);
+                trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
+                                *((u64 *)run->mmio.data));
+                if (vcpu->arch.mmio_decode.sign_extend && len < 4) {
+                        mask = 1U << ((len * 8) - 1);
+                        *dest = (*dest ^ mask) - mask;
+                }
+        }
+        return 0;
+}
+static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
+                      struct kvm_exit_mmio *mmio)
+{
+        unsigned long rt, len;
+        bool is_write, sign_extend;
+        if ((vcpu->arch.hsr >> 8) & 1) {
+                /* cache operation on I/O addr, tell guest unsupported */
+                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        if ((vcpu->arch.hsr >> 7) & 1) {
+                /* page table accesses IO mem: tell guest to fix its TTBR */
+                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        switch ((vcpu->arch.hsr >> 22) & 0x3) {
+        case 0:
+                len = 1;
+                break;
+        case 1:
+                len = 2;
+                break;
+        case 2:
+                len = 4;
+                break;
+        default:
+                kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
+                return -EFAULT;
+        }
+        is_write = vcpu->arch.hsr & HSR_WNR;
+        sign_extend = vcpu->arch.hsr & HSR_SSE;
+        rt = (vcpu->arch.hsr & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
+        if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
+                /* IO memory trying to read/write pc */
+                kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                return 1;
+        }
+        mmio->is_write = is_write;
+        mmio->phys_addr = fault_ipa;
+        mmio->len = len;
+        vcpu->arch.mmio_decode.sign_extend = sign_extend;
+        vcpu->arch.mmio_decode.rt = rt;
+        /*
+         * The MMIO instruction is emulated and should not be re-executed
+         * in the guest.
+         */
+        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+        return 0;
+}
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa)
+{
+        struct kvm_exit_mmio mmio;
+        unsigned long rt;
+        int ret;
+        /*
+         * Prepare MMIO operation. First stash it in a private
+         * structure that we can use for in-kernel emulation. If the
+         * kernel can't handle it, copy it into run->mmio and let user
+         * space do its magic.
+         */
+        if (vcpu->arch.hsr & HSR_ISV) {
+                ret = decode_hsr(vcpu, fault_ipa, &mmio);
+                if (ret)
+                        return ret;
+        } else {
+                kvm_err("load/store instruction decoding not implemented\n");
+                return -ENOSYS;
+        }
+        rt = vcpu->arch.mmio_decode.rt;
+        trace_kvm_mmio((mmio.is_write) ? KVM_TRACE_MMIO_WRITE :
+                                         KVM_TRACE_MMIO_READ_UNSATISFIED,
+                        mmio.len, fault_ipa,
+                        (mmio.is_write) ? *vcpu_reg(vcpu, rt) : 0);
+        if (mmio.is_write)
+                memcpy(mmio.data, vcpu_reg(vcpu, rt), mmio.len);
+        if (vgic_handle_mmio(vcpu, run, &mmio))
+                return 1;
+        kvm_prepare_mmio(run, &mmio);
+        return 0;
+}
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
new file mode 100644
index 000000000000..99e07c7dd745
--- /dev/null
+++ b/arch/arm/kvm/mmu.c
@@ -0,0 +1,782 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/mman.h>
+#include <linux/kvm_host.h>
+#include <linux/io.h>
+#include <trace/events/kvm.h>
+#include <asm/idmap.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_mmio.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/mach/map.h>
+#include <trace/events/kvm.h>
+#include "trace.h"
+extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
+static void kvm_tlb_flush_vmid(struct kvm *kvm)
+{
+        kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
+}
+static void kvm_set_pte(pte_t *pte, pte_t new_pte)
+{
+        pte_val(*pte) = new_pte;
+        /*
+         * flush_pmd_entry just takes a void pointer and cleans the necessary
+         * cache entries, so we can reuse the function for ptes.
+         */
+        flush_pmd_entry(pte);
+}
+static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
+                                  int min, int max)
+{
+        void *page;
+        BUG_ON(max > KVM_NR_MEM_OBJS);
+        if (cache->nobjs >= min)
+                return 0;
+        while (cache->nobjs < max) {
+                page = (void *)__get_free_page(PGALLOC_GFP);
+                if (!page)
+                        return -ENOMEM;
+                cache->objects[cache->nobjs++] = page;
+        }
+        return 0;
+}
+static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
+{
+        while (mc->nobjs)
+                free_page((unsigned long)mc->objects[--mc->nobjs]);
+}
+static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
+{
+        void *p;
+        BUG_ON(!mc || !mc->nobjs);
+        p = mc->objects[--mc->nobjs];
+        return p;
+}
+static void free_ptes(pmd_t *pmd, unsigned long addr)
+{
+        pte_t *pte;
+        unsigned int i;
+        for (i = 0; i < PTRS_PER_PMD; i++, addr += PMD_SIZE) {
+                if (!pmd_none(*pmd) && pmd_table(*pmd)) {
+                        pte = pte_offset_kernel(pmd, addr);
+                        pte_free_kernel(NULL, pte);
+                }
+                pmd++;
+        }
+}
+/**
+ * free_hyp_pmds - free a Hyp-mode level-2 tables and child level-3 tables
+ *
+ * Assumes this is a page table used strictly in Hyp-mode and therefore contains
+ * only mappings in the kernel memory area, which is above PAGE_OFFSET.
+ */
+void free_hyp_pmds(void)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr;
+        mutex_lock(&kvm_hyp_pgd_mutex);
+        for (addr = PAGE_OFFSET; addr != 0; addr += PGDIR_SIZE) {
+                pgd = hyp_pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none(*pud))
+                        continue;
+                BUG_ON(pud_bad(*pud));
+                pmd = pmd_offset(pud, addr);
+                free_ptes(pmd, addr);
+                pmd_free(NULL, pmd);
+                pud_clear(pud);
+        }
+        mutex_unlock(&kvm_hyp_pgd_mutex);
+}
+static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
+                                    unsigned long end)
+{
+        pte_t *pte;
+        unsigned long addr;
+        struct page *page;
+        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
+                pte = pte_offset_kernel(pmd, addr);
+                BUG_ON(!virt_addr_valid(addr));
+                page = virt_to_page(addr);
+                kvm_set_pte(pte, mk_pte(page, PAGE_HYP));
+        }
+}
+static void create_hyp_io_pte_mappings(pmd_t *pmd, unsigned long start,
+                                       unsigned long end,
+                                       unsigned long *pfn_base)
+{
+        pte_t *pte;
+        unsigned long addr;
+        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
+                pte = pte_offset_kernel(pmd, addr);
+                BUG_ON(pfn_valid(*pfn_base));
+                kvm_set_pte(pte, pfn_pte(*pfn_base, PAGE_HYP_DEVICE));
+                (*pfn_base)++;
+        }
+}
+static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
+                                   unsigned long end, unsigned long *pfn_base)
+{
+        pmd_t *pmd;
+        pte_t *pte;
+        unsigned long addr, next;
+        for (addr = start; addr < end; addr = next) {
+                pmd = pmd_offset(pud, addr);
+                BUG_ON(pmd_sect(*pmd));
+                if (pmd_none(*pmd)) {
+                        pte = pte_alloc_one_kernel(NULL, addr);
+                        if (!pte) {
+                                kvm_err("Cannot allocate Hyp pte\n");
+                                return -ENOMEM;
+                        }
+                        pmd_populate_kernel(NULL, pmd, pte);
+                }
+                next = pmd_addr_end(addr, end);
+                /*
+                 * If pfn_base is NULL, we map kernel pages into HYP with the
+                 * virtual address. Otherwise, this is considered an I/O
+                 * mapping and we map the physical region starting at
+                 * *pfn_base to [start, end[.
+                 */
+                if (!pfn_base)
+                        create_hyp_pte_mappings(pmd, addr, next);
+                else
+                        create_hyp_io_pte_mappings(pmd, addr, next, pfn_base);
+        }
+        return 0;
+}
+static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
+{
+        unsigned long start = (unsigned long)from;
+        unsigned long end = (unsigned long)to;
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr, next;
+        int err = 0;
+        BUG_ON(start > end);
+        if (start < PAGE_OFFSET)
+                return -EINVAL;
+        mutex_lock(&kvm_hyp_pgd_mutex);
+        for (addr = start; addr < end; addr = next) {
+                pgd = hyp_pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none_or_clear_bad(pud)) {
+                        pmd = pmd_alloc_one(NULL, addr);
+                        if (!pmd) {
+                                kvm_err("Cannot allocate Hyp pmd\n");
+                                err = -ENOMEM;
+                                goto out;
+                        }
+                        pud_populate(NULL, pud, pmd);
+                }
+                next = pgd_addr_end(addr, end);
+                err = create_hyp_pmd_mappings(pud, addr, next, pfn_base);
+                if (err)
+                        goto out;
+        }
+out:
+        mutex_unlock(&kvm_hyp_pgd_mutex);
+        return err;
+}
+/**
+ * create_hyp_mappings - map a kernel virtual address range in Hyp mode
+ * @from:       The virtual kernel start address of the range
+ * @to:         The virtual kernel end address of the range (exclusive)
+ *
+ * The same virtual address as the kernel virtual address is also used in
+ * Hyp-mode mapping to the same underlying physical pages.
+ *
+ * Note: Wrapping around zero in the "to" address is not supported.
+ */
+int create_hyp_mappings(void *from, void *to)
+{
+        return __create_hyp_mappings(from, to, NULL);
+}
+/**
+ * create_hyp_io_mappings - map a physical IO range in Hyp mode
+ * @from:       The virtual HYP start address of the range
+ * @to:         The virtual HYP end address of the range (exclusive)
+ * @addr:       The physical start address which gets mapped
+ */
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t addr)
+{
+        unsigned long pfn = __phys_to_pfn(addr);
+        return __create_hyp_mappings(from, to, &pfn);
+}
+/**
+ * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
+ * @kvm:        The KVM struct pointer for the VM.
+ *
+ * Allocates the 1st level table only of size defined by S2_PGD_ORDER (can
+ * support either full 40-bit input addresses or limited to 32-bit input
+ * addresses). Clears the allocated pages.
+ *
+ * Note we don't need locking here as this is only called when the VM is
+ * created, which can only be done once.
+ */
+int kvm_alloc_stage2_pgd(struct kvm *kvm)
+{
+        pgd_t *pgd;
+        if (kvm->arch.pgd != NULL) {
+                kvm_err("kvm_arch already initialized?\n");
+                return -EINVAL;
+        }
+        pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, S2_PGD_ORDER);
+        if (!pgd)
+                return -ENOMEM;
+        /* stage-2 pgd must be aligned to its size */
+        VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
+        memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
+        clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
+        kvm->arch.pgd = pgd;
+        return 0;
+}
+static void clear_pud_entry(pud_t *pud)
+{
+        pmd_t *pmd_table = pmd_offset(pud, 0);
+        pud_clear(pud);
+        pmd_free(NULL, pmd_table);
+        put_page(virt_to_page(pud));
+}
+static void clear_pmd_entry(pmd_t *pmd)
+{
+        pte_t *pte_table = pte_offset_kernel(pmd, 0);
+        pmd_clear(pmd);
+        pte_free_kernel(NULL, pte_table);
+        put_page(virt_to_page(pmd));
+}
+static bool pmd_empty(pmd_t *pmd)
+{
+        struct page *pmd_page = virt_to_page(pmd);
+        return page_count(pmd_page) == 1;
+}
+static void clear_pte_entry(pte_t *pte)
+{
+        if (pte_present(*pte)) {
+                kvm_set_pte(pte, __pte(0));
+                put_page(virt_to_page(pte));
+        }
+}
+static bool pte_empty(pte_t *pte)
+{
+        struct page *pte_page = virt_to_page(pte);
+        return page_count(pte_page) == 1;
+}
+/**
+ * unmap_stage2_range -- Clear stage2 page table entries to unmap a range
+ * @kvm:   The VM pointer
+ * @start: The intermediate physical base address of the range to unmap
+ * @size:  The size of the area to unmap
+ *
+ * Clear a range of stage-2 mappings, lowering the various ref-counts.  Must
+ * be called while holding mmu_lock (unless for freeing the stage2 pgd before
+ * destroying the VM), otherwise another faulting VCPU may come in and mess
+ * with things behind our backs.
+ */
+static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *pte;
+        phys_addr_t addr = start, end = start + size;
+        u64 range;
+        while (addr < end) {
+                pgd = kvm->arch.pgd + pgd_index(addr);
+                pud = pud_offset(pgd, addr);
+                if (pud_none(*pud)) {
+                        addr += PUD_SIZE;
+                        continue;
+                }
+                pmd = pmd_offset(pud, addr);
+                if (pmd_none(*pmd)) {
+                        addr += PMD_SIZE;
+                        continue;
+                }
+                pte = pte_offset_kernel(pmd, addr);
+                clear_pte_entry(pte);
+                range = PAGE_SIZE;
+                /* If we emptied the pte, walk back up the ladder */
+                if (pte_empty(pte)) {
+                        clear_pmd_entry(pmd);
+                        range = PMD_SIZE;
+                        if (pmd_empty(pmd)) {
+                                clear_pud_entry(pud);
+                                range = PUD_SIZE;
+                        }
+                }
+                addr += range;
+        }
+}
+/**
+ * kvm_free_stage2_pgd - free all stage-2 tables
+ * @kvm:        The KVM struct pointer for the VM.
+ *
+ * Walks the level-1 page table pointed to by kvm->arch.pgd and frees all
+ * underlying level-2 and level-3 tables before freeing the actual level-1 table
+ * and setting the struct pointer to NULL.
+ *
+ * Note we don't need locking here as this is only called when the VM is
+ * destroyed, which can only be done once.
+ */
+void kvm_free_stage2_pgd(struct kvm *kvm)
+{
+        if (kvm->arch.pgd == NULL)
+                return;
+        unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE);
+        free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER);
+        kvm->arch.pgd = NULL;
+}
+static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
+                          phys_addr_t addr, const pte_t *new_pte, bool iomap)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        pte_t *pte, old_pte;
+        /* Create 2nd stage page table mapping - Level 1 */
+        pgd = kvm->arch.pgd + pgd_index(addr);
+        pud = pud_offset(pgd, addr);
+        if (pud_none(*pud)) {
+                if (!cache)
+                        return 0; /* ignore calls from kvm_set_spte_hva */
+                pmd = mmu_memory_cache_alloc(cache);
+                pud_populate(NULL, pud, pmd);
+                pmd += pmd_index(addr);
+                get_page(virt_to_page(pud));
+        } else
+                pmd = pmd_offset(pud, addr);
+        /* Create 2nd stage page table mapping - Level 2 */
+        if (pmd_none(*pmd)) {
+                if (!cache)
+                        return 0; /* ignore calls from kvm_set_spte_hva */
+                pte = mmu_memory_cache_alloc(cache);
+                clean_pte_table(pte);
+                pmd_populate_kernel(NULL, pmd, pte);
+                pte += pte_index(addr);
+                get_page(virt_to_page(pmd));
+        } else
+                pte = pte_offset_kernel(pmd, addr);
+        if (iomap && pte_present(*pte))
+                return -EFAULT;
+        /* Create 2nd stage page table mapping - Level 3 */
+        old_pte = *pte;
+        kvm_set_pte(pte, *new_pte);
+        if (pte_present(old_pte))
+                kvm_tlb_flush_vmid(kvm);
+        else
+                get_page(virt_to_page(pte));
+        return 0;
+}
+/**
+ * kvm_phys_addr_ioremap - map a device range to guest IPA
+ *
+ * @kvm:        The KVM pointer
+ * @guest_ipa:  The IPA at which to insert the mapping
+ * @pa:         The physical address of the device
+ * @size:       The size of the mapping
+ */
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size)
+{
+        phys_addr_t addr, end;
+        int ret = 0;
+        unsigned long pfn;
+        struct kvm_mmu_memory_cache cache = { 0, };
+        end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK;
+        pfn = __phys_to_pfn(pa);
+        for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
+                pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR);
+                ret = mmu_topup_memory_cache(&cache, 2, 2);
+                if (ret)
+                        goto out;
+                spin_lock(&kvm->mmu_lock);
+                ret = stage2_set_pte(kvm, &cache, addr, &pte, true);
+                spin_unlock(&kvm->mmu_lock);
+                if (ret)
+                        goto out;
+                pfn++;
+        }
+out:
+        mmu_free_memory_cache(&cache);
+        return ret;
+}
+static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+        /*
+         * If we are going to insert an instruction page and the icache is
+         * either VIPT or PIPT, there is a potential problem where the host
+         * (or another VM) may have used the same page as this guest, and we
+         * read incorrect data from the icache.  If we're using a PIPT cache,
+         * we can invalidate just that page, but if we are using a VIPT cache
+         * we need to invalidate the entire icache - damn shame - as written
+         * in the ARM ARM (DDI 0406C.b - Page B3-1393).
+         *
+         * VIVT caches are tagged using both the ASID and the VMID and doesn't
+         * need any kind of flushing (DDI 0406C.b - Page B3-1392).
+         */
+        if (icache_is_pipt()) {
+                unsigned long hva = gfn_to_hva(kvm, gfn);
+                __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
+        } else if (!icache_is_vivt_asid_tagged()) {
+                /* any kind of VIPT cache */
+                __flush_icache_all();
+        }
+}
+static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
+                          gfn_t gfn, struct kvm_memory_slot *memslot,
+                          unsigned long fault_status)
+{
+        pte_t new_pte;
+        pfn_t pfn;
+        int ret;
+        bool write_fault, writable;
+        unsigned long mmu_seq;
+        struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
+        write_fault = kvm_is_write_fault(vcpu->arch.hsr);
+        if (fault_status == FSC_PERM && !write_fault) {
+                kvm_err("Unexpected L2 read permission error\n");
+                return -EFAULT;
+        }
+        /* We need minimum second+third level pages */
+        ret = mmu_topup_memory_cache(memcache, 2, KVM_NR_MEM_OBJS);
+        if (ret)
+                return ret;
+        mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /*
+         * Ensure the read of mmu_notifier_seq happens before we call
+         * gfn_to_pfn_prot (which calls get_user_pages), so that we don't risk
+         * the page we just got a reference to gets unmapped before we have a
+         * chance to grab the mmu_lock, which ensure that if the page gets
+         * unmapped afterwards, the call to kvm_unmap_hva will take it away
+         * from us again properly. This smp_rmb() interacts with the smp_wmb()
+         * in kvm_mmu_notifier_invalidate_<page|range_end>.
+         */
+        smp_rmb();
+        pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write_fault, &writable);
+        if (is_error_pfn(pfn))
+                return -EFAULT;
+        new_pte = pfn_pte(pfn, PAGE_S2);
+        coherent_icache_guest_page(vcpu->kvm, gfn);
+        spin_lock(&vcpu->kvm->mmu_lock);
+        if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
+                goto out_unlock;
+        if (writable) {
+                pte_val(new_pte) |= L_PTE_S2_RDWR;
+                kvm_set_pfn_dirty(pfn);
+        }
+        stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false);
+out_unlock:
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_release_pfn_clean(pfn);
+        return 0;
+}
+/**
+ * kvm_handle_guest_abort - handles all 2nd stage aborts
+ * @vcpu:       the VCPU pointer
+ * @run:        the kvm_run structure
+ *
+ * Any abort that gets to the host is almost guaranteed to be caused by a
+ * missing second stage translation table entry, which can mean that either the
+ * guest simply needs more memory and we must allocate an appropriate page or it
+ * can mean that the guest tried to access I/O memory, which is emulated by user
+ * space. The distinction is based on the IPA causing the fault and whether this
+ * memory region has been registered as standard RAM by user space.
+ */
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        unsigned long hsr_ec;
+        unsigned long fault_status;
+        phys_addr_t fault_ipa;
+        struct kvm_memory_slot *memslot;
+        bool is_iabt;
+        gfn_t gfn;
+        int ret, idx;
+        hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
+        is_iabt = (hsr_ec == HSR_EC_IABT);
+        fault_ipa = ((phys_addr_t)vcpu->arch.hpfar & HPFAR_MASK) << 8;
+        trace_kvm_guest_fault(*vcpu_pc(vcpu), vcpu->arch.hsr,
+                              vcpu->arch.hxfar, fault_ipa);
+        /* Check the stage-2 fault is trans. fault or write fault */
+        fault_status = (vcpu->arch.hsr & HSR_FSC_TYPE);
+        if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
+                kvm_err("Unsupported fault status: EC=%#lx DFCS=%#lx\n",
+                        hsr_ec, fault_status);
+                return -EFAULT;
+        }
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+        gfn = fault_ipa >> PAGE_SHIFT;
+        if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
+                if (is_iabt) {
+                        /* Prefetch Abort on I/O address */
+                        kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                        ret = 1;
+                        goto out_unlock;
+                }
+                if (fault_status != FSC_FAULT) {
+                        kvm_err("Unsupported fault status on io memory: %#lx\n",
+                                fault_status);
+                        ret = -EFAULT;
+                        goto out_unlock;
+                }
+                /* Adjust page offset */
+                fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK;
+                ret = io_mem_abort(vcpu, run, fault_ipa);
+                goto out_unlock;
+        }
+        memslot = gfn_to_memslot(vcpu->kvm, gfn);
+        ret = user_mem_abort(vcpu, fault_ipa, gfn, memslot, fault_status);
+        if (ret == 0)
+                ret = 1;
+out_unlock:
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+        return ret;
+}
+static void handle_hva_to_gpa(struct kvm *kvm,
+                              unsigned long start,
+                              unsigned long end,
+                              void (*handler)(struct kvm *kvm,
+                                              gpa_t gpa, void *data),
+                              void *data)
+{
+        struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
+        slots = kvm_memslots(kvm);
+        /* we only care about the pages that the guest sees */
+        kvm_for_each_memslot(memslot, slots) {
+                unsigned long hva_start, hva_end;
+                gfn_t gfn, gfn_end;
+                hva_start = max(start, memslot->userspace_addr);
+                hva_end = min(end, memslot->userspace_addr +
+                                        (memslot->npages << PAGE_SHIFT));
+                if (hva_start >= hva_end)
+                        continue;
+                /*
+                 * {gfn(page) | page intersects with [hva_start, hva_end)} =
+                 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
+                 */
+                gfn = hva_to_gfn_memslot(hva_start, memslot);
+                gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
+                for (; gfn < gfn_end; ++gfn) {
+                        gpa_t gpa = gfn << PAGE_SHIFT;
+                        handler(kvm, gpa, data);
+                }
+        }
+}
+static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
+{
+        unmap_stage2_range(kvm, gpa, PAGE_SIZE);
+        kvm_tlb_flush_vmid(kvm);
+}
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
+{
+        unsigned long end = hva + PAGE_SIZE;
+        if (!kvm->arch.pgd)
+                return 0;
+        trace_kvm_unmap_hva(hva);
+        handle_hva_to_gpa(kvm, hva, end, &kvm_unmap_hva_handler, NULL);
+        return 0;
+}
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end)
+{
+        if (!kvm->arch.pgd)
+                return 0;
+        trace_kvm_unmap_hva_range(start, end);
+        handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);
+        return 0;
+}
+static void kvm_set_spte_handler(struct kvm *kvm, gpa_t gpa, void *data)
+{
+        pte_t *pte = (pte_t *)data;
+        stage2_set_pte(kvm, NULL, gpa, pte, false);
+}
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
+{
+        unsigned long end = hva + PAGE_SIZE;
+        pte_t stage2_pte;
+        if (!kvm->arch.pgd)
+                return;
+        trace_kvm_set_spte_hva(hva);
+        stage2_pte = pfn_pte(pte_pfn(pte), PAGE_S2);
+        handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte);
+}
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu)
+{
+        mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
+}
+phys_addr_t kvm_mmu_get_httbr(void)
+{
+        VM_BUG_ON(!virt_addr_valid(hyp_pgd));
+        return virt_to_phys(hyp_pgd);
+}
+int kvm_mmu_init(void)
+{
+        if (!hyp_pgd) {
+                kvm_err("Hyp mode PGD not allocated\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+/**
+ * kvm_clear_idmap - remove all idmaps from the hyp pgd
+ *
+ * Free the underlying pmds for all pgds in range and clear the pgds (but
+ * don't free them) afterwards.
+ */
+void kvm_clear_hyp_idmap(void)
+{
+        unsigned long addr, end;
+        unsigned long next;
+        pgd_t *pgd = hyp_pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        addr = virt_to_phys(__hyp_idmap_text_start);
+        end = virt_to_phys(__hyp_idmap_text_end);
+        pgd += pgd_index(addr);
+        do {
+                next = pgd_addr_end(addr, end);
+                if (pgd_none_or_clear_bad(pgd))
+                        continue;
+                pud = pud_offset(pgd, addr);
+                pmd = pmd_offset(pud, addr);
+                pud_clear(pud);
+                clean_pmd_entry(pmd);
+                pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
+        } while (pgd++, addr = next, addr < end);
+}
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
new file mode 100644
index 000000000000..7ee5bb7a3667
--- /dev/null
+++ b/arch/arm/kvm/psci.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2012 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kvm_host.h>
+#include <linux/wait.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_psci.h>
+/*
+ * This is an implementation of the Power State Coordination Interface
+ * as described in ARM document number ARM DEN 0022A.
+ */
+static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
+{
+        vcpu->arch.pause = true;
+}
+static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
+{
+        struct kvm *kvm = source_vcpu->kvm;
+        struct kvm_vcpu *vcpu;
+        wait_queue_head_t *wq;
+        unsigned long cpu_id;
+        phys_addr_t target_pc;
+        cpu_id = *vcpu_reg(source_vcpu, 1);
+        if (vcpu_mode_is_32bit(source_vcpu))
+                cpu_id &= ~((u32) 0);
+        if (cpu_id >= atomic_read(&kvm->online_vcpus))
+                return KVM_PSCI_RET_INVAL;
+        target_pc = *vcpu_reg(source_vcpu, 2);
+        vcpu = kvm_get_vcpu(kvm, cpu_id);
+        wq = kvm_arch_vcpu_wq(vcpu);
+        if (!waitqueue_active(wq))
+                return KVM_PSCI_RET_INVAL;
+        kvm_reset_vcpu(vcpu);
+        /* Gracefully handle Thumb2 entry point */
+        if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
+                target_pc &= ~((phys_addr_t) 1);
+                vcpu_set_thumb(vcpu);
+        }
+        *vcpu_pc(vcpu) = target_pc;
+        vcpu->arch.pause = false;
+        smp_mb();               /* Make sure the above is visible */
+        wake_up_interruptible(wq);
+        return KVM_PSCI_RET_SUCCESS;
+}
+/**
+ * kvm_psci_call - handle PSCI call if r0 value is in range
+ * @vcpu: Pointer to the VCPU struct
+ *
+ * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * The calling convention is similar to SMC calls to the secure world where
+ * the function number is placed in r0 and this function returns true if the
+ * function number specified in r0 is withing the PSCI range, and false
+ * otherwise.
+ */
+bool kvm_psci_call(struct kvm_vcpu *vcpu)
+{
+        unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
+        unsigned long val;
+        switch (psci_fn) {
+        case KVM_PSCI_FN_CPU_OFF:
+                kvm_psci_vcpu_off(vcpu);
+                val = KVM_PSCI_RET_SUCCESS;
+                break;
+        case KVM_PSCI_FN_CPU_ON:
+                val = kvm_psci_vcpu_on(vcpu);
+                break;
+        case KVM_PSCI_FN_CPU_SUSPEND:
+        case KVM_PSCI_FN_MIGRATE:
+                val = KVM_PSCI_RET_NI;
+                break;
+        default:
+                return false;
+        }
+        *vcpu_reg(vcpu, 0) = val;
+        return true;
+}
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
new file mode 100644
index 000000000000..b80256b554cd
--- /dev/null
+++ b/arch/arm/kvm/reset.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+#include <asm/unified.h>
+#include <asm/ptrace.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_coproc.h>
+/******************************************************************************
+ * Cortex-A15 Reset Values
+ */
+static const int a15_max_cpu_idx = 3;
+static struct kvm_regs a15_regs_reset = {
+        .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
+};
+/*******************************************************************************
+ * Exported reset function
+ */
+/**
+ * kvm_reset_vcpu - sets core registers and cp15 registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architectually defined reset values.
+ */
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
+{
+        struct kvm_regs *cpu_reset;
+        switch (vcpu->arch.target) {
+        case KVM_ARM_TARGET_CORTEX_A15:
+                if (vcpu->vcpu_id > a15_max_cpu_idx)
+                        return -EINVAL;
+                cpu_reset = &a15_regs_reset;
+                vcpu->arch.midr = read_cpuid_id();
+                break;
+        default:
+                return -ENODEV;
+        }
+        /* Reset core registers */
+        memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs));
+        /* Reset CP15 registers */
+        kvm_reset_coprocs(vcpu);
+        return 0;
+}
diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h
new file mode 100644
index 000000000000..a8e73ed5ad5b
--- /dev/null
+++ b/arch/arm/kvm/trace.h
@@ -0,0 +1,235 @@
+#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_KVM_H
+#include <linux/tracepoint.h>
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM kvm
+/*
+ * Tracepoints for entry/exit to guest
+ */
+TRACE_EVENT(kvm_entry,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("PC: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_exit,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("PC: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_guest_fault,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long hsr,
+                 unsigned long hxfar,
+                 unsigned long long ipa),
+        TP_ARGS(vcpu_pc, hsr, hxfar, ipa),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  hsr             )
+                __field(        unsigned long,  hxfar           )
+                __field(   unsigned long long,  ipa             )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->hsr                    = hsr;
+                __entry->hxfar                  = hxfar;
+                __entry->ipa                    = ipa;
+        ),
+        TP_printk("guest fault at PC %#08lx (hxfar %#08lx, "
+                  "ipa %#16llx, hsr %#08lx",
+                  __entry->vcpu_pc, __entry->hxfar,
+                  __entry->ipa, __entry->hsr)
+);
+TRACE_EVENT(kvm_irq_line,
+        TP_PROTO(unsigned int type, int vcpu_idx, int irq_num, int level),
+        TP_ARGS(type, vcpu_idx, irq_num, level),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   type            )
+                __field(        int,            vcpu_idx        )
+                __field(        int,            irq_num         )
+                __field(        int,            level           )
+        ),
+        TP_fast_assign(
+                __entry->type           = type;
+                __entry->vcpu_idx       = vcpu_idx;
+                __entry->irq_num        = irq_num;
+                __entry->level          = level;
+        ),
+        TP_printk("Inject %s interrupt (%d), vcpu->idx: %d, num: %d, level: %d",
+                  (__entry->type == KVM_ARM_IRQ_TYPE_CPU) ? "CPU" :
+                  (__entry->type == KVM_ARM_IRQ_TYPE_PPI) ? "VGIC PPI" :
+                  (__entry->type == KVM_ARM_IRQ_TYPE_SPI) ? "VGIC SPI" : "UNKNOWN",
+                  __entry->type, __entry->vcpu_idx, __entry->irq_num, __entry->level)
+);
+TRACE_EVENT(kvm_mmio_emulate,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long instr,
+                 unsigned long cpsr),
+        TP_ARGS(vcpu_pc, instr, cpsr),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  instr           )
+                __field(        unsigned long,  cpsr            )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->instr                  = instr;
+                __entry->cpsr                   = cpsr;
+        ),
+        TP_printk("Emulate MMIO at: 0x%08lx (instr: %08lx, cpsr: %08lx)",
+                  __entry->vcpu_pc, __entry->instr, __entry->cpsr)
+);
+/* Architecturally implementation defined CP15 register access */
+TRACE_EVENT(kvm_emulate_cp15_imp,
+        TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
+                 unsigned long CRm, unsigned long Op2, bool is_write),
+        TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   Op1             )
+                __field(        unsigned int,   Rt1             )
+                __field(        unsigned int,   CRn             )
+                __field(        unsigned int,   CRm             )
+                __field(        unsigned int,   Op2             )
+                __field(        bool,           is_write        )
+        ),
+        TP_fast_assign(
+                __entry->is_write               = is_write;
+                __entry->Op1                    = Op1;
+                __entry->Rt1                    = Rt1;
+                __entry->CRn                    = CRn;
+                __entry->CRm                    = CRm;
+                __entry->Op2                    = Op2;
+        ),
+        TP_printk("Implementation defined CP15: %s\tp15, %u, r%u, c%u, c%u, %u",
+                        (__entry->is_write) ? "mcr" : "mrc",
+                        __entry->Op1, __entry->Rt1, __entry->CRn,
+                        __entry->CRm, __entry->Op2)
+);
+TRACE_EVENT(kvm_wfi,
+        TP_PROTO(unsigned long vcpu_pc),
+        TP_ARGS(vcpu_pc),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+        ),
+        TP_printk("guest executed wfi at: 0x%08lx", __entry->vcpu_pc)
+);
+TRACE_EVENT(kvm_unmap_hva,
+        TP_PROTO(unsigned long hva),
+        TP_ARGS(hva),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  hva             )
+        ),
+        TP_fast_assign(
+                __entry->hva            = hva;
+        ),
+        TP_printk("mmu notifier unmap hva: %#08lx", __entry->hva)
+);
+TRACE_EVENT(kvm_unmap_hva_range,
+        TP_PROTO(unsigned long start, unsigned long end),
+        TP_ARGS(start, end),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  start           )
+                __field(        unsigned long,  end             )
+        ),
+        TP_fast_assign(
+                __entry->start          = start;
+                __entry->end            = end;
+        ),
+        TP_printk("mmu notifier unmap range: %#08lx -- %#08lx",
+                  __entry->start, __entry->end)
+);
+TRACE_EVENT(kvm_set_spte_hva,
+        TP_PROTO(unsigned long hva),
+        TP_ARGS(hva),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  hva             )
+        ),
+        TP_fast_assign(
+                __entry->hva            = hva;
+        ),
+        TP_printk("mmu notifier set pte hva: %#08lx", __entry->hva)
+);
+TRACE_EVENT(kvm_hvc,
+        TP_PROTO(unsigned long vcpu_pc, unsigned long r0, unsigned long imm),
+        TP_ARGS(vcpu_pc, r0, imm),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  vcpu_pc         )
+                __field(        unsigned long,  r0              )
+                __field(        unsigned long,  imm             )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_pc                = vcpu_pc;
+                __entry->r0             = r0;
+                __entry->imm            = imm;
+        ),
+        TP_printk("HVC at 0x%08lx (r0: 0x%08lx, imm: 0x%lx",
+                  __entry->vcpu_pc, __entry->r0, __entry->imm)
+);
+#endif /* _TRACE_KVM_H */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH arch/arm/kvm
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE trace
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
new file mode 100644
index 000000000000..c9a17316e9fe
--- /dev/null
+++ b/arch/arm/kvm/vgic.c
@@ -0,0 +1,1506 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/cpu.h>
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+/*
+ * How the whole thing works (courtesy of Christoffer Dall):
+ *
+ * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
+ *   something is pending
+ * - VGIC pending interrupts are stored on the vgic.irq_state vgic
+ *   bitmap (this bitmap is updated by both user land ioctls and guest
+ *   mmio ops, and other in-kernel peripherals such as the
+ *   arch. timers) and indicate the 'wire' state.
+ * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
+ *   recalculated
+ * - To calculate the oracle, we need info for each cpu from
+ *   compute_pending_for_cpu, which considers:
+ *   - PPI: dist->irq_state & dist->irq_enable
+ *   - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
+ *   - irq_spi_target is a 'formatted' version of the GICD_ICFGR
+ *     registers, stored on each vcpu. We only keep one bit of
+ *     information per interrupt, making sure that only one vcpu can
+ *     accept the interrupt.
+ * - The same is true when injecting an interrupt, except that we only
+ *   consider a single interrupt at a time. The irq_spi_cpu array
+ *   contains the target CPU for each SPI.
+ *
+ * The handling of level interrupts adds some extra complexity. We
+ * need to track when the interrupt has been EOIed, so we can sample
+ * the 'line' again. This is achieved as such:
+ *
+ * - When a level interrupt is moved onto a vcpu, the corresponding
+ *   bit in irq_active is set. As long as this bit is set, the line
+ *   will be ignored for further interrupts. The interrupt is injected
+ *   into the vcpu with the GICH_LR_EOI bit set (generate a
+ *   maintenance interrupt on EOI).
+ * - When the interrupt is EOIed, the maintenance interrupt fires,
+ *   and clears the corresponding bit in irq_active. This allow the
+ *   interrupt line to be sampled again.
+ */
+#define VGIC_ADDR_UNDEF         (-1)
+#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
+/* Physical address of vgic virtual cpu interface */
+static phys_addr_t vgic_vcpu_base;
+/* Virtual control interface base address */
+static void __iomem *vgic_vctrl_base;
+static struct device_node *vgic_node;
+#define ACCESS_READ_VALUE       (1 << 0)
+#define ACCESS_READ_RAZ         (0 << 0)
+#define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
+#define ACCESS_WRITE_IGNORED    (0 << 1)
+#define ACCESS_WRITE_SETBIT     (1 << 1)
+#define ACCESS_WRITE_CLEARBIT   (2 << 1)
+#define ACCESS_WRITE_VALUE      (3 << 1)
+#define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
+static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
+static void vgic_update_state(struct kvm *kvm);
+static void vgic_kick_vcpus(struct kvm *kvm);
+static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
+static u32 vgic_nr_lr;
+static unsigned int vgic_maint_irq;
+static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
+                                int cpuid, u32 offset)
+{
+        offset >>= 2;
+        if (!offset)
+                return x->percpu[cpuid].reg;
+        else
+                return x->shared.reg + offset - 1;
+}
+static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
+                                   int cpuid, int irq)
+{
+        if (irq < VGIC_NR_PRIVATE_IRQS)
+                return test_bit(irq, x->percpu[cpuid].reg_ul);
+        return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
+}
+static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
+                                    int irq, int val)
+{
+        unsigned long *reg;
+        if (irq < VGIC_NR_PRIVATE_IRQS) {
+                reg = x->percpu[cpuid].reg_ul;
+        } else {
+                reg =  x->shared.reg_ul;
+                irq -= VGIC_NR_PRIVATE_IRQS;
+        }
+        if (val)
+                set_bit(irq, reg);
+        else
+                clear_bit(irq, reg);
+}
+static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
+{
+        if (unlikely(cpuid >= VGIC_MAX_CPUS))
+                return NULL;
+        return x->percpu[cpuid].reg_ul;
+}
+static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
+{
+        return x->shared.reg_ul;
+}
+static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
+{
+        offset >>= 2;
+        BUG_ON(offset > (VGIC_NR_IRQS / 4));
+        if (offset < 4)
+                return x->percpu[cpuid] + offset;
+        else
+                return x->shared + offset - 8;
+}
+#define VGIC_CFG_LEVEL  0
+#define VGIC_CFG_EDGE   1
+static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        int irq_val;
+        irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
+        return irq_val == VGIC_CFG_EDGE;
+}
+static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
+}
+static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
+}
+static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
+}
+static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
+}
+static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
+}
+static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
+}
+static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
+}
+static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
+{
+        if (irq < VGIC_NR_PRIVATE_IRQS)
+                set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
+        else
+                set_bit(irq - VGIC_NR_PRIVATE_IRQS,
+                        vcpu->arch.vgic_cpu.pending_shared);
+}
+static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
+{
+        if (irq < VGIC_NR_PRIVATE_IRQS)
+                clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
+        else
+                clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
+                          vcpu->arch.vgic_cpu.pending_shared);
+}
+static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
+{
+        return *((u32 *)mmio->data) & mask;
+}
+static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
+{
+        *((u32 *)mmio->data) = value & mask;
+}
+/**
+ * vgic_reg_access - access vgic register
+ * @mmio:   pointer to the data describing the mmio access
+ * @reg:    pointer to the virtual backing of vgic distributor data
+ * @offset: least significant 2 bits used for word offset
+ * @mode:   ACCESS_ mode (see defines above)
+ *
+ * Helper to make vgic register access easier using one of the access
+ * modes defined for vgic register access
+ * (read,raz,write-ignored,setbit,clearbit,write)
+ */
+static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
+                            phys_addr_t offset, int mode)
+{
+        int word_offset = (offset & 3) * 8;
+        u32 mask = (1UL << (mmio->len * 8)) - 1;
+        u32 regval;
+        /*
+         * Any alignment fault should have been delivered to the guest
+         * directly (ARM ARM B3.12.7 "Prioritization of aborts").
+         */
+        if (reg) {
+                regval = *reg;
+        } else {
+                BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
+                regval = 0;
+        }
+        if (mmio->is_write) {
+                u32 data = mmio_data_read(mmio, mask) << word_offset;
+                switch (ACCESS_WRITE_MASK(mode)) {
+                case ACCESS_WRITE_IGNORED:
+                        return;
+                case ACCESS_WRITE_SETBIT:
+                        regval |= data;
+                        break;
+                case ACCESS_WRITE_CLEARBIT:
+                        regval &= ~data;
+                        break;
+                case ACCESS_WRITE_VALUE:
+                        regval = (regval & ~(mask << word_offset)) | data;
+                        break;
+                }
+                *reg = regval;
+        } else {
+                switch (ACCESS_READ_MASK(mode)) {
+                case ACCESS_READ_RAZ:
+                        regval = 0;
+                        /* fall through */
+                case ACCESS_READ_VALUE:
+                        mmio_data_write(mmio, mask, regval >> word_offset);
+                }
+        }
+}
+static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
+                             struct kvm_exit_mmio *mmio, phys_addr_t offset)
+{
+        u32 reg;
+        u32 word_offset = offset & 3;
+        switch (offset & ~3) {
+        case 0:                 /* CTLR */
+                reg = vcpu->kvm->arch.vgic.enabled;
+                vgic_reg_access(mmio, &reg, word_offset,
+                                ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
+                if (mmio->is_write) {
+                        vcpu->kvm->arch.vgic.enabled = reg & 1;
+                        vgic_update_state(vcpu->kvm);
+                        return true;
+                }
+                break;
+        case 4:                 /* TYPER */
+                reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
+                reg |= (VGIC_NR_IRQS >> 5) - 1;
+                vgic_reg_access(mmio, &reg, word_offset,
+                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
+                break;
+        case 8:                 /* IIDR */
+                reg = 0x4B00043B;
+                vgic_reg_access(mmio, &reg, word_offset,
+                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
+                break;
+        }
+        return false;
+}
+static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
+                               struct kvm_exit_mmio *mmio, phys_addr_t offset)
+{
+        vgic_reg_access(mmio, NULL, offset,
+                        ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
+        return false;
+}
+static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
+                                       struct kvm_exit_mmio *mmio,
+                                       phys_addr_t offset)
+{
+        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
+                                       vcpu->vcpu_id, offset);
+        vgic_reg_access(mmio, reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
+        if (mmio->is_write) {
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
+                                         struct kvm_exit_mmio *mmio,
+                                         phys_addr_t offset)
+{
+        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
+                                       vcpu->vcpu_id, offset);
+        vgic_reg_access(mmio, reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
+        if (mmio->is_write) {
+                if (offset < 4) /* Force SGI enabled */
+                        *reg |= 0xffff;
+                vgic_retire_disabled_irqs(vcpu);
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
+                                        struct kvm_exit_mmio *mmio,
+                                        phys_addr_t offset)
+{
+        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
+                                       vcpu->vcpu_id, offset);
+        vgic_reg_access(mmio, reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
+        if (mmio->is_write) {
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
+                                          struct kvm_exit_mmio *mmio,
+                                          phys_addr_t offset)
+{
+        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
+                                       vcpu->vcpu_id, offset);
+        vgic_reg_access(mmio, reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
+        if (mmio->is_write) {
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
+                                     struct kvm_exit_mmio *mmio,
+                                     phys_addr_t offset)
+{
+        u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
+                                        vcpu->vcpu_id, offset);
+        vgic_reg_access(mmio, reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
+        return false;
+}
+#define GICD_ITARGETSR_SIZE     32
+#define GICD_CPUTARGETS_BITS    8
+#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
+static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
+{
+        struct vgic_dist *dist = &kvm->arch.vgic;
+        struct kvm_vcpu *vcpu;
+        int i, c;
+        unsigned long *bmap;
+        u32 val = 0;
+        irq -= VGIC_NR_PRIVATE_IRQS;
+        kvm_for_each_vcpu(c, vcpu, kvm) {
+                bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
+                for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
+                        if (test_bit(irq + i, bmap))
+                                val |= 1 << (c + i * 8);
+        }
+        return val;
+}
+static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
+{
+        struct vgic_dist *dist = &kvm->arch.vgic;
+        struct kvm_vcpu *vcpu;
+        int i, c;
+        unsigned long *bmap;
+        u32 target;
+        irq -= VGIC_NR_PRIVATE_IRQS;
+        /*
+         * Pick the LSB in each byte. This ensures we target exactly
+         * one vcpu per IRQ. If the byte is null, assume we target
+         * CPU0.
+         */
+        for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
+                int shift = i * GICD_CPUTARGETS_BITS;
+                target = ffs((val >> shift) & 0xffU);
+                target = target ? (target - 1) : 0;
+                dist->irq_spi_cpu[irq + i] = target;
+                kvm_for_each_vcpu(c, vcpu, kvm) {
+                        bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
+                        if (c == target)
+                                set_bit(irq + i, bmap);
+                        else
+                                clear_bit(irq + i, bmap);
+                }
+        }
+}
+static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
+                                   struct kvm_exit_mmio *mmio,
+                                   phys_addr_t offset)
+{
+        u32 reg;
+        /* We treat the banked interrupts targets as read-only */
+        if (offset < 32) {
+                u32 roreg = 1 << vcpu->vcpu_id;
+                roreg |= roreg << 8;
+                roreg |= roreg << 16;
+                vgic_reg_access(mmio, &roreg, offset,
+                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
+                return false;
+        }
+        reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
+        vgic_reg_access(mmio, &reg, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
+        if (mmio->is_write) {
+                vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+static u32 vgic_cfg_expand(u16 val)
+{
+        u32 res = 0;
+        int i;
+        /*
+         * Turn a 16bit value like abcd...mnop into a 32bit word
+         * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
+         */
+        for (i = 0; i < 16; i++)
+                res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
+        return res;
+}
+static u16 vgic_cfg_compress(u32 val)
+{
+        u16 res = 0;
+        int i;
+        /*
+         * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
+         * abcd...mnop which is what we really care about.
+         */
+        for (i = 0; i < 16; i++)
+                res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
+        return res;
+}
+/*
+ * The distributor uses 2 bits per IRQ for the CFG register, but the
+ * LSB is always 0. As such, we only keep the upper bit, and use the
+ * two above functions to compress/expand the bits
+ */
+static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
+                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
+{
+        u32 val;
+        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
+                                       vcpu->vcpu_id, offset >> 1);
+        if (offset & 2)
+                val = *reg >> 16;
+        else
+                val = *reg & 0xffff;
+        val = vgic_cfg_expand(val);
+        vgic_reg_access(mmio, &val, offset,
+                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
+        if (mmio->is_write) {
+                if (offset < 4) {
+                        *reg = ~0U; /* Force PPIs/SGIs to 1 */
+                        return false;
+                }
+                val = vgic_cfg_compress(val);
+                if (offset & 2) {
+                        *reg &= 0xffff;
+                        *reg |= val << 16;
+                } else {
+                        *reg &= 0xffff << 16;
+                        *reg |= val;
+                }
+        }
+        return false;
+}
+static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
+                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
+{
+        u32 reg;
+        vgic_reg_access(mmio, &reg, offset,
+                        ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
+        if (mmio->is_write) {
+                vgic_dispatch_sgi(vcpu, reg);
+                vgic_update_state(vcpu->kvm);
+                return true;
+        }
+        return false;
+}
+/*
+ * I would have liked to use the kvm_bus_io_*() API instead, but it
+ * cannot cope with banked registers (only the VM pointer is passed
+ * around, and we need the vcpu). One of these days, someone please
+ * fix it!
+ */
+struct mmio_range {
+        phys_addr_t base;
+        unsigned long len;
+        bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
+                            phys_addr_t offset);
+};
+static const struct mmio_range vgic_ranges[] = {
+        {
+                .base           = GIC_DIST_CTRL,
+                .len            = 12,
+                .handle_mmio    = handle_mmio_misc,
+        },
+        {
+                .base           = GIC_DIST_IGROUP,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_raz_wi,
+        },
+        {
+                .base           = GIC_DIST_ENABLE_SET,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_set_enable_reg,
+        },
+        {
+                .base           = GIC_DIST_ENABLE_CLEAR,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_clear_enable_reg,
+        },
+        {
+                .base           = GIC_DIST_PENDING_SET,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_set_pending_reg,
+        },
+        {
+                .base           = GIC_DIST_PENDING_CLEAR,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_clear_pending_reg,
+        },
+        {
+                .base           = GIC_DIST_ACTIVE_SET,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_raz_wi,
+        },
+        {
+                .base           = GIC_DIST_ACTIVE_CLEAR,
+                .len            = VGIC_NR_IRQS / 8,
+                .handle_mmio    = handle_mmio_raz_wi,
+        },
+        {
+                .base           = GIC_DIST_PRI,
+                .len            = VGIC_NR_IRQS,
+                .handle_mmio    = handle_mmio_priority_reg,
+        },
+        {
+                .base           = GIC_DIST_TARGET,
+                .len            = VGIC_NR_IRQS,
+                .handle_mmio    = handle_mmio_target_reg,
+        },
+        {
+                .base           = GIC_DIST_CONFIG,
+                .len            = VGIC_NR_IRQS / 4,
+                .handle_mmio    = handle_mmio_cfg_reg,
+        },
+        {
+                .base           = GIC_DIST_SOFTINT,
+                .len            = 4,
+                .handle_mmio    = handle_mmio_sgi_reg,
+        },
+        {}
+};
+static const
+struct mmio_range *find_matching_range(const struct mmio_range *ranges,
+                                       struct kvm_exit_mmio *mmio,
+                                       phys_addr_t base)
+{
+        const struct mmio_range *r = ranges;
+        phys_addr_t addr = mmio->phys_addr - base;
+        while (r->len) {
+                if (addr >= r->base &&
+                    (addr + mmio->len) <= (r->base + r->len))
+                        return r;
+                r++;
+        }
+        return NULL;
+}
+/**
+ * vgic_handle_mmio - handle an in-kernel MMIO access
+ * @vcpu:       pointer to the vcpu performing the access
+ * @run:        pointer to the kvm_run structure
+ * @mmio:       pointer to the data describing the access
+ *
+ * returns true if the MMIO access has been performed in kernel space,
+ * and false if it needs to be emulated in user space.
+ */
+bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                      struct kvm_exit_mmio *mmio)
+{
+        const struct mmio_range *range;
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        unsigned long base = dist->vgic_dist_base;
+        bool updated_state;
+        unsigned long offset;
+        if (!irqchip_in_kernel(vcpu->kvm) ||
+            mmio->phys_addr < base ||
+            (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
+                return false;
+        /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
+        if (mmio->len > 4) {
+                kvm_inject_dabt(vcpu, mmio->phys_addr);
+                return true;
+        }
+        range = find_matching_range(vgic_ranges, mmio, base);
+        if (unlikely(!range || !range->handle_mmio)) {
+                pr_warn("Unhandled access %d %08llx %d\n",
+                        mmio->is_write, mmio->phys_addr, mmio->len);
+                return false;
+        }
+        spin_lock(&vcpu->kvm->arch.vgic.lock);
+        offset = mmio->phys_addr - range->base - base;
+        updated_state = range->handle_mmio(vcpu, mmio, offset);
+        spin_unlock(&vcpu->kvm->arch.vgic.lock);
+        kvm_prepare_mmio(run, mmio);
+        kvm_handle_mmio_return(vcpu, run);
+        if (updated_state)
+                vgic_kick_vcpus(vcpu->kvm);
+        return true;
+}
+static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
+{
+        struct kvm *kvm = vcpu->kvm;
+        struct vgic_dist *dist = &kvm->arch.vgic;
+        int nrcpus = atomic_read(&kvm->online_vcpus);
+        u8 target_cpus;
+        int sgi, mode, c, vcpu_id;
+        vcpu_id = vcpu->vcpu_id;
+        sgi = reg & 0xf;
+        target_cpus = (reg >> 16) & 0xff;
+        mode = (reg >> 24) & 3;
+        switch (mode) {
+        case 0:
+                if (!target_cpus)
+                        return;
+        case 1:
+                target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
+                break;
+        case 2:
+                target_cpus = 1 << vcpu_id;
+                break;
+        }
+        kvm_for_each_vcpu(c, vcpu, kvm) {
+                if (target_cpus & 1) {
+                        /* Flag the SGI as pending */
+                        vgic_dist_irq_set(vcpu, sgi);
+                        dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
+                        kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
+                }
+                target_cpus >>= 1;
+        }
+}
+static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
+        unsigned long pending_private, pending_shared;
+        int vcpu_id;
+        vcpu_id = vcpu->vcpu_id;
+        pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
+        pend_shared = vcpu->arch.vgic_cpu.pending_shared;
+        pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
+        enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
+        bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
+        pending = vgic_bitmap_get_shared_map(&dist->irq_state);
+        enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
+        bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
+        bitmap_and(pend_shared, pend_shared,
+                   vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
+                   VGIC_NR_SHARED_IRQS);
+        pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
+        pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
+        return (pending_private < VGIC_NR_PRIVATE_IRQS ||
+                pending_shared < VGIC_NR_SHARED_IRQS);
+}
+/*
+ * Update the interrupt state and determine which CPUs have pending
+ * interrupts. Must be called with distributor lock held.
+ */
+static void vgic_update_state(struct kvm *kvm)
+{
+        struct vgic_dist *dist = &kvm->arch.vgic;
+        struct kvm_vcpu *vcpu;
+        int c;
+        if (!dist->enabled) {
+                set_bit(0, &dist->irq_pending_on_cpu);
+                return;
+        }
+        kvm_for_each_vcpu(c, vcpu, kvm) {
+                if (compute_pending_for_cpu(vcpu)) {
+                        pr_debug("CPU%d has pending interrupts\n", c);
+                        set_bit(c, &dist->irq_pending_on_cpu);
+                }
+        }
+}
+#define LR_CPUID(lr)    \
+        (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
+#define MK_LR_PEND(src, irq)    \
+        (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
+/*
+ * An interrupt may have been disabled after being made pending on the
+ * CPU interface (the classic case is a timer running while we're
+ * rebooting the guest - the interrupt would kick as soon as the CPU
+ * interface gets enabled, with deadly consequences).
+ *
+ * The solution is to examine already active LRs, and check the
+ * interrupt is still enabled. If not, just retire it.
+ */
+static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        int lr;
+        for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
+                int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
+                if (!vgic_irq_is_enabled(vcpu, irq)) {
+                        vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
+                        clear_bit(lr, vgic_cpu->lr_used);
+                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE;
+                        if (vgic_irq_is_active(vcpu, irq))
+                                vgic_irq_clear_active(vcpu, irq);
+                }
+        }
+}
+/*
+ * Queue an interrupt to a CPU virtual interface. Return true on success,
+ * or false if it wasn't possible to queue it.
+ */
+static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        int lr;
+        /* Sanitize the input... */
+        BUG_ON(sgi_source_id & ~7);
+        BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
+        BUG_ON(irq >= VGIC_NR_IRQS);
+        kvm_debug("Queue IRQ%d\n", irq);
+        lr = vgic_cpu->vgic_irq_lr_map[irq];
+        /* Do we have an active interrupt for the same CPUID? */
+        if (lr != LR_EMPTY &&
+            (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
+                kvm_debug("LR%d piggyback for IRQ%d %x\n",
+                          lr, irq, vgic_cpu->vgic_lr[lr]);
+                BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
+                vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
+                goto out;
+        }
+        /* Try to use another LR for this interrupt */
+        lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
+                               vgic_cpu->nr_lr);
+        if (lr >= vgic_cpu->nr_lr)
+                return false;
+        kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
+        vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
+        vgic_cpu->vgic_irq_lr_map[irq] = lr;
+        set_bit(lr, vgic_cpu->lr_used);
+out:
+        if (!vgic_irq_is_edge(vcpu, irq))
+                vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
+        return true;
+}
+static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        unsigned long sources;
+        int vcpu_id = vcpu->vcpu_id;
+        int c;
+        sources = dist->irq_sgi_sources[vcpu_id][irq];
+        for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
+                if (vgic_queue_irq(vcpu, c, irq))
+                        clear_bit(c, &sources);
+        }
+        dist->irq_sgi_sources[vcpu_id][irq] = sources;
+        /*
+         * If the sources bitmap has been cleared it means that we
+         * could queue all the SGIs onto link registers (see the
+         * clear_bit above), and therefore we are done with them in
+         * our emulated gic and can get rid of them.
+         */
+        if (!sources) {
+                vgic_dist_irq_clear(vcpu, irq);
+                vgic_cpu_irq_clear(vcpu, irq);
+                return true;
+        }
+        return false;
+}
+static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
+{
+        if (vgic_irq_is_active(vcpu, irq))
+                return true; /* level interrupt, already queued */
+        if (vgic_queue_irq(vcpu, 0, irq)) {
+                if (vgic_irq_is_edge(vcpu, irq)) {
+                        vgic_dist_irq_clear(vcpu, irq);
+                        vgic_cpu_irq_clear(vcpu, irq);
+                } else {
+                        vgic_irq_set_active(vcpu, irq);
+                }
+                return true;
+        }
+        return false;
+}
+/*
+ * Fill the list registers with pending interrupts before running the
+ * guest.
+ */
+static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        int i, vcpu_id;
+        int overflow = 0;
+        vcpu_id = vcpu->vcpu_id;
+        /*
+         * We may not have any pending interrupt, or the interrupts
+         * may have been serviced from another vcpu. In all cases,
+         * move along.
+         */
+        if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
+                pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
+                goto epilog;
+        }
+        /* SGIs */
+        for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
+                if (!vgic_queue_sgi(vcpu, i))
+                        overflow = 1;
+        }
+        /* PPIs */
+        for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
+                if (!vgic_queue_hwirq(vcpu, i))
+                        overflow = 1;
+        }
+        /* SPIs */
+        for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
+                if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
+                        overflow = 1;
+        }
+epilog:
+        if (overflow) {
+                vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
+        } else {
+                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
+                /*
+                 * We're about to run this VCPU, and we've consumed
+                 * everything the distributor had in store for
+                 * us. Claim we don't have anything pending. We'll
+                 * adjust that if needed while exiting.
+                 */
+                clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
+        }
+}
+static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        bool level_pending = false;
+        kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
+        /*
+         * We do not need to take the distributor lock here, since the only
+         * action we perform is clearing the irq_active_bit for an EOIed
+         * level interrupt.  There is a potential race with
+         * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
+         * check if the interrupt is already active. Two possibilities:
+         *
+         * - The queuing is occurring on the same vcpu: cannot happen,
+         *   as we're already in the context of this vcpu, and
+         *   executing the handler
+         * - The interrupt has been migrated to another vcpu, and we
+         *   ignore this interrupt for this run. Big deal. It is still
+         *   pending though, and will get considered when this vcpu
+         *   exits.
+         */
+        if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
+                /*
+                 * Some level interrupts have been EOIed. Clear their
+                 * active bit.
+                 */
+                int lr, irq;
+                for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
+                                 vgic_cpu->nr_lr) {
+                        irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
+                        vgic_irq_clear_active(vcpu, irq);
+                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
+                        /* Any additional pending interrupt? */
+                        if (vgic_dist_irq_is_pending(vcpu, irq)) {
+                                vgic_cpu_irq_set(vcpu, irq);
+                                level_pending = true;
+                        } else {
+                                vgic_cpu_irq_clear(vcpu, irq);
+                        }
+                }
+        }
+        if (vgic_cpu->vgic_misr & GICH_MISR_U)
+                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
+        return level_pending;
+}
+/*
+ * Sync back the VGIC state after a guest run. We do not really touch
+ * the distributor here (the irq_pending_on_cpu bit is safe to set),
+ * so there is no need for taking its lock.
+ */
+static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        int lr, pending;
+        bool level_pending;
+        level_pending = vgic_process_maintenance(vcpu);
+        /* Clear mappings for empty LRs */
+        for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
+                         vgic_cpu->nr_lr) {
+                int irq;
+                if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
+                        continue;
+                irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
+                BUG_ON(irq >= VGIC_NR_IRQS);
+                vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
+        }
+        /* Check if we still have something up our sleeve... */
+        pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
+                                      vgic_cpu->nr_lr);
+        if (level_pending || pending < vgic_cpu->nr_lr)
+                set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
+}
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+        spin_lock(&dist->lock);
+        __kvm_vgic_flush_hwstate(vcpu);
+        spin_unlock(&dist->lock);
+}
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+        __kvm_vgic_sync_hwstate(vcpu);
+}
+int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
+{
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return 0;
+        return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
+}
+static void vgic_kick_vcpus(struct kvm *kvm)
+{
+        struct kvm_vcpu *vcpu;
+        int c;
+        /*
+         * We've injected an interrupt, time to find out who deserves
+         * a good kick...
+         */
+        kvm_for_each_vcpu(c, vcpu, kvm) {
+                if (kvm_vgic_vcpu_pending_irq(vcpu))
+                        kvm_vcpu_kick(vcpu);
+        }
+}
+static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
+{
+        int is_edge = vgic_irq_is_edge(vcpu, irq);
+        int state = vgic_dist_irq_is_pending(vcpu, irq);
+        /*
+         * Only inject an interrupt if:
+         * - edge triggered and we have a rising edge
+         * - level triggered and we change level
+         */
+        if (is_edge)
+                return level > state;
+        else
+                return level != state;
+}
+static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
+                                  unsigned int irq_num, bool level)
+{
+        struct vgic_dist *dist = &kvm->arch.vgic;
+        struct kvm_vcpu *vcpu;
+        int is_edge, is_level;
+        int enabled;
+        bool ret = true;
+        spin_lock(&dist->lock);
+        vcpu = kvm_get_vcpu(kvm, cpuid);
+        is_edge = vgic_irq_is_edge(vcpu, irq_num);
+        is_level = !is_edge;
+        if (!vgic_validate_injection(vcpu, irq_num, level)) {
+                ret = false;
+                goto out;
+        }
+        if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
+                cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
+                vcpu = kvm_get_vcpu(kvm, cpuid);
+        }
+        kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
+        if (level)
+                vgic_dist_irq_set(vcpu, irq_num);
+        else
+                vgic_dist_irq_clear(vcpu, irq_num);
+        enabled = vgic_irq_is_enabled(vcpu, irq_num);
+        if (!enabled) {
+                ret = false;
+                goto out;
+        }
+        if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
+                /*
+                 * Level interrupt in progress, will be picked up
+                 * when EOId.
+                 */
+                ret = false;
+                goto out;
+        }
+        if (level) {
+                vgic_cpu_irq_set(vcpu, irq_num);
+                set_bit(cpuid, &dist->irq_pending_on_cpu);
+        }
+out:
+        spin_unlock(&dist->lock);
+        return ret;
+}
+/**
+ * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
+ * @kvm:     The VM structure pointer
+ * @cpuid:   The CPU for PPIs
+ * @irq_num: The IRQ number that is assigned to the device
+ * @level:   Edge-triggered:  true:  to trigger the interrupt
+ *                            false: to ignore the call
+ *           Level-sensitive  true:  activates an interrupt
+ *                            false: deactivates an interrupt
+ *
+ * The GIC is not concerned with devices being active-LOW or active-HIGH for
+ * level-sensitive interrupts.  You can think of the level parameter as 1
+ * being HIGH and 0 being LOW and all devices being active-HIGH.
+ */
+int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
+                        bool level)
+{
+        if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
+                vgic_kick_vcpus(kvm);
+        return 0;
+}
+static irqreturn_t vgic_maintenance_handler(int irq, void *data)
+{
+        /*
+         * We cannot rely on the vgic maintenance interrupt to be
+         * delivered synchronously. This means we can only use it to
+         * exit the VM, and we perform the handling of EOIed
+         * interrupts on the exit path (see vgic_process_maintenance).
+         */
+        return IRQ_HANDLED;
+}
+int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
+{
+        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+        int i;
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return 0;
+        if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
+                return -EBUSY;
+        for (i = 0; i < VGIC_NR_IRQS; i++) {
+                if (i < VGIC_NR_PPIS)
+                        vgic_bitmap_set_irq_val(&dist->irq_enabled,
+                                                vcpu->vcpu_id, i, 1);
+                if (i < VGIC_NR_PRIVATE_IRQS)
+                        vgic_bitmap_set_irq_val(&dist->irq_cfg,
+                                                vcpu->vcpu_id, i, VGIC_CFG_EDGE);
+                vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
+        }
+        /*
+         * By forcing VMCR to zero, the GIC will restore the binary
+         * points to their reset values. Anything else resets to zero
+         * anyway.
+         */
+        vgic_cpu->vgic_vmcr = 0;
+        vgic_cpu->nr_lr = vgic_nr_lr;
+        vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
+        return 0;
+}
+static void vgic_init_maintenance_interrupt(void *info)
+{
+        enable_percpu_irq(vgic_maint_irq, 0);
+}
+static int vgic_cpu_notify(struct notifier_block *self,
+                           unsigned long action, void *cpu)
+{
+        switch (action) {
+        case CPU_STARTING:
+        case CPU_STARTING_FROZEN:
+                vgic_init_maintenance_interrupt(NULL);
+                break;
+        case CPU_DYING:
+        case CPU_DYING_FROZEN:
+                disable_percpu_irq(vgic_maint_irq);
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block vgic_cpu_nb = {
+        .notifier_call = vgic_cpu_notify,
+};
+int kvm_vgic_hyp_init(void)
+{
+        int ret;
+        struct resource vctrl_res;
+        struct resource vcpu_res;
+        vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
+        if (!vgic_node) {
+                kvm_err("error: no compatible vgic node in DT\n");
+                return -ENODEV;
+        }
+        vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
+        if (!vgic_maint_irq) {
+                kvm_err("error getting vgic maintenance irq from DT\n");
+                ret = -ENXIO;
+                goto out;
+        }
+        ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
+                                 "vgic", kvm_get_running_vcpus());
+        if (ret) {
+                kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
+                goto out;
+        }
+        ret = register_cpu_notifier(&vgic_cpu_nb);
+        if (ret) {
+                kvm_err("Cannot register vgic CPU notifier\n");
+                goto out_free_irq;
+        }
+        ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
+        if (ret) {
+                kvm_err("Cannot obtain VCTRL resource\n");
+                goto out_free_irq;
+        }
+        vgic_vctrl_base = of_iomap(vgic_node, 2);
+        if (!vgic_vctrl_base) {
+                kvm_err("Cannot ioremap VCTRL\n");
+                ret = -ENOMEM;
+                goto out_free_irq;
+        }
+        vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
+        vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
+        ret = create_hyp_io_mappings(vgic_vctrl_base,
+                                     vgic_vctrl_base + resource_size(&vctrl_res),
+                                     vctrl_res.start);
+        if (ret) {
+                kvm_err("Cannot map VCTRL into hyp\n");
+                goto out_unmap;
+        }
+        kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
+                 vctrl_res.start, vgic_maint_irq);
+        on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
+        if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
+                kvm_err("Cannot obtain VCPU resource\n");
+                ret = -ENXIO;
+                goto out_unmap;
+        }
+        vgic_vcpu_base = vcpu_res.start;
+        goto out;
+out_unmap:
+        iounmap(vgic_vctrl_base);
+out_free_irq:
+        free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
+out:
+        of_node_put(vgic_node);
+        return ret;
+}
+int kvm_vgic_init(struct kvm *kvm)
+{
+        int ret = 0, i;
+        mutex_lock(&kvm->lock);
+        if (vgic_initialized(kvm))
+                goto out;
+        if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
+            IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
+                kvm_err("Need to set vgic cpu and dist addresses first\n");
+                ret = -ENXIO;
+                goto out;
+        }
+        ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
+                                    vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
+        if (ret) {
+                kvm_err("Unable to remap VGIC CPU to VCPU\n");
+                goto out;
+        }
+        for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
+                vgic_set_target_reg(kvm, 0, i);
+        kvm_timer_init(kvm);
+        kvm->arch.vgic.ready = true;
+out:
+        mutex_unlock(&kvm->lock);
+        return ret;
+}
+int kvm_vgic_create(struct kvm *kvm)
+{
+        int ret = 0;
+        mutex_lock(&kvm->lock);
+        if (atomic_read(&kvm->online_vcpus) || kvm->arch.vgic.vctrl_base) {
+                ret = -EEXIST;
+                goto out;
+        }
+        spin_lock_init(&kvm->arch.vgic.lock);
+        kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
+        kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
+        kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
+out:
+        mutex_unlock(&kvm->lock);
+        return ret;
+}
+static bool vgic_ioaddr_overlap(struct kvm *kvm)
+{
+        phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
+        phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
+        if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
+                return 0;
+        if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
+            (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
+                return -EBUSY;
+        return 0;
+}
+static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
+                              phys_addr_t addr, phys_addr_t size)
+{
+        int ret;
+        if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
+                return -EEXIST;
+        if (addr + size < addr)
+                return -EINVAL;
+        ret = vgic_ioaddr_overlap(kvm);
+        if (ret)
+                return ret;
+        *ioaddr = addr;
+        return ret;
+}
+int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
+{
+        int r = 0;
+        struct vgic_dist *vgic = &kvm->arch.vgic;
+        if (addr & ~KVM_PHYS_MASK)
+                return -E2BIG;
+        if (addr & ~PAGE_MASK)
+                return -EINVAL;
+        mutex_lock(&kvm->lock);
+        switch (type) {
+        case KVM_VGIC_V2_ADDR_TYPE_DIST:
+                r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
+                                       addr, KVM_VGIC_V2_DIST_SIZE);
+                break;
+        case KVM_VGIC_V2_ADDR_TYPE_CPU:
+                r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
+                                       addr, KVM_VGIC_V2_CPU_SIZE);
+                break;
+        default:
+                r = -ENODEV;
+        }
+        mutex_unlock(&kvm->lock);
+        return r;
+}
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 0dc53854a5d8..6b93f6a1a3c7 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -77,6 +77,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
                arm_delay_ops.delay             = __timer_delay;
                arm_delay_ops.const_udelay      = __timer_const_udelay;
                arm_delay_ops.udelay            = __timer_udelay;
+                arm_delay_ops.const_clock       = true;
                delay_calibrated                = true;
        } else {
                pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 958358c91afd..6071f4c3d654 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -352,12 +352,6 @@ config MACH_USB_A9263
          Select this if you are using a Calao Systems USB-A9263.
          <http://www.calao-systems.com>
-config MACH_NEOCORE926
-        bool "Adeneo NEOCORE926"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using the Adeneo Neocore 926 board.
 endif
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b38a1dcb79b8..39218ca6d8e8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,7 +66,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
 obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
-obj-$(CONFIG_MACH_NEOCORE926)   += board-neocore926.o
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 7aeb473ee539..9706c000f294 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -210,6 +210,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
+        CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
        CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index cafe98836c8a..2acdff4c1dfe 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 static struct clock_event_device clkevt = {
        .name           = "at91_tick",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .rating         = 150,
        .set_next_event = clkevt32k_next_event,
        .set_mode       = clkevt32k_mode,
@@ -265,17 +264,10 @@ void __init at91rm9200_timer_init(void)
        at91_st_write(AT91_ST_RTMR, 1);
        /* Setup timer clockevent, with minimum of two ticks (important!!) */
-        clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
-        clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
-        clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
        clkevt.cpumask = cpumask_of(0);
-        clockevents_register_device(&clkevt);
+        clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
+                                        2, AT91_ST_ALMV);
        /* register clocksource */
        clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
 }
-struct sys_timer at91rm9200_timer = {
-        .init           = at91rm9200_timer_init,
-};
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 358412f1f5f8..3a4bc2e1a65e 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -104,12 +104,38 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
        }
 }
+static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
+{
+        /* Disable timer */
+        pit_write(AT91_PIT_MR, 0);
+}
+static void at91sam926x_pit_reset(void)
+{
+        /* Disable timer and irqs */
+        pit_write(AT91_PIT_MR, 0);
+        /* Clear any pending interrupts, wait for PIT to stop counting */
+        while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
+                cpu_relax();
+        /* Start PIT but don't enable IRQ */
+        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+}
+static void at91sam926x_pit_resume(struct clock_event_device *cedev)
+{
+        at91sam926x_pit_reset();
+}
 static struct clock_event_device pit_clkevt = {
        .name           = "pit",
        .features       = CLOCK_EVT_FEAT_PERIODIC,
        .shift          = 32,
        .rating         = 100,
        .set_mode       = pit_clkevt_mode,
+        .suspend        = at91sam926x_pit_suspend,
+        .resume         = at91sam926x_pit_resume,
 };
@@ -150,19 +176,6 @@ static struct irqaction at91sam926x_pit_irq = {
        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 };
-static void at91sam926x_pit_reset(void)
-{
-        /* Disable timer and irqs */
-        pit_write(AT91_PIT_MR, 0);
-        /* Clear any pending interrupts, wait for PIT to stop counting */
-        while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
-                cpu_relax();
-        /* Start PIT but don't enable IRQ */
-        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
-}
 #ifdef CONFIG_OF
 static struct of_device_id pit_timer_ids[] = {
        { .compatible = "atmel,at91sam9260-pit" },
@@ -211,7 +224,7 @@ static int __init of_at91sam926x_pit_init(void)
 /*
 * Set up both clocksource and clockevent support.
 */
-static void __init at91sam926x_pit_init(void)
+void __init at91sam926x_pit_init(void)
 {
        unsigned long   pit_rate;
        unsigned        bits;
@@ -250,12 +263,6 @@ static void __init at91sam926x_pit_init(void)
        clockevents_register_device(&pit_clkevt);
 }
-static void at91sam926x_pit_suspend(void)
-{
-        /* Disable timer */
-        pit_write(AT91_PIT_MR, 0);
-}
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
 #if defined(CONFIG_OF)
@@ -272,9 +279,3 @@ void __init at91sam926x_ioremap_pit(u32 addr)
        if (!pit_base_addr)
                panic("Impossible to ioremap PIT\n");
 }
-struct sys_timer at91sam926x_timer = {
-        .init           = at91sam926x_pit_init,
-        .suspend        = at91sam926x_pit_suspend,
-        .resume         = at91sam926x_pit_reset,
-};
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 0e57e440c061..0c07a4459cb2 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -42,9 +42,10 @@
 #define AT91_TC_CLK1BASE        0x40
 #define AT91_TC_CLK2BASE        0x80
-static unsigned long at91x40_gettimeoffset(void)
+static u32 at91x40_gettimeoffset(void)
 {
-        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
+                (AT91X40_MASTER_CLOCK / 128)) * 1000;
 }
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
@@ -64,6 +65,8 @@ void __init at91x40_timer_init(void)
 {
        unsigned int v;
+        arch_gettimeoffset = at91x40_gettimeoffset;
        at91_tc_write(AT91_TC_BCR, 0);
        v = at91_tc_read(AT91_TC_BMR);
        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
@@ -79,9 +82,3 @@ void __init at91x40_timer_init(void)
        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
-struct sys_timer at91x40_timer = {
-        .init   = at91x40_timer_init,
-        .offset = at91x40_gettimeoffset,
-};
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index b99b5752cc10..35ab632bbf68 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -90,7 +90,7 @@ static void __init onearm_board_init(void)
 MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = onearm_init_early,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 854b97974287..f95e31cda4b3 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -210,7 +210,7 @@ static void __init afeb9260_board_init(void)
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
        /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = afeb9260_init_early,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 28a18ce6d914..ade948b82662 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -187,7 +187,7 @@ static void __init cam60_board_init(void)
 MACHINE_START(CAM60, "KwikByte CAM60")
        /* Maintainer: KwikByte */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = cam60_init_early,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index c17bb533a949..92983050a9bd 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -157,7 +157,7 @@ static void __init carmeva_board_init(void)
 MACHINE_START(CARMEVA, "Carmeva")
        /* Maintainer: Conitec Datasystems */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = carmeva_init_early,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 847432441ecc..008527efdbcf 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -374,7 +374,7 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
 MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 #endif
        /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = cpu9krea_init_early,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2a7af7868747..42f1353a4baf 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -178,7 +178,7 @@ static void __init cpuat91_board_init(void)
 MACHINE_START(CPUAT91, "Eukrea")
        /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = cpuat91_init_early,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 48a531e05be3..e5fde215225b 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -251,7 +251,7 @@ static void __init csb337_board_init(void)
 MACHINE_START(CSB337, "Cogent CSB337")
        /* Maintainer: Bill Gatliff */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = csb337_init_early,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index ec0f3abd504b..fdf11061c577 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -132,7 +132,7 @@ static void __init csb637_board_init(void)
 MACHINE_START(CSB637, "Cogent CSB637")
        /* Maintainer: Bill Gatliff */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = csb637_init_early,
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 881170ce61dd..8db30132abed 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -49,7 +49,7 @@ static const char *at91_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index b489388a6f84..becf0a6a289e 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -44,7 +44,7 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
        /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
-        .timer          = &at91x40_timer,
+        .init_time      = at91x40_timer_init,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = at91eb01_init_early,
        .init_irq       = at91eb01_init_irq,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 9f5e71c95f05..f9be8161bbfa 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -116,7 +116,7 @@ static void __init eb9200_board_init(void)
 }
 MACHINE_START(ATEB9200, "Embest ATEB9200")
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = eb9200_init_early,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index ef69e0ebe949..b2fcd71262ba 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -181,7 +181,7 @@ static void __init ecb_at91board_init(void)
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
        /* Maintainer: emQbit.com */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ecb_at91init_early,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 50f3d3795c05..77de410efc90 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -149,7 +149,7 @@ static void __init eco920_board_init(void)
 MACHINE_START(ECO920, "eco920")
        /* Maintainer: Sascha Hauer */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = eco920_init_early,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 5d44eba0f20f..737c08563628 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -159,7 +159,7 @@ static void __init flexibity_board_init(void)
 MACHINE_START(FLEXIBITY, "Flexibity Connect")
        /* Maintainer: Maxim Osipov */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = flexibity_init_early,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 191d37c16bab..2ea7059b840b 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -261,7 +261,7 @@ static void __init foxg20_board_init(void)
 MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
        /* Maintainer: Sergio Tanzilli */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = foxg20_init_early,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 23a2fa17ab29..c1d61d247790 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -574,7 +574,7 @@ static void __init gsia18s_board_init(void)
 }
 MACHINE_START(GSIA18S, "GS_IA18_S")
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = gsia18s_init_early,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 9a43d1e1a037..88e2f5d2d16d 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -103,7 +103,7 @@ static void __init kafa_board_init(void)
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
        /* Maintainer: Sergei Sharonov */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = kafa_init_early,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index f168bec2369f..0c519d9ebffc 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -149,7 +149,7 @@ static void __init kb9202_board_init(void)
 MACHINE_START(KB9200, "KB920x")
        /* Maintainer: KwikByte, Inc. */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = kb9202_init_early,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
deleted file mode 100644
index bc7a1c4a1f6a..000000000000
--- a/arch/arm/mach-at91/board-neocore926.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-neocore926.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation
- *  Copyright (C) 2008 ADENEO.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/fb.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <video/atmel_lcdc.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/sizes.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-static void __init neocore926_init_early(void)
-{
-        /* Initialize processor: 20 MHz crystal */
-        at91_initialize(20000000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata neocore926_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata neocore926_udc_data = {
-        .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PA15);     /* Touchscreen PENIRQ */
-}
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-static void __init neocore926_add_device_ts(void)
-{
-        at91_set_B_periph(AT91_PIN_PA15, 1);    /* External IRQ1, with pullup */
-        at91_set_gpio_input(AT91_PIN_PC13, 1);  /* Touchscreen BUSY signal */
-}
-#else
-static void __init neocore926_add_device_ts(void) {}
-#endif
-/*
- * SPI devices.
- */
-static struct spi_board_info neocore926_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 1,
-                .max_speed_hz   = 125000 * 16,
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
-        },
-#endif
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata neocore926_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PE18,
-                .wp_pin         = AT91_PIN_PE19,
-        },
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata neocore926_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata neocore926_nand_partition[] = {
-        {
-                .name   = "Linux Kernel",       /* "Partition 1", */
-                .offset = 0,
-                .size   = SZ_8M,
-        },
-        {
-                .name   = "Filesystem",         /* "Partition 2", */
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_32M,
-        },
-        {
-                .name   = "Free",               /* "Partition 3", */
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata neocore926_nand_data = {
-        .ale                    = 21,
-        .cle                    = 22,
-        .rdy_pin                = AT91_PIN_PB19,
-        .rdy_pin_active_low     = 1,
-        .enable_pin             = AT91_PIN_PD15,
-        .ecc_mode               = NAND_ECC_SOFT,
-        .parts                  = neocore926_nand_partition,
-        .num_parts              = ARRAY_SIZE(neocore926_nand_partition),
-        .det_pin                = -EINVAL,
-};
-static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 6,
-        .write_cycle            = 6,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init neocore926_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &neocore926_nand_smc_config);
-        at91_add_device_nand(&neocore926_nand_data);
-}
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(5000),
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(int on)
-{
-        at91_set_gpio_value(AT91_PIN_PA30, on);
-}
-/* Driver datas */
-static struct atmel_lcdfb_info __initdata neocore926_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9263_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB555,
-};
-#else
-static struct atmel_lcdfb_info __initdata neocore926_lcdc_data;
-#endif
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button neocore926_buttons[] = {
-        {       /* BP1, "leftclic" */
-                .code           = BTN_LEFT,
-                .gpio           = AT91_PIN_PC5,
-                .active_low     = 1,
-                .desc           = "left_click",
-                .wakeup         = 1,
-        },
-        {       /* BP2, "rightclic" */
-                .code           = BTN_RIGHT,
-                .gpio           = AT91_PIN_PC4,
-                .active_low     = 1,
-                .desc           = "right_click",
-                .wakeup         = 1,
-        },
-};
-static struct gpio_keys_platform_data neocore926_button_data = {
-        .buttons        = neocore926_buttons,
-        .nbuttons       = ARRAY_SIZE(neocore926_buttons),
-};
-static struct platform_device neocore926_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &neocore926_button_data,
-        }
-};
-static void __init neocore926_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PC5, 0);  /* left button */
-        at91_set_deglitch(AT91_PIN_PC5, 1);
-        at91_set_GPIO_periph(AT91_PIN_PC4, 0);  /* right button */
-        at91_set_deglitch(AT91_PIN_PC4, 1);
-        platform_device_register(&neocore926_button_device);
-}
-#else
-static void __init neocore926_add_device_buttons(void) {}
-#endif
-/*
- * AC97
- */
-static struct ac97c_platform_data neocore926_ac97_data = {
-        .reset_pin      = AT91_PIN_PA13,
-};
-static void __init neocore926_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&neocore926_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&neocore926_udc_data);
-        /* SPI */
-        at91_set_gpio_output(AT91_PIN_PE20, 1);         /* select spi0 clock */
-        at91_add_device_spi(neocore926_spi_devices, ARRAY_SIZE(neocore926_spi_devices));
-        /* Touchscreen */
-        neocore926_add_device_ts();
-        /* MMC */
-        at91_add_device_mci(0, &neocore926_mci0_data);
-        /* Ethernet */
-        at91_add_device_eth(&neocore926_macb_data);
-        /* NAND */
-        neocore926_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LCD Controller */
-        at91_add_device_lcdc(&neocore926_lcdc_data);
-        /* Push Buttons */
-        neocore926_add_device_buttons();
-        /* AC97 */
-        at91_add_device_ac97(&neocore926_ac97_data);
-}
-MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
-        /* Maintainer: ADENEO */
-        .timer          = &at91sam926x_timer,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = neocore926_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = neocore926_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 0299554495dd..65c0d6b5ecba 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -217,7 +217,7 @@ static void __init pcontrol_g20_board_init(void)
 MACHINE_START(PCONTROL_G20, "PControl G20")
        /* Maintainer: pgsellmann@portner-elektronik.at */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = pcontrol_g20_init_early,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 4938f1cd5e13..ab2b2ec36c14 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -119,7 +119,7 @@ static void __init picotux200_board_init(void)
 MACHINE_START(PICOTUX2XX, "picotux 200")
        /* Maintainer: Kleinhenz Elektronik GmbH */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = picotux200_init_early,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 33b1628467ea..aa3bc9b0f150 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -257,7 +257,7 @@ static void __init ek_board_init(void)
 MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
        /* Maintainer: calao-systems */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-rm9200-dt.c
index 5f9ce3da3fde..3fcb6623a33e 100644
--- a/arch/arm/mach-at91/board-rm9200-dt.c
+++ b/arch/arm/mach-at91/board-rm9200-dt.c
@@ -47,7 +47,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
 };
 DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 9e5061bef0d0..690541b18cbc 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -219,7 +219,7 @@ static void __init dk_board_init(void)
 MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
        /* Maintainer: SAN People/Atmel */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = dk_init_early,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 58277dbc718f..8b17dadc1aba 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -186,7 +186,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
        /* Maintainer: SAN People/Atmel */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index 2e8b8339a206..f6d7f1958c7e 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -222,7 +222,7 @@ static void __init rsi_ews_board_init(void)
 MACHINE_START(RSI_EWS, "RSI EWS")
        /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = rsi_ews_init_early,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index b75fbf6003a1..43ee4dc43b50 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -218,7 +218,7 @@ static void __init ek_board_init(void)
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
        /* Maintainer: Olimex */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index f0135cd1d858..0b153c87521d 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -343,7 +343,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 13ebaa8e4100..b446645c7727 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -612,7 +612,7 @@ MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 #endif
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 89b9608742a7..3284df05df14 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -443,7 +443,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 1b7dd9f688d3..f9cd1f2c7146 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -409,7 +409,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
@@ -419,7 +419,7 @@ MACHINE_END
 MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index e4cc375e3a32..2a94896a1375 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -502,7 +502,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 377a1097afa7..aa265dcf2128 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -320,7 +320,7 @@ static void __init ek_board_init(void)
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
        /* Maintainer: Atmel */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 98771500ddb9..3aaa9784cf0e 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -177,7 +177,7 @@ static void __init snapper9260_board_init(void)
 }
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = snapper9260_init_early,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 48a962b61fa3..a033b8df9fb2 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -272,7 +272,7 @@ static void __init stamp9g20evb_board_init(void)
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
        /* Maintainer: taskit GmbH */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = stamp9g20_init_early,
@@ -282,7 +282,7 @@ MACHINE_END
 MACHINE_START(STAMP9G20, "taskit Stamp9G20")
        /* Maintainer: taskit GmbH */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = stamp9g20_init_early,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1060f96e589..2487d944a1bc 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -355,7 +355,7 @@ static void __init ek_board_init(void)
 MACHINE_START(USB_A9263, "CALAO USB_A9263")
        /* Maintainer: calao-systems */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
@@ -365,7 +365,7 @@ MACHINE_END
 MACHINE_START(USB_A9260, "CALAO USB_A9260")
        /* Maintainer: calao-systems */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
@@ -375,7 +375,7 @@ MACHINE_END
 MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
        /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
-        .timer          = &at91sam926x_timer,
+        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = ek_init_early,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 8673aebcb85d..be083771df2e 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -587,7 +587,7 @@ static void __init yl9200_board_init(void)
 MACHINE_START(YL9200, "uCdragon YL-9200")
        /* Maintainer: S.Birtles */
-        .timer          = &at91rm9200_timer,
+        .init_time      = at91rm9200_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = yl9200_init_early,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index fc593d615e7d..78ab06548658 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -36,12 +36,11 @@ extern int  __init at91_aic5_of_init(struct device_node *node,
 /* Timer */
-struct sys_timer;
 extern void at91rm9200_ioremap_st(u32 addr);
-extern struct sys_timer at91rm9200_timer;
+extern void at91rm9200_timer_init(void);
 extern void at91sam926x_ioremap_pit(u32 addr);
-extern struct sys_timer at91sam926x_timer;
+extern void at91sam926x_pit_init(void);
-extern struct sys_timer at91x40_timer;
+extern void at91x40_timer_init(void);
 /* Clocks */
 #ifdef CONFIG_AT91_PMC_UNIT
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 97ad68a826f8..5659f7c72120 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -196,6 +196,4 @@ static inline void flush(void)
                barrier();
 }
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 48705c10a0fe..bf02471d7e7c 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -7,7 +7,6 @@ config ARCH_BCM
        select ARM_GIC
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select GENERIC_TIME
        select GPIO_BCM
        select SPARSE_IRQ
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index 3a62f1b1cabc..f0f9abafad29 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -11,34 +11,19 @@
 * GNU General Public License for more details.
 */
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/time.h>
-static const struct of_device_id irq_match[] = {
-        {.compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {}
-};
 static void timer_init(void)
 {
 }
-static struct sys_timer timer = {
-        .init = timer_init,
-};
-static void __init init_irq(void)
-{
-        of_irq_init(irq_match);
-}
 static void __init board_init(void)
 {
@@ -49,9 +34,8 @@ static void __init board_init(void)
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
-        .init_irq = init_irq,
+        .init_irq = irqchip_init,
-        .timer = &timer,
+        .init_time = timer_init,
        .init_machine = board_init,
        .dt_compat = bcm11351_dt_compat,
-        .handle_irq = gic_handle_irq,
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index f0d739f4b7a3..6f5785985dd1 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -17,8 +17,8 @@
 #include <linux/irqchip/bcm2835.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
-#include <linux/bcm2835_timer.h>
 #include <linux/clk/bcm2835.h>
+#include <linux/clocksource.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -26,11 +26,13 @@
 #include <mach/bcm2835_soc.h>
 #define PM_RSTC                         0x1c
+#define PM_RSTS                         0x20
 #define PM_WDOG                         0x24
 #define PM_PASSWORD                     0x5a000000
 #define PM_RSTC_WRCFG_MASK              0x00000030
 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
+#define PM_RSTS_HADWRH_SET              0x00000040
 static void __iomem *wdt_regs;
@@ -67,6 +69,29 @@ static void bcm2835_restart(char mode, const char *cmd)
        mdelay(1);
 }
+/*
+ * We can't really power off, but if we do the normal reset scheme, and
+ * indicate to bootcode.bin not to reboot, then most of the chip will be
+ * powered off.
+ */
+static void bcm2835_power_off(void)
+{
+        u32 val;
+        /*
+         * We set the watchdog hard reset bit here to distinguish this reset
+         * from the normal (full) reset. bootcode.bin will not reboot after a
+         * hard reset.
+         */
+        val = readl_relaxed(wdt_regs + PM_RSTS);
+        val &= ~PM_RSTC_WRCFG_MASK;
+        val |= PM_PASSWORD | PM_RSTS_HADWRH_SET;
+        writel_relaxed(val, wdt_regs + PM_RSTS);
+        /* Continue with normal reset mechanism */
+        bcm2835_restart(0, "");
+}
 static struct map_desc io_map __initdata = {
        .virtual = BCM2835_PERIPH_VIRT,
        .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
@@ -84,6 +109,9 @@ static void __init bcm2835_init(void)
        int ret;
        bcm2835_setup_restart();
+        if (wdt_regs)
+                pm_power_off = bcm2835_power_off;
        bcm2835_init_clocks();
        ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
@@ -104,7 +132,7 @@ DT_MACHINE_START(BCM2835, "BCM2835")
        .init_irq = bcm2835_init_irq,
        .handle_irq = bcm2835_handle_irq,
        .init_machine = bcm2835_init,
-        .timer = &bcm2835_timer,
+        .init_time = clocksource_of_init,
        .restart = bcm2835_restart,
        .dt_compat = bcm2835_compat
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
index cc46dcc72377..bf86dca3bf71 100644
--- a/arch/arm/mach-bcm2835/include/mach/uncompress.h
+++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h
@@ -42,4 +42,3 @@ static inline void flush(void)
 }
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 3fbf43f72589..f38584709df7 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -170,7 +170,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .init_machine   = autcpu12_init,
        .init_late      = autcpu12_init_late,
        .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index 60900ddf97c9..baab7da33c9b 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -140,7 +140,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .init_machine   = cdb89712_init,
        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 0b32a487183b..014aa3c19a03 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -40,7 +40,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
        .fixup          = fixup_clep7312,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 71aa5cf2c0d3..5f928e9ed2ef 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -173,7 +173,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .reserve        = edb7211_reserve,
        .map_io         = edb7211_map_io,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .init_machine   = edb7211_init,
        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index 7d0125580366..c5675efc8c6a 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -78,7 +78,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
        .fixup          = fortunet_fixup,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 1518fc83babd..8d3ee6771135 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -224,7 +224,7 @@ MACHINE_START(P720T, "ARM-Prospector720T")
        .map_io         = p720t_map_io,
        .init_early     = p720t_init_early,
        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
+        .init_time      = clps711x_timer_init,
        .init_machine   = p720t_init,
        .init_late      = p720t_init_late,
        .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index e046439573ee..20ff50f3ccf0 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -282,7 +282,7 @@ static void add_fixed_clk(struct clk *clk, const char *name, int rate)
        clk_register_clkdev(clk, name, NULL);
 }
-static void __init clps711x_timer_init(void)
+void __init clps711x_timer_init(void)
 {
        int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
        u32 tmp;
@@ -345,10 +345,6 @@ static void __init clps711x_timer_init(void)
        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
-struct sys_timer clps711x_timer = {
-        .init           = clps711x_timer_init,
-};
 void clps711x_restart(char mode, const char *cmd)
 {
        soft_restart(0);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index b7c0c75c90c0..f84a7292c70e 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -8,10 +8,8 @@
 #define CLPS711X_NR_GPIO        (4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
-struct sys_timer;
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
+extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
-extern struct sys_timer clps711x_timer;
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 7b28d6a47690..5f02d06dc655 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -53,5 +53,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index ae305397003c..a71867e1d8d6 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -28,7 +28,6 @@
 #include <linux/usb/ohci_pdriver.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -250,8 +249,7 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
        .atag_offset    = 0x100,
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
-        .timer          = &cns3xxx_timer,
+        .init_time      = cns3xxx_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = cns3420_init,
        .restart        = cns3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 031805b1428d..e698f26cc0cb 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -12,10 +12,10 @@
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/cns3xxx.h>
 #include "core.h"
@@ -134,7 +134,6 @@ static int cns3xxx_timer_set_next_event(unsigned long evt,
 static struct clock_event_device cns3xxx_tmr1_clockevent = {
        .name           = "cns3xxx timer1",
-        .shift          = 8,
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_mode       = cns3xxx_timer_set_mode,
        .set_next_event = cns3xxx_timer_set_next_event,
@@ -145,15 +144,9 @@ static struct clock_event_device cns3xxx_tmr1_clockevent = {
 static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
 {
        cns3xxx_tmr1_clockevent.irq = timer_irq;
-        cns3xxx_tmr1_clockevent.mult =
+        clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
-                div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
+                                        (cns3xxx_cpu_clock() >> 3) * 1000000,
-                       cns3xxx_tmr1_clockevent.shift);
+                                        0xf, 0xffffffff);
-        cns3xxx_tmr1_clockevent.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
-        cns3xxx_tmr1_clockevent.min_delta_ns =
-                clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
-        clockevents_register_device(&cns3xxx_tmr1_clockevent);
 }
 /*
@@ -235,17 +228,13 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
        cns3xxx_clockevents_init(timer_irq);
 }
-static void __init cns3xxx_timer_init(void)
+void __init cns3xxx_timer_init(void)
 {
        cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
        __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
 }
-struct sys_timer cns3xxx_timer = {
-        .init = cns3xxx_timer_init,
-};
 #ifdef CONFIG_CACHE_L2X0
 void __init cns3xxx_l2x0_init(void)
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 4894b8c17151..b23b17b4da10 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,7 +11,7 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
-extern struct sys_timer cns3xxx_timer;
+extern void cns3xxx_timer_init(void);
 #ifdef CONFIG_CACHE_L2X0
 void __init cns3xxx_l2x0_init(void);
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
index a91b6058ab4f..7a030b99df84 100644
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -51,4 +51,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0153950f6068..a075b3e0c5c7 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -62,6 +62,7 @@ config MACH_DA8XX_DT
        bool "Support DA8XX platforms using device tree"
        default y
        depends on ARCH_DAVINCI_DA8XX
+        select PINCTRL
        help
          Say y here to include support for TI DaVinci DA850 based using
          Flattened Device Tree. More information at Documentation/devicetree
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 95b5e102ceb1..6da25eebf911 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -652,8 +652,13 @@ static __init void da830_evm_init(void)
        if (ret)
                pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
-        ret = da8xx_register_spi(0, da830evm_spi_info,
+        ret = spi_register_board_info(da830evm_spi_info,
-                                 ARRAY_SIZE(da830evm_spi_info));
+                                      ARRAY_SIZE(da830evm_spi_info));
+        if (ret)
+                pr_warn("%s: spi info registration failed: %d\n", __func__,
+                        ret);
+        ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
        if (ret)
                pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
                           ret);
@@ -679,7 +684,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
        .atag_offset    = 0x100,
        .map_io         = da830_evm_map_io,
        .init_irq       = cp_intc_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = da830_evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0299915575a8..c2dfe06563df 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -349,13 +349,13 @@ static inline void da850_evm_setup_nor_nand(void)
        if (!HAS_MMC) {
                ret = davinci_cfg_reg_list(da850_evm_nand_pins);
                if (ret)
-                        pr_warning("da850_evm_init: nand mux setup failed: "
+                        pr_warn("%s: NAND mux setup failed: %d\n",
-                                        "%d\n", ret);
+                                __func__, ret);
                ret = davinci_cfg_reg_list(da850_evm_nor_pins);
                if (ret)
-                        pr_warning("da850_evm_init: nor mux setup failed: %d\n",
+                        pr_warn("%s: NOR mux setup failed: %d\n",
-                                ret);
+                                __func__, ret);
                da850_evm_init_nor();
@@ -477,19 +477,19 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
        ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
        if (ret) {
-                pr_warning("Cannot open UI expander pin %d\n", sel_a);
+                pr_warn("Cannot open UI expander pin %d\n", sel_a);
                goto exp_setup_sela_fail;
        }
        ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
        if (ret) {
-                pr_warning("Cannot open UI expander pin %d\n", sel_b);
+                pr_warn("Cannot open UI expander pin %d\n", sel_b);
                goto exp_setup_selb_fail;
        }
        ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
        if (ret) {
-                pr_warning("Cannot open UI expander pin %d\n", sel_c);
+                pr_warn("Cannot open UI expander pin %d\n", sel_c);
                goto exp_setup_selc_fail;
        }
@@ -501,7 +501,7 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
        da850_evm_ui_keys_init(gpio);
        ret = platform_device_register(&da850_evm_ui_keys_device);
        if (ret) {
-                pr_warning("Could not register UI GPIO expander push-buttons");
+                pr_warn("Could not register UI GPIO expander push-buttons");
                goto exp_setup_keys_fail;
        }
@@ -690,14 +690,14 @@ static int da850_evm_bb_expander_setup(struct i2c_client *client,
        da850_evm_bb_keys_init(gpio);
        ret = platform_device_register(&da850_evm_bb_keys_device);
        if (ret) {
-                pr_warning("Could not register baseboard GPIO expander keys");
+                pr_warn("Could not register baseboard GPIO expander keys");
                goto io_exp_setup_sw_fail;
        }
        da850_evm_bb_leds_init(gpio);
        ret = platform_device_register(&da850_evm_bb_leds_device);
        if (ret) {
-                pr_warning("Could not register baseboard GPIO expander LEDS");
+                pr_warn("Could not register baseboard GPIO expander LEDs");
                goto io_exp_setup_leds_fail;
        }
@@ -1065,21 +1065,19 @@ static int __init da850_evm_config_emac(void)
        }
        if (ret)
-                pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
+                pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
-                                ret);
+                        __func__, ret);
        /* configure the CFGCHIP3 register for RMII or MII */
        __raw_writel(val, cfg_chip3_base);
        ret = davinci_cfg_reg(DA850_GPIO2_6);
        if (ret)
-                pr_warning("da850_evm_init:GPIO(2,6) mux setup "
+                pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
-                                                        "failed\n");
        ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
        if (ret) {
-                pr_warning("Cannot open GPIO %d\n",
+                pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN);
-                                        DA850_MII_MDIO_CLKEN_PIN);
                return ret;
        }
@@ -1090,8 +1088,7 @@ static int __init da850_evm_config_emac(void)
        ret = da8xx_register_emac();
        if (ret)
-                pr_warning("da850_evm_init: emac registration failed: %d\n",
+                pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-                                ret);
        return 0;
 }
@@ -1256,11 +1253,24 @@ static struct vpif_capture_config da850_vpif_capture_config = {
 };
 /* VPIF display configuration */
+static struct adv7343_platform_data adv7343_pdata = {
+        .mode_config = {
+                .dac_3 = 1,
+                .dac_2 = 1,
+                .dac_1 = 1,
+        },
+        .sd_config = {
+                .sd_dac_out1 = 1,
+        },
+};
 static struct vpif_subdev_info da850_vpif_subdev[] = {
        {
                .name = "adv7343",
                .board_info = {
                        I2C_BOARD_INFO("adv7343", 0x2a),
+                        .platform_data = &adv7343_pdata,
                },
        },
 };
@@ -1443,57 +1453,53 @@ static __init void da850_evm_init(void)
        ret = pmic_tps65070_init();
        if (ret)
-                pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
+                pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
-                                ret);
        ret = da850_register_edma(da850_edma_rsv);
        if (ret)
-                pr_warning("da850_evm_init: edma registration failed: %d\n",
+                pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-                                ret);
        ret = davinci_cfg_reg_list(da850_i2c0_pins);
        if (ret)
-                pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
+                pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
        if (ret)
-                pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
+                pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_watchdog();
        if (ret)
-                pr_warning("da830_evm_init: watchdog registration failed: %d\n",
+                pr_warn("%s: watchdog registration failed: %d\n",
-                                ret);
+                        __func__, ret);
        if (HAS_MMC) {
                ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
                if (ret)
-                        pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
+                        pr_warn("%s: MMCSD0 mux setup failed: %d\n",
-                                        " %d\n", ret);
+                                __func__, ret);
                ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
                if (ret)
-                        pr_warning("da850_evm_init: can not open GPIO %d\n",
+                        pr_warn("%s: can not open GPIO %d\n",
-                                        DA850_MMCSD_CD_PIN);
+                                __func__, DA850_MMCSD_CD_PIN);
                gpio_direction_input(DA850_MMCSD_CD_PIN);
                ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
                if (ret)
-                        pr_warning("da850_evm_init: can not open GPIO %d\n",
+                        pr_warn("%s: can not open GPIO %d\n",
-                                        DA850_MMCSD_WP_PIN);
+                                __func__, DA850_MMCSD_WP_PIN);
                gpio_direction_input(DA850_MMCSD_WP_PIN);
                ret = da8xx_register_mmcsd0(&da850_mmc_config);
                if (ret)
-                        pr_warning("da850_evm_init: mmcsd0 registration failed:"
+                        pr_warn("%s: MMCSD0 registration failed: %d\n",
-                                        " %d\n", ret);
+                                __func__, ret);
                ret = da850_wl12xx_init();
                if (ret)
-                        pr_warning("da850_evm_init: wl12xx initialization"
+                        pr_warn("%s: WL12xx initialization failed: %d\n",
-                                   " failed: %d\n", ret);
+                                __func__, ret);
        }
        davinci_serial_init(&da850_evm_uart_config);
@@ -1511,16 +1517,14 @@ static __init void da850_evm_init(void)
        ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
        if (ret)
-                pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
+                pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
-                                ret);
        da850_evm_snd_data.sram_pool = sram_get_gen_pool();
        da8xx_register_mcasp(0, &da850_evm_snd_data);
        ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
        if (ret)
-                pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
+                pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_uio_pruss();
        if (ret)
@@ -1530,51 +1534,49 @@ static __init void da850_evm_init(void)
        /* Handle board specific muxing for LCD here */
        ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
        if (ret)
-                pr_warning("da850_evm_init: evm specific lcd mux setup "
+                pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
-                                "failed: %d\n", ret);
+                        __func__, ret);
        ret = da850_lcd_hw_init();
        if (ret)
-                pr_warning("da850_evm_init: lcd initialization failed: %d\n",
+                pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
-                                ret);
        sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
        ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
        if (ret)
-                pr_warning("da850_evm_init: lcdc registration failed: %d\n",
+                pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_rtc();
        if (ret)
-                pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
+                pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
        ret = da850_evm_init_cpufreq();
        if (ret)
-                pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
+                pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_cpuidle();
        if (ret)
-                pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
+                pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
-                                ret);
        ret = da850_register_pm(&da850_pm_device);
        if (ret)
-                pr_warning("da850_evm_init: suspend registration failed: %d\n",
+                pr_warn("%s: suspend registration failed: %d\n", __func__, ret);
-                                ret);
        da850_vpif_init();
-        ret = da8xx_register_spi(1, da850evm_spi_info,
+        ret = spi_register_board_info(da850evm_spi_info,
-                                 ARRAY_SIZE(da850evm_spi_info));
+                                      ARRAY_SIZE(da850evm_spi_info));
        if (ret)
-                pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
+                pr_warn("%s: spi info registration failed: %d\n", __func__,
-                                ret);
+                        ret);
+        ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
+        if (ret)
+                pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
        ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
        if (ret)
-                pr_warning("da850_evm_init: sata registration failed: %d\n",
+                pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
-                                ret);
        da850_evm_setup_mac_addr();
 }
@@ -1599,7 +1601,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
        .atag_offset    = 0x100,
        .map_io         = da850_evm_map_io,
        .init_irq       = cp_intc_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = da850_evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index cdf8d0746e79..147b8e1a4407 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -355,7 +355,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
        .atag_offset  = 0x100,
        .map_io       = dm355_evm_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = dm355_evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index d41954507fc2..dff4ddc5ef81 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -274,7 +274,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
        .atag_offset  = 0x100,
        .map_io       = dm355_leopard_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = dm355_leopard_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 5d49c75388ca..c2d4958a0cb6 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -616,7 +616,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
        .atag_offset    = 0x100,
        .map_io         = dm365_evm_map_io,
        .init_irq       = davinci_irq_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = dm365_evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index f5e018de7fa5..71735e7797cc 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -690,7 +690,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = {
                        .std            = VENC_STD_ALL,
                        .capabilities   = V4L2_OUT_CAP_STD,
                },
-                .subdev_name    = VPBE_VENC_SUBDEV_NAME,
+                .subdev_name    = DM644X_VPBE_VENC_SUBDEV_NAME,
                .default_mode   = "ntsc",
                .num_modes      = ARRAY_SIZE(dm644xevm_enc_std_timing),
                .modes          = dm644xevm_enc_std_timing,
@@ -702,7 +702,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = {
                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
                        .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
                },
-                .subdev_name    = VPBE_VENC_SUBDEV_NAME,
+                .subdev_name    = DM644X_VPBE_VENC_SUBDEV_NAME,
                .default_mode   = "480p59_94",
                .num_modes      = ARRAY_SIZE(dm644xevm_enc_preset_timing),
                .modes          = dm644xevm_enc_preset_timing,
@@ -713,10 +713,10 @@ static struct vpbe_config dm644xevm_display_cfg = {
        .module_name    = "dm644x-vpbe-display",
        .i2c_adapter_id = 1,
        .osd            = {
-                .module_name    = VPBE_OSD_SUBDEV_NAME,
+                .module_name    = DM644X_VPBE_OSD_SUBDEV_NAME,
        },
        .venc           = {
-                .module_name    = VPBE_VENC_SUBDEV_NAME,
+                .module_name    = DM644X_VPBE_VENC_SUBDEV_NAME,
        },
        .num_outputs    = ARRAY_SIZE(dm644xevm_vpbe_outputs),
        .outputs        = dm644xevm_vpbe_outputs,
@@ -825,7 +825,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
        .atag_offset  = 0x100,
        .map_io       = davinci_evm_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = davinci_evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6e2f1631df5b..de7adff324dc 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -818,7 +818,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
        .atag_offset  = 0x100,
        .map_io       = davinci_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
@@ -829,7 +829,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
        .atag_offset  = 0x100,
        .map_io       = davinci_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = evm_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 43e4a0d663fa..9549d53aa63f 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -529,8 +529,13 @@ static void __init mityomapl138_init(void)
        mityomapl138_setup_nand();
-        ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
+        ret = spi_register_board_info(mityomapl138_spi_flash_info,
-                               ARRAY_SIZE(mityomapl138_spi_flash_info));
+                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
+        if (ret)
+                pr_warn("spi info registration failed: %d\n", ret);
+        ret = da8xx_register_spi_bus(1,
+                                     ARRAY_SIZE(mityomapl138_spi_flash_info));
        if (ret)
                pr_warning("spi 1 registration failed: %d\n", ret);
@@ -570,7 +575,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
        .atag_offset    = 0x100,
        .map_io         = mityomapl138_map_io,
        .init_irq       = cp_intc_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = mityomapl138_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 3e3e3afebf88..1c98107527fa 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -237,7 +237,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
        .atag_offset    = 0x100,
        .map_io          = davinci_ntosd2_map_io,
        .init_irq       = davinci_irq_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = davinci_ntosd2_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index dc1208e9e664..5a2bd44da54d 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -48,8 +48,7 @@ static __init void omapl138_hawk_config_emac(void)
        val &= ~BIT(8);
        ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
        if (ret) {
-                pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
+                pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret);
-                        __func__, ret);
                return;
        }
@@ -61,8 +60,7 @@ static __init void omapl138_hawk_config_emac(void)
        ret = da8xx_register_emac();
        if (ret)
-                pr_warning("%s: emac registration failed: %d\n",
+                pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-                        __func__, ret);
 }
 /*
@@ -147,15 +145,14 @@ static __init void omapl138_hawk_mmc_init(void)
        ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
        if (ret) {
-                pr_warning("%s: MMC/SD0 mux setup failed: %d\n",
+                pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret);
-                        __func__, ret);
                return;
        }
        ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
                        GPIOF_DIR_IN, "MMC CD");
        if (ret < 0) {
-                pr_warning("%s: can not open GPIO %d\n",
+                pr_warn("%s: can not open GPIO %d\n",
                        __func__, DA850_HAWK_MMCSD_CD_PIN);
                return;
        }
@@ -163,15 +160,14 @@ static __init void omapl138_hawk_mmc_init(void)
        ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
                        GPIOF_DIR_IN, "MMC WP");
        if (ret < 0) {
-                pr_warning("%s: can not open GPIO %d\n",
+                pr_warn("%s: can not open GPIO %d\n",
                        __func__, DA850_HAWK_MMCSD_WP_PIN);
                goto mmc_setup_wp_fail;
        }
        ret = da8xx_register_mmcsd0(&da850_mmc_config);
        if (ret) {
-                pr_warning("%s: MMC/SD0 registration failed: %d\n",
+                pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret);
-                        __func__, ret);
                goto mmc_setup_mmcsd_fail;
        }
@@ -250,8 +246,7 @@ static __init void omapl138_hawk_usb_init(void)
        ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
        if (ret) {
-                pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
+                pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
-                        __func__, ret);
                return;
        }
@@ -280,8 +275,7 @@ static __init void omapl138_hawk_usb_init(void)
        ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
        if (ret) {
-                pr_warning("%s: USB 1.1 registration failed: %d\n",
+                pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-                        __func__, ret);
                goto usb11_setup_fail;
        }
@@ -307,8 +301,7 @@ static __init void omapl138_hawk_init(void)
        ret = da850_register_edma(da850_edma_rsv);
        if (ret)
-                pr_warning("%s: EDMA registration failed: %d\n",
+                pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-                        __func__, ret);
        omapl138_hawk_mmc_init();
@@ -316,9 +309,8 @@ static __init void omapl138_hawk_init(void)
        ret = da8xx_register_watchdog();
        if (ret)
-                pr_warning("omapl138_hawk_init: "
+                pr_warn("%s: watchdog registration failed: %d\n",
-                        "watchdog registration failed: %d\n",
+                        __func__, ret);
-                        ret);
 }
 #ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -341,7 +333,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
        .atag_offset    = 0x100,
        .map_io         = omapl138_hawk_map_io,
        .init_irq       = cp_intc_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = omapl138_hawk_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 6957787fa7f3..739be7e738fe 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -155,7 +155,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
        .atag_offset  = 0x100,
        .map_io       = davinci_sffsdr_map_io,
        .init_irq     = davinci_irq_init,
-        .timer        = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine = davinci_sffsdr_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index be3099733b1f..4f416023d4e2 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -280,7 +280,7 @@ MACHINE_START(TNETV107X, "TNETV107X EVM")
        .atag_offset    = 0x100,
        .map_io         = tnetv107x_init,
        .init_irq       = cp_intc_init,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = tnetv107x_evm_board_init,
        .init_late      = davinci_init_late,
        .dma_zone_size  = SZ_128M,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 34668ead53c7..d458558ee84a 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -52,6 +52,40 @@ static void __clk_disable(struct clk *clk)
                __clk_disable(clk->parent);
 }
+int davinci_clk_reset(struct clk *clk, bool reset)
+{
+        unsigned long flags;
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->flags & CLK_PSC)
+                davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(davinci_clk_reset);
+int davinci_clk_reset_assert(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->reset)
+                return -EINVAL;
+        return clk->reset(clk, true);
+}
+EXPORT_SYMBOL(davinci_clk_reset_assert);
+int davinci_clk_reset_deassert(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->reset)
+                return -EINVAL;
+        return clk->reset(clk, false);
+}
+EXPORT_SYMBOL(davinci_clk_reset_deassert);
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
@@ -535,7 +569,7 @@ int davinci_set_refclk_rate(unsigned long rate)
 }
 int __init davinci_clk_init(struct clk_lookup *clocks)
-  {
+{
        struct clk_lookup *c;
        struct clk *clk;
        size_t num_clocks = 0;
@@ -576,6 +610,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
                if (clk->lpsc)
                        clk->flags |= CLK_PSC;
+                if (clk->flags & PSC_LRST)
+                        clk->reset = davinci_clk_reset;
                clk_register(clk);
                num_clocks++;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 46f0f1bf1a4c..8694b395fc92 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -103,6 +103,7 @@ struct clk {
        unsigned long (*recalc) (struct clk *);
        int (*set_rate) (struct clk *clk, unsigned long rate);
        int (*round_rate) (struct clk *clk, unsigned long rate);
+        int (*reset) (struct clk *clk, bool reset);
 };
 /* Clock flags: SoC-specific flags start at BIT(16) */
@@ -112,6 +113,7 @@ struct clk {
 #define PRE_PLL                 BIT(4) /* source is before PLL mult/div */
 #define PSC_SWRSTDISABLE        BIT(5) /* Disable state is SwRstDisable */
 #define PSC_FORCE               BIT(6) /* Force module state transtition */
+#define PSC_LRST                BIT(8) /* Use local reset on enable/disable */
 #define CLK(dev, con, ck)       \
        {                       \
@@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
 int davinci_set_refclk_rate(unsigned long rate);
 int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
+int davinci_clk_reset(struct clk *clk, bool reset);
 extern struct platform_device davinci_wdt_device;
 extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 9107691adbdb..5ac9e9384b15 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -25,35 +25,44 @@
 #define DAVINCI_CPUIDLE_MAX_STATES      2
-struct davinci_ops {
+static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
-        void (*enter) (u32 flags);
+static void __iomem *ddr2_reg_base;
-        void (*exit) (u32 flags);
+static bool ddr2_pdown;
-        u32 flags;
-};
+static void davinci_save_ddr_power(int enter, bool pdown)
+{
+        u32 val;
+        val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
+        if (enter) {
+                if (pdown)
+                        val |= DDR2_SRPD_BIT;
+                else
+                        val &= ~DDR2_SRPD_BIT;
+                val |= DDR2_LPMODEN_BIT;
+        } else {
+                val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
+        }
+        __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
+}
 /* Actual code that puts the SoC in different idle states */
 static int davinci_enter_idle(struct cpuidle_device *dev,
                                struct cpuidle_driver *drv,
                                                int index)
 {
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
+        davinci_save_ddr_power(1, ddr2_pdown);
-        struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
-        if (ops && ops->enter)
-                ops->enter(ops->flags);
        index = cpuidle_wrap_enter(dev, drv, index,
                                arm_cpuidle_simple_enter);
-        if (ops && ops->exit)
+        davinci_save_ddr_power(0, ddr2_pdown);
-                ops->exit(ops->flags);
        return index;
 }
-/* fields in davinci_ops.flags */
-#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
 static struct cpuidle_driver davinci_idle_driver = {
        .name                   = "cpuidle-davinci",
        .owner                  = THIS_MODULE,
@@ -70,45 +79,6 @@ static struct cpuidle_driver davinci_idle_driver = {
        .state_count = DAVINCI_CPUIDLE_MAX_STATES,
 };
-static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
-static void __iomem *ddr2_reg_base;
-static void davinci_save_ddr_power(int enter, bool pdown)
-{
-        u32 val;
-        val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
-        if (enter) {
-                if (pdown)
-                        val |= DDR2_SRPD_BIT;
-                else
-                        val &= ~DDR2_SRPD_BIT;
-                val |= DDR2_LPMODEN_BIT;
-        } else {
-                val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
-        }
-        __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
-}
-static void davinci_c2state_enter(u32 flags)
-{
-        davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
-}
-static void davinci_c2state_exit(u32 flags)
-{
-        davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
-}
-static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
-        [1] = {
-                .enter  = davinci_c2state_enter,
-                .exit   = davinci_c2state_exit,
-        },
-};
 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 {
        int ret;
@@ -124,11 +94,7 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
        ddr2_reg_base = pdata->ddr2_ctlr_base;
-        if (pdata->ddr2_pdown)
+        ddr2_pdown = pdata->ddr2_pdown;
-                davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
-        cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
-        device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
        ret = cpuidle_register_driver(&davinci_idle_driver);
        if (ret) {
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 6b9154e9f908..0c4a26ddebba 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -76,6 +76,13 @@ static struct clk pll0_aux_clk = {
        .flags          = CLK_PLL | PRE_PLL,
 };
+static struct clk pll0_sysclk1 = {
+        .name           = "pll0_sysclk1",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV1,
+};
 static struct clk pll0_sysclk2 = {
        .name           = "pll0_sysclk2",
        .parent         = &pll0_clk,
@@ -368,10 +375,19 @@ static struct clk sata_clk = {
        .flags          = PSC_FORCE,
 };
+static struct clk dsp_clk = {
+        .name           = "dsp",
+        .parent         = &pll0_sysclk1,
+        .domain         = DAVINCI_GPSC_DSPDOMAIN,
+        .lpsc           = DA8XX_LPSC0_GEM,
+        .flags          = PSC_LRST | PSC_FORCE,
+};
 static struct clk_lookup da850_clks[] = {
        CLK(NULL,               "ref",          &ref_clk),
        CLK(NULL,               "pll0",         &pll0_clk),
        CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
+        CLK(NULL,               "pll0_sysclk1", &pll0_sysclk1),
        CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
        CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
        CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
@@ -413,6 +429,7 @@ static struct clk_lookup da850_clks[] = {
        CLK("spi_davinci.1",    NULL,           &spi1_clk),
        CLK("vpif",             NULL,           &vpif_clk),
        CLK("ahci",             NULL,           &sata_clk),
+        CLK("davinci-rproc.0",  NULL,           &dsp_clk),
        CLK(NULL,               NULL,           NULL),
 };
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 37c27af18fa0..6b7a0a27fbd1 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -37,11 +37,18 @@ static void __init da8xx_init_irq(void)
        of_irq_init(da8xx_irq_match);
 }
+struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
+        OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
+        {}
+};
 #ifdef CONFIG_ARCH_DAVINCI_DA850
 static void __init da850_init_machine(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             da850_auxdata_lookup, NULL);
        da8xx_uart_clk_enable();
 }
@@ -56,7 +63,7 @@ static const char *da850_boards_compat[] __initdata = {
 DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
        .map_io         = da850_init,
        .init_irq       = da8xx_init_irq,
-        .timer          = &davinci_timer,
+        .init_time      = davinci_timer_init,
        .init_machine   = da850_init_machine,
        .dt_compat      = da850_boards_compat,
        .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 2d5502d84a22..fc50243b1481 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -359,7 +359,7 @@ static struct resource da8xx_watchdog_resources[] = {
        },
 };
-struct platform_device da8xx_wdt_device = {
+static struct platform_device da8xx_wdt_device = {
        .name           = "watchdog",
        .id             = -1,
        .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
@@ -368,7 +368,15 @@ struct platform_device da8xx_wdt_device = {
 void da8xx_restart(char mode, const char *cmd)
 {
-        davinci_watchdog_reset(&da8xx_wdt_device);
+        struct device *dev;
+        dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
+        if (!dev) {
+                pr_err("%s: failed to find watchdog device\n", __func__);
+                return;
+        }
+        davinci_watchdog_reset(to_platform_device(dev));
 }
 int __init da8xx_register_watchdog(void)
@@ -751,7 +759,7 @@ void __iomem * __init da8xx_get_mem_ctlr(void)
        da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
        if (!da8xx_ddr2_ctlr_base)
-                pr_warning("%s: Unable to map DDR2 controller", __func__);
+                pr_warn("%s: Unable to map DDR2 controller", __func__);
        return da8xx_ddr2_ctlr_base;
 }
@@ -832,7 +840,7 @@ static struct resource da8xx_spi1_resources[] = {
        },
 };
-struct davinci_spi_platform_data da8xx_spi_pdata[] = {
+static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
        [0] = {
                .version        = SPI_VERSION_2,
                .intr_line      = 1,
@@ -866,20 +874,12 @@ static struct platform_device da8xx_spi_device[] = {
        },
 };
-int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
+int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
-                              unsigned len)
 {
-        int ret;
        if (instance < 0 || instance > 1)
                return -EINVAL;
-        ret = spi_register_board_info(info, len);
+        da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
-        if (ret)
-                pr_warning("%s: failed to register board info for spi %d :"
-                           " %d\n", __func__, instance, ret);
-        da8xx_spi_pdata[instance].num_chipselect = len;
        if (instance == 1 && cpu_is_davinci_da850()) {
                da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 11c79a3362ef..db1dd92e00af 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -669,19 +669,14 @@ static struct resource dm644x_osd_resources[] = {
        },
 };
-static struct osd_platform_data dm644x_osd_data = {
-        .vpbe_type     = VPBE_VERSION_1,
-};
 static struct platform_device dm644x_osd_dev = {
-        .name           = VPBE_OSD_SUBDEV_NAME,
+        .name           = DM644X_VPBE_OSD_SUBDEV_NAME,
        .id             = -1,
        .num_resources  = ARRAY_SIZE(dm644x_osd_resources),
        .resource       = dm644x_osd_resources,
        .dev            = {
                .dma_mask               = &dm644x_video_dma_mask,
                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &dm644x_osd_data,
        },
 };
@@ -751,12 +746,11 @@ static struct platform_device dm644x_vpbe_display = {
 };
 static struct venc_platform_data dm644x_venc_pdata = {
-        .venc_type      = VPBE_VERSION_1,
        .setup_clock    = dm644x_venc_setup_clock,
 };
 static struct platform_device dm644x_venc_dev = {
-        .name           = VPBE_VENC_SUBDEV_NAME,
+        .name           = DM644X_VPBE_VENC_SUBDEV_NAME,
        .id             = -1,
        .num_resources  = ARRAY_SIZE(dm644x_venc_resources),
        .resource       = dm644x_venc_resources,
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index a3b040219876..3e8af6a0b64c 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -18,4 +18,7 @@ struct clk;
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
+int davinci_clk_reset_assert(struct clk *c);
+int davinci_clk_reset_deassert(struct clk *c);
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 046c7238a3d6..b124b77c90c5 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -15,9 +15,7 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
-struct sys_timer;
+extern void davinci_timer_init(void);
-extern struct sys_timer davinci_timer;
 extern void davinci_irq_init(void);
 extern void __iomem *davinci_intc_base;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 700d311c6854..de439b7b9af1 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -82,8 +82,7 @@ void __init da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
-int da8xx_register_spi(int instance,
+int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
-                const struct spi_board_info *info, unsigned len);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
@@ -110,9 +109,7 @@ extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
-extern struct davinci_spi_platform_data da8xx_spi_pdata[];
-extern struct platform_device da8xx_wdt_device;
 extern const short da830_emif25_pins[];
 extern const short da830_spi0_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 40a0027838e8..0a22710493fd 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -246,6 +246,7 @@
 #define MDSTAT_STATE_MASK       0x3f
 #define PDSTAT_STATE_MASK       0x1f
+#define MDCTL_LRST              BIT(8)
 #define MDCTL_FORCE             BIT(31)
 #define PDCTL_NEXT              BIT(0)
 #define PDCTL_EPCGOOD           BIT(8)
@@ -253,6 +254,8 @@
 #ifndef __ASSEMBLER__
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
+extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
+                bool reset);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                unsigned int id, bool enable, u32 flags);
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 3a0ff905a69b..f49c2916aa3a 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -101,4 +101,3 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 }
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index d7e210f4b55c..82fdc69d5728 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -35,7 +35,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
-                pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
+                pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
                                (int)soc_info->psc_bases, ctlr);
                return 0;
        }
@@ -48,6 +48,31 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
        return mdstat & BIT(12);
 }
+/* Control "reset" line associated with PSC domain */
+void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset)
+{
+        u32 mdctl;
+        void __iomem *psc_base;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
+                pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
+                                (int)soc_info->psc_bases, ctlr);
+                return;
+        }
+        psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
+        mdctl = readl(psc_base + MDCTL + 4 * id);
+        if (reset)
+                mdctl &= ~MDCTL_LRST;
+        else
+                mdctl |= MDCTL_LRST;
+        writel(mdctl, psc_base + MDCTL + 4 * id);
+        iounmap(psc_base);
+}
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                unsigned int id, bool enable, u32 flags)
@@ -58,7 +83,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
        u32 next_state = PSC_STATE_ENABLE;
        if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
-                pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
+                pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
                                (int)soc_info->psc_bases, ctlr);
                return;
        }
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9847938785ca..bad361ec1666 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -337,7 +337,7 @@ static struct clock_event_device clockevent_davinci = {
 };
-static void __init davinci_timer_init(void)
+void __init davinci_timer_init(void)
 {
        struct clk *timer_clk;
        struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -410,11 +410,6 @@ static void __init davinci_timer_init(void)
                timer32_config(&timers[i]);
 }
-struct sys_timer davinci_timer = {
-        .init   = davinci_timer_init,
-};
 /* reset board using watchdog timer */
 void davinci_watchdog_reset(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 603c5fd99e8a..36469d813951 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -2,8 +2,12 @@ if ARCH_DOVE
 menu "Marvell Dove Implementations"
+config DOVE_LEGACY
+        bool
 config MACH_DOVE_DB
        bool "Marvell DB-MV88AP510 Development Board"
+        select DOVE_LEGACY
        select I2C_BOARDINFO
        help
          Say 'Y' here if you want your kernel to support the
@@ -11,6 +15,7 @@ config MACH_DOVE_DB
 config MACH_CM_A510
        bool "CompuLab CM-A510 Board"
+        select DOVE_LEGACY
        help
          Say 'Y' here if you want your kernel to support the
          CompuLab CM-A510 Board.
@@ -19,6 +24,8 @@ config MACH_DOVE_DT
        bool "Marvell Dove Flattened Device Tree"
        select MVEBU_CLK_CORE
        select MVEBU_CLK_GATING
+        select REGULATOR
+        select REGULATOR_FIXED_VOLTAGE
        select USE_OF
        help
          Say 'Y' here if you want your kernel to support the
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 5e683baf96cf..3f0a858fb597 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,6 @@
-obj-y                           += common.o addr-map.o irq.o mpp.o
+obj-y                           += common.o addr-map.o irq.o
+obj-$(CONFIG_DOVE_LEGACY)       += mpp.o
 obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
+obj-$(CONFIG_MACH_DOVE_DT)      += board-dt.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
new file mode 100644
index 000000000000..fbde1dd67113
--- /dev/null
+++ b/arch/arm/mach-dove/board-dt.c
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-dove/board-dt.c
+ *
+ * Marvell Dove 88AP510 System On Chip FDT Board
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/mvebu.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_data/usb-ehci-orion.h>
+#include <asm/hardware/cache-tauros2.h>
+#include <asm/mach/arch.h>
+#include <mach/pm.h>
+#include <plat/common.h>
+#include <plat/irq.h>
+#include "common.h"
+/*
+ * There are still devices that doesn't even know about DT,
+ * get clock gates here and add a clock lookup.
+ */
+static void __init dove_legacy_clk_init(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                         "marvell,dove-gating-clock");
+        struct of_phandle_args clkspec;
+        clkspec.np = np;
+        clkspec.args_count = 1;
+        clkspec.args[0] = CLOCK_GATING_BIT_GBE;
+        orion_clkdev_add(NULL, "mv643xx_eth_port.0",
+                         of_clk_get_from_provider(&clkspec));
+        clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
+        orion_clkdev_add("0", "pcie",
+                         of_clk_get_from_provider(&clkspec));
+        clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
+        orion_clkdev_add("1", "pcie",
+                         of_clk_get_from_provider(&clkspec));
+}
+static void __init dove_of_clk_init(void)
+{
+        mvebu_clocks_init();
+        dove_legacy_clk_init();
+}
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+static void __init dove_dt_init(void)
+{
+        pr_info("Dove 88AP510 SoC\n");
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init(0);
+#endif
+        dove_setup_cpu_mbus();
+        /* Setup root of clk tree */
+        dove_of_clk_init();
+        /* Internal devices not ported to DT yet */
+        dove_ge00_init(&dove_dt_ge00_data);
+        dove_pcie_init(1, 1);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char * const dove_dt_board_compat[] = {
+        "marvell,dove",
+        NULL
+};
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .init_time      = dove_timer_init,
+        .init_machine   = dove_dt_init,
+        .restart        = dove_restart,
+        .dt_compat      = dove_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 792b4e2e24f1..0dc39cf30fdd 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -92,6 +92,6 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
        .map_io         = dove_map_io,
        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
-        .timer          = &dove_timer,
+        .init_time      = dove_timer_init,
        .restart        = dove_restart,
 MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 89f4f993cd03..c6b3b2bb50e7 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -8,35 +8,24 @@
 * warranty of any kind, whether express or implied.
 */
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
 #include <linux/clk-provider.h>
 #include <linux/clk/mvebu.h>
-#include <linux/ata_platform.h>
+#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
+#include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
-#include <asm/page.h>
+#include <linux/platform_data/dma-mv_xor.h>
-#include <asm/setup.h>
+#include <linux/platform_data/usb-ehci-orion.h>
-#include <asm/timex.h>
+#include <linux/platform_device.h>
 #include <asm/hardware/cache-tauros2.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/pci.h>
-#include <mach/dove.h>
-#include <mach/pm.h>
 #include <mach/bridge-regs.h>
-#include <asm/mach/arch.h>
+#include <mach/pm.h>
-#include <linux/irq.h>
-#include <plat/time.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <linux/platform_data/dma-mv_xor.h>
-#include <plat/irq.h>
 #include <plat/common.h>
-#include <plat/addr-map.h>
+#include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 /*****************************************************************************
@@ -242,17 +231,13 @@ static int __init dove_find_tclk(void)
        return 166666667;
 }
-static void __init dove_timer_init(void)
+void __init dove_timer_init(void)
 {
        dove_tclk = dove_find_tclk();
        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
                        IRQ_DOVE_BRIDGE, dove_tclk);
 }
-struct sys_timer dove_timer = {
-        .init = dove_timer_init,
-};
 /*****************************************************************************
 * Cryptographic Engines and Security Accelerator (CESA)
 ****************************************************************************/
@@ -375,88 +360,3 @@ void dove_restart(char mode, const char *cmd)
        while (1)
                ;
 }
-#if defined(CONFIG_MACH_DOVE_DT)
-/*
- * There are still devices that doesn't even know about DT,
- * get clock gates here and add a clock lookup.
- */
-static void __init dove_legacy_clk_init(void)
-{
-        struct device_node *np = of_find_compatible_node(NULL, NULL,
-                                         "marvell,dove-gating-clock");
-        struct of_phandle_args clkspec;
-        clkspec.np = np;
-        clkspec.args_count = 1;
-        clkspec.args[0] = CLOCK_GATING_BIT_USB0;
-        orion_clkdev_add(NULL, "orion-ehci.0",
-                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CLOCK_GATING_BIT_USB1;
-        orion_clkdev_add(NULL, "orion-ehci.1",
-                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CLOCK_GATING_BIT_GBE;
-        orion_clkdev_add(NULL, "mv643xx_eth_port.0",
-                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
-        orion_clkdev_add("0", "pcie",
-                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
-        orion_clkdev_add("1", "pcie",
-                         of_clk_get_from_provider(&clkspec));
-}
-static void __init dove_of_clk_init(void)
-{
-        mvebu_clocks_init();
-        dove_legacy_clk_init();
-}
-static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
-        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
-};
-static void __init dove_dt_init(void)
-{
-        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
-                (dove_tclk + 499999) / 1000000);
-#ifdef CONFIG_CACHE_TAUROS2
-        tauros2_init(0);
-#endif
-        dove_setup_cpu_mbus();
-        /* Setup root of clk tree */
-        dove_of_clk_init();
-        /* Internal devices not ported to DT yet */
-        dove_rtc_init();
-        dove_ge00_init(&dove_dt_ge00_data);
-        dove_ehci0_init();
-        dove_ehci1_init();
-        dove_pcie_init(1, 1);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char * const dove_dt_board_compat[] = {
-        "marvell,dove",
-        NULL
-};
-DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
-        .map_io         = dove_map_io,
-        .init_early     = dove_init_early,
-        .init_irq       = orion_dt_init_irq,
-        .timer          = &dove_timer,
-        .init_machine   = dove_dt_init,
-        .restart        = dove_restart,
-        .dt_compat      = dove_dt_board_compat,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 1a233404b735..ee59fba4c6d1 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -14,7 +14,7 @@
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
-extern struct sys_timer dove_timer;
+extern void dove_timer_init(void);
 /*
 * Basic Dove init functions used early by machine-setup.
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index bc2867f11346..76e26f949c27 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -98,6 +98,6 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
        .map_io         = dove_map_io,
        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
-        .timer          = &dove_timer,
+        .init_time      = dove_timer_init,
        .restart        = dove_restart,
 MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
index 2c5cdd7a3eed..5c8ae9b9d39a 100644
--- a/arch/arm/mach-dove/include/mach/uncompress.h
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -34,4 +34,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index f0fe6b5350e2..b13cc74114db 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -158,7 +158,7 @@ static void __init ebsa110_init_early(void)
 * interrupt, then the PIT counter will roll over (ie, be negative).
 * This actually works out to be convenient.
 */
-static unsigned long ebsa110_gettimeoffset(void)
+static u32 ebsa110_gettimeoffset(void)
 {
        unsigned long offset, count;
@@ -181,7 +181,7 @@ static unsigned long ebsa110_gettimeoffset(void)
         */
        offset = offset * (1000000 / HZ) / COUNT;
-        return offset;
+        return offset * 1000;
 }
 static irqreturn_t
@@ -213,8 +213,10 @@ static struct irqaction ebsa110_timer_irq = {
 /*
 * Set up timer interrupt.
 */
-static void __init ebsa110_timer_init(void)
+void __init ebsa110_timer_init(void)
 {
+        arch_gettimeoffset = ebsa110_gettimeoffset;
        /*
         * Timer 1, mode 2, LSB/MSB
         */
@@ -225,11 +227,6 @@ static void __init ebsa110_timer_init(void)
        setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq);
 }
-static struct sys_timer ebsa110_timer = {
-        .init           = ebsa110_timer_init,
-        .offset         = ebsa110_gettimeoffset,
-};
 static struct plat_serial8250_port serial_platform_data[] = {
        {
                .iobase         = 0x3f8,
@@ -328,6 +325,6 @@ MACHINE_START(EBSA110, "EBSA110")
        .map_io         = ebsa110_map_io,
        .init_early     = ebsa110_init_early,
        .init_irq       = ebsa110_init_irq,
-        .timer          = &ebsa110_timer,
+        .init_time      = ebsa110_timer_init,
        .restart        = ebsa110_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ebsa110/include/mach/uncompress.h b/arch/arm/mach-ebsa110/include/mach/uncompress.h
index 32041509fbf8..ab64bea69c72 100644
--- a/arch/arm/mach-ebsa110/include/mach/uncompress.h
+++ b/arch/arm/mach-ebsa110/include/mach/uncompress.h
@@ -42,4 +42,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 41383bf03d4b..bda6c3a5c923 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -17,7 +17,6 @@
 #include <mach/hardware.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,8 +38,7 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = adssphere_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e85bf17f2d2a..c49ed3dc1aea 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -34,6 +34,7 @@
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/export.h>
+#include <linux/irqchip/arm-vic.h>
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -44,8 +45,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/vic.h>
 #include "soc.h"
 /*************************************************************************
@@ -140,11 +139,29 @@ static struct irqaction ep93xx_timer_irq = {
        .handler        = ep93xx_timer_interrupt,
 };
-static void __init ep93xx_timer_init(void)
+static u32 ep93xx_gettimeoffset(void)
+{
+        int offset;
+        offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
+        /*
+         * Timer 4 is based on a 983.04 kHz reference clock,
+         * so dividing by 983040 gives the fraction of a second,
+         * so dividing by 0.983040 converts to uS.
+         * Refactor the calculation to avoid overflow.
+         * Finally, multiply by 1000 to give nS.
+         */
+        return (offset + (53 * offset / 3072)) * 1000;
+}
+void __init ep93xx_timer_init(void)
 {
        u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
                    EP93XX_TIMER123_CONTROL_CLKSEL;
+        arch_gettimeoffset = ep93xx_gettimeoffset;
        /* Enable periodic HZ timer.  */
        __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
        __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
@@ -158,21 +175,6 @@ static void __init ep93xx_timer_init(void)
        setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 }
-static unsigned long ep93xx_gettimeoffset(void)
-{
-        int offset;
-        offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
-        /* Calculate (1000000 / 983040) * offset.  */
-        return offset + (53 * offset / 3072);
-}
-struct sys_timer ep93xx_timer = {
-        .init           = ep93xx_timer_init,
-        .offset         = ep93xx_gettimeoffset,
-};
 /*************************************************************************
 * EP93xx IRQ handling
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index b8f53d57a299..27b14ae92c7e 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -39,7 +39,6 @@
 #include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -276,8 +275,7 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -290,8 +288,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -304,8 +301,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -318,8 +314,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -332,8 +327,7 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -346,8 +340,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -360,8 +353,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -374,8 +366,7 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 7fd705b5efe4..0cca5b183309 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -17,7 +17,6 @@
 #include <mach/hardware.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,8 +38,7 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = gesbc9312_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 33a5122c6dc8..a14e1b37beff 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -53,7 +53,7 @@ int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
 void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
-extern struct sys_timer ep93xx_timer;
+extern void ep93xx_timer_init(void);
 void ep93xx_restart(char, const char *);
 void ep93xx_init_late(void);
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d64274fc5760..d2afb4dd82ab 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -86,5 +86,3 @@ static void arch_decomp_setup(void)
 {
        ethernet_reset();
 }
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 3d7cdab725b2..373583c29825 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -18,7 +18,6 @@
 #include <mach/hardware.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -82,8 +81,7 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -96,8 +94,7 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -110,8 +107,7 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
@@ -124,8 +120,7 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 0eb3f17a6fa2..36f22c1a31fe 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -25,7 +25,6 @@
 #include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -83,8 +82,7 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = simone_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 50043eef1cf2..aa86f86638dd 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -31,7 +31,6 @@
 #include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -176,8 +175,7 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = snappercl15_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3c4c233391dc..61f4b5dc4d7d 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -22,7 +22,6 @@
 #include <mach/hardware.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -246,8 +245,7 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
        .atag_offset    = 0x100,
        .map_io         = ts72xx_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = ts72xx_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index ba92e25e3016..605956fd07a2 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -34,7 +34,6 @@
 #include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -364,8 +363,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
        .atag_offset    = 0x100,
        .map_io         = vision_map_io,
        .init_irq       = ep93xx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = ep93xx_timer_init,
-        .timer          = &ep93xx_timer,
        .init_machine   = vision_init_machine,
        .init_late      = ep93xx_init_late,
        .restart        = ep93xx_restart,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e103c290bc9e..70f94c87479d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -105,11 +105,6 @@ config EXYNOS4_SETUP_FIMD0
        help
          Common setup code for FIMD0.
-config EXYNOS_DEV_SYSMMU
-        bool
-        help
-          Common setup code for SYSTEM MMU in EXYNOS platforms
 config EXYNOS4_DEV_USB_OHCI
        bool
        help
@@ -414,7 +409,7 @@ config MACH_EXYNOS4_DT
        select CPU_EXYNOS4210
        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
        select PINCTRL
-        select PINCTRL_EXYNOS4
+        select PINCTRL_EXYNOS
        select USE_OF
        help
          Machine support for Samsung Exynos4 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b189881657ec..435757e57bb4 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
 obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
-obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bbcb3dea0d40..8a8468d83c8c 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,7 +24,6 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
 #include "common.h"
 #include "clock-exynos4.h"
@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 14),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+                .devname        = "exynos-sysmmu.0",
                .enable         = exynos4_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+                .devname        = "exynos-sysmmu.1",
                .enable         = exynos4_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 2),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
+                .devname        = "exynos-sysmmu.2",
                .enable         = exynos4_clk_ip_tv_ctrl,
                .ctrlbit        = (1 << 4),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+                .devname        = "exynos-sysmmu.3",
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 11),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
+                .devname        = "exynos-sysmmu.4",
                .enable         = exynos4_clk_ip_image_ctrl,
                .ctrlbit        = (1 << 4),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
+                .devname        = "exynos-sysmmu.5",
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
+                .devname        = "exynos-sysmmu.6",
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 8),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
+                .devname        = "exynos-sysmmu.7",
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 9),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
+                .devname        = "exynos-sysmmu.8",
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 10),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
+                .devname        = "exynos-sysmmu.10",
                .enable         = exynos4_clk_ip_lcd0_ctrl,
                .ctrlbit        = (1 << 4),
        }
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index fed4c26e9dad..19af9f783c56 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -26,7 +26,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
 #include "common.h"
 #include "clock-exynos4.h"
@@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_ip_lcd1_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
+                .devname        = "exynos-sysmmu.9",
                .enable         = exynos4_clk_ip_image_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
+                .devname        = "exynos-sysmmu.11",
                .enable         = exynos4_clk_ip_lcd1_ctrl,
                .ctrlbit        = (1 << 4),
        }, {
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 8fba0b5fb8ab..529476f8ec71 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -26,7 +26,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
 #include "common.h"
 #include "clock-exynos4.h"
@@ -111,21 +110,31 @@ static struct clksrc_clk clksrcs[] = {
 static struct clk init_clocks_off[] = {
        {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
+                .devname        = "exynos-sysmmu.9",
                .enable         = exynos4_clk_ip_dmc_ctrl,
                .ctrlbit        = (1 << 24),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .devname        = "exynos-sysmmu.12",
                .enable         = exynos4212_clk_ip_isp0_ctrl,
                .ctrlbit        = (7 << 8),
        }, {
-                .name           = SYSMMU_CLOCK_NAME2,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .devname        = "exynos-sysmmu.13",
                .enable         = exynos4212_clk_ip_isp1_ctrl,
                .ctrlbit        = (1 << 4),
        }, {
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.14",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.15",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
                .name           = "flite",
                .devname        = "exynos-fimc-lite.0",
                .enable         = exynos4212_clk_ip_isp0_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index e9d7b80bae49..b0ea31fc9fb8 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -24,7 +24,6 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
 #include "common.h"
@@ -859,73 +858,78 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+                .devname        = "exynos-sysmmu.1",
                .enable         = &exynos5_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+                .devname        = "exynos-sysmmu.0",
                .enable         = &exynos5_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 2),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
+                .devname        = "exynos-sysmmu.2",
                .enable         = &exynos5_clk_ip_disp1_ctrl,
                .ctrlbit        = (1 << 9)
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+                .devname        = "exynos-sysmmu.3",
                .enable         = &exynos5_clk_ip_gen_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
+                .devname        = "exynos-sysmmu.4",
                .enable         = &exynos5_clk_ip_gen_ctrl,
                .ctrlbit        = (1 << 6)
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+                .devname        = "exynos-sysmmu.5",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+                .devname        = "exynos-sysmmu.6",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 8),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+                .devname        = "exynos-sysmmu.7",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 9),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+                .devname        = "exynos-sysmmu.8",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 10),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .devname        = "exynos-sysmmu.9",
                .enable         = &exynos5_clk_ip_isp0_ctrl,
                .ctrlbit        = (0x3F << 8),
        }, {
-                .name           = SYSMMU_CLOCK_NAME2,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
+                .devname        = "exynos-sysmmu.10",
                .enable         = &exynos5_clk_ip_isp1_ctrl,
                .ctrlbit        = (0xF << 4),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
+                .devname        = "exynos-sysmmu.11",
+                .enable         = &exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 8)
+        }, {
+                .name           = "sysmmu",
+                .devname        = "exynos-sysmmu.12",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 11),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
+                .devname        = "exynos-sysmmu.13",
                .enable         = &exynos5_clk_ip_gscl_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
-                .name           = SYSMMU_CLOCK_NAME,
+                .name           = "sysmmu",
-                .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
+                .devname        = "exynos-sysmmu.14",
                .enable         = &exynos5_clk_ip_acp_ctrl,
                .ctrlbit        = (1 << 7)
        }
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1a89824a5f78..d63d399c7bae 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/gpio.h>
@@ -22,12 +23,13 @@
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip.h>
 #include <linux/of_address.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/cacheflush.h>
@@ -35,7 +37,6 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
-#include <mach/pmu.h>
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -299,6 +300,7 @@ void exynos4_restart(char mode, const char *cmd)
 void exynos5_restart(char mode, const char *cmd)
 {
+        struct device_node *np;
        u32 val;
        void __iomem *addr;
@@ -306,8 +308,9 @@ void exynos5_restart(char mode, const char *cmd)
                val = 0x1;
                addr = EXYNOS_SWRESET;
        } else if (of_machine_is_compatible("samsung,exynos5440")) {
-                val = (0x10 << 20) | (0x1 << 16);
+                np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
-                addr = EXYNOS5440_SWRESET;
+                addr = of_iomap(np, 0) + 0xcc;
+                val = (0xfff << 20) | (0x1 << 16);
        } else {
                pr_err("%s: cannot support non-DT\n", __func__);
                return;
@@ -438,220 +441,6 @@ static void __init exynos5_init_clocks(int xtal)
 #endif
 }
-#define COMBINER_ENABLE_SET     0x0
-#define COMBINER_ENABLE_CLEAR   0x4
-#define COMBINER_INT_STATUS     0xC
-static DEFINE_SPINLOCK(irq_controller_lock);
-struct combiner_chip_data {
-        unsigned int irq_offset;
-        unsigned int irq_mask;
-        void __iomem *base;
-};
-static struct irq_domain *combiner_irq_domain;
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-        struct combiner_chip_data *combiner_data =
-                irq_data_get_irq_chip_data(data);
-        return combiner_data->base;
-}
-static void combiner_mask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->hwirq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-static void combiner_unmask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->hwirq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        unsigned int cascade_irq, combiner_irq;
-        unsigned long status;
-        chained_irq_enter(chip, desc);
-        spin_lock(&irq_controller_lock);
-        status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
-        spin_unlock(&irq_controller_lock);
-        status &= chip_data->irq_mask;
-        if (status == 0)
-                goto out;
-        combiner_irq = __ffs(status);
-        cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-        if (unlikely(cascade_irq >= NR_IRQS))
-                do_bad_IRQ(cascade_irq, desc);
-        else
-                generic_handle_irq(cascade_irq);
- out:
-        chained_irq_exit(chip, desc);
-}
-static struct irq_chip combiner_chip = {
-        .name           = "COMBINER",
-        .irq_mask       = combiner_mask_irq,
-        .irq_unmask     = combiner_unmask_irq,
-};
-static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
-{
-        unsigned int max_nr;
-        if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
-        else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
-        if (combiner_nr >= max_nr)
-                BUG();
-        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
-                BUG();
-        irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-static void __init combiner_init_one(unsigned int combiner_nr,
-                                     void __iomem *base)
-{
-        combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
-                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
-        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-        /* Disable all interrupts */
-        __raw_writel(combiner_data[combiner_nr].irq_mask,
-                     base + COMBINER_ENABLE_CLEAR);
-}
-#ifdef CONFIG_OF
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-                                     struct device_node *controller,
-                                     const u32 *intspec, unsigned int intsize,
-                                     unsigned long *out_hwirq,
-                                     unsigned int *out_type)
-{
-        if (d->of_node != controller)
-                return -EINVAL;
-        if (intsize < 2)
-                return -EINVAL;
-        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
-        *out_type = 0;
-        return 0;
-}
-#else
-static int combiner_irq_domain_xlate(struct irq_domain *d,
-                                     struct device_node *controller,
-                                     const u32 *intspec, unsigned int intsize,
-                                     unsigned long *out_hwirq,
-                                     unsigned int *out_type)
-{
-        return -EINVAL;
-}
-#endif
-static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                                   irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
-        irq_set_chip_data(irq, &combiner_data[hw >> 3]);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        return 0;
-}
-static struct irq_domain_ops combiner_irq_domain_ops = {
-        .xlate  = combiner_irq_domain_xlate,
-        .map    = combiner_irq_domain_map,
-};
-static void __init combiner_init(void __iomem *combiner_base,
-                                 struct device_node *np)
-{
-        int i, irq, irq_base;
-        unsigned int max_nr, nr_irq;
-        if (np) {
-                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
-                        pr_warning("%s: number of combiners not specified, "
-                                "setting default as %d.\n",
-                                __func__, EXYNOS4_MAX_COMBINER_NR);
-                        max_nr = EXYNOS4_MAX_COMBINER_NR;
-                }
-        } else {
-                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-                                                EXYNOS4_MAX_COMBINER_NR;
-        }
-        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
-        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
-        if (IS_ERR_VALUE(irq_base)) {
-                irq_base = COMBINER_IRQ(0, 0);
-                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
-        }
-        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
-                                &combiner_irq_domain_ops, &combiner_data);
-        if (WARN_ON(!combiner_irq_domain)) {
-                pr_warning("%s: irq domain init failed\n", __func__);
-                return;
-        }
-        for (i = 0; i < max_nr; i++) {
-                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
-                irq = IRQ_SPI(i);
-#ifdef CONFIG_OF
-                if (np)
-                        irq = irq_of_parse_and_map(np, i);
-#endif
-                combiner_cascade_irq(i, irq);
-        }
-}
-#ifdef CONFIG_OF
-static int __init combiner_of_init(struct device_node *np,
-                                   struct device_node *parent)
-{
-        void __iomem *combiner_base;
-        combiner_base = of_iomap(np, 0);
-        if (!combiner_base) {
-                pr_err("%s: failed to map combiner registers\n", __func__);
-                return -ENXIO;
-        }
-        combiner_init(combiner_base, np);
-        return 0;
-}
-static const struct of_device_id exynos_dt_irq_match[] = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
-        { .compatible = "samsung,exynos4210-combiner",
-                        .data = combiner_of_init, },
-        {},
-};
-#endif
 void __init exynos4_init_irq(void)
 {
        unsigned int gic_bank_offset;
@@ -662,7 +451,7 @@ void __init exynos4_init_irq(void)
                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
        else
-                of_irq_init(exynos_dt_irq_match);
+                irqchip_init();
 #endif
        if (!of_have_populated_dt())
@@ -679,7 +468,7 @@ void __init exynos4_init_irq(void)
 void __init exynos5_init_irq(void)
 {
 #ifdef CONFIG_OF
-        of_irq_init(exynos_dt_irq_match);
+        irqchip_init();
 #endif
        /*
         * The parameters of s5p_init_irq() are for VIC init.
@@ -1031,8 +820,8 @@ static int __init exynos_init_irq_eint(void)
         * interrupt support code here can be completely removed.
         */
        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,pinctrl-exynos4210", },
+                { .compatible = "samsung,exynos4210-pinctrl", },
-                { .compatible = "samsung,pinctrl-exynos4x12", },
+                { .compatible = "samsung,exynos4x12-pinctrl", },
        };
        struct device_node *pctrl_np, *wkup_np;
        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 04744f9c120f..9339bb8954be 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
-extern struct sys_timer exynos4_timer;
+extern void exynos4_timer_init(void);
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -60,8 +60,31 @@ void exynos4212_register_clocks(void);
 #define exynos4212_register_clocks()
 #endif
+struct device_node;
+void combiner_init(void __iomem *combiner_base, struct device_node *np);
 extern struct smp_operations exynos_smp_ops;
 extern void exynos_cpu_die(unsigned int cpu);
+/* PMU(Power Management Unit) support */
+#define PMU_TABLE_END   NULL
+enum sys_powerdown {
+        SYS_AFTR,
+        SYS_LPA,
+        SYS_SLEEP,
+        NUM_SYS_POWERDOWN,
+};
+extern unsigned long l2x0_regs_phys;
+struct exynos_pmu_conf {
+        void __iomem *reg;
+        unsigned int val[NUM_SYS_POWERDOWN];
+};
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void s3c_cpu_resume(void);
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 050924152776..fcfe0251aa3e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -23,10 +23,11 @@
 #include <asm/cpuidle.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
-#include <mach/pmu.h>
 #include <plat/cpu.h>
+#include "common.h"
 #define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
                        (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 9d1a60951d7b..c662c89794b2 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -21,7 +21,8 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
-#include <mach/regs-audss.h>
+#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
 static int exynos4_cfg_i2s(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
deleted file mode 100644
index c5b1ea301df0..000000000000
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* linux/arch/arm/mach-exynos/dev-sysmmu.c
- *
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - System MMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <plat/cpu.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/sysmmu.h>
-static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
-#define SYSMMU_PLATFORM_DEVICE(ipname, devid)                           \
-static struct sysmmu_platform_data platdata_##ipname = {                \
-        .dbgname = #ipname,                                             \
-};                                                                      \
-struct platform_device SYSMMU_PLATDEV(ipname) =                         \
-{                                                                       \
-        .name           = SYSMMU_DEVNAME_BASE,                          \
-        .id             = devid,                                        \
-        .dev            = {                                             \
-                .dma_mask               = &exynos_sysmmu_dma_mask,      \
-                .coherent_dma_mask      = DMA_BIT_MASK(32),             \
-                .platform_data          = &platdata_##ipname,           \
-        },                                                              \
-}
-SYSMMU_PLATFORM_DEVICE(mfc_l,   0);
-SYSMMU_PLATFORM_DEVICE(mfc_r,   1);
-SYSMMU_PLATFORM_DEVICE(tv,      2);
-SYSMMU_PLATFORM_DEVICE(jpeg,    3);
-SYSMMU_PLATFORM_DEVICE(rot,     4);
-SYSMMU_PLATFORM_DEVICE(fimc0,   5); /* fimc* and gsc* exist exclusively */
-SYSMMU_PLATFORM_DEVICE(fimc1,   6);
-SYSMMU_PLATFORM_DEVICE(fimc2,   7);
-SYSMMU_PLATFORM_DEVICE(fimc3,   8);
-SYSMMU_PLATFORM_DEVICE(gsc0,    5);
-SYSMMU_PLATFORM_DEVICE(gsc1,    6);
-SYSMMU_PLATFORM_DEVICE(gsc2,    7);
-SYSMMU_PLATFORM_DEVICE(gsc3,    8);
-SYSMMU_PLATFORM_DEVICE(isp,     9);
-SYSMMU_PLATFORM_DEVICE(fimd0,   10);
-SYSMMU_PLATFORM_DEVICE(fimd1,   11);
-SYSMMU_PLATFORM_DEVICE(camif0,  12);
-SYSMMU_PLATFORM_DEVICE(camif1,  13);
-SYSMMU_PLATFORM_DEVICE(2d,      14);
-#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
-#define SYSMMU_RESOURCE(core, ipname)                                   \
-        static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
-#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)                          \
-        DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),      \
-        DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
-#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)                  \
-        SYSMMU_RESOURCE(core, ipname) {                                 \
-                DEFINE_SYSMMU_RESOURCE(core, mem, irq)                  \
-        }
-struct sysmmu_resource_map {
-        struct platform_device *pdev;
-        struct resource *res;
-        u32 rnum;
-        struct device *pdd;
-        char *clocknames;
-};
-#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {                \
-        .pdev = &SYSMMU_PLATDEV(ipname),                                \
-        .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),             \
-        .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
-        .clocknames = SYSMMU_CLOCK_NAME,                                \
-}
-#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {      \
-        .pdev = &SYSMMU_PLATDEV(ipname),                                \
-        .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),             \
-        .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
-        .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,         \
-}
-#ifdef CONFIG_EXYNOS_DEV_PD
-#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {         \
-        .pdev = &SYSMMU_PLATDEV(ipname),                                \
-        .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),            \
-        .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
-        .clocknames = SYSMMU_CLOCK_NAME,                                \
-        .pdd = &exynos##core##_device_pd[pd].dev,                       \
-}
-#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
-        .pdev = &SYSMMU_PLATDEV(ipname),                                \
-        .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),            \
-        .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
-        .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,         \
-        .pdd = &exynos##core##_device_pd[pd].dev,                       \
-}
-#else
-#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)           \
-                SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
-#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)  \
-                SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
-#endif /* CONFIG_EXYNOS_DEV_PD */
-#ifdef CONFIG_ARCH_EXYNOS4
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,  FIMC0,  FIMC0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,  FIMC1,  FIMC1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,  FIMC2,  FIMC2);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,  FIMC3,  FIMC3);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,   JPEG,   JPEG);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,     G2D,    2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,     TV,     TV_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,    ROTATOR, ROTATOR);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,  FIMD0,  LCD0_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,  FIMD1,  LCD1_M1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r,  MFC_R,  MFC_M0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l,  MFC_L,  MFC_M1);
-SYSMMU_RESOURCE(EXYNOS4, isp) {
-        DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
-};
-static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,    fimc0,  PD_CAM),
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,    fimc1,  PD_CAM),
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,    fimc2,  PD_CAM),
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,    fimc3,  PD_CAM),
-        SYSMMU_RESOURCE_MAPPING_PD(4, tv,       tv,     PD_TV),
-        SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r,    mfc_r,  PD_MFC),
-        SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l,    mfc_l,  PD_MFC),
-        SYSMMU_RESOURCE_MAPPING_PD(4, rot,      rot,    PD_LCD0),
-        SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,     jpeg,   PD_CAM),
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,    fimd0,  PD_LCD0),
-};
-static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
-        SYSMMU_RESOURCE_MAPPING_PD(4, 2d,       2d,     PD_LCD0),
-        SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,    fimd1,  PD_LCD1),
-};
-static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
-        SYSMMU_RESOURCE_MAPPING(4,      2d,     2d_acp),
-        SYSMMU_RESOURCE_MAPPING_PD(4,   camif0, flite0, PD_ISP),
-        SYSMMU_RESOURCE_MAPPING_PD(4,   camif1, flite1, PD_ISP),
-        SYSMMU_RESOURCE_MAPPING_PD(4,   isp,    isp,    PD_ISP),
-};
-#endif /* CONFIG_ARCH_EXYNOS4 */
-#ifdef CONFIG_ARCH_EXYNOS5
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,   JPEG,   JPEG);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,  FIMD1,  FIMD1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,     2D,     2D);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,    ROTATOR, ROTATOR);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,     TV,     TV);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0,  LITE0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1,  LITE1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,   GSC0,   GSC0);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,   GSC1,   GSC1);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,   GSC2,   GSC2);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,   GSC3,   GSC3);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r,  MFC_R,  MFC_R);
-SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l,  MFC_L,  MFC_L);
-SYSMMU_RESOURCE(EXYNOS5, isp) {
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
-        DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
-};
-static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
-        SYSMMU_RESOURCE_MAPPING(5,      jpeg,   jpeg),
-        SYSMMU_RESOURCE_MAPPING(5,      fimd1,  fimd1),
-        SYSMMU_RESOURCE_MAPPING(5,      2d,     2d),
-        SYSMMU_RESOURCE_MAPPING(5,      rot,    rot),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   tv,     tv,     PD_DISP1),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   camif0, flite0, PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   camif1, flite1, PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   gsc0,   gsc0,   PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   gsc1,   gsc1,   PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   gsc2,   gsc2,   PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   gsc3,   gsc3,   PD_GSCL),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   mfc_r,  mfc_r,  PD_MFC),
-        SYSMMU_RESOURCE_MAPPING_PD(5,   mfc_l,  mfc_l,  PD_MFC),
-        SYSMMU_RESOURCE_MAPPING_MCPD(5, isp,    isp,    PD_ISP, mc_platdata),
-};
-#endif /* CONFIG_ARCH_EXYNOS5 */
-static int __init init_sysmmu_platform_device(void)
-{
-        int i, j;
-        struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
-        int nmap[2] = {0, 0};
-#ifdef CONFIG_ARCH_EXYNOS5
-        if (soc_is_exynos5250()) {
-                resmap[0] = sysmmu_resmap5;
-                nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
-                nmap[1] = 0;
-        }
-#endif
-#ifdef CONFIG_ARCH_EXYNOS4
-        if (resmap[0] == NULL) {
-                resmap[0] = sysmmu_resmap4;
-                nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
-        }
-        if (soc_is_exynos4210()) {
-                resmap[1] = sysmmu_resmap4210;
-                nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
-        }
-        if (soc_is_exynos4412() || soc_is_exynos4212()) {
-                resmap[1] = sysmmu_resmap4212;
-                nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
-        }
-#endif
-        for (j = 0; j < 2; j++) {
-                for (i = 0; i < nmap[j]; i++) {
-                        struct sysmmu_resource_map *map;
-                        struct sysmmu_platform_data *platdata;
-                        map = &resmap[j][i];
-                        map->pdev->dev.parent = map->pdd;
-                        platdata = map->pdev->dev.platform_data;
-                        platdata->clockname = map->clocknames;
-                        if (platform_device_add_resources(map->pdev, map->res,
-                                                                map->rnum)) {
-                                pr_err("%s: Failed to add device resources for "
-                                                "%s.%d\n", __func__,
-                                                map->pdev->name, map->pdev->id);
-                                continue;
-                        }
-                        if (platform_device_register(map->pdev)) {
-                                pr_err("%s: Failed to register %s.%d\n",
-                                        __func__, map->pdev->name,
-                                                map->pdev->id);
-                        }
-                }
-        }
-        return 0;
-}
-arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
deleted file mode 100644
index 7517c3f417af..000000000000
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - CPUFreq support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-enum cpufreq_level_index {
-        L0, L1, L2, L3, L4,
-        L5, L6, L7, L8, L9,
-        L10, L11, L12, L13, L14,
-        L15, L16, L17, L18, L19,
-        L20,
-};
-struct exynos_dvfs_info {
-        unsigned long   mpll_freq_khz;
-        unsigned int    pll_safe_idx;
-        unsigned int    pm_lock_idx;
-        unsigned int    max_support_idx;
-        unsigned int    min_support_idx;
-        struct clk      *cpu_clk;
-        unsigned int    *volt_table;
-        struct cpufreq_frequency_table  *freq_table;
-        void (*set_freq)(unsigned int, unsigned int);
-        bool (*need_apll_change)(unsigned int, unsigned int);
-};
-extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
-extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
-extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
deleted file mode 100644
index 7c27c2d4bf44..000000000000
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * EXYNOS4210 - PMU(Power Management Unit) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_PMU_H
-#define __ASM_ARCH_PMU_H __FILE__
-#define PMU_TABLE_END   NULL
-enum sys_powerdown {
-        SYS_AFTR,
-        SYS_LPA,
-        SYS_SLEEP,
-        NUM_SYS_POWERDOWN,
-};
-extern unsigned long l2x0_regs_phys;
-struct exynos_pmu_conf {
-        void __iomem *reg;
-        unsigned int val[NUM_SYS_POWERDOWN];
-};
-extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
-extern void s3c_cpu_resume(void);
-#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
deleted file mode 100644
index ca5a8b64218a..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-audss.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-audss.h
- *
- * Copyright (c) 2011 Samsung Electronics
- *              http://www.samsung.com
- *
- * Exynos4 Audio SubSystem clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_AUDSS_H
-#define __PLAT_REGS_AUDSS_H __FILE__
-#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
-#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
index 9c7b4bfd546f..f2b50506b9f6 100644
--- a/arch/arm/mach-exynos/include/mach/regs-irq.h
+++ b/arch/arm/mach-exynos/include/mach/regs-irq.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_REGS_IRQ_H
 #define __ASM_ARCH_REGS_IRQ_H __FILE__
-#include <asm/hardware/gic.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/map.h>
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
deleted file mode 100644
index 88a4543b0001..000000000000
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - System MMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
-#define _ARM_MACH_EXYNOS_SYSMMU_H_
-struct sysmmu_platform_data {
-        char *dbgname;
-        /* comma(,) separated list of clock names for clock gating */
-        char *clockname;
-};
-#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
-#define SYSMMU_CLOCK_NAME "sysmmu"
-#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
-#ifdef CONFIG_EXYNOS_DEV_SYSMMU
-#include <linux/device.h>
-struct platform_device;
-#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
-extern struct platform_device SYSMMU_PLATDEV(mfc_l);
-extern struct platform_device SYSMMU_PLATDEV(mfc_r);
-extern struct platform_device SYSMMU_PLATDEV(tv);
-extern struct platform_device SYSMMU_PLATDEV(jpeg);
-extern struct platform_device SYSMMU_PLATDEV(rot);
-extern struct platform_device SYSMMU_PLATDEV(fimc0);
-extern struct platform_device SYSMMU_PLATDEV(fimc1);
-extern struct platform_device SYSMMU_PLATDEV(fimc2);
-extern struct platform_device SYSMMU_PLATDEV(fimc3);
-extern struct platform_device SYSMMU_PLATDEV(gsc0);
-extern struct platform_device SYSMMU_PLATDEV(gsc1);
-extern struct platform_device SYSMMU_PLATDEV(gsc2);
-extern struct platform_device SYSMMU_PLATDEV(gsc3);
-extern struct platform_device SYSMMU_PLATDEV(isp);
-extern struct platform_device SYSMMU_PLATDEV(fimd0);
-extern struct platform_device SYSMMU_PLATDEV(fimd1);
-extern struct platform_device SYSMMU_PLATDEV(camif0);
-extern struct platform_device SYSMMU_PLATDEV(camif1);
-extern struct platform_device SYSMMU_PLATDEV(2d);
-#ifdef CONFIG_IOMMU_API
-static inline void platform_set_sysmmu(
-                                struct device *sysmmu, struct device *dev)
-{
-        dev->archdata.iommu = sysmmu;
-}
-#endif
-#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
-#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
-#endif
-#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
-#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index b938f9fc1dd1..685f29173afa 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -16,7 +16,6 @@
 #include <linux/smsc911x.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/cpu.h>
@@ -201,9 +200,8 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = armlex4210_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = armlex4210_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 92757ff817ae..3358088c822a 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,7 +15,6 @@
 #include <linux/serial_core.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <mach/map.h>
 #include <plat/cpu.h>
@@ -80,6 +79,40 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
                                "exynos-tmu", NULL),
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
+                        "exynos-sysmmu.0", NULL), /* MFC_L */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
+                        "exynos-sysmmu.1", NULL), /* MFC_R */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
+                        "exynos-sysmmu.2", NULL), /* TV */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
+                        "exynos-sysmmu.3", NULL), /* JPEG */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
+                        "exynos-sysmmu.4", NULL), /* ROTATOR */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
+                        "exynos-sysmmu.5", NULL), /* FIMC0 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
+                        "exynos-sysmmu.6", NULL), /* FIMC1 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
+                        "exynos-sysmmu.7", NULL), /* FIMC2 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
+                        "exynos-sysmmu.8", NULL), /* FIMC3 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
+                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
+                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
+                        "exynos-sysmmu.10", NULL), /* FIMD0 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
+                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
+                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
+                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
+                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
+                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
        {},
 };
@@ -107,10 +140,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = exynos4_dt_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = exynos4_dt_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .dt_compat      = exynos4_dt_compat,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e99d3d8f2bcf..acaeb14db54b 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -16,7 +16,6 @@
 #include <linux/io.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <mach/map.h>
 #include <mach/regs-pmu.h>
@@ -104,6 +103,42 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
                                "exynos-tmu", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
+                                "samsung-i2s.0", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
+                                "samsung-i2s.1", NULL),
+        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
+                                "samsung-i2s.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
+                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
+                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
+                        "exynos-sysmmu.2", NULL), /* TV */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
+                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
+                        "exynos-sysmmu.4", NULL), /* ROTATOR */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
+                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
+                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
+                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
+                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
+                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
+                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
+                        "exynos-sysmmu.11", NULL), /* FIMD1 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
+                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
+                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
+        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
+                        "exynos-sysmmu.14", NULL), /* G2D */
        {},
 };
@@ -179,10 +214,9 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
        .init_irq       = exynos5_init_irq,
        .smp            = smp_ops(exynos_smp_ops),
        .map_io         = exynos5_dt_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = exynos5_dt_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .dt_compat      = exynos5_dt_compat,
        .restart        = exynos5_restart,
        .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 27d4ed8b116e..1ea79730187f 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -39,7 +39,6 @@
 #include <media/v4l2-mediabus.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/adc.h>
@@ -1209,25 +1208,25 @@ static struct i2c_board_info m5mols_board_info = {
        .platform_data  = &m5mols_platdata,
 };
-static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
+static struct fimc_source_info nuri_camera_sensors[] = {
        {
                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_ITU_601,
+                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
                .board_info     = &s5k6aa_board_info,
                .clk_frequency  = 24000000UL,
                .i2c_bus_num    = 6,
        }, {
                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_MIPI_CSI2,
+                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
                .board_info     = &m5mols_board_info,
                .clk_frequency  = 24000000UL,
        },
 };
 static struct s5p_platform_fimc fimc_md_platdata = {
-        .isp_info       = nuri_camera_sensors,
+        .source_info    = nuri_camera_sensors,
        .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
 };
@@ -1379,10 +1378,9 @@ MACHINE_START(NURI, "NURI")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = nuri_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = nuri_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .reserve        = &nuri_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5e34b9c16196..579d2d171daa 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -29,7 +29,6 @@
 #include <linux/platform_data/usb-exynos.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
@@ -814,10 +813,9 @@ MACHINE_START(ORIGEN, "ORIGEN")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = origen_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = origen_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .reserve        = &origen_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index ae6da40c2aa9..fe6149624b84 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -25,7 +25,6 @@
 #include <linux/platform_data/s3c-hsotg.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/samsung_fimd.h>
@@ -376,9 +375,8 @@ MACHINE_START(SMDK4212, "SMDK4212")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .restart        = exynos4_restart,
        .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,10 +388,9 @@ MACHINE_START(SMDK4412, "SMDK4412")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .restart        = exynos4_restart,
        .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 35548e3c097d..d71672922b19 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -26,7 +26,6 @@
 #include <linux/platform_data/usb-exynos.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
@@ -423,9 +422,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .reserve        = &smdkv310_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
@@ -436,10 +434,9 @@ MACHINE_START(SMDKC210, "SMDKC210")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &exynos4_timer,
+        .init_time      = exynos4_timer_init,
        .reserve        = &smdkv310_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 9e3340f18950..497fcb793dc1 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -29,7 +29,6 @@
 #include <drm/exynos_drm.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/samsung_fimd.h>
@@ -988,12 +987,12 @@ static struct i2c_board_info m5mols_board_info = {
        .platform_data = &m5mols_platdata,
 };
-static struct s5p_fimc_isp_info universal_camera_sensors[] = {
+static struct fimc_source_info universal_camera_sensors[] = {
        {
                .mux_id         = 0,
                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_ITU_601,
+                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
                .board_info     = &s5k6aa_board_info,
                .i2c_bus_num    = 0,
                .clk_frequency  = 24000000UL,
@@ -1001,7 +1000,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
                .mux_id         = 0,
                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_MIPI_CSI2,
+                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
                .board_info     = &m5mols_board_info,
                .i2c_bus_num    = 0,
                .clk_frequency  = 24000000UL,
@@ -1009,7 +1008,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
 };
 static struct s5p_platform_fimc fimc_md_platdata = {
-        .isp_info       = universal_camera_sensors,
+        .source_info    = universal_camera_sensors,
        .num_clients    = ARRAY_SIZE(universal_camera_sensors),
 };
@@ -1151,10 +1150,9 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = universal_map_io,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = universal_machine_init,
        .init_late      = exynos_init_late,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .reserve        = &universal_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 57668eb68e75..c9d6650f9b5d 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -22,7 +22,6 @@
 #include <linux/of.h>
 #include <asm/arch_timer.h>
-#include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <plat/cpu.h>
@@ -255,13 +254,9 @@ static struct irqaction mct_comp_event_irq = {
 static void exynos4_clockevent_init(void)
 {
-        clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
-        mct_comp_device.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &mct_comp_device);
-        mct_comp_device.min_delta_ns =
-                clockevent_delta2ns(0xf, &mct_comp_device);
        mct_comp_device.cpumask = cpumask_of(0);
-        clockevents_register_device(&mct_comp_device);
+        clockevents_config_and_register(&mct_comp_device, clk_rate,
+                                        0xf, 0xffffffff);
        if (soc_is_exynos5250())
                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
@@ -404,14 +399,8 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
        evt->set_mode = exynos4_tick_set_mode;
        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
        evt->rating = 450;
+        clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
-        clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
+                                        0xf, 0x7fffffff);
-        evt->max_delta_ns =
-                clockevent_delta2ns(0x7fffffff, evt);
-        evt->min_delta_ns =
-                clockevent_delta2ns(0xf, evt);
-        clockevents_register_device(evt);
        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
@@ -478,7 +467,7 @@ static void __init exynos4_timer_resources(void)
 #endif /* CONFIG_LOCAL_TIMERS */
 }
-static void __init exynos_timer_init(void)
+void __init exynos4_timer_init(void)
 {
        if (soc_is_exynos5440()) {
                arch_timer_of_register();
@@ -494,7 +483,3 @@ static void __init exynos_timer_init(void)
        exynos4_clocksource_init();
        exynos4_clockevent_init();
 }
-struct sys_timer exynos4_timer = {
-        .init           = exynos_timer_init,
-};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index c5c840e947b8..60f7c5be057d 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,9 +20,9 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
@@ -149,7 +149,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
                __raw_writel(virt_to_phys(exynos4_secondary_startup),
                                                        cpu_boot_reg(phys_cpu));
-                gic_raise_softirq(cpumask_of(cpu), 0);
+                arch_send_wakeup_ipi_mask(cpumask_of(cpu));
                if (pen_release == -1)
                        break;
@@ -190,8 +190,6 @@ static void __init exynos_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index b9b539cac81e..e3faaa812016 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -34,7 +34,8 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
-#include <mach/pmu.h>
+#include "common.h"
 static struct sleep_save exynos4_set_clksrc[] = {
        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
@@ -91,8 +92,8 @@ static int exynos_cpu_suspend(unsigned long arg)
        /* issue the standby signal into the pm unit. */
        cpu_do_idle();
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 static void exynos_pm_prepare(void)
@@ -282,6 +283,8 @@ static void exynos_pm_resume(void)
        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
                tmp |= S5P_CENTRAL_LOWPWR_CFG;
                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+                /* clear the wakeup state register */
+                __raw_writel(0x0, S5P_WAKEUP_STAT);
                /* No need to perform below restore code */
                goto early_wakeup;
        }
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 3a48c852be6c..daebc1abc966 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,7 +14,8 @@
 #include <linux/bug.h>
 #include <mach/regs-clock.h>
-#include <mach/pmu.h>
+#include "common.h"
 static struct exynos_pmu_conf *exynos_pmu_config;
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 25b453601acc..6987a09ec219 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -90,6 +90,6 @@ MACHINE_START(CATS, "Chalice-CATS")
        .fixup          = fixup_cats,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
-        .timer          = &isa_timer,
+        .init_time      = isa_timer_init,
        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index c9767b892cb2..a846e50a07b8 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,6 +1,6 @@
-extern struct sys_timer footbridge_timer;
+extern void footbridge_timer_init(void);
-extern struct sys_timer isa_timer;
+extern void isa_timer_init(void);
 extern void isa_rtc_init(void);
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 3b54196447c7..9ee78f7b4990 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -93,7 +93,7 @@ static struct irqaction footbridge_timer_irq = {
 /*
 * Set up timer interrupt.
 */
-static void __init footbridge_timer_init(void)
+void __init footbridge_timer_init(void)
 {
        struct clock_event_device *ce = &ckevt_dc21285;
@@ -101,14 +101,6 @@ static void __init footbridge_timer_init(void)
        setup_irq(ce->irq, &footbridge_timer_irq);
-        clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
-        ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
-        ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
        ce->cpumask = cpumask_of(smp_processor_id());
+        clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
-        clockevents_register_device(ce);
 }
-struct sys_timer footbridge_timer = {
-        .init           = footbridge_timer_init,
-};
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index b09551ef89ca..b08243500e2e 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -101,7 +101,7 @@ MACHINE_START(EBSA285, "EBSA285")
        .video_end      = 0x000bffff,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
-        .timer          = &footbridge_timer,
+        .init_time      = footbridge_timer_init,
        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/include/mach/uncompress.h b/arch/arm/mach-footbridge/include/mach/uncompress.h
index 5dfa44287346..a69398c05a52 100644
--- a/arch/arm/mach-footbridge/include/mach/uncompress.h
+++ b/arch/arm/mach-footbridge/include/mach/uncompress.h
@@ -35,4 +35,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index c40bb415f4b5..d9301dd56354 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -31,14 +31,10 @@ static struct irqaction pit_timer_irq = {
        .dev_id         = &i8253_clockevent,
 };
-static void __init isa_timer_init(void)
+void __init isa_timer_init(void)
 {
        clocksource_i8253_init();
        setup_irq(i8253_clockevent.irq, &pit_timer_irq);
        clockevent_i8253_init(false);
 }
-struct sys_timer isa_timer = {
-        .init           = isa_timer_init,
-};
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index d2d14339c6c4..90ea23fdce4c 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -766,6 +766,6 @@ MACHINE_START(NETWINDER, "Rebel-NetWinder")
        .fixup          = fixup_netwinder,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
-        .timer          = &isa_timer,
+        .init_time      = isa_timer_init,
        .restart        = netwinder_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index e1e9990fa957..7bdeabdcd4d8 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -18,7 +18,7 @@ MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
        .atag_offset    = 0x100,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
-        .timer          = &footbridge_timer,
+        .init_time      = footbridge_timer_init,
        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 5927d3c253aa..08bd650c42f3 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -31,10 +31,6 @@
 #include "common.h"
-static struct sys_timer ib4220b_timer = {
-        .init   = gemini_timer_init,
-};
 static struct gpio_led ib4220b_leds[] = {
        {
                .name                   = "nas4220b:orange:hdd",
@@ -105,6 +101,6 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
        .atag_offset    = 0x100,
        .map_io         = gemini_map_io,
        .init_irq       = gemini_init_irq,
-        .timer          = &ib4220b_timer,
+        .init_time      = gemini_timer_init,
        .init_machine   = ib4220b_init,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index cd7437a1cea0..fa0a36337f4d 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -71,10 +71,6 @@ static struct platform_device rut1xx_leds = {
        },
 };
-static struct sys_timer rut1xx_timer = {
-        .init   = gemini_timer_init,
-};
 static void __init rut1xx_init(void)
 {
        gemini_gpio_init();
@@ -89,6 +85,6 @@ MACHINE_START(RUT100, "Teltonika RUT100")
        .atag_offset    = 0x100,
        .map_io         = gemini_map_io,
        .init_irq       = gemini_init_irq,
-        .timer          = &rut1xx_timer,
+        .init_time      = gemini_timer_init,
        .init_machine   = rut1xx_init,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index a367880368f1..3321cd6cc1f3 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -80,10 +80,6 @@ static struct platform_device wbd111_leds_device = {
        },
 };
-static struct sys_timer wbd111_timer = {
-        .init   = gemini_timer_init,
-};
 static struct mtd_partition wbd111_partitions[] = {
        {
                .name           = "RedBoot",
@@ -132,6 +128,6 @@ MACHINE_START(WBD111, "Wiliboard WBD-111")
        .atag_offset    = 0x100,
        .map_io         = gemini_map_io,
        .init_irq       = gemini_init_irq,
-        .timer          = &wbd111_timer,
+        .init_time      = gemini_timer_init,
        .init_machine   = wbd111_init,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index f382811c1319..fe33c825fdaf 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -80,10 +80,6 @@ static struct platform_device wbd222_leds_device = {
        },
 };
-static struct sys_timer wbd222_timer = {
-        .init   = gemini_timer_init,
-};
 static struct mtd_partition wbd222_partitions[] = {
        {
                .name           = "RedBoot",
@@ -132,6 +128,6 @@ MACHINE_START(WBD222, "Wiliboard WBD-222")
        .atag_offset    = 0x100,
        .map_io         = gemini_map_io,
        .init_irq       = gemini_init_irq,
-        .timer          = &wbd222_timer,
+        .init_time      = gemini_timer_init,
        .init_machine   = wbd222_init,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 0efa26247235..02e225673acb 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -39,6 +39,4 @@ static inline void flush(void)
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index aa1331e86bcf..17ef91fa3d56 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -42,12 +42,12 @@ void __init arch_dma_init(dma_t *dma)
 }
 /*
- * Return usecs since last timer reload
+ * Return nsecs since last timer reload
 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
 */
-unsigned long h720x_gettimeoffset(void)
+u32 h720x_gettimeoffset(void)
 {
-        return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
+        return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000;
 }
 /*
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
index 2489537d33dd..7e738410ca93 100644
--- a/arch/arm/mach-h720x/common.h
+++ b/arch/arm/mach-h720x/common.h
@@ -13,18 +13,18 @@
 *
 */
-extern unsigned long h720x_gettimeoffset(void);
+extern u32 h720x_gettimeoffset(void);
 extern void __init h720x_init_irq(void);
 extern void __init h720x_map_io(void);
 extern void h720x_restart(char, const char *);
 #ifdef CONFIG_ARCH_H7202
-extern struct sys_timer h7202_timer;
+extern void h7202_timer_init(void);
 extern void __init init_hw_h7202(void);
 extern void __init h7202_init_irq(void);
 extern void __init h7202_init_time(void);
 #endif
 #ifdef CONFIG_ARCH_H7201
-extern struct sys_timer h7201_timer;
+extern void h7201_timer_init(void);
 #endif
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
index 24df2a349a98..13c741215387 100644
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ b/arch/arm/mach-h720x/cpu-h7201.c
@@ -44,8 +44,10 @@ static struct irqaction h7201_timer_irq = {
 /*
 * Setup TIMER0 as system timer
 */
-void __init h7201_init_time(void)
+void __init h7201_timer_init(void)
 {
+        arch_gettimeoffset = h720x_gettimeoffset;
        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
@@ -53,8 +55,3 @@ void __init h7201_init_time(void)
        setup_irq(IRQ_TIMER0, &h7201_timer_irq);
 }
-struct sys_timer h7201_timer = {
-        .init           = h7201_init_time,
-        .offset         = h720x_gettimeoffset,
-};
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index c37d570b852d..e2ae7e898f9d 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -178,8 +178,10 @@ static struct irqaction h7202_timer_irq = {
 /*
 * Setup TIMER0 as system timer
 */
-void __init h7202_init_time(void)
+void __init h7202_timer_init(void)
 {
+        arch_gettimeoffset = h720x_gettimeoffset;
        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
@@ -188,11 +190,6 @@ void __init h7202_init_time(void)
        setup_irq(IRQ_TIMER0, &h7202_timer_irq);
 }
-struct sys_timer h7202_timer = {
-        .init           = h7202_init_time,
-        .offset         = h720x_gettimeoffset,
-};
 void __init h7202_init_irq (void)
 {
        int     irq;
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 5fdb20c855e2..4fdeb686c0a9 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -32,7 +32,7 @@ MACHINE_START(H7201, "Hynix GMS30C7201")
        .atag_offset    = 0x1000,
        .map_io         = h720x_map_io,
        .init_irq       = h720x_init_irq,
-        .timer          = &h7201_timer,
+        .init_time      = h7201_timer_init,
        .dma_zone_size  = SZ_256M,
        .restart        = h720x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 169673036c59..f68e967a2062 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -74,7 +74,7 @@ MACHINE_START(H7202, "Hynix HMS30C7202")
        .atag_offset    = 0x100,
        .map_io         = h720x_map_io,
        .init_irq       = h7202_init_irq,
-        .timer          = &h7202_timer,
+        .init_time      = h7202_timer_init,
        .init_machine   = init_eval_h7202,
        .dma_zone_size  = SZ_256M,
        .restart        = h720x_restart,
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
index d6623234f61e..43e343c4b50a 100644
--- a/arch/arm/mach-h720x/include/mach/uncompress.h
+++ b/arch/arm/mach-h720x/include/mach/uncompress.h
@@ -32,6 +32,5 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 551c97e87a78..44b12f9c1584 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,5 +1,7 @@
 config ARCH_HIGHBANK
        bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
@@ -11,5 +13,7 @@ config ARCH_HIGHBANK
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
        select HAVE_SMP
+        select MAILBOX
+        select PL320_MBOX
        select SPARSE_IRQ
        select USE_OF
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 80235b46cb58..3f65206a9b92 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -2,7 +2,6 @@
 #define __HIGHBANK_CORE_H
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_clocks_init(void);
 extern void highbank_restart(char, const char *);
 extern void __iomem *scu_base_addr;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 981dc1e1da51..a4f9f50247d4 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -18,6 +18,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
@@ -25,14 +26,15 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
 #include <linux/amba/bus.h>
+#include <linux/clk-provider.h>
 #include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,19 +61,13 @@ static void __init highbank_scu_map_io(void)
 void highbank_set_cpu_jump(int cpu, void *jump_addr)
 {
-        cpu = cpu_logical_map(cpu);
+        cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
                          HB_JUMP_TABLE_PHYS(cpu) + 15);
 }
-const static struct of_device_id irq_match[] = {
-        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {}
-};
 #ifdef CONFIG_CACHE_L2X0
 static void highbank_l2x0_disable(void)
 {
@@ -82,7 +78,7 @@ static void highbank_l2x0_disable(void)
 static void __init highbank_init_irq(void)
 {
-        of_irq_init(irq_match);
+        irqchip_init();
        if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
                highbank_scu_map_io();
@@ -116,7 +112,7 @@ static void __init highbank_timer_init(void)
        WARN_ON(!timer_base);
        irq = irq_of_parse_and_map(np, 0);
-        highbank_clocks_init();
+        of_clk_init(NULL);
        lookup.clk = of_clk_get(np, 0);
        clkdev_add(&lookup);
@@ -129,10 +125,6 @@ static void __init highbank_timer_init(void)
        arch_timer_sched_clock_init();
 }
-static struct sys_timer highbank_timer = {
-        .init = highbank_timer_init,
-};
 static void highbank_power_off(void)
 {
        highbank_set_pwr_shutdown();
@@ -209,8 +201,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
        .smp            = smp_ops(highbank_smp_ops),
        .map_io         = debug_ll_io_init,
        .init_irq       = highbank_init_irq,
-        .timer          = &highbank_timer,
+        .init_time      = highbank_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
        .restart        = highbank_restart,
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index 4ecc864ac8b9..8797a7001720 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -17,9 +17,9 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/smp_scu.h>
-#include <asm/hardware/gic.h>
 #include "core.h"
@@ -33,7 +33,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        highbank_set_cpu_jump(cpu, secondary_startup);
-        gic_raise_softirq(cpumask_of(cpu), 0);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        return 0;
 }
@@ -56,8 +56,6 @@ static void __init highbank_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 70af9d13fcef..5995df7f2622 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
 static inline void highbank_set_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        else
@@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
 static inline void highbank_clear_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
        else
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0a2349dc7018..4c9c6f9d2c55 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -95,9 +95,6 @@ config MACH_MX27
 config ARCH_MX5
        bool
-config ARCH_MX50
-        bool
 config ARCH_MX51
        bool
@@ -164,11 +161,6 @@ config SOC_IMX5
        select CPU_V7
        select MXC_TZIC
-config SOC_IMX50
-        bool
-        select ARCH_MX50
-        select SOC_IMX5
 config  SOC_IMX51
        bool
        select ARCH_MX5
@@ -488,7 +480,7 @@ config MACH_MX31ADS_WM1133_EV1
        bool "Support Wolfson Microelectronics 1133-EV1 module"
        depends on MACH_MX31ADS
        depends on MFD_WM8350_I2C
-        depends on REGULATOR_WM8350
+        depends on REGULATOR_WM8350 = y
        select MFD_WM8350_CONFIG_MODE_0
        select MFD_WM8352_CONFIG_MODE_0
        help
@@ -738,25 +730,10 @@ endif
 if ARCH_MULTI_V7
-comment "i.MX5 platforms:"
-config MACH_MX50_RDP
-        bool "Support MX50 reference design platform"
-        depends on BROKEN
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX50
-        help
-          Include support for MX50 reference design platform (RDP) board. This
-          includes specific configurations for the board and its peripherals.
 comment "i.MX51 machines:"
 config MACH_IMX51_DT
        bool "Support i.MX51 platforms from device tree"
-        select MACH_MX51_BABBAGE
        select SOC_IMX51
        help
          Include support for Freescale i.MX51 based platforms
@@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE
          u-boot. This includes specific configurations for the board and its
          peripherals.
-config MACH_MX51_3DS
-        bool "Support MX51PDK (3DS)"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_DEBUG_BOARD
-        select SOC_IMX51
-        help
-          Include support for MX51PDK (3DS) platform. This includes specific
-          configurations for the board and its peripherals.
 config MACH_EUKREA_CPUIMX51SD
        bool "Support Eukrea CPUIMX51SD module"
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0634b3152c24..c4ce0906d76a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -28,7 +28,11 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-y += cpuidle.o
+obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+endif
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
@@ -88,7 +92,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
-obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
@@ -103,10 +106,8 @@ endif
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
-obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index b27815de8473..41ba1bb0437b 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35)	+= 0x80008000
 params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
 initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
-zreladdr-$(CONFIG_SOC_IMX50)    += 0x70008000
-params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
-initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
 zreladdr-$(CONFIG_SOC_IMX51)    += 0x90008000
 params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
 initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 2c570cdaae7b..69858c78f40d 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -224,6 +224,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
        clk_prepare_enable(clk[emi_ahb]);
+        /* Clock source for gpt must be derived from AHB */
+        clk_set_parent(clk[per5_sel], clk[ahb]);
        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 1ffe3b534e51..30b3242a7d49 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = {
        "32k", "usb_div", "dptc",
 };
-static const char *ssi_sel_clks[] = { "spll", "mpll", };
+static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
 enum mx27_clks {
        dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
@@ -82,7 +82,7 @@ enum mx27_clks {
        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-        mpll_sel, clk_max
+        mpll_sel, spll_gate, clk_max
 };
 static struct clk *clk[clk_max];
@@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref)
                        ARRAY_SIZE(mpll_sel_clks));
        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
@@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
        clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
        clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+        clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
        clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
        clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
@@ -228,9 +229,12 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
-        clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
+        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
+        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
+        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
+        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 16ccbd41dea9..b5b65f3efaf1 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -34,8 +34,8 @@ static const char *csi_sel[] = { "upll", "spll", };
 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
 enum mx31_clks {
-        ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
+        dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
-        per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
+        per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
        fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
        iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
        uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
@@ -46,12 +46,15 @@ enum mx31_clks {
 };
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 int __init mx31_clocks_init(unsigned long fref)
 {
        void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
        int i;
+        struct device_node *np;
+        clk[dummy] = imx_clk_fixed("dummy", 0);
        clk[ckih] = imx_clk_fixed("ckih", fref);
        clk[ckil] = imx_clk_fixed("ckil", 32768);
        clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
@@ -116,6 +119,14 @@ int __init mx31_clocks_init(unsigned long fref)
                        pr_err("imx31 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
+        if (np) {
+                clk_data.clks = clk;
+                clk_data.clk_num = ARRAY_SIZE(clk);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index f0727e80815d..74e3a34d78b8 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -67,13 +67,13 @@ enum mx35_clks {
 static struct clk *clk[clk_max];
-int __init mx35_clocks_init()
+int __init mx35_clocks_init(void)
 {
        void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
        u32 pdr0, consumer_sel, hsp_sel;
        struct arm_ahb_div *aad;
        unsigned char *hsp_div;
-        int i;
+        u32 i;
        pdr0 = __raw_readl(base + MXC_CCM_PDR0);
        consumer_sel = (pdr0 >> 16) & 0xf;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fb7cb841b64c..0f39f8c93b94 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -83,6 +83,7 @@ enum imx5_clks {
        ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
        can_sel, can1_serial_gate, can1_ipg_gate,
+        owire_gate,
        clk_max
 };
@@ -233,12 +234,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
        clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
        clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
+        clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
        for (i = 0; i < ARRAY_SIZE(clk); i++)
                if (IS_ERR(clk[i]))
                        pr_err("i.MX5 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
-        
        clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index c0c4e723b7f5..7b025ee528a5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -54,9 +54,18 @@
 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+#define CGPR                            0x64
+#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
 static void __iomem *ccm_base;
-void __init imx6q_clock_map_io(void) { }
+void imx6q_set_chicken_bit(void)
+{
+        u32 val = readl_relaxed(ccm_base + CGPR);
+        val |= BM_CGPR_CHICKEN_BIT;
+        writel_relaxed(val, ccm_base + CGPR);
+}
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 {
@@ -68,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                break;
        case WAIT_UNCLOCKED:
                val |= 0x1 << BP_CLPCR_LPM;
+                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
                break;
        case STOP_POWER_ON:
                val |= 0x2 << BP_CLPCR_LPM;
@@ -154,8 +164,8 @@ enum mx6q_clks {
        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
+        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        clk_max
+        usbphy2_gate, clk_max
 };
 static struct clk *clk[clk_max];
@@ -208,8 +218,21 @@ int __init mx6q_clocks_init(void)
        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
-        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
+        /*
-        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+         * Bit 20 is the reserved and read-only bit, we do this only for:
+         * - Do nothing for usbphy clk_enable/disable
+         * - Keep refcount when do usbphy clk_enable/disable, in that case,
+         * the clk framework may need to enable/disable usbphy's parent
+         */
+        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
+        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
+        /*
+         * usbphy*_gate needs to be on after system boots up, and software
+         * never needs to control it anymore.
+         */
+        clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
+        clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
@@ -436,6 +459,11 @@ int __init mx6q_clocks_init(void)
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                clk_prepare_enable(clk[clks_init_on[i]]);
+        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+                clk_prepare_enable(clk[usbphy1_gate]);
+                clk_prepare_enable(clk[usbphy2_gate]);
+        }
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index fa36fb84ab19..5a800bfcec5b 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -21,7 +21,6 @@ extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
-extern void mx50_map_io(void);
 extern void mx51_map_io(void);
 extern void mx53_map_io(void);
 extern void imx1_init_early(void);
@@ -30,7 +29,6 @@ extern void imx25_init_early(void);
 extern void imx27_init_early(void);
 extern void imx31_init_early(void);
 extern void imx35_init_early(void);
-extern void imx50_init_early(void);
 extern void imx51_init_early(void);
 extern void imx53_init_early(void);
 extern void mxc_init_irq(void __iomem *);
@@ -41,7 +39,6 @@ extern void mx25_init_irq(void);
 extern void mx27_init_irq(void);
 extern void mx31_init_irq(void);
 extern void mx35_init_irq(void);
-extern void mx50_init_irq(void);
 extern void mx51_init_irq(void);
 extern void mx53_init_irq(void);
 extern void imx1_soc_init(void);
@@ -50,7 +47,6 @@ extern void imx25_soc_init(void);
 extern void imx27_soc_init(void);
 extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
-extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx51_init_late(void);
 extern void imx53_init_late(void);
@@ -109,27 +105,22 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx27_handle_irq avic_handle_irq
 #define imx31_handle_irq avic_handle_irq
 #define imx35_handle_irq avic_handle_irq
-#define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq gic_handle_irq
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-#ifdef CONFIG_DEBUG_LL
-extern void imx_lluart_map_io(void);
-#else
-static inline void imx_lluart_map_io(void) {}
-#endif
 extern void v7_cpu_resume(void);
 extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
 extern void imx_scu_map_io(void);
 extern void imx_smp_prepare(void);
+extern void imx_scu_standby_enable(void);
 #else
 static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
+static inline void imx_scu_standby_enable(void) {}
 #endif
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
@@ -139,7 +130,7 @@ extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-extern void imx6q_clock_map_io(void);
+extern void imx6q_set_chicken_bit(void);
 extern void imx_cpu_die(unsigned int cpu);
 extern int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index d88760014ff9..d7ce72252a4e 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -22,7 +22,6 @@
 static int mx5_cpu_rev = -1;
 #define IIM_SREV 0x24
-#define MX50_HW_ADADIG_DIGPROG  0xB0
 static int get_mx51_srev(void)
 {
@@ -108,41 +107,3 @@ int mx53_revision(void)
        return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx53_revision);
-static int get_mx50_srev(void)
-{
-        void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
-        u32 rev;
-        if (!anatop) {
-                mx5_cpu_rev = -EINVAL;
-                return 0;
-        }
-        rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
-        rev &= 0xff;
-        iounmap(anatop);
-        if (rev == 0x0)
-                return IMX_CHIP_REVISION_1_0;
-        else if (rev == 0x1)
-                return IMX_CHIP_REVISION_1_1;
-        return 0;
-}
-/*
- * Returns:
- *      the silicon revision of the cpu
- *      -EINVAL - not a mx50
- */
-int mx50_revision(void)
-{
-        if (!cpu_is_mx50())
-                return -EINVAL;
-        if (mx5_cpu_rev == -1)
-                mx5_cpu_rev = get_mx50_srev();
-        return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx50_revision);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
new file mode 100644
index 000000000000..d533e2695f0e
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clockchips.h>
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include "common.h"
+#include "cpuidle.h"
+static atomic_t master = ATOMIC_INIT(0);
+static DEFINE_SPINLOCK(master_lock);
+static int imx6q_enter_wait(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
+{
+        int cpu = dev->cpu;
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
+        if (atomic_inc_return(&master) == num_online_cpus()) {
+                /*
+                 * With this lock, we prevent other cpu to exit and enter
+                 * this function again and become the master.
+                 */
+                if (!spin_trylock(&master_lock))
+                        goto idle;
+                imx6q_set_lpm(WAIT_UNCLOCKED);
+                cpu_do_idle();
+                imx6q_set_lpm(WAIT_CLOCKED);
+                spin_unlock(&master_lock);
+                goto done;
+        }
+idle:
+        cpu_do_idle();
+done:
+        atomic_dec(&master);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
+        return index;
+}
+/*
+ * For each cpu, setup the broadcast timer because local timer
+ * stops for the states other than WFI.
+ */
+static void imx6q_setup_broadcast_timer(void *arg)
+{
+        int cpu = smp_processor_id();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
+}
+static struct cpuidle_driver imx6q_cpuidle_driver = {
+        .name = "imx6q_cpuidle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+        .states = {
+                /* WFI */
+                ARM_CPUIDLE_WFI_STATE,
+                /* WAIT */
+                {
+                        .exit_latency = 50,
+                        .target_residency = 75,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = imx6q_enter_wait,
+                        .name = "WAIT",
+                        .desc = "Clock off",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
+};
+int __init imx6q_cpuidle_init(void)
+{
+        /* Need to enable SCU standby for entering WAIT modes */
+        imx_scu_standby_enable();
+        /* Set chicken bit to get a reliable WAIT mode support */
+        imx6q_set_chicken_bit();
+        /* Configure the broadcast timer on each cpu */
+        on_each_cpu(imx6q_setup_broadcast_timer, NULL, 1);
+        return imx_cpuidle_init(&imx6q_cpuidle_driver);
+}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index bc932d1af372..e092d1359d94 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -14,9 +14,14 @@
 #ifdef CONFIG_CPU_IDLE
 extern int imx_cpuidle_init(struct cpuidle_driver *drv);
+extern int imx6q_cpuidle_init(void);
 #else
 static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
 {
        return -ENODEV;
 }
+static inline int imx6q_cpuidle_init(void)
+{
+        return -ENODEV;
+}
 #endif
diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
deleted file mode 100644
index 2c290391f298..000000000000
--- a/arch/arm/mach-imx/devices-imx50.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include "devices/devices-common.h"
-extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
-#define imx50_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
-extern const struct imx_fec_data imx50_fec_data;
-#define imx50_add_fec(pdata)    \
-        imx_add_fec(&imx50_fec_data, pdata)
-extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
-#define imx50_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 9a8f1ca7bcb1..9b9ba1f4ffe1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
        bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
+        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
 config IMX_HAVE_PLATFORM_FLEXCAN
        bool
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index 2cb188ad9a0a..63eba08f87b1 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
        imx_fec_data_entry_single(MX35, "imx27-fec");
 #endif
-#ifdef CONFIG_SOC_IMX50
-/* i.mx50 has the i.mx25 type fec */
-const struct imx_fec_data imx50_fec_data __initconst =
-        imx_fec_data_entry_single(MX50, "imx25-fec");
-#endif
 #ifdef CONFIG_SOC_IMX51
 /* i.mx51 has the i.mx27 type fec */
 const struct imx_fec_data imx51_fec_data __initconst =
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 8e30e5703cd2..57d342e85c2f 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
-#ifdef CONFIG_SOC_IMX50
-const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
-#define imx50_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx50_imx_i2c_data_entry(0, 1),
-        imx50_imx_i2c_data_entry(1, 2),
-        imx50_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
 #ifdef CONFIG_SOC_IMX51
 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #define imx51_imx_i2c_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 67bf866a2cb6..faac4aa6ca6d 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
-#ifdef CONFIG_SOC_IMX50
-const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
-#define imx50_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
-        imx50_imx_uart_data_entry(0, 1),
-        imx50_imx_uart_data_entry(1, 2),
-        imx50_imx_uart_data_entry(2, 3),
-        imx50_imx_uart_data_entry(3, 4),
-        imx50_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX50 */
 #ifdef CONFIG_SOC_IMX51
 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
 #define imx51_imx_uart_data_entry(_id, _hwid)                           \
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index 04a5961beeac..e02de188ae83 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = {
 static struct clock_event_device clockevent_epit = {
        .name           = "epit",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .set_mode       = epit_set_mode,
        .set_next_event = epit_set_next_event,
        .rating         = 200,
@@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = {
 static int __init epit_clockevent_init(struct clk *timer_clk)
 {
-        unsigned int c = clk_get_rate(timer_clk);
-        clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
-                                        clockevent_epit.shift);
-        clockevent_epit.max_delta_ns =
-                        clockevent_delta2ns(0xfffffffe, &clockevent_epit);
-        clockevent_epit.min_delta_ns =
-                        clockevent_delta2ns(0x800, &clockevent_epit);
        clockevent_epit.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&clockevent_epit,
-        clockevents_register_device(&clockevent_epit);
+                                        clk_get_rate(timer_clk),
+                                        0x800, 0xfffffffe);
        return 0;
 }
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index e1537f9e45b8..a96ccc7f5012 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -15,7 +15,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <asm/hardware/gic.h>
+#include <linux/irqchip/arm-gic.h>
 #define GPC_IMR1                0x008
 #define GPC_PGC_CPU_PDN         0x2a0
@@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d)
 void __init imx_gpc_init(void)
 {
        struct device_node *np;
+        int i;
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
        gpc_base = of_iomap(np, 0);
        WARN_ON(!gpc_base);
+        /* Initially mask all interrupts */
+        for (i = 0; i < IMR_NUM; i++)
+                writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
        /* Register GPC as the secondary interrupt controller behind GIC */
        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 3ce7fa3bd43f..911e9b31b03f 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -72,11 +72,6 @@
 *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
 *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
 *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- * mx50:
- *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
 * mx51:
 *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
 *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
@@ -108,7 +103,6 @@
 #include "mxc.h"
 #include "mx6q.h"
-#include "mx50.h"
 #include "mx51.h"
 #include "mx53.h"
 #include "mx3x.h"
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb128a4..921fc1555854 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -17,53 +17,6 @@
        .section ".text.head", "ax"
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3      @ NumWays - 1
-        add     r2, r2, #1              @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4      @ SetShift
-        clz     r1, r3          @ WayShift
-        add     r4, r3, #1      @ NumWays
-1:      sub     r2, r2, #1      @ NumSets--
-        mov     r3, r4          @ Temp = NumWays
-2:      subs    r3, r3, #1      @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 #ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
        bl      v7_invalidate_l1
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index e17dfbc42192..03b65e5ea541 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -22,15 +22,6 @@ static void __init imx25_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static void __init imx25_timer_init(void)
-{
-        mx25_clocks_init_dt();
-}
-static struct sys_timer imx25_timer = {
-        .init = imx25_timer_init,
-};
 static const char * const imx25_dt_board_compat[] __initconst = {
        "fsl,imx25",
        NULL
@@ -41,7 +32,7 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
        .init_early     = imx25_init_early,
        .init_irq       = mx25_init_irq,
        .handle_irq     = imx25_handle_irq,
-        .timer          = &imx25_timer,
+        .init_time      = imx25_timer_init,
        .init_machine   = imx25_dt_init,
        .dt_compat      = imx25_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index ebfae96543c4..c915a490a11c 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -39,26 +39,22 @@ static void __init imx27_dt_init(void)
                             imx27_auxdata_lookup, NULL);
 }
-static void __init imx27_timer_init(void)
-{
-        mx27_clocks_init_dt();
-}
-static struct sys_timer imx27_timer = {
-        .init = imx27_timer_init,
-};
 static const char * const imx27_dt_board_compat[] __initconst = {
        "fsl,imx27",
        NULL
 };
+static void __init imx27_timer_init(void)
+{
+        mx27_clocks_init_dt();
+}
 DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
        .map_io         = mx27_map_io,
        .init_early     = imx27_init_early,
        .init_irq       = mx27_init_irq,
        .handle_irq     = imx27_handle_irq,
-        .timer          = &imx27_timer,
+        .init_time      = imx27_timer_init,
        .init_machine   = imx27_dt_init,
        .dt_compat      = imx27_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index af476de2570e..67de611e29ab 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -18,46 +18,27 @@
 #include "common.h"
 #include "mx31.h"
-static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
-                        "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
-                        "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
-                        "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
-                        "imx21-uart.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
-                        "imx21-uart.4", NULL),
-        { /* sentinel */ }
-};
 static void __init imx31_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-                             imx31_auxdata_lookup, NULL);
-}
-static void __init imx31_timer_init(void)
-{
-        mx31_clocks_init_dt();
 }
-static struct sys_timer imx31_timer = {
-        .init = imx31_timer_init,
-};
 static const char *imx31_dt_board_compat[] __initdata = {
        "fsl,imx31",
        NULL
 };
+static void __init imx31_dt_timer_init(void)
+{
+        mx31_clocks_init_dt();
+}
 DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
        .map_io         = mx31_map_io,
        .init_early     = imx31_init_early,
        .init_irq       = mx31_init_irq,
        .handle_irq     = imx31_handle_irq,
-        .timer          = &imx31_timer,
+        .init_time      = imx31_dt_timer_init,
        .init_machine   = imx31_dt_init,
        .dt_compat      = imx31_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5ffa40c673f8..e2926a8863f8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -24,26 +24,22 @@ static void __init imx51_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static void __init imx51_timer_init(void)
-{
-        mx51_clocks_init_dt();
-}
-static struct sys_timer imx51_timer = {
-        .init = imx51_timer_init,
-};
 static const char *imx51_dt_board_compat[] __initdata = {
        "fsl,imx51",
        NULL
 };
+static void __init imx51_timer_init(void)
+{
+        mx51_clocks_init_dt();
+}
 DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
        .map_io         = mx51_map_io,
        .init_early     = imx51_init_early,
        .init_irq       = mx51_init_irq,
        .handle_irq     = imx51_handle_irq,
-        .timer          = &imx51_timer,
+        .init_time      = imx51_timer_init,
        .init_machine   = imx51_dt_init,
        .init_late      = imx51_init_late,
        .dt_compat      = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h
deleted file mode 100644
index 00f56e0e8009..000000000000
--- a/arch/arm/mach-imx/iomux-mx50.h
+++ /dev/null
@@ -1,977 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __MACH_IOMUX_MX50_H__
-#define __MACH_IOMUX_MX50_H__
-#include "iomux-v3.h"
-#define MX50_ELCDIF_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_SD_PAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
-#define MX50_UART_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
-#define MX50_I2C_PAD_CTRL       (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
-#define MX50_USB_PAD_CTRL       (PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
-#define MX50_FEC_PAD_CTRL       (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
-                                        PAD_CTL_DSE_HIGH)
-#define MX50_OWIRE_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
-                                        PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX50_KEYPAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
-#define MX50_CSPI_SS_PAD        (PAD_CTL_PKE | PAD_CTL_PUE | \
-                                        PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_COL0__KEY_COL0     IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__GPIO_4_0     IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL0__NANDF_CLE    IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_ROW0__KEY_ROW0     IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW0__GPIO_4_1     IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW0__NANDF_ALE    IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_COL1__KEY_COL1     IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__GPIO_4_2     IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL1__NANDF_CE0    IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_ROW1__KEY_ROW1     IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW1__GPIO_4_3     IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW1__NANDF_CE1    IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_COL2__KEY_COL2     IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_COL2__GPIO_4_4     IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL2__NANDF_CE2    IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_ROW2__KEY_ROW2     IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW2__GPIO_4_5     IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW2__NANDF_CE3    IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__GPIO_4_6     IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_COL3__NANDF_READY  IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
-                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_KEY_COL3__SDMA_EXT0    IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__KEY_ROW3     IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
-#define MX50_PAD_KEY_ROW3__GPIO_4_7     IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_KEY_ROW3__NANDF_DQS    IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_KEY_ROW3__SDMA_EXT1    IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__I2C1_SCL     IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__GPIO_6_18    IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__I2C1_SDA     IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__GPIO_6_19    IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SDA__UART2_RXD    IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__I2C2_SCL     IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__GPIO_6_20    IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__DCDC_OK      IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__I2C2_SDA     IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__GPIO_6_21    IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__UART2_RTS    IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_I2C2_SDA__PWRSTABLE    IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__I2C3_SCL     IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPIO_6_22    IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__FEC_MDC      IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_I2C3_SCL__PMIC_RDY     IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__GPT_CAPIN1   IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SCL__USBOTG_OC    IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__I2C3_SDA     IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                                MX50_I2C_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPIO_6_23    IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__FEC_MDIO     IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__PWRFAIL_INT  IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__ALARM_DEB    IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__GPT_CAPIN1   IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C3_SDA__USBOTG_PWR   IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_PWM1__PWM1_PWMO        IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__GPIO_6_24        IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM1__USBOTG_OC        IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
-#define MX50_PAD_PWM1__GPT_CMPOUT1      IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__PWM2_PWMO        IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPIO_6_25        IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__USBOTG_PWR       IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_PWM2__DCDC_PWM         IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__GPT_CMPOUT2      IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PWM2__ANY_PU_RST       IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__OWIRE           IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPIO_6_26       IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__USBH1_OC        IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
-#define MX50_PAD_OWIRE__SSI_EXT1_CLK    IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__EPDC_PWRIRQ     IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_OWIRE__GPT_CMPOUT3     IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__EPITO           IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPIO_6_27       IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__USBH1_PWR       IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
-                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EPITO__SSI_EXT2_CLK    IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__TOG_EN          IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPITO__GPT_CLKIN       IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__WDOG             IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__GPIO_6_28        IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__WDOG_RST         IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_WDOG__XTAL32K          IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__SSI_TXFS     IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXFS__GPIO_6_0     IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__SSI_TXC       IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXC__GPIO_6_1      IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__SSI_TXD       IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__GPIO_6_2      IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_TXD__CSPI_RDY      IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__SSI_RXD       IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__GPIO_6_3      IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXD__CSPI_SS3      IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_SSI_RXFS__AUD3_RXFS    IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__GPIO_6_4     IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__WEIM_D6      IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__CSPI_SS2     IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_SSI_RXFS__FEC_COL      IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SSI_RXFS__FEC_MDC      IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SSI_RXC__AUD3_RXC      IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__GPIO_6_5      IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__UART5_RXD     IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__WEIM_D7       IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__CSPI_SS1      IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_SSI_RXC__FEC_RX_CLK    IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXC__FEC_MDIO      IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_TXD__GPIO_6_6    IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RXD__GPIO_6_7    IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__GPIO_6_8    IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__SD4_D4      IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__SD4_CMD     IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__GPIO_6_9    IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__UART5_RXD   IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__GPIO_6_10   IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__SD4_D6      IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_TXD__SD4_D4      IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__GPIO_6_11   IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__SD4_D7      IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RXD__SD4_D5      IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__GPIO_6_12   IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__SD4_CMD     IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_CTS__SD4_D6      IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__GPIO_6_13   IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__SD4_CLK     IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART2_RTS__SD4_D7      IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__GPIO_6_14   IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD1_D4      IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD4_D0      IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__SD2_WP      IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_TXD__WEIM_D12    IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__UART3_RXD   IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__GPIO_6_15   IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD1_D5      IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD4_D1      IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__SD2_CD      IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART3_RXD__WEIM_D13    IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__GPIO_6_16   IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD1_D6      IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD4_D2      IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__SD2_LCTL    IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__WEIM_D14    IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__UART4_RXD   IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__GPIO_6_17   IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__UART3_RTS   IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD1_D7      IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD4_D3      IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__SD1_LCTL    IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART4_RXD__WEIM_D15    IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SCLK__CSPI_SCLK   IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SCLK__GPIO_4_8    IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MOSI__CSPI_MOSI   IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MOSI__GPIO_4_9    IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MISO__CSPI_MISO   IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_MISO__GPIO_4_10   IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_CSPI_SS0__CSPI_SS0     IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_CSPI_SS0__GPIO_4_11    IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12         IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY          IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY        IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__UART3_RTS         IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6        IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SCLK__WEIM_D8           IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13         IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1          IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1        IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7        IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MOSI__WEIM_D9           IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__GPIO_4_14         IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__CSPI_SS2          IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2        IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MISO__UART4_RTS         IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8        IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_MISO__WEIM_D10          IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__GPIO_4_15          IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_ECSPI1_SS0__CSPI_SS3           IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3         IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9         IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI1_SS0__WEIM_D11           IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK       IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16         IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR         IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY        IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__UART5_RTS         IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK     IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4        IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SCLK__WEIM_D8           IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI       IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17         IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD         IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1        IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN         IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5        IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MOSI__WEIM_D9           IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__GPIO_4_18         IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS         IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2        IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6        IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__WEIM_D10          IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0         IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_SS0__GPIO_4_19          IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS          IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3         IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_SS0__UART5_RXD          IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC       IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7         IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_ECSPI2_SS0__WEIM_D11           IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__GPIO_5_0      IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CLK__CLKO          IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__GPIO_5_1      IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_CMD__CLKO2         IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D0__SD1_D0         IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D0__GPIO_5_2       IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D0__PLL1_BYP       IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D1__SD1_D1         IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D1__GPIO_5_3       IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D1__PLL2_BYP       IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D2__SD1_D2         IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D2__GPIO_5_4       IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D2__PLL3_BYP       IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD1_D3__SD1_D3         IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD1_D3__GPIO_5_5       IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__SD2_CLK       IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__GPIO_5_6      IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CLK__MSHC_SCLK     IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__SD2_CMD       IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__GPIO_5_7      IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CMD__MSHC_BS       IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D0__SD2_D0         IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D0__GPIO_5_8       IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D0__MSHC_D0        IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D0__KEY_COL4       IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__SD2_D1         IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D1__GPIO_5_9       IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D1__MSHC_D1        IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D1__KEY_ROW4       IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__SD2_D2         IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D2__GPIO_5_10      IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D2__MSHC_D2        IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D2__KEY_COL5       IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__SD2_D3         IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D3__GPIO_5_11      IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D3__MSHC_D3        IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D3__KEY_ROW5       IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__SD2_D4         IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D4__GPIO_5_12      IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__AUD4_RXFS      IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__KEY_COL6       IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__WEIM_D0        IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D4__CCM_OUT0       IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__SD2_D5         IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D5__GPIO_5_13      IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__AUD4_RXC       IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__KEY_ROW6       IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__WEIM_D1        IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D5__CCM_OUT1       IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__SD2_D6         IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D6__GPIO_5_14      IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__AUD4_RXD       IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__KEY_COL7       IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__WEIM_D2        IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D6__CCM_OUT2       IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__SD2_D7         IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_D7__GPIO_5_15      IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__AUD4_TXFS      IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__KEY_ROW7       IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__WEIM_D3        IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_D7__CCM_STOP       IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__SD2_WP         IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_WP__GPIO_5_16      IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__AUD4_TXD       IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__WEIM_D4        IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_WP__CCM_WAIT       IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__SD2_CD         IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD2_CD__GPIO_5_17      IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__AUD4_TXC       IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__WEIM_D5        IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD2_CD__CCM_REF_EN     IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B       IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1       IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B       IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0       IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS   IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD   IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB       IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI   IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK   IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO   IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__DISP_D0       IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D0__GPIO_2_0      IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D0__FEC_TXCLK     IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D1__DISP_D1       IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D1__GPIO_2_1      IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D1__FEC_RX_ER     IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D1__WEIM_A17      IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__DISP_D2       IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D2__GPIO_2_2      IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D2__FEC_RX_DV     IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D2__WEIM_A18      IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__DISP_D3       IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D3__GPIO_2_3      IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_RXD1      IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D3__WEIM_A19      IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D3__FEC_COL       IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__DISP_D4       IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D4__GPIO_2_4      IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D4__FEC_RXD0      IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX50_PAD_DISP_D4__WEIM_A20      IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__DISP_D5       IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D5__GPIO_2_5      IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D5__FEC_TX_EN     IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D5__WEIM_A21      IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__DISP_D6       IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D6__GPIO_2_6      IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_TXD1      IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D6__WEIM_A22      IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D6__FEC_RX_CLK    IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__DISP_D7       IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D7__GPIO_2_7      IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D7__FEC_TXD0      IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_DISP_D7__WEIM_A23      IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__ELCDIF_WR     IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_WR__GPIO_2_16     IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_WR__WEIM_A24      IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__ELCDIF_RD     IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RD__GPIO_2_19     IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RD__ELCDIF_EN     IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RD__WEIM_A25      IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RS__GPIO_2_17     IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RS__ELCDIF_VSYNC  IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RS__WEIM_A26      IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__ELCDIF_CS     IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_CS__GPIO_2_21     IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__ELCDIF_HSYNC  IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_CS__WEIM_A27      IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_CS__WEIM_CS3      IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC        IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__GPIO_2_18           IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_BUSY__WEIM_CS3            IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__GPIO_2_20  IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_RESET__WEIM_CS3   IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__SD3_CMD       IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_CMD__GPIO_5_18     IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_CMD__NANDF_WRN     IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_CMD__SSP_CMD       IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__SD3_CLK       IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_CLK__GPIO_5_19     IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_CLK__NANDF_RDN     IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_CLK__SSP_CLK       IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__SD3_D0         IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D0__GPIO_5_20      IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D0__NANDF_D4       IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D0__SSP_D0         IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D0__PLL1_BYP       IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D1__SD3_D1         IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D1__GPIO_5_21      IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D1__NANDF_D5       IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D1__PLL2_BYP       IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__SD3_D2         IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D2__GPIO_5_22      IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D2__NANDF_D6       IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D2__SSP_D2         IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D2__PLL3_BYP       IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D3__SD3_D3         IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D3__GPIO_5_23      IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D3__NANDF_D7       IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D3__SSP_D3         IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D4__SD3_D4         IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D4__GPIO_5_24      IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D4__NANDF_D0       IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D4__SSP_D4         IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D5__SD3_D5         IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D5__GPIO_5_25      IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D5__NANDF_D1       IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D5__SSP_D5         IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D6__SD3_D6         IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D6__GPIO_5_26      IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D6__NANDF_D2       IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D6__SSP_D6         IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_D7__SD3_D7         IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_D7__GPIO_5_27      IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_D7__NANDF_D3       IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_D7__SSP_D7         IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__SD3_WP         IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_WP__GPIO_5_28      IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_SD3_WP__NANDF_RESETN   IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_SD3_WP__SSP_CD         IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SD3_WP__SD4_LCTL       IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_SD3_WP__WEIM_CS3       IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__DISP_D8       IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D8__GPIO_2_8      IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__NANDF_CLE     IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__SD1_LCTL      IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D8__SD4_CMD       IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D8__KEY_COL4      IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D8__FEC_TX_CLK    IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__DISP_D9       IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D9__GPIO_2_9      IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__NANDF_ALE     IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__SD2_LCTL      IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D9__SD4_CLK       IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D9__KEY_ROW4      IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D9__FEC_RX_ER     IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__DISP_D10     IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D10__GPIO_2_10    IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__NANDF_CEN0   IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__SD3_LCTL     IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D10__SD4_D0       IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D10__KEY_COL5     IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D10__FEC_RX_DV    IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__DISP_D11     IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D11__GPIO_2_11    IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__NANDF_CEN1   IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__SD4_D1       IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D11__KEY_ROW5     IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D11__FEC_RDAT1    IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__DISP_D12     IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D12__GPIO_2_12    IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__NANDF_CEN2   IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__SD1_CD       IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D12__SD4_D2       IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D12__KEY_COL6     IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D12__FEC_RDAT0    IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__DISP_D13     IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D13__GPIO_2_13    IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__NANDF_CEN3   IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__SD3_CD       IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D13__SD4_D3       IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D13__KEY_ROW6     IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D13__FEC_TX_EN    IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__DISP_D14     IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D14__GPIO_2_14    IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__NANDF_RDY0   IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__SD1_WP       IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D14__SD4_WP       IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D14__KEY_COL7     IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D14__FEC_TDAT1    IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__DISP_D15     IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_DISP_D15__GPIO_2_15    IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__NANDF_DQS    IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__SD3_RST      IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D15__SD4_CD       IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
-#define MX50_PAD_DISP_D15__KEY_ROW7     IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
-#define MX50_PAD_DISP_D15__FEC_TDAT0    IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__EPDC_D0       IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__GPIO_3_0      IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__WEIM_D0       IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_RS     IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__EPDC_D1       IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__GPIO_3_1      IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__WEIM_D1       IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_CS     IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D1__ELCDIF_EN     IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__EPDC_D2       IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__GPIO_3_2      IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__WEIM_D2       IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_WR     IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC  IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__EPDC_D3       IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__GPIO_3_3      IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__WEIM_D3       IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_RD     IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC  IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__EPDC_D4       IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__GPIO_3_4      IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D4__WEIM_D4       IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__EPDC_D5       IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__GPIO_3_5      IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D5__WEIM_D5       IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__EPDC_D6       IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__GPIO_3_6      IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D6__WEIM_D6       IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__EPDC_D7       IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__GPIO_3_7      IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D7__WEIM_D7       IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__EPDC_D8       IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__GPIO_3_8      IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__WEIM_D8       IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D8__ELCDIF_D24    IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__EPDC_D9       IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__GPIO_3_9      IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__EPDC_D10     IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__GPIO_3_10    IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__WEIM_D10     IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D10__ELCDIF_D26   IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__EPDC_D11     IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__GPIO_3_11    IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__WEIM_D11     IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D11__ELCDIF_D27   IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__EPDC_D12     IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__GPIO_3_12    IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__WEIM_D12     IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D12__ELCDIF_D28   IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__EPDC_D13     IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__GPIO_3_13    IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__WEIM_D13     IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D13__ELCDIF_D29   IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__EPDC_D14     IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__GPIO_3_14    IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__WEIM_D14     IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__ELCDIF_D30   IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D14__AUD6_TXD     IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__EPDC_D15     IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__GPIO_3_15    IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__WEIM_D15     IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__ELCDIF_D31   IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_D15__AUD6_TXC     IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__GPIO_3_16  IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__WEIM_D16   IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS  IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__EPDC_GDSP   IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__GPIO_3_17   IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__WEIM_D17    IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__ELCDIF_D17  IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDSP__AUD6_RXD    IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__EPDC_GDOE   IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__GPIO_3_18   IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__WEIM_D18    IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__ELCDIF_D18  IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDOE__AUD6_RXC    IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__EPDC_GDRL   IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__GPIO_3_19   IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__WEIM_D19    IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__ELCDIF_D19  IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_GDRL__AUD6_RXFS   IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__GPIO_3_20  IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__WEIM_D20   IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLK__AUD5_TXD   IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21  IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__WEIM_D21   IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC   IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__GPIO_3_22  IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__WEIM_D22   IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOED__AUD5_TXFS  IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__EPDC_SDOE   IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__GPIO_3_23   IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__WEIM_D23    IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__ELCDIF_D23  IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDOE__AUD5_RXD    IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__EPDC_SDLE   IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__GPIO_3_24   IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__WEIM_D24    IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__ELCDIF_D8   IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDLE__AUD5_RXC    IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN       IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25         IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__WEIM_D25          IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9         IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS         IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__GPIO_3_26  IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__WEIM_D26   IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDSHR__AUD4_TXD   IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM       IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27         IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__WEIM_D27          IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11        IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC          IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT     IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28        IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28         IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12       IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS        IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0   IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29       IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29        IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13      IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD        IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1   IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30       IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30        IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14      IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC        IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2   IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31       IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31        IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15      IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS       IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0       IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3        IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20       IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2        IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1       IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__GPIO_4_21  IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM0__WEIM_EB3   IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__GPIO_4_22  IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_VCOM1__WEIM_CS3   IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__EPDC_BDR0   IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__GPIO_4_23   IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR0__ELCDIF_D7   IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__EPDC_BDR1   IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__GPIO_4_24   IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_BDR1__ELCDIF_D6   IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__GPIO_4_25  IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5  IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__GPIO_4_26  IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4  IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2         IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__GPIO_4_27          IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3        IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__GPIO_4_28  IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2  IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__GPIO_4_29  IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1  IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__GPIO_4_30  IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0  IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__WEIM_A0       IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__GPIO_1_0      IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA0__KEY_COL4      IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__WEIM_A1       IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__GPIO_1_1      IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA1__KEY_ROW4      IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
-#define MX50_PAD_EIM_DA2__WEIM_A2       IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__GPIO_1_2      IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA2__KEY_COL5      IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__WEIM_A3       IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__GPIO_1_3      IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA3__KEY_ROW5      IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
-#define MX50_PAD_EIM_DA4__WEIM_A4       IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__GPIO_1_4      IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA4__KEY_COL6      IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__WEIM_A5       IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__GPIO_1_5      IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA5__KEY_ROW6      IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
-#define MX50_PAD_EIM_DA6__WEIM_A6       IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__GPIO_1_6      IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA6__KEY_COL7      IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__WEIM_A7       IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__GPIO_1_7      IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA7__KEY_ROW7      IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
-#define MX50_PAD_EIM_DA8__WEIM_A8       IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA8__GPIO_1_8      IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA8__NANDF_CLE     IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA9__WEIM_A9       IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA9__GPIO_1_9      IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA9__NANDF_ALE     IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA10__WEIM_A10     IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA10__GPIO_1_10    IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA10__NANDF_CE0    IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA11__WEIM_A11     IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA11__GPIO_1_11    IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA11__NANDF_CE1    IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA12__WEIM_A12     IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA12__GPIO_1_12    IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA12__NANDF_CE2    IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA12__EPDC_SDCE6   IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__WEIM_A13     IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA13__GPIO_1_13    IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA13__NANDF_CE3    IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
-#define MX50_PIN_EIM_DA13__EPDC_SDCE7   IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__WEIM_A14     IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__GPIO_1_14    IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA14__NANDF_READY  IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
-                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define MX50_PAD_EIM_DA14__EPDC_SDCE8   IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__WEIM_A15     IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_DA15__GPIO_1_15    IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PIN_EIM_DA15__NANDF_DQS    IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
-#define MX50_PAD_EIM_DA15__EPDC_SDCE9   IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__WEIM_CS2      IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__GPIO_1_16     IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS2__WEIM_A27      IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__WEIM_CS1      IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS1__GPIO_1_17     IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__WEIM_CS0      IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CS0__GPIO_1_18     IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__WEIM_EB0      IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB0__GPIO_1_19     IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__WEIM_EB1      IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_EB1__GPIO_1_20     IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__WEIM_WAIT    IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_WAIT__GPIO_1_21    IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__WEIM_BCLK    IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_BCLK__GPIO_1_22    IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__WEIM_RDY      IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RDY__GPIO_1_23     IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__WEIM_OE        IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_OE__GPIO_1_24      IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__WEIM_RW        IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_RW__GPIO_1_25      IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__WEIM_LBA      IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_LBA__GPIO_1_26     IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CRE__WEIM_CRE      IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EIM_CRE__GPIO_1_27     IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
-#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
deleted file mode 100644
index 2fdc9bf2fb5e..000000000000
--- a/arch/arm/mach-imx/lluart.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-#include "hardware.h"
-#define IMX6Q_UART1_BASE_ADDR   0x02020000
-#define IMX6Q_UART2_BASE_ADDR   0x021e8000
-#define IMX6Q_UART3_BASE_ADDR   0x021ec000
-#define IMX6Q_UART4_BASE_ADDR   0x021f0000
-#define IMX6Q_UART5_BASE_ADDR   0x021f4000
-/*
- * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
- * of IMX6Q_UART##n##_BASE_ADDR.
- */
-#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
-#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
-#define IMX6Q_DEBUG_UART_BASE   IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
-static struct map_desc imx_lluart_desc = {
-#ifdef CONFIG_DEBUG_IMX6Q_UART
-        .virtual        = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
-        .pfn            = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
-        .length         = 0x4000,
-        .type           = MT_DEVICE,
-#endif
-};
-void __init imx_lluart_map_io(void)
-{
-        if (imx_lluart_desc.virtual)
-                iotable_init(&imx_lluart_desc, 1);
-}
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 5c9bd2c66e6d..067580b2969b 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -137,17 +137,13 @@ static void __init apf9328_timer_init(void)
        mx1_clocks_init(32768);
 }
-static struct sys_timer apf9328_timer = {
-        .init   = apf9328_timer_init,
-};
 MACHINE_START(APF9328, "Armadeus APF9328")
        /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
        .map_io       = mx1_map_io,
        .init_early   = imx1_init_early,
        .init_irq     = mx1_init_irq,
        .handle_irq   = imx1_handle_irq,
-        .timer        = &apf9328_timer,
+        .init_time      = apf9328_timer_init,
        .init_machine = apf9328_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 59bd6b06a6b5..368a6e3f5926 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -557,10 +557,6 @@ static void __init armadillo5x0_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer armadillo5x0_timer = {
-        .init   = armadillo5x0_timer_init,
-};
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        /* Maintainer: Alberto Panizzo  */
        .atag_offset = 0x100,
@@ -568,7 +564,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &armadillo5x0_timer,
+        .init_time      = armadillo5x0_timer_init,
        .init_machine = armadillo5x0_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 3a39d5aec07a..2d00476f7d2c 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -53,16 +53,12 @@ static void __init bug_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer bug_timer = {
-        .init = bug_timer_init,
-};
 MACHINE_START(BUG, "BugLabs BUGBase")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &bug_timer,
+        .init_time      = bug_timer_init,
        .init_machine = bug_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 12a370646b45..146559311bd2 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -309,17 +309,13 @@ static void __init eukrea_cpuimx27_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer eukrea_cpuimx27_timer = {
-        .init = eukrea_cpuimx27_timer_init,
-};
 MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
        .atag_offset = 0x100,
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &eukrea_cpuimx27_timer,
+        .init_time      = eukrea_cpuimx27_timer_init,
        .init_machine = eukrea_cpuimx27_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 5a31bf8c8f4c..771362d1fbee 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -193,10 +193,6 @@ static void __init eukrea_cpuimx35_timer_init(void)
        mx35_clocks_init();
 }
-static struct sys_timer eukrea_cpuimx35_timer = {
-        .init   = eukrea_cpuimx35_timer_init,
-};
 MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        /* Maintainer: Eukrea Electromatique */
        .atag_offset = 0x100,
@@ -204,7 +200,7 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
        .handle_irq = imx35_handle_irq,
-        .timer = &eukrea_cpuimx35_timer,
+        .init_time      = eukrea_cpuimx35_timer_init,
        .init_machine = eukrea_cpuimx35_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index b727de029c8f..9b7393234f6f 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -355,10 +355,6 @@ static void __init eukrea_cpuimx51sd_timer_init(void)
        mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
-static struct sys_timer mxc_timer = {
-        .init   = eukrea_cpuimx51sd_timer_init,
-};
 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
        /* Maintainer: Eric Bénard <eric@eukrea.com> */
        .atag_offset = 0x100,
@@ -366,7 +362,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
        .handle_irq = imx51_handle_irq,
-        .timer = &mxc_timer,
+        .init_time      = eukrea_cpuimx51sd_timer_init,
        .init_machine = eukrea_cpuimx51sd_init,
        .init_late      = imx51_init_late,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 75027a5ad8b7..4bf454424249 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -159,10 +159,6 @@ static void __init eukrea_cpuimx25_timer_init(void)
        mx25_clocks_init();
 }
-static struct sys_timer eukrea_cpuimx25_timer = {
-        .init   = eukrea_cpuimx25_timer_init,
-};
 MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        /* Maintainer: Eukrea Electromatique */
        .atag_offset = 0x100,
@@ -170,7 +166,7 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
        .handle_irq = imx25_handle_irq,
-        .timer = &eukrea_cpuimx25_timer,
+        .init_time = eukrea_cpuimx25_timer_init,
        .init_machine = eukrea_cpuimx25_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 318bd8df7fcc..29ac8ee651d2 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -598,10 +598,6 @@ static void __init visstrim_m10_timer_init(void)
        mx27_clocks_init((unsigned long)25000000);
 }
-static struct sys_timer visstrim_m10_timer = {
-        .init   = visstrim_m10_timer_init,
-};
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
        .atag_offset = 0x100,
        .reserve = visstrim_reserve,
@@ -609,7 +605,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &visstrim_m10_timer,
+        .init_time      = visstrim_m10_timer_init,
        .init_machine = visstrim_m10_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 53a860112938..1a851aea6832 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -65,10 +65,6 @@ static void __init mx27ipcam_timer_init(void)
        mx27_clocks_init(25000000);
 }
-static struct sys_timer mx27ipcam_timer = {
-        .init   = mx27ipcam_timer_init,
-};
 MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
        /* maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -76,7 +72,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &mx27ipcam_timer,
+        .init_time      = mx27ipcam_timer_init,
        .init_machine = mx27ipcam_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index fc8dce931378..3da2e3e44ce9 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -72,17 +72,13 @@ static void __init mx27lite_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer mx27lite_timer = {
-        .init   = mx27lite_timer_init,
-};
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
        .atag_offset = 0x100,
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &mx27lite_timer,
+        .init_time      = mx27lite_timer_init,
        .init_machine = mx27lite_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 860284dea0e7..f579c616feed 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -44,26 +44,22 @@ static void __init imx53_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static void __init imx53_timer_init(void)
-{
-        mx53_clocks_init_dt();
-}
-static struct sys_timer imx53_timer = {
-        .init = imx53_timer_init,
-};
 static const char *imx53_dt_board_compat[] __initdata = {
        "fsl,imx53",
        NULL
 };
+static void __init imx53_timer_init(void)
+{
+        mx53_clocks_init_dt();
+}
 DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
        .map_io         = mx53_map_io,
        .init_early     = imx53_init_early,
        .init_irq       = mx53_init_irq,
        .handle_irq     = imx53_handle_irq,
-        .timer          = &imx53_timer,
+        .init_time      = imx53_timer_init,
        .init_machine   = imx53_dt_init,
        .init_late      = imx53_init_late,
        .dt_compat      = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4eb1b3ac794c..9ffd103b27e4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,25 +12,26 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/cpuidle.h>
+#include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/opp.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
-#include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -201,37 +202,91 @@ static void __init imx6q_init_machine(void)
        imx6q_1588_init();
 }
-static struct cpuidle_driver imx6q_cpuidle_driver = {
+#define OCOTP_CFG3                      0x440
-        .name                   = "imx6q_cpuidle",
+#define OCOTP_CFG3_SPEED_SHIFT          16
-        .owner                  = THIS_MODULE,
+#define OCOTP_CFG3_SPEED_1P2GHZ         0x3
-        .en_core_tk_irqen       = 1,
-        .states[0]              = ARM_CPUIDLE_WFI_STATE,
+static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
-        .state_count            = 1,
+{
+        struct device_node *np;
+        void __iomem *base;
+        u32 val;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
+        if (!np) {
+                pr_warn("failed to find ocotp node\n");
+                return;
+        }
+        base = of_iomap(np, 0);
+        if (!base) {
+                pr_warn("failed to map ocotp\n");
+                goto put_node;
+        }
+        val = readl_relaxed(base + OCOTP_CFG3);
+        val >>= OCOTP_CFG3_SPEED_SHIFT;
+        if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+                if (opp_disable(cpu_dev, 1200000000))
+                        pr_warn("failed to disable 1.2 GHz OPP\n");
+put_node:
+        of_node_put(np);
+}
+static void __init imx6q_opp_init(struct device *cpu_dev)
+{
+        struct device_node *np;
+        np = of_find_node_by_path("/cpus/cpu@0");
+        if (!np) {
+                pr_warn("failed to find cpu0 node\n");
+                return;
+        }
+        cpu_dev->of_node = np;
+        if (of_init_opp_table(cpu_dev)) {
+                pr_warn("failed to init OPP table\n");
+                goto put_node;
+        }
+        imx6q_opp_check_1p2ghz(cpu_dev);
+put_node:
+        of_node_put(np);
+}
+struct platform_device imx6q_cpufreq_pdev = {
+        .name = "imx6q-cpufreq",
 };
 static void __init imx6q_init_late(void)
 {
-        imx_cpuidle_init(&imx6q_cpuidle_driver);
+        /*
+         * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
+         * to run cpuidle on them.
+         */
+        if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
+                imx6q_cpuidle_init();
+        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
+                imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
+                platform_device_register(&imx6q_cpufreq_pdev);
+        }
 }
 static void __init imx6q_map_io(void)
 {
-        imx_lluart_map_io();
+        debug_ll_io_init();
        imx_scu_map_io();
-        imx6q_clock_map_io();
 }
-static const struct of_device_id imx6q_irq_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { /* sentinel */ }
-};
 static void __init imx6q_init_irq(void)
 {
        l2x0_of_init(0, ~0UL);
        imx_src_init();
        imx_gpc_init();
-        of_irq_init(imx6q_irq_match);
+        irqchip_init();
 }
 static void __init imx6q_timer_init(void)
@@ -241,10 +296,6 @@ static void __init imx6q_timer_init(void)
        imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 }
-static struct sys_timer imx6q_timer = {
-        .init = imx6q_timer_init,
-};
 static const char *imx6q_dt_compat[] __initdata = {
        "fsl,imx6q",
        NULL,
@@ -254,8 +305,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
        .smp            = smp_ops(imx_smp_ops),
        .map_io         = imx6q_map_io,
        .init_irq       = imx6q_init_irq,
-        .handle_irq     = imx6q_handle_irq,
+        .init_time      = imx6q_timer_init,
-        .timer          = &imx6q_timer,
        .init_machine   = imx6q_init_machine,
        .init_late      = imx6q_init_late,
        .dt_compat      = imx6q_dt_compat,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 2e536ea53444..c7bc41d6b468 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -284,17 +284,13 @@ static void __init kzm_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer kzm_timer = {
-        .init = kzm_timer_init,
-};
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
        .atag_offset = 0x100,
        .map_io = kzm_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &kzm_timer,
+        .init_time      = kzm_timer_init,
        .init_machine = kzm_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 06b483783e68..9f883e4d6fc9 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -132,10 +132,6 @@ static void __init mx1ads_timer_init(void)
        mx1_clocks_init(32000);
 }
-static struct sys_timer mx1ads_timer = {
-        .init   = mx1ads_timer_init,
-};
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
        /* Maintainer: Sascha Hauer, Pengutronix */
        .atag_offset = 0x100,
@@ -143,7 +139,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
        .handle_irq = imx1_handle_irq,
-        .timer = &mx1ads_timer,
+        .init_time      = mx1ads_timer_init,
        .init_machine = mx1ads_init,
        .restart        = mxc_restart,
 MACHINE_END
@@ -154,7 +150,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
        .handle_irq = imx1_handle_irq,
-        .timer = &mx1ads_timer,
+        .init_time      = mx1ads_timer_init,
        .init_machine = mx1ads_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 6adb3136bb08..a06aa4dc37fc 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -318,10 +318,6 @@ static void __init mx21ads_timer_init(void)
        mx21_clocks_init(32768, 26000000);
 }
-static struct sys_timer mx21ads_timer = {
-        .init   = mx21ads_timer_init,
-};
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        /* maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -329,7 +325,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        .init_early = imx21_init_early,
        .init_irq = mx21_init_irq,
        .handle_irq = imx21_handle_irq,
-        .timer = &mx21ads_timer,
+        .init_time      = mx21ads_timer_init,
        .init_machine = mx21ads_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index b1b03aa55bb8..8bcda688a006 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -257,10 +257,6 @@ static void __init mx25pdk_timer_init(void)
        mx25_clocks_init();
 }
-static struct sys_timer mx25pdk_timer = {
-        .init   = mx25pdk_timer_init,
-};
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -268,7 +264,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
        .handle_irq = imx25_handle_irq,
-        .timer = &mx25pdk_timer,
+        .init_time      = mx25pdk_timer_init,
        .init_machine = mx25pdk_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index d0e547fa925f..25b3e4c9bc0a 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -538,10 +538,6 @@ static void __init mx27pdk_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer mx27pdk_timer = {
-        .init   = mx27pdk_timer_init,
-};
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        /* maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -549,7 +545,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &mx27pdk_timer,
+        .init_time      = mx27pdk_timer_init,
        .init_machine = mx27pdk_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 3d036f57f0e6..9821b824dcaf 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -323,10 +323,6 @@ static void __init mx27ads_timer_init(void)
        mx27_clocks_init(fref);
 }
-static struct sys_timer mx27ads_timer = {
-        .init   = mx27ads_timer_init,
-};
 static struct map_desc mx27ads_io_desc[] __initdata = {
        {
                .virtual = PBC_BASE_ADDRESS,
@@ -349,7 +345,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &mx27ads_timer,
+        .init_time      = mx27ads_timer_init,
        .init_machine = mx27ads_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index bc301befdd06..1ed916175d41 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -762,10 +762,6 @@ static void __init mx31_3ds_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer mx31_3ds_timer = {
-        .init   = mx31_3ds_timer_init,
-};
 static void __init mx31_3ds_reserve(void)
 {
        /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
@@ -780,7 +776,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &mx31_3ds_timer,
+        .init_time      = mx31_3ds_timer_init,
        .init_machine = mx31_3ds_init,
        .reserve = mx31_3ds_reserve,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 8b56f8883f32..daf8889125cc 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -576,10 +576,6 @@ static void __init mx31ads_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer mx31ads_timer = {
-        .init   = mx31ads_timer_init,
-};
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -587,7 +583,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
        .init_early = imx31_init_early,
        .init_irq = mx31ads_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &mx31ads_timer,
+        .init_time      = mx31ads_timer_init,
        .init_machine = mx31ads_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 08b9965c8b36..832b1e2f964e 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -303,17 +303,13 @@ static void __init mx31lilly_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer mx31lilly_timer = {
-        .init   = mx31lilly_timer_init,
-};
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
        .atag_offset = 0x100,
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &mx31lilly_timer,
+        .init_time      = mx31lilly_timer_init,
        .init_machine = mx31lilly_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bdcd92e59518..bea07299b61a 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -285,10 +285,6 @@ static void __init mx31lite_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer mx31lite_timer = {
-        .init   = mx31lite_timer_init,
-};
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
@@ -296,7 +292,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &mx31lite_timer,
+        .init_time      = mx31lite_timer_init,
        .init_machine = mx31lite_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 2517cfa9f26b..dae4cd7be040 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -596,10 +596,6 @@ static void __init mx31moboard_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer mx31moboard_timer = {
-        .init   = mx31moboard_timer_init,
-};
 static void __init mx31moboard_reserve(void)
 {
        /* reserve 4 MiB for mx3-camera */
@@ -615,7 +611,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &mx31moboard_timer,
+        .init_time      = mx31moboard_timer_init,
        .init_machine = mx31moboard_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 5277da45d60c..a42f4f07051f 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -602,10 +602,6 @@ static void __init mx35pdk_timer_init(void)
        mx35_clocks_init();
 }
-static struct sys_timer mx35pdk_timer = {
-        .init   = mx35pdk_timer_init,
-};
 static void __init mx35_3ds_reserve(void)
 {
        /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
@@ -620,7 +616,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
        .handle_irq = imx35_handle_irq,
-        .timer = &mx35pdk_timer,
+        .init_time      = mx35pdk_timer_init,
        .init_machine = mx35_3ds_init,
        .reserve = mx35_3ds_reserve,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
deleted file mode 100644
index 0c1f88a80bdc..000000000000
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#include "devices-imx50.h"
-#include "hardware.h"
-#include "iomux-mx50.h"
-#define FEC_EN          IMX_GPIO_NR(6, 23)
-#define FEC_RESET_B     IMX_GPIO_NR(4, 12)
-static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
-        /* SD1 */
-        MX50_PAD_ECSPI2_SS0__GPIO_4_19,
-        MX50_PAD_EIM_CRE__GPIO_1_27,
-        MX50_PAD_SD1_CMD__SD1_CMD,
-        MX50_PAD_SD1_CLK__SD1_CLK,
-        MX50_PAD_SD1_D0__SD1_D0,
-        MX50_PAD_SD1_D1__SD1_D1,
-        MX50_PAD_SD1_D2__SD1_D2,
-        MX50_PAD_SD1_D3__SD1_D3,
-        /* SD2 */
-        MX50_PAD_SD2_CD__GPIO_5_17,
-        MX50_PAD_SD2_WP__GPIO_5_16,
-        MX50_PAD_SD2_CMD__SD2_CMD,
-        MX50_PAD_SD2_CLK__SD2_CLK,
-        MX50_PAD_SD2_D0__SD2_D0,
-        MX50_PAD_SD2_D1__SD2_D1,
-        MX50_PAD_SD2_D2__SD2_D2,
-        MX50_PAD_SD2_D3__SD2_D3,
-        MX50_PAD_SD2_D4__SD2_D4,
-        MX50_PAD_SD2_D5__SD2_D5,
-        MX50_PAD_SD2_D6__SD2_D6,
-        MX50_PAD_SD2_D7__SD2_D7,
-        /* SD3 */
-        MX50_PAD_SD3_CMD__SD3_CMD,
-        MX50_PAD_SD3_CLK__SD3_CLK,
-        MX50_PAD_SD3_D0__SD3_D0,
-        MX50_PAD_SD3_D1__SD3_D1,
-        MX50_PAD_SD3_D2__SD3_D2,
-        MX50_PAD_SD3_D3__SD3_D3,
-        MX50_PAD_SD3_D4__SD3_D4,
-        MX50_PAD_SD3_D5__SD3_D5,
-        MX50_PAD_SD3_D6__SD3_D6,
-        MX50_PAD_SD3_D7__SD3_D7,
-        /* PWR_INT */
-        MX50_PAD_ECSPI2_MISO__GPIO_4_18,
-        /* UART pad setting */
-        MX50_PAD_UART1_TXD__UART1_TXD,
-        MX50_PAD_UART1_RXD__UART1_RXD,
-        MX50_PAD_UART1_RTS__UART1_RTS,
-        MX50_PAD_UART2_TXD__UART2_TXD,
-        MX50_PAD_UART2_RXD__UART2_RXD,
-        MX50_PAD_UART2_CTS__UART2_CTS,
-        MX50_PAD_UART2_RTS__UART2_RTS,
-        MX50_PAD_I2C1_SCL__I2C1_SCL,
-        MX50_PAD_I2C1_SDA__I2C1_SDA,
-        MX50_PAD_I2C2_SCL__I2C2_SCL,
-        MX50_PAD_I2C2_SDA__I2C2_SDA,
-        MX50_PAD_EPITO__USBH1_PWR,
-        /* Need to comment below line if
-         * one needs to debug owire.
-         */
-        MX50_PAD_OWIRE__USBH1_OC,
-        /* using gpio to control otg pwr */
-        MX50_PAD_PWM2__GPIO_6_25,
-        MX50_PAD_I2C3_SCL__USBOTG_OC,
-        MX50_PAD_SSI_RXC__FEC_MDIO,
-        MX50_PAD_SSI_RXFS__FEC_MDC,
-        MX50_PAD_DISP_D0__FEC_TXCLK,
-        MX50_PAD_DISP_D1__FEC_RX_ER,
-        MX50_PAD_DISP_D2__FEC_RX_DV,
-        MX50_PAD_DISP_D3__FEC_RXD1,
-        MX50_PAD_DISP_D4__FEC_RXD0,
-        MX50_PAD_DISP_D5__FEC_TX_EN,
-        MX50_PAD_DISP_D6__FEC_TXD1,
-        MX50_PAD_DISP_D7__FEC_TXD0,
-        MX50_PAD_I2C3_SDA__GPIO_6_23,
-        MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
-        MX50_PAD_CSPI_SS0__CSPI_SS0,
-        MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
-        MX50_PAD_CSPI_MOSI__CSPI_MOSI,
-        MX50_PAD_CSPI_MISO__CSPI_MISO,
-        /* SGTL500_OSC_EN */
-        MX50_PAD_UART1_CTS__GPIO_6_8,
-        /* SGTL_AMP_SHDN */
-        MX50_PAD_UART3_RXD__GPIO_6_15,
-        /* Keypad */
-        MX50_PAD_KEY_COL0__KEY_COL0,
-        MX50_PAD_KEY_ROW0__KEY_ROW0,
-        MX50_PAD_KEY_COL1__KEY_COL1,
-        MX50_PAD_KEY_ROW1__KEY_ROW1,
-        MX50_PAD_KEY_COL2__KEY_COL2,
-        MX50_PAD_KEY_ROW2__KEY_ROW2,
-        MX50_PAD_KEY_COL3__KEY_COL3,
-        MX50_PAD_KEY_ROW3__KEY_ROW3,
-        MX50_PAD_EIM_DA0__KEY_COL4,
-        MX50_PAD_EIM_DA1__KEY_ROW4,
-        MX50_PAD_EIM_DA2__KEY_COL5,
-        MX50_PAD_EIM_DA3__KEY_ROW5,
-        MX50_PAD_EIM_DA4__KEY_COL6,
-        MX50_PAD_EIM_DA5__KEY_ROW6,
-        MX50_PAD_EIM_DA6__KEY_COL7,
-        MX50_PAD_EIM_DA7__KEY_ROW7,
-        /*EIM pads */
-        MX50_PAD_EIM_DA8__GPIO_1_8,
-        MX50_PAD_EIM_DA9__GPIO_1_9,
-        MX50_PAD_EIM_DA10__GPIO_1_10,
-        MX50_PAD_EIM_DA11__GPIO_1_11,
-        MX50_PAD_EIM_DA12__GPIO_1_12,
-        MX50_PAD_EIM_DA13__GPIO_1_13,
-        MX50_PAD_EIM_DA14__GPIO_1_14,
-        MX50_PAD_EIM_DA15__GPIO_1_15,
-        MX50_PAD_EIM_CS2__GPIO_1_16,
-        MX50_PAD_EIM_CS1__GPIO_1_17,
-        MX50_PAD_EIM_CS0__GPIO_1_18,
-        MX50_PAD_EIM_EB0__GPIO_1_19,
-        MX50_PAD_EIM_EB1__GPIO_1_20,
-        MX50_PAD_EIM_WAIT__GPIO_1_21,
-        MX50_PAD_EIM_BCLK__GPIO_1_22,
-        MX50_PAD_EIM_RDY__GPIO_1_23,
-        MX50_PAD_EIM_OE__GPIO_1_24,
-};
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static const struct fec_platform_data fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static inline void mx50_rdp_fec_reset(void)
-{
-        gpio_request(FEC_EN, "fec-en");
-        gpio_direction_output(FEC_EN, 0);
-        gpio_request(FEC_RESET_B, "fec-reset_b");
-        gpio_direction_output(FEC_RESET_B, 0);
-        msleep(1);
-        gpio_set_value(FEC_RESET_B, 1);
-}
-static const struct imxi2c_platform_data i2c_data __initconst = {
-        .bitrate = 100000,
-};
-/*
- * Board specific initialization.
- */
-static void __init mx50_rdp_board_init(void)
-{
-        imx50_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
-                                        ARRAY_SIZE(mx50_rdp_pads));
-        imx50_add_imx_uart(0, &uart_pdata);
-        imx50_add_imx_uart(1, &uart_pdata);
-        mx50_rdp_fec_reset();
-        imx50_add_fec(&fec_data);
-        imx50_add_imx_i2c(0, &i2c_data);
-        imx50_add_imx_i2c(1, &i2c_data);
-        imx50_add_imx_i2c(2, &i2c_data);
-}
-static void __init mx50_rdp_timer_init(void)
-{
-        mx50_clocks_init(32768, 24000000, 22579200);
-}
-static struct sys_timer mx50_rdp_timer = {
-        .init   = mx50_rdp_timer_init,
-};
-MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
-        .map_io = mx50_map_io,
-        .init_early = imx50_init_early,
-        .init_irq = mx50_init_irq,
-        .handle_irq = imx50_handle_irq,
-        .timer = &mx50_rdp_timer,
-        .init_machine = mx50_rdp_board_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
deleted file mode 100644
index abc25bd1107b..000000000000
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "3ds_debugboard.h"
-#include "common.h"
-#include "devices-imx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-#define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
-static iomux_v3_cfg_t mx51_3ds_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        MX51_PAD_EIM_D25__UART2_CTS,
-        MX51_PAD_EIM_D26__UART2_RTS,
-        /* UART3 */
-        MX51_PAD_UART3_RXD__UART3_RXD,
-        MX51_PAD_UART3_TXD__UART3_TXD,
-        MX51_PAD_EIM_D24__UART3_CTS,
-        MX51_PAD_EIM_D27__UART3_RTS,
-        /* CPLD PARENT IRQ PIN */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        /* KPP */
-        MX51_PAD_KEY_ROW0__KEY_ROW0,
-        MX51_PAD_KEY_ROW1__KEY_ROW1,
-        MX51_PAD_KEY_ROW2__KEY_ROW2,
-        MX51_PAD_KEY_ROW3__KEY_ROW3,
-        MX51_PAD_KEY_COL0__KEY_COL0,
-        MX51_PAD_KEY_COL1__KEY_COL1,
-        MX51_PAD_KEY_COL2__KEY_COL2,
-        MX51_PAD_KEY_COL3__KEY_COL3,
-        MX51_PAD_KEY_COL4__KEY_COL4,
-        MX51_PAD_KEY_COL5__KEY_COL5,
-        /* eCSPI2 */
-        MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
-        MX51_PAD_NANDF_RB3__ECSPI2_MISO,
-        MX51_PAD_NANDF_D15__ECSPI2_MOSI,
-        MX51_PAD_NANDF_D12__GPIO3_28,
-};
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static int mx51_3ds_board_keymap[] = {
-        KEY(0, 0, KEY_1),
-        KEY(0, 1, KEY_2),
-        KEY(0, 2, KEY_3),
-        KEY(0, 3, KEY_F1),
-        KEY(0, 4, KEY_UP),
-        KEY(0, 5, KEY_F2),
-        KEY(1, 0, KEY_4),
-        KEY(1, 1, KEY_5),
-        KEY(1, 2, KEY_6),
-        KEY(1, 3, KEY_LEFT),
-        KEY(1, 4, KEY_SELECT),
-        KEY(1, 5, KEY_RIGHT),
-        KEY(2, 0, KEY_7),
-        KEY(2, 1, KEY_8),
-        KEY(2, 2, KEY_9),
-        KEY(2, 3, KEY_F3),
-        KEY(2, 4, KEY_DOWN),
-        KEY(2, 5, KEY_F4),
-        KEY(3, 0, KEY_0),
-        KEY(3, 1, KEY_OK),
-        KEY(3, 2, KEY_ESC),
-        KEY(3, 3, KEY_ENTER),
-        KEY(3, 4, KEY_MENU),
-        KEY(3, 5, KEY_BACK)
-};
-static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
-        .keymap         = mx51_3ds_board_keymap,
-        .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
-};
-static int mx51_3ds_spi2_cs[] = {
-        MXC_SPI_CS(0),
-        MX51_3DS_ECSPI2_CS,
-};
-static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
-        .chipselect     = mx51_3ds_spi2_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
-};
-static struct spi_board_info mx51_3ds_spi_nor_device[] = {
-        {
-         .modalias = "m25p80",
-         .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
-         .bus_num = 1,
-         .chip_select = 1,
-         .mode = SPI_MODE_0,
-         .platform_data = NULL,},
-};
-/*
- * Board specific initialization.
- */
-static void __init mx51_3ds_init(void)
-{
-        imx51_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
-                                        ARRAY_SIZE(mx51_3ds_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
-        spi_register_board_info(mx51_3ds_spi_nor_device,
-                                ARRAY_SIZE(mx51_3ds_spi_nor_device));
-        if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
-                printk(KERN_WARNING "Init of the debugboard failed, all "
-                                    "devices on the board are unusable.\n");
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-        imx51_add_imx_keypad(&mx51_3ds_map_data);
-        imx51_add_imx2_wdt(0);
-}
-static void __init mx51_3ds_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-static struct sys_timer mx51_3ds_timer = {
-        .init = mx51_3ds_timer_init,
-};
-MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_3ds_timer,
-        .init_machine = mx51_3ds_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index d9a84ca2199a..6c4d7feb4520 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -418,10 +418,6 @@ static void __init mx51_babbage_timer_init(void)
        mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
-static struct sys_timer mx51_babbage_timer = {
-        .init = mx51_babbage_timer_init,
-};
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
        /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
        .atag_offset = 0x100,
@@ -429,7 +425,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
        .init_early = imx51_init_early,
        .init_irq = mx51_init_irq,
        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_babbage_timer,
+        .init_time      = mx51_babbage_timer_init,
        .init_machine = mx51_babbage_init,
        .init_late      = imx51_init_late,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index f4a8c7e108e1..a27faaba98ec 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -261,10 +261,6 @@ static void __init mxt_td60_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer mxt_td60_timer = {
-        .init   = mxt_td60_timer_init,
-};
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        /* maintainer: Maxtrack Industrial */
        .atag_offset = 0x100,
@@ -272,7 +268,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &mxt_td60_timer,
+        .init_time      = mxt_td60_timer_init,
        .init_machine = mxt_td60_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index eee369fa94a2..b8b15bb1ffdf 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -416,10 +416,6 @@ static void __init pca100_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer pca100_timer = {
-        .init = pca100_timer_init,
-};
 MACHINE_START(PCA100, "phyCARD-i.MX27")
        .atag_offset = 0x100,
        .map_io = mx27_map_io,
@@ -427,6 +423,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
        .init_machine = pca100_init,
-        .timer = &pca100_timer,
+        .init_time      = pca100_timer_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 547fef133f65..bc0261e99d39 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -685,10 +685,6 @@ static void __init pcm037_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer pcm037_timer = {
-        .init   = pcm037_timer_init,
-};
 static void __init pcm037_reserve(void)
 {
        /* reserve 4 MiB for mx3-camera */
@@ -709,7 +705,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &pcm037_timer,
+        .init_time      = pcm037_timer_init,
        .init_machine = pcm037_init,
        .init_late = pcm037_init_late,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4aa0d0798605..e805ac273e9c 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -346,17 +346,13 @@ static void __init pcm038_timer_init(void)
        mx27_clocks_init(26000000);
 }
-static struct sys_timer pcm038_timer = {
-        .init = pcm038_timer_init,
-};
 MACHINE_START(PCM038, "phyCORE-i.MX27")
        .atag_offset = 0x100,
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
        .handle_irq = imx27_handle_irq,
-        .timer = &pcm038_timer,
+        .init_time      = pcm038_timer_init,
        .init_machine = pcm038_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 92445440221e..8ed533f0f8ca 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -394,10 +394,6 @@ static void __init pcm043_timer_init(void)
        mx35_clocks_init();
 }
-static struct sys_timer pcm043_timer = {
-        .init   = pcm043_timer_init,
-};
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
        /* Maintainer: Pengutronix */
        .atag_offset = 0x100,
@@ -405,7 +401,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
        .handle_irq = imx35_handle_irq,
-        .timer = &pcm043_timer,
+        .init_time = pcm043_timer_init,
        .init_machine = pcm043_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 96d9a91f8a3b..22af27ed457e 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -260,10 +260,6 @@ static void __init qong_timer_init(void)
        mx31_clocks_init(26000000);
 }
-static struct sys_timer qong_timer = {
-        .init   = qong_timer_init,
-};
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        /* Maintainer: DENX Software Engineering GmbH */
        .atag_offset = 0x100,
@@ -271,7 +267,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
        .handle_irq = imx31_handle_irq,
-        .timer = &qong_timer,
+        .init_time      = qong_timer_init,
        .init_machine = qong_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index fc970409dbaf..b0fa10dd79fe 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -131,10 +131,6 @@ static void __init scb9328_timer_init(void)
        mx1_clocks_init(32000);
 }
-static struct sys_timer scb9328_timer = {
-        .init   = scb9328_timer_init,
-};
 MACHINE_START(SCB9328, "Synertronixx scb9328")
        /* Sascha Hauer */
        .atag_offset = 100,
@@ -142,7 +138,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
        .handle_irq = imx1_handle_irq,
-        .timer = &scb9328_timer,
+        .init_time      = scb9328_timer_init,
        .init_machine = scb9328_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 3aecf91e4289..0910761e8280 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -305,17 +305,13 @@ static void __init vpr200_timer_init(void)
        mx35_clocks_init();
 }
-static struct sys_timer vpr200_timer = {
-        .init   = vpr200_timer_init,
-};
 MACHINE_START(VPR200, "VPR200")
        /* Maintainer: Creative Product Design */
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
        .handle_irq = imx35_handle_irq,
-        .timer = &vpr200_timer,
+        .init_time = vpr200_timer_init,
        .init_machine = vpr200_board_init,
        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 79d71cf23a1d..cf34994cfe28 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -24,16 +24,6 @@
 #include "iomux-v3.h"
 /*
- * Define the MX50 memory map.
- */
-static struct map_desc mx50_io_desc[] __initdata = {
-        imx_map_entry(MX50, TZIC, MT_DEVICE),
-        imx_map_entry(MX50, SPBA0, MT_DEVICE),
-        imx_map_entry(MX50, AIPS1, MT_DEVICE),
-        imx_map_entry(MX50, AIPS2, MT_DEVICE),
-};
-/*
 * Define the MX51 memory map.
 */
 static struct map_desc mx51_io_desc[] __initdata = {
@@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = {
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
-void __init mx50_map_io(void)
-{
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
-}
 void __init mx51_map_io(void)
 {
        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
@@ -74,13 +59,6 @@ void __init mx53_map_io(void)
        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
 }
-void __init imx50_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX50);
-        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-}
 /*
 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
 * the Freescale marketing division. However this did not remove the
@@ -115,11 +93,6 @@ void __init imx53_init_early(void)
        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
-void __init mx50_init_irq(void)
-{
-        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-}
 void __init mx51_init_irq(void)
 {
        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
@@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
        .script_addrs = &imx51_sdma_script,
 };
-static const struct resource imx50_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
-};
 static const struct resource imx51_audmux_res[] __initconst = {
        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 };
-void __init imx50_soc_init(void)
-{
-        mxc_device_init();
-        /* i.mx50 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
-        /* i.mx50 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
-                                        ARRAY_SIZE(imx50_audmux_res));
-}
 void __init imx51_soc_init(void)
 {
        mxc_device_init();
diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h
deleted file mode 100644
index 09ac19c1570c..000000000000
--- a/arch/arm/mach-imx/mx50.h
+++ /dev/null
@@ -1,290 +0,0 @@
-#ifndef __MACH_MX50_H__
-#define __MACH_MX50_H__
-/*
- * IROM
- */
-#define MX50_IROM_BASE_ADDR             0x0
-#define MX50_IROM_SIZE                  SZ_64K
-/* TZIC */
-#define MX50_TZIC_BASE_ADDR             0x0fffc000
-#define MX50_TZIC_SIZE                  SZ_16K
-/*
- * IRAM
- */
-#define MX50_IRAM_BASE_ADDR     0xf8000000      /* internal ram */
-#define MX50_IRAM_PARTITIONS    16
-#define MX50_IRAM_SIZE          (MX50_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-/*
- * Databahn
- */
-#define MX50_DATABAHN_BASE_ADDR                 0x14000000
-/*
- * Graphics Memory of GPU
- */
-#define MX50_GPU2D_BASE_ADDR            0x20000000
-#define MX50_DEBUG_BASE_ADDR            0x40000000
-#define MX50_DEBUG_SIZE                 SZ_1M
-#define MX50_ETB_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00001000)
-#define MX50_ETM_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00002000)
-#define MX50_TPIU_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00003000)
-#define MX50_CTI0_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00004000)
-#define MX50_CTI1_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00005000)
-#define MX50_CTI2_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00006000)
-#define MX50_CTI3_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00007000)
-#define MX50_CORTEX_DBG_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x00008000)
-#define MX50_APBHDMA_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01000000)
-#define MX50_OCOTP_CTRL_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x01002000)
-#define MX50_DIGCTL_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01004000)
-#define MX50_GPMI_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01006000)
-#define MX50_BCH_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01008000)
-#define MX50_ELCDIF_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x0100a000)
-#define MX50_EPXP_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x0100c000)
-#define MX50_DCP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x0100e000)
-#define MX50_EPDC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01010000)
-#define MX50_QOSC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01012000)
-#define MX50_PERFMON_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01014000)
-#define MX50_SSP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01016000)
-#define MX50_ANATOP_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01018000)
-#define MX50_NIC_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x08000000)
-/*
- * SPBA global module enabled #0
- */
-#define MX50_SPBA0_BASE_ADDR            0x50000000
-#define MX50_SPBA0_SIZE                 SZ_1M
-#define MX50_MMC_SDHC1_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00004000)
-#define MX50_MMC_SDHC2_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00008000)
-#define MX50_UART3_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x0000c000)
-#define MX50_CSPI1_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x00010000)
-#define MX50_SSI2_BASE_ADDR             (MX50_SPBA0_BASE_ADDR + 0x00014000)
-#define MX50_MMC_SDHC3_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00020000)
-#define MX50_MMC_SDHC4_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00024000)
-/*
- * AIPS 1
- */
-#define MX50_AIPS1_BASE_ADDR    0x53f00000
-#define MX50_AIPS1_SIZE         SZ_1M
-#define MX50_OTG_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00080000)
-#define MX50_GPIO1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00084000)
-#define MX50_GPIO2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00088000)
-#define MX50_GPIO3_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x0008c000)
-#define MX50_GPIO4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00090000)
-#define MX50_KPP_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00094000)
-#define MX50_WDOG_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x00098000)
-#define MX50_GPT1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a0000)
-#define MX50_SRTC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a4000)
-#define MX50_IOMUXC_BASE_ADDR   (MX50_AIPS1_BASE_ADDR + 0x000a8000)
-#define MX50_EPIT1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000ac000)
-#define MX50_PWM1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b4000)
-#define MX50_PWM2_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b8000)
-#define MX50_UART1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000bc000)
-#define MX50_UART2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000c0000)
-#define MX50_SRC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d0000)
-#define MX50_CCM_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d4000)
-#define MX50_GPC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d8000)
-#define MX50_GPIO5_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000dc000)
-#define MX50_GPIO6_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000e0000)
-#define MX50_I2C3_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000ec000)
-#define MX50_UART4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000f0000)
-#define MX50_MSHC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f4000)
-#define MX50_RNGB_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f8000)
-/*
- * AIPS 2
- */
-#define MX50_AIPS2_BASE_ADDR    0x63f00000
-#define MX50_AIPS2_SIZE         SZ_1M
-#define MX50_PLL1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00080000)
-#define MX50_PLL2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00084000)
-#define MX50_PLL3_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00088000)
-#define MX50_UART5_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x00090000)
-#define MX50_AHBMAX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x00094000)
-#define MX50_ARM_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000a0000)
-#define MX50_OWIRE_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000a4000)
-#define MX50_CSPI2_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000ac000)
-#define MX50_SDMA_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000b0000)
-#define MX50_ROMCP_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000b8000)
-#define MX50_CSPI3_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000c0000)
-#define MX50_I2C2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c4000)
-#define MX50_I2C1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c8000)
-#define MX50_SSI1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000cc000)
-#define MX50_AUDMUX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x000d0000)
-#define MX50_WEIM_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000d8000)
-#define MX50_FEC_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000ec000)
-/*
- * Memory regions and CS
- */
-#define MX50_CSD0_BASE_ADDR             0x70000000
-#define MX50_CSD1_BASE_ADDR             0xb0000000
-#define MX50_CS0_BASE_ADDR              0xf0000000
-#define MX50_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX50_IO_ADDRESS(x)              IOMEM(MX50_IO_P2V(x))
-/*
- * defines for SPBA modules
- */
-#define MX50_SPBA_SDHC1         0x04
-#define MX50_SPBA_SDHC2         0x08
-#define MX50_SPBA_UART3         0x0c
-#define MX50_SPBA_CSPI1         0x10
-#define MX50_SPBA_SSI2          0x14
-#define MX50_SPBA_SDHC3         0x20
-#define MX50_SPBA_SDHC4         0x24
-#define MX50_SPBA_SPDIF         0x28
-#define MX50_SPBA_ATA           0x30
-#define MX50_SPBA_SLIM          0x34
-#define MX50_SPBA_HSI2C         0x38
-#define MX50_SPBA_CTRL          0x3c
-/*
- * DMA request assignments
- */
-#define MX50_DMA_REQ_GPC                1
-#define MX50_DMA_REQ_ATA_UART4_RX       2
-#define MX50_DMA_REQ_ATA_UART4_TX       3
-#define MX50_DMA_REQ_CSPI1_RX           6
-#define MX50_DMA_REQ_CSPI1_TX           7
-#define MX50_DMA_REQ_CSPI2_RX           8
-#define MX50_DMA_REQ_CSPI2_TX           9
-#define MX50_DMA_REQ_I2C3_SDHC3         10
-#define MX50_DMA_REQ_SDHC4              11
-#define MX50_DMA_REQ_UART2_FIRI_RX      12
-#define MX50_DMA_REQ_UART2_FIRI_TX      13
-#define MX50_DMA_REQ_EXT0               14
-#define MX50_DMA_REQ_EXT1               15
-#define MX50_DMA_REQ_UART5_RX           16
-#define MX50_DMA_REQ_UART5_TX           17
-#define MX50_DMA_REQ_UART1_RX           18
-#define MX50_DMA_REQ_UART1_TX           19
-#define MX50_DMA_REQ_I2C1_SDHC1         20
-#define MX50_DMA_REQ_I2C2_SDHC2         21
-#define MX50_DMA_REQ_SSI2_RX2           22
-#define MX50_DMA_REQ_SSI2_TX2           23
-#define MX50_DMA_REQ_SSI2_RX1           24
-#define MX50_DMA_REQ_SSI2_TX1           25
-#define MX50_DMA_REQ_SSI1_RX2           26
-#define MX50_DMA_REQ_SSI1_TX2           27
-#define MX50_DMA_REQ_SSI1_RX1           28
-#define MX50_DMA_REQ_SSI1_TX1           29
-#define MX50_DMA_REQ_CSPI_RX            38
-#define MX50_DMA_REQ_CSPI_TX            39
-#define MX50_DMA_REQ_UART3_RX           42
-#define MX50_DMA_REQ_UART3_TX           43
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX50_INT_MMC_SDHC1      (NR_IRQS_LEGACY + 1)
-#define MX50_INT_MMC_SDHC2      (NR_IRQS_LEGACY + 2)
-#define MX50_INT_MMC_SDHC3      (NR_IRQS_LEGACY + 3)
-#define MX50_INT_MMC_SDHC4      (NR_IRQS_LEGACY + 4)
-#define MX50_INT_DAP            (NR_IRQS_LEGACY + 5)
-#define MX50_INT_SDMA           (NR_IRQS_LEGACY + 6)
-#define MX50_INT_IOMUX          (NR_IRQS_LEGACY + 7)
-#define MX50_INT_UART4          (NR_IRQS_LEGACY + 13)
-#define MX50_INT_USB_H1         (NR_IRQS_LEGACY + 14)
-#define MX50_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
-#define MX50_INT_DATABAHN       (NR_IRQS_LEGACY + 19)
-#define MX50_INT_ELCDIF         (NR_IRQS_LEGACY + 20)
-#define MX50_INT_EPXP           (NR_IRQS_LEGACY + 21)
-#define MX50_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
-#define MX50_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
-#define MX50_INT_EPDC           (NR_IRQS_LEGACY + 27)
-#define MX50_INT_NIC            (NR_IRQS_LEGACY + 28)
-#define MX50_INT_SSI1           (NR_IRQS_LEGACY + 29)
-#define MX50_INT_SSI2           (NR_IRQS_LEGACY + 30)
-#define MX50_INT_UART1          (NR_IRQS_LEGACY + 31)
-#define MX50_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX50_INT_UART3          (NR_IRQS_LEGACY + 33)
-#define MX50_INT_RESV34         (NR_IRQS_LEGACY + 34)
-#define MX50_INT_RESV35         (NR_IRQS_LEGACY + 35)
-#define MX50_INT_CSPI1          (NR_IRQS_LEGACY + 36)
-#define MX50_INT_CSPI2          (NR_IRQS_LEGACY + 37)
-#define MX50_INT_CSPI           (NR_IRQS_LEGACY + 38)
-#define MX50_INT_GPT            (NR_IRQS_LEGACY + 39)
-#define MX50_INT_EPIT1          (NR_IRQS_LEGACY + 40)
-#define MX50_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
-#define MX50_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
-#define MX50_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
-#define MX50_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
-#define MX50_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
-#define MX50_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
-#define MX50_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
-#define MX50_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
-#define MX50_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
-#define MX50_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
-#define MX50_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
-#define MX50_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
-#define MX50_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
-#define MX50_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
-#define MX50_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
-#define MX50_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
-#define MX50_INT_WDOG1          (NR_IRQS_LEGACY + 58)
-#define MX50_INT_KPP            (NR_IRQS_LEGACY + 60)
-#define MX50_INT_PWM1           (NR_IRQS_LEGACY + 61)
-#define MX50_INT_I2C1           (NR_IRQS_LEGACY + 62)
-#define MX50_INT_I2C2           (NR_IRQS_LEGACY + 63)
-#define MX50_INT_I2C3           (NR_IRQS_LEGACY + 64)
-#define MX50_INT_RESV65         (NR_IRQS_LEGACY + 65)
-#define MX50_INT_DCDC           (NR_IRQS_LEGACY + 66)
-#define MX50_INT_THERMAL_ALARM  (NR_IRQS_LEGACY + 67)
-#define MX50_INT_ANA3           (NR_IRQS_LEGACY + 68)
-#define MX50_INT_ANA4           (NR_IRQS_LEGACY + 69)
-#define MX50_INT_CCM1           (NR_IRQS_LEGACY + 71)
-#define MX50_INT_CCM2           (NR_IRQS_LEGACY + 72)
-#define MX50_INT_GPC1           (NR_IRQS_LEGACY + 73)
-#define MX50_INT_GPC2           (NR_IRQS_LEGACY + 74)
-#define MX50_INT_SRC            (NR_IRQS_LEGACY + 75)
-#define MX50_INT_NM             (NR_IRQS_LEGACY + 76)
-#define MX50_INT_PMU            (NR_IRQS_LEGACY + 77)
-#define MX50_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
-#define MX50_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
-#define MX50_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
-#define MX50_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
-#define MX50_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
-#define MX50_INT_UART5          (NR_IRQS_LEGACY + 86)
-#define MX50_INT_FEC            (NR_IRQS_LEGACY + 87)
-#define MX50_INT_OWIRE          (NR_IRQS_LEGACY + 88)
-#define MX50_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
-#define MX50_INT_SJC            (NR_IRQS_LEGACY + 90)
-#define MX50_INT_DCP_CHAN1_3    (NR_IRQS_LEGACY + 91)
-#define MX50_INT_DCP_CHAN0      (NR_IRQS_LEGACY + 92)
-#define MX50_INT_PWM2           (NR_IRQS_LEGACY + 94)
-#define MX50_INT_RNGB           (NR_IRQS_LEGACY + 97)
-#define MX50_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
-#define MX50_INT_RAWNAND_BCH    (NR_IRQS_LEGACY + 100)
-#define MX50_INT_RAWNAND_GPMI   (NR_IRQS_LEGACY + 102)
-#define MX50_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
-#define MX50_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
-#define MX50_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
-#define MX50_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
-#define MX50_INT_MSHC           (NR_IRQS_LEGACY + 109)
-#define MX50_INT_APBHDMA_CHAN0  (NR_IRQS_LEGACY + 110)
-#define MX50_INT_APBHDMA_CHAN1  (NR_IRQS_LEGACY + 111)
-#define MX50_INT_APBHDMA_CHAN2  (NR_IRQS_LEGACY + 112)
-#define MX50_INT_APBHDMA_CHAN3  (NR_IRQS_LEGACY + 113)
-#define MX50_INT_APBHDMA_CHAN4  (NR_IRQS_LEGACY + 114)
-#define MX50_INT_APBHDMA_CHAN5  (NR_IRQS_LEGACY + 115)
-#define MX50_INT_APBHDMA_CHAN6  (NR_IRQS_LEGACY + 116)
-#define MX50_INT_APBHDMA_CHAN7  (NR_IRQS_LEGACY + 117)
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx50_revision(void);
-#endif
-#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index d78298366a91..7dce17a9fe6c 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -32,7 +32,6 @@
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
-#define MXC_CPU_MX50            50
 #define MXC_CPU_MX51            51
 #define MXC_CPU_MX53            53
@@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
-#ifdef CONFIG_SOC_IMX50
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MX50
-# endif
-# define cpu_is_mx50()          (mxc_cpu_type == MXC_CPU_MX50)
-#else
-# define cpu_is_mx50()          (0)
-#endif
 #ifdef CONFIG_SOC_IMX51
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 66fae885c842..7c0b03f67b05 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,14 +12,16 @@
 #include <linux/init.h>
 #include <linux/smp.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include "common.h"
 #include "hardware.h"
+#define SCU_STANDBY_ENABLE      (1 << 5)
 static void __iomem *scu_base;
 static struct map_desc scu_io_desc __initdata = {
@@ -42,6 +44,14 @@ void __init imx_scu_map_io(void)
        scu_base = IMX_IO_ADDRESS(base);
 }
+void imx_scu_standby_enable(void)
+{
+        u32 val = readl_relaxed(scu_base);
+        val |= SCU_STANDBY_ENABLE;
+        writel_relaxed(val, scu_base);
+}
 static void __cpuinit imx_secondary_init(unsigned int cpu)
 {
        /*
@@ -71,8 +81,6 @@ static void __init imx_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 void imx_smp_prepare(void)
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 2e063c2deb9e..f67fd7ee8127 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -34,7 +34,7 @@
 /*
 * set cpu low power mode before WFI instruction. This function is called
- * mx5 because it can be used for mx50, mx51, and mx53.
+ * mx5 because it can be used for mx51, and mx53.
 */
 static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 {
@@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
        __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
        __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
+        __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
-        /* Enable NEON SRPG for all but MX50TO1.0. */
-        if (mx50_revision() != IMX_CHIP_REVISION_1_0)
-                __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
        if (stop_mode) {
                empgc0 |= MXC_SRPGCR_PCR;
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index f017302f6d09..fea91313678b 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -152,7 +152,8 @@ static int v2_set_next_event(unsigned long evt,
        __raw_writel(tcmp, timer_base + V2_TCMP);
-        return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
+        return evt < 0x7fffffff &&
+                (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
                                -ETIME : 0;
 }
@@ -256,7 +257,6 @@ static struct irqaction mxc_timer_irq = {
 static struct clock_event_device clockevent_mxc = {
        .name           = "mxc_timer1",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .set_mode       = mxc_set_mode,
        .set_next_event = mx1_2_set_next_event,
        .rating         = 200,
@@ -264,21 +264,13 @@ static struct clock_event_device clockevent_mxc = {
 static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
-        unsigned int c = clk_get_rate(timer_clk);
        if (timer_is_v2())
                clockevent_mxc.set_next_event = v2_set_next_event;
-        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
-                                        clockevent_mxc.shift);
-        clockevent_mxc.max_delta_ns =
-                        clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
-        clockevent_mxc.min_delta_ns =
-                        clockevent_delta2ns(0xff, &clockevent_mxc);
        clockevent_mxc.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&clockevent_mxc,
-        clockevents_register_device(&clockevent_mxc);
+                                        clk_get_rate(timer_clk),
+                                        0xff, 0xfffffffe);
        return 0;
 }
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 79197d8b34aa..72516658be1e 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,10 +1,5 @@
 #include <linux/amba/serial.h>
-#ifdef CONFIG_ARCH_INTEGRATOR_AP
 extern struct amba_pl010_data ap_uart_data;
-#else
-/* Not used without Integrator/AP support anyway */
-struct amba_pl010_data ap_uart_data {};
-#endif
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 39c060f75e47..81461d218717 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -71,7 +71,7 @@ int __init integrator_init(bool is_cp)
         * hard-code them. The Integator/CP and forward have proper cell IDs.
         * Else we leave them undefined to the bus driver can autoprobe them.
         */
-        if (!is_cp) {
+        if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) {
                rtc_device.periphid     = 0x00041030;
                uart0_device.periphid   = 0x00041010;
                uart1_device.periphid   = 0x00041010;
diff --git a/arch/arm/mach-integrator/include/mach/uncompress.h b/arch/arm/mach-integrator/include/mach/uncompress.h
index 30452f00a164..8f3cc9954c16 100644
--- a/arch/arm/mach-integrator/include/mach/uncompress.h
+++ b/arch/arm/mach-integrator/include/mach/uncompress.h
@@ -46,5 +46,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 11e2a4145807..ea961445e0e9 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -94,7 +94,7 @@ void __iomem *ap_syscon_base;
 * f1b00000     1b000000        GPIO
 */
-static struct map_desc ap_io_desc[] __initdata = {
+static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
@@ -425,7 +425,7 @@ void __init ap_init_early(void)
 #ifdef CONFIG_OF
-static void __init ap_init_timer_of(void)
+static void __init ap_of_timer_init(void)
 {
        struct device_node *node;
        const char *path;
@@ -464,10 +464,6 @@ static void __init ap_init_timer_of(void)
        integrator_clockevent_init(rate, base, irq);
 }
-static struct sys_timer ap_of_timer = {
-        .init           = ap_init_timer_of,
-};
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
        { /* Sentinel */ }
@@ -586,7 +582,7 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
        .init_early     = ap_init_early,
        .init_irq       = ap_init_irq_of,
        .handle_irq     = fpga_handle_irq,
-        .timer          = &ap_of_timer,
+        .init_time      = ap_of_timer_init,
        .init_machine   = ap_init_of,
        .restart        = integrator_restart,
        .dt_compat      = ap_dt_board_compat,
@@ -613,7 +609,6 @@ static struct map_desc ap_io_desc_atag[] __initdata = {
 static void __init ap_map_io_atag(void)
 {
        iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
-        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
        ap_map_io();
 }
@@ -638,7 +633,7 @@ static struct platform_device cfi_flash_device = {
        .resource       = &cfi_flash_resource,
 };
-static void __init ap_init_timer(void)
+static void __init ap_timer_init(void)
 {
        struct clk *clk;
        unsigned long rate;
@@ -657,10 +652,6 @@ static void __init ap_init_timer(void)
                                IRQ_TIMERINT1);
 }
-static struct sys_timer ap_timer = {
-        .init           = ap_init_timer,
-};
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 static void __init ap_init_irq(void)
@@ -685,6 +676,7 @@ static void __init ap_init(void)
        platform_device_register(&cfi_flash_device);
+        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
        for (i = 0; i < 4; i++) {
                struct lm_device *lmdev;
@@ -716,7 +708,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        .init_early     = ap_init_early,
        .init_irq       = ap_init_irq,
        .handle_irq     = fpga_handle_irq,
-        .timer          = &ap_timer,
+        .init_time      = ap_timer_init,
        .init_machine   = ap_init,
        .restart        = integrator_restart,
 MACHINE_END
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 7322838c0447..2b0db82a5381 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -78,7 +78,7 @@ static void __iomem *intcp_con_base;
 * fcb00000     cb000000        CP system control
 */
-static struct map_desc intcp_io_desc[] __initdata = {
+static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
@@ -251,7 +251,7 @@ static void __init intcp_init_early(void)
 #ifdef CONFIG_OF
-static void __init intcp_timer_init_of(void)
+static void __init cp_of_timer_init(void)
 {
        struct device_node *node;
        const char *path;
@@ -283,10 +283,6 @@ static void __init intcp_timer_init_of(void)
        sp804_clockevents_init(base, irq, node->name);
 }
-static struct sys_timer cp_of_timer = {
-        .init           = intcp_timer_init_of,
-};
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
        { /* Sentinel */ }
@@ -390,7 +386,7 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq_of,
        .handle_irq     = fpga_handle_irq,
-        .timer          = &cp_of_timer,
+        .init_time      = cp_of_timer_init,
        .init_machine   = intcp_init_of,
        .restart        = integrator_restart,
        .dt_compat      = intcp_dt_board_compat,
@@ -512,7 +508,7 @@ static void __init intcp_init_irq(void)
 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
-static void __init intcp_timer_init(void)
+static void __init cp_timer_init(void)
 {
        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
@@ -522,10 +518,6 @@ static void __init intcp_timer_init(void)
        sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
 }
-static struct sys_timer cp_timer = {
-        .init           = intcp_timer_init,
-};
 #define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
 #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
@@ -565,7 +557,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq,
        .handle_irq     = fpga_handle_irq,
-        .timer          = &cp_timer,
+        .init_time      = cp_timer_init,
        .init_machine   = intcp_init,
        .restart        = integrator_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h
index fa4f80522fad..d3791ece2772 100644
--- a/arch/arm/mach-iop13xx/include/mach/uncompress.h
+++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h
@@ -20,4 +20,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index e3f3e7daa79e..02a8228ac2d3 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -84,17 +84,13 @@ static void __init iq81340mc_timer_init(void)
        iop_init_time(bus_freq);
 }
-static struct sys_timer iq81340mc_timer = {
-       .init       = iq81340mc_timer_init,
-};
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
        .atag_offset    = 0x100,
        .init_early     = iop13xx_init_early,
        .map_io         = iop13xx_map_io,
        .init_irq       = iop13xx_init_irq,
-        .timer          = &iq81340mc_timer,
+        .init_time      = iq81340mc_timer_init,
        .init_machine   = iq81340mc_init,
        .restart        = iop13xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index e94744111634..1b80f10722b3 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -86,17 +86,13 @@ static void __init iq81340sc_timer_init(void)
        iop_init_time(bus_freq);
 }
-static struct sys_timer iq81340sc_timer = {
-       .init       = iq81340sc_timer_init,
-};
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
        /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
        .atag_offset    = 0x100,
        .init_early     = iop13xx_init_early,
        .map_io         = iop13xx_map_io,
        .init_irq       = iop13xx_init_irq,
-        .timer          = &iq81340sc_timer,
+        .init_time      = iq81340sc_timer_init,
        .init_machine   = iq81340sc_init,
        .restart        = iop13xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 9f369f09c29d..31fbb6c61b25 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -40,10 +40,6 @@ static void __init em7210_timer_init(void)
        iop_init_time(200000000);
 }
-static struct sys_timer em7210_timer = {
-        .init           = em7210_timer_init,
-};
 /*
 * EM7210 RTC
 */
@@ -205,7 +201,7 @@ MACHINE_START(EM7210, "Lanner EM7210")
        .atag_offset    = 0x100,
        .map_io         = em7210_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &em7210_timer,
+        .init_time      = em7210_timer_init,
        .init_machine   = em7210_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 02e20c3912ba..ac304705fe68 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -44,10 +44,6 @@ static void __init glantank_timer_init(void)
        iop_init_time(200000000);
 }
-static struct sys_timer glantank_timer = {
-        .init           = glantank_timer_init,
-};
 /*
 * GLAN Tank I/O.
@@ -209,7 +205,7 @@ MACHINE_START(GLANTANK, "GLAN Tank")
        .atag_offset    = 0x100,
        .map_io         = glantank_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &glantank_timer,
+        .init_time      = glantank_timer_init,
        .init_machine   = glantank_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index 4fd715496f45..b3d45fd365e7 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -36,4 +36,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 * nothing to do
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index ddd1c7ecfe57..f2cd2966212d 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -75,10 +75,6 @@ static void __init iq31244_timer_init(void)
        }
 }
-static struct sys_timer iq31244_timer = {
-        .init           = iq31244_timer_init,
-};
 /*
 * IQ31244 I/O.
@@ -314,7 +310,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
        .atag_offset    = 0x100,
        .map_io         = iq31244_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &iq31244_timer,
+        .init_time      = iq31244_timer_init,
        .init_machine   = iq31244_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
@@ -329,7 +325,7 @@ MACHINE_START(EP80219, "Intel EP80219")
        .atag_offset    = 0x100,
        .map_io         = iq31244_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &iq31244_timer,
+        .init_time      = iq31244_timer_init,
        .init_machine   = iq31244_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index bf155e6a3b45..015435de90dd 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -43,10 +43,6 @@ static void __init iq80321_timer_init(void)
        iop_init_time(200000000);
 }
-static struct sys_timer iq80321_timer = {
-        .init           = iq80321_timer_init,
-};
 /*
 * IQ80321 I/O.
@@ -188,7 +184,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
        .atag_offset    = 0x100,
        .map_io         = iq80321_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &iq80321_timer,
+        .init_time      = iq80321_timer_init,
        .init_machine   = iq80321_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 5a7ae91e8849..ea0984a7449e 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -50,10 +50,6 @@ static void __init n2100_timer_init(void)
        iop_init_time(198000000);
 }
-static struct sys_timer n2100_timer = {
-        .init           = n2100_timer_init,
-};
 /*
 * N2100 I/O.
@@ -337,7 +333,7 @@ MACHINE_START(N2100, "Thecus N2100")
        .atag_offset    = 0x100,
        .map_io         = n2100_map_io,
        .init_irq       = iop32x_init_irq,
-        .timer          = &n2100_timer,
+        .init_time      = n2100_timer_init,
        .init_machine   = n2100_init_machine,
        .restart        = n2100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index f99bb848c5a1..ed282e14176d 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -34,4 +34,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 * nothing to do
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index e74a7debe793..c43304a10fa7 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -45,10 +45,6 @@ static void __init iq80331_timer_init(void)
                iop_init_time(266000000);
 }
-static struct sys_timer iq80331_timer = {
-        .init           = iq80331_timer_init,
-};
 /*
 * IQ80331 PCI.
@@ -143,7 +139,7 @@ MACHINE_START(IQ80331, "Intel IQ80331")
        .atag_offset    = 0x100,
        .map_io         = iop3xx_map_io,
        .init_irq       = iop33x_init_irq,
-        .timer          = &iq80331_timer,
+        .init_time      = iq80331_timer_init,
        .init_machine   = iq80331_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index e2f5beece6e8..8192987e78e5 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -45,10 +45,6 @@ static void __init iq80332_timer_init(void)
                iop_init_time(266000000);
 }
-static struct sys_timer iq80332_timer = {
-        .init           = iq80332_timer_init,
-};
 /*
 * IQ80332 PCI.
@@ -143,7 +139,7 @@ MACHINE_START(IQ80332, "Intel IQ80332")
        .atag_offset    = 0x100,
        .map_io         = iop3xx_map_io,
        .init_irq       = iop33x_init_irq,
-        .timer          = &iq80332_timer,
+        .init_time      = iq80332_timer_init,
        .init_machine   = iq80332_init_machine,
        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 90e42e9982cb..6beec150c060 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = avila_init,
 #if defined(CONFIG_PCI)
@@ -187,7 +187,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = avila_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8c0c0e2d0727..1dbeb7c99d58 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -307,10 +307,6 @@ void __init ixp4xx_timer_init(void)
        ixp4xx_clockevent_init();
 }
-struct sys_timer ixp4xx_timer = {
-        .init           = ixp4xx_timer_init,
-};
 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
@@ -523,22 +519,15 @@ static struct clock_event_device clockevent_ixp4xx = {
        .name           = "ixp4xx timer1",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .rating         = 200,
-        .shift          = 24,
        .set_mode       = ixp4xx_set_mode,
        .set_next_event = ixp4xx_set_next_event,
 };
 static void __init ixp4xx_clockevent_init(void)
 {
-        clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
-                                        clockevent_ixp4xx.shift);
-        clockevent_ixp4xx.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
-        clockevent_ixp4xx.min_delta_ns =
-                clockevent_delta2ns(0xf, &clockevent_ixp4xx);
        clockevent_ixp4xx.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
-        clockevents_register_device(&clockevent_ixp4xx);
+                                        0xf, 0xfffffffe);
 }
 void ixp4xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 1b83110028d6..820cae8608fc 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -112,7 +112,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = coyote_init,
 #if defined(CONFIG_PCI)
@@ -132,7 +132,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = coyote_init,
        .restart        = ixp4xx_restart,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 97a0af8f1955..5d413f8c5700 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -226,10 +226,6 @@ static void __init dsmg600_timer_init(void)
    ixp4xx_timer_init();
 }
-static struct sys_timer dsmg600_timer = {
-    .init   = dsmg600_timer_init,
-};
 static void __init dsmg600_init(void)
 {
        ixp4xx_sys_init();
@@ -282,7 +278,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &dsmg600_timer,
+        .init_time      = dsmg600_timer_init,
        .init_machine   = dsmg600_init,
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 9175a25a7511..429966b756ed 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -272,7 +272,7 @@ MACHINE_START(FSG, "Freecom FSG-3")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = fsg_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 033c71758953..3d24b3fcee87 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -99,7 +99,7 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = gateway7001_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 53b8348dfcc2..e54ff491c105 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -498,7 +498,7 @@ MACHINE_START(GORAMO_MLR, "MultiLink")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = gmlr_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 18ebc6be7969..16a12994fb53 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = gtwx5715_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index 5bce94aacca9..db5afb69c123 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -89,8 +89,6 @@ struct ixp4xx_pata_data {
        void __iomem    *cs1;
 };
-struct sys_timer;
 #define IXP4XX_ETH_NPEA         0x00
 #define IXP4XX_ETH_NPEB         0x10
 #define IXP4XX_ETH_NPEC         0x20
@@ -125,7 +123,6 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern struct sys_timer ixp4xx_timer;
 extern void ixp4xx_restart(char, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index eb945a926d07..7b25c0225e46 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -53,6 +53,4 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 */
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 108a9d3f382d..22d688b7d513 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -252,7 +252,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
@@ -268,7 +268,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
@@ -283,7 +283,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
@@ -298,7 +298,7 @@ MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = ixdp425_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 33cb0955b6bf..ed667ce9f576 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -317,7 +317,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .init_machine   = nas100d_init,
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index e2903faaebb3..7e55236c26ea 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -232,10 +232,6 @@ static void __init nslu2_timer_init(void)
    ixp4xx_timer_init();
 }
-static struct sys_timer nslu2_timer = {
-    .init   = nslu2_timer_init,
-};
 static void __init nslu2_init(void)
 {
        uint8_t __iomem *f;
@@ -303,7 +299,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &nslu2_timer,
+        .init_time      = nslu2_timer_init,
        .init_machine   = nslu2_init,
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 158ddb79821d..46a89f5e8269 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -245,7 +245,7 @@ MACHINE_START(DEVIXP, "Omicron DEVIXP")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .init_machine   = omixp_init,
        .restart        = ixp4xx_restart,
 MACHINE_END
@@ -257,7 +257,7 @@ MACHINE_START(MICCPT, "Omicron MICCPT")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .init_machine   = omixp_init,
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
@@ -272,7 +272,7 @@ MACHINE_START(MIC256, "Omicron MIC256")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .init_machine   = omixp_init,
        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 2798f435aaf4..d42730a1d4ab 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -239,7 +239,7 @@ MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = vulcan_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index a785175b115b..8f9ea2f3a9a5 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -100,7 +100,7 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
        .map_io         = ixp4xx_map_io,
        .init_early     = ixp4xx_init_early,
        .init_irq       = ixp4xx_init_irq,
-        .timer          = &ixp4xx_timer,
+        .init_time      = ixp4xx_timer_init,
        .atag_offset    = 0x100,
        .init_machine   = wg302v2_init,
 #if defined(CONFIG_PCI)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index f91cdff5a3e4..7b6a64bc5f40 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,13 @@ config ARCH_KIRKWOOD_DT
          Say 'Y' here if you want your kernel to support the
          Marvell Kirkwood using flattened device tree.
+config MACH_GURUPLUG_DT
+        bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell GuruPlug Reference Board (Flattened Device Tree).
 config MACH_DREAMPLUG_DT
        bool "Marvell DreamPlug (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 8d2e5a96247c..4cc4bee4d0cf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -19,9 +19,9 @@ obj-$(CONFIG_MACH_NET2BIG_V2)		+= netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
-obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
+obj-$(CONFIG_MACH_GURUPLUG_DT)          += board-guruplug.o
 obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 08248e24ffcd..0903242c00dc 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
@@ -26,10 +25,6 @@ static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
 };
-static struct mvsdio_platform_data dreamplug_mvsdio_data = {
-        /* unfortunately the CD signal has not been connected */
-};
 void __init dreamplug_init(void)
 {
        /*
@@ -37,5 +32,4 @@ void __init dreamplug_init(void)
         */
        kirkwood_ge00_init(&dreamplug_ge00_data);
        kirkwood_ge01_init(&dreamplug_ge01_data);
-        kirkwood_sdio_init(&dreamplug_mvsdio_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index de4fd2bb1e27..2e73e9d53f70 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -55,10 +55,6 @@ static void __init kirkwood_legacy_clk_init(void)
        orion_clkdev_add("0", "pcie",
                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CGC_BIT_USB0;
-        orion_clkdev_add(NULL, "orion-ehci.0",
-                         of_clk_get_from_provider(&clkspec));
        clkspec.args[0] = CGC_BIT_PEX1;
        orion_clkdev_add("1", "pcie",
                         of_clk_get_from_provider(&clkspec));
@@ -66,11 +62,6 @@ static void __init kirkwood_legacy_clk_init(void)
        clkspec.args[0] = CGC_BIT_GE1;
        orion_clkdev_add(NULL, "mv643xx_eth_port.1",
                         of_clk_get_from_provider(&clkspec));
-        clkspec.args[0] = CGC_BIT_SDIO;
-        orion_clkdev_add(NULL, "mvsdio",
-                         of_clk_get_from_provider(&clkspec));
 }
 static void __init kirkwood_of_clk_init(void)
@@ -98,6 +89,8 @@ static void __init kirkwood_dt_init(void)
        /* Setup root of clk tree */
        kirkwood_of_clk_init();
+        kirkwood_cpuidle_init();
 #ifdef CONFIG_KEXEC
        kexec_reinit = kirkwood_enable_pcie;
 #endif
@@ -105,6 +98,9 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("globalscale,dreamplug"))
                dreamplug_init();
+        if (of_machine_is_compatible("globalscale,guruplug"))
+                guruplug_dt_init();
        if (of_machine_is_compatible("dlink,dns-kirkwood"))
                dnskw_init();
@@ -148,14 +144,12 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("usi,topkick"))
                usi_topkick_init();
-        if (of_machine_is_compatible("zyxel,nsa310"))
-                nsa310_init();
        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 static const char * const kirkwood_dt_board_compat[] = {
        "globalscale,dreamplug",
+        "globalscale,guruplug",
        "dlink,dns-320",
        "dlink,dns-325",
        "iom,iconnect",
@@ -183,7 +177,7 @@ DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = orion_dt_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .init_machine   = kirkwood_dt_init,
        .restart        = kirkwood_restart,
        .dt_compat      = kirkwood_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
new file mode 100644
index 000000000000..0a0df4554d8b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-kirkwood/board-guruplug.c
+ *
+ * Marvell Guruplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+static struct mv643xx_eth_platform_data guruplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static struct mv643xx_eth_platform_data guruplug_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
+};
+static struct mvsdio_platform_data guruplug_mvsdio_data = {
+        /* unfortunately the CD signal has not been connected */
+};
+void __init guruplug_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_ge00_init(&guruplug_ge00_data);
+        kirkwood_ge01_init(&guruplug_ge01_data);
+        kirkwood_sdio_init(&guruplug_mvsdio_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index 9f6f496380d8..9a857ae83984 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/input.h>
 #include "common.h"
 static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 56bfe5a1605a..7d6dc669e17f 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -12,9 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
@@ -24,11 +22,6 @@ static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(2),
 };
-static struct mvsdio_platform_data mplcec4_mvsdio_data = {
-        .gpio_card_detect = 47, /* MPP47 used as SD card detect */
-};
 void __init mplcec4_init(void)
 {
        /*
@@ -36,7 +29,6 @@ void __init mplcec4_init(void)
         */
        kirkwood_ge00_init(&mplcec4_ge00_data);
        kirkwood_ge01_init(&mplcec4_ge01_data);
-        kirkwood_sdio_init(&mplcec4_mvsdio_data);
        kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index f4632a809f68..f2ea3b7ad726 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 #include "common.h"
@@ -23,13 +22,6 @@ static struct mv643xx_eth_platform_data ns2_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-#define NS2_GPIO_POWER_OFF      31
-static void ns2_power_off(void)
-{
-        gpio_set_value(NS2_GPIO_POWER_OFF, 1);
-}
 void __init ns2_init(void)
 {
        /*
@@ -39,10 +31,4 @@ void __init ns2_init(void)
            of_machine_is_compatible("lacie,netspace_mini_v2"))
                ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
        kirkwood_ge00_init(&ns2_ge00_data);
-        if (gpio_request(NS2_GPIO_POWER_OFF, "power-off") == 0 &&
-            gpio_direction_output(NS2_GPIO_POWER_OFF, 0) == 0)
-                pm_power_off = ns2_power_off;
-        else
-                pr_err("ns2: failed to configure power-off GPIO\n");
 }
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
index f58d2e1a4042..55ade93b93bf 100644
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ b/arch/arm/mach-kirkwood/board-nsa310.c
@@ -10,85 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
+#include <linux/of.h>
 #include "common.h"
-#include "mpp.h"
-#define NSA310_GPIO_USB_POWER_OFF       21
-#define NSA310_GPIO_POWER_OFF           48
-static unsigned int nsa310_mpp_config[] __initdata = {
-        MPP12_GPIO, /* led esata green */
-        MPP13_GPIO, /* led esata red */
-        MPP15_GPIO, /* led usb green */
-        MPP16_GPIO, /* led usb red */
-        MPP21_GPIO, /* control usb power off */
-        MPP28_GPIO, /* led sys green */
-        MPP29_GPIO, /* led sys red */
-        MPP36_GPIO, /* key reset */
-        MPP37_GPIO, /* key copy */
-        MPP39_GPIO, /* led copy green */
-        MPP40_GPIO, /* led copy red */
-        MPP41_GPIO, /* led hdd green */
-        MPP42_GPIO, /* led hdd red */
-        MPP44_GPIO, /* ?? */
-        MPP46_GPIO, /* key power */
-        MPP48_GPIO, /* control power off */
-        0
-};
-static struct i2c_board_info __initdata nsa310_i2c_info[] = {
-        { I2C_BOARD_INFO("adt7476", 0x2e) },
-};
-static void nsa310_power_off(void)
-{
-        gpio_set_value(NSA310_GPIO_POWER_OFF, 1);
-}
-static int __init nsa310_gpio_request(unsigned int gpio, unsigned long flags,
-                                       const char *label)
-{
-        int err;
-        err = gpio_request_one(gpio, flags, label);
-        if (err)
-                pr_err("NSA-310: can't setup GPIO%u (%s), err=%d\n",
-                        gpio, label, err);
-        return err;
-}
-static void __init nsa310_gpio_init(void)
-{
-        int err;
-        err = nsa310_gpio_request(NSA310_GPIO_POWER_OFF, GPIOF_OUT_INIT_LOW,
-                                  "Power Off");
-        if (!err)
-                pm_power_off = nsa310_power_off;
-        nsa310_gpio_request(NSA310_GPIO_USB_POWER_OFF, GPIOF_OUT_INIT_LOW,
-                            "USB Power Off");
-}
-void __init nsa310_init(void)
-{
-        u32 dev, rev;
-        kirkwood_mpp_conf(nsa310_mpp_config);
-        nsa310_gpio_init();
-        kirkwood_pcie_id(&dev, &rev);
-        i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info));
-}
 static int __init nsa310_pci_init(void)
 {
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
index 815fc6451d52..b11d8fdeca93 100644
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
@@ -11,60 +11,16 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/clk.h>
-#include <linux/clk-private.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data openblocks_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
-static unsigned int openblocks_a6_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_NF_IO3,
-        MPP2_NF_IO4,
-        MPP3_NF_IO5,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP6_SYSRST_OUTn,
-        MPP8_UART1_RTS,
-        MPP9_UART1_CTS,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_UART1_TXD,
-        MPP14_UART1_RXD,
-        MPP15_UART0_RTS,
-        MPP16_UART0_CTS,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP20_GPIO, /* DIP SW0 */
-        MPP21_GPIO, /* DIP SW1 */
-        MPP22_GPIO, /* DIP SW2 */
-        MPP23_GPIO, /* DIP SW3 */
-        MPP24_GPIO, /* GPIO 0 */
-        MPP25_GPIO, /* GPIO 1 */
-        MPP26_GPIO, /* GPIO 2 */
-        MPP27_GPIO, /* GPIO 3 */
-        MPP28_GPIO, /* GPIO 4 */
-        MPP29_GPIO, /* GPIO 5 */
-        MPP30_GPIO, /* GPIO 6 */
-        MPP31_GPIO, /* GPIO 7 */
-        MPP36_TW1_SDA,
-        MPP37_TW1_SCK,
-        MPP38_GPIO, /* INIT */
-        MPP39_GPIO, /* USB OC */
-        MPP41_GPIO, /* LED: Red */
-        MPP42_GPIO, /* LED: Green */
-        MPP43_GPIO, /* LED: Yellow */
-        0,
-};
 void __init openblocks_a6_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(openblocks_a6_mpp_config);
        kirkwood_ge00_init(&openblocks_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
index 23d2dd1b1b1e..1cc04ec33f0b 100644
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ b/arch/arm/mach-kirkwood/board-usi_topkick.c
@@ -14,64 +14,16 @@
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data topkick_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
-static struct mvsdio_platform_data topkick_mvsdio_data = {
-        /* unfortunately the CD signal has not been connected */
-};
-/*
- * GPIO LED layout
- *
- *       /-SYS_LED(2)
- *       |
- *       |   /-DISK_LED
- *       |   |
- *       |   |   /-WLAN_LED(2)
- *       |   |   |
- * [SW] [*] [*] [*]
- */
-/*
- * Switch positions
- *
- *     /-SW_LEFT
- *     |
- *     |   /-SW_IDLE
- *     |   |
- *     |   |   /-SW_RIGHT
- *     |   |   |
- * PS [L] [I] [R] LEDS
- */
-static unsigned int topkick_mpp_config[] __initdata = {
-        MPP21_GPIO,     /* DISK_LED           (low active) - yellow */
-        MPP36_GPIO,     /* SATA0 power enable (high active) */
-        MPP37_GPIO,     /* SYS_LED2           (low active) - red */
-        MPP38_GPIO,     /* SYS_LED            (low active) - blue */
-        MPP39_GPIO,     /* WLAN_LED           (low active) - green */
-        MPP43_GPIO,     /* SW_LEFT            (low active) */
-        MPP44_GPIO,     /* SW_RIGHT           (low active) */
-        MPP45_GPIO,     /* SW_IDLE            (low active) */
-        MPP46_GPIO,     /* SW_LEFT            (low active) */
-        MPP48_GPIO,     /* WLAN_LED2          (low active) - yellow */
-        0
-};
 void __init usi_topkick_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(topkick_mpp_config);
        kirkwood_ge00_init(&topkick_ge00_data);
-        kirkwood_sdio_init(&topkick_mvsdio_data);
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index bac21a554c91..49792a0cd2d3 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -499,6 +499,28 @@ void __init kirkwood_wdt_init(void)
        orion_wdt_init();
 }
+/*****************************************************************************
+ * CPU idle
+ ****************************************************************************/
+static struct resource kirkwood_cpuidle_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = DDR_OPERATION_BASE,
+                .end    = DDR_OPERATION_BASE + 3,
+        },
+};
+static struct platform_device kirkwood_cpuidle = {
+        .name           = "kirkwood_cpuidle",
+        .id             = -1,
+        .resource       = kirkwood_cpuidle_resource,
+        .num_resources  = 1,
+};
+void __init kirkwood_cpuidle_init(void)
+{
+        platform_device_register(&kirkwood_cpuidle);
+}
 /*****************************************************************************
 * Time handling
@@ -530,7 +552,7 @@ static int __init kirkwood_find_tclk(void)
        return 166666667;
 }
-static void __init kirkwood_timer_init(void)
+void __init kirkwood_timer_init(void)
 {
        kirkwood_tclk = kirkwood_find_tclk();
@@ -538,10 +560,6 @@ static void __init kirkwood_timer_init(void)
                        IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
-struct sys_timer kirkwood_timer = {
-        .init = kirkwood_timer_init,
-};
 /*****************************************************************************
 * Audio
 ****************************************************************************/
@@ -671,6 +689,7 @@ void __init kirkwood_init(void)
        kirkwood_xor1_init();
        kirkwood_crypto_init();
+        kirkwood_cpuidle_init();
 #ifdef CONFIG_KEXEC
        kexec_reinit = kirkwood_enable_pcie;
 #endif
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ffa57f08c80..5ed70565c843 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -50,6 +50,7 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
 void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
                            int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
+void kirkwood_cpuidle_init(void);
 void kirkwood_restart(char, const char *);
 void kirkwood_clk_init(void);
@@ -59,6 +60,11 @@ void dreamplug_init(void);
 #else
 static inline void dreamplug_init(void) {};
 #endif
+#ifdef CONFIG_MACH_GURUPLUG_DT
+void guruplug_dt_init(void);
+#else
+static inline void guruplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
@@ -129,12 +135,6 @@ void ns2_init(void);
 static inline void ns2_init(void) {};
 #endif
-#ifdef CONFIG_MACH_NSA310_DT
-void nsa310_init(void);
-#else
-static inline void nsa310_init(void) {};
-#endif
 #ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
 void openblocks_a6_init(void);
 #else
@@ -156,7 +156,7 @@ void kirkwood_xor1_init(void);
 void kirkwood_crypto_init(void);
 extern int kirkwood_tclk;
-extern struct sys_timer kirkwood_timer;
+extern void kirkwood_timer_init(void);
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c
deleted file mode 100644
index f7304670f2f8..000000000000
--- a/arch/arm/mach-kirkwood/cpuidle.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/cpuidle.c
- *
- * CPU idle Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * The cpu idle uses wait-for-interrupt and DDR self refresh in order
- * to implement two idle states -
- * #1 wait-for-interrupt
- * #2 wait-for-interrupt and DDR self refresh
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/cpuidle.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <asm/proc-fns.h>
-#include <asm/cpuidle.h>
-#include <mach/kirkwood.h>
-#define KIRKWOOD_MAX_STATES     2
-/* Actual code that puts the SoC in different idle states */
-static int kirkwood_enter_idle(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                               int index)
-{
-        writel(0x7, DDR_OPERATION_BASE);
-        cpu_do_idle();
-        return index;
-}
-static struct cpuidle_driver kirkwood_idle_driver = {
-        .name                   = "kirkwood_idle",
-        .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
-        .states[0]              = ARM_CPUIDLE_WFI_STATE,
-        .states[1]              = {
-                .enter                  = kirkwood_enter_idle,
-                .exit_latency           = 10,
-                .target_residency       = 100000,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "DDR SR",
-                .desc                   = "WFI and DDR Self Refresh",
-        },
-        .state_count = KIRKWOOD_MAX_STATES,
-};
-static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
-/* Initialize CPU idle by registering the idle states */
-static int kirkwood_init_cpuidle(void)
-{
-        struct cpuidle_device *device;
-        device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
-        device->state_count = KIRKWOOD_MAX_STATES;
-        cpuidle_register_driver(&kirkwood_idle_driver);
-        if (cpuidle_register_device(device)) {
-                pr_err("kirkwood_init_cpuidle: Failed registering\n");
-                return -EIO;
-        }
-        return 0;
-}
-device_initcall(kirkwood_init_cpuidle);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 2c1a453df201..453418063c1e 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -226,6 +226,6 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index c49b177c1523..5a369fe74754 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -103,6 +103,6 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 791a98fafa29..060ccf9cb63f 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -19,7 +19,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -107,6 +106,6 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 7cb55f982243..1c6e736cbbf8 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -126,6 +126,6 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 041653a04a9c..a05563a31c95 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -60,8 +60,9 @@
 * Register Map
 */
 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
+#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
 #define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
-#define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
+#define DDR_OPERATION_BASE      (DDR_PHYS_BASE + 0x1418)
 #define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
diff --git a/arch/arm/mach-kirkwood/include/mach/uncompress.h b/arch/arm/mach-kirkwood/include/mach/uncompress.h
index 75d5497df3a8..5bca5534021f 100644
--- a/arch/arm/mach-kirkwood/include/mach/uncompress.h
+++ b/arch/arm/mach-kirkwood/include/mach/uncompress.h
@@ -44,4 +44,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 6d8364a97810..ba384b992bef 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -167,6 +167,6 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 728e86d33f0c..3b706611da8e 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -263,7 +263,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -275,7 +275,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -287,7 +287,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index a3b091470b8a..913d032cdb19 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -404,7 +404,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -416,7 +416,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 7e81e9b586bf..8ddd69fdc937 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -221,7 +221,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -234,7 +234,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -247,7 +247,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index a1c3ab6fc809..d96ad4c09972 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -247,13 +247,9 @@ static struct hw_pci kirkwood_pci __initdata = {
 static void __init add_pcie_port(int index, void __iomem *base)
 {
-        pr_info("Kirkwood PCIe port %d: ", index);
+        pcie_port_map[num_pcie_ports++] = index;
+        pr_info("Kirkwood PCIe port %d: link %s\n", index,
-        if (orion_pcie_link_up(base)) {
+                orion_pcie_link_up(base) ? "up" : "down");
-                pr_info("link up\n");
-                pcie_port_map[num_pcie_ports++] = index;
-        } else
-                pr_info("link down, ignoring\n");
 }
 void __init kirkwood_pcie_init(unsigned int portmask)
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 19072c84008f..e4fd3129d36f 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -84,6 +84,6 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 9717101a7437..c7d93b48926b 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -120,6 +120,6 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 8a175948b28d..55b68fa39f45 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -143,7 +143,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -155,7 +155,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index f2daf711e72e..8736f8c97518 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -211,6 +211,6 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 73e2b6ca9564..283abff90228 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -137,6 +137,6 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index e4c61279ea86..81d585806b2f 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -181,6 +181,6 @@ MACHINE_START(TS41X, "QNAP TS-41x")
        .map_io         = kirkwood_map_io,
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
-        .timer          = &kirkwood_timer,
+        .init_time      = kirkwood_timer_init,
        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index b0c306ccbc6e..456d6386edf8 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -227,6 +227,6 @@ MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = acs5k_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index e0d36cef2c56..d37c218c3584 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -125,6 +125,6 @@ MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = dsm320_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index a8270725b76d..3acbdfd31391 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -57,6 +57,6 @@ MACHINE_START(KS8695, "KS8695 Centaur Development Board")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = micrel_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c
index 1623ba461e47..002bc619bb68 100644
--- a/arch/arm/mach-ks8695/board-og.c
+++ b/arch/arm/mach-ks8695/board-og.c
@@ -145,7 +145,7 @@ MACHINE_START(CM4002, "OpenGear/CM4002")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = og_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -157,7 +157,7 @@ MACHINE_START(CM4008, "OpenGear/CM4008")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = og_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -169,7 +169,7 @@ MACHINE_START(CM41XX, "OpenGear/CM41xx")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = og_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -181,7 +181,7 @@ MACHINE_START(IM4004, "OpenGear/IM4004")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = og_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -193,7 +193,7 @@ MACHINE_START(IM42XX, "OpenGear/IM42xx")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = og_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ks8695/board-sg.c b/arch/arm/mach-ks8695/board-sg.c
index f35b98b5bf37..fdf2352d2cf8 100644
--- a/arch/arm/mach-ks8695/board-sg.c
+++ b/arch/arm/mach-ks8695/board-sg.c
@@ -91,7 +91,7 @@ MACHINE_START(LITE300, "SecureComputing/SG300")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = sg_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -103,7 +103,7 @@ MACHINE_START(SG310, "McAfee/SG310")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = sg_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
@@ -115,7 +115,7 @@ MACHINE_START(SE4200, "SecureComputing/SE4200")
        .map_io         = ks8695_map_io,
        .init_irq       = ks8695_init_irq,
        .init_machine   = sg_init,
-        .timer          = &ks8695_timer,
+        .init_time      = ks8695_timer_init,
        .restart        = ks8695_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index f8bdb11a9c33..6e97ce462d73 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -13,4 +13,4 @@
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
 extern void ks8695_restart(char, const char *);
-extern struct sys_timer ks8695_timer;
+extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 8879d610308a..c089a1aea674 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -32,6 +32,5 @@ static inline void flush(void)
 }
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 46c84bc7792c..c272a3863d5f 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -146,7 +146,7 @@ static void ks8695_timer_setup(void)
                                        0xFFFFFFFFU);
 }
-static void __init ks8695_timer_init (void)
+void __init ks8695_timer_init(void)
 {
        ks8695_timer_setup();
@@ -154,10 +154,6 @@ static void __init ks8695_timer_init (void)
        setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
-struct sys_timer ks8695_timer = {
-        .init           = ks8695_timer_init,
-};
 void ks8695_restart(char mode, const char *cmd)
 {
        unsigned int reg;
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index afeac3b1fae6..e0b26062a272 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -25,7 +25,7 @@
 /*
 * Other arch specific structures and functions
 */
-extern struct sys_timer lpc32xx_timer;
+extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
index c142487d299a..1198a89183cd 100644
--- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -55,6 +55,5 @@ static inline void flush(void)
 /* NULL functions; we don't presently need them */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index e8ff4c3f0566..c1cd5a943ab1 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -263,7 +263,7 @@ DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
        .atag_offset    = 0x100,
        .map_io         = lpc32xx_map_io,
        .init_irq       = lpc32xx_init_irq,
-        .timer          = &lpc32xx_timer,
+        .init_time      = lpc32xx_timer_init,
        .init_machine   = lpc3250_machine_init,
        .dt_compat      = lpc32xx_dt_compat,
        .restart        = lpc23xx_restart,
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index c40667c33161..20eab63d10ba 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -70,7 +70,6 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
 static struct clock_event_device lpc32xx_clkevt = {
        .name           = "lpc32xx_clkevt",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .rating         = 300,
        .set_next_event = lpc32xx_clkevt_next_event,
        .set_mode       = lpc32xx_clkevt_mode,
@@ -100,7 +99,7 @@ static struct irqaction lpc32xx_timer_irq = {
 * clocks need to be enabled here manually and then tagged as used in
 * the clock driver initialization
 */
-static void __init lpc32xx_timer_init(void)
+void __init lpc32xx_timer_init(void)
 {
        u32 clkrate, pllreg;
@@ -141,14 +140,8 @@ static void __init lpc32xx_timer_init(void)
        setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
        /* Setup the clockevent structure. */
-        lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
-                lpc32xx_clkevt.shift);
-        lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
-                &lpc32xx_clkevt);
-        lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
-                &lpc32xx_clkevt) + 1;
        lpc32xx_clkevt.cpumask = cpumask_of(0);
-        clockevents_register_device(&lpc32xx_clkevt);
+        clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
        /* Use timer1 as clock source. */
        __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
@@ -161,8 +154,3 @@ static void __init lpc32xx_timer_init(void)
        clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
                "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 }
-struct sys_timer lpc32xx_timer = {
-        .init           = &lpc32xx_timer_init,
-};
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index e5dba9c5dc54..9f64d5632e07 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -262,7 +262,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa168_init_irq,
-        .timer          = &pxa168_timer,
+        .init_time      = pxa168_timer_init,
        .init_machine   = common_init,
        .restart        = pxa168_restart,
 MACHINE_END
@@ -271,7 +271,7 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa168_init_irq,
-        .timer          = &pxa168_timer,
+        .init_time      = pxa168_timer_init,
        .init_machine   = common_init,
        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 603542ae6fbd..1f94957b56ae 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -45,7 +45,7 @@ MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa168_init_irq,
-        .timer          = &pxa168_timer,
+        .init_time      = pxa168_timer_init,
        .init_machine   = avengers_lite_init,
        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 5cb769cd26d9..2358011c7d8e 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -218,7 +218,7 @@ MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = BROWNSTONE_NR_IRQS,
        .init_irq       = mmp2_init_irq,
-        .timer          = &mmp2_timer,
+        .init_time      = mmp2_timer_init,
        .init_machine   = brownstone_init,
        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index bd453274fca2..0bdc50b134ce 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,7 +1,5 @@
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-struct sys_timer;
 extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index 8059cc0905c6..754c352dd02b 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -121,7 +121,7 @@ MACHINE_START(FLINT, "Flint Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = FLINT_NR_IRQS,
        .init_irq       = mmp2_init_irq,
-        .timer          = &mmp2_timer,
+        .init_time      = mmp2_timer_init,
        .init_machine   = flint_init,
        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 5c3d61ee729a..d1e2d595e79c 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -194,7 +194,7 @@ MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa168_init_irq,
-        .timer          = &pxa168_timer,
+        .init_time      = pxa168_timer_init,
        .init_machine   = gplugd_init,
        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index c4ca4d17194a..0764f4ecec82 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -3,9 +3,7 @@
 #include <linux/platform_data/pxa_sdhci.h>
-struct sys_timer;
+extern void mmp2_timer_init(void);
-extern struct sys_timer mmp2_timer;
 extern void __init mmp2_init_icu(void);
 extern void __init mmp2_init_irq(void);
 extern void mmp2_clear_pmic_int(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 37632d964d50..7ed1df21ea1c 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,7 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
-struct sys_timer;
+extern void pxa168_timer_init(void);
-extern struct sys_timer pxa168_timer;
 extern void __init pxa168_init_irq(void);
 extern void pxa168_restart(char, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 3b58a3b2d7df..b914afa1fcdc 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -1,15 +1,14 @@
 #ifndef __ASM_MACH_PXA910_H
 #define __ASM_MACH_PXA910_H
-struct sys_timer;
+extern void pxa910_timer_init(void);
-extern struct sys_timer pxa910_timer;
 extern void __init pxa910_init_irq(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
 #include <linux/platform_data/mtd-nand-pxa3xx.h>
+#include <video/mmp_disp.h>
 extern struct pxa_device_desc pxa910_device_uart1;
 extern struct pxa_device_desc pxa910_device_uart2;
@@ -23,7 +22,9 @@ extern struct pxa_device_desc pxa910_device_nand;
 extern struct platform_device pxa168_device_u2o;
 extern struct platform_device pxa168_device_u2ootg;
 extern struct platform_device pxa168_device_u2oehci;
+extern struct pxa_device_desc pxa910_device_disp;
+extern struct pxa_device_desc pxa910_device_fb;
+extern struct pxa_device_desc pxa910_device_panel;
 extern struct platform_device pxa910_device_gpio;
 extern struct platform_device pxa910_device_rtc;
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index d6daeb7e4ef1..8890fa8fa771 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -43,9 +43,3 @@ static inline void arch_decomp_setup(void)
        if (machine_is_avengers_lite())
                UART = (unsigned long *)UART3_BASE;
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index ff73249884d0..66634fd0ecb0 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -174,7 +174,7 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = JASPER_NR_IRQS,
        .init_irq       = mmp2_init_irq,
-        .timer          = &mmp2_timer,
+        .init_time      = mmp2_timer_init,
        .init_machine   = jasper_init,
        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 033cc31b3c72..d063efa0a4f1 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -22,10 +22,6 @@
 extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
-static struct sys_timer mmp_dt_timer = {
-        .init   = mmp_dt_init_timer,
-};
 static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
@@ -69,7 +65,7 @@ static const char *mmp_dt_board_compat[] __initdata = {
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
        .map_io         = mmp_map_io,
        .init_irq       = mmp_dt_irq_init,
-        .timer          = &mmp_dt_timer,
+        .init_time      = mmp_dt_init_timer,
        .init_machine   = pxa168_dt_init,
        .dt_compat      = mmp_dt_board_compat,
 MACHINE_END
@@ -77,7 +73,7 @@ MACHINE_END
 DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
        .map_io         = mmp_map_io,
        .init_irq       = mmp_dt_irq_init,
-        .timer          = &mmp_dt_timer,
+        .init_time      = mmp_dt_init_timer,
        .init_machine   = pxa910_dt_init,
        .dt_compat      = mmp_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 535a5ed5977b..fad431aa6e09 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -24,10 +24,6 @@
 extern void __init mmp_dt_irq_init(void);
 extern void __init mmp_dt_init_timer(void);
-static struct sys_timer mmp_dt_timer = {
-        .init   = mmp_dt_init_timer,
-};
 static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
@@ -54,7 +50,7 @@ static const char *mmp2_dt_board_compat[] __initdata = {
 DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
        .map_io         = mmp_map_io,
        .init_irq       = mmp_dt_irq_init,
-        .timer          = &mmp_dt_timer,
+        .init_time      = mmp_dt_init_timer,
        .init_machine   = mmp2_dt_init,
        .dt_compat      = mmp2_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 3a3768c7a191..d94d114eef7b 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -114,7 +114,7 @@ postcore_initcall(mmp2_init);
 #define APBC_TIMERS     APBC_REG(0x024)
-static void __init mmp2_timer_init(void)
+void __init mmp2_timer_init(void)
 {
        unsigned long clk_rst;
@@ -130,10 +130,6 @@ static void __init mmp2_timer_init(void)
        timer_init(IRQ_MMP2_TIMER1);
 }
-struct sys_timer mmp2_timer = {
-        .init   = mmp2_timer_init,
-};
 /* on-chip devices */
 MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
 MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index b7f074f15498..9bc7b86a86a7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -67,7 +67,7 @@ postcore_initcall(pxa168_init);
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
 #define APBC_TIMERS     APBC_REG(0x34)
-static void __init pxa168_timer_init(void)
+void __init pxa168_timer_init(void)
 {
        /* this is early, we have to initialize the CCU registers by
         * ourselves instead of using clk_* API. Clock rate is defined
@@ -81,10 +81,6 @@ static void __init pxa168_timer_init(void)
        timer_init(IRQ_PXA168_TIMER1);
 }
-struct sys_timer pxa168_timer = {
-        .init   = pxa168_timer_init,
-};
 void pxa168_clear_keypad_wakeup(void)
 {
        uint32_t val;
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 8b1e16fbb7a5..36cb321a3d70 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -101,7 +101,7 @@ postcore_initcall(pxa910_init);
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
 #define APBC_TIMERS     APBC_REG(0x34)
-static void __init pxa910_timer_init(void)
+void __init pxa910_timer_init(void)
 {
        /* reset and configure */
        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
@@ -110,10 +110,6 @@ static void __init pxa910_timer_init(void)
        timer_init(IRQ_PXA910_AP1_TIMER1);
 }
-struct sys_timer pxa910_timer = {
-        .init   = pxa910_timer_init,
-};
 /* on-chip devices */
 /* NOTE: there are totally 3 UARTs on PXA910:
@@ -138,6 +134,9 @@ PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
 PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
+PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
+PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
+PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
 struct resource pxa910_resource_gpio[] = {
        {
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index b28f9084dfff..4c127d23955d 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -103,7 +103,7 @@ MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa910_init_irq,
-        .timer          = &pxa910_timer,
+        .init_time      = pxa910_timer_init,
        .init_machine   = tavorevb_init,
        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index dd30ea74785c..8609967975ed 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -86,7 +86,7 @@ MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = MMP_NR_IRQS,
        .init_irq       = pxa168_init_irq,
-        .timer          = &pxa168_timer,
+        .init_time      = pxa168_timer_init,
        .init_machine   = teton_bga_init,
        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 936447c70977..86a18b3d252e 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -141,7 +141,6 @@ static void timer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device ckevt = {
        .name           = "clockevent",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .rating         = 200,
        .set_next_event = timer_set_next_event,
        .set_mode       = timer_set_mode,
@@ -198,15 +197,13 @@ void __init timer_init(int irq)
        setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
-        ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
-        ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
-        ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
        ckevt.cpumask = cpumask_of(0);
        setup_irq(irq, &timer_irq);
        clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
-        clockevents_register_device(&ckevt);
+        clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE,
+                                        MIN_DELTA, MAX_DELTA);
 }
 #ifdef CONFIG_OF
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ce55fd8821c4..22a9058f9f4d 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/mfd/88pm860x.h>
 #include <linux/platform_data/mv_usb.h>
+#include <linux/spi/spi.h>
+#include <linux/delay.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -184,6 +186,92 @@ static struct pxa3xx_nand_platform_data dkb_nand_info = {
 };
 #endif
+#ifdef CONFIG_MMP_DISP
+/* path config */
+#define CFG_IOPADMODE(iopad)   (iopad)  /* 0x0 ~ 0xd */
+#define SCLK_SOURCE_SELECT(x)  (x << 30) /* 0x0 ~ 0x3 */
+/* link config */
+#define CFG_DUMBMODE(mode)     (mode << 28) /* 0x0 ~ 0x6*/
+#define CFG_GRA_SWAPRB(x)      (x << 0) /* 1: rbswap enabled */
+static struct mmp_mach_path_config dkb_disp_config[] = {
+        [0] = {
+                .name = "mmp-parallel",
+                .overlay_num = 2,
+                .output_type = PATH_OUT_PARALLEL,
+                .path_config = CFG_IOPADMODE(0x1)
+                        | SCLK_SOURCE_SELECT(0x1),
+                .link_config = CFG_DUMBMODE(0x2)
+                        | CFG_GRA_SWAPRB(0x1),
+        },
+};
+static struct mmp_mach_plat_info dkb_disp_info = {
+        .name = "mmp-disp",
+        .clk_name = "disp0",
+        .path_num = 1,
+        .paths = dkb_disp_config,
+};
+static struct mmp_buffer_driver_mach_info dkb_fb_info = {
+        .name = "mmp-fb",
+        .path_name = "mmp-parallel",
+        .overlay_id = 0,
+        .dmafetch_id = 1,
+        .default_pixfmt = PIXFMT_RGB565,
+};
+static void dkb_tpo_panel_power(int on)
+{
+        int err;
+        u32 spi_reset = mfp_to_gpio(MFP_PIN_GPIO106);
+        if (on) {
+                err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
+                if (err) {
+                        pr_err("failed to request GPIO for TPO LCD RESET\n");
+                        return;
+                }
+                gpio_direction_output(spi_reset, 0);
+                udelay(100);
+                gpio_set_value(spi_reset, 1);
+                gpio_free(spi_reset);
+        } else {
+                err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
+                if (err) {
+                        pr_err("failed to request LCD RESET gpio\n");
+                        return;
+                }
+                gpio_set_value(spi_reset, 0);
+                gpio_free(spi_reset);
+        }
+}
+static struct mmp_mach_panel_info dkb_tpo_panel_info = {
+        .name = "tpo-hvga",
+        .plat_path_name = "mmp-parallel",
+        .plat_set_onoff = dkb_tpo_panel_power,
+};
+static struct spi_board_info spi_board_info[] __initdata = {
+        {
+                .modalias       = "tpo-hvga",
+                .platform_data  = &dkb_tpo_panel_info,
+                .bus_num        = 5,
+        }
+};
+static void __init add_disp(void)
+{
+        pxa_register_device(&pxa910_device_disp,
+                &dkb_disp_info, sizeof(dkb_disp_info));
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+        pxa_register_device(&pxa910_device_fb,
+                &dkb_fb_info, sizeof(dkb_fb_info));
+        pxa_register_device(&pxa910_device_panel,
+                &dkb_tpo_panel_info, sizeof(dkb_tpo_panel_info));
+}
+#endif
 static void __init ttc_dkb_init(void)
 {
        mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -212,13 +300,17 @@ static void __init ttc_dkb_init(void)
        pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
        platform_device_register(&pxa168_device_u2ootg);
 #endif
+#ifdef CONFIG_MMP_DISP
+        add_disp();
+#endif
 }
 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
        .map_io         = mmp_map_io,
        .nr_irqs        = TTCDKB_NR_IRQS,
        .init_irq       = pxa910_init_irq,
-        .timer          = &pxa910_timer,
+        .init_time      = pxa910_timer_init,
        .init_machine   = ttc_dkb_init,
        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index b5b4de2cdf9e..7dcfc5300bbd 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -11,26 +11,15 @@
 */
 #include <linux/init.h>
+#include <linux/irqchip.h>
 #include <linux/of.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <mach/board.h>
 #include "common.h"
-static const struct of_device_id msm_dt_gic_match[] __initconst = {
-        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
-        {}
-};
-static void __init msm8x60_init_irq(void)
-{
-        of_irq_init(msm_dt_gic_match);
-}
 static void __init msm8x60_init_late(void)
 {
        smd_debugfs_init();
@@ -55,10 +44,9 @@ static const char *msm8x60_fluid_match[] __initdata = {
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
        .smp = smp_ops(msm_smp_ops),
        .map_io = msm_map_msm8x60_io,
-        .init_irq = msm8x60_init_irq,
+        .init_irq = irqchip_init,
-        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_dt_init,
        .init_late = msm8x60_init_late,
-        .timer = &msm_dt_timer,
+        .init_time      = msm_dt_timer_init,
        .dt_compat = msm8x60_fluid_match,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index 4490edb71c17..73019363ffa4 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -11,24 +11,13 @@
 */
 #include <linux/init.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include "common.h"
-static const struct of_device_id msm_dt_gic_match[] __initconst = {
-        { .compatible = "qcom,msm-qgic2", .data = gic_of_init },
-        { }
-};
-static void __init msm_dt_init_irq(void)
-{
-        of_irq_init(msm_dt_gic_match);
-}
 static void __init msm_dt_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -42,9 +31,8 @@ static const char * const msm8960_dt_match[] __initconst = {
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
        .smp = smp_ops(msm_smp_ops),
        .map_io = msm_map_msm8960_io,
-        .init_irq = msm_dt_init_irq,
+        .init_irq = irqchip_init,
-        .timer = &msm_dt_timer,
+        .init_time      = msm_dt_timer_init,
        .init_machine = msm_dt_init,
        .dt_compat = msm8960_dt_match,
-        .handle_irq = gic_handle_irq,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 6ce542e2e21c..84d720af34ab 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -106,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
        .init_irq       = halibut_init_irq,
        .init_machine   = halibut_init,
        .init_late      = halibut_init_late,
-        .timer          = &msm7x01_timer,
+        .init_time      = msm7x01_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index df00bc03ce74..30c3496db593 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -75,7 +75,7 @@ static void __init mahimahi_init_late(void)
        smd_debugfs_init();
 }
-extern struct sys_timer msm_timer;
+void msm_timer_init(void);
 MACHINE_START(MAHIMAHI, "mahimahi")
        .atag_offset    = 0x100,
@@ -84,5 +84,5 @@ MACHINE_START(MAHIMAHI, "mahimahi")
        .init_irq       = msm_init_irq,
        .init_machine   = mahimahi_init,
        .init_late      = mahimahi_init_late,
-        .timer          = &msm_timer,
+        .init_time      = msm_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index effa6f4336c7..7bc3f82e3ec9 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -131,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm7x30_timer,
+        .init_time      = msm7x30_timer_init,
 MACHINE_END
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -142,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm7x30_timer,
+        .init_time      = msm7x30_timer_init,
 MACHINE_END
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -153,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm7x30_timer,
+        .init_time      = msm7x30_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 2448fcf09eb1..686e7949a73a 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -200,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
        .init_irq = qsd8x50_init_irq,
        .init_machine = qsd8x50_init,
        .init_late = qsd8x50_init_late,
-        .timer = &qsd8x50_timer,
+        .init_time      = qsd8x50_timer_init,
 MACHINE_END
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
@@ -209,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
        .init_irq = qsd8x50_init_irq,
        .init_machine = qsd8x50_init,
        .init_late = qsd8x50_init_late,
-        .timer = &qsd8x50_timer,
+        .init_time      = qsd8x50_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index b7b0fc7e3278..70730111b37c 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -53,7 +53,7 @@ static struct platform_device *devices[] __initdata = {
        &msm_device_uart3,
 };
-extern struct sys_timer msm_timer;
+void msm_timer_init(void);
 static void __init sapphire_init_irq(void)
 {
@@ -113,5 +113,5 @@ MACHINE_START(SAPPHIRE, "sapphire")
        .init_irq       = sapphire_init_irq,
        .init_machine   = sapphire_init,
        .init_late      = sapphire_init_late,
-        .timer          = &msm_timer,
+        .init_time      = msm_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 4ba0800e243e..919bfa32871a 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -110,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream")
        .init_irq       = trout_init_irq,
        .init_machine   = trout_init,
        .init_late      = trout_init_late,
-        .timer          = &msm7x01_timer,
+        .init_time      = msm7x01_timer_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 633a7159d5ff..ce8215a269e5 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -12,10 +12,10 @@
 #ifndef __MACH_COMMON_H
 #define __MACH_COMMON_H
-extern struct sys_timer msm7x01_timer;
+extern void msm7x01_timer_init(void);
-extern struct sys_timer msm7x30_timer;
+extern void msm7x30_timer_init(void);
-extern struct sys_timer msm_dt_timer;
+extern void msm_dt_timer_init(void);
-extern struct sys_timer qsd8x50_timer;
+extern void qsd8x50_timer_init(void);
 extern void msm_map_common_io(void);
 extern void msm_map_msm7x30_io(void);
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index c14011fe832d..fa97a10d8695 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -60,8 +60,4 @@ static inline void arch_decomp_setup(void)
 {
 }
-static inline void arch_decomp_wdog(void)
-{
-}
 #endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 7ed69b69c87c..42932865416a 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -15,8 +15,8 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
-#include <asm/hardware/gic.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <asm/mach-types.h>
@@ -115,7 +115,7 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id
         * the boot monitor to read the system wide flags register,
         * and branch to the address found there.
         */
-        gic_raise_softirq(cpumask_of(cpu), 0);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
@@ -153,8 +153,6 @@ static void __init msm_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h
index 12da4cacd4a8..e8d043a0e990 100644
--- a/arch/arm/mach-msm/proc_comm.h
+++ b/arch/arm/mach-msm/proc_comm.h
@@ -253,6 +253,6 @@ enum {
                (((drvstr) & 0xF) << 17))
 int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
-void __init proc_comm_boot_wait(void);
+void proc_comm_boot_wait(void);
 #endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 476549a8a709..2969027f02fa 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -25,7 +25,6 @@
 #include <linux/of_irq.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
@@ -144,13 +143,9 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
        evt->rating = msm_clockevent.rating;
        evt->set_mode = msm_timer_set_mode;
        evt->set_next_event = msm_timer_set_next_event;
-        evt->shift = msm_clockevent.shift;
-        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
-        evt->min_delta_ns = clockevent_delta2ns(4, evt);
        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-        clockevents_register_device(evt);
+        clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
        enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
        return 0;
 }
@@ -229,7 +224,7 @@ static const struct of_device_id msm_gpt_match[] __initconst = {
        { },
 };
-static void __init msm_dt_timer_init(void)
+void __init msm_dt_timer_init(void)
 {
        struct device_node *np;
        u32 freq;
@@ -296,10 +291,6 @@ static void __init msm_dt_timer_init(void)
        msm_timer_init(freq, 32, irq, !!percpu_offset);
 }
-struct sys_timer msm_dt_timer = {
-        .init = msm_dt_timer_init
-};
 #endif
 static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
@@ -317,7 +308,7 @@ static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
        return 0;
 }
-static void __init msm7x01_timer_init(void)
+void __init msm7x01_timer_init(void)
 {
        struct clocksource *cs = &msm_clocksource;
@@ -330,28 +321,16 @@ static void __init msm7x01_timer_init(void)
                        false);
 }
-struct sys_timer msm7x01_timer = {
+void __init msm7x30_timer_init(void)
-        .init = msm7x01_timer_init
-};
-static void __init msm7x30_timer_init(void)
 {
        if (msm_timer_map(0xc0100004, 0xc0100024))
                return;
        msm_timer_init(24576000 / 4, 32, 1, false);
 }
-struct sys_timer msm7x30_timer = {
+void __init qsd8x50_timer_init(void)
-        .init = msm7x30_timer_init
-};
-static void __init qsd8x50_timer_init(void)
 {
        if (msm_timer_map(0xAC100000, 0xAC100010))
                return;
        msm_timer_init(19200000 / 4, 32, 7, false);
 }
-struct sys_timer qsd8x50_timer = {
-        .init = qsd8x50_timer_init
-};
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index ee74ec97c141..1f2ef98b37c6 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -150,6 +150,6 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
        .map_io         = mv78xx0_map_io,
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
-        .timer          = &mv78xx0_timer,
+        .init_time      = mv78xx0_timer_init,
        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index d0cb4857b4b3..0efa14498ebc 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -336,16 +336,12 @@ void __init mv78xx0_init_early(void)
        orion_time_set_base(TIMER_VIRT_BASE);
 }
-static void __init_refok mv78xx0_timer_init(void)
+void __init_refok mv78xx0_timer_init(void)
 {
        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
                        IRQ_MV78XX0_TIMER_1, get_tclk());
 }
-struct sys_timer mv78xx0_timer = {
-        .init = mv78xx0_timer_init,
-};
 /*****************************************************************************
 * General
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 507c767d49e0..5e9485bad0ac 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -47,7 +47,7 @@ void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
 void mv78xx0_restart(char, const char *);
-extern struct sys_timer mv78xx0_timer;
+extern void mv78xx0_timer_init(void);
 #endif
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 4d6d48bf51ef..4e0f22b30bc8 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -98,6 +98,6 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
        .map_io         = mv78xx0_map_io,
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
-        .timer          = &mv78xx0_timer,
+        .init_time      = mv78xx0_timer_init,
        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
index 365264298e79..6a761c44a296 100644
--- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h
+++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
@@ -44,4 +44,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 9a882706e138..d2d06f3957f3 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -83,6 +83,6 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
        .map_io         = mv78xx0_map_io,
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
-        .timer          = &mv78xx0_timer,
+        .init_time      = mv78xx0_timer_init,
        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 99df4df680fd..da93bcbc74c1 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,7 +3,8 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
-obj-y += system-controller.o
+obj-y                            += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_ARCH_MVEBU)         += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 7434b5e36197..a5ea616d6d12 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -56,10 +56,6 @@ void __init armada_370_xp_init_early(void)
        init_dma_coherent_pool_size(SZ_1M);
 }
-struct sys_timer armada_370_xp_timer = {
-        .init           = armada_370_xp_timer_and_clk_init,
-};
 static void __init armada_370_xp_dt_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -78,7 +74,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
        .init_early     = armada_370_xp_init_early,
        .init_irq       = armada_370_xp_init_irq,
        .handle_irq     = armada_370_xp_handle_irq,
-        .timer          = &armada_370_xp_timer,
+        .init_time      = armada_370_xp_timer_and_clk_init,
        .restart        = mvebu_restart,
        .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 8e3fb082c3c6..274ff58271de 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -34,6 +34,7 @@
 #define ARMADA_370_XP_INT_CONTROL               (0x00)
 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
+#define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
@@ -41,28 +42,90 @@
 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
+#define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
 #define ACTIVE_DOORBELLS                        (8)
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 static void __iomem *per_cpu_int_base;
 static void __iomem *main_int_base;
 static struct irq_domain *armada_370_xp_mpic_domain;
+/*
+ * In SMP mode:
+ * For shared global interrupts, mask/unmask global enable bit
+ * For CPU interrtups, mask/unmask the calling CPU's bit
+ */
 static void armada_370_xp_irq_mask(struct irq_data *d)
 {
+#ifdef CONFIG_SMP
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+                writel(hwirq, main_int_base +
+                                ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+        else
+                writel(hwirq, per_cpu_int_base +
+                                ARMADA_370_XP_INT_SET_MASK_OFFS);
+#else
        writel(irqd_to_hwirq(d),
               per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+#endif
 }
 static void armada_370_xp_irq_unmask(struct irq_data *d)
 {
+#ifdef CONFIG_SMP
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+                writel(hwirq, main_int_base +
+                                ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+        else
+                writel(hwirq, per_cpu_int_base +
+                                ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+#else
        writel(irqd_to_hwirq(d),
               per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+#endif
 }
 #ifdef CONFIG_SMP
 static int armada_xp_set_affinity(struct irq_data *d,
                                  const struct cpumask *mask_val, bool force)
 {
+        unsigned long reg;
+        unsigned long new_mask = 0;
+        unsigned long online_mask = 0;
+        unsigned long count = 0;
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+        int cpu;
+        for_each_cpu(cpu, mask_val) {
+                new_mask |= 1 << cpu_logical_map(cpu);
+                count++;
+        }
+        /*
+         * Forbid mutlicore interrupt affinity
+         * This is required since the MPIC HW doesn't limit
+         * several CPUs from acknowledging the same interrupt.
+         */
+        if (count > 1)
+                return -EINVAL;
+        for_each_cpu(cpu, cpu_online_mask)
+                online_mask |= 1 << cpu_logical_map(cpu);
+        raw_spin_lock(&irq_controller_lock);
+        reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
+        reg = (reg & (~online_mask)) | new_mask;
+        writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
+        raw_spin_unlock(&irq_controller_lock);
        return 0;
 }
 #endif
@@ -82,10 +145,17 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 {
        armada_370_xp_irq_mask(irq_get_irq_data(virq));
        writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
-        irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
-                                 handle_level_irq);
        irq_set_status_flags(virq, IRQ_LEVEL);
+        if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
+                irq_set_percpu_devid(virq);
+                irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                        handle_percpu_devid_irq);
+        } else {
+                irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                        handle_level_irq);
+        }
        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
        return 0;
@@ -155,6 +225,15 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 #ifdef CONFIG_SMP
        armada_xp_mpic_smp_cpu_init();
+        /*
+         * Set the default affinity from all CPUs to the boot cpu.
+         * This is required since the MPIC doesn't limit several CPUs
+         * from acknowledging the same interrupt.
+         */
+        cpumask_clear(irq_default_affinity);
+        cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 #endif
        return 0;
@@ -173,7 +252,7 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
                if (irqnr > 1022)
                        break;
-                if (irqnr >= 8) {
+                if (irqnr > 0) {
                        irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
                                        irqnr);
                        handle_IRQ(irqnr, regs);
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index ef2811495446..533f5186e200 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -72,6 +72,5 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 }
 #define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
 #endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index c66129b5dd18..052186713347 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -119,6 +119,23 @@ static struct fb_videomode apf28dev_video_modes[] = {
        },
 };
+static struct fb_videomode cfa10049_video_modes[] = {
+        {
+                .name           = "Himax HX8357-B",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 480,
+                .pixclock       = 108506, /* picosecond (9.216 MHz) */
+                .left_margin    = 2,
+                .right_margin   = 2,
+                .upper_margin   = 2,
+                .lower_margin   = 2,
+                .hsync_len      = 15,
+                .vsync_len      = 15,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT
+        },
+};
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 /*
@@ -163,19 +180,11 @@ static void __init imx23_timer_init(void)
        mx23_clocks_init();
 }
-static struct sys_timer imx23_timer = {
-        .init = imx23_timer_init,
-};
 static void __init imx28_timer_init(void)
 {
        mx28_clocks_init();
 }
-static struct sys_timer imx28_timer = {
-        .init = imx28_timer_init,
-};
 enum mac_oui {
        OUI_FSL,
        OUI_DENX,
@@ -395,6 +404,17 @@ static void __init cfa10049_init(void)
        update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
+static void __init cfa10037_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+        mxsfb_pdata.mode_list = cfa10049_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
+}
 static void __init apf28_init(void)
 {
        enable_clk_enet_out();
@@ -415,6 +435,8 @@ static void __init mxs_machine_init(void)
                m28evk_init();
        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                apx4devkit_init();
+        else if (of_machine_is_compatible("crystalfontz,cfa10037"))
+                cfa10037_init();
        else if (of_machine_is_compatible("crystalfontz,cfa10049"))
                cfa10049_init();
        else if (of_machine_is_compatible("armadeus,imx28-apf28"))
@@ -446,7 +468,7 @@ DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
        .map_io         = mx23_map_io,
        .init_irq       = icoll_init_irq,
        .handle_irq     = icoll_handle_irq,
-        .timer          = &imx23_timer,
+        .init_time      = imx23_timer_init,
        .init_machine   = mxs_machine_init,
        .dt_compat      = imx23_dt_compat,
        .restart        = mxs_restart,
@@ -456,7 +478,7 @@ DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
        .map_io         = mx28_map_io,
        .init_irq       = icoll_init_irq,
        .handle_irq     = icoll_handle_irq,
-        .timer          = &imx28_timer,
+        .init_time      = imx28_timer_init,
        .init_machine   = mxs_machine_init,
        .dt_compat      = imx28_dt_compat,
        .restart        = mxs_restart,
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 856f4c796061..421020498a1b 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -72,8 +72,9 @@
 #define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
 #define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
 #define BP_TIMROT_TIMCTRLn_SELECT       0
-#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
+#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL         0x8
-#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
+#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL         0xb
+#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS        0xf
 static struct clock_event_device mxs_clockevent_device;
 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
@@ -195,7 +196,6 @@ static void mxs_set_mode(enum clock_event_mode mode,
 static struct clock_event_device mxs_clockevent_device = {
        .name           = "mxs_timrot",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .set_mode       = mxs_set_mode,
        .set_next_event = timrotv2_set_next_event,
        .rating         = 200,
@@ -203,25 +203,13 @@ static struct clock_event_device mxs_clockevent_device = {
 static int __init mxs_clockevent_init(struct clk *timer_clk)
 {
-        unsigned int c = clk_get_rate(timer_clk);
+        if (timrot_is_v1())
-        mxs_clockevent_device.mult =
-                div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
-        mxs_clockevent_device.cpumask = cpumask_of(0);
-        if (timrot_is_v1()) {
                mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
-                mxs_clockevent_device.max_delta_ns =
+        mxs_clockevent_device.cpumask = cpumask_of(0);
-                        clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
+        clockevents_config_and_register(&mxs_clockevent_device,
-                mxs_clockevent_device.min_delta_ns =
+                                        clk_get_rate(timer_clk),
-                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
+                                        timrot_is_v1() ? 0xf : 0x2,
-        } else {
+                                        timrot_is_v1() ? 0xfffe : 0xfffffffe);
-                mxs_clockevent_device.max_delta_ns =
-                        clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
-                mxs_clockevent_device.min_delta_ns =
-                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
-        }
-        clockevents_register_device(&mxs_clockevent_device);
        return 0;
 }
@@ -288,7 +276,7 @@ void __init mxs_timer_init(void)
        /* one for clock_event */
        __raw_writel((timrot_is_v1() ?
                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
-                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
                        BM_TIMROT_TIMCTRLn_UPDATE |
                        BM_TIMROT_TIMCTRLn_IRQ_EN,
                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
@@ -296,7 +284,7 @@ void __init mxs_timer_init(void)
        /* another for clocksource */
        __raw_writel((timrot_is_v1() ?
                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
-                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
                        BM_TIMROT_TIMCTRLn_RELOAD,
                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index aa627465d914..27c2cb7ab813 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -23,9 +23,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-vic.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 9b915119b8d6..768b26bbb42b 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -21,5 +21,4 @@ extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
 extern void netx_restart(char, const char *);
-struct sys_timer;
+extern void netx_timer_init(void);
-extern struct sys_timer netx_timer;
diff --git a/arch/arm/mach-netx/include/mach/uncompress.h b/arch/arm/mach-netx/include/mach/uncompress.h
index 84f91284f612..5cb1051b5831 100644
--- a/arch/arm/mach-netx/include/mach/uncompress.h
+++ b/arch/arm/mach-netx/include/mach/uncompress.h
@@ -73,4 +73,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 8b781ff7c9e9..9b558eb3070f 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -28,7 +28,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <linux/platform_data/eth-netx.h>
@@ -204,8 +203,7 @@ MACHINE_START(NXDB500, "Hilscher nxdb500")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = netx_timer_init,
-        .timer          = &netx_timer,
        .init_machine   = nxdb500_init,
        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index b26dbce334f2..a5e86cd365e7 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -28,7 +28,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <linux/platform_data/eth-netx.h>
@@ -97,8 +96,7 @@ MACHINE_START(NXDKN, "Hilscher nxdkn")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = netx_timer_init,
-        .timer          = &netx_timer,
        .init_machine   = nxdkn_init,
        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 257382efafa0..ad17885d0159 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -28,7 +28,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <linux/platform_data/eth-netx.h>
@@ -181,8 +180,7 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = netx_timer_init,
-        .timer          = &netx_timer,
        .init_machine   = nxeb500hmi_init,
        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index e24c141ba489..6df42e643031 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -76,7 +76,6 @@ static int netx_set_next_event(unsigned long evt,
 static struct clock_event_device netx_clockevent = {
        .name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
-        .shift = 32,
        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_next_event = netx_set_next_event,
        .set_mode = netx_set_mode,
@@ -107,7 +106,7 @@ static struct irqaction netx_timer_irq = {
 /*
 * Set up timer interrupt
 */
-static void __init netx_timer_init(void)
+void __init netx_timer_init(void)
 {
        /* disable timer initially */
        writel(0, NETX_GPIO_COUNTER_CTRL(0));
@@ -140,18 +139,9 @@ static void __init netx_timer_init(void)
        clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
                "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
-        netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
-                        netx_clockevent.shift);
-        netx_clockevent.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &netx_clockevent);
        /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
         * Adding some safety ... */
-        netx_clockevent.min_delta_ns =
-                clockevent_delta2ns(0xa00, &netx_clockevent);
        netx_clockevent.cpumask = cpumask_of(0);
-        clockevents_register_device(&netx_clockevent);
+        clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE,
+                                        0xa00, 0xfffffffe);
 }
-struct sys_timer netx_timer = {
-        .init           = netx_timer_init,
-};
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 706dc5727bbe..82226a5d60ef 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -4,19 +4,13 @@ menu "Nomadik boards"
 config MACH_NOMADIK_8815NHK
        bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
-        select CLKSRC_NOMADIK_MTU
        select NOMADIK_8815
+        select I2C
+        select I2C_ALGOBIT
 endmenu
 config NOMADIK_8815
        bool
-config I2C_BITBANG_8815NHK
-        tristate "Driver for bit-bang busses found on the 8815 NHK"
-        depends on I2C && MACH_NOMADIK_8815NHK
-        depends on PINCTRL_NOMADIK
-        default y
-        select I2C_ALGOBIT
 endif
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index a42c9a33d3bf..1071c3b04d1a 100644
--- a/arch/arm/mach-nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
@@ -9,9 +9,3 @@
 # Cpu revision
 obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
-# Specific board support
-obj-$(CONFIG_MACH_NOMADIK_8815NHK) += board-nhk8815.o
-# Nomadik extra devices
-obj-$(CONFIG_I2C_BITBANG_8815NHK) += i2c-8815nhk.o
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
deleted file mode 100644
index 9f19069248da..000000000000
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- *  linux/arch/arm/mach-nomadik/board-8815nhk.c
- *
- *  Copyright (C) STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- *
- *  NHK15 board specifc driver definition
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
-#include <linux/mtd/onenand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
-#include <asm/hardware/vic.h>
-#include <asm/sizes.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/time.h>
-#include <mach/irqs.h>
-#include "cpu-8815.h"
-/* Initial value for SRC control register: all timers use MXTAL/8 source */
-#define SRC_CR_INIT_MASK        0x00007fff
-#define SRC_CR_INIT_VAL         0x2aaa8000
-#define ALE_OFF 0x1000000
-#define CLE_OFF 0x800000
-/* These addresses span 16MB, so use three individual pages */
-static struct resource nhk8815_nand_resources[] = {
-        {
-                .name = "nand_data",
-                .start = 0x40000000,
-                .end = 0x40000000 + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .name = "nand_addr",
-                .start = 0x40000000 + ALE_OFF,
-                .end = 0x40000000 +ALE_OFF + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .name = "nand_cmd",
-                .start = 0x40000000 + CLE_OFF,
-                .end = 0x40000000 + CLE_OFF + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .name  = "fsmc_regs",
-                .start = NOMADIK_FSMC_BASE,
-                .end   = NOMADIK_FSMC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-/*
- * These partitions are the same as those used in the 2.6.20 release
- * shipped by the vendor; the first two partitions are mandated
- * by the boot ROM, and the bootloader area is somehow oversized...
- */
-static struct mtd_partition nhk8815_partitions[] = {
-        {
-                .name   = "X-Loader(NAND)",
-                .offset = 0,
-                .size   = SZ_256K,
-        }, {
-                .name   = "MemInit(NAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_256K,
-        }, {
-                .name   = "BootLoader(NAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_2M,
-        }, {
-                .name   = "Kernel zImage(NAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 3 * SZ_1M,
-        }, {
-                .name   = "Root Filesystem(NAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 22 * SZ_1M,
-        }, {
-                .name   = "User Filesystem(NAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-static struct fsmc_nand_timings nhk8815_nand_timings = {
-        .thiz   = 0,
-        .thold  = 0x10,
-        .twait  = 0x0A,
-        .tset   = 0,
-};
-static struct fsmc_nand_platform_data nhk8815_nand_platform_data = {
-        .nand_timings = &nhk8815_nand_timings,
-        .partitions = nhk8815_partitions,
-        .nr_partitions = ARRAY_SIZE(nhk8815_partitions),
-        .width = FSMC_NAND_BW8,
-};
-static struct platform_device nhk8815_nand_device = {
-        .name = "fsmc-nand",
-        .id = -1,
-        .resource = nhk8815_nand_resources,
-        .num_resources = ARRAY_SIZE(nhk8815_nand_resources),
-        .dev = {
-                .platform_data = &nhk8815_nand_platform_data,
-        },
-};
-/* These are the partitions for the OneNand device, different from above */
-static struct mtd_partition nhk8815_onenand_partitions[] = {
-        {
-                .name   = "X-Loader(OneNAND)",
-                .offset = 0,
-                .size   = SZ_256K,
-        }, {
-                .name   = "MemInit(OneNAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_256K,
-        }, {
-                .name   = "BootLoader(OneNAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_2M-SZ_256K,
-        }, {
-                .name   = "SysImage(OneNAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 4 * SZ_1M,
-        }, {
-                .name   = "Root Filesystem(OneNAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 22 * SZ_1M,
-        }, {
-                .name   = "User Filesystem(OneNAND)",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-static struct onenand_platform_data nhk8815_onenand_data = {
-        .parts          = nhk8815_onenand_partitions,
-        .nr_parts       = ARRAY_SIZE(nhk8815_onenand_partitions),
-};
-static struct resource nhk8815_onenand_resource[] = {
-        {
-                .start          = 0x30000000,
-                .end            = 0x30000000 + SZ_128K - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-static struct platform_device nhk8815_onenand_device = {
-        .name           = "onenand-flash",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &nhk8815_onenand_data,
-        },
-        .resource       = nhk8815_onenand_resource,
-        .num_resources  = ARRAY_SIZE(nhk8815_onenand_resource),
-};
-/* bus control reg. and bus timing reg. for CS0..CS3 */
-#define FSMC_BCR(x)     (NOMADIK_FSMC_VA + (x << 3))
-#define FSMC_BTR(x)     (NOMADIK_FSMC_VA + (x << 3) + 0x04)
-static void __init nhk8815_onenand_init(void)
-{
-#ifdef CONFIG_MTD_ONENAND
-       /* Set up SMCS0 for OneNand */
-        writel(0x000030db, FSMC_BCR(0));
-        writel(0x02100551, FSMC_BTR(0));
-#endif
-}
-static struct mmci_platform_data mmcsd_plat_data = {
-        .ocr_mask = MMC_VDD_29_30,
-        .f_max = 48000000,
-        .gpio_wp = -1,
-        .gpio_cd = 111,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
-};
-static int __init nhk8815_mmcsd_init(void)
-{
-        int ret;
-        ret = gpio_request(112, "card detect bias");
-        if (ret)
-                return ret;
-        gpio_direction_output(112, 0);
-        amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180);
-        return 0;
-}
-module_init(nhk8815_mmcsd_init);
-static struct resource nhk8815_eth_resources[] = {
-        {
-                .name = "smc91x-regs",
-                .start = 0x34000000 + 0x300,
-                .end = 0x34000000 + SZ_64K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = NOMADIK_GPIO_TO_IRQ(115),
-                .end = NOMADIK_GPIO_TO_IRQ(115),
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
-        }
-};
-static struct platform_device nhk8815_eth_device = {
-        .name = "smc91x",
-        .resource = nhk8815_eth_resources,
-        .num_resources = ARRAY_SIZE(nhk8815_eth_resources),
-};
-static int __init nhk8815_eth_init(void)
-{
-        int gpio_nr = 115; /* hardwired in the board */
-        int err;
-        err = gpio_request(gpio_nr, "eth_irq");
-        if (!err) err = nmk_gpio_set_mode(gpio_nr, NMK_GPIO_ALT_GPIO);
-        if (!err) err = gpio_direction_input(gpio_nr);
-        if (err)
-                pr_err("Error %i in %s\n", err, __func__);
-        return err;
-}
-device_initcall(nhk8815_eth_init);
-static struct platform_device *nhk8815_platform_devices[] __initdata = {
-        &nhk8815_nand_device,
-        &nhk8815_onenand_device,
-        &nhk8815_eth_device,
-        /* will add more devices */
-};
-static void __init nomadik_timer_init(void)
-{
-        u32 src_cr;
-        /* Configure timer sources in "system reset controller" ctrl reg */
-        src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
-        src_cr &= SRC_CR_INIT_MASK;
-        src_cr |= SRC_CR_INIT_VAL;
-        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
-        nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0);
-}
-static struct sys_timer nomadik_timer = {
-        .init   = nomadik_timer_init,
-};
-static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = {
-        {
-                I2C_BOARD_INFO("stw4811", 0x2d),
-        },
-};
-static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = {
-        {
-                I2C_BOARD_INFO("camera", 0x10),
-        },
-        {
-                I2C_BOARD_INFO("stw5095", 0x1a),
-        },
-        {
-                I2C_BOARD_INFO("lis3lv02dl", 0x1d),
-        },
-};
-static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
-        {
-                I2C_BOARD_INFO("stw4811-usb", 0x2d),
-        },
-};
-static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-static struct pinctrl_map __initdata nhk8815_pinmap[] = {
-        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
-        /* Hog in MMC/SD card mux */
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
-        /* MCCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
-        /* MCCMD */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
-        /* MCCMDDIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
-        /* MCDAT3-0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
-        /* MCDAT0DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
-        /* MCDAT31DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
-        /* MCMSFBCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
-        /* CD input GPIO */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
-        /* CD bias drive */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
-};
-static void __init nhk8815_platform_init(void)
-{
-        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
-        cpu8815_platform_init();
-        nhk8815_onenand_init();
-        platform_add_devices(nhk8815_platform_devices,
-                             ARRAY_SIZE(nhk8815_platform_devices));
-        amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0);
-        amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0);
-        i2c_register_board_info(0, nhk8815_i2c0_devices,
-                                ARRAY_SIZE(nhk8815_i2c0_devices));
-        i2c_register_board_info(1, nhk8815_i2c1_devices,
-                                ARRAY_SIZE(nhk8815_i2c1_devices));
-        i2c_register_board_info(2, nhk8815_i2c2_devices,
-                                ARRAY_SIZE(nhk8815_i2c2_devices));
-}
-MACHINE_START(NOMADIK, "NHK8815")
-        /* Maintainer: ST MicroElectronics */
-        .atag_offset    = 0x100,
-        .map_io         = cpu8815_map_io,
-        .init_irq       = cpu8815_init_irq,
-        .handle_irq     = vic_handle_irq,
-        .timer          = &nomadik_timer,
-        .init_machine   = nhk8815_platform_init,
-        .restart        = cpu8815_restart,
-MACHINE_END
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 1273931303fb..21c1aa512640 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -25,138 +25,308 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
+#include <linux/irqchip.h>
 #include <linux/platform_data/clk-nomadik.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/mtd/fsmc.h>
+#include <linux/gpio.h>
+#include <linux/amba/mmci.h>
-#include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/hardware/vic.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
-#include "cpu-8815.h"
+/*
+ * These are the only hard-coded address offsets we still have to use.
+ */
+#define NOMADIK_FSMC_BASE       0x10100000      /* FSMC registers */
+#define NOMADIK_SDRAMC_BASE     0x10110000      /* SDRAM Controller */
+#define NOMADIK_CLCDC_BASE      0x10120000      /* CLCD Controller */
+#define NOMADIK_MDIF_BASE       0x10120000      /* MDIF */
+#define NOMADIK_DMA0_BASE       0x10130000      /* DMA0 Controller */
+#define NOMADIK_IC_BASE         0x10140000      /* Vectored Irq Controller */
+#define NOMADIK_DMA1_BASE       0x10150000      /* DMA1 Controller */
+#define NOMADIK_USB_BASE        0x10170000      /* USB-OTG conf reg base */
+#define NOMADIK_CRYP_BASE       0x10180000      /* Crypto processor */
+#define NOMADIK_SHA1_BASE       0x10190000      /* SHA-1 Processor */
+#define NOMADIK_XTI_BASE        0x101A0000      /* XTI */
+#define NOMADIK_RNG_BASE        0x101B0000      /* Random number generator */
+#define NOMADIK_SRC_BASE        0x101E0000      /* SRC base */
+#define NOMADIK_WDOG_BASE       0x101E1000      /* Watchdog */
+#define NOMADIK_MTU0_BASE       0x101E2000      /* Multiple Timer 0 */
+#define NOMADIK_MTU1_BASE       0x101E3000      /* Multiple Timer 1 */
+#define NOMADIK_GPIO0_BASE      0x101E4000      /* GPIO0 */
+#define NOMADIK_GPIO1_BASE      0x101E5000      /* GPIO1 */
+#define NOMADIK_GPIO2_BASE      0x101E6000      /* GPIO2 */
+#define NOMADIK_GPIO3_BASE      0x101E7000      /* GPIO3 */
+#define NOMADIK_RTC_BASE        0x101E8000      /* Real Time Clock base */
+#define NOMADIK_PMU_BASE        0x101E9000      /* Power Management Unit */
+#define NOMADIK_OWM_BASE        0x101EA000      /* One wire master */
+#define NOMADIK_SCR_BASE        0x101EF000      /* Secure Control registers */
+#define NOMADIK_MSP2_BASE       0x101F0000      /* MSP 2 interface */
+#define NOMADIK_MSP1_BASE       0x101F1000      /* MSP 1 interface */
+#define NOMADIK_UART2_BASE      0x101F2000      /* UART 2 interface */
+#define NOMADIK_SSIRx_BASE      0x101F3000      /* SSI 8-ch rx interface */
+#define NOMADIK_SSITx_BASE      0x101F4000      /* SSI 8-ch tx interface */
+#define NOMADIK_MSHC_BASE       0x101F5000      /* Memory Stick(Pro) Host */
+#define NOMADIK_SDI_BASE        0x101F6000      /* SD-card/MM-Card */
+#define NOMADIK_I2C1_BASE       0x101F7000      /* I2C1 interface */
+#define NOMADIK_I2C0_BASE       0x101F8000      /* I2C0 interface */
+#define NOMADIK_MSP0_BASE       0x101F9000      /* MSP 0 interface */
+#define NOMADIK_FIRDA_BASE      0x101FA000      /* FIrDA interface */
+#define NOMADIK_UART1_BASE      0x101FB000      /* UART 1 interface */
+#define NOMADIK_SSP_BASE        0x101FC000      /* SSP interface */
+#define NOMADIK_UART0_BASE      0x101FD000      /* UART 0 interface */
+#define NOMADIK_SGA_BASE        0x101FE000      /* SGA interface */
+#define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
+#define NOMADIK_UART1_VBASE     0xF01FB000
-/* The 8815 has 4 GPIO blocks, let's register them immediately */
+static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static resource_size_t __initdata cpu8815_gpio_base[] = {
+static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-        NOMADIK_GPIO0_BASE,
+static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-        NOMADIK_GPIO1_BASE,
+static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-        NOMADIK_GPIO2_BASE,
-        NOMADIK_GPIO3_BASE,
+static struct pinctrl_map __initdata nhk8815_pinmap[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+        /* Hog in MMC/SD card mux */
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
+        /* MCCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
+        /* MCCMD */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
+        /* MCCMDDIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
+        /* MCDAT3-0 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
+        /* MCDAT0DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
+        /* MCDAT31DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
+        /* MCMSFBCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
+        /* CD input GPIO */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
+        /* CD bias drive */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
+        /* I2C0 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
+        /* I2C1 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
+        /* I2C2 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
 };
-static struct platform_device *
+/* This is needed for LL-debug/earlyprintk/debug-macro.S */
-cpu8815_add_gpio(int id, resource_size_t addr, int irq,
+static struct map_desc cpu8815_io_desc[] __initdata = {
-                 struct nmk_gpio_platform_data *pdata)
+        {
+                .virtual =      NOMADIK_UART1_VBASE,
+                .pfn =          __phys_to_pfn(NOMADIK_UART1_BASE),
+                .length =       SZ_4K,
+                .type =         MT_DEVICE,
+        },
+};
+static void __init cpu8815_map_io(void)
 {
-        struct resource resources[] = {
+        iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
-                {
-                        .start  = addr,
-                        .end    = addr + 127,
-                        .flags  = IORESOURCE_MEM,
-                },
-                {
-                        .start  = irq,
-                        .end    = irq,
-                        .flags  = IORESOURCE_IRQ,
-                }
-        };
-        return platform_device_register_resndata(NULL, "gpio", id,
-                                resources, ARRAY_SIZE(resources),
-                                pdata, sizeof(*pdata));
 }
-void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
+static void cpu8815_restart(char mode, const char *cmd)
-                       struct nmk_gpio_platform_data *pdata)
 {
-        int first = 0;
+        void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
-        int i;
-        for (i = 0; i < num; i++, first += 32, irq++) {
+        /* FIXME: use egpio when implemented */
-                pdata->first_gpio = first;
-                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
-                pdata->num_gpio = 32;
-                cpu8815_add_gpio(i, base[i], irq, pdata);
+        /* Write anything to Reset status register */
-        }
+        writel(1, srcbase + 0x18);
 }
-static inline void
+/* Initial value for SRC control register: all timers use MXTAL/8 source */
-cpu8815_add_pinctrl(struct device *parent, const char *name)
+#define SRC_CR_INIT_MASK        0x00007fff
+#define SRC_CR_INIT_VAL         0x2aaa8000
+static void __init cpu8815_timer_init_of(void)
 {
-        struct platform_device_info pdevinfo = {
+        struct device_node *mtu;
-                .parent = parent,
+        void __iomem *base;
-                .name = name,
+        int irq;
-                .id = -1,
+        u32 src_cr;
-        };
+        /* We need this to be up now */
+        nomadik_clk_init();
+        mtu = of_find_node_by_path("/mtu0");
+        if (!mtu)
+                return;
+        base = of_iomap(mtu, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(mtu, 0);
-        platform_device_register_full(&pdevinfo);
+        pr_info("Remapped MTU @ %p, irq: %d\n", base, irq);
+        /* Configure timer sources in "system reset controller" ctrl reg */
+        src_cr = readl(base);
+        src_cr &= SRC_CR_INIT_MASK;
+        src_cr |= SRC_CR_INIT_VAL;
+        writel(src_cr, base);
+        nmdk_timer_init(base, irq);
 }
-static int __init cpu8815_init(void)
+static struct fsmc_nand_timings cpu8815_nand_timings = {
+        .thiz   = 0,
+        .thold  = 0x10,
+        .twait  = 0x0A,
+        .tset   = 0,
+};
+static struct fsmc_nand_platform_data cpu8815_nand_data = {
+        .nand_timings = &cpu8815_nand_timings,
+};
+/*
+ * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects
+ * to simply request an IRQ passed as a resource. So the GPIO pin needs
+ * to be requested by this hog and set as input.
+ */
+static int __init cpu8815_eth_init(void)
 {
-        struct nmk_gpio_platform_data pdata = {
+        struct device_node *eth;
-                /* No custom data yet */
+        int gpio, irq, err;
-        };
+        eth = of_find_node_by_path("/usb-s8815/ethernet-gpio");
-        cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
+        if (!eth) {
-                          IRQ_GPIO0, &pdata);
+                pr_info("could not find any ethernet GPIO\n");
-        cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
+                return 0;
-        amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
+        }
-        amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
+        gpio = of_get_gpio(eth, 0);
+        err = gpio_request(gpio, "eth_irq");
+        if (err) {
+                pr_info("failed to request ethernet GPIO\n");
+                return -ENODEV;
+        }
+        err = gpio_direction_input(gpio);
+        if (err) {
+                pr_info("failed to set ethernet GPIO as input\n");
+                return -ENODEV;
+        }
+        irq = gpio_to_irq(gpio);
+        pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq);
        return 0;
 }
-arch_initcall(cpu8815_init);
+device_initcall(cpu8815_eth_init);
-/* All SoC devices live in the same area (see hardware.h) */
+/*
-static struct map_desc nomadik_io_desc[] __initdata = {
+ * TODO:
-        {
+ * cannot be set from device tree, convert to a proper DT
-                .virtual =      NOMADIK_IO_VIRTUAL,
+ * binding.
-                .pfn =          __phys_to_pfn(NOMADIK_IO_PHYSICAL),
+ */
-                .length =       NOMADIK_IO_SIZE,
+static struct mmci_platform_data mmcsd_plat_data = {
-                .type =         MT_DEVICE,
+        .ocr_mask = MMC_VDD_29_30,
-        }
-        /* static ram and secured ram may be added later */
 };
-void __init cpu8815_map_io(void)
+/*
+ * This GPIO pin turns on a line that is used to detect card insertion
+ * on this board.
+ */
+static int __init cpu8815_mmcsd_init(void)
 {
-        iotable_init(nomadik_io_desc, ARRAY_SIZE(nomadik_io_desc));
+        struct device_node *cdbias;
-}
+        int gpio, err;
-void __init cpu8815_init_irq(void)
+        cdbias = of_find_node_by_path("/usb-s8815/mmcsd-gpio");
-{
+        if (!cdbias) {
-        /* This modified VIC cell has two register blocks, at 0 and 0x20 */
+                pr_info("could not find MMC/SD card detect bias node\n");
-        vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START +  0, ~0, 0);
+                return 0;
-        vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0);
+        }
+        gpio = of_get_gpio(cdbias, 0);
-        /*
+        if (gpio < 0) {
-         * Init clocks here so that they are available for system timer
+                pr_info("could not obtain MMC/SD card detect bias GPIO\n");
-         * initialization.
+                return 0;
-         */
+        }
-        nomadik_clk_init();
+        err = gpio_request(gpio, "card detect bias");
+        if (err) {
+                pr_info("failed to request card detect bias GPIO %d\n", gpio);
+                return -ENODEV;
+        }
+        err = gpio_direction_output(gpio, 0);
+        if (err){
+                pr_info("failed to set GPIO %d as output, low\n", gpio);
+                return err;
+        }
+        pr_info("enabled USB-S8815 CD bias GPIO %d, low\n", gpio);
+        return 0;
 }
+device_initcall(cpu8815_mmcsd_init);
-/*
- * This function is called from the board init ("init_machine").
+/* These are mostly to get the right device names for the clock lookups */
- */
+static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
- void __init cpu8815_platform_init(void)
+        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE,
+                "gpio.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE,
+                "gpio.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE,
+                "gpio.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
+                "gpio.3", NULL),
+        OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
+                "pinctrl-stn8815", NULL),
+        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
+                "uart0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE,
+                "uart1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE,
+                "rng", NULL),
+        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE,
+                "rtc-pl031", NULL),
+        OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
+                "fsmc-nand", &cpu8815_nand_data),
+        OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
+                "mmci", &mmcsd_plat_data),
+        { /* sentinel */ },
+};
+static void __init cpu8815_init_of(void)
 {
 #ifdef CONFIG_CACHE_L2X0
        /* At full speed latency must be >=2, so 0x249 in low bits */
-        l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
+        l2x0_of_init(0x00730249, 0xfe000fff);
 #endif
-         return;
+        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        cpu8815_auxdata_lookup, NULL);
 }
-void cpu8815_restart(char mode, const char *cmd)
+static const char * cpu8815_board_compat[] = {
-{
+        "calaosystems,usb-s8815",
-        void __iomem *src_rstsr = io_p2v(NOMADIK_SRC_BASE + 0x18);
+        NULL,
+};
-        /* FIXME: use egpio when implemented */
-        /* Write anything to Reset status register */
+DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
-        writel(1, src_rstsr);
+        .map_io         = cpu8815_map_io,
-}
+        .init_irq       = irqchip_init,
+        .init_time      = cpu8815_timer_init_of,
+        .init_machine   = cpu8815_init_of,
+        .restart        = cpu8815_restart,
+        .dt_compat      = cpu8815_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-nomadik/cpu-8815.h b/arch/arm/mach-nomadik/cpu-8815.h
deleted file mode 100644
index 71c21e8a11dc..000000000000
--- a/arch/arm/mach-nomadik/cpu-8815.h
+++ /dev/null
@@ -1,4 +0,0 @@
-extern void cpu8815_map_io(void);
-extern void cpu8815_platform_init(void);
-extern void cpu8815_init_irq(void);
-extern void cpu8815_restart(char, const char *);
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
deleted file mode 100644
index 0c2f6628299a..000000000000
--- a/arch/arm/mach-nomadik/i2c-8815nhk.c
+++ /dev/null
@@ -1,88 +0,0 @@
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
-#include <linux/i2c-gpio.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-/*
- * There are two busses in the 8815NHK.
- * They could, in theory, be driven by the hardware component, but we
- * use bit-bang through GPIO by now, to keep things simple
- */
-/* I2C0 connected to the STw4811 power management chip */
-static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
-        /* keep defaults for timeouts; pins are push-pull bidirectional */
-        .scl_pin = 62,
-        .sda_pin = 63,
-};
-/* I2C1 connected to various sensors */
-static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
-        /* keep defaults for timeouts; pins are push-pull bidirectional */
-        .scl_pin = 53,
-        .sda_pin = 54,
-};
-/* I2C2 connected to the USB portions of the STw4811 only */
-static struct i2c_gpio_platform_data nhk8815_i2c_data2 = {
-        /* keep defaults for timeouts; pins are push-pull bidirectional */
-        .scl_pin = 73,
-        .sda_pin = 74,
-};
-static struct platform_device nhk8815_i2c_dev0 = {
-        .name   = "i2c-gpio",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &nhk8815_i2c_data0,
-        },
-};
-static struct platform_device nhk8815_i2c_dev1 = {
-        .name   = "i2c-gpio",
-        .id     = 1,
-        .dev    = {
-                .platform_data = &nhk8815_i2c_data1,
-        },
-};
-static struct platform_device nhk8815_i2c_dev2 = {
-        .name   = "i2c-gpio",
-        .id     = 2,
-        .dev    = {
-                .platform_data = &nhk8815_i2c_data2,
-        },
-};
-static pin_cfg_t cpu8815_pins_i2c[] = {
-        PIN_CFG_INPUT(62, GPIO, PULLUP),
-        PIN_CFG_INPUT(63, GPIO, PULLUP),
-        PIN_CFG_INPUT(53, GPIO, PULLUP),
-        PIN_CFG_INPUT(54, GPIO, PULLUP),
-        PIN_CFG_INPUT(73, GPIO, PULLUP),
-        PIN_CFG_INPUT(74, GPIO, PULLUP),
-};
-static int __init nhk8815_i2c_init(void)
-{
-        nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c));
-        platform_device_register(&nhk8815_i2c_dev0);
-        platform_device_register(&nhk8815_i2c_dev1);
-        platform_device_register(&nhk8815_i2c_dev2);
-        return 0;
-}
-static void __exit nhk8815_i2c_exit(void)
-{
-        platform_device_unregister(&nhk8815_i2c_dev0);
-        platform_device_unregister(&nhk8815_i2c_dev1);
-        platform_device_unregister(&nhk8815_i2c_dev2);
-        return;
-}
-module_init(nhk8815_i2c_init);
-module_exit(nhk8815_i2c_exit);
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
deleted file mode 100644
index 02035e459f50..000000000000
--- a/arch/arm/mach-nomadik/include/mach/hardware.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file contains the hardware definitions of the Nomadik.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * YOU should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
-#define NOMADIK_IO_VIRTUAL      0xF0000000      /* VA of IO  */
-#define NOMADIK_IO_PHYSICAL     0x10000000      /* PA of IO */
-#define NOMADIK_IO_SIZE         0x00300000      /* 3MB for all regs */
-/* used in C code, so cast to proper type */
-#define io_p2v(x) ((void __iomem *)(x) \
-                        - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
-#define io_v2p(x) ((unsigned long)(x) \
-                        - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
-/* used in asm code, so no casts */
-#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
-/*
- *   Base address defination for Nomadik Onchip Logic Block
- */
-#define NOMADIK_FSMC_BASE       0x10100000      /* FSMC registers */
-#define NOMADIK_SDRAMC_BASE     0x10110000      /* SDRAM Controller */
-#define NOMADIK_CLCDC_BASE      0x10120000      /* CLCD Controller */
-#define NOMADIK_MDIF_BASE       0x10120000      /* MDIF */
-#define NOMADIK_DMA0_BASE       0x10130000      /* DMA0 Controller */
-#define NOMADIK_IC_BASE         0x10140000      /* Vectored Irq Controller */
-#define NOMADIK_DMA1_BASE       0x10150000      /* DMA1 Controller */
-#define NOMADIK_USB_BASE        0x10170000      /* USB-OTG conf reg base */
-#define NOMADIK_CRYP_BASE       0x10180000      /* Crypto processor */
-#define NOMADIK_SHA1_BASE       0x10190000      /* SHA-1 Processor */
-#define NOMADIK_XTI_BASE        0x101A0000      /* XTI */
-#define NOMADIK_RNG_BASE        0x101B0000      /* Random number generator */
-#define NOMADIK_SRC_BASE        0x101E0000      /* SRC base */
-#define NOMADIK_WDOG_BASE       0x101E1000      /* Watchdog */
-#define NOMADIK_MTU0_BASE       0x101E2000      /* Multiple Timer 0 */
-#define NOMADIK_MTU1_BASE       0x101E3000      /* Multiple Timer 1 */
-#define NOMADIK_GPIO0_BASE      0x101E4000      /* GPIO0 */
-#define NOMADIK_GPIO1_BASE      0x101E5000      /* GPIO1 */
-#define NOMADIK_GPIO2_BASE      0x101E6000      /* GPIO2 */
-#define NOMADIK_GPIO3_BASE      0x101E7000      /* GPIO3 */
-#define NOMADIK_RTC_BASE        0x101E8000      /* Real Time Clock base */
-#define NOMADIK_PMU_BASE        0x101E9000      /* Power Management Unit */
-#define NOMADIK_OWM_BASE        0x101EA000      /* One wire master */
-#define NOMADIK_SCR_BASE        0x101EF000      /* Secure Control registers */
-#define NOMADIK_MSP2_BASE       0x101F0000      /* MSP 2 interface */
-#define NOMADIK_MSP1_BASE       0x101F1000      /* MSP 1 interface */
-#define NOMADIK_UART2_BASE      0x101F2000      /* UART 2 interface */
-#define NOMADIK_SSIRx_BASE      0x101F3000      /* SSI 8-ch rx interface */
-#define NOMADIK_SSITx_BASE      0x101F4000      /* SSI 8-ch tx interface */
-#define NOMADIK_MSHC_BASE       0x101F5000      /* Memory Stick(Pro) Host */
-#define NOMADIK_SDI_BASE        0x101F6000      /* SD-card/MM-Card */
-#define NOMADIK_I2C1_BASE       0x101F7000      /* I2C1 interface */
-#define NOMADIK_I2C0_BASE       0x101F8000      /* I2C0 interface */
-#define NOMADIK_MSP0_BASE       0x101F9000      /* MSP 0 interface  */
-#define NOMADIK_FIRDA_BASE      0x101FA000      /* FIrDA interface  */
-#define NOMADIK_UART1_BASE      0x101FB000      /* UART 1 interface */
-#define NOMADIK_SSP_BASE        0x101FC000      /* SSP interface  */
-#define NOMADIK_UART0_BASE      0x101FD000      /* UART 0 interface */
-#define NOMADIK_SGA_BASE        0x101FE000      /* SGA interface */
-#define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
-/* Other ranges, not for p2v/v2p */
-#define NOMADIK_BACKUP_RAM      0x80010000
-#define NOMADIK_EBROM           0x80000000      /* Embedded boot ROM */
-#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000     /* HAMACV Data Memory Start */
-#define NOMADIK_HAMACV_DMEM_END 0xA01FFFFF      /* HAMACV Data Memory End */
-#define NOMADIK_HAMACA_DMEM     0xA0200000      /* HAMACA Data Memory Space */
-#define NOMADIK_FSMC_VA         IO_ADDRESS(NOMADIK_FSMC_BASE)
-#define NOMADIK_MTU0_VA         IO_ADDRESS(NOMADIK_MTU0_BASE)
-#define NOMADIK_MTU1_VA         IO_ADDRESS(NOMADIK_MTU1_BASE)
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
index 215f8cdb4004..90ac965a92fe 100644
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
-#include <mach/hardware.h>
 #define IRQ_VIC_START           32      /* first VIC interrupt is 1 */
 /*
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
index 7d4687e9cbdf..106fccca2021 100644
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -21,7 +21,6 @@
 #include <asm/setup.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
 /* we need the constants in amba/serial.h, but it refers to amba_device */
 struct amba_device;
@@ -58,6 +57,4 @@ static inline void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog() /* nothing to do here */
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 2e98a3ac7c5e..2aab761ee68d 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -628,6 +628,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
        .init_irq       = omap1_init_irq,
        .init_machine   = ams_delta_init,
        .init_late      = ams_delta_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 560a7dcf0a56..702d58039cc1 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -364,6 +364,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_fsample_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 608e7d2a2778..e1d9171774bc 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -84,6 +84,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_generic_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 2274bd677efc..0dac3d239e32 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -461,6 +461,6 @@ MACHINE_START(OMAP_H2, "TI-H2")
        .init_irq       = omap1_init_irq,
        .init_machine   = h2_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 1051935f0aac..816ecd13f81e 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -454,6 +454,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
        .init_irq       = omap1_init_irq,
        .init_machine   = h3_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 356f816c84a6..35a2379b986f 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -603,6 +603,6 @@ MACHINE_START(HERALD, "HTC Herald")
        .init_irq       = omap1_init_irq,
        .init_machine   = htcherald_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index f8033fab0f82..bd5f02e9c354 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -458,6 +458,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
        .init_irq       = omap1_init_irq,
        .init_machine   = innovator_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 24d2f2df11a0..62a15e289c79 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -7,6 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -23,6 +24,8 @@
 #include <linux/platform_data/keypad-omap.h>
 #include <linux/platform_data/lcd-mipid.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/i2c-cbus-gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -212,6 +215,45 @@ static inline void nokia770_mmc_init(void)
 }
 #endif
+#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE)
+static struct i2c_cbus_platform_data nokia770_cbus_data = {
+        .clk_gpio = OMAP_MPUIO(9),
+        .dat_gpio = OMAP_MPUIO(10),
+        .sel_gpio = OMAP_MPUIO(11),
+};
+static struct platform_device nokia770_cbus_device = {
+        .name   = "i2c-cbus-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data = &nokia770_cbus_data,
+        },
+};
+static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
+        {
+                I2C_BOARD_INFO("retu-mfd", 0x01),
+        },
+};
+static void __init nokia770_cbus_init(void)
+{
+        const int retu_irq_gpio = 62;
+        if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
+                return;
+        irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
+        nokia770_i2c_board_info_2[0].irq = gpio_to_irq(retu_irq_gpio);
+        i2c_register_board_info(2, nokia770_i2c_board_info_2,
+                                ARRAY_SIZE(nokia770_i2c_board_info_2));
+        platform_device_register(&nokia770_cbus_device);
+}
+#else /* CONFIG_I2C_CBUS_GPIO */
+static void __init nokia770_cbus_init(void)
+{
+}
+#endif /* CONFIG_I2C_CBUS_GPIO */
 static void __init omap_nokia770_init(void)
 {
        /* On Nokia 770, the SleepX signal is masked with an
@@ -233,6 +275,7 @@ static void __init omap_nokia770_init(void)
        mipid_dev_init();
        omap1_usb_init(&nokia770_usb_config);
        nokia770_mmc_init();
+        nokia770_cbus_init();
 }
 MACHINE_START(NOKIA770, "Nokia 770")
@@ -242,6 +285,6 @@ MACHINE_START(NOKIA770, "Nokia 770")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_nokia770_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 872ea47cd28a..a7ce69286688 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -609,6 +609,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
        .init_irq       = omap1_init_irq,
        .init_machine   = osk_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index c33dceb46607..845a1a7aef95 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -268,6 +268,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmte_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 2948b0ee4be8..65a4a3e357f2 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -314,6 +314,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmtt_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 7a05895c0be3..01c970071fd8 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -330,6 +330,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmz71_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 27f8d12ec222..8b2f7127f716 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -326,6 +326,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_perseus2_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 20ed52ae1714..9732a98f3e06 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -407,6 +407,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_sx1_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index abf705f49b19..6c116e1a4b01 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -289,6 +289,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
        .init_irq       = omap1_init_irq,
        .init_machine   = voiceblue_init,
        .init_late      = omap1_init_late,
-        .timer          = &omap1_timer,
+        .init_time      = omap1_timer_init,
        .restart        = voiceblue_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index b53e0854422f..fb18831e88aa 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -75,7 +75,7 @@ extern void __init omap_check_revision(void);
 extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
                               unsigned int ctrl);
-extern struct sys_timer omap1_timer;
+extern void omap1_timer_init(void);
 #ifdef CONFIG_OMAP_32K_TIMER
 extern int omap_32k_timer_init(void);
 #else
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index e190611e4b46..1a4e887f028d 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -24,7 +24,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
@@ -270,11 +270,17 @@ static u32 configure_dma_errata(void)
        return errata;
 }
+static const struct platform_device_info omap_dma_dev_info = {
+        .name = "omap-dma-engine",
+        .id = -1,
+        .dma_mask = DMA_BIT_MASK(32),
+};
 static int __init omap1_system_dma_init(void)
 {
        struct omap_system_dma_plat_info        *p;
        struct omap_dma_dev_attr                *d;
-        struct platform_device                  *pdev;
+        struct platform_device                  *pdev, *dma_pdev;
        int ret;
        pdev = platform_device_alloc("omap_dma_system", 0);
@@ -380,8 +386,16 @@ static int __init omap1_system_dma_init(void)
        dma_common_ch_start     = CPC;
        dma_common_ch_end       = COLOR;
+        dma_pdev = platform_device_register_full(&omap_dma_dev_info);
+        if (IS_ERR(dma_pdev)) {
+                ret = PTR_ERR(dma_pdev);
+                goto exit_release_pdev;
+        }
        return ret;
+exit_release_pdev:
+        platform_device_del(pdev);
 exit_release_chan:
        kfree(d->chan);
 exit_release_d:
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index faca808cb3d9..7f5761cffd2e 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -91,3 +91,9 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
        return platform_device_register(pdev);
 }
+static  int __init omap_i2c_cmdline(void)
+{
+        return omap_register_i2c_bus_cmdline();
+}
+subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h
index ad6fbe7d83f2..4869633de8cd 100644
--- a/arch/arm/mach-omap1/include/mach/uncompress.h
+++ b/arch/arm/mach-omap1/include/mach/uncompress.h
@@ -115,8 +115,3 @@ static inline void arch_decomp_setup(void)
                DEBUG_LL_OMAP1(3, sx1);
        } while (0);
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d4816fd6fc9..726ec23d29c7 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -145,7 +145,6 @@ static void omap_mpu_set_mode(enum clock_event_mode mode,
 static struct clock_event_device clockevent_mpu_timer1 = {
        .name           = "mpu_timer1",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .set_next_event = omap_mpu_set_next_event,
        .set_mode       = omap_mpu_set_mode,
 };
@@ -170,15 +169,9 @@ static __init void omap_init_mpu_timer(unsigned long rate)
        setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
        omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
-        clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
-                                            clockevent_mpu_timer1.shift);
-        clockevent_mpu_timer1.max_delta_ns =
-                clockevent_delta2ns(-1, &clockevent_mpu_timer1);
-        clockevent_mpu_timer1.min_delta_ns =
-                clockevent_delta2ns(1, &clockevent_mpu_timer1);
        clockevent_mpu_timer1.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_mpu_timer1);
+        clockevents_config_and_register(&clockevent_mpu_timer1, rate,
+                                        1, -1);
 }
@@ -236,12 +229,8 @@ static inline void omap_mpu_timer_init(void)
 * Timer initialization
 * ---------------------------------------------------------------------------
 */
-static void __init omap1_timer_init(void)
+void __init omap1_timer_init(void)
 {
        if (omap_32k_timer_init() != 0)
                omap_mpu_timer_init();
 }
-struct sys_timer omap1_timer = {
-        .init           = omap1_timer_init,
-};
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 41152fadd4c0..0b74246ba62c 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -140,7 +140,6 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device clockevent_32k_timer = {
        .name           = "32k-timer",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .set_next_event = omap_32k_timer_set_next_event,
        .set_mode       = omap_32k_timer_set_mode,
 };
@@ -165,16 +164,9 @@ static __init void omap_init_32k_timer(void)
 {
        setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-        clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
-                                           NSEC_PER_SEC,
-                                           clockevent_32k_timer.shift);
-        clockevent_32k_timer.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
-        clockevent_32k_timer.min_delta_ns =
-                clockevent_delta2ns(1, &clockevent_32k_timer);
        clockevent_32k_timer.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_32k_timer);
+        clockevents_config_and_register(&clockevent_32k_timer,
+                                        OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
 }
 /*
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 41b581fd0213..49ac3dfebef9 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,3 +1,26 @@
+config ARCH_OMAP
+        bool
+config ARCH_OMAP2PLUS
+        bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_OMAP
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select HAVE_CLK
+        select OMAP_DM_TIMER
+        select PINCTRL
+        select PROC_DEVICETREE if PROC_FS
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
 if ARCH_OMAP2PLUS
 menu "TI OMAP2/3/4 Specific Features"
@@ -76,12 +99,12 @@ config ARCH_OMAP4
 config SOC_OMAP5
        bool "TI OMAP5"
-        select ARM_ARCH_TIMER
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
        select CPU_V7
        select HAVE_SMP
        select COMMON_CLK
+        select HAVE_ARM_ARCH_TIMER
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
@@ -165,12 +188,6 @@ config MACH_OMAP_H4
        select OMAP_DEBUG_DEVICES
        select OMAP_PACKAGE_ZAF
-config MACH_OMAP_APOLLON
-        bool "OMAP 2420 Apollon board"
-        depends on SOC_OMAP2420
-        default y
-        select OMAP_PACKAGE_ZAC
 config MACH_OMAP_2430SDP
        bool "OMAP 2430 SDP board"
        depends on SOC_OMAP2430
@@ -397,7 +414,7 @@ config OMAP3_SDRC_AC_TIMING
 config OMAP4_ERRATA_I688
        bool "OMAP4 errata: Async Bridge Corruption"
-        depends on ARCH_OMAP4
+        depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
        select ARCH_HAS_BARRIERS
        help
          If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 947cafe65aef..b068b7fe99ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -2,13 +2,16 @@
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-omap/include
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
         omap_device.o sram.o
 omap-2-3-common                         = irq.o
-hwmod-common                            = omap_hwmod.o \
+hwmod-common                            = omap_hwmod.o omap_hwmod_reset.o \
                                          omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
                                          clkt_dpll.o clkt_clksel.o
@@ -53,6 +56,7 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 # Restart code (OMAP4/5 currently in omap4-common.c)
 obj-$(CONFIG_SOC_OMAP2420)              += omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
+obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
 # Pin multiplexing
@@ -220,7 +224,6 @@ endif
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
-obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
 obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
new file mode 100644
index 000000000000..88e4fa8af031
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -0,0 +1,34 @@
+/*
+ * am33xx-restart.c - Code common to all AM33xx machines.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include "common.h"
+#include "prm-regbits-33xx.h"
+#include "prm33xx.h"
+/**
+ * am3xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void am33xx_restart(char mode, const char *cmd)
+{
+        /* TODO: Handle mode and cmd if necessary */
+        am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK,
+                                AM33XX_GLOBAL_WARM_SW_RST_MASK,
+                                AM33XX_PRM_DEVICE_MOD,
+                                AM33XX_PRM_RSTCTRL_OFFSET);
+        /* OCP barrier */
+        (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
+                                  AM33XX_PRM_RSTCTRL_OFFSET);
+}
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index af11dcdb7e2c..25b79a297365 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -62,8 +62,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
 {
        struct platform_device *pdev;
-        pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
+        pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
-                                 NULL, 0, false);
        if (IS_ERR(pdev)) {
                WARN(1, "Can't build omap_device for %s:%s.\n",
                     oh->class->name, oh->name);
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 4815ea6f8f5d..a3e0aaa4886b 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -27,6 +27,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -263,6 +264,7 @@ static void __init omap_2430sdp_init(void)
        omap_hsmmc_init(mmc);
        omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_smc91x_init();
@@ -284,6 +286,6 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_2430sdp_init,
        .init_late      = omap2430_init_late,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index bb73afc9ac17..ce812decfaca 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -25,6 +25,8 @@
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/omap-twl4030.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -209,6 +211,19 @@ static struct omap2_hsmmc_info mmc[] = {
        {}      /* Terminator */
 };
+static struct omap_tw4030_pdata omap_twl4030_audio_data = {
+        .voice_connected = true,
+        .custom_routing = true,
+        .has_hs         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+        .has_hf         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+        .has_mainmic    = true,
+        .has_submic     = true,
+        .has_hsmic      = true,
+        .has_linein     = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+};
 static int sdp3430_twl_gpio_setup(struct device *dev,
                unsigned gpio, unsigned ngpio)
 {
@@ -225,6 +240,9 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
        /* gpio + 15 is "sub_lcd_nRST" (output) */
        gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
+        omap_twl4030_audio_data.jack_detect = gpio + 2;
+        omap_twl4030_audio_init("SDP3430", &omap_twl4030_audio_data);
        return 0;
 }
@@ -382,6 +400,9 @@ static int __init omap3430_i2c_init(void)
        sdp3430_twldata.vpll2->constraints.apply_uV = true;
        sdp3430_twldata.vpll2->constraints.name = "VDVI";
+        sdp3430_twldata.audio->codec->hs_extmute = 1;
+        sdp3430_twldata.audio->codec->hs_extmute_gpio = -EINVAL;
        omap3_pmic_init("twl4030", &sdp3430_twldata);
        /* i2c2 on camera connector (for sensor control) and optional isp1301 */
@@ -424,7 +445,7 @@ static void enable_board_wakeup_source(void)
                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -579,6 +600,7 @@ static void __init omap_3430sdp_init(void)
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
        omap_serial_init();
        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_smc91x_init();
        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
@@ -597,6 +619,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_3430sdp_init,
        .init_late      = omap3430_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 050aaa771254..67447bd4564f 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -53,7 +53,7 @@ static void enable_board_wakeup_source(void)
                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -211,6 +211,6 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_sdp_init,
        .init_late      = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 1cc6696594fd..35f3ad0cb7c7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -24,12 +24,15 @@
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/pwm.h>
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
+#include <linux/pwm_backlight.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap4-keypad.h>
 #include <linux/usb/musb.h>
+#include <linux/usb/phy.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -256,10 +259,20 @@ static struct gpio_led_platform_data sdp4430_led_data = {
        .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
 };
+static struct pwm_lookup sdp4430_pwm_lookup[] = {
+        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
+        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
+        PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
+};
 static struct led_pwm sdp4430_pwm_leds[] = {
        {
+                .name           = "omap4::keypad",
+                .max_brightness = 127,
+                .pwm_period_ns  = 7812500,
+        },
+        {
                .name           = "omap4:green:chrg",
-                .pwm_id         = 1,
                .max_brightness = 255,
                .pwm_period_ns  = 7812500,
        },
@@ -278,6 +291,20 @@ static struct platform_device sdp4430_leds_pwm = {
        },
 };
+static struct platform_pwm_backlight_data sdp4430_backlight_data = {
+        .max_brightness = 127,
+        .dft_brightness = 127,
+        .pwm_period_ns = 7812500,
+};
+static struct platform_device sdp4430_backlight_pwm = {
+        .name   = "pwm-backlight",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &sdp4430_backlight_data,
+        },
+};
 static int omap_prox_activate(struct device *dev)
 {
        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
@@ -412,6 +439,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
        &sdp4430_gpio_keys_device,
        &sdp4430_leds_gpio,
        &sdp4430_leds_pwm,
+        &sdp4430_backlight_pwm,
        &sdp4430_vbat,
        &sdp4430_dmic_codec,
        &sdp4430_abe_audio,
@@ -696,6 +724,7 @@ static void __init omap_4430sdp_init(void)
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
        usb_musb_init(&musb_board_data);
        status = omap_ethernet_init();
@@ -707,6 +736,7 @@ static void __init omap_4430sdp_init(void)
                                ARRAY_SIZE(sdp4430_spi_board_info));
        }
+        pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
        status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
        if (status)
                pr_err("Keypad initialization failed: %d\n", status);
@@ -722,9 +752,8 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = omap_4430sdp_init,
        .init_late      = omap4430_init_late,
-        .timer          = &omap4_timer,
+        .init_time      = omap4_local_timer_init,
        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 51b96a1206d1..7d3358b2e593 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -20,12 +20,18 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/mfd/tps65910.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include "common.h"
+#include "common-board-devices.h"
+#include "board-flash.h"
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -36,11 +42,12 @@
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
-static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -51,6 +58,54 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .reset_gpio_port[2]  = -EINVAL
 };
+static struct mtd_partition crane_nand_partitions[] = {
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 14 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "U-Boot Env",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 2 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 40 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "File System",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+static struct tps65910_board tps65910_pdata = {
+        .irq = 7 + OMAP_INTC_START,
+        .en_ck32k_xtal = true,
+};
+static struct i2c_board_info __initdata tps65910_board_info[] = {
+        {
+                I2C_BOARD_INFO("tps65910", 0x2d),
+                .platform_data = &tps65910_pdata,
+        },
+};
+static void __init am3517_crane_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, tps65910_board_info,
+                        ARRAY_SIZE(tps65910_board_info));
+}
 static void __init am3517_crane_init(void)
 {
        int ret;
@@ -58,6 +113,10 @@ static void __init am3517_crane_init(void)
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
+        board_nand_init(crane_nand_partitions,
+                        ARRAY_SIZE(crane_nand_partitions), 0,
+                        NAND_BUSWIDTH_16, NULL);
+        am3517_crane_i2c_init();
        /* Configure GPIO for EHCI port */
        if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
@@ -92,6 +151,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_crane_init,
        .init_late      = am35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index f81a303b87ff..9fb85908a61e 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -274,7 +274,7 @@ static __init void am3517_evm_mcbsp1_init(void)
        omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
 }
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
                defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
@@ -393,6 +393,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_evm_init,
        .init_late      = am35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
deleted file mode 100644
index 5d0a61f54165..000000000000
--- a/arch/arm/mach-omap2/board-apollon.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-apollon.c
- *
- * Copyright (C) 2005,2006 Samsung Electronics
- * Author: Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Modified from mach-omap/omap2/board-h4.c
- *
- * Code for apollon OMAP2 board. Should work on many OMAP2 systems where
- * the bootloader passes the board-specific data to the kernel.
- * Do not put any board specific code to this file; create a new machine
- * type if you need custom low-level initializations.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/onenand.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/smc91x.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/leds-omap.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include "common.h"
-#include "gpmc.h"
-#include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include "mux.h"
-#include "control.h"
-/* LED & Switch macros */
-#define LED0_GPIO13             13
-#define LED1_GPIO14             14
-#define LED2_GPIO15             15
-#define SW_ENTER_GPIO16         16
-#define SW_UP_GPIO17            17
-#define SW_DOWN_GPIO58          58
-#define APOLLON_FLASH_CS        0
-#define APOLLON_ETH_CS          1
-#define APOLLON_ETHR_GPIO_IRQ   74
-static struct mtd_partition apollon_partitions[] = {
-        {
-                .name           = "X-Loader + U-Boot",
-                .offset         = 0,
-                .size           = SZ_128K,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "params",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_128K,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_2M,
-        },
-        {
-                .name           = "rootfs",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_16M,
-        },
-        {
-                .name           = "filesystem00",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_32M,
-        },
-        {
-                .name           = "filesystem01",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct onenand_platform_data apollon_flash_data = {
-        .parts          = apollon_partitions,
-        .nr_parts       = ARRAY_SIZE(apollon_partitions),
-};
-static struct resource apollon_flash_resource[] = {
-        [0] = {
-                .flags          = IORESOURCE_MEM,
-        },
-};
-static struct platform_device apollon_onenand_device = {
-        .name           = "onenand-flash",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &apollon_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(apollon_flash_resource),
-        .resource       = apollon_flash_resource,
-};
-static void __init apollon_flash_init(void)
-{
-        unsigned long base;
-        if (gpmc_cs_request(APOLLON_FLASH_CS, SZ_128K, &base) < 0) {
-                printk(KERN_ERR "Cannot request OneNAND GPMC CS\n");
-                return;
-        }
-        apollon_flash_resource[0].start = base;
-        apollon_flash_resource[0].end   = base + SZ_128K - 1;
-}
-static struct smc91x_platdata appolon_smc91x_info = {
-        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-        .leda   = RPC_LED_100_10,
-        .ledb   = RPC_LED_TX_RX,
-};
-static struct resource apollon_smc91x_resources[] = {
-        [0] = {
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        },
-};
-static struct platform_device apollon_smc91x_device = {
-        .name           = "smc91x",
-        .id             = -1,
-        .dev    = {
-                .platform_data  = &appolon_smc91x_info,
-        },
-        .num_resources  = ARRAY_SIZE(apollon_smc91x_resources),
-        .resource       = apollon_smc91x_resources,
-};
-static struct omap_led_config apollon_led_config[] = {
-        {
-                .cdev   = {
-                        .name   = "apollon:led0",
-                },
-                .gpio   = LED0_GPIO13,
-        },
-        {
-                .cdev   = {
-                        .name   = "apollon:led1",
-                },
-                .gpio   = LED1_GPIO14,
-        },
-        {
-                .cdev   = {
-                        .name   = "apollon:led2",
-                },
-                .gpio   = LED2_GPIO15,
-        },
-};
-static struct omap_led_platform_data apollon_led_data = {
-        .nr_leds        = ARRAY_SIZE(apollon_led_config),
-        .leds           = apollon_led_config,
-};
-static struct platform_device apollon_led_device = {
-        .name           = "omap-led",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &apollon_led_data,
-        },
-};
-static struct platform_device *apollon_devices[] __initdata = {
-        &apollon_onenand_device,
-        &apollon_smc91x_device,
-        &apollon_led_device,
-};
-static inline void __init apollon_init_smc91x(void)
-{
-        unsigned long base;
-        unsigned int rate;
-        struct clk *gpmc_fck;
-        int eth_cs;
-        int err;
-        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
-        if (IS_ERR(gpmc_fck)) {
-                WARN_ON(1);
-                return;
-        }
-        clk_prepare_enable(gpmc_fck);
-        rate = clk_get_rate(gpmc_fck);
-        eth_cs = APOLLON_ETH_CS;
-        /* Make sure CS1 timings are correct */
-        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
-        if (rate >= 160000000) {
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
-        } else if (rate >= 130000000) {
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
-        } else {/* rate = 100000000 */
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
-        }
-        if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
-                goto out;
-        }
-        apollon_smc91x_resources[0].start = base + 0x300;
-        apollon_smc91x_resources[0].end   = base + 0x30f;
-        udelay(100);
-        omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0);
-        err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq");
-        if (err) {
-                printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
-                        APOLLON_ETHR_GPIO_IRQ);
-                gpmc_cs_free(APOLLON_ETH_CS);
-        }
-out:
-        clk_disable_unprepare(gpmc_fck);
-        clk_put(gpmc_fck);
-}
-static struct panel_generic_dpi_data apollon_panel_data = {
-        .name                   = "apollon",
-};
-static struct omap_dss_device apollon_lcd_device = {
-        .name                   = "lcd",
-        .driver_name            = "generic_dpi_panel",
-        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .phy.dpi.data_lines     = 18,
-        .data                   = &apollon_panel_data,
-};
-static struct omap_dss_device *apollon_dss_devices[] = {
-        &apollon_lcd_device,
-};
-static struct omap_dss_board_info apollon_dss_data = {
-        .num_devices    = ARRAY_SIZE(apollon_dss_devices),
-        .devices        = apollon_dss_devices,
-        .default_device = &apollon_lcd_device,
-};
-static struct gpio apollon_gpio_leds[] __initdata = {
-        { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
-        { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
-        { LED2_GPIO15, GPIOF_OUT_INIT_LOW, "LED2" }, /* LED2 - AA4  */
-};
-static void __init apollon_led_init(void)
-{
-        omap_mux_init_signal("vlynq_clk.gpio_13", 0);
-        omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
-        omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
-        gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
-}
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-static void __init omap_apollon_init(void)
-{
-        u32 v;
-        omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-        apollon_init_smc91x();
-        apollon_led_init();
-        apollon_flash_init();
-        /* REVISIT: where's the correct place */
-        omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
-        /* LCD PWR_EN */
-        omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
-        /* Use Internal loop-back in MMC/SDIO Module Input Clock selection */
-        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        v |= (1 << 24);
-        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-        /*
-         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
-         * if not needed.
-         */
-        apollon_smc91x_resources[1].start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
-        apollon_smc91x_resources[1].end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
-        platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap_display_init(&apollon_dss_data);
-}
-MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap242x_map_io,
-        .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = omap_apollon_init,
-        .init_late      = omap2420_init_late,
-        .timer          = &omap2_timer,
-        .restart        = omap2xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index b3102c2f4a3c..af2bb219e214 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
@@ -418,7 +419,7 @@ static struct omap2_hsmmc_info mmc[] = {
        {}      /* Terminator */
 };
-static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -722,8 +723,9 @@ static void __init cm_t3x_common_init(void)
        cm_t35_init_ethernet();
        cm_t35_init_led();
        cm_t35_init_display();
-        omap_twl4030_audio_init("cm-t3x");
+        omap_twl4030_audio_init("cm-t3x", NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        cm_t35_init_usbh();
        cm_t35_init_camera();
@@ -751,7 +753,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t35_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -764,6 +766,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3730_init,
        .init_late     = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index ebbc2adb499e..a66da808cc4a 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -32,6 +32,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mmc/host.h>
 #include <linux/can/platform/ti_hecc.h>
 #include <asm/mach-types.h>
@@ -46,6 +47,7 @@
 #include "mux.h"
 #include "control.h"
+#include "hsmmc.h"
 #include "common-board-devices.h"
 #include "am35xx-emac.h"
 #include "gpmc-nand.h"
@@ -121,6 +123,26 @@ static void cm_t3517_init_hecc(void)
 static inline void cm_t3517_init_hecc(void) {}
 #endif
+#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+static struct omap2_hsmmc_info cm_t3517_mmc[] = {
+        {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = 144,
+                .gpio_wp        = 59,
+        },
+        {
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+#else
+#define cm_t3517_mmc NULL
+#endif
 #if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
 #define RTC_IO_GPIO             (153)
 #define RTC_WR_GPIO             (154)
@@ -166,7 +188,7 @@ static inline void cm_t3517_init_rtc(void) {}
 #define HSUSB2_RESET_GPIO       (147)
 #define USB_HUB_RESET_GPIO      (152)
-static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = {
+static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -271,6 +293,10 @@ static struct omap_board_mux board_mux[] __initdata = {
        /* CM-T3517 USB HUB nRESET */
        OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* CD - GPIO144 and WP - GPIO59 for MMC1 - SB-T35 */
+        OMAP3_MUX(UART2_CTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(GPMC_CLK, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
@@ -286,6 +312,7 @@ static void __init cm_t3517_init(void)
        cm_t3517_init_usbh();
        cm_t3517_init_hecc();
        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
+        omap_hsmmc_init(cm_t3517_mmc);
 }
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
@@ -297,6 +324,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3517_init,
        .init_late      = am35xx_init_late,
-        .timer          = &omap3_gp_timer,
+        .init_time      = omap3_gp_gptimer_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 12865af25d3a..53056c3b0836 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -435,7 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
        &omap_dm9000_dev,
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -622,12 +623,13 @@ static void __init devkit8000_init(void)
        omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(devkit8000_nand_partitions,
                        ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
                        NAND_BUSWIDTH_16, NULL);
-        omap_twl4030_audio_init("omap3beagle");
+        omap_twl4030_audio_init("omap3beagle", NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -643,6 +645,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = devkit8000_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_secure_timer,
+        .init_time      = omap3_secure_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 53cb380b7877..0274ff7a2a2b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -16,7 +16,6 @@
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include "common.h"
@@ -65,7 +64,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .dt_compat      = omap242x_boards_compat,
        .restart        = omap2xxx_restart,
 MACHINE_END
@@ -84,7 +83,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .dt_compat      = omap243x_boards_compat,
        .restart        = omap2xxx_restart,
 MACHINE_END
@@ -103,7 +102,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .dt_compat      = omap3_boards_compat,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -120,7 +119,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap3_secure_timer,
+        .init_time      = omap3_secure_sync32k_timer_init,
        .dt_compat      = omap3_gp_boards_compat,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -139,8 +138,9 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
        .init_irq       = omap_intc_of_init,
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap3_am33xx_timer,
+        .init_time      = omap3_am33xx_gptimer_timer_init,
        .dt_compat      = am33xx_boards_compat,
+        .restart        = am33xx_restart,
 MACHINE_END
 #endif
@@ -156,10 +156,9 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = omap_gic_of_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = omap_generic_init,
        .init_late      = omap4430_init_late,
-        .timer          = &omap4_timer,
+        .init_time      = omap4_local_timer_init,
        .dt_compat      = omap4_boards_compat,
        .restart        = omap44xx_restart,
 MACHINE_END
@@ -177,9 +176,8 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
        .map_io         = omap5_map_io,
        .init_early     = omap5_init_early,
        .init_irq       = omap_gic_of_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = omap_generic_init,
-        .timer          = &omap5_timer,
+        .init_time      = omap5_realtime_timer_init,
        .dt_compat      = omap5_boards_compat,
        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 3be1311f9e33..812c829fa46f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -342,6 +342,6 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_h4_init,
        .init_late      = omap2420_init_late,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0f24cb84ba5a..bf92678a01d0 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -18,6 +18,7 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/input.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -300,20 +301,20 @@ static struct omap2_hsmmc_info mmc[] = {
 static struct gpio_led igep_gpio_leds[] = {
        [0] = {
-                .name                   = "gpio-led:red:d0",
+                .name                   = "omap3:red:user0",
-                .default_trigger        = "default-off"
+                .default_state          = 0,
        },
        [1] = {
-                .name                   = "gpio-led:green:d0",
+                .name                   = "omap3:green:boot",
-                .default_trigger        = "default-off",
+                .default_state          = 1,
        },
        [2] = {
-                .name                   = "gpio-led:red:d1",
+                .name                   = "omap3:red:user1",
-                .default_trigger        = "default-off",
+                .default_state          = 0,
        },
        [3] = {
-                .name                   = "gpio-led:green:d1",
+                .name                   = "omap3:green:user1",
-                .default_trigger        = "heartbeat",
+                .default_state          = 0,
                .gpio                   = -EINVAL, /* gets replaced */
                .active_low             = 1,
        },
@@ -526,7 +527,7 @@ static void __init igep_i2c_init(void)
        omap3_pmic_init("twl4030", &igep_twldata);
 }
-static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -537,7 +538,7 @@ static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
        .reset_gpio_port[2] = -EINVAL,
 };
-static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -625,11 +626,12 @@ static void __init igep_init(void)
        omap_serial_init();
        omap_sdrc_init(m65kxxxxam_sdrc_params,
                                  m65kxxxxam_sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        igep_flash_init();
        igep_leds_init();
-        omap_twl4030_audio_init("igep2");
+        omap_twl4030_audio_init("igep2", NULL);
        /*
         * WLAN-BT combo module from MuRata which has a Marvell WLAN
@@ -655,7 +657,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -668,6 +670,6 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 0869f4f3d3e1..b12fe966a7b9 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
@@ -418,6 +419,7 @@ static void __init omap_ldp_init(void)
        omap_ads7846_init(1, 54, 310, NULL);
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
                        ZOOM_NAND_CS, 0, nand_default_timings);
@@ -435,6 +437,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_ldp_init,
        .init_late      = omap3430_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 0abb30fe399c..f6eeb87e4e95 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -731,7 +731,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .restart        = omap2xxx_restart,
 MACHINE_END
@@ -744,7 +744,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .restart        = omap2xxx_restart,
 MACHINE_END
@@ -757,6 +757,6 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
-        .timer          = &omap2_timer,
+        .init_time      = omap2_sync32k_timer_init,
        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 22c483d5dfa8..c3558f93d42c 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -20,6 +20,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/leds.h>
+#include <linux/pwm.h>
+#include <linux/leds_pwm.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -30,6 +32,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -55,6 +58,32 @@
 #define NAND_CS 0
+static struct pwm_lookup pwm_lookup[] = {
+        /* LEDB -> PMU_STAT */
+        PWM_LOOKUP("twl-pwmled", 1, "leds_pwm", "beagleboard::pmu_stat"),
+};
+static struct led_pwm pwm_leds[] = {
+        {
+                .name           = "beagleboard::pmu_stat",
+                .max_brightness = 127,
+                .pwm_period_ns  = 7812500,
+        },
+};
+static struct led_pwm_platform_data pwm_data = {
+        .num_leds       = ARRAY_SIZE(pwm_leds),
+        .leds           = pwm_leds,
+};
+static struct platform_device leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &pwm_data,
+        },
+};
 /*
 * OMAP3 Beagle revision
 * Run time detection of Beagle revision is done by reading GPIO.
@@ -292,9 +321,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
                        "nEN_USB_PWR");
-        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
        return 0;
 }
@@ -376,11 +402,6 @@ static struct gpio_led gpio_leds[] = {
                .default_trigger        = "mmc0",
                .gpio                   = 149,
        },
-        {
-                .name                   = "beagleboard::pmu_stat",
-                .gpio                   = -EINVAL,      /* gets replaced */
-                .active_low             = true,
-        },
 };
 static struct gpio_led_platform_data gpio_led_info = {
@@ -428,9 +449,10 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
        &leds_gpio,
        &keys_gpio,
        &madc_hwmon,
+        &leds_pwm,
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -494,7 +516,7 @@ static int __init beagle_opp_init(void)
        }
        return 0;
 }
-device_initcall(beagle_opp_init);
+omap_device_initcall(beagle_opp_init);
 static void __init omap3_beagle_init(void)
 {
@@ -519,12 +541,13 @@ static void __init omap3_beagle_init(void)
        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                                  mt46h32m32lf6_sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3beagle_nand_partitions,
                        ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
                        NAND_BUSWIDTH_16, NULL);
-        omap_twl4030_audio_init("omap3beagle");
+        omap_twl4030_audio_init("omap3beagle", NULL);
        /* Ensure msecure is mux'd to be able to set the RTC. */
        omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
@@ -532,6 +555,8 @@ static void __init omap3_beagle_init(void)
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+        pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
 }
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
@@ -544,6 +569,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_beagle_init,
        .init_late      = omap3_init_late,
-        .timer          = &omap3_secure_timer,
+        .init_time      = omap3_secure_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 3985f35aee06..48789e0bb915 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -41,6 +41,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
 #include <linux/export.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -309,7 +310,7 @@ static struct omap2_hsmmc_info mmc[] = {
                .gpio_wp        = 63,
                .deferred       = true,
        },
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        {
                .name           = "wl1271",
                .mmc            = 2,
@@ -450,7 +451,7 @@ static struct regulator_init_data omap3evm_vio = {
        .consumer_supplies      = omap3evm_vio_supply,
 };
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
 #define OMAP3EVM_WLAN_PMENA_GPIO        (150)
 #define OMAP3EVM_WLAN_IRQ_GPIO          (149)
@@ -538,7 +539,7 @@ static int __init omap3_evm_i2c_init(void)
        return 0;
 }
-static struct usbhs_omap_board_data usbhs_bdata __initdata = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -563,7 +564,7 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
                                OMAP_PIN_OFF_NONE),
        OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
                                OMAP_PIN_OFF_NONE),
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        /* WLAN IRQ - GPIO 149 */
        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
@@ -601,7 +602,7 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = {
        OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
        OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        /* WLAN IRQ - GPIO 149 */
        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
@@ -637,7 +638,7 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = {
 static void __init omap3_evm_wl12xx_init(void)
 {
-#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#ifdef CONFIG_WILINK_PLATFORM_DATA
        int ret;
        /* WL12xx WLAN Init */
@@ -734,6 +735,7 @@ static void __init omap3_evm_init(void)
                omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
                usbhs_bdata.reset_gpio_port[1] = 135;
        }
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(&musb_board_data);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3evm_nand_partitions,
@@ -744,7 +746,7 @@ static void __init omap3_evm_init(void)
        omap3evm_init_smsc911x();
        omap3_evm_display_init();
        omap3_evm_wl12xx_init();
-        omap_twl4030_audio_init("omap3evm");
+        omap_twl4030_audio_init("omap3evm", NULL);
 }
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
@@ -757,6 +759,6 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_evm_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 2a065ba6eb58..bab51e64c4b5 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -29,6 +29,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,6 +216,7 @@ static void __init omap3logic_init(void)
        board_mmc_init();
        board_smsc911x_init();
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
@@ -231,7 +233,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -244,6 +246,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index a53a6683c1b8..2bba362148a0 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -35,6 +35,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
@@ -567,7 +568,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
        &pandora_backlight,
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -601,6 +602,7 @@ static void __init omap3pandora_init(void)
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
        usbhs_init(&usbhs_bdata);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        gpmc_nand_init(&pandora_nand_data, NULL);
@@ -618,6 +620,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3pandora_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 53a6cbcf9747..95c10b3aa678 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -33,6 +33,7 @@
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/i2c/at24.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -361,7 +362,7 @@ static struct platform_device *omap3_stalker_devices[] __initdata = {
        &keys_gpio,
 };
-static struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -404,6 +405,7 @@ static void __init omap3_stalker_init(void)
        omap_serial_init();
        omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
@@ -427,6 +429,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        .handle_irq             = omap3_intc_handle_irq,
        .init_machine           = omap3_stalker_init,
        .init_late              = omap35xx_init_late,
-        .timer                  = &omap3_secure_timer,
+        .init_time              = omap3_secure_sync32k_timer_init,
        .restart                = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 263cb9cfbf37..bcd44fbcd877 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
@@ -309,7 +310,7 @@ static struct platform_device *omap3_touchbook_devices[] __initdata = {
        &keys_gpio,
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -365,6 +366,7 @@ static void __init omap3_touchbook_init(void)
        /* Touchscreen and accelerometer */
        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        board_nand_init(omap3touchbook_nand_partitions,
@@ -386,6 +388,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_touchbook_init,
        .init_late      = omap3430_init_late,
-        .timer          = &omap3_secure_timer,
+        .init_time      = omap3_secure_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 769c1feee1c4..b02c2f00609b 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -30,10 +30,11 @@
 #include <linux/regulator/fixed.h>
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
+#include <linux/usb/phy.h>
 #include <linux/wl12xx.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -139,7 +140,7 @@ static struct platform_device *panda_devices[] __initdata = {
        &btwilink_device,
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -447,6 +448,7 @@ static void __init omap4_panda_init(void)
        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
+        usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto");
        usb_musb_init(&musb_board_data);
        omap4_panda_display_init();
 }
@@ -459,9 +461,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = omap4_panda_init,
        .init_late      = omap4430_init_late,
-        .timer          = &omap4_timer,
+        .init_time      = omap4_local_timer_init,
        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index c8fde3e56441..86bab51154ee 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -36,6 +36,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/phy.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
@@ -457,7 +458,7 @@ static int __init overo_spi_init(void)
        return 0;
 }
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -499,6 +500,7 @@ static void __init overo_init(void)
                                  mt46h32m32lf6_sdrc_params);
        board_nand_init(overo_nand_partitions,
                        ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        overo_spi_init();
@@ -506,7 +508,7 @@ static void __init overo_init(void)
        overo_display_init();
        overo_init_led();
        overo_init_keys();
-        omap_twl4030_audio_init("overo");
+        omap_twl4030_audio_init("overo", NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -551,6 +553,6 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = overo_init,
        .init_late      = omap35xx_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0c777b75e484..345e8c4b8731 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -18,6 +18,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/usb/phy.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -134,6 +135,7 @@ static void __init rm680_init(void)
        sdrc_params = nokia_get_sdram_timings();
        omap_sdrc_init(sdrc_params, sdrc_params);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        rm680_peripherals_init();
 }
@@ -147,7 +149,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rm680_init,
        .init_late      = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -160,6 +162,6 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rm680_init,
        .init_late      = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index cf07e289b4ea..3a077df6b8df 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -40,9 +40,9 @@
 #include <sound/tpa6130a2-plat.h>
 #include <media/radio-si4713.h>
 #include <media/si4713.h>
-#include <linux/leds-lp5523.h>
+#include <linux/platform_data/leds-lp55xx.h>
-#include <../drivers/staging/iio/light/tsl2563.h>
+#include <linux/platform_data/tsl2563.h>
 #include <linux/lis3lv02d.h>
 #if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
@@ -160,32 +160,41 @@ static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
 #endif
 #if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
-static struct lp5523_led_config rx51_lp5523_led_config[] = {
+static struct lp55xx_led_config rx51_lp5523_led_config[] = {
        {
+                .name           = "lp5523:kb1",
                .chan_nr        = 0,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:kb2",
                .chan_nr        = 1,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:kb3",
                .chan_nr        = 2,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:kb4",
                .chan_nr        = 3,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:b",
                .chan_nr        = 4,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:g",
                .chan_nr        = 5,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:r",
                .chan_nr        = 6,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:kb5",
                .chan_nr        = 7,
                .led_current    = 50,
        }, {
+                .name           = "lp5523:kb6",
                .chan_nr        = 8,
                .led_current    = 50,
        }
@@ -207,10 +216,10 @@ static void rx51_lp5523_enable(bool state)
        gpio_set_value(RX51_LP5523_CHIP_EN_GPIO, !!state);
 }
-static struct lp5523_platform_data rx51_lp5523_platform_data = {
+static struct lp55xx_platform_data rx51_lp5523_platform_data = {
        .led_config             = rx51_lp5523_led_config,
        .num_channels           = ARRAY_SIZE(rx51_lp5523_led_config),
-        .clock_mode             = LP5523_CLOCK_AUTO,
+        .clock_mode             = LP55XX_CLOCK_AUTO,
        .setup_resources        = rx51_lp5523_setup,
        .release_resources      = rx51_lp5523_release,
        .enable                 = rx51_lp5523_enable,
@@ -1253,6 +1262,16 @@ static void __init rx51_init_lirc(void)
 }
 #endif
+static struct platform_device madc_hwmon = {
+        .name   = "twl4030_madc_hwmon",
+        .id     = -1,
+};
+static void __init rx51_init_twl4030_hwmon(void)
+{
+        platform_device_register(&madc_hwmon);
+}
 void __init rx51_peripherals_init(void)
 {
        rx51_i2c_init();
@@ -1272,5 +1291,6 @@ void __init rx51_peripherals_init(void)
                omap_hsmmc_init(mmc);
        rx51_charger_init();
+        rx51_init_twl4030_hwmon();
 }
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 46f4fc982766..eb667261df08 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -18,6 +18,7 @@
 #include <video/omapdss.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include "soc.h"
 #include "board-rx51.h"
 #include "mux.h"
@@ -85,5 +86,5 @@ static int __init rx51_video_init(void)
        return 0;
 }
-subsys_initcall(rx51_video_init);
+omap_subsys_initcall(rx51_video_init);
 #endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index d0374ea2dfb0..f7c4616cbb60 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -123,6 +123,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rx51_init,
        .init_late      = omap3430_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 1a3e056d63a7..6273c286e1d8 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -43,7 +43,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
        .map_io         = ti81xx_map_io,
        .init_early     = ti81xx_init_early,
        .init_irq       = ti81xx_init_irq,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .init_machine   = ti81xx_evm_init,
        .init_late      = ti81xx_init_late,
        .restart        = omap44xx_restart,
@@ -55,7 +55,7 @@ MACHINE_START(TI8148EVM, "ti8148evm")
        .map_io         = ti81xx_map_io,
        .init_early     = ti81xx_init_early,
        .init_irq       = ti81xx_init_irq,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .init_machine   = ti81xx_evm_init,
        .init_late      = ti81xx_init_late,
        .restart        = omap44xx_restart,
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 1c7c834a5b5f..8cef477d6b00 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -49,13 +49,13 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
 }
-/*
+/* Register offsets in TWL4030_MODULE_INTBR */
- * PWMA/B register offsets (TWL4030_MODULE_PWMA)
- */
 #define TWL_INTBR_PMBR1 0xD
 #define TWL_INTBR_GPBR1 0xC
-#define TWL_LED_PWMON   0x0
-#define TWL_LED_PWMOFF  0x1
+/* Register offsets in TWL_MODULE_PWM */
+#define TWL_LED_PWMON   0x3
+#define TWL_LED_PWMOFF  0x4
 static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
 {
@@ -93,8 +93,8 @@ static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
        }
        c = ((50 * (100 - level)) / 100) + 1;
-        twl_i2c_write_u8(TWL4030_MODULE_PWM1, 0x7F, TWL_LED_PWMOFF);
+        twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, TWL_LED_PWMOFF);
-        twl_i2c_write_u8(TWL4030_MODULE_PWM1, c, TWL_LED_PWMON);
+        twl_i2c_write_u8(TWL_MODULE_PWM, c, TWL_LED_PWMON);
 #else
        pr_warn("Backlight not enabled\n");
 #endif
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 26e07addc9d7..cdc0c1021863 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -20,6 +20,8 @@
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/omap-twl4030.h>
+#include <linux/usb/phy.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,11 +36,9 @@
 #include "common-board-devices.h"
 #define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
-#define ZOOM2_HEADSET_EXTMUTE_GPIO      (153)
+#define OMAP_ZOOM_TSC2004_IRQ_GPIO      (153)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
-#define LCD_PANEL_ENABLE_GPIO           (7 + OMAP_MAX_GPIO_LINES)
 /* Zoom2 has Qwerty keyboard*/
 static uint32_t board_keymap[] = {
        KEY(0, 0, KEY_E),
@@ -226,22 +226,31 @@ static struct omap2_hsmmc_info mmc[] = {
        {}      /* Terminator */
 };
+static struct omap_tw4030_pdata omap_twl4030_audio_data = {
+        .voice_connected = true,
+        .custom_routing = true,
+        .has_hs         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+        .has_hf         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+        .has_mainmic    = true,
+        .has_submic     = true,
+        .has_hsmic      = true,
+        .has_linein     = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
+};
 static int zoom_twl_gpio_setup(struct device *dev,
                unsigned gpio, unsigned ngpio)
 {
-        int ret;
        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
        mmc[0].gpio_cd = gpio + 0;
        omap_hsmmc_late_init(mmc);
-        ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
+        /* Audio setup */
-                               "lcd enable");
+        omap_twl4030_audio_data.jack_detect = gpio + 2;
-        if (ret)
+        omap_twl4030_audio_init("Zoom2", &omap_twl4030_audio_data);
-                pr_err("Failed to get LCD_PANEL_ENABLE_GPIO (gpio%d).\n",
-                                LCD_PANEL_ENABLE_GPIO);
-        return ret;
+        return 0;
 }
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
@@ -264,14 +273,9 @@ static int __init omap_i2c_init(void)
                        TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-        if (machine_is_omap_zoom2()) {
+        if (machine_is_omap_zoom2())
-                struct twl4030_codec_data *codec_data;
+                zoom_twldata.audio->codec->ramp_delay_value = 3; /* 161 ms */
-                codec_data = zoom_twldata.audio->codec;
-                codec_data->ramp_delay_value = 3;       /* 161 ms */
-                codec_data->hs_extmute = 1;
-                codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO;
-        }
        omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, NULL, 0);
@@ -298,6 +302,7 @@ void __init zoom_peripherals_init(void)
        omap_hsmmc_init(mmc);
        omap_i2c_init();
        platform_device_register(&omap_vwlan_device);
+        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
        usb_musb_init(NULL);
        enable_board_wakeup_source();
        omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index d7fa31e67238..5e4d4c9fe61a 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -92,7 +92,7 @@ static struct mtd_partition zoom_nand_partitions[] = {
        },
 };
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
        .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -137,7 +137,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .init_late      = omap3430_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
@@ -150,6 +150,6 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .init_late      = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .init_time      = omap3_sync32k_timer_init,
        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index ab7e952d2070..0f0a97c1fcc0 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -622,15 +622,10 @@ static struct clk_hw_omap gpios_fck_hw = {
 DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
-static struct clk wu_l4_ick;
-DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
-DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
 static struct clk gpios_ick;
 static const char *gpios_ick_parent_names[] = {
-        "wu_l4_ick",
+        "sys_ck",
 };
 static struct clk_hw_omap gpios_ick_hw = {
@@ -1682,13 +1677,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
 DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
-static struct clk wdt1_osc_ck;
-static const struct clk_ops wdt1_osc_ck_ops = {};
-DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
-DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
 static struct clk wdt3_fck;
 static struct clk_hw_omap wdt3_fck_hw = {
@@ -1767,7 +1755,6 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
@@ -1797,7 +1784,6 @@ static struct omap_clk omap2420_clks[] = {
        /* L4 domain clocks */
        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
-        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
        /* virtual meta-group clock */
        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
        /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index eb3dab68d536..aed8f74ca076 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -601,15 +601,10 @@ static struct clk_hw_omap gpios_fck_hw = {
 DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
-static struct clk wu_l4_ick;
-DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
-DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
 static struct clk gpios_ick;
 static const char *gpios_ick_parent_names[] = {
-        "wu_l4_ick",
+        "sys_ck",
 };
 static struct clk_hw_omap gpios_ick_hw = {
@@ -1811,13 +1806,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
 DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
-static struct clk wdt1_osc_ck;
-static const struct clk_ops wdt1_osc_ck_ops = {};
-DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
-DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
 static struct clk wdt4_fck;
 static struct clk_hw_omap wdt4_fck_hw = {
@@ -1869,7 +1857,6 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
@@ -1898,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
        /* L4 domain clocks */
        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
-        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
        /* virtual meta-group clock */
        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
        /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad606759..476b82066cb6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
 * and ALT_CLK1/2)
 */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
+DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-                   AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
+                   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
 /* DPLL_PER */
 static struct dpll_data dpll_per_dd = {
@@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 };
-DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
+DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
+                        gpio_fck_ops, CLK_SET_RATE_PARENT);
 DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 6ef87580c33f..4579c3c5338f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = {
        .parent_names   = dpll4_m5x2_ck_parent_names,
        .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
        .ops            = &dpll4_m5x2_ck_3630_ops,
+        .flags          = CLK_SET_RATE_PARENT,
 };
 static struct clk cam_mclk;
@@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = {
        .clkdm_name     = "cam_clkdm",
 };
-DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .hw             = &cam_mclk_hw.hw,
+        .parent_names   = cam_mclk_parent_names,
+        .num_parents    = ARRAY_SIZE(cam_mclk_parent_names),
+        .ops            = &aes2_ick_ops,
+        .flags          = CLK_SET_RATE_PARENT,
+};
 static const struct clksel_rate clkout2_src_core_rates[] = {
        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046b47f4..3d58f335f173 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -16,6 +16,10 @@
 * XXX Some of the ES1 clocks have been removed/changed; once support
 * is added for discriminating clocks by ES level, these should be added back
 * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
 */
 #include <linux/kernel.h>
@@ -315,7 +319,7 @@ DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
                   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-static const struct clk_ops dmic_fck_ops = {
+static const struct clk_ops dpll_hsd_ops = {
        .enable         = &omap2_dflt_clk_enable,
        .disable        = &omap2_dflt_clk_disable,
        .is_enabled     = &omap2_dflt_clk_is_enabled,
@@ -325,6 +329,12 @@ static const struct clk_ops dmic_fck_ops = {
        .init           = &omap2_init_clk_clkdm,
 };
+static const struct clk_ops func_dmic_abe_gfclk_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
 static const char *dpll_core_m3x2_ck_parents[] = {
        "dpll_core_x2_ck",
 };
@@ -340,7 +350,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
                         OMAP4430_CM_DIV_M3_DPLL_CORE,
                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_core_m3x2_ck_parents, dmic_fck_ops);
+                         dpll_core_m3x2_ck_parents, dpll_hsd_ops);
 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
@@ -547,7 +557,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
                         OMAP4430_CM_DIV_M3_DPLL_PER,
                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_per_m3x2_ck_parents, dmic_fck_ops);
+                         dpll_per_m3x2_ck_parents, dpll_hsd_ops);
 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
                          0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
@@ -595,15 +605,26 @@ static const char *dpll_usb_ck_parents[] = {
 static struct clk dpll_usb_ck;
+static const struct clk_ops dpll_usb_ck_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .get_parent     = &omap2_init_dpll_parent,
+        .init           = &omap2_init_clk_clkdm,
+};
 static struct clk_hw_omap dpll_usb_ck_hw = {
        .hw = {
                .clk = &dpll_usb_ck,
        },
        .dpll_data      = &dpll_usb_dd,
+        .clkdm_name     = "l3_init_clkdm",
        .ops            = &clkhwops_omap3_dpll,
 };
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
 static const char *dpll_usb_clkdcoldo_ck_parents[] = {
        "dpll_usb_ck",
@@ -749,10 +770,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
                OMAP4430_CM_L4SEC_AES2_CLKCTRL,
                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
-                OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
                OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
@@ -774,11 +791,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
                OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 static const char *dmic_sync_mux_ck_parents[] = {
        "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
 };
@@ -795,23 +807,13 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *dmic_fck_parents[] = {
+static const char *func_dmic_abe_gfclk_parents[] = {
        "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 };
-/* Merged func_dmic_abe_gfclk into dmic */
+DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-static struct clk dmic_fck;
+                    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
+                    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
-                         OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-                         OMAP4430_CLKSEL_SOURCE_MASK,
-                         OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         dmic_fck_parents, dmic_fck_ops);
-DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
-                OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
                OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -833,177 +835,57 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
-                OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
-                OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
                   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
                   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
-                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
                OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
 static const struct clksel sgx_clk_mux_sel[] = {
        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
        { .parent = NULL },
 };
-static const char *gpu_fck_parents[] = {
+static const char *sgx_clk_mux_parents[] = {
        "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
 };
-/* Merged sgx_clk_mux into gpu */
+DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
+                    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-                         OMAP4430_CM_GFX_GFX_CLKCTRL,
+                    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-                         OMAP4430_CLKSEL_SGX_FCLK_MASK,
-                         OMAP4430_CM_GFX_GFX_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         gpu_fck_parents, dmic_fck_ops);
-DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
-                OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
                   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
                   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
                   NULL);
-DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
-                OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
-                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
-                OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-static struct clk l3_instr_ick;
-static const char *l3_instr_ick_parent_names[] = {
-        "l3_div_ck",
-};
-static const struct clk_ops l3_instr_ick_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .init           = &omap2_init_clk_clkdm,
-};
-static struct clk_hw_omap l3_instr_ick_hw = {
-        .hw = {
-                .clk = &l3_instr_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
-static struct clk l3_main_3_ick;
-static struct clk_hw_omap l3_main_3_ick_hw = {
-        .hw = {
-                .clk = &l3_main_3_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
               OMAP4430_CM1_ABE_MCASP_CLKCTRL,
               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
@@ -1016,17 +898,13 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mcasp_fck_parents[] = {
+static const char *func_mcasp_abe_gfclk_parents[] = {
        "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 };
-/* Merged func_mcasp_abe_gfclk into mcasp */
+DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
+                    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-                         OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+                    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-                         OMAP4430_CLKSEL_SOURCE_MASK,
-                         OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mcasp_fck_parents, dmic_fck_ops);
 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
               OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
@@ -1040,17 +918,14 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mcbsp1_fck_parents[] = {
+static const char *func_mcbsp1_gfclk_parents[] = {
        "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 };
-/* Merged func_mcbsp1_gfclk into mcbsp1 */
+DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
+                    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-                         OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-                         OMAP4430_CLKSEL_SOURCE_MASK,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mcbsp1_fck_parents, dmic_fck_ops);
 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
               OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
@@ -1064,17 +939,14 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mcbsp2_fck_parents[] = {
+static const char *func_mcbsp2_gfclk_parents[] = {
        "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 };
-/* Merged func_mcbsp2_gfclk into mcbsp2 */
+DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
+                    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-                         OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-                         OMAP4430_CLKSEL_SOURCE_MASK,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mcbsp2_fck_parents, dmic_fck_ops);
 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
               OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
@@ -1088,17 +960,14 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mcbsp3_fck_parents[] = {
+static const char *func_mcbsp3_gfclk_parents[] = {
        "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 };
-/* Merged func_mcbsp3_gfclk into mcbsp3 */
+DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
+                    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-                         OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-                         OMAP4430_CLKSEL_SOURCE_MASK,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mcbsp3_fck_parents, dmic_fck_ops);
 static const char *mcbsp4_sync_mux_ck_parents[] = {
        "func_96m_fclk", "per_abe_nc_fclk",
@@ -1115,37 +984,14 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mcbsp4_fck_parents[] = {
+static const char *per_mcbsp4_gfclk_parents[] = {
        "mcbsp4_sync_mux_ck", "pad_clks_ck",
 };
-/* Merged per_mcbsp4_gfclk into mcbsp4 */
+DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
+                    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-                         OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-                         OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mcbsp4_fck_parents, dmic_fck_ops);
-DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
-                OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 static const struct clksel hsmmc1_fclk_sel[] = {
        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
@@ -1153,69 +999,22 @@ static const struct clksel hsmmc1_fclk_sel[] = {
        { .parent = NULL },
 };
-static const char *mmc1_fck_parents[] = {
+static const char *hsmmc1_fclk_parents[] = {
        "func_64m_fclk", "func_96m_fclk",
 };
-/* Merged hsmmc1_fclk into mmc1 */
+DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
+                    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mmc1_fck_parents, dmic_fck_ops);
-/* Merged hsmmc2_fclk into mmc2 */
-DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
-                         OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         mmc1_fck_parents, dmic_fck_ops);
-DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-static struct clk ocp_wp_noc_ick;
+DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
+                    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-static struct clk_hw_omap ocp_wp_noc_ick_hw = {
+                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-        .hw = {
-                .clk = &ocp_wp_noc_ick,
-        },
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-        .clkdm_name     = "l3_instr_clkdm",
-};
-DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
-DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
                OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
-                OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
 DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
                OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
@@ -1232,10 +1031,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
                OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
@@ -1249,10 +1044,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
                0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1271,52 +1062,35 @@ static const struct clksel dmt1_clk_mux_sel[] = {
        { .parent = NULL },
 };
-/* Merged dmt1_clk_mux into timer1 */
+DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
+                    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                    abe_dpll_bypass_clk_mux_ck_parents,
-                         OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
+                    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-/* Merged cm2_dm10_mux into timer10 */
+                    abe_dpll_bypass_clk_mux_ck_parents,
-DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-                         OMAP4430_CLKSEL_MASK,
+DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                    abe_dpll_bypass_clk_mux_ck_parents,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+                    func_dmic_abe_gfclk_ops);
-/* Merged cm2_dm11_mux into timer11 */
+DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                    abe_dpll_bypass_clk_mux_ck_parents,
-                         OMAP4430_CLKSEL_MASK,
+                    func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+                    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                    abe_dpll_bypass_clk_mux_ck_parents,
-/* Merged cm2_dm2_mux into timer2 */
+                    func_dmic_abe_gfclk_ops);
-DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CLKSEL_MASK,
+                    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                    abe_dpll_bypass_clk_mux_ck_parents,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                    func_dmic_abe_gfclk_ops);
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
-/* Merged cm2_dm3_mux into timer3 */
-DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-                         OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
-/* Merged cm2_dm4_mux into timer4 */
-DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-                         OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
 static const struct clksel timer5_sync_mux_sel[] = {
        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
@@ -1324,61 +1098,30 @@ static const struct clksel timer5_sync_mux_sel[] = {
        { .parent = NULL },
 };
-static const char *timer5_fck_parents[] = {
+static const char *timer5_sync_mux_parents[] = {
        "syc_clk_div_ck", "sys_32k_ck",
 };
-/* Merged timer5_sync_mux into timer5 */
+DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
+                    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-                         OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         timer5_fck_parents, dmic_fck_ops);
-/* Merged timer6_sync_mux into timer6 */
-DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
-                         OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         timer5_fck_parents, dmic_fck_ops);
-/* Merged timer7_sync_mux into timer7 */
-DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
-                         OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         timer5_fck_parents, dmic_fck_ops);
-/* Merged timer8_sync_mux into timer8 */
-DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
-                         OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         timer5_fck_parents, dmic_fck_ops);
-/* Merged cm2_dm9_mux into timer9 */
-DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
-                         OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-                         OMAP4430_CLKSEL_MASK,
-                         OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
-                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
-DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L4PER_UART1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
+DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
+                    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                    abe_dpll_bypass_clk_mux_ck_parents,
+                    func_dmic_abe_gfclk_ops);
 static struct clk usb_host_fs_fck;
@@ -1512,18 +1255,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
                0x0, NULL);
-DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
-                0x0, NULL);
-DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 /* Remaining optional clocks */
 static const char *pmd_stm_clock_mux_ck_parents[] = {
        "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
@@ -1774,106 +1505,61 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
-        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
-        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
-        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
+        CLK(NULL,       "func_dmic_abe_gfclk",                  &func_dmic_abe_gfclk,   CK_443X),
-        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
        CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
-        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
-        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
-        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
-        CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
-        CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
-        CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
-        CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
-        CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
-        CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
+        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux,   CK_443X),
-        CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
-        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
-        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
-        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
-        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
-        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
-        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
-        CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
-        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
-        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
-        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
-        CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
+        CLK(NULL,       "func_mcasp_abe_gfclk",                 &func_mcasp_abe_gfclk,  CK_443X),
        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
+        CLK(NULL,       "func_mcbsp1_gfclk",                    &func_mcbsp1_gfclk,     CK_443X),
        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
+        CLK(NULL,       "func_mcbsp2_gfclk",                    &func_mcbsp2_gfclk,     CK_443X),
        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
+        CLK(NULL,       "func_mcbsp3_gfclk",                    &func_mcbsp3_gfclk,     CK_443X),
        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
-        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
+        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
-        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
+        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
-        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
-        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
-        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
-        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
-        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
-        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
-        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
-        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
-        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
-        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
-        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
-        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
-        CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
+        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux,  CK_443X),
-        CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
+        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux,  CK_443X),
-        CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
+        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux,  CK_443X),
-        CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
+        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux,   CK_443X),
-        CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
+        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux,   CK_443X),
-        CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
+        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux,   CK_443X),
-        CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
+        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux,       CK_443X),
-        CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
+        CLK(NULL,       "timer6_sync_mux",                      &timer6_sync_mux,       CK_443X),
-        CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
+        CLK(NULL,       "timer7_sync_mux",                      &timer7_sync_mux,       CK_443X),
-        CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
+        CLK(NULL,       "timer8_sync_mux",                      &timer8_sync_mux,       CK_443X),
-        CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
+        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux,   CK_443X),
-        CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
-        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
-        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
-        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
@@ -1901,9 +1587,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
-        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
@@ -1980,15 +1663,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
-static const char *enable_init_clks[] = {
-        "emif1_fck",
-        "emif2_fck",
-        "gpmc_ick",
-        "l3_instr_ick",
-        "l3_main_3_ick",
-        "ocp_wp_noc_ick",
-};
 int __init omap4xxx_clk_init(void)
 {
        u32 cpu_clkflg;
@@ -2019,9 +1693,6 @@ int __init omap4xxx_clk_init(void)
        omap2_clk_disable_autoidle_all();
-        omap2_clk_enable_init_clocks(enable_init_clks,
-                                     ARRAY_SIZE(enable_init_clks));
        /*
         * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
         * state when turning the ABE clock domain. Workaround this by
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b40204837bd7..60ddd8612b4d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,17 @@ struct clockdomain;
                .ops = &_clkops_name,                           \
        };
+#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name,      \
+                                _clkops_name, _flags)           \
+        static struct clk _name = {                             \
+                .name = #_name,                                 \
+                .hw = &_name##_hw.hw,                           \
+                .parent_names = _parent_array_name,             \
+                .num_parents = ARRAY_SIZE(_parent_array_name),  \
+                .ops = &_clkops_name,                           \
+                .flags = _flags,                                \
+        };
 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name)           \
        static struct clk_hw_omap _name##_hw = {                \
                .hw = {                                         \
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 1ff646908627..b870f6a9e283 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -52,6 +52,6 @@ static int __init omap2xxx_clk_arch_init(void)
        return ret;
 }
-arch_initcall(omap2xxx_clk_arch_init);
+omap_arch_initcall(omap2xxx_clk_arch_init);
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 4eacab8f1176..0b02b4161d71 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -94,6 +94,6 @@ static int __init omap3xxx_clk_arch_init(void)
        return ret;
 }
-arch_initcall(omap3xxx_clk_arch_init);
+omap_arch_initcall(omap3xxx_clk_arch_init);
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 7faf82d4e85c..2da3b5ec010c 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -92,8 +92,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
        pwrdm_add_clkdm(pwrdm, clkdm);
-        spin_lock_init(&clkdm->lock);
        pr_debug("clockdomain: registered %s\n", clkdm->name);
        return 0;
@@ -122,7 +120,7 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
        return cd;
 }
-/*
+/**
 * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
 * @autodep: struct clkdm_autodep * to resolve
 *
@@ -154,88 +152,206 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
        autodep->clkdm.ptr = clkdm;
 }
-/*
+/**
- * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
+ * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
- * @clkdm: struct clockdomain *
+ * @clkdm: clockdomain that we are resolving dependencies for
+ * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
 *
- * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
+ * Iterates through @clkdm_deps, looking up the struct clockdomain named by
- * in hardware-supervised mode.  Meant to be called from clock framework
+ * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
- * when a clock inside clockdomain 'clkdm' is enabled.  No return value.
+ * No return value.
+ */
+static void _resolve_clkdm_deps(struct clockdomain *clkdm,
+                                struct clkdm_dep *clkdm_deps)
+{
+        struct clkdm_dep *cd;
+        for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
+                if (cd->clkdm)
+                        continue;
+                cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+                WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
+                     clkdm->name, cd->clkdm_name);
+        }
+}
+/**
+ * _clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 (lockless)
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
 *
- * XXX autodeps are deprecated and should be removed at the earliest
+ * When the clockdomain represented by @clkdm2 wakes up, wake up
- * opportunity
+ * @clkdm1. Implemented in hardware on the OMAP, this feature is
+ * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
+ * Returns -EINVAL if presented with invalid clockdomain pointers,
+ * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
+ * success.
 */
-void _clkdm_add_autodeps(struct clockdomain *clkdm)
+static int _clkdm_add_wkdep(struct clockdomain *clkdm1,
+                            struct clockdomain *clkdm2)
 {
-        struct clkdm_autodep *autodep;
+        struct clkdm_dep *cd;
+        int ret = 0;
-        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+        if (!clkdm1 || !clkdm2)
-                return;
+                return -EINVAL;
-        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
-                if (IS_ERR(autodep->clkdm.ptr))
+        if (IS_ERR(cd))
-                        continue;
+                ret = PTR_ERR(cd);
-                pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+        if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
-                         clkdm->name, autodep->clkdm.ptr->name);
+                ret = -EINVAL;
+        if (ret) {
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
+                return ret;
+        }
+        cd->wkdep_usecount++;
+        if (cd->wkdep_usecount == 1) {
+                pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
-                clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
+                ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
-                clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
        }
+        return ret;
 }
-/*
+/**
- * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
+ * _clkdm_del_wkdep - remove a wakeup dep from clkdm2 to clkdm1 (lockless)
- * @clkdm: struct clockdomain *
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
 *
- * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
+ * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
- * in hardware-supervised mode.  Meant to be called from clock framework
+ * wakes up.  Returns -EINVAL if presented with invalid clockdomain
- * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
+ * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
+ * 0 upon success.
+ */
+static int _clkdm_del_wkdep(struct clockdomain *clkdm1,
+                            struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+        int ret = 0;
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+        if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
+                ret = -EINVAL;
+        if (ret) {
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
+                return ret;
+        }
+        cd->wkdep_usecount--;
+        if (cd->wkdep_usecount == 0) {
+                pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+                         clkdm1->name, clkdm2->name);
+                ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
+        }
+        return ret;
+}
+/**
+ * _clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 (lockless)
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
 *
- * XXX autodeps are deprecated and should be removed at the earliest
+ * Prevent @clkdm1 from automatically going inactive (and then to
- * opportunity
+ * retention or off) if @clkdm2 is active.  Returns -EINVAL if
+ * presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep
+ * dependencies, -ENOENT if the specified dependency cannot be set in
+ * hardware, or 0 upon success.
 */
-void _clkdm_del_autodeps(struct clockdomain *clkdm)
+static int _clkdm_add_sleepdep(struct clockdomain *clkdm1,
+                               struct clockdomain *clkdm2)
 {
-        struct clkdm_autodep *autodep;
+        struct clkdm_dep *cd;
+        int ret = 0;
-        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+        if (!clkdm1 || !clkdm2)
-                return;
+                return -EINVAL;
-        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
-                if (IS_ERR(autodep->clkdm.ptr))
+        if (IS_ERR(cd))
-                        continue;
+                ret = PTR_ERR(cd);
-                pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+        if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
-                         clkdm->name, autodep->clkdm.ptr->name);
+                ret = -EINVAL;
-                clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
+        if (ret) {
-                clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                         clkdm1->name, clkdm2->name);
+                return ret;
+        }
+        cd->sleepdep_usecount++;
+        if (cd->sleepdep_usecount == 1) {
+                pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+                         clkdm1->name, clkdm2->name);
+                ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
        }
+        return ret;
 }
 /**
- * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
+ * _clkdm_del_sleepdep - remove a sleep dep from clkdm2 to clkdm1 (lockless)
- * @clkdm: clockdomain that we are resolving dependencies for
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
- * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
+ * @clkdm2: when this struct clockdomain * is active (source)
 *
- * Iterates through @clkdm_deps, looking up the struct clockdomain named by
+ * Allow @clkdm1 to automatically go inactive (and then to retention or
- * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
+ * off), independent of the activity state of @clkdm2.  Returns -EINVAL
- * No return value.
+ * if presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep dependencies,
+ * -ENOENT if the specified dependency cannot be cleared in hardware, or
+ * 0 upon success.
 */
-static void _resolve_clkdm_deps(struct clockdomain *clkdm,
+static int _clkdm_del_sleepdep(struct clockdomain *clkdm1,
-                                struct clkdm_dep *clkdm_deps)
+                               struct clockdomain *clkdm2)
 {
        struct clkdm_dep *cd;
+        int ret = 0;
-        for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
+        if (!clkdm1 || !clkdm2)
-                if (cd->clkdm)
+                return -EINVAL;
-                        continue;
-                cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-                WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
-                     clkdm->name, cd->clkdm_name);
+        if (IS_ERR(cd))
+                ret = PTR_ERR(cd);
+        if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
+                ret = -EINVAL;
+        if (ret) {
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                         clkdm1->name, clkdm2->name);
+                return ret;
        }
+        cd->sleepdep_usecount--;
+        if (cd->sleepdep_usecount == 0) {
+                pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+                         clkdm1->name, clkdm2->name);
+                ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
+        }
+        return ret;
 }
 /* Public functions */
@@ -456,30 +572,18 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
 int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
        struct clkdm_dep *cd;
-        int ret = 0;
+        int ret;
        if (!clkdm1 || !clkdm2)
                return -EINVAL;
        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
        if (IS_ERR(cd))
-                ret = PTR_ERR(cd);
+                return PTR_ERR(cd);
-        if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
+        pwrdm_lock(cd->clkdm->pwrdm.ptr);
-                ret = -EINVAL;
+        ret = _clkdm_add_wkdep(clkdm1, clkdm2);
+        pwrdm_unlock(cd->clkdm->pwrdm.ptr);
-        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
-                         clkdm1->name, clkdm2->name);
-                return ret;
-        }
-        if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
-                pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
-                         clkdm1->name, clkdm2->name);
-                ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
-        }
        return ret;
 }
@@ -497,30 +601,18 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
        struct clkdm_dep *cd;
-        int ret = 0;
+        int ret;
        if (!clkdm1 || !clkdm2)
                return -EINVAL;
        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
        if (IS_ERR(cd))
-                ret = PTR_ERR(cd);
+                return PTR_ERR(cd);
-        if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
+        pwrdm_lock(cd->clkdm->pwrdm.ptr);
-                ret = -EINVAL;
+        ret = _clkdm_del_wkdep(clkdm1, clkdm2);
+        pwrdm_unlock(cd->clkdm->pwrdm.ptr);
-        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
-                         clkdm1->name, clkdm2->name);
-                return ret;
-        }
-        if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
-                pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
-                         clkdm1->name, clkdm2->name);
-                ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
-        }
        return ret;
 }
@@ -560,7 +652,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                return ret;
        }
-        /* XXX It's faster to return the atomic wkdep_usecount */
+        /* XXX It's faster to return the wkdep_usecount */
        return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
 }
@@ -600,30 +692,18 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
        struct clkdm_dep *cd;
-        int ret = 0;
+        int ret;
        if (!clkdm1 || !clkdm2)
                return -EINVAL;
-        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
        if (IS_ERR(cd))
-                ret = PTR_ERR(cd);
+                return PTR_ERR(cd);
-        if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
+        pwrdm_lock(cd->clkdm->pwrdm.ptr);
-                ret = -EINVAL;
+        ret = _clkdm_add_sleepdep(clkdm1, clkdm2);
+        pwrdm_unlock(cd->clkdm->pwrdm.ptr);
-        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
-                         clkdm1->name, clkdm2->name);
-                return ret;
-        }
-        if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
-                pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
-                         clkdm1->name, clkdm2->name);
-                ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
-        }
        return ret;
 }
@@ -643,30 +723,18 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 {
        struct clkdm_dep *cd;
-        int ret = 0;
+        int ret;
        if (!clkdm1 || !clkdm2)
                return -EINVAL;
-        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
        if (IS_ERR(cd))
-                ret = PTR_ERR(cd);
+                return PTR_ERR(cd);
-        if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
+        pwrdm_lock(cd->clkdm->pwrdm.ptr);
-                ret = -EINVAL;
+        ret = _clkdm_del_sleepdep(clkdm1, clkdm2);
+        pwrdm_unlock(cd->clkdm->pwrdm.ptr);
-        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
-                         clkdm1->name, clkdm2->name);
-                return ret;
-        }
-        if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
-                pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
-                         clkdm1->name, clkdm2->name);
-                ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
-        }
        return ret;
 }
@@ -708,7 +776,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                return ret;
        }
-        /* XXX It's faster to return the atomic sleepdep_usecount */
+        /* XXX It's faster to return the sleepdep_usecount */
        return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
 }
@@ -734,18 +802,17 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 }
 /**
- * clkdm_sleep - force clockdomain sleep transition
+ * clkdm_sleep_nolock - force clockdomain sleep transition (lockless)
 * @clkdm: struct clockdomain *
 *
 * Instruct the CM to force a sleep transition on the specified
- * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if
+ * clockdomain @clkdm.  Only for use by the powerdomain code.  Returns
- * clockdomain does not support software-initiated sleep; 0 upon
+ * -EINVAL if @clkdm is NULL or if clockdomain does not support
- * success.
+ * software-initiated sleep; 0 upon success.
 */
-int clkdm_sleep(struct clockdomain *clkdm)
+int clkdm_sleep_nolock(struct clockdomain *clkdm)
 {
        int ret;
-        unsigned long flags;
        if (!clkdm)
                return -EINVAL;
@@ -761,26 +828,45 @@ int clkdm_sleep(struct clockdomain *clkdm)
        pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
-        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
        ret = arch_clkdm->clkdm_sleep(clkdm);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+        ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
        return ret;
 }
 /**
- * clkdm_wakeup - force clockdomain wakeup transition
+ * clkdm_sleep - force clockdomain sleep transition
 * @clkdm: struct clockdomain *
 *
- * Instruct the CM to force a wakeup transition on the specified
+ * Instruct the CM to force a sleep transition on the specified
- * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if the
+ * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if
- * clockdomain does not support software-controlled wakeup; 0 upon
+ * clockdomain does not support software-initiated sleep; 0 upon
 * success.
 */
-int clkdm_wakeup(struct clockdomain *clkdm)
+int clkdm_sleep(struct clockdomain *clkdm)
+{
+        int ret;
+        pwrdm_lock(clkdm->pwrdm.ptr);
+        ret = clkdm_sleep_nolock(clkdm);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
+        return ret;
+}
+/**
+ * clkdm_wakeup_nolock - force clockdomain wakeup transition (lockless)
+ * @clkdm: struct clockdomain *
+ *
+ * Instruct the CM to force a wakeup transition on the specified
+ * clockdomain @clkdm.  Only for use by the powerdomain code.  Returns
+ * -EINVAL if @clkdm is NULL or if the clockdomain does not support
+ * software-controlled wakeup; 0 upon success.
+ */
+int clkdm_wakeup_nolock(struct clockdomain *clkdm)
 {
        int ret;
-        unsigned long flags;
        if (!clkdm)
                return -EINVAL;
@@ -796,28 +882,46 @@ int clkdm_wakeup(struct clockdomain *clkdm)
        pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
-        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
        ret = arch_clkdm->clkdm_wakeup(clkdm);
-        ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
+        ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
        return ret;
 }
 /**
- * clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ * clkdm_wakeup - force clockdomain wakeup transition
 * @clkdm: struct clockdomain *
 *
- * Allow the hardware to automatically switch the clockdomain @clkdm into
+ * Instruct the CM to force a wakeup transition on the specified
- * active or idle states, as needed by downstream clocks.  If the
+ * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if the
+ * clockdomain does not support software-controlled wakeup; 0 upon
+ * success.
+ */
+int clkdm_wakeup(struct clockdomain *clkdm)
+{
+        int ret;
+        pwrdm_lock(clkdm->pwrdm.ptr);
+        ret = clkdm_wakeup_nolock(clkdm);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
+        return ret;
+}
+/**
+ * clkdm_allow_idle_nolock - enable hwsup idle transitions for clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Allow the hardware to automatically switch the clockdomain @clkdm
+ * into active or idle states, as needed by downstream clocks.  If the
 * clockdomain has any downstream clocks enabled in the clock
 * framework, wkdep/sleepdep autodependencies are added; this is so
- * device drivers can read and write to the device.  No return value.
+ * device drivers can read and write to the device.  Only for use by
+ * the powerdomain code.  No return value.
 */
-void clkdm_allow_idle(struct clockdomain *clkdm)
+void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
 {
-        unsigned long flags;
        if (!clkdm)
                return;
@@ -833,11 +937,26 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
        pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
                 clkdm->name);
-        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
        arch_clkdm->clkdm_allow_idle(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+}
+/**
+ * clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Allow the hardware to automatically switch the clockdomain @clkdm into
+ * active or idle states, as needed by downstream clocks.  If the
+ * clockdomain has any downstream clocks enabled in the clock
+ * framework, wkdep/sleepdep autodependencies are added; this is so
+ * device drivers can read and write to the device.  No return value.
+ */
+void clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        pwrdm_lock(clkdm->pwrdm.ptr);
+        clkdm_allow_idle_nolock(clkdm);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
 }
 /**
@@ -847,12 +966,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
 * Prevent the hardware from automatically switching the clockdomain
 * @clkdm into inactive or idle states.  If the clockdomain has
 * downstream clocks enabled in the clock framework, wkdep/sleepdep
- * autodependencies are removed.  No return value.
+ * autodependencies are removed.  Only for use by the powerdomain
+ * code.  No return value.
 */
-void clkdm_deny_idle(struct clockdomain *clkdm)
+void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
 {
-        unsigned long flags;
        if (!clkdm)
                return;
@@ -868,11 +986,25 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
        pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
                 clkdm->name);
-        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
        arch_clkdm->clkdm_deny_idle(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+}
+/**
+ * clkdm_deny_idle - disable hwsup idle transitions for clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Prevent the hardware from automatically switching the clockdomain
+ * @clkdm into inactive or idle states.  If the clockdomain has
+ * downstream clocks enabled in the clock framework, wkdep/sleepdep
+ * autodependencies are removed.  No return value.
+ */
+void clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        pwrdm_lock(clkdm->pwrdm.ptr);
+        clkdm_deny_idle_nolock(clkdm);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
 }
 /**
@@ -889,14 +1021,11 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
 bool clkdm_in_hwsup(struct clockdomain *clkdm)
 {
        bool ret;
-        unsigned long flags;
        if (!clkdm)
                return false;
-        spin_lock_irqsave(&clkdm->lock, flags);
        ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
-        spin_unlock_irqrestore(&clkdm->lock, flags);
        return ret;
 }
@@ -918,30 +1047,91 @@ bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
        return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
 }
+/* Public autodep handling functions (deprecated) */
+/**
+ * clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
+ * @clkdm: struct clockdomain *
+ *
+ * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
+ * in hardware-supervised mode.  Meant to be called from clock framework
+ * when a clock inside clockdomain 'clkdm' is enabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
+ */
+void clkdm_add_autodeps(struct clockdomain *clkdm)
+{
+        struct clkdm_autodep *autodep;
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+                return;
+        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+                if (IS_ERR(autodep->clkdm.ptr))
+                        continue;
+                pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+                         clkdm->name, autodep->clkdm.ptr->name);
+                _clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
+                _clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
+        }
+}
+/**
+ * clkdm_del_autodeps - remove auto sleepdeps/wkdeps from clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
+ * in hardware-supervised mode.  Meant to be called from clock framework
+ * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
+ */
+void clkdm_del_autodeps(struct clockdomain *clkdm)
+{
+        struct clkdm_autodep *autodep;
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+                return;
+        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+                if (IS_ERR(autodep->clkdm.ptr))
+                        continue;
+                pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+                         clkdm->name, autodep->clkdm.ptr->name);
+                _clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
+                _clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
+        }
+}
 /* Clockdomain-to-clock/hwmod framework interface code */
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 {
-        unsigned long flags;
        if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
                return -EINVAL;
-        spin_lock_irqsave(&clkdm->lock, flags);
+        pwrdm_lock(clkdm->pwrdm.ptr);
        /*
         * For arch's with no autodeps, clkcm_clk_enable
         * should be called for every clock instance or hwmod that is
         * enabled, so the clkdm can be force woken up.
         */
-        if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) {
+        clkdm->usecount++;
-                spin_unlock_irqrestore(&clkdm->lock, flags);
+        if (clkdm->usecount > 1 && autodeps) {
+                pwrdm_unlock(clkdm->pwrdm.ptr);
                return 0;
        }
        arch_clkdm->clkdm_clk_enable(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
        pr_debug("clockdomain: %s: enabled\n", clkdm->name);
@@ -990,36 +1180,34 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-        unsigned long flags;
        if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
-        spin_lock_irqsave(&clkdm->lock, flags);
+        pwrdm_lock(clkdm->pwrdm.ptr);
        /* corner case: disabling unused clocks */
-        if ((__clk_get_enable_count(clk) == 0) &&
+        if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
-            (atomic_read(&clkdm->usecount) == 0))
                goto ccd_exit;
-        if (atomic_read(&clkdm->usecount) == 0) {
+        if (clkdm->usecount == 0) {
-                spin_unlock_irqrestore(&clkdm->lock, flags);
+                pwrdm_unlock(clkdm->pwrdm.ptr);
                WARN_ON(1); /* underflow */
                return -ERANGE;
        }
-        if (atomic_dec_return(&clkdm->usecount) > 0) {
+        clkdm->usecount--;
-                spin_unlock_irqrestore(&clkdm->lock, flags);
+        if (clkdm->usecount > 0) {
+                pwrdm_unlock(clkdm->pwrdm.ptr);
                return 0;
        }
        arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
 ccd_exit:
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
        return 0;
 }
@@ -1072,8 +1260,6 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 */
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 {
-        unsigned long flags;
        /* The clkdm attribute does not exist yet prior OMAP4 */
        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                return 0;
@@ -1086,22 +1272,23 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
        if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
-        spin_lock_irqsave(&clkdm->lock, flags);
+        pwrdm_lock(clkdm->pwrdm.ptr);
-        if (atomic_read(&clkdm->usecount) == 0) {
+        if (clkdm->usecount == 0) {
-                spin_unlock_irqrestore(&clkdm->lock, flags);
+                pwrdm_unlock(clkdm->pwrdm.ptr);
                WARN_ON(1); /* underflow */
                return -ERANGE;
        }
-        if (atomic_dec_return(&clkdm->usecount) > 0) {
+        clkdm->usecount--;
-                spin_unlock_irqrestore(&clkdm->lock, flags);
+        if (clkdm->usecount > 0) {
+                pwrdm_unlock(clkdm->pwrdm.ptr);
                return 0;
        }
        arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
+        pwrdm_unlock(clkdm->pwrdm.ptr);
        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index bc42446e23ab..2da37656a693 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -15,7 +15,6 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
 #include <linux/init.h>
-#include <linux/spinlock.h>
 #include "powerdomain.h"
 #include "clock.h"
@@ -92,8 +91,8 @@ struct clkdm_autodep {
 struct clkdm_dep {
        const char *clkdm_name;
        struct clockdomain *clkdm;
-        atomic_t wkdep_usecount;
+        s16 wkdep_usecount;
-        atomic_t sleepdep_usecount;
+        s16 sleepdep_usecount;
 };
 /* Possible flags for struct clockdomain._flags */
@@ -137,9 +136,8 @@ struct clockdomain {
        const u16 clkdm_offs;
        struct clkdm_dep *wkdep_srcs;
        struct clkdm_dep *sleepdep_srcs;
-        atomic_t usecount;
+        int usecount;
        struct list_head node;
-        spinlock_t lock;
 };
 /**
@@ -196,12 +194,16 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
 int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
 int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
+void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
 bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
+int clkdm_wakeup_nolock(struct clockdomain *clkdm);
 int clkdm_wakeup(struct clockdomain *clkdm);
+int clkdm_sleep_nolock(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
 int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
@@ -214,8 +216,9 @@ extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
-extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
-extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
+extern void clkdm_add_autodeps(struct clockdomain *clkdm);
+extern void clkdm_del_autodeps(struct clockdomain *clkdm);
 extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index db650690e9d0..6774a53a3874 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -273,9 +273,6 @@ int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 {
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                       clkdm->clktrctrl_mask);
 }
@@ -284,9 +281,6 @@ static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
 {
        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                        clkdm->clktrctrl_mask);
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_del_autodeps(clkdm);
 }
 static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
@@ -298,18 +292,8 @@ static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                              clkdm->clktrctrl_mask);
+        if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-        if (hwsup) {
+                omap2xxx_clkdm_wakeup(clkdm);
-                /* Disable HW transitions when we are changing deps */
-                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-                _clkdm_add_autodeps(clkdm);
-                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                        omap2xxx_clkdm_wakeup(clkdm);
-        }
        return 0;
 }
@@ -324,17 +308,8 @@ static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                              clkdm->clktrctrl_mask);
-        if (hwsup) {
+        if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                /* Disable HW transitions when we are changing deps */
+                omap2xxx_clkdm_sleep(clkdm);
-                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-                _clkdm_del_autodeps(clkdm);
-                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                        omap2xxx_clkdm_sleep(clkdm);
-        }
        return 0;
 }
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 058ce3c0873e..325a51576576 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
 {
        int i = 0;
-        if (!clkctrl_offs)
-                return 0;
        omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
                          MAX_MODULE_READY_TIME, i);
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 5fa0b62e1a79..64f4bafe7bd9 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,16 +17,11 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
 #include "common.h"
 #include "cm.h"
 #include "cm-regbits-33xx.h"
-#include "cm33xx.h"
+#include "iomap.h"
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
@@ -381,6 +376,7 @@
 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+#ifndef __ASSEMBLER__
 extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@@ -417,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
 }
 #endif
+#endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index c2086f2e86b6..9061c307d915 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -186,7 +186,7 @@ static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
                        continue; /* only happens if data is erroneous */
                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->sleepdep_usecount, 0);
+                cd->sleepdep_usecount = 0;
        }
        omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
                                    OMAP3430_CM_SLEEPDEP);
@@ -209,8 +209,8 @@ static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
 static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 {
-        if (atomic_read(&clkdm->usecount) > 0)
+        if (clkdm->usecount > 0)
-                _clkdm_add_autodeps(clkdm);
+                clkdm_add_autodeps(clkdm);
        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                       clkdm->clktrctrl_mask);
@@ -221,8 +221,8 @@ static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                        clkdm->clktrctrl_mask);
-        if (atomic_read(&clkdm->usecount) > 0)
+        if (clkdm->usecount > 0)
-                _clkdm_del_autodeps(clkdm);
+                clkdm_del_autodeps(clkdm);
 }
 static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
@@ -250,7 +250,7 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
                /* Disable HW transitions when we are changing deps */
                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                                clkdm->clktrctrl_mask);
-                _clkdm_add_autodeps(clkdm);
+                clkdm_add_autodeps(clkdm);
                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                               clkdm->clktrctrl_mask);
        } else {
@@ -287,7 +287,7 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
                /* Disable HW transitions when we are changing deps */
                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                                clkdm->clktrctrl_mask);
-                _clkdm_del_autodeps(clkdm);
+                clkdm_del_autodeps(clkdm);
                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                               clkdm->clktrctrl_mask);
        } else {
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 7f9a464f01e9..f0290f5566fe 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -393,7 +393,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
                        continue; /* only happens if data is erroneous */
                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
+                cd->wkdep_usecount = 0;
        }
        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 948bcaa82eb6..0a6b9c7a63da 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -79,13 +79,13 @@ static inline int omap_mux_late_init(void)
 extern void omap2_init_common_infrastructure(void);
-extern struct sys_timer omap2_timer;
+extern void omap2_sync32k_timer_init(void);
-extern struct sys_timer omap3_timer;
+extern void omap3_sync32k_timer_init(void);
-extern struct sys_timer omap3_secure_timer;
+extern void omap3_secure_sync32k_timer_init(void);
-extern struct sys_timer omap3_gp_timer;
+extern void omap3_gp_gptimer_timer_init(void);
-extern struct sys_timer omap3_am33xx_timer;
+extern void omap3_am33xx_gptimer_timer_init(void);
-extern struct sys_timer omap4_timer;
+extern void omap4_local_timer_init(void);
-extern struct sys_timer omap5_timer;
+extern void omap5_realtime_timer_init(void);
 void omap2420_init_early(void);
 void omap2430_init_early(void);
@@ -119,6 +119,14 @@ static inline void omap2xxx_restart(char mode, const char *cmd)
 }
 #endif
+#ifdef CONFIG_SOC_AM33XX
+void am33xx_restart(char mode, const char *cmd);
+#else
+static inline void am33xx_restart(char mode, const char *cmd)
+{
+}
+#endif
 #ifdef CONFIG_ARCH_OMAP3
 void omap3xxx_restart(char mode, const char *cmd);
 #else
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 22590dbe8f14..80392fca86c6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,40 +36,66 @@
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
-        u32 mpu_state;
+        u8 mpu_state;
-        u32 core_state;
+        u8 core_state;
+        u8 per_min_state;
+        u8 flags;
 };
 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
+/*
+ * Possible flag bits for struct omap3_idle_statedata.flags:
+ *
+ * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
+ *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
+ *    mode, so wakeup latency is greatly reduced, at the cost of additional
+ *    energy consumption.  This also prevents the CORE clockdomain from
+ *    entering idle.
+ */
+#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE           BIT(0)
+/*
+ * Prevent PER OFF if CORE is not in RETention or OFF as this would
+ * disable PER wakeups completely.
+ */
 static struct omap3_idle_statedata omap3_idle_data[] = {
        {
                .mpu_state = PWRDM_POWER_ON,
                .core_state = PWRDM_POWER_ON,
+                /* In C1 do not allow PER state lower than CORE state */
+                .per_min_state = PWRDM_POWER_ON,
+                .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
        },
        {
                .mpu_state = PWRDM_POWER_ON,
                .core_state = PWRDM_POWER_ON,
+                .per_min_state = PWRDM_POWER_RET,
        },
        {
                .mpu_state = PWRDM_POWER_RET,
                .core_state = PWRDM_POWER_ON,
+                .per_min_state = PWRDM_POWER_RET,
        },
        {
                .mpu_state = PWRDM_POWER_OFF,
                .core_state = PWRDM_POWER_ON,
+                .per_min_state = PWRDM_POWER_RET,
        },
        {
                .mpu_state = PWRDM_POWER_RET,
                .core_state = PWRDM_POWER_RET,
+                .per_min_state = PWRDM_POWER_OFF,
        },
        {
                .mpu_state = PWRDM_POWER_OFF,
                .core_state = PWRDM_POWER_RET,
+                .per_min_state = PWRDM_POWER_OFF,
        },
        {
                .mpu_state = PWRDM_POWER_OFF,
                .core_state = PWRDM_POWER_OFF,
+                .per_min_state = PWRDM_POWER_OFF,
        },
 };
@@ -80,27 +106,25 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
                                int index)
 {
        struct omap3_idle_statedata *cx = &omap3_idle_data[index];
-        u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
        local_fiq_disable();
-        pwrdm_set_next_pwrst(mpu_pd, mpu_state);
-        pwrdm_set_next_pwrst(core_pd, core_state);
        if (omap_irq_pending() || need_resched())
                goto return_sleep_time;
        /* Deny idle for C1 */
-        if (index == 0) {
+        if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
                clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
-                clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
+        } else {
+                pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
+                pwrdm_set_next_pwrst(core_pd, cx->core_state);
        }
        /*
         * Call idle CPU PM enter notifier chain so that
         * VFP context is saved.
         */
-        if (mpu_state == PWRDM_POWER_OFF)
+        if (cx->mpu_state == PWRDM_POWER_OFF)
                cpu_pm_enter();
        /* Execute ARM wfi */
@@ -110,17 +134,15 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
         * Call idle CPU PM enter notifier chain to restore
         * VFP context.
         */
-        if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+        if (cx->mpu_state == PWRDM_POWER_OFF &&
+            pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
                cpu_pm_exit();
        /* Re-allow idle for C1 */
-        if (index == 0) {
+        if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
                clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
-                clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
-        }
 return_sleep_time:
        local_fiq_enable();
        return index;
@@ -185,7 +207,7 @@ static int next_valid_state(struct cpuidle_device *dev,
         * Start search from the next (lower) state.
         */
        for (idx = index - 1; idx >= 0; idx--) {
-                cx =  &omap3_idle_data[idx];
+                cx = &omap3_idle_data[idx];
                if ((cx->mpu_state >= mpu_deepest_state) &&
                    (cx->core_state >= core_deepest_state)) {
                        next_index = idx;
@@ -209,10 +231,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                               struct cpuidle_driver *drv,
                               int index)
 {
-        int new_state_idx;
+        int new_state_idx, ret;
-        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
+        u8 per_next_state, per_saved_state;
        struct omap3_idle_statedata *cx;
-        int ret;
        /*
         * Use only C1 if CAM is active.
@@ -233,25 +254,13 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
        /* Program PER state */
        cx = &omap3_idle_data[new_state_idx];
-        core_next_state = cx->core_state;
-        per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
-        if (new_state_idx == 0) {
-                /* In C1 do not allow PER state lower than CORE state */
-                if (per_next_state < core_next_state)
-                        per_next_state = core_next_state;
-        } else {
-                /*
-                 * Prevent PER OFF if CORE is not in RETention or OFF as this
-                 * would disable PER wakeups completely.
-                 */
-                if ((per_next_state == PWRDM_POWER_OFF) &&
-                    (core_next_state > PWRDM_POWER_RET))
-                        per_next_state = PWRDM_POWER_RET;
-        }
-        /* Are we changing PER target state? */
+        per_next_state = pwrdm_read_next_pwrst(per_pd);
-        if (per_next_state != per_saved_state)
+        per_saved_state = per_next_state;
+        if (per_next_state < cx->per_min_state) {
+                per_next_state = cx->per_min_state;
                pwrdm_set_next_pwrst(per_pd, per_next_state);
+        }
        ret = omap3_enter_idle(dev, drv, new_state_idx);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 626f3ea3142f..1ec7f0597710 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,6 +20,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
 #include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/usb/omap_control_usb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -61,14 +62,13 @@ static int __init omap3_l3_init(void)
        if (!oh)
                pr_err("could not look up %s\n", oh_name);
-        pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+        pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0);
-                                                           NULL, 0, 0);
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap3_l3_init);
+omap_postcore_initcall(omap3_l3_init);
 static int __init omap4_l3_init(void)
 {
@@ -96,14 +96,13 @@ static int __init omap4_l3_init(void)
                        pr_err("could not look up %s\n", oh_name);
        }
-        pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
+        pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0);
-                                                     0, NULL, 0, 0);
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap4_l3_init);
+omap_postcore_initcall(omap4_l3_init);
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -254,6 +253,49 @@ static inline void omap_init_camera(void)
 #endif
 }
+#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
+static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
+        .type = 1,
+};
+struct resource omap4_control_usb_res[] = {
+        {
+                .name   = "control_dev_conf",
+                .start  = 0x4a002300,
+                .end    = 0x4a002303,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "otghs_control",
+                .start  = 0x4a00233c,
+                .end    = 0x4a00233f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device omap4_control_usb = {
+        .name = "omap-control-usb",
+        .id = -1,
+        .dev = {
+                .platform_data = &omap4_control_usb_pdata,
+        },
+        .num_resources = 2,
+        .resource = omap4_control_usb_res,
+};
+static inline void __init omap_init_control_usb(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+        if (platform_device_register(&omap4_control_usb))
+                pr_err("Error registering omap_control_usb device\n");
+}
+#else
+static inline void omap_init_control_usb(void) { }
+#endif /* CONFIG_OMAP_CONTROL_USB */
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                        *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
@@ -273,7 +315,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
        keypad_data = sdp4430_keypad_data;
        pdev = omap_device_build(name, id, oh, keypad_data,
-                        sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
+                                 sizeof(struct omap4_keypad_platform_data));
        if (IS_ERR(pdev)) {
                WARN(1, "Can't build omap_device for %s:%s.\n",
@@ -297,7 +339,7 @@ static inline void __init omap_init_mbox(void)
                return;
        }
-        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
                                                __func__, PTR_ERR(pdev));
 }
@@ -337,7 +379,7 @@ static void __init omap_init_mcpdm(void)
                return;
        }
-        pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
 }
 #else
@@ -358,7 +400,7 @@ static void __init omap_init_dmic(void)
                return;
        }
-        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
 }
 #else
@@ -384,8 +426,7 @@ static void __init omap_init_hdmi_audio(void)
                return;
        }
-        pdev = omap_device_build("omap-hdmi-audio-dai",
+        pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
-                -1, oh, NULL, 0, NULL, 0, 0);
        WARN(IS_ERR(pdev),
             "Can't build omap_device for omap-hdmi-audio-dai.\n");
@@ -429,8 +470,7 @@ static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
        }
        spi_num++;
-        pdev = omap_device_build(name, spi_num, oh, pdata,
+        pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata));
-                                sizeof(*pdata), NULL, 0, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
                                name, oh->name);
        kfree(pdata);
@@ -460,7 +500,7 @@ static void omap_init_rng(void)
        if (!oh)
                return;
-        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
@@ -689,8 +729,7 @@ static void __init omap_init_ocp2scp(void)
        pdata->dev_cnt  = dev_cnt;
-        pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL,
+        pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
-                                                                0, false);
        if (IS_ERR(pdev)) {
                pr_err("Could not build omap_device for %s %s\n",
                                                name, oh_name);
@@ -721,6 +760,7 @@ static int __init omap2_init_devices(void)
        omap_init_mbox();
        /* If dtb is there, the devices will be created dynamically */
        if (!of_have_populated_dt()) {
+                omap_init_control_usb();
                omap_init_dmic();
                omap_init_mcpdm();
                omap_init_mcspi();
@@ -734,4 +774,4 @@ static int __init omap2_init_devices(void)
        return 0;
 }
-arch_initcall(omap2_init_devices);
+omap_arch_initcall(omap2_init_devices);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index cc75aaf6e764..ff37be1f6f93 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -226,7 +226,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name,
                dev_set_name(&pdev->dev, "%s", pdev->name);
        ohs[0] = oh;
-        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
+        od = omap_device_alloc(pdev, ohs, 1);
        if (IS_ERR(od)) {
                pr_err("Could not alloc omap_device for %s\n", pdev_name);
                r = -ENOMEM;
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 612b98249873..dab9fc014b97 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -27,7 +27,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/dma-mapping.h>
 #include <linux/omap-dma.h>
 #include "soc.h"
@@ -248,7 +248,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        p->errata               = configure_dma_errata();
-        pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
+        pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
        kfree(p);
        if (IS_ERR(pdev)) {
                pr_err("%s: Can't build omap_device for %s:%s.\n",
@@ -288,9 +288,26 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        return 0;
 }
+static const struct platform_device_info omap_dma_dev_info = {
+        .name = "omap-dma-engine",
+        .id = -1,
+        .dma_mask = DMA_BIT_MASK(32),
+};
 static int __init omap2_system_dma_init(void)
 {
-        return omap_hwmod_for_each_by_class("dma",
+        struct platform_device *pdev;
+        int res;
+        res = omap_hwmod_for_each_by_class("dma",
                        omap2_system_dma_init_dev, NULL);
+        if (res)
+                return res;
+        pdev = platform_device_register_full(&omap_dma_dev_info);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+        return res;
 }
-arch_initcall(omap2_system_dma_init);
+omap_arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 0a02aab5df67..3aed4b0b9563 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                if (dd->last_rounded_rate == 0)
                        return -EINVAL;
-                /* No freqsel on OMAP4 and OMAP3630 */
+                /* No freqsel on AM335x, OMAP4 and OMAP3630 */
-                if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+                if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
+                    !cpu_is_omap3630()) {
                        freqsel = _omap3_dpll_compute_freqsel(clk,
                                                dd->last_rounded_n);
                        WARN_ON(!freqsel);
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 2a2cfa88ddbf..59a4af779f42 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -51,8 +51,7 @@ static int __init omap_init_drm(void)
        oh = omap_hwmod_lookup("dmm");
        if (oh) {
-                pdev = omap_device_build(oh->name, -1, oh, NULL, 0, NULL, 0,
+                pdev = omap_device_build(oh->name, -1, oh, NULL, 0);
-                                        false);
                WARN(IS_ERR(pdev), "Could not build omap_device for %s\n",
                        oh->name);
        }
@@ -63,6 +62,6 @@ static int __init omap_init_drm(void)
 }
-arch_initcall(omap_init_drm);
+omap_arch_initcall(omap_init_drm);
 #endif
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index b3566f68a559..cbeaca2d7695 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -47,4 +47,4 @@ static int __init emu_init(void)
        return 0;
 }
-subsys_initcall(emu_init);
+omap_subsys_initcall(emu_init);
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index d9bd965f6d07..190ae493c6ef 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -89,7 +89,7 @@ static int __init omap_init_vrfb(void)
                return 0;
 }
-arch_initcall(omap_init_vrfb);
+omap_arch_initcall(omap_init_vrfb);
 #endif
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@@ -113,6 +113,6 @@ static int __init omap_init_fb(void)
        return platform_device_register(&omap_fb_device);
 }
-arch_initcall(omap_init_fb);
+omap_arch_initcall(omap_init_fb);
 #endif
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 399acabc3d0b..7a577145b68b 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/platform_data/gpio-omap.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "omap-pm.h"
@@ -131,8 +132,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
        pwrdm = omap_hwmod_get_pwrdm(oh);
        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
-        pdev = omap_device_build(name, id - 1, oh, pdata,
+        pdev = omap_device_build(name, id - 1, oh, pdata, sizeof(*pdata));
-                                sizeof(*pdata), NULL, 0, false);
        kfree(pdata);
        if (IS_ERR(pdev)) {
@@ -147,7 +147,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 /*
 * gpio_init needs to be done before
 * machine_init functions access gpio APIs.
- * Hence gpio_init is a postcore_initcall.
+ * Hence gpio_init is a omap_postcore_initcall.
 */
 static int __init omap2_gpio_init(void)
 {
@@ -157,4 +157,4 @@ static int __init omap2_gpio_init(void)
        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
 }
-postcore_initcall(omap2_gpio_init);
+omap_postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index db969a5c4998..afc1e8c32d6c 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
        return 0;
 }
-static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
        /* support only OMAP3 class */
-        if (!cpu_is_omap34xx()) {
+        if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
                pr_err("BCH ecc is not supported on this CPU\n");
                return 0;
        }
        /*
-         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
+         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
-         * Other chips may be added if confirmed to work.
+         * and AM33xx derivates. Other chips may be added if confirmed to work.
         */
        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
+            (!soc_is_am33xx())) {
                pr_err("BCH 4-bit mode is not supported on this CPU\n");
                return 0;
        }
@@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
        return 1;
 }
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
+int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
-                          struct gpmc_timings *gpmc_t)
+                   struct gpmc_timings *gpmc_t)
 {
        int err = 0;
        struct device *dev = &gpmc_nand_device.dev;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 94a349e4dc96..fadd87435cd0 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
        return ret;
 }
-void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
+void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
        int err;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8033cb747c86..e4b16c8efe8b 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -25,6 +25,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_mtd.h>
+#include <linux/of_device.h>
+#include <linux/mtd/nand.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
@@ -34,6 +38,8 @@
 #include "common.h"
 #include "omap_device.h"
 #include "gpmc.h"
+#include "gpmc-nand.h"
+#include "gpmc-onenand.h"
 #define DEVICE_NAME             "omap-gpmc"
@@ -145,7 +151,8 @@ static unsigned gpmc_irq_start;
 static struct resource  gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
+/* Define chip-selects as reserved by default until probe completes */
+static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -783,9 +790,6 @@ static int gpmc_mem_init(void)
         * even if we didn't boot from ROM.
         */
        boot_rom_space = BOOT_ROM_SPACE;
-        /* In apollon the CS0 is mapped as 0x0000 0000 */
-        if (machine_is_omap_apollon())
-                boot_rom_space = 0;
        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
        gpmc_mem_root.end = GPMC_MEM_END;
@@ -1118,8 +1122,215 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
        /* TODO: remove, see function definition */
        gpmc_convert_ps_to_ns(gpmc_t);
+        /* Now the GPMC is initialised, unreserve the chip-selects */
+        gpmc_cs_map = 0;
+        return 0;
+}
+#ifdef CONFIG_OF
+static struct of_device_id gpmc_dt_ids[] = {
+        { .compatible = "ti,omap2420-gpmc" },
+        { .compatible = "ti,omap2430-gpmc" },
+        { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
+        { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
+        { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
+        { }
+};
+MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
+static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
+                                                struct gpmc_timings *gpmc_t)
+{
+        u32 val;
+        memset(gpmc_t, 0, sizeof(*gpmc_t));
+        /* minimum clock period for syncronous mode */
+        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
+                gpmc_t->sync_clk = val;
+        /* chip select timtings */
+        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
+                gpmc_t->cs_on = val;
+        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
+                gpmc_t->cs_rd_off = val;
+        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
+                gpmc_t->cs_wr_off = val;
+        /* ADV signal timings */
+        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
+                gpmc_t->adv_on = val;
+        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
+                gpmc_t->adv_rd_off = val;
+        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
+                gpmc_t->adv_wr_off = val;
+        /* WE signal timings */
+        if (!of_property_read_u32(np, "gpmc,we-on", &val))
+                gpmc_t->we_on = val;
+        if (!of_property_read_u32(np, "gpmc,we-off", &val))
+                gpmc_t->we_off = val;
+        /* OE signal timings */
+        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
+                gpmc_t->oe_on = val;
+        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
+                gpmc_t->oe_off = val;
+        /* access and cycle timings */
+        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
+                gpmc_t->page_burst_access = val;
+        if (!of_property_read_u32(np, "gpmc,access", &val))
+                gpmc_t->access = val;
+        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
+                gpmc_t->rd_cycle = val;
+        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
+                gpmc_t->wr_cycle = val;
+        /* only for OMAP3430 */
+        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
+                gpmc_t->wr_access = val;
+        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
+                gpmc_t->wr_data_mux_bus = val;
+}
+#ifdef CONFIG_MTD_NAND
+static const char * const nand_ecc_opts[] = {
+        [OMAP_ECC_HAMMING_CODE_DEFAULT]         = "sw",
+        [OMAP_ECC_HAMMING_CODE_HW]              = "hw",
+        [OMAP_ECC_HAMMING_CODE_HW_ROMCODE]      = "hw-romcode",
+        [OMAP_ECC_BCH4_CODE_HW]                 = "bch4",
+        [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
+};
+static int gpmc_probe_nand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
+        u32 val;
+        const char *s;
+        struct gpmc_timings gpmc_t;
+        struct omap_nand_platform_data *gpmc_nand_data;
+        if (of_property_read_u32(child, "reg", &val) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+        gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
+                                      GFP_KERNEL);
+        if (!gpmc_nand_data)
+                return -ENOMEM;
+        gpmc_nand_data->cs = val;
+        gpmc_nand_data->of_node = child;
+        if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
+                for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
+                        if (!strcasecmp(s, nand_ecc_opts[val])) {
+                                gpmc_nand_data->ecc_opt = val;
+                                break;
+                        }
+        val = of_get_nand_bus_width(child);
+        if (val == 16)
+                gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_nand_init(gpmc_nand_data, &gpmc_t);
+        return 0;
+}
+#else
+static int gpmc_probe_nand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
        return 0;
 }
+#endif
+#ifdef CONFIG_MTD_ONENAND
+static int gpmc_probe_onenand_child(struct platform_device *pdev,
+                                 struct device_node *child)
+{
+        u32 val;
+        struct omap_onenand_platform_data *gpmc_onenand_data;
+        if (of_property_read_u32(child, "reg", &val) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+        gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
+                                         GFP_KERNEL);
+        if (!gpmc_onenand_data)
+                return -ENOMEM;
+        gpmc_onenand_data->cs = val;
+        gpmc_onenand_data->of_node = child;
+        gpmc_onenand_data->dma_channel = -1;
+        if (!of_property_read_u32(child, "dma-channel", &val))
+                gpmc_onenand_data->dma_channel = val;
+        gpmc_onenand_init(gpmc_onenand_data);
+        return 0;
+}
+#else
+static int gpmc_probe_onenand_child(struct platform_device *pdev,
+                                    struct device_node *child)
+{
+        return 0;
+}
+#endif
+static int gpmc_probe_dt(struct platform_device *pdev)
+{
+        int ret;
+        struct device_node *child;
+        const struct of_device_id *of_id =
+                of_match_device(gpmc_dt_ids, &pdev->dev);
+        if (!of_id)
+                return 0;
+        for_each_node_by_name(child, "nand") {
+                ret = gpmc_probe_nand_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+        for_each_node_by_name(child, "onenand") {
+                ret = gpmc_probe_onenand_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+        return 0;
+}
+#else
+static int gpmc_probe_dt(struct platform_device *pdev)
+{
+        return 0;
+}
+#endif
 static int gpmc_probe(struct platform_device *pdev)
 {
@@ -1134,11 +1345,9 @@ static int gpmc_probe(struct platform_device *pdev)
        phys_base = res->start;
        mem_size = resource_size(res);
-        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
+        gpmc_base = devm_ioremap_resource(&pdev->dev, res);
-        if (!gpmc_base) {
+        if (IS_ERR(gpmc_base))
-                dev_err(&pdev->dev, "error: request memory / ioremap\n");
+                return PTR_ERR(gpmc_base);
-                return -EADDRNOTAVAIL;
-        }
        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
        if (res == NULL)
@@ -1174,6 +1383,14 @@ static int gpmc_probe(struct platform_device *pdev)
        if (IS_ERR_VALUE(gpmc_setup_irq()))
                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+        rc = gpmc_probe_dt(pdev);
+        if (rc < 0) {
+                clk_disable_unprepare(gpmc_l3_clk);
+                clk_put(gpmc_l3_clk);
+                dev_err(gpmc_dev, "failed to probe DT parameters\n");
+                return rc;
+        }
        return 0;
 }
@@ -1191,6 +1408,7 @@ static struct platform_driver gpmc_driver = {
        .driver         = {
                .name   = DEVICE_NAME,
                .owner  = THIS_MODULE,
+                .of_match_table = of_match_ptr(gpmc_dt_ids),
        },
 };
@@ -1205,7 +1423,7 @@ static __exit void gpmc_exit(void)
 }
-postcore_initcall(gpmc_init);
+omap_postcore_initcall(gpmc_init);
 module_exit(gpmc_exit);
 static int __init omap_gpmc_init(void)
@@ -1214,18 +1432,25 @@ static int __init omap_gpmc_init(void)
        struct platform_device *pdev;
        char *oh_name = "gpmc";
+        /*
+         * if the board boots up with a populated DT, do not
+         * manually add the device from this initcall
+         */
+        if (of_have_populated_dt())
+                return -ENODEV;
        oh = omap_hwmod_lookup(oh_name);
        if (!oh) {
                pr_err("Could not look up %s\n", oh_name);
                return -ENODEV;
        }
-        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
 }
-postcore_initcall(omap_gpmc_init);
+omap_postcore_initcall(omap_gpmc_init);
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index ab7bf181a105..cbc8e3c480e0 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -27,6 +27,7 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include "hdq1w.h"
@@ -87,10 +88,10 @@ static int __init omap_init_hdq(void)
        if (!oh)
                return 0;
-        pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0);
+        pdev = omap_device_build(devname, id, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
             devname, oh->name);
        return 0;
 }
-arch_initcall(omap_init_hdq);
+omap_arch_initcall(omap_init_hdq);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 4a964338992a..2ef1f8714fcf 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -522,7 +522,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
        }
        dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
-        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
+        od = omap_device_alloc(pdev, ohs, 1);
        if (IS_ERR(od)) {
                pr_err("Could not allocate od for %s\n", name);
                goto put_pdev;
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 1df9b5feda16..ef175acaeaa2 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/hwspinlock.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
@@ -46,8 +47,7 @@ static int __init hwspinlocks_init(void)
                return -EINVAL;
        pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata,
-                                sizeof(struct hwspinlock_pdata),
+                                sizeof(struct hwspinlock_pdata));
-                                NULL, 0, false);
        if (IS_ERR(pdev)) {
                pr_err("Can't build omap_device for %s:%s\n", dev_name,
                                                                oh_name);
@@ -57,4 +57,4 @@ static int __init hwspinlocks_init(void)
        return retval;
 }
 /* early board code might need to reserve specific hwspinlock instances */
-postcore_initcall(hwspinlocks_init);
+omap_postcore_initcall(hwspinlocks_init);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b9074dde3b9c..d940e53dd9f2 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -178,10 +178,14 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
        if (cpu_is_omap34xx())
                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
        pdev = omap_device_build(name, bus_id, oh, pdata,
-                        sizeof(struct omap_i2c_bus_platform_data),
+                                 sizeof(struct omap_i2c_bus_platform_data));
-                        NULL, 0, 0);
        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
        return PTR_RET(pdev);
 }
+static  int __init omap_i2c_cmdline(void)
+{
+        return omap_register_i2c_bus_cmdline();
+}
+omap_subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1377c363fded..577298ed5a44 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -399,8 +399,18 @@ void __init omap3xxx_check_revision(void)
                }
                break;
        case 0xb944:
-                omap_revision = AM335X_REV_ES1_0;
+                switch (rev) {
-                cpu_rev = "1.0";
+                case 0:
+                        omap_revision = AM335X_REV_ES1_0;
+                        cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = AM335X_REV_ES2_0;
+                        cpu_rev = "2.0";
+                        break;
+                }
                break;
        case 0xb8f2:
                switch (rev) {
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
index 70eda00db7a4..7ca1fcff453b 100644
--- a/arch/arm/mach-omap2/include/mach/serial.h
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -8,20 +8,6 @@
 * GNU General Public License for more details.
 */
-/*
- * Memory entry used for the DEBUG_LL UART configuration, relative to
- * start of RAM. See also uncompress.h and debug-macro.S.
- *
- * Note that using a memory location for storing the UART configuration
- * has at least two limitations:
- *
- * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
- *    uncompress code could then partially overwrite itself
- * 2. We assume printascii is called at least once before paging_init,
- *    and addruart has a chance to read OMAP_UART_INFO
- */
-#define OMAP_UART_INFO_OFS      0x3ffc
 /* OMAP2 serial ports */
 #define OMAP2_UART1_BASE        0x4806a000
 #define OMAP2_UART2_BASE        0x4806c000
@@ -68,29 +54,6 @@
 #define OMAP24XX_BASE_BAUD      (48000000/16)
-/*
- * DEBUG_LL port encoding stored into the UART1 scratchpad register by
- * decomp_setup in uncompress.h
- */
-#define OMAP2UART1              21
-#define OMAP2UART2              22
-#define OMAP2UART3              23
-#define OMAP3UART1              OMAP2UART1
-#define OMAP3UART2              OMAP2UART2
-#define OMAP3UART3              33
-#define OMAP3UART4              34              /* Only on 36xx */
-#define OMAP4UART1              OMAP2UART1
-#define OMAP4UART2              OMAP2UART2
-#define OMAP4UART3              43
-#define OMAP4UART4              44
-#define TI81XXUART1             81
-#define TI81XXUART2             82
-#define TI81XXUART3             83
-#define AM33XXUART1             84
-#define OMAP5UART3              OMAP4UART3
-#define OMAP5UART4              OMAP4UART4
-#define ZOOM_UART               95              /* Only on zoom2/3 */
 #ifndef __ASSEMBLER__
 struct omap_board_data;
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
deleted file mode 100644
index 8e3546d3e041..000000000000
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/serial.h>
-#define MDR1_MODE_MASK                  0x07
-volatile u8 *uart_base;
-int uart_shift;
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
-        /*
-         * Get address of some.bss variable and round it down
-         * a la CONFIG_AUTO_ZRELADDR.
-         */
-        u32 ram_start = (u32)&uart_shift & 0xf8000000;
-        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
-        *uart_info = port;
-}
-static void putc(int c)
-{
-        if (!uart_base)
-                return;
-        /* Check for UART 16x mode */
-        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
-                return;
-        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
-                barrier();
-        uart_base[UART_TX << uart_shift] = c;
-}
-static inline void flush(void)
-{
-}
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
-        if (machine_is_##mach()) {                                      \
-                uart_base = (volatile u8 *)(dbg_uart);                  \
-                uart_shift = (dbg_shft);                                \
-                port = (dbg_id);                                        \
-                set_omap_uart_info(port);                               \
-                break;                                                  \
-        }
-#define DEBUG_LL_OMAP2(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP2UART##p)
-#define DEBUG_LL_OMAP3(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP3UART##p)
-#define DEBUG_LL_OMAP4(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP4UART##p)
-#define DEBUG_LL_OMAP5(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP5UART##p)
-/* Zoom2/3 shift is different for UART1 and external port */
-#define DEBUG_LL_ZOOM(mach)                                             \
-        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI81XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI81XXUART##p)
-#define DEBUG_LL_AM33XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                AM33XXUART##p)
-static inline void arch_decomp_setup(void)
-{
-        int port = 0;
-        /*
-         * Initialize the port based on the machine ID from the bootloader.
-         * Note that we're using macros here instead of switch statement
-         * as machine_is functions are optimized out for the boards that
-         * are not selected.
-         */
-        do {
-                /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap_2430sdp);
-                DEBUG_LL_OMAP2(1, omap_apollon);
-                DEBUG_LL_OMAP2(1, omap_h4);
-                /* omap2 based boards using UART3 */
-                DEBUG_LL_OMAP2(3, nokia_n800);
-                DEBUG_LL_OMAP2(3, nokia_n810);
-                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
-                /* omap3 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap3evm);
-                DEBUG_LL_OMAP3(1, omap_3430sdp);
-                DEBUG_LL_OMAP3(1, omap_3630sdp);
-                DEBUG_LL_OMAP3(1, omap3530_lv_som);
-                DEBUG_LL_OMAP3(1, omap3_torpedo);
-                /* omap3 based boards using UART3 */
-                DEBUG_LL_OMAP3(3, cm_t35);
-                DEBUG_LL_OMAP3(3, cm_t3517);
-                DEBUG_LL_OMAP3(3, cm_t3730);
-                DEBUG_LL_OMAP3(3, craneboard);
-                DEBUG_LL_OMAP3(3, devkit8000);
-                DEBUG_LL_OMAP3(3, igep0020);
-                DEBUG_LL_OMAP3(3, igep0030);
-                DEBUG_LL_OMAP3(3, nokia_rm680);
-                DEBUG_LL_OMAP3(3, nokia_rm696);
-                DEBUG_LL_OMAP3(3, nokia_rx51);
-                DEBUG_LL_OMAP3(3, omap3517evm);
-                DEBUG_LL_OMAP3(3, omap3_beagle);
-                DEBUG_LL_OMAP3(3, omap3_pandora);
-                DEBUG_LL_OMAP3(3, omap_ldp);
-                DEBUG_LL_OMAP3(3, overo);
-                DEBUG_LL_OMAP3(3, touchbook);
-                /* omap4 based boards using UART3 */
-                DEBUG_LL_OMAP4(3, omap_4430sdp);
-                DEBUG_LL_OMAP4(3, omap4_panda);
-                /* omap5 based boards using UART3 */
-                DEBUG_LL_OMAP5(3, omap5_sevm);
-                /* zoom2/3 external uart */
-                DEBUG_LL_ZOOM(omap_zoom2);
-                DEBUG_LL_ZOOM(omap_zoom3);
-                /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI81XX(3, ti8168evm);
-                /* TI8148 base boards using UART1 */
-                DEBUG_LL_TI81XX(1, ti8148evm);
-                /* AM33XX base boards using UART1 */
-                DEBUG_LL_AM33XX(1, am335xevm);
-        } while (0);
-}
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index df49f2a49461..5d8768075dd9 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -23,6 +23,7 @@
 #include <linux/omap-dma.h>
+#include "soc.h"
 #include "omap_device.h"
 /*
@@ -101,7 +102,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                count++;
        }
        pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
-                                sizeof(*pdata), NULL, 0, false);
+                                    sizeof(*pdata));
        kfree(pdata);
        if (IS_ERR(pdev))  {
                pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
@@ -118,4 +119,4 @@ static int __init omap2_mcbsp_init(void)
        return 0;
 }
-arch_initcall(omap2_mcbsp_init);
+omap_arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index aafdd4ca9f4f..c52d8b4a3e91 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -150,7 +150,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
                return;
        }
        pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
-                                 sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
+                                 sizeof(struct omap_mmc_platform_data));
        if (IS_ERR(pdev))
                WARN(1, "Can'd build omap_device for %s:%s.\n",
                                        dev_name, oh->name);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 6da4f7ae9d7f..f6daae821ebb 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/platform_data/iommu-omap.h>
+#include "soc.h"
 #include "omap_hwmod.h"
 #include "omap_device.h"
@@ -41,8 +42,7 @@ static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
                pdata->deassert_reset = omap_device_deassert_hardreset;
        }
-        pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata),
+        pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata));
-                                NULL, 0, 0);
        kfree(pdata);
@@ -61,7 +61,7 @@ static int __init omap_iommu_init(void)
        return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
 }
 /* must be ready before omap3isp is probed */
-subsys_initcall(omap_iommu_init);
+omap_subsys_initcall(omap_iommu_init);
 static void __exit omap_iommu_exit(void)
 {
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index aac46bfdbeb2..8bcb64bcdcdb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -87,37 +87,6 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 }
 /*
- * Set the CPUx powerdomain's previous power state
- */
-static inline void set_cpu_next_pwrst(unsigned int cpu_id,
-                                unsigned int power_state)
-{
-        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-}
-/*
- * Read CPU's previous power state
- */
-static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
-{
-        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-        return pwrdm_read_prev_pwrst(pm_info->pwrdm);
-}
-/*
- * Clear the CPUx powerdomain's previous power state
- */
-static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
-{
-        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-}
-/*
 * Store the SCU power status value to scratchpad memory
 */
 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
@@ -230,6 +199,7 @@ static void save_l2x0_context(void)
 */
 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 {
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
        unsigned int save_state = 0;
        unsigned int wakeup_cpu;
@@ -268,7 +238,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                save_state = 2;
        cpu_clear_prev_logic_pwrst(cpu);
-        set_cpu_next_pwrst(cpu, power_state);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
        scu_pwrst_prepare(cpu, power_state);
        l2x0_pwrst_prepare(cpu, save_state);
@@ -286,7 +256,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
         * domain transition
         */
        wakeup_cpu = smp_processor_id();
-        set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
        pwrdm_post_transition(NULL);
@@ -300,8 +270,8 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 */
 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
-        unsigned int cpu_state = 0;
        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
+        unsigned int cpu_state = 0;
        if (omap_rev() == OMAP4430_REV_ES1_0)
                return -ENXIO;
@@ -309,8 +279,8 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
        if (power_state == PWRDM_POWER_OFF)
                cpu_state = 1;
-        clear_cpu_prev_pwrst(cpu);
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
-        set_cpu_next_pwrst(cpu, power_state);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
        set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
        scu_pwrst_prepare(cpu, power_state);
@@ -321,7 +291,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
         */
        omap4_finish_suspend(cpu_state);
-        set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 707098ecf8d3..7f5626d8fd3e 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -19,9 +19,9 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include "omap-secure.h"
@@ -157,7 +157,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
                booted = true;
        }
-        gic_raise_softirq(cpumask_of(cpu), 0);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        /*
         * Now the secondary core is starting up let it run its
@@ -215,7 +215,7 @@ static void __init omap4_smp_init_cpus(void)
                 * Currently we can't call ioremap here because
                 * SoC detection won't work until after init_early.
                 */
-                scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+                scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
                BUG_ON(!scu_base);
                ncores = scu_get_core_count(scu_base);
        } else if (cpu_id == CPU_CORTEX_A15) {
@@ -231,8 +231,6 @@ static void __init omap4_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 5d3b4f4f81ae..f8bb3b9b6a76 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -24,8 +24,7 @@
 #include <linux/cpu.h>
 #include <linux/notifier.h>
 #include <linux/cpu_pm.h>
+#include <linux/irqchip/arm-gic.h>
-#include <asm/hardware/gic.h>
 #include "omap-wakeupgen.h"
 #include "omap-secure.h"
@@ -46,7 +45,7 @@
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
-static DEFINE_SPINLOCK(wakeupgen_lock);
+static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[MAX_IRQS];
 static unsigned int irq_banks = MAX_NR_REG_BANKS;
 static unsigned int max_irqs = MAX_IRQS;
@@ -134,9 +133,9 @@ static void wakeupgen_mask(struct irq_data *d)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 /*
@@ -146,9 +145,9 @@ static void wakeupgen_unmask(struct irq_data *d)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 #ifdef CONFIG_HOTPLUG_CPU
@@ -189,7 +188,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 {
        unsigned long flags;
-        spin_lock_irqsave(&wakeupgen_lock, flags);
+        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
        if (set) {
                _wakeupgen_save_masks(cpu);
                _wakeupgen_set_all(cpu, WKG_MASK_ALL);
@@ -197,7 +196,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
                _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
                _wakeupgen_restore_masks(cpu);
        }
-        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index be6bc89ab1e8..719b716a4494 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -13,6 +13,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
+#include "soc.h"
 #include "common.h"
 #include "prm2xxx.h"
@@ -62,4 +63,4 @@ static int __init omap2xxx_common_look_up_clks_for_reset(void)
        return 0;
 }
-core_initcall(omap2xxx_common_look_up_clks_for_reset);
+omap_core_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 6897ae21bb82..708bb115a27f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -15,13 +15,14 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/export.h>
+#include <linux/irqchip/arm-gic.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
@@ -225,7 +226,7 @@ static int __init omap_l2_cache_init(void)
        return 0;
 }
-early_initcall(omap_l2_cache_init);
+omap_early_initcall(omap_l2_cache_init);
 #endif
 void __iomem *omap4_get_sar_ram_base(void)
@@ -253,18 +254,12 @@ static int __init omap4_sar_ram_init(void)
        return 0;
 }
-early_initcall(omap4_sar_ram_init);
+omap_early_initcall(omap4_sar_ram_init);
-static struct of_device_id irq_match[] __initdata = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
-        { }
-};
 void __init omap_gic_of_init(void)
 {
        omap_wakeupgen_init();
-        of_irq_init(irq_match);
+        irqchip_init();
 }
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
diff --git a/arch/arm/mach-omap2/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h
index 43b927b2e2e8..8a515bb74639 100644
--- a/arch/arm/mach-omap2/omap44xx.h
+++ b/arch/arm/mach-omap2/omap44xx.h
@@ -40,7 +40,6 @@
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
 #define OMAP44XX_IRQ_GIC_START          32
-#define OMAP44XX_SCU_BASE               0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
 #define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e065daa537c0..381be7ac0c17 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -17,68 +17,15 @@
 * to control power management and interconnect properties of their
 * devices.
 *
- * In the medium- to long-term, this code should either be
+ * In the medium- to long-term, this code should be implemented as a
- * a) implemented via arch-specific pointers in platform_data
+ * proper omap_bus/omap_device in Linux, no more platform_data func
- * or
+ * pointers
- * b) implemented as a proper omap_bus/omap_device in Linux, no more
- *    platform_data func pointers
 *
 *
- * Guidelines for usage by driver authors:
- *
- * 1. These functions are intended to be used by device drivers via
- * function pointers in struct platform_data.  As an example,
- * omap_device_enable() should be passed to the driver as
- *
- * struct foo_driver_platform_data {
- * ...
- *      int (*device_enable)(struct platform_device *pdev);
- * ...
- * }
- *
- * Note that the generic "device_enable" name is used, rather than
- * "omap_device_enable".  This is so other architectures can pass in their
- * own enable/disable functions here.
- *
- * This should be populated during device setup:
- *
- * ...
- * pdata->device_enable = omap_device_enable;
- * ...
- *
- * 2. Drivers should first check to ensure the function pointer is not null
- * before calling it, as in:
- *
- * if (pdata->device_enable)
- *     pdata->device_enable(pdev);
- *
- * This allows other architectures that don't use similar device_enable()/
- * device_shutdown() functions to execute normally.
- *
- * ...
- *
- * Suggested usage by device drivers:
- *
- * During device initialization:
- * device_enable()
- *
- * During device idle:
- * (save remaining device context if necessary)
- * device_idle();
- *
- * During device resume:
- * device_enable();
- * (restore context if necessary)
- *
- * During device shutdown:
- * device_shutdown()
- * (device must be reinitialized at this point to use it again)
- *
 */
 #undef DEBUG
 #include <linux/kernel.h>
-#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/err.h>
@@ -89,158 +36,12 @@
 #include <linux/of.h>
 #include <linux/notifier.h>
+#include "soc.h"
 #include "omap_device.h"
 #include "omap_hwmod.h"
-/* These parameters are passed to _omap_device_{de,}activate() */
-#define USE_WAKEUP_LAT                  0
-#define IGNORE_WAKEUP_LAT               1
-static int omap_early_device_register(struct platform_device *pdev);
-static struct omap_device_pm_latency omap_default_latency[] = {
-        {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-        }
-};
 /* Private functions */
-/**
- * _omap_device_activate - increase device readiness
- * @od: struct omap_device *
- * @ignore_lat: increase to latency target (0) or full readiness (1)?
- *
- * Increase readiness of omap_device @od (thus decreasing device
- * wakeup latency, but consuming more power).  If @ignore_lat is
- * IGNORE_WAKEUP_LAT, make the omap_device fully active.  Otherwise,
- * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
- * latency is greater than the requested maximum wakeup latency, step
- * backwards in the omap_device_pm_latency table to ensure the
- * device's maximum wakeup latency is less than or equal to the
- * requested maximum wakeup latency.  Returns 0.
- */
-static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
-{
-        struct timespec a, b, c;
-        dev_dbg(&od->pdev->dev, "omap_device: activating\n");
-        while (od->pm_lat_level > 0) {
-                struct omap_device_pm_latency *odpl;
-                unsigned long long act_lat = 0;
-                od->pm_lat_level--;
-                odpl = od->pm_lats + od->pm_lat_level;
-                if (!ignore_lat &&
-                    (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
-                        break;
-                read_persistent_clock(&a);
-                /* XXX check return code */
-                odpl->activate_func(od);
-                read_persistent_clock(&b);
-                c = timespec_sub(b, a);
-                act_lat = timespec_to_ns(&c);
-                dev_dbg(&od->pdev->dev,
-                        "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
-                        od->pm_lat_level, act_lat);
-                if (act_lat > odpl->activate_lat) {
-                        odpl->activate_lat_worst = act_lat;
-                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
-                                odpl->activate_lat = act_lat;
-                                dev_dbg(&od->pdev->dev,
-                                        "new worst case activate latency %d: %llu\n",
-                                        od->pm_lat_level, act_lat);
-                        } else
-                                dev_warn(&od->pdev->dev,
-                                         "activate latency %d higher than expected. (%llu > %d)\n",
-                                         od->pm_lat_level, act_lat,
-                                         odpl->activate_lat);
-                }
-                od->dev_wakeup_lat -= odpl->activate_lat;
-        }
-        return 0;
-}
-/**
- * _omap_device_deactivate - decrease device readiness
- * @od: struct omap_device *
- * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
- *
- * Decrease readiness of omap_device @od (thus increasing device
- * wakeup latency, but conserving power).  If @ignore_lat is
- * IGNORE_WAKEUP_LAT, make the omap_device fully inactive.  Otherwise,
- * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
- * latency is less than the requested maximum wakeup latency, step
- * forwards in the omap_device_pm_latency table to ensure the device's
- * maximum wakeup latency is less than or equal to the requested
- * maximum wakeup latency.  Returns 0.
- */
-static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
-{
-        struct timespec a, b, c;
-        dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
-        while (od->pm_lat_level < od->pm_lats_cnt) {
-                struct omap_device_pm_latency *odpl;
-                unsigned long long deact_lat = 0;
-                odpl = od->pm_lats + od->pm_lat_level;
-                if (!ignore_lat &&
-                    ((od->dev_wakeup_lat + odpl->activate_lat) >
-                     od->_dev_wakeup_lat_limit))
-                        break;
-                read_persistent_clock(&a);
-                /* XXX check return code */
-                odpl->deactivate_func(od);
-                read_persistent_clock(&b);
-                c = timespec_sub(b, a);
-                deact_lat = timespec_to_ns(&c);
-                dev_dbg(&od->pdev->dev,
-                        "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
-                        od->pm_lat_level, deact_lat);
-                if (deact_lat > odpl->deactivate_lat) {
-                        odpl->deactivate_lat_worst = deact_lat;
-                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
-                                odpl->deactivate_lat = deact_lat;
-                                dev_dbg(&od->pdev->dev,
-                                        "new worst case deactivate latency %d: %llu\n",
-                                        od->pm_lat_level, deact_lat);
-                        } else
-                                dev_warn(&od->pdev->dev,
-                                         "deactivate latency %d higher than expected. (%llu > %d)\n",
-                                         od->pm_lat_level, deact_lat,
-                                         odpl->deactivate_lat);
-                }
-                od->dev_wakeup_lat += odpl->activate_lat;
-                od->pm_lat_level++;
-        }
-        return 0;
-}
 static void _add_clkdev(struct omap_device *od, const char *clk_alias,
                       const char *clk_name)
 {
@@ -315,9 +116,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
 * @oh: ptr to the single omap_hwmod that backs this omap_device
 * @pdata: platform_data ptr to associate with the platform_device
 * @pdata_len: amount of memory pointed to by @pdata
- * @pm_lats: pointer to a omap_device_pm_latency array for this device
- * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- * @is_early_device: should the device be registered as an early device or not
 *
 * Function for building an omap_device already registered from device-tree
 *
@@ -356,7 +154,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                hwmods[i] = oh;
        }
-        od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
+        od = omap_device_alloc(pdev, hwmods, oh_cnt);
        if (!od) {
                dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
                        oh_name);
@@ -407,6 +205,39 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
        return NOTIFY_DONE;
 }
+/**
+ * _omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
+ * @od: struct omap_device *od
+ *
+ * Enable all underlying hwmods.  Returns 0.
+ */
+static int _omap_device_enable_hwmods(struct omap_device *od)
+{
+        int i;
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_enable(od->hwmods[i]);
+        /* XXX pass along return value here? */
+        return 0;
+}
+/**
+ * _omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
+ * @od: struct omap_device *od
+ *
+ * Idle all underlying hwmods.  Returns 0.
+ */
+static int _omap_device_idle_hwmods(struct omap_device *od)
+{
+        int i;
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_idle(od->hwmods[i]);
+        /* XXX pass along return value here? */
+        return 0;
+}
 /* Public functions for use by core code */
@@ -526,18 +357,14 @@ static int _od_fill_dma_resources(struct omap_device *od,
 * @oh: ptr to the single omap_hwmod that backs this omap_device
 * @pdata: platform_data ptr to associate with the platform_device
 * @pdata_len: amount of memory pointed to by @pdata
- * @pm_lats: pointer to a omap_device_pm_latency array for this device
- * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
 *
 * Convenience function for allocating an omap_device structure and filling
- * hwmods, resources and pm_latency attributes.
+ * hwmods, and resources.
 *
 * Returns an struct omap_device pointer or ERR_PTR() on error;
 */
 struct omap_device *omap_device_alloc(struct platform_device *pdev,
-                                        struct omap_hwmod **ohs, int oh_cnt,
+                                        struct omap_hwmod **ohs, int oh_cnt)
-                                        struct omap_device_pm_latency *pm_lats,
-                                        int pm_lats_cnt)
 {
        int ret = -ENOMEM;
        struct omap_device *od;
@@ -626,18 +453,6 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
                goto oda_exit3;
 have_everything:
-        if (!pm_lats) {
-                pm_lats = omap_default_latency;
-                pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
-        }
-        od->pm_lats_cnt = pm_lats_cnt;
-        od->pm_lats = kmemdup(pm_lats,
-                        sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
-                        GFP_KERNEL);
-        if (!od->pm_lats)
-                goto oda_exit3;
        pdev->archdata.od = od;
        for (i = 0; i < oh_cnt; i++) {
@@ -663,7 +478,6 @@ void omap_device_delete(struct omap_device *od)
                return;
        od->pdev->archdata.od = NULL;
-        kfree(od->pm_lats);
        kfree(od->hwmods);
        kfree(od);
 }
@@ -675,9 +489,6 @@ void omap_device_delete(struct omap_device *od)
 * @oh: ptr to the single omap_hwmod that backs this omap_device
 * @pdata: platform_data ptr to associate with the platform_device
 * @pdata_len: amount of memory pointed to by @pdata
- * @pm_lats: pointer to a omap_device_pm_latency array for this device
- * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- * @is_early_device: should the device be registered as an early device or not
 *
 * Convenience function for building and registering a single
 * omap_device record, which in turn builds and registers a
@@ -685,11 +496,10 @@ void omap_device_delete(struct omap_device *od)
 * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
 * passes along the return value of omap_device_build_ss().
 */
-struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build(const char *pdev_name,
-                                      struct omap_hwmod *oh, void *pdata,
+                                                 int pdev_id,
-                                      int pdata_len,
+                                                 struct omap_hwmod *oh,
-                                      struct omap_device_pm_latency *pm_lats,
+                                                 void *pdata, int pdata_len)
-                                      int pm_lats_cnt, int is_early_device)
 {
        struct omap_hwmod *ohs[] = { oh };
@@ -697,8 +507,7 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
                return ERR_PTR(-EINVAL);
        return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
-                                    pdata_len, pm_lats, pm_lats_cnt,
+                                    pdata_len);
-                                    is_early_device);
 }
 /**
@@ -708,9 +517,6 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
 * @oh: ptr to the single omap_hwmod that backs this omap_device
 * @pdata: platform_data ptr to associate with the platform_device
 * @pdata_len: amount of memory pointed to by @pdata
- * @pm_lats: pointer to a omap_device_pm_latency array for this device
- * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
- * @is_early_device: should the device be registered as an early device or not
 *
 * Convenience function for building and registering an omap_device
 * subsystem record.  Subsystem records consist of multiple
@@ -718,11 +524,11 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
 * platform_device record.  Returns an ERR_PTR() on error, or passes
 * along the return value of omap_device_register().
 */
-struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build_ss(const char *pdev_name,
-                                         struct omap_hwmod **ohs, int oh_cnt,
+                                                    int pdev_id,
-                                         void *pdata, int pdata_len,
+                                                    struct omap_hwmod **ohs,
-                                         struct omap_device_pm_latency *pm_lats,
+                                                    int oh_cnt, void *pdata,
-                                         int pm_lats_cnt, int is_early_device)
+                                                    int pdata_len)
 {
        int ret = -ENOMEM;
        struct platform_device *pdev;
@@ -746,7 +552,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p
        else
                dev_set_name(&pdev->dev, "%s", pdev->name);
-        od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
+        od = omap_device_alloc(pdev, ohs, oh_cnt);
        if (IS_ERR(od))
                goto odbs_exit1;
@@ -754,10 +560,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p
        if (ret)
                goto odbs_exit2;
-        if (is_early_device)
+        ret = omap_device_register(pdev);
-                ret = omap_early_device_register(pdev);
-        else
-                ret = omap_device_register(pdev);
        if (ret)
                goto odbs_exit2;
@@ -774,24 +577,6 @@ odbs_exit:
        return ERR_PTR(ret);
 }
-/**
- * omap_early_device_register - register an omap_device as an early platform
- * device.
- * @od: struct omap_device * to register
- *
- * Register the omap_device structure.  This currently just calls
- * platform_early_add_device() on the underlying platform_device.
- * Returns 0 by default.
- */
-static int __init omap_early_device_register(struct platform_device *pdev)
-{
-        struct platform_device *devices[1];
-        devices[0] = pdev;
-        early_platform_add_devices(devices, 1);
-        return 0;
-}
 #ifdef CONFIG_PM_RUNTIME
 static int _od_runtime_suspend(struct device *dev)
 {
@@ -902,10 +687,9 @@ int omap_device_register(struct platform_device *pdev)
 * to be accessible and ready to operate.  This generally involves
 * enabling clocks, setting SYSCONFIG registers; and in the future may
 * involve remuxing pins.  Device drivers should call this function
- * (through platform_data function pointers) where they would normally
+ * indirectly via pm_runtime_get*().  Returns -EINVAL if called when
- * enable clocks, etc.  Returns -EINVAL if called when the omap_device
+ * the omap_device is already enabled, or passes along the return
- * is already enabled, or passes along the return value of
+ * value of _omap_device_enable_hwmods().
- * _omap_device_activate().
 */
 int omap_device_enable(struct platform_device *pdev)
 {
@@ -921,14 +705,8 @@ int omap_device_enable(struct platform_device *pdev)
                return -EINVAL;
        }
-        /* Enable everything if we're enabling this device from scratch */
+        ret = _omap_device_enable_hwmods(od);
-        if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
-                od->pm_lat_level = od->pm_lats_cnt;
-        ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
-        od->dev_wakeup_lat = 0;
-        od->_dev_wakeup_lat_limit = UINT_MAX;
        od->_state = OMAP_DEVICE_STATE_ENABLED;
        return ret;
@@ -938,14 +716,10 @@ int omap_device_enable(struct platform_device *pdev)
 * omap_device_idle - idle an omap_device
 * @od: struct omap_device * to idle
 *
- * Idle omap_device @od by calling as many .deactivate_func() entries
+ * Idle omap_device @od.  Device drivers call this function indirectly
- * in the omap_device's pm_lats table as is possible without exceeding
+ * via pm_runtime_put*().  Returns -EINVAL if the omap_device is not
- * the device's maximum wakeup latency limit, pm_lat_limit.  Device
- * drivers should call this function (through platform_data function
- * pointers) where they would normally disable clocks after operations
- * complete, etc..  Returns -EINVAL if the omap_device is not
 * currently enabled, or passes along the return value of
- * _omap_device_deactivate().
+ * _omap_device_idle_hwmods().
 */
 int omap_device_idle(struct platform_device *pdev)
 {
@@ -961,7 +735,7 @@ int omap_device_idle(struct platform_device *pdev)
                return -EINVAL;
        }
-        ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
+        ret = _omap_device_idle_hwmods(od);
        od->_state = OMAP_DEVICE_STATE_IDLE;
@@ -969,42 +743,6 @@ int omap_device_idle(struct platform_device *pdev)
 }
 /**
- * omap_device_shutdown - shut down an omap_device
- * @od: struct omap_device * to shut down
- *
- * Shut down omap_device @od by calling all .deactivate_func() entries
- * in the omap_device's pm_lats table and then shutting down all of
- * the underlying omap_hwmods.  Used when a device is being "removed"
- * or a device driver is being unloaded.  Returns -EINVAL if the
- * omap_device is not currently enabled or idle, or passes along the
- * return value of _omap_device_deactivate().
- */
-int omap_device_shutdown(struct platform_device *pdev)
-{
-        int ret, i;
-        struct omap_device *od;
-        od = to_omap_device(pdev);
-        if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
-            od->_state != OMAP_DEVICE_STATE_IDLE) {
-                dev_warn(&pdev->dev,
-                         "omap_device: %s() called from invalid state %d\n",
-                         __func__, od->_state);
-                return -EINVAL;
-        }
-        ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
-        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_shutdown(od->hwmods[i]);
-        od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
-        return ret;
-}
-/**
 * omap_device_assert_hardreset - set a device's hardreset line
 * @pdev: struct platform_device * to reset
 * @name: const char * name of the reset line
@@ -1060,86 +798,6 @@ int omap_device_deassert_hardreset(struct platform_device *pdev,
 }
 /**
- * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
- * @od: struct omap_device *
- *
- * When a device's maximum wakeup latency limit changes, call some of
- * the .activate_func or .deactivate_func function pointers in the
- * omap_device's pm_lats array to ensure that the device's maximum
- * wakeup latency is less than or equal to the new latency limit.
- * Intended to be called by OMAP PM code whenever a device's maximum
- * wakeup latency limit changes (e.g., via
- * omap_pm_set_dev_wakeup_lat()).  Returns 0 if nothing needs to be
- * done (e.g., if the omap_device is not currently idle, or if the
- * wakeup latency is already current with the new limit) or passes
- * along the return value of _omap_device_deactivate() or
- * _omap_device_activate().
- */
-int omap_device_align_pm_lat(struct platform_device *pdev,
-                             u32 new_wakeup_lat_limit)
-{
-        int ret = -EINVAL;
-        struct omap_device *od;
-        od = to_omap_device(pdev);
-        if (new_wakeup_lat_limit == od->dev_wakeup_lat)
-                return 0;
-        od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
-        if (od->_state != OMAP_DEVICE_STATE_IDLE)
-                return 0;
-        else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
-                ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
-        else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
-                ret = _omap_device_activate(od, USE_WAKEUP_LAT);
-        return ret;
-}
-/**
- * omap_device_get_pwrdm - return the powerdomain * associated with @od
- * @od: struct omap_device *
- *
- * Return the powerdomain associated with the first underlying
- * omap_hwmod for this omap_device.  Intended for use by core OMAP PM
- * code.  Returns NULL on error or a struct powerdomain * upon
- * success.
- */
-struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
-{
-        /*
-         * XXX Assumes that all omap_hwmod powerdomains are identical.
-         * This may not necessarily be true.  There should be a sanity
-         * check in here to WARN() if any difference appears.
-         */
-        if (!od->hwmods_cnt)
-                return NULL;
-        return omap_hwmod_get_pwrdm(od->hwmods[0]);
-}
-/**
- * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
- * @od: struct omap_device *
- *
- * Return the MPU's virtual address for the base of the hwmod, from
- * the ioremap() that the hwmod code does.  Only valid if there is one
- * hwmod associated with this device.  Returns NULL if there are zero
- * or more than one hwmods associated with this omap_device;
- * otherwise, passes along the return value from
- * omap_hwmod_get_mpu_rt_va().
- */
-void __iomem *omap_device_get_rt_va(struct omap_device *od)
-{
-        if (od->hwmods_cnt != 1)
-                return NULL;
-        return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
-}
-/**
 * omap_device_get_by_hwmod_name() - convert a hwmod name to
 * device pointer.
 * @oh_name: name of the hwmod device
@@ -1173,82 +831,6 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name)
        return &oh->od->pdev->dev;
 }
-EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
-/*
- * Public functions intended for use in omap_device_pm_latency
- * .activate_func and .deactivate_func function pointers
- */
-/**
- * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
- * @od: struct omap_device *od
- *
- * Enable all underlying hwmods.  Returns 0.
- */
-int omap_device_enable_hwmods(struct omap_device *od)
-{
-        int i;
-        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_enable(od->hwmods[i]);
-        /* XXX pass along return value here? */
-        return 0;
-}
-/**
- * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
- * @od: struct omap_device *od
- *
- * Idle all underlying hwmods.  Returns 0.
- */
-int omap_device_idle_hwmods(struct omap_device *od)
-{
-        int i;
-        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_idle(od->hwmods[i]);
-        /* XXX pass along return value here? */
-        return 0;
-}
-/**
- * omap_device_disable_clocks - disable all main and interface clocks
- * @od: struct omap_device *od
- *
- * Disable the main functional clock and interface clock for all of the
- * omap_hwmods associated with the omap_device.  Returns 0.
- */
-int omap_device_disable_clocks(struct omap_device *od)
-{
-        int i;
-        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_disable_clocks(od->hwmods[i]);
-        /* XXX pass along return value here? */
-        return 0;
-}
-/**
- * omap_device_enable_clocks - enable all main and interface clocks
- * @od: struct omap_device *od
- *
- * Enable the main functional clock and interface clock for all of the
- * omap_hwmods associated with the omap_device.  Returns 0.
- */
-int omap_device_enable_clocks(struct omap_device *od)
-{
-        int i;
-        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_enable_clocks(od->hwmods[i]);
-        /* XXX pass along return value here? */
-        return 0;
-}
 static struct notifier_block platform_nb = {
        .notifier_call = _omap_device_notifier_call,
@@ -1259,7 +841,7 @@ static int __init omap_device_init(void)
        bus_register_notifier(&platform_bus_type, &platform_nb);
        return 0;
 }
-core_initcall(omap_device_init);
+omap_core_initcall(omap_device_init);
 /**
 * omap_device_late_idle - idle devices without drivers
@@ -1297,4 +879,4 @@ static int __init omap_device_late_init(void)
        bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
        return 0;
 }
-late_initcall(omap_device_late_init);
+omap_late_initcall(omap_device_late_init);
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 0933c599bf89..044c31d50e5b 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -13,20 +13,12 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
- * Eventually this type of functionality should either be
+ * This type of functionality should be implemented as a proper
- * a) implemented via arch-specific pointers in platform_device
+ * omap_bus/omap_device in Linux.
- * or
- * b) implemented as a proper omap_bus/omap_device in Linux, no more
- *    platform_device
 *
 * omap_device differs from omap_hwmod in that it includes external
 * (e.g., board- and system-level) integration details.  omap_hwmod
 * stores hardware data that is invariant for a given OMAP chip.
- *
- * To do:
- * - GPIO integration
- * - regulator integration
- *
 */
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
@@ -45,19 +37,14 @@ extern struct dev_pm_domain omap_device_pm_domain;
 #define OMAP_DEVICE_STATE_SHUTDOWN      3
 /* omap_device.flags values */
-#define OMAP_DEVICE_SUSPENDED BIT(0)
+#define OMAP_DEVICE_SUSPENDED           BIT(0)
-#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
+#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND  BIT(1)
 /**
 * struct omap_device - omap_device wrapper for platform_devices
 * @pdev: platform_device
 * @hwmods: (one .. many per omap_device)
 * @hwmods_cnt: ARRAY_SIZE() of @hwmods
- * @pm_lats: ptr to an omap_device_pm_latency table
- * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
- * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- * @dev_wakeup_lat: dev wakeup latency in nanoseconds
- * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
 * @_state: one of OMAP_DEVICE_STATE_* (see above)
 * @flags: device flags
 * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
@@ -71,12 +58,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
 struct omap_device {
        struct platform_device          *pdev;
        struct omap_hwmod               **hwmods;
-        struct omap_device_pm_latency   *pm_lats;
-        u32                             dev_wakeup_lat;
-        u32                             _dev_wakeup_lat_limit;
        unsigned long                   _driver_status;
-        u8                              pm_lats_cnt;
-        s8                              pm_lat_level;
        u8                              hwmods_cnt;
        u8                              _state;
        u8                              flags;
@@ -86,36 +68,25 @@ struct omap_device {
 int omap_device_enable(struct platform_device *pdev);
 int omap_device_idle(struct platform_device *pdev);
-int omap_device_shutdown(struct platform_device *pdev);
 /* Core code interface */
 struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
-                                      struct omap_hwmod *oh, void *pdata,
+                                          struct omap_hwmod *oh, void *pdata,
-                                      int pdata_len,
+                                          int pdata_len);
-                                      struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt, int is_early_device);
 struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                         struct omap_hwmod **oh, int oh_cnt,
-                                         void *pdata, int pdata_len,
+                                         void *pdata, int pdata_len);
-                                         struct omap_device_pm_latency *pm_lats,
-                                         int pm_lats_cnt, int is_early_device);
 struct omap_device *omap_device_alloc(struct platform_device *pdev,
-                                      struct omap_hwmod **ohs, int oh_cnt,
+                                      struct omap_hwmod **ohs, int oh_cnt);
-                                      struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt);
 void omap_device_delete(struct omap_device *od);
 int omap_device_register(struct platform_device *pdev);
-void __iomem *omap_device_get_rt_va(struct omap_device *od);
 struct device *omap_device_get_by_hwmod_name(const char *oh_name);
 /* OMAP PM interface */
-int omap_device_align_pm_lat(struct platform_device *pdev,
-                             u32 new_wakeup_lat_limit);
-struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
 int omap_device_get_context_loss_count(struct platform_device *pdev);
 /* Other */
@@ -124,40 +95,6 @@ int omap_device_assert_hardreset(struct platform_device *pdev,
                                 const char *name);
 int omap_device_deassert_hardreset(struct platform_device *pdev,
                                 const char *name);
-int omap_device_idle_hwmods(struct omap_device *od);
-int omap_device_enable_hwmods(struct omap_device *od);
-int omap_device_disable_clocks(struct omap_device *od);
-int omap_device_enable_clocks(struct omap_device *od);
-/*
- * Entries should be kept in latency order ascending
- *
- * deact_lat is the maximum number of microseconds required to complete
- * deactivate_func() at the device's slowest OPP.
- *
- * act_lat is the maximum number of microseconds required to complete
- * activate_func() at the device's slowest OPP.
- *
- * This will result in some suboptimal power management decisions at fast
- * OPPs, but avoids having to recompute all device power management decisions
- * if the system shifts from a fast OPP to a slow OPP (in order to meet
- * latency requirements).
- *
- * XXX should deactivate_func/activate_func() take platform_device pointers
- * rather than omap_device pointers?
- */
-struct omap_device_pm_latency {
-        u32 deactivate_lat;
-        u32 deactivate_lat_worst;
-        int (*deactivate_func)(struct omap_device *od);
-        u32 activate_lat;
-        u32 activate_lat_worst;
-        int (*activate_func)(struct omap_device *od);
-        u32 flags;
-};
-#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 /* Get omap_device pointer from platform_device pointer */
 static inline struct omap_device *to_omap_device(struct platform_device *pdev)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 4653efb87a27..c2c798c08c2b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,6 +139,8 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
+#include <asm/system_misc.h>
 #include "clock.h"
 #include "omap_hwmod.h"
@@ -2053,6 +2055,23 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh)
 }
 /**
+ * _enable_preprogram - Pre-program an IP block during the _enable() process
+ * @oh: struct omap_hwmod *
+ *
+ * Some IP blocks (such as AESS) require some additional programming
+ * after enable before they can enter idle.  If a function pointer to
+ * do so is present in the hwmod data, then call it and pass along the
+ * return value; otherwise, return 0.
+ */
+static int __init _enable_preprogram(struct omap_hwmod *oh)
+{
+        if (!oh->class->enable_preprogram)
+                return 0;
+        return oh->class->enable_preprogram(oh);
+}
+/**
 * _enable - enable an omap_hwmod
 * @oh: struct omap_hwmod *
 *
@@ -2134,6 +2153,8 @@ static int _enable(struct omap_hwmod *oh)
        _enable_clocks(oh);
        if (soc_ops.enable_module)
                soc_ops.enable_module(oh);
+        if (oh->flags & HWMOD_BLOCK_WFI)
+                disable_hlt();
        if (soc_ops.update_context_lost)
                soc_ops.update_context_lost(oh);
@@ -2156,6 +2177,7 @@ static int _enable(struct omap_hwmod *oh)
                                _update_sysc_cache(oh);
                        _enable_sysc(oh);
                }
+                r = _enable_preprogram(oh);
        } else {
                if (soc_ops.disable_module)
                        soc_ops.disable_module(oh);
@@ -2195,6 +2217,8 @@ static int _idle(struct omap_hwmod *oh)
                _idle_sysc(oh);
        _del_initiator_dep(oh, mpu_oh);
+        if (oh->flags & HWMOD_BLOCK_WFI)
+                enable_hlt();
        if (soc_ops.disable_module)
                soc_ops.disable_module(oh);
@@ -2303,6 +2327,8 @@ static int _shutdown(struct omap_hwmod *oh)
        if (oh->_state == _HWMOD_STATE_ENABLED) {
                _del_initiator_dep(oh, mpu_oh);
                /* XXX what about the other system initiators here? dma, dsp */
+                if (oh->flags & HWMOD_BLOCK_WFI)
+                        enable_hlt();
                if (soc_ops.disable_module)
                        soc_ops.disable_module(oh);
                _disable_clocks(oh);
@@ -3041,11 +3067,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
                                     struct omap_hwmod_rst_info *ohri)
 {
-        if (ohri->st_shift)
-                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
-                       oh->name, ohri->name);
        return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+                                ohri->st_shift,
                                oh->clkdm->pwrdm.ptr->prcm_offs,
                                oh->prcm.omap4.rstctrl_offs,
                                oh->prcm.omap4.rstst_offs);
@@ -3303,7 +3326,7 @@ static int __init omap_hwmod_setup_all(void)
        return 0;
 }
-core_initcall(omap_hwmod_setup_all);
+omap_core_initcall(omap_hwmod_setup_all);
 /**
 * omap_hwmod_enable - enable an omap_hwmod
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 3ae852a522f9..d43d9b608eda 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -451,6 +451,14 @@ struct omap_hwmod_omap4_prcm {
 *     enabled.  This prevents the hwmod code from being able to
 *     enable and reset the IP block early.  XXX Eventually it should
 *     be possible to query the clock framework for this information.
+ * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
+ *     correctly if the MPU is allowed to go idle while the
+ *     peripherals are active.  This is apparently true for the I2C on
+ *     OMAP2420, and also the EMAC on AM3517/3505.  It's unlikely that
+ *     this is really true -- we're probably not configuring something
+ *     correctly, or this is being abused to deal with some PM latency
+ *     issues -- but we're currently suffering from a shortage of
+ *     folks who are able to track these issues down properly.
 */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -462,6 +470,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_CONTROL_OPT_CLKS_IN_RESET         (1 << 7)
 #define HWMOD_16BIT_REG                         (1 << 8)
 #define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
+#define HWMOD_BLOCK_WFI                         (1 << 10)
 /*
 * omap_hwmod._int_flags definitions
@@ -501,6 +510,7 @@ struct omap_hwmod_omap4_prcm {
 * @rev: revision of the IP class
 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
+ * @enable_preprogram:  ptr to fn to be executed during device enable
 *
 * Represent the class of a OMAP hardware "modules" (e.g. timer,
 * smartreflex, gpio, uart...)
@@ -524,6 +534,7 @@ struct omap_hwmod_class {
        u32                                     rev;
        int                                     (*pre_shutdown)(struct omap_hwmod *oh);
        int                                     (*reset)(struct omap_hwmod *oh);
+        int                                     (*enable_preprogram)(struct omap_hwmod *oh);
 };
 /**
@@ -671,6 +682,12 @@ extern void __init omap_hwmod_init(void);
 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
 /*
+ *
+ */
+extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
+/*
 * Chip variant-specific hwmod init routines - XXX should be converted
 * to use initcalls once the initial boot ordering is straightened out
 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5efe58c0be0..6a764af6c6d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -121,7 +121,12 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
        },
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
-        .flags          = HWMOD_16BIT_REG,
+        /*
+         * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
+         * while a transfer is active seems to cause the I2C block to
+         * timeout. Why? Good question."
+         */
+        .flags          = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
 };
 /* I2C2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 646c14d9fdb9..26eee4a556ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -262,13 +262,15 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
        .name           = "wkup_m3",
        .class          = &am33xx_wkup_m3_hwmod_class,
        .clkdm_name     = "l4_wkup_aon_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
+        /* Keep hardreset asserted */
+        .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
        .mpu_irqs       = am33xx_wkup_m3_irqs,
        .main_clk       = "dpll_core_m4_div2_ck",
        .prcm           = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
                        .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+                        .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -414,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 *    - cEFUSE (doesn't fall under any ocp_if)
 *    - clkdiv32k
 *    - debugss
- *    - ocmc ram
 *    - ocp watch point
 *    - aes0
 *    - sha0
@@ -481,25 +482,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
        },
 };
-/* ocmcram */
-static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
-        .name = "ocmcram",
-};
-static struct omap_hwmod am33xx_ocmcram_hwmod = {
-        .name           = "ocmcram",
-        .class          = &am33xx_ocmcram_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
 /* ocpwp */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
        .name           = "ocpwp",
@@ -570,6 +552,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
 #endif
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
        .name           = "smartreflex",
@@ -783,9 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
        },
 };
-/*
+/* pwmss  */
- * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
- */
 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
        .rev_offs       = 0x0,
        .sysc_offs      = 0x4,
@@ -801,18 +800,23 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
        .sysc           = &am33xx_epwmss_sysc,
 };
-/* ehrpwm0 */
+static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+        .name           = "ecap",
-        { .name = "int", .irq = 86 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
-        { .irq = -1 },
 };
-static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
-        .name           = "ehrpwm0",
+        .name           = "eqep",
+};
+static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
+        .name           = "ehrpwm",
+};
+/* epwmss0 */
+static struct omap_hwmod am33xx_epwmss0_hwmod = {
+        .name           = "epwmss0",
        .class          = &am33xx_epwmss_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm0_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
@@ -822,63 +826,58 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
        },
 };
-/* ehrpwm1 */
+/* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-        { .name = "int", .irq = 87 + OMAP_INTC_START, },
+        { .irq = 31 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
        { .irq = -1 },
 };
-static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+static struct omap_hwmod am33xx_ecap0_hwmod = {
-        .name           = "ehrpwm1",
+        .name           = "ecap0",
-        .class          = &am33xx_epwmss_hwmod_class,
+        .class          = &am33xx_ecap_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm1_irqs,
+        .mpu_irqs       = am33xx_ecap0_irqs,
        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
 };
-/* ehrpwm2 */
+/* eqep0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
-        { .name = "int", .irq = 39 + OMAP_INTC_START, },
+        { .irq = 79 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
        { .irq = -1 },
 };
-static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+static struct omap_hwmod am33xx_eqep0_hwmod = {
-        .name           = "ehrpwm2",
+        .name           = "eqep0",
-        .class          = &am33xx_epwmss_hwmod_class,
+        .class          = &am33xx_eqep_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm2_irqs,
+        .mpu_irqs       = am33xx_eqep0_irqs,
        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
 };
-/* ecap0 */
+/* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-        { .irq = 31 + OMAP_INTC_START, },
+        { .name = "int", .irq = 86 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
        { .irq = -1 },
 };
-static struct omap_hwmod am33xx_ecap0_hwmod = {
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
-        .name           = "ecap0",
+        .name           = "ehrpwm0",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm0_irqs,
+        .main_clk       = "l4ls_gclk",
+};
+/* epwmss1 */
+static struct omap_hwmod am33xx_epwmss1_hwmod = {
+        .name           = "epwmss1",
        .class          = &am33xx_epwmss_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap0_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -892,13 +891,50 @@ static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
 static struct omap_hwmod am33xx_ecap1_hwmod = {
        .name           = "ecap1",
-        .class          = &am33xx_epwmss_hwmod_class,
+        .class          = &am33xx_ecap_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
        .mpu_irqs       = am33xx_ecap1_irqs,
        .main_clk       = "l4ls_gclk",
+};
+/* eqep1 */
+static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
+        { .irq = 88 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_eqep1_hwmod = {
+        .name           = "eqep1",
+        .class          = &am33xx_eqep_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_eqep1_irqs,
+        .main_clk       = "l4ls_gclk",
+};
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+        { .name = "int", .irq = 87 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+        .name           = "ehrpwm1",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm1_irqs,
+        .main_clk       = "l4ls_gclk",
+};
+/* epwmss2 */
+static struct omap_hwmod am33xx_epwmss2_hwmod = {
+        .name           = "epwmss2",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -912,16 +948,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
 static struct omap_hwmod am33xx_ecap2_hwmod = {
        .name           = "ecap2",
+        .class          = &am33xx_ecap_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
        .mpu_irqs       = am33xx_ecap2_irqs,
-        .class          = &am33xx_epwmss_hwmod_class,
+        .main_clk       = "l4ls_gclk",
+};
+/* eqep2 */
+static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
+        { .irq = 89 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_eqep2_hwmod = {
+        .name           = "eqep2",
+        .class          = &am33xx_eqep_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_eqep2_irqs,
+        .main_clk       = "l4ls_gclk",
+};
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+        { .name = "int", .irq = 39 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+        .name           = "ehrpwm2",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm2_irqs,
        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
 };
 /*
@@ -1824,6 +1883,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
        .class          = &am33xx_tptc_hwmod_class,
        .clkdm_name     = "l3_clkdm",
        .mpu_irqs       = am33xx_tptc0_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
        .main_clk       = "l3_gclk",
        .prcm           = {
                .omap4  = {
@@ -2496,7 +2556,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
        {
                .pa_start       = 0x4a100000,
                .pa_end         = 0x4a100000 + SZ_2K - 1,
-                .flags          = ADDR_TYPE_RT,
        },
        /* cpsw wr */
        {
@@ -2547,162 +2606,202 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
        .user           = OCP_USER_MPU,
 };
-/*
+static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
        {
                .pa_start       = 0x48300000,
                .pa_end         = 0x48300000 + SZ_16 - 1,
                .flags          = ADDR_TYPE_RT
        },
-        {
-                .pa_start       = 0x48300200,
-                .pa_end         = 0x48300200 + SZ_256 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_ehrpwm0_hwmod,
+        .slave          = &am33xx_epwmss0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm0_addr_space,
+        .addr           = am33xx_epwmss0_addr_space,
        .user           = OCP_USER_MPU,
 };
-/*
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-        {
-                .pa_start       = 0x48302000,
-                .pa_end         = 0x48302000 + SZ_16 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
        {
-                .pa_start       = 0x48302200,
+                .pa_start       = 0x48300100,
-                .pa_end         = 0x48302200 + SZ_256 - 1,
+                .pa_end         = 0x48300100 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
-        .master         = &am33xx_l4_ls_hwmod,
+        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_ehrpwm1_hwmod,
+        .slave          = &am33xx_ecap0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm1_addr_space,
+        .addr           = am33xx_ecap0_addr_space,
        .user           = OCP_USER_MPU,
 };
-/*
+static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
        {
-                .pa_start       = 0x48304000,
+                .pa_start       = 0x48300180,
-                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .pa_end         = 0x48300180 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .pa_start       = 0x48304200,
-                .pa_end         = 0x48304200 + SZ_256 - 1,
-                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
-        .master         = &am33xx_l4_ls_hwmod,
+        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_ehrpwm2_hwmod,
+        .slave          = &am33xx_eqep0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm2_addr_space,
+        .addr           = am33xx_eqep0_addr_space,
        .user           = OCP_USER_MPU,
 };
-/*
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
-        {
-                .pa_start       = 0x48300000,
-                .pa_end         = 0x48300000 + SZ_16 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
        {
-                .pa_start       = 0x48300100,
+                .pa_start       = 0x48300200,
-                .pa_end         = 0x48300100 + SZ_256 - 1,
+                .pa_end         = 0x48300200 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
-        .master         = &am33xx_l4_ls_hwmod,
+        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_ecap0_hwmod,
+        .slave          = &am33xx_ehrpwm0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap0_addr_space,
+        .addr           = am33xx_ehrpwm0_addr_space,
        .user           = OCP_USER_MPU,
 };
-/*
- * Splitting the resources to handle access of PWMSS config space
+static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
        {
                .pa_start       = 0x48302000,
                .pa_end         = 0x48302000 + SZ_16 - 1,
                .flags          = ADDR_TYPE_RT
        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_epwmss1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_epwmss1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
        {
                .pa_start       = 0x48302100,
-                .pa_end         = 0x48302100 + SZ_256 - 1,
+                .pa_end         = 0x48302100 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
-        .master         = &am33xx_l4_ls_hwmod,
+        .master         = &am33xx_epwmss1_hwmod,
        .slave          = &am33xx_ecap1_hwmod,
        .clk            = "l4ls_gclk",
        .addr           = am33xx_ecap1_addr_space,
        .user           = OCP_USER_MPU,
 };
-/*
+static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
- * Splitting the resources to handle access of PWMSS config space
+        {
- * and module specific part independently
+                .pa_start       = 0x48302180,
- */
+                .pa_end         = 0x48302180 + SZ_128 - 1,
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
+        .master         = &am33xx_epwmss1_hwmod,
+        .slave          = &am33xx_eqep1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_eqep1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+        {
+                .pa_start       = 0x48302200,
+                .pa_end         = 0x48302200 + SZ_128 - 1,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
+        .master         = &am33xx_epwmss1_hwmod,
+        .slave          = &am33xx_ehrpwm1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
        {
                .pa_start       = 0x48304000,
                .pa_end         = 0x48304000 + SZ_16 - 1,
                .flags          = ADDR_TYPE_RT
        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_epwmss2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_epwmss2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
        {
                .pa_start       = 0x48304100,
-                .pa_end         = 0x48304100 + SZ_256 - 1,
+                .pa_end         = 0x48304100 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
-        .master         = &am33xx_l4_ls_hwmod,
+        .master         = &am33xx_epwmss2_hwmod,
        .slave          = &am33xx_ecap2_hwmod,
        .clk            = "l4ls_gclk",
        .addr           = am33xx_ecap2_addr_space,
        .user           = OCP_USER_MPU,
 };
+static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
+        {
+                .pa_start       = 0x48304180,
+                .pa_end         = 0x48304180 + SZ_128 - 1,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
+        .master         = &am33xx_epwmss2_hwmod,
+        .slave          = &am33xx_eqep2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_eqep2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+        {
+                .pa_start       = 0x48304200,
+                .pa_end         = 0x48304200 + SZ_128 - 1,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
+        .master         = &am33xx_epwmss2_hwmod,
+        .slave          = &am33xx_ehrpwm2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm2_addr_space,
+        .user           = OCP_USER_MPU,
+};
 /* l3s cfg -> gpmc */
 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
        {
@@ -3328,6 +3427,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
        .flags          = OCPIF_SWSUP_IDLE,
 };
+/* l3 main -> ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_ocmcram_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_fw__emif_fw,
        &am33xx_l3_main__emif,
@@ -3385,12 +3491,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_ls__uart6,
        &am33xx_l4_ls__spinlock,
        &am33xx_l4_ls__elm,
-        &am33xx_l4_ls__ehrpwm0,
+        &am33xx_l4_ls__epwmss0,
-        &am33xx_l4_ls__ehrpwm1,
+        &am33xx_epwmss0__ecap0,
-        &am33xx_l4_ls__ehrpwm2,
+        &am33xx_epwmss0__eqep0,
-        &am33xx_l4_ls__ecap0,
+        &am33xx_epwmss0__ehrpwm0,
-        &am33xx_l4_ls__ecap1,
+        &am33xx_l4_ls__epwmss1,
-        &am33xx_l4_ls__ecap2,
+        &am33xx_epwmss1__ecap1,
+        &am33xx_epwmss1__eqep1,
+        &am33xx_epwmss1__ehrpwm1,
+        &am33xx_l4_ls__epwmss2,
+        &am33xx_epwmss2__ecap2,
+        &am33xx_epwmss2__eqep2,
+        &am33xx_epwmss2__ehrpwm2,
        &am33xx_l3_s__gpmc,
        &am33xx_l3_main__lcdc,
        &am33xx_l4_ls__mcspi0,
@@ -3398,6 +3510,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__tptc0,
        &am33xx_l3_main__tptc1,
        &am33xx_l3_main__tptc2,
+        &am33xx_l3_main__ocmc,
        &am33xx_l3_s__usbss,
        &am33xx_l4_hs__cpgmac0,
        &am33xx_cpgmac0__mdio,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8bb2628df34e..ac7e03ec952f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3493,7 +3493,12 @@ static struct omap_hwmod am35xx_emac_hwmod = {
        .name           = "davinci_emac",
        .mpu_irqs       = am35xx_emac_mpu_irqs,
        .class          = &am35xx_emac_class,
-        .flags          = HWMOD_NO_IDLEST,
+        /*
+         * According to Mark Greer, the MPU will not return from WFI
+         * when the EMAC signals an interrupt.
+         * http://www.spinics.net/lists/arm-kernel/msg174734.html
+         */
+        .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
 };
 /* l3_core -> davinci emac interface */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 793f54ac7d14..0e47d2e1687c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -322,6 +322,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
        .name   = "aess",
        .sysc   = &omap44xx_aess_sysc,
+        .enable_preprogram = omap_hwmod_aess_preprogram,
 };
 /* aess */
@@ -348,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_aess_irqs,
        .sdma_reqs      = omap44xx_aess_sdma_reqs,
-        .main_clk       = "aess_fck",
+        .main_clk       = "aess_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
@@ -616,7 +617,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_dmic_irqs,
        .sdma_reqs      = omap44xx_dmic_sdma_reqs,
-        .main_clk       = "dmic_fck",
+        .main_clk       = "func_dmic_abe_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
@@ -1161,7 +1162,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .mpu_irqs       = omap44xx_gpio1_irqs,
-        .main_clk       = "gpio1_ick",
+        .main_clk       = "l4_wkup_clk_mux_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
@@ -1190,7 +1191,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_gpio2_irqs,
-        .main_clk       = "gpio2_ick",
+        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -1219,7 +1220,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_gpio3_irqs,
-        .main_clk       = "gpio3_ick",
+        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -1248,7 +1249,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_gpio4_irqs,
-        .main_clk       = "gpio4_ick",
+        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -1277,7 +1278,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_gpio5_irqs,
-        .main_clk       = "gpio5_ick",
+        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -1306,7 +1307,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .mpu_irqs       = omap44xx_gpio6_irqs,
-        .main_clk       = "gpio6_ick",
+        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -1405,7 +1406,7 @@ static struct omap_hwmod omap44xx_gpu_hwmod = {
        .class          = &omap44xx_gpu_hwmod_class,
        .clkdm_name     = "l3_gfx_clkdm",
        .mpu_irqs       = omap44xx_gpu_irqs,
-        .main_clk       = "gpu_fck",
+        .main_clk       = "sgx_clk_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
@@ -1446,7 +1447,7 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
        .mpu_irqs       = omap44xx_hdq1w_irqs,
-        .main_clk       = "hdq1w_fck",
+        .main_clk       = "func_12m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
@@ -1550,7 +1551,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c1_irqs,
        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
-        .main_clk       = "i2c1_fck",
+        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -1580,7 +1581,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c2_irqs,
        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
-        .main_clk       = "i2c2_fck",
+        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -1610,7 +1611,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c3_irqs,
        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
-        .main_clk       = "i2c3_fck",
+        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -1640,7 +1641,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c4_irqs,
        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
-        .main_clk       = "i2c4_fck",
+        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -1743,7 +1744,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
        .clkdm_name     = "iss_clkdm",
        .mpu_irqs       = omap44xx_iss_irqs,
        .sdma_reqs      = omap44xx_iss_sdma_reqs,
-        .main_clk       = "iss_fck",
+        .main_clk       = "ducati_clk_mux_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
@@ -1785,7 +1786,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
        .mpu_irqs       = omap44xx_iva_irqs,
        .rst_lines      = omap44xx_iva_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
-        .main_clk       = "iva_fck",
+        .main_clk       = "dpll_iva_m5x2_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
@@ -1829,7 +1830,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
        .class          = &omap44xx_kbd_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .mpu_irqs       = omap44xx_kbd_irqs,
-        .main_clk       = "kbd_fck",
+        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
@@ -1920,7 +1921,7 @@ static struct omap_hwmod omap44xx_mcasp_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_mcasp_irqs,
        .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
-        .main_clk       = "mcasp_fck",
+        .main_clk       = "func_mcasp_abe_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
@@ -1972,7 +1973,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_mcbsp1_irqs,
        .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
-        .main_clk       = "mcbsp1_fck",
+        .main_clk       = "func_mcbsp1_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
@@ -2007,7 +2008,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_mcbsp2_irqs,
        .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
-        .main_clk       = "mcbsp2_fck",
+        .main_clk       = "func_mcbsp2_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
@@ -2042,7 +2043,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_mcbsp3_irqs,
        .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
-        .main_clk       = "mcbsp3_fck",
+        .main_clk       = "func_mcbsp3_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
@@ -2077,7 +2078,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mcbsp4_irqs,
        .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
-        .main_clk       = "mcbsp4_fck",
+        .main_clk       = "per_mcbsp4_gfclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
@@ -2140,7 +2141,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
        .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
        .mpu_irqs       = omap44xx_mcpdm_irqs,
        .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
-        .main_clk       = "mcpdm_fck",
+        .main_clk       = "pad_clks_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
@@ -2201,7 +2202,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mcspi1_irqs,
        .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -2237,7 +2238,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mcspi2_irqs,
        .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -2273,7 +2274,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mcspi3_irqs,
        .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
-        .main_clk       = "mcspi3_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -2307,7 +2308,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mcspi4_irqs,
        .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
-        .main_clk       = "mcspi4_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -2363,7 +2364,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
        .clkdm_name     = "l3_init_clkdm",
        .mpu_irqs       = omap44xx_mmc1_irqs,
        .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
-        .main_clk       = "mmc1_fck",
+        .main_clk       = "hsmmc1_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -2392,7 +2393,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
        .clkdm_name     = "l3_init_clkdm",
        .mpu_irqs       = omap44xx_mmc2_irqs,
        .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
-        .main_clk       = "mmc2_fck",
+        .main_clk       = "hsmmc2_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -2420,7 +2421,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mmc3_irqs,
        .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
-        .main_clk       = "mmc3_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
@@ -2448,7 +2449,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mmc4_irqs,
        .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
-        .main_clk       = "mmc4_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
@@ -2476,7 +2477,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mmc5_irqs,
        .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
-        .main_clk       = "mmc5_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
@@ -2702,13 +2703,6 @@ static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
                .end            = 0x4a0ae000,
                .flags          = IORESOURCE_MEM,
        },
-        {
-                /* XXX: Remove this once control module driver is in place */
-                .name           = "ctrl_dev",
-                .start          = 0x4a002300,
-                .end            = 0x4a002303,
-                .flags          = IORESOURCE_MEM,
-        },
        { }
 };
@@ -2725,7 +2719,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
        .name           = "ocp2scp_usb_phy",
        .class          = &omap44xx_ocp2scp_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "ocp2scp_usb_phy_phy_48m",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -3162,7 +3156,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
        .clkdm_name     = "l4_wkup_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer1_irqs,
-        .main_clk       = "timer1_fck",
+        .main_clk       = "dmt1_clk_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
@@ -3185,7 +3179,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer2_irqs,
-        .main_clk       = "timer2_fck",
+        .main_clk       = "cm2_dm2_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
@@ -3206,7 +3200,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_timer3_irqs,
-        .main_clk       = "timer3_fck",
+        .main_clk       = "cm2_dm3_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
@@ -3227,7 +3221,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_timer4_irqs,
-        .main_clk       = "timer4_fck",
+        .main_clk       = "cm2_dm4_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
@@ -3248,7 +3242,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_timer5_irqs,
-        .main_clk       = "timer5_fck",
+        .main_clk       = "timer5_sync_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
@@ -3270,8 +3264,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_timer6_irqs,
+        .main_clk       = "timer6_sync_mux",
-        .main_clk       = "timer6_fck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
@@ -3293,7 +3286,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_timer7_irqs,
-        .main_clk       = "timer7_fck",
+        .main_clk       = "timer7_sync_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
@@ -3315,7 +3308,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_timer8_irqs,
-        .main_clk       = "timer8_fck",
+        .main_clk       = "timer8_sync_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
@@ -3337,7 +3330,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_timer9_irqs,
-        .main_clk       = "timer9_fck",
+        .main_clk       = "cm2_dm9_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
@@ -3360,7 +3353,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer10_irqs,
-        .main_clk       = "timer10_fck",
+        .main_clk       = "cm2_dm10_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
@@ -3382,7 +3375,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_timer11_irqs,
-        .main_clk       = "timer11_fck",
+        .main_clk       = "cm2_dm11_mux",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
@@ -3433,7 +3426,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_uart1_irqs,
        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -3461,7 +3454,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_uart2_irqs,
        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -3490,7 +3483,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
        .mpu_irqs       = omap44xx_uart3_irqs,
        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -3518,7 +3511,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_uart4_irqs,
        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
-        .main_clk       = "uart4_fck",
+        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -3797,7 +3790,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
        .class          = &omap44xx_wd_timer_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .mpu_irqs       = omap44xx_wd_timer2_irqs,
-        .main_clk       = "wd_timer2_fck",
+        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
@@ -3818,7 +3811,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
        .class          = &omap44xx_wd_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
        .mpu_irqs       = omap44xx_wd_timer3_irqs,
-        .main_clk       = "wd_timer3_fck",
+        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
@@ -4249,6 +4242,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
        {
+                .name           = "dmem",
+                .pa_start       = 0x40180000,
+                .pa_end         = 0x4018ffff
+        },
+        {
+                .name           = "cmem",
+                .pa_start       = 0x401a0000,
+                .pa_end         = 0x401a1fff
+        },
+        {
+                .name           = "smem",
+                .pa_start       = 0x401c0000,
+                .pa_end         = 0x401c5fff
+        },
+        {
+                .name           = "pmem",
+                .pa_start       = 0x401e0000,
+                .pa_end         = 0x401e1fff
+        },
+        {
+                .name           = "mpu",
                .pa_start       = 0x401f1000,
                .pa_end         = 0x401f13ff,
                .flags          = ADDR_TYPE_RT
@@ -4267,6 +4281,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
        {
+                .name           = "dmem_dma",
+                .pa_start       = 0x49080000,
+                .pa_end         = 0x4908ffff
+        },
+        {
+                .name           = "cmem_dma",
+                .pa_start       = 0x490a0000,
+                .pa_end         = 0x490a1fff
+        },
+        {
+                .name           = "smem_dma",
+                .pa_start       = 0x490c0000,
+                .pa_end         = 0x490c5fff
+        },
+        {
+                .name           = "pmem_dma",
+                .pa_start       = 0x490e0000,
+                .pa_end         = 0x490e1fff
+        },
+        {
+                .name           = "dma",
                .pa_start       = 0x490f1000,
                .pa_end         = 0x490f13ff,
                .flags          = ADDR_TYPE_RT
@@ -6156,12 +6191,6 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
                .pa_end         = 0x4a0ab7ff,
                .flags          = ADDR_TYPE_RT
        },
-        {
-                /* XXX: Remove this once control module driver is in place */
-                .pa_start       = 0x4a00233c,
-                .pa_end         = 0x4a00233f,
-                .flags          = ADDR_TYPE_RT
-        },
        { }
 };
@@ -6282,7 +6311,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l3_main_1__l3_main_3,
        &omap44xx_l3_main_2__l3_main_3,
        &omap44xx_l4_cfg__l3_main_3,
-        /* &omap44xx_aess__l4_abe, */
+        &omap44xx_aess__l4_abe,
        &omap44xx_dsp__l4_abe,
        &omap44xx_l3_main_1__l4_abe,
        &omap44xx_mpu__l4_abe,
@@ -6291,8 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_cfg__l4_wkup,
        &omap44xx_mpu__mpu_private,
        &omap44xx_l4_cfg__ocp_wp_noc,
-        /* &omap44xx_l4_abe__aess, */
+        &omap44xx_l4_abe__aess,
-        /* &omap44xx_l4_abe__aess_dma, */
+        &omap44xx_l4_abe__aess_dma,
        &omap44xx_l3_main_2__c2c,
        &omap44xx_l4_wkup__counter_32k,
        &omap44xx_l4_cfg__ctrl_module_core,
diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c
new file mode 100644
index 000000000000..65e186c9df55
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_reset.c
@@ -0,0 +1,53 @@
+/*
+ * OMAP IP block custom reset and preprogramming stubs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * A small number of IP blocks need custom reset and preprogramming
+ * functions.  The stubs in this file provide a standard way for the
+ * hwmod code to call these functions, which are to be located under
+ * drivers/.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <sound/aess.h>
+#include "omap_hwmod.h"
+/**
+ * omap_hwmod_aess_preprogram - enable AESS internal autogating
+ * @oh: struct omap_hwmod *
+ *
+ * The AESS will not IdleAck to the PRCM until its internal autogating
+ * is enabled.  Since internal autogating is disabled by default after
+ * AESS reset, we must enable autogating after the hwmod code resets
+ * the AESS.  Returns 0.
+ */
+int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
+{
+        void __iomem *va;
+        va = omap_hwmod_get_mpu_rt_va(oh);
+        if (!va)
+                return -EINVAL;
+        aess_enable_autogating(va);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index e237602e10ea..eb8a25de67ed 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -63,7 +63,7 @@ static int __init omap4430_phy_power_down(void)
        return 0;
 }
-early_initcall(omap4430_phy_power_down);
+omap_early_initcall(omap4430_phy_power_down);
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 62772e0e0d69..fc67add76444 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -168,4 +168,4 @@ int __init omap3_opp_init(void)
        return r;
 }
-device_initcall(omap3_opp_init);
+omap_device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d470b728e720..1ef7a3e5ce4a 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -177,4 +177,4 @@ int __init omap4_opp_init(void)
                        ARRAY_SIZE(omap446x_opp_def_list));
        return r;
 }
-device_initcall(omap4_opp_init);
+omap_device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index e2c291f52f92..1edd000a8143 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -83,10 +83,8 @@ static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
                strncmp(clkdm->name, "dpll", 4) == 0)
                return 0;
-        seq_printf(s, "%s->%s (%d)", clkdm->name,
+        seq_printf(s, "%s->%s (%d)\n", clkdm->name, clkdm->pwrdm.ptr->name,
-                        clkdm->pwrdm.ptr->name,
+                   clkdm->usecount);
-                        atomic_read(&clkdm->usecount));
-        seq_printf(s, "\n");
        return 0;
 }
@@ -279,6 +277,6 @@ static int __init pm_dbg_init(void)
        return 0;
 }
-arch_initcall(pm_dbg_init);
+omap_arch_initcall(pm_dbg_init);
 #endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index f4b3143a8b1d..673a4c1d1d76 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -32,8 +32,6 @@
 #include "pm.h"
 #include "twl-common.h"
-static struct omap_device_pm_latency *pm_lats;
 /*
 * omap_pm_suspend: points to a function that does the SoC-specific
 * suspend work
@@ -82,7 +80,7 @@ static int __init _init_omap_device(char *name)
                 __func__, name))
                return -ENODEV;
-        pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
+        pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
        if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
                 __func__, name))
                return -ENODEV;
@@ -108,80 +106,19 @@ static void __init omap2_init_processor_devices(void)
        }
 }
-/* Types of sleep_switch used in omap_set_pwrdm_state */
-#define FORCEWAKEUP_SWITCH      0
-#define LOWPOWERSTATE_SWITCH    1
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
+        /* XXX The usecount test is racy */
        if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
            !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
                clkdm_allow_idle(clkdm);
        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                 atomic_read(&clkdm->usecount) == 0)
+                 clkdm->usecount == 0)
                clkdm_sleep(clkdm);
        return 0;
 }
 /*
- * This sets pwrdm state (other than mpu & core. Currently only ON &
- * RET are supported.
- */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
-{
-        u8 curr_pwrst, next_pwrst;
-        int sleep_switch = -1, ret = 0, hwsup = 0;
-        if (!pwrdm || IS_ERR(pwrdm))
-                return -EINVAL;
-        while (!(pwrdm->pwrsts & (1 << pwrst))) {
-                if (pwrst == PWRDM_POWER_OFF)
-                        return ret;
-                pwrst--;
-        }
-        next_pwrst = pwrdm_read_next_pwrst(pwrdm);
-        if (next_pwrst == pwrst)
-                return ret;
-        curr_pwrst = pwrdm_read_pwrst(pwrdm);
-        if (curr_pwrst < PWRDM_POWER_ON) {
-                if ((curr_pwrst > pwrst) &&
-                        (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
-                        sleep_switch = LOWPOWERSTATE_SWITCH;
-                } else {
-                        hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
-                        clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                        sleep_switch = FORCEWAKEUP_SWITCH;
-                }
-        }
-        ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
-        if (ret)
-                pr_err("%s: unable to set power state of powerdomain: %s\n",
-                       __func__, pwrdm->name);
-        switch (sleep_switch) {
-        case FORCEWAKEUP_SWITCH:
-                if (hwsup)
-                        clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
-                else
-                        clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
-                break;
-        case LOWPOWERSTATE_SWITCH:
-                pwrdm_set_lowpwrstchange(pwrdm);
-                pwrdm_wait_transition(pwrdm);
-                pwrdm_state_switch(pwrdm);
-                break;
-        }
-        return ret;
-}
-/*
 * This API is to be called during init to set the various voltage
 * domains to the voltage as per the opp table. Typically we boot up
 * at the nominal voltage. So this function finds out the rate of
@@ -336,7 +273,7 @@ static int __init omap2_common_pm_init(void)
        return 0;
 }
-postcore_initcall(omap2_common_pm_init);
+omap_postcore_initcall(omap2_common_pm_init);
 int __init omap2_common_pm_late_init(void)
 {
@@ -345,19 +282,19 @@ int __init omap2_common_pm_late_init(void)
         * a completely different mechanism.
         * Disable this part if a DT blob is available.
         */
-        if (of_have_populated_dt())
+        if (!of_have_populated_dt()) {
-                return 0;
-        /* Init the voltage layer */
+                /* Init the voltage layer */
-        omap_pmic_late_init();
+                omap_pmic_late_init();
-        omap_voltage_late_init();
+                omap_voltage_late_init();
-        /* Initialize the voltages */
+                /* Initialize the voltages */
-        omap3_init_voltages();
+                omap3_init_voltages();
-        omap4_init_voltages();
+                omap4_init_voltages();
-        /* Smartreflex device init */
+                /* Smartreflex device init */
-        omap_devinit_smartreflex();
+                omap_devinit_smartreflex();
+        }
 #ifdef CONFIG_SUSPEND
        suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index c22503b17abd..7bdd22afce69 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,7 +33,6 @@ static inline int omap4_idle_init(void)
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
-extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index c333fa6dffa8..b59d93908341 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -54,7 +54,6 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
-static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                  void __iomem *sdrc_power);
@@ -90,11 +89,7 @@ static int omap2_enter_full_retention(void)
        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
        omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
-        /*
+        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
-         * Set MPU powerdomain's next power state to RETENTION;
-         * preserve logic state during retention
-         */
-        pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
        /* Workaround to kill USB */
@@ -137,15 +132,10 @@ no_sleep:
        /* Mask future PRCM-to-MPU interrupts */
        omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
-        return 0;
+        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
-}
+        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
-static int omap2_i2c_active(void)
-{
-        u32 l;
-        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        return 0;
-        return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 }
 static int sti_console_enabled;
@@ -172,10 +162,7 @@ static int omap2_allow_mpu_retention(void)
 static void omap2_enter_mpu_retention(void)
 {
-        /* Putting MPU into the WFI state while a transfer is active
+        const int zero = 0;
-         * seems to cause the I2C block to timeout. Why? Good question. */
-        if (omap2_i2c_active())
-                return;
        /* The peripherals seem not to be able to wake up the MPU when
         * it is in retention mode. */
@@ -186,17 +173,17 @@ static void omap2_enter_mpu_retention(void)
                omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
                /* Try to enter MPU retention */
-                omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+                pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
-                                  OMAP_LOGICRETSTATE_MASK,
-                                  MPU_MOD, OMAP2_PM_PWSTCTRL);
        } else {
                /* Block MPU retention */
+                pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
-                omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
-                                                 OMAP2_PM_PWSTCTRL);
        }
-        omap2_sram_idle();
+        /* WFI */
+        asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
+        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 }
 static int omap2_can_sleep(void)
@@ -251,25 +238,17 @@ static void __init prcm_setup_regs(void)
        for (i = 0; i < num_mem_banks; i++)
                pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
-        /* Set CORE powerdomain's next power state to RETENTION */
+        pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
-        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
-        /*
-         * Set MPU powerdomain's next power state to RETENTION;
-         * preserve logic state during retention
-         */
        pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
-        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
        /* Force-power down DSP, GFX powerdomains */
        pwrdm = clkdm_get_pwrdm(dsp_clkdm);
        pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-        clkdm_sleep(dsp_clkdm);
        pwrdm = clkdm_get_pwrdm(gfx_clkdm);
        pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-        clkdm_sleep(gfx_clkdm);
        /* Enable hardware-supervised idle for all clkdms */
        clkdm_for_each(omap_pm_clkdms_setup, NULL);
@@ -356,11 +335,9 @@ int __init omap2_pm_init(void)
        /*
         * We copy the assembler sleep/wakeup routines to SRAM.
         * These routines need to be in SRAM as that's the only
-         * memory the MPU can see when it wakes up.
+         * memory the MPU can see when it wakes up after the entire
+         * chip enters idle.
         */
-        omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
-                                         omap24xx_idle_loop_suspend_sz);
        omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
                                            omap24xx_cpu_suspend_sz);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7be3622cfc85..2d93d8b23835 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -351,12 +351,10 @@ static void omap3_pm_idle(void)
        if (omap_irq_pending())
                goto out;
-        trace_power_start(POWER_CSTATE, 1, smp_processor_id());
        trace_cpu_idle(1, smp_processor_id());
        omap_sram_idle();
-        trace_power_end(smp_processor_id());
        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 out:
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index aa6fd98f606e..ea62e75ef21d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -77,10 +77,20 @@ static int omap4_pm_suspend(void)
                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
                pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
        }
-        if (ret)
+        if (ret) {
                pr_crit("Could not enter target state in pm_suspend\n");
-        else
+                /*
+                 * OMAP4 chip PM currently works only with certain (newer)
+                 * versions of bootloaders. This is due to missing code in the
+                 * kernel to properly reset and initialize some devices.
+                 * Warn the user about the bootloader version being one of the
+                 * possible causes.
+                 * http://www.spinics.net/lists/arm-kernel/msg218641.html
+                 */
+                pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
+        } else {
                pr_info("Successfully put all powerdomains to target state\n");
+        }
        return 0;
 }
@@ -146,6 +156,13 @@ int __init omap4_pm_init(void)
        }
        pr_err("Power Management for TI OMAP4.\n");
+        /*
+         * OMAP4 chip PM currently works only with certain (newer)
+         * versions of bootloaders. This is due to missing code in the
+         * kernel to properly reset and initialize some devices.
+         * http://www.spinics.net/lists/arm-kernel/msg218641.html
+         */
+        pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
        ret = pwrdm_for_each(pwrdms_setup, NULL);
        if (ret) {
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index eb78ae7a3464..9debf822687c 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -48,8 +48,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
                }
        }
-        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0,
+        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0);
-                                            NULL, 0, 0);
        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
             dev_name);
@@ -89,4 +88,4 @@ static int __init omap_init_pmu(void)
        return omap2_init_pmu(oh_num, oh_names);
 }
-subsys_initcall(omap_init_pmu);
+omap_subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index dea62a9aad07..8e61d80bf6b3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/string.h>
+#include <linux/spinlock.h>
 #include <trace/events/power.h>
 #include "cm2xxx_3xxx.h"
@@ -42,6 +43,16 @@ enum {
        PWRDM_STATE_PREV,
 };
+/*
+ * Types of sleep_switch used internally in omap_set_pwrdm_state()
+ * and its associated static functions
+ *
+ * XXX Better documentation is needed here
+ */
+#define ALREADYACTIVE_SWITCH            0
+#define FORCEWAKEUP_SWITCH              1
+#define LOWPOWERSTATE_SWITCH            2
+#define ERROR_SWITCH                    3
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
@@ -101,6 +112,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        pwrdm->voltdm.ptr = voltdm;
        INIT_LIST_HEAD(&pwrdm->voltdm_node);
        voltdm_add_pwrdm(voltdm, pwrdm);
+        spin_lock_init(&pwrdm->_lock);
        list_add(&pwrdm->node, &pwrdm_list);
@@ -112,7 +124,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        for (i = 0; i < pwrdm->banks; i++)
                pwrdm->ret_mem_off_counter[i] = 0;
-        pwrdm_wait_transition(pwrdm);
+        arch_pwrdm->pwrdm_wait_transition(pwrdm);
        pwrdm->state = pwrdm_read_pwrst(pwrdm);
        pwrdm->state_counter[pwrdm->state] = 1;
@@ -143,7 +155,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
 static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 {
-        int prev, state, trace_state = 0;
+        int prev, next, state, trace_state = 0;
        if (pwrdm == NULL)
                return -EINVAL;
@@ -164,9 +176,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
                 * If the power domain did not hit the desired state,
                 * generate a trace event with both the desired and hit states
                 */
-                if (state != prev) {
+                next = pwrdm_read_next_pwrst(pwrdm);
+                if (next != prev) {
                        trace_state = (PWRDM_TRACE_STATES_FLAG |
-                                       ((state & OMAP_POWERSTATE_MASK) << 8) |
+                                       ((next & OMAP_POWERSTATE_MASK) << 8) |
                                       ((prev & OMAP_POWERSTATE_MASK) << 0));
                        trace_power_domain_target(pwrdm->name, trace_state,
                                                  smp_processor_id());
@@ -199,6 +212,80 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
        return 0;
 }
+/**
+ * _pwrdm_save_clkdm_state_and_activate - prepare for power state change
+ * @pwrdm: struct powerdomain * to operate on
+ * @curr_pwrst: current power state of @pwrdm
+ * @pwrst: power state to switch to
+ * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised
+ *
+ * Determine whether the powerdomain needs to be turned on before
+ * attempting to switch power states.  Called by
+ * omap_set_pwrdm_state().  NOTE that if the powerdomain contains
+ * multiple clockdomains, this code assumes that the first clockdomain
+ * supports software-supervised wakeup mode - potentially a problem.
+ * Returns the power state switch mode currently in use (see the
+ * "Types of sleep_switch" comment above).
+ */
+static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
+                                               u8 curr_pwrst, u8 pwrst,
+                                               bool *hwsup)
+{
+        u8 sleep_switch;
+        if (curr_pwrst < 0) {
+                WARN_ON(1);
+                sleep_switch = ERROR_SWITCH;
+        } else if (curr_pwrst < PWRDM_POWER_ON) {
+                if (curr_pwrst > pwrst &&
+                    pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
+                    arch_pwrdm->pwrdm_set_lowpwrstchange) {
+                        sleep_switch = LOWPOWERSTATE_SWITCH;
+                } else {
+                        *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
+                        clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]);
+                        sleep_switch = FORCEWAKEUP_SWITCH;
+                }
+        } else {
+                sleep_switch = ALREADYACTIVE_SWITCH;
+        }
+        return sleep_switch;
+}
+/**
+ * _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change
+ * @pwrdm: struct powerdomain * to operate on
+ * @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate()
+ * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode?
+ *
+ * Restore the clockdomain state perturbed by
+ * _pwrdm_save_clkdm_state_and_activate(), and call the power state
+ * bookkeeping code.  Called by omap_set_pwrdm_state().  NOTE that if
+ * the powerdomain contains multiple clockdomains, this assumes that
+ * the first associated clockdomain supports either
+ * hardware-supervised idle control in the register, or
+ * software-supervised sleep.  No return value.
+ */
+static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm,
+                                       u8 sleep_switch, bool hwsup)
+{
+        switch (sleep_switch) {
+        case FORCEWAKEUP_SWITCH:
+                if (hwsup)
+                        clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
+                else
+                        clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]);
+                break;
+        case LOWPOWERSTATE_SWITCH:
+                if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
+                    arch_pwrdm->pwrdm_set_lowpwrstchange)
+                        arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
+                pwrdm_state_switch_nolock(pwrdm);
+                break;
+        }
+}
 /* Public functions */
 /**
@@ -275,6 +362,30 @@ int pwrdm_complete_init(void)
 }
 /**
+ * pwrdm_lock - acquire a Linux spinlock on a powerdomain
+ * @pwrdm: struct powerdomain * to lock
+ *
+ * Acquire the powerdomain spinlock on @pwrdm.  No return value.
+ */
+void pwrdm_lock(struct powerdomain *pwrdm)
+        __acquires(&pwrdm->_lock)
+{
+        spin_lock_irqsave(&pwrdm->_lock, pwrdm->_lock_flags);
+}
+/**
+ * pwrdm_unlock - release a Linux spinlock on a powerdomain
+ * @pwrdm: struct powerdomain * to unlock
+ *
+ * Release the powerdomain spinlock on @pwrdm.  No return value.
+ */
+void pwrdm_unlock(struct powerdomain *pwrdm)
+        __releases(&pwrdm->_lock)
+{
+        spin_unlock_irqrestore(&pwrdm->_lock, pwrdm->_lock_flags);
+}
+/**
 * pwrdm_lookup - look up a powerdomain by name, return a pointer
 * @name: name of powerdomain
 *
@@ -920,65 +1031,27 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
        return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
 }
-/**
+int pwrdm_state_switch_nolock(struct powerdomain *pwrdm)
- * pwrdm_set_lowpwrstchange - Request a low power state change
- * @pwrdm: struct powerdomain *
- *
- * Allows a powerdomain to transtion to a lower power sleep state
- * from an existing sleep state without waking up the powerdomain.
- * Returns -EINVAL if the powerdomain pointer is null or if the
- * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
- * upon success.
- */
-int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
-        int ret = -EINVAL;
-        if (!pwrdm)
-                return -EINVAL;
-        if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
-                return -EINVAL;
-        pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
-                 pwrdm->name);
-        if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
-                ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
-        return ret;
-}
-/**
- * pwrdm_wait_transition - wait for powerdomain power transition to finish
- * @pwrdm: struct powerdomain * to wait for
- *
- * If the powerdomain @pwrdm is in the process of a state transition,
- * spin until it completes the power transition, or until an iteration
- * bailout value is reached. Returns -EINVAL if the powerdomain
- * pointer is null, -EAGAIN if the bailout value was reached, or
- * returns 0 upon success.
- */
-int pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
-        int ret = -EINVAL;
+        int ret;
-        if (!pwrdm)
+        if (!pwrdm || !arch_pwrdm)
                return -EINVAL;
-        if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
+        ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
-                ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
+        if (!ret)
+                ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
        return ret;
 }
-int pwrdm_state_switch(struct powerdomain *pwrdm)
+int __deprecated pwrdm_state_switch(struct powerdomain *pwrdm)
 {
        int ret;
-        ret = pwrdm_wait_transition(pwrdm);
+        pwrdm_lock(pwrdm);
-        if (!ret)
+        ret = pwrdm_state_switch_nolock(pwrdm);
-                ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+        pwrdm_unlock(pwrdm);
        return ret;
 }
@@ -1004,6 +1077,61 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
 }
 /**
+ * omap_set_pwrdm_state - change a powerdomain's current power state
+ * @pwrdm: struct powerdomain * to change the power state of
+ * @pwrst: power state to change to
+ *
+ * Change the current hardware power state of the powerdomain
+ * represented by @pwrdm to the power state represented by @pwrst.
+ * Returns -EINVAL if @pwrdm is null or invalid or if the
+ * powerdomain's current power state could not be read, or returns 0
+ * upon success or if @pwrdm does not support @pwrst or any
+ * lower-power state.  XXX Should not return 0 if the @pwrdm does not
+ * support @pwrst or any lower-power state: this should be an error.
+ */
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u8 curr_pwrst, next_pwrst, sleep_switch;
+        int ret = 0;
+        bool hwsup = false;
+        if (!pwrdm || IS_ERR(pwrdm))
+                return -EINVAL;
+        while (!(pwrdm->pwrsts & (1 << pwrst))) {
+                if (pwrst == PWRDM_POWER_OFF)
+                        return ret;
+                pwrst--;
+        }
+        pwrdm_lock(pwrdm);
+        curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+        if (curr_pwrst == pwrst && next_pwrst == pwrst)
+                goto osps_out;
+        sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
+                                                            pwrst, &hwsup);
+        if (sleep_switch == ERROR_SWITCH) {
+                ret = -EINVAL;
+                goto osps_out;
+        }
+        ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
+        if (ret)
+                pr_err("%s: unable to set power state of powerdomain: %s\n",
+                       __func__, pwrdm->name);
+        _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup);
+osps_out:
+        pwrdm_unlock(pwrdm);
+        return ret;
+}
+/**
 * pwrdm_get_context_loss_count - get powerdomain's context loss count
 * @pwrdm: struct powerdomain * to wait for
 *
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 5277d56eb37f..140c36074fed 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -19,8 +19,7 @@
 #include <linux/types.h>
 #include <linux/list.h>
+#include <linux/spinlock.h>
-#include <linux/atomic.h>
 #include "voltage.h"
@@ -44,18 +43,20 @@
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | PWRSTS_ON)
-/* Powerdomain flags */
+/*
-#define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
+ * Powerdomain flags (struct powerdomain.flags)
-#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ *
-                                          * in MEM bank 1 position. This is
+ * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
-                                          * true for OMAP3430
+ *
-                                          */
+ * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
-#define PWRDM_HAS_LOWPOWERSTATECHANGE   (1 << 2) /*
+ * bank 1 position. This is true for OMAP3430
-                                                  * support to transition from a
+ *
-                                                  * sleep state to a lower sleep
+ * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
-                                                  * state without waking up the
+ * to a lower sleep state without waking up the powerdomain
-                                                  * powerdomain
+ */
-                                                  */
+#define PWRDM_HAS_HDWR_SAR              BIT(0)
+#define PWRDM_HAS_MPU_QUIRK             BIT(1)
+#define PWRDM_HAS_LOWPOWERSTATECHANGE   BIT(2)
 /*
 * Number of memory banks that are power-controllable.  On OMAP4430, the
@@ -103,6 +104,8 @@ struct powerdomain;
 * @state_counter:
 * @timer:
 * @state_timer:
+ * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
+ * @_lock_flags: stored flags when @_lock is taken
 *
 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
 */
@@ -127,7 +130,8 @@ struct powerdomain {
        unsigned state_counter[PWRDM_MAX_PWRSTS];
        unsigned ret_logic_off_counter;
        unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
+        spinlock_t _lock;
+        unsigned long _lock_flags;
        const u8 pwrstctrl_offs;
        const u8 pwrstst_offs;
        const u32 logicretstate_mask;
@@ -162,6 +166,16 @@ struct powerdomain {
 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
 * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ *
+ * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
+ * chips, a powerdomain's power state is not allowed to directly
+ * transition from one low-power state (e.g., CSWR) to another
+ * low-power state (e.g., OFF) without first waking up the
+ * powerdomain.  This wastes energy.  So OMAP4 chips support the
+ * ability to transition a powerdomain power state directly from one
+ * low-power state to another.  The function pointed to by
+ * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
+ * hardware powerdomain state machine to enable this feature.
 */
 struct pwrdm_ops {
        int     (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
@@ -225,15 +239,15 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_wait_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
 int pwrdm_state_switch(struct powerdomain *pwrdm);
 int pwrdm_pre_transition(struct powerdomain *pwrdm);
 int pwrdm_post_transition(struct powerdomain *pwrdm);
-int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
@@ -253,5 +267,7 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
 extern struct powerdomain wkup_omap2_pwrdm;
 extern struct powerdomain gfx_omap2_pwrdm;
+extern void pwrdm_lock(struct powerdomain *pwrdm);
+extern void pwrdm_unlock(struct powerdomain *pwrdm);
 #endif
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index d3a5399091ad..7b946f1005b1 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -54,12 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 struct powerdomain wkup_omap2_pwrdm = {
        .name           = "wkup_pwrdm",
        .prcm_offs      = WKUP_MOD,
        .pwrsts         = PWRSTS_ON,
-        .voltdm         = { .name = "wakeup" },
+        .voltdm         = { .name = "wakeup" },
 };
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index ba520d4f7c7b..578eef86fcf2 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -38,7 +38,7 @@ static struct powerdomain dsp_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain mpu_24xx_pwrdm = {
@@ -53,13 +53,14 @@ static struct powerdomain mpu_24xx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain core_24xx_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 3,
        .pwrsts_mem_ret   = {
                [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
@@ -71,7 +72,7 @@ static struct powerdomain core_24xx_pwrdm = {
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
                [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
@@ -93,7 +94,7 @@ static struct powerdomain mdm_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 /*
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 8b23d234fb55..f0e14e9efe5a 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -50,7 +50,7 @@ static struct powerdomain iva2_pwrdm = {
                [2] = PWRSTS_OFF_ON,
                [3] = PWRSTS_ON,
        },
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain mpu_3xxx_pwrdm = {
@@ -66,7 +66,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_OFF_ON,
        },
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain mpu_am35x_pwrdm = {
@@ -82,7 +82,7 @@ static struct powerdomain mpu_am35x_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,
        },
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 /*
@@ -109,7 +109,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
                [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain core_3xxx_es3_1_pwrdm = {
@@ -131,7 +131,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
                [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain core_am35x_pwrdm = {
@@ -148,7 +148,7 @@ static struct powerdomain core_am35x_pwrdm = {
                [0] = PWRSTS_ON, /* MEM1ONSTATE */
                [1] = PWRSTS_ON, /* MEM2ONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dss_pwrdm = {
@@ -163,7 +163,7 @@ static struct powerdomain dss_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dss_am35x_pwrdm = {
@@ -178,7 +178,7 @@ static struct powerdomain dss_am35x_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 /*
@@ -199,7 +199,7 @@ static struct powerdomain sgx_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain sgx_am35x_pwrdm = {
@@ -214,7 +214,7 @@ static struct powerdomain sgx_am35x_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain cam_pwrdm = {
@@ -229,7 +229,7 @@ static struct powerdomain cam_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain per_pwrdm = {
@@ -244,7 +244,7 @@ static struct powerdomain per_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain per_am35x_pwrdm = {
@@ -259,13 +259,13 @@ static struct powerdomain per_am35x_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain emu_pwrdm = {
        .name           = "emu_pwrdm",
        .prcm_offs      = OMAP3430_EMU_MOD,
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain neon_pwrdm = {
@@ -273,7 +273,7 @@ static struct powerdomain neon_pwrdm = {
        .prcm_offs        = OMAP3430_NEON_MOD,
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain neon_am35x_pwrdm = {
@@ -281,7 +281,7 @@ static struct powerdomain neon_am35x_pwrdm = {
        .prcm_offs        = OMAP3430_NEON_MOD,
        .pwrsts           = PWRSTS_ON,
        .pwrsts_logic_ret = PWRSTS_ON,
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain usbhost_pwrdm = {
@@ -303,37 +303,37 @@ static struct powerdomain usbhost_pwrdm = {
        .pwrsts_mem_on    = {
                [0] = PWRSTS_ON,  /* MEMONSTATE */
        },
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll1_pwrdm = {
        .name           = "dpll1_pwrdm",
        .prcm_offs      = MPU_MOD,
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain dpll2_pwrdm = {
        .name           = "dpll2_pwrdm",
        .prcm_offs      = OMAP3430_IVA2_MOD,
-        .voltdm           = { .name = "mpu_iva" },
+        .voltdm           = { .name = "mpu_iva" },
 };
 static struct powerdomain dpll3_pwrdm = {
        .name           = "dpll3_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll4_pwrdm = {
        .name           = "dpll4_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 static struct powerdomain dpll5_pwrdm = {
        .name           = "dpll5_pwrdm",
        .prcm_offs      = PLL_MOD,
-        .voltdm           = { .name = "core" },
+        .voltdm           = { .name = "core" },
 };
 /* As powerdomains are added or removed above, this list must also be changed */
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a3e121f94a86..947f6adfed0c 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -210,6 +210,7 @@ int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
                                             PM_WKDEP, (1 << clkdm2->dep_bit));
 }
+/* XXX Caller must hold the clkdm's powerdomain lock */
 int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 {
        struct clkdm_dep *cd;
@@ -221,7 +222,7 @@ int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
                /* PRM accesses are slow, so minimize them */
                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
+                cd->wkdep_usecount = 0;
        }
        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 1ac73883f891..44c0d7216aa7 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
-int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
                u16 rstctrl_offs, u16 rstst_offs)
 {
        int c;
-        u32 mask = 1 << shift;
+        u32 mask = 1 << st_shift;
        /* Check the current status to avoid  de-asserting the line twice */
        if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
@@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
        /* Clear the reset status by writing 1 to the status bit */
        am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
        /* de-assert the reset control line */
+        mask = 1 << shift;
        am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
-        /* wait the status to be set */
-        omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+        /* wait the status to be set */
+        omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
                                                           rstst_offs),
                          MAX_MODULE_HARDRESET_WAIT, c);
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c563a821..9b9918dfb119 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -117,6 +117,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET         0x0004
 #define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+#ifndef __ASSEMBLER__
 extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
 extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
 extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@@ -124,6 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
 extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
                u16 rstctrl_offs);
 extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
-extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
                u16 rstctrl_offs, u16 rstst_offs);
+#endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index e648bd55b072..7721990d2006 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -427,7 +427,7 @@ static int __init omap3xxx_prm_late_init(void)
        return ret;
 }
-subsys_initcall(omap3xxx_prm_late_init);
+omap_subsys_initcall(omap3xxx_prm_late_init);
 static void __exit omap3xxx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index c05a343d465d..d35f98aabf7a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -665,7 +665,7 @@ static int __init omap44xx_prm_late_init(void)
        return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 }
-subsys_initcall(omap44xx_prm_late_init);
+omap_subsys_initcall(omap44xx_prm_late_init);
 static void __exit omap44xx_prm_exit(void)
 {
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 04fdbc4c499b..8396b5b7e912 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -254,7 +254,7 @@ static int __init omap_serial_early_init(void)
        return 0;
 }
-core_initcall(omap_serial_early_init);
+omap_core_initcall(omap_serial_early_init);
 /**
 * omap_serial_init_port() - initialize single serial port
@@ -316,8 +316,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
        if (WARN_ON(!oh))
                return;
-        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
-                                 NULL, 0, false);
        if (IS_ERR(pdev)) {
                WARN(1, "Could not build omap_device for %s: %s.\n", name,
                     oh->name);
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index ce0ccd26efbd..1d3cb25c9629 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -37,25 +37,6 @@
        .text
 /*
- * Forces OMAP into idle state
- *
- * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
- * for normal idles.
- *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- *       wakes up it continues execution at the point it went to sleep.
- */
-        .align  3
-ENTRY(omap24xx_idle_loop_suspend)
-        stmfd   sp!, {r0, lr}           @ save registers on stack
-        mov     r0, #0                  @ clear for mcr setup
-        mcr     p15, 0, r0, c7, c0, 4   @ wait for interrupt
-        ldmfd   sp!, {r0, pc}           @ restore regs and return
-ENTRY(omap24xx_idle_loop_suspend_sz)
-        .word   . - omap24xx_idle_loop_suspend
-/*
 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
 * SDRC shutdown then ARM shutdown.  Upon wake MPU is back on so just restore
 * SDRC.
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 1da8f03c479e..aee3c8940a30 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -12,6 +12,7 @@
 */
 #include <linux/power/smartreflex.h>
+#include "soc.h"
 #include "voltage.h"
 static int sr_class3_enable(struct omap_sr *sr)
@@ -58,4 +59,4 @@ static int __init sr_class3_init(void)
        pr_info("SmartReflex Class3 initialized\n");
        return sr_register_class(&class3_data);
 }
-late_initcall(sr_class3_init);
+omap_late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index f31d90774de0..c62116bbc760 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -42,6 +42,9 @@
 #undef MULTI_OMAP2
 #undef OMAP_NAME
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define MULTI_OMAP2
+#endif
 #ifdef CONFIG_SOC_OMAP2420
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
@@ -112,6 +115,11 @@ int omap_type(void);
 */
 unsigned int omap_rev(void);
+static inline int soc_is_omap(void)
+{
+        return omap_rev() != 0;
+}
 /*
 * Get the CPU revision for OMAP devices
 */
@@ -387,6 +395,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_CLASS            0x33500033
 #define AM335X_REV_ES1_0        AM335X_CLASS
+#define AM335X_REV_ES2_0        (AM335X_CLASS | (0x1 << 8))
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
@@ -465,5 +474,26 @@ static inline unsigned int omap4_has_ ##feat(void)	\
 OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
+/*
+ * We need to make sure omap initcalls don't run when
+ * multiplatform kernels are booted on other SoCs.
+ */
+#define omap_initcall(level, fn)                \
+static int __init __used __##fn(void)           \
+{                                               \
+        if (!soc_is_omap())                     \
+                return 0;                       \
+        return fn();                            \
+}                                               \
+level(__##fn);
+#define omap_early_initcall(fn)         omap_initcall(early_initcall, fn)
+#define omap_core_initcall(fn)          omap_initcall(core_initcall, fn)
+#define omap_postcore_initcall(fn)      omap_initcall(postcore_initcall, fn)
+#define omap_arch_initcall(fn)          omap_initcall(arch_initcall, fn)
+#define omap_subsys_initcall(fn)        omap_initcall(subsys_initcall, fn)
+#define omap_device_initcall(fn)        omap_initcall(device_initcall, fn)
+#define omap_late_initcall(fn)          omap_initcall(late_initcall, fn)
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index b9753fe27232..d7bc33f15344 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -152,8 +152,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data->enable_on_init = sr_enable_on_init;
-        pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
+        pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
-                                 NULL, 0, 0);
        if (IS_ERR(pdev))
                pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
                        __func__, name, oh->name);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b8ad6e632bb8..2bdd4cf17a8f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -131,7 +131,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device clockevent_gpt = {
        .name           = "gp_timer",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
        .rating         = 300,
        .set_next_event = omap2_gp_timer_set_next_event,
        .set_mode       = omap2_gp_timer_set_mode,
@@ -228,7 +227,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        int r = 0;
        if (of_have_populated_dt()) {
-                np = omap_get_timer_dt(omap_timer_match, NULL);
+                np = omap_get_timer_dt(omap_timer_match, property);
                if (!np)
                        return -ENODEV;
@@ -336,17 +335,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
        __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
-        clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
-                                     clockevent_gpt.shift);
-        clockevent_gpt.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
-        clockevent_gpt.min_delta_ns =
-                clockevent_delta2ns(3, &clockevent_gpt);
-                /* Timer internal resynch latency. */
        clockevent_gpt.cpumask = cpu_possible_mask;
        clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
-        clockevents_register_device(&clockevent_gpt);
+        clockevents_config_and_register(&clockevent_gpt, clkev.rate,
+                                        3, /* Timer internal resynch latency */
+                                        0xffffffff);
        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
                gptimer_id, clkev.rate);
@@ -552,7 +545,7 @@ static inline void __init realtime_counter_init(void)
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
                               clksrc_nr, clksrc_src)                   \
-static void __init omap##name##_gptimer_timer_init(void)                \
+void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
@@ -561,7 +554,7 @@ static void __init omap##name##_gptimer_timer_init(void)		\
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
                                clksrc_nr, clksrc_src)                  \
-static void __init omap##name##_sync32k_timer_init(void)                \
+void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
@@ -572,33 +565,23 @@ static void __init omap##name##_sync32k_timer_init(void)		\
                omap2_sync32k_clocksource_init();                       \
 }
-#define OMAP_SYS_TIMER(name, clksrc)                                    \
-struct sys_timer omap##name##_timer = {                                 \
-        .init   = omap##name##_##clksrc##_timer_init,                   \
-};
 #ifdef CONFIG_ARCH_OMAP2
 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
                        2, OMAP2_MPU_SOURCE);
-OMAP_SYS_TIMER(2, sync32k);
 #endif /* CONFIG_ARCH_OMAP2 */
 #ifdef CONFIG_ARCH_OMAP3
 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_TIMER(3, sync32k);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_TIMER(3_secure, sync32k);
 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
                       2, OMAP3_MPU_SOURCE);
-OMAP_SYS_TIMER(3_gp, gptimer);
 #endif /* CONFIG_ARCH_OMAP3 */
 #ifdef CONFIG_SOC_AM33XX
 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
                       2, OMAP4_MPU_SOURCE);
-OMAP_SYS_TIMER(3_am33xx, gptimer);
 #endif /* CONFIG_SOC_AM33XX */
 #ifdef CONFIG_ARCH_OMAP4
@@ -606,7 +589,7 @@ OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
-static void __init omap4_local_timer_init(void)
+void __init omap4_local_timer_init(void)
 {
        omap4_sync32k_timer_init();
        /* Local timers are not supprted on OMAP4430 ES1.0 */
@@ -624,18 +607,17 @@ static void __init omap4_local_timer_init(void)
        }
 }
 #else /* CONFIG_LOCAL_TIMERS */
-static void __init omap4_local_timer_init(void)
+void __init omap4_local_timer_init(void)
 {
        omap4_sync32k_timer_init();
 }
 #endif /* CONFIG_LOCAL_TIMERS */
-OMAP_SYS_TIMER(4, local);
 #endif /* CONFIG_ARCH_OMAP4 */
 #ifdef CONFIG_SOC_OMAP5
 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
                        2, OMAP4_MPU_SOURCE);
-static void __init omap5_realtime_timer_init(void)
+void __init omap5_realtime_timer_init(void)
 {
        int err;
@@ -646,7 +628,6 @@ static void __init omap5_realtime_timer_init(void)
        if (err)
                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
-OMAP_SYS_TIMER(5, realtime);
 #endif /* CONFIG_SOC_OMAP5 */
 /**
@@ -702,8 +683,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
        pdata->timer_errata = omap_dm_timer_get_errata();
        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
-        pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+        pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
-                                 NULL, 0, 0);
        if (IS_ERR(pdev)) {
                pr_err("%s: Can't build omap_device for %s: %s.\n",
@@ -738,7 +718,7 @@ static int __init omap2_dm_timer_init(void)
        return 0;
 }
-arch_initcall(omap2_dm_timer_init);
+omap_arch_initcall(omap2_dm_timer_init);
 /**
 * omap2_override_clocksource - clocksource override with user configuration
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index e49b40b4c90a..51e138cc5398 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -23,6 +23,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/gpio.h>
+#include <linux/string.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -56,7 +57,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
                           struct twl4030_platform_data *pmic_data)
 {
        omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-        strncpy(pmic_i2c_board_info.type, pmic_type,
+        strlcpy(pmic_i2c_board_info.type, pmic_type,
                sizeof(pmic_i2c_board_info.type));
        pmic_i2c_board_info.irq = pmic_irq;
        pmic_i2c_board_info.platform_data = pmic_data;
@@ -528,24 +529,29 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
        defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
 #include <linux/platform_data/omap-twl4030.h>
+/* Commonly used configuration */
 static struct omap_tw4030_pdata omap_twl4030_audio_data;
 static struct platform_device audio_device = {
        .name           = "omap-twl4030",
        .id             = -1,
-        .dev = {
-                .platform_data = &omap_twl4030_audio_data,
-        },
 };
-void __init omap_twl4030_audio_init(char *card_name)
+void omap_twl4030_audio_init(char *card_name,
+                                    struct omap_tw4030_pdata *pdata)
 {
-        omap_twl4030_audio_data.card_name = card_name;
+        if (!pdata)
+                pdata = &omap_twl4030_audio_data;
+        pdata->card_name = card_name;
+        audio_device.dev.platform_data = pdata;
        platform_device_register(&audio_device);
 }
 #else /* SOC_OMAP_TWL4030 */
-void __init omap_twl4030_audio_init(char *card_name)
+void omap_twl4030_audio_init(char *card_name,
+                                    struct omap_tw4030_pdata *pdata)
 {
        return;
 }
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index dcfbad5ac471..24b65d081b69 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -32,6 +32,7 @@
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct omap_tw4030_pdata;
 struct i2c_board_info;
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
@@ -60,6 +61,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                           u32 pdata_flags, u32 regulators_flags);
-void omap_twl4030_audio_init(char *card_name);
+void omap_twl4030_audio_init(char *card_name, struct omap_tw4030_pdata *pdata);
 #endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 2e44e8a22884..5706bdccf45e 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -37,19 +37,6 @@
 #define USBHS_UHH_HWMODNAME     "usb_host_hs"
 #define USBHS_TLL_HWMODNAME     "usb_tll_hs"
-static struct usbhs_omap_platform_data          usbhs_data;
-static struct usbtll_omap_platform_data         usbtll_data;
-static struct ehci_hcd_omap_platform_data       ehci_data;
-static struct ohci_hcd_omap_platform_data       ohci_data;
-static struct omap_device_pm_latency omap_uhhtll_latency[] = {
-          {
-                .deactivate_func = omap_device_idle_hwmods,
-                .activate_func   = omap_device_enable_hwmods,
-                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
-          },
-};
 /* MUX settings for EHCI pins */
 /*
 * setup_ehci_io_mux - initialize IO pad mux for USBHOST
@@ -485,32 +472,18 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
        }
 }
-void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 {
        struct omap_hwmod       *uhh_hwm, *tll_hwm;
        struct platform_device  *pdev;
        int                     bus_id = -1;
-        int                     i;
-        for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
-                usbhs_data.port_mode[i] = pdata->port_mode[i];
-                usbtll_data.port_mode[i] = pdata->port_mode[i];
-                ohci_data.port_mode[i] = pdata->port_mode[i];
-                ehci_data.port_mode[i] = pdata->port_mode[i];
-                ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
-                ehci_data.regulator[i] = pdata->regulator[i];
-        }
-        ehci_data.phy_reset = pdata->phy_reset;
-        ohci_data.es2_compatibility = pdata->es2_compatibility;
-        usbhs_data.ehci_data = &ehci_data;
-        usbhs_data.ohci_data = &ohci_data;
        if (cpu_is_omap34xx()) {
                setup_ehci_io_mux(pdata->port_mode);
                setup_ohci_io_mux(pdata->port_mode);
                if (omap_rev() <= OMAP3430_REV_ES2_1)
-                        usbhs_data.single_ulpi_bypass = true;
+                        pdata->single_ulpi_bypass = true;
        } else if (cpu_is_omap44xx()) {
                setup_4430ehci_io_mux(pdata->port_mode);
@@ -530,9 +503,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
        }
        pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
-                                &usbtll_data, sizeof(usbtll_data),
+                                pdata, sizeof(*pdata));
-                                omap_uhhtll_latency,
-                                ARRAY_SIZE(omap_uhhtll_latency), false);
        if (IS_ERR(pdev)) {
                pr_err("Could not build hwmod device %s\n",
                       USBHS_TLL_HWMODNAME);
@@ -540,9 +511,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
        }
        pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
-                                &usbhs_data, sizeof(usbhs_data),
+                                pdata, sizeof(*pdata));
-                                omap_uhhtll_latency,
-                                ARRAY_SIZE(omap_uhhtll_latency), false);
        if (IS_ERR(pdev)) {
                pr_err("Could not build hwmod devices %s\n",
                       USBHS_UHH_HWMODNAME);
@@ -552,7 +521,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 #else
-void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
+void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 {
 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 7b33b375fe77..3242a554ad6b 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,6 +85,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
        musb_plat.mode = board_data->mode;
        musb_plat.extvbus = board_data->extvbus;
+        if (cpu_is_omap44xx())
+                musb_plat.has_mailbox = true;
        if (soc_is_am35xx()) {
                oh_name = "am35x_otg_hs";
                name = "musb-am35x";
@@ -102,7 +105,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
                return;
        pdev = omap_device_build(name, bus_id, oh, &musb_plat,
-                               sizeof(musb_plat), NULL, 0, false);
+                                 sizeof(musb_plat));
        if (IS_ERR(pdev)) {
                pr_err("Could not build omap_device for %s %s\n",
                                                name, oh_name);
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 9b986ead7c45..3319f5cf47a3 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -53,26 +53,8 @@
 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 #define USBPHY_DATA_POLARITY    (1 << 23)
-struct usbhs_omap_board_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        /* have to be valid if phy_reset is true and portx is in phy mode */
-        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
-        /* Set this to true for ES2.x silicon */
-        unsigned                        es2_compatibility:1;
-        unsigned                        phy_reset:1;
-        /*
-         * Regulators for USB PHYs.
-         * Each PHY can have a separate regulator.
-         */
-        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
-};
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
-extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 7c2b4ed38f02..d15c7bbab8e2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -124,10 +124,9 @@ static int __init omap_init_wdt(void)
        pdata.read_reset_sources = prm_read_reset_sources;
        pdev = omap_device_build(dev_name, id, oh, &pdata,
-                                 sizeof(struct omap_wd_timer_platform_data),
+                                 sizeof(struct omap_wd_timer_platform_data));
-                                 NULL, 0, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
             dev_name, oh->name);
        return 0;
 }
-subsys_initcall(omap_init_wdt);
+omap_subsys_initcall(omap_init_wdt);
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 32e5c211a89b..35a8014529ca 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -72,7 +72,7 @@ DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion_dt_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .init_machine   = orion5x_dt_init,
        .restart        = orion5x_restart,
        .dt_compat      = orion5x_dt_compat,
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 550f92320afb..d068f1431c40 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -217,7 +217,7 @@ int __init orion5x_find_tclk(void)
        return 166666667;
 }
-static void __init orion5x_timer_init(void)
+void __init orion5x_timer_init(void)
 {
        orion5x_tclk = orion5x_find_tclk();
@@ -225,10 +225,6 @@ static void __init orion5x_timer_init(void)
                        IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
-struct sys_timer orion5x_timer = {
-        .init = orion5x_timer_init,
-};
 /*****************************************************************************
 * General
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 7db5cdd9c4b7..e60345760283 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -15,7 +15,7 @@ void orion5x_init(void);
 void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
 void clk_init(void);
 extern int orion5x_tclk;
-extern struct sys_timer orion5x_timer;
+extern void orion5x_timer_init(void);
 /*
 * Enumerations and functions for Orion windows mapping. Used by Orion core
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index e3629c063df2..57d0af74874d 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -342,7 +342,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
@@ -355,7 +355,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 41fe2b1ff47c..76665640087b 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -362,6 +362,6 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index e533588880ff..6eb1732757fd 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -714,7 +714,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h
index 4322dba468a4..abd26b542c3c 100644
--- a/arch/arm/mach-orion5x/include/mach/uncompress.h
+++ b/arch/arm/mach-orion5x/include/mach/uncompress.h
@@ -46,4 +46,3 @@ static void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index f1ae10ae5bd4..b98403526218 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -383,7 +383,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
@@ -397,7 +397,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 0c9e413b5805..044da5b6a6ae 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -322,7 +322,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index c1b5d8a58037..d49f93423f52 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -269,7 +269,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 949eaa8f12e3..8e3965c6c0fe 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -271,7 +271,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 1c16d045333e..0ec94a1f2b16 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -265,7 +265,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c87fde4deeca..18143f2a9093 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -233,7 +233,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 3506f16c0bf2..282e503b003e 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -425,7 +425,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 9b1c95310291..d6e72f672afb 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -171,7 +171,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 51ba2b81a10b..c8b7913310e5 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -183,7 +183,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 0a56b9444f1b..f9e156725d7c 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -281,6 +281,6 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index ed50910b08a4..78a1e6ab1b9d 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -123,7 +123,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 90e571dc4deb..acc0877ec1c9 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -361,7 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index b184f680e0db..9c17f0c2b488 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -326,7 +326,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index a5c2e64c4ece..8cc5ab6c503e 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -315,7 +315,7 @@ MACHINE_START(TS409, "QNAP TS-409")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index b0727dcd1ef9..e960855d32ac 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -619,6 +619,6 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
        .map_io         = ts78xx_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 754c12b6abf0..66552ca7e05d 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -176,7 +176,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 45c21251eb1e..2c5408e2e689 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -264,7 +264,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
        .map_io         = orion5x_map_io,
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
+        .init_time      = orion5x_timer_init,
        .fixup          = tag_fixup_mem32,
        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 868796f8085c..13bae78b215a 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -7,7 +7,6 @@ config ARCH_PICOXCELL
        select DW_APB_TIMER
        select DW_APB_TIMER_OF
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_TCM
        select NO_IOPORT
        select SPARSE_IRQ
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index f6c0849af5e9..70b441ad1d18 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -9,6 +9,7 @@
 */
 #include <linux/delay.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -17,7 +18,6 @@
 #include <linux/dw_apb_timer.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
 #include "common.h"
@@ -70,16 +70,6 @@ static const char *picoxcell_dt_match[] = {
        NULL
 };
-static const struct of_device_id vic_of_match[] __initconst = {
-        { .compatible = "arm,pl192-vic", .data = vic_of_init, },
-        { /* Sentinel */ }
-};
-static void __init picoxcell_init_irq(void)
-{
-        of_irq_init(vic_of_match);
-}
 static void picoxcell_wdt_restart(char mode, const char *cmd)
 {
        /*
@@ -97,9 +87,8 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
        .map_io         = picoxcell_map_io,
        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = picoxcell_init_irq,
+        .init_irq       = irqchip_init,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = dw_apb_timer_init,
-        .timer          = &dw_apb_timer,
        .init_machine   = picoxcell_init_machine,
        .dt_compat      = picoxcell_dt_match,
        .restart        = picoxcell_wdt_restart,
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
index a65cb02f84c8..481b42a4ef15 100644
--- a/arch/arm/mach-picoxcell/common.h
+++ b/arch/arm/mach-picoxcell/common.h
@@ -12,6 +12,6 @@
 #include <asm/mach/time.h>
-extern struct sys_timer dw_apb_timer;
+extern void dw_apb_timer_init(void);
 #endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 558ccfb8d458..4f7379fe01e2 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -11,6 +11,16 @@ config ARCH_PRIMA2
        help
          Support for CSR SiRFSoC ARM Cortex A9 Platform
+config ARCH_MARCO
+        bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
+        default y
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_SMP
+        select SMP_ON_UP
+        help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
 endmenu
 config SIRF_IRQ
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index fc9ce22e2b5a..bfe360cbd177 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,4 +1,3 @@
-obj-y := timer.o
 obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
@@ -6,3 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SIRF_IRQ) += irq.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
+obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
+obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index f25a54194639..2d57aa479a7b 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -8,6 +8,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/irqchip.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -30,6 +31,12 @@ void __init sirfsoc_init_late(void)
        sirfsoc_pm_init();
 }
+static __init void sirfsoc_map_io(void)
+{
+        sirfsoc_map_lluart();
+        sirfsoc_map_scu();
+}
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
       "sirf,prima2",
@@ -38,9 +45,12 @@ static const char *prima2_dt_match[] __initdata = {
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
-        .map_io         = sirfsoc_map_lluart,
+        .map_io         = sirfsoc_map_io,
        .init_irq       = sirfsoc_of_irq_init,
-        .timer          = &sirfsoc_timer,
+        .init_time      = sirfsoc_prima2_timer_init,
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        .handle_irq     = sirfsoc_handle_irq,
+#endif
        .dma_zone_size  = SZ_256M,
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
@@ -48,3 +58,22 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        .restart        = sirfsoc_restart,
 MACHINE_END
 #endif
+#ifdef CONFIG_ARCH_MARCO
+static const char *marco_dt_match[] __initdata = {
+        "sirf,marco",
+        NULL
+};
+DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
+        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .smp            = smp_ops(sirfsoc_smp_ops),
+        .map_io         = sirfsoc_map_io,
+        .init_irq       = irqchip_init,
+        .init_time      = sirfsoc_marco_timer_init,
+        .init_machine   = sirfsoc_mach_init,
+        .init_late      = sirfsoc_init_late,
+        .dt_compat      = marco_dt_match,
+        .restart        = sirfsoc_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 60d826fc2185..b7c26b62e4a7 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -11,12 +11,19 @@
 #include <linux/init.h>
 #include <asm/mach/time.h>
+#include <asm/exception.h>
-extern struct sys_timer sirfsoc_timer;
+extern void sirfsoc_prima2_timer_init(void);
+extern void sirfsoc_marco_timer_init(void);
+extern struct smp_operations   sirfsoc_smp_ops;
+extern void sirfsoc_secondary_startup(void);
+extern void sirfsoc_cpu_die(unsigned int cpu);
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
 extern void sirfsoc_restart(char, const char *);
+extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 #ifndef CONFIG_DEBUG_LL
 static inline void sirfsoc_map_lluart(void)  {}
@@ -24,6 +31,12 @@ static inline void sirfsoc_map_lluart(void)  {}
 extern void __init sirfsoc_map_lluart(void);
 #endif
+#ifndef CONFIG_SMP
+static inline void sirfsoc_map_scu(void) {}
+#else
+extern void sirfsoc_map_scu(void);
+#endif
 #ifdef CONFIG_SUSPEND
 extern int sirfsoc_pm_init(void);
 #else
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
new file mode 100644
index 000000000000..5b8a408d8921
--- /dev/null
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -0,0 +1,40 @@
+/*
+ * Entry of the second core for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+        __CPUINIT
+/*
+ * SIRFSOC specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sirfsoc_secondary_startup)
+        bl v7_invalidate_l1
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+ENDPROC(sirfsoc_secondary_startup)
+        .align
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
new file mode 100644
index 000000000000..f4b17cbababd
--- /dev/null
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -0,0 +1,41 @@
+/*
+ * CPU hotplug support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+        flush_cache_all();
+        /* we put the platform to just WFI */
+        for (;;) {
+                __asm__ __volatile__("dsb\n\t" "wfi\n\t"
+                        : : : "memory");
+                if (pen_release == cpu_logical_map(cpu)) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+        }
+}
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref sirfsoc_cpu_die(unsigned int cpu)
+{
+        platform_do_lowpower(cpu);
+}
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
index f6014a07541f..b778a0f248ed 100644
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -10,8 +10,8 @@
 #define __ASM_ARCH_IRQS_H
 #define SIRFSOC_INTENAL_IRQ_START  0
-#define SIRFSOC_INTENAL_IRQ_END    59
+#define SIRFSOC_INTENAL_IRQ_END    127
 #define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
-#define NR_IRQS 220
+#define NR_IRQS 288
 #endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
index c98b4d5ac24a..c10510d01a44 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -10,7 +10,13 @@
 #define __MACH_PRIMA2_SIRFSOC_UART_H
 /* UART-1: used as serial debug port */
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
 #define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE          0
+#endif
 #define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
 #define SIRFSOC_UART1_SIZE              SZ_4K
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 0c898fcf909c..d1513a33709a 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -17,14 +17,15 @@ void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog()
 static __inline__ void putc(char c)
 {
        /*
         * during kernel decompression, all mappings are flat:
         *  virt_addr == phys_addr
         */
+        if (!SIRFSOC_UART1_PA_BASE)
+                return;
        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
                & SIRFSOC_UART1_TXFIFO_FULL)
                barrier();
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index 7dee9176e77a..6c0f3e9c43fb 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -9,17 +9,19 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <mach/hardware.h>
-#include <asm/mach/irq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/irqdomain.h>
 #include <linux/syscore_ops.h>
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+#include <mach/hardware.h>
 #define SIRFSOC_INT_RISC_MASK0          0x0018
 #define SIRFSOC_INT_RISC_MASK1          0x001C
 #define SIRFSOC_INT_RISC_LEVEL0         0x0020
 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
+#define SIRFSOC_INIT_IRQ_ID             0x0038
 void __iomem *sirfsoc_intc_base;
@@ -52,6 +54,16 @@ static __init void sirfsoc_irq_init(void)
        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
 }
+asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
+{
+        u32 irqstat, irqnr;
+        irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
+        irqnr = irqstat & 0xff;
+        handle_IRQ(irqnr, regs);
+}
 static struct of_device_id intc_ids[]  = {
        { .compatible = "sirf,prima2-intc" },
        {},
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index c99837797d76..cbcbe9cb094c 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -11,19 +11,38 @@
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
-static struct of_device_id prima2_l2x0_ids[]  = {
+struct l2x0_aux
-        { .compatible = "sirf,prima2-pl310-cache" },
+{
+        u32 val;
+        u32 mask;
+};
+static struct l2x0_aux prima2_l2x0_aux __initconst = {
+        .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT,
+        .mask = 0,
+};
+static struct l2x0_aux marco_l2x0_aux __initconst = {
+        .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+                (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
+        .mask = L2X0_AUX_CTRL_MASK,
+};
+static struct of_device_id sirf_l2x0_ids[] __initconst = {
+        { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
+        { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
        {},
 };
 static int __init sirfsoc_l2x0_init(void)
 {
        struct device_node *np;
+        const struct l2x0_aux *aux;
-        np = of_find_matching_node(NULL, prima2_l2x0_ids);
+        np = of_find_matching_node(NULL, sirf_l2x0_ids);
        if (np) {
-                pr_info("Initializing prima2 L2 cache\n");
+                aux = of_match_node(sirf_l2x0_ids, np)->data;
-                return l2x0_of_init(0x40000, 0);
+                return l2x0_of_init(aux->val, aux->mask);
        }
        return 0;
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
new file mode 100644
index 000000000000..4b788310f6a6
--- /dev/null
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -0,0 +1,157 @@
+/*
+ * plat smp support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <mach/map.h>
+#include "common.h"
+static void __iomem *scu_base;
+static void __iomem *rsc_base;
+static DEFINE_SPINLOCK(boot_lock);
+static struct map_desc scu_io_desc __initdata = {
+        .length         = SZ_4K,
+        .type           = MT_DEVICE,
+};
+void __init sirfsoc_map_scu(void)
+{
+        unsigned long base;
+        /* Get SCU base */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+        scu_io_desc.virtual = SIRFSOC_VA(base);
+        scu_io_desc.pfn = __phys_to_pfn(base);
+        iotable_init(&scu_io_desc, 1);
+        scu_base = (void __iomem *)SIRFSOC_VA(base);
+}
+static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
+{
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+        smp_wmb();
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+static struct of_device_id rsc_ids[]  = {
+        { .compatible = "sirf,marco-rsc" },
+        {},
+};
+static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+        struct device_node *np;
+        np = of_find_matching_node(NULL, rsc_ids);
+        if (!np)
+                return -ENODEV;
+        rsc_base = of_iomap(np, 0);
+        if (!rsc_base)
+                return -ENOMEM;
+        /*
+         * write the address of secondary startup into the sram register
+         * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
+         * RSC register at offset 0x28, which is what boot rom code is
+         * waiting for. This would wake up the secondary core from WFE
+         */
+#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
+        __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+                rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
+#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
+        __raw_writel(0x3CAF5D62,
+                rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
+        /* make sure write buffer is drained */
+        mb();
+        spin_lock(&boot_lock);
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu_logical_map(cpu);
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        /*
+         * Send the secondary CPU SEV, thereby causing the boot monitor to read
+         * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
+         */
+        dsb_sev();
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+                udelay(10);
+        }
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
+{
+        scu_enable(scu_base);
+}
+struct smp_operations sirfsoc_smp_ops __initdata = {
+        .smp_prepare_cpus       = sirfsoc_smp_prepare_cpus,
+        .smp_secondary_init     = sirfsoc_secondary_init,
+        .smp_boot_secondary     = sirfsoc_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = sirfsoc_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 762adb73ab7c..435019ca0a48 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
 static struct of_device_id rstc_ids[]  = {
        { .compatible = "sirf,prima2-rstc" },
+        { .compatible = "sirf,marco-rstc" },
        {},
 };
@@ -42,27 +43,37 @@ early_initcall(sirfsoc_of_rstc_init);
 int sirfsoc_reset_device(struct device *dev)
 {
-        const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
+        u32 reset_bit;
-        unsigned int reset_bit;
-        if (!prop)
+        if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
-                return -ENODEV;
+                return -EINVAL;
-        reset_bit = be32_to_cpup(prop);
        mutex_lock(&rstc_lock);
-        /*
+        if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
-         * Writing 1 to this bit resets corresponding block. Writing 0 to this
+                /*
-         * bit de-asserts reset signal of the corresponding block.
+                 * Writing 1 to this bit resets corresponding block. Writing 0 to this
-         * datasheet doesn't require explicit delay between the set and clear
+                 * bit de-asserts reset signal of the corresponding block.
-         * of reset bit. it could be shorter if tests pass.
+                 * datasheet doesn't require explicit delay between the set and clear
-         */
+                 * of reset bit. it could be shorter if tests pass.
-        writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+                 */
-                sirfsoc_rstc_base + (reset_bit / 32) * 4);
+                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
-        msleep(10);
+                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
-        writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+                msleep(10);
-                sirfsoc_rstc_base + (reset_bit / 32) * 4);
+                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
+        } else {
+                /*
+                 * For MARCO and POLO
+                 * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
+                 * register de-asserts reset signal of the corresponding block.
+                 * datasheet doesn't require explicit delay between the set and clear
+                 * of reset bit. it could be shorter if tests pass.
+                 */
+                writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
+                msleep(10);
+                writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+        }
        mutex_unlock(&rstc_lock);
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
index 557353602130..9f2da2eec4dc 100644
--- a/arch/arm/mach-prima2/rtciobrg.c
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -104,6 +104,7 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
 static const struct of_device_id rtciobrg_ids[] = {
        { .compatible = "sirf,prima2-rtciobg" },
+        { .compatible = "sirf,marco-rtciobg" },
        {}
 };
diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
new file mode 100644
index 000000000000..f4eea2e97eb0
--- /dev/null
+++ b/arch/arm/mach-prima2/timer-marco.c
@@ -0,0 +1,316 @@
+/*
+ * System timer for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <asm/sched_clock.h>
+#include <asm/localtimer.h>
+#include <asm/mach/time.h>
+#include "common.h"
+#define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
+#define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
+#define SIRFSOC_TIMER_MATCH_0                           0x0018
+#define SIRFSOC_TIMER_MATCH_1                           0x001c
+#define SIRFSOC_TIMER_COUNTER_0                         0x0048
+#define SIRFSOC_TIMER_COUNTER_1                         0x004c
+#define SIRFSOC_TIMER_INTR_STATUS                       0x0060
+#define SIRFSOC_TIMER_WATCHDOG_EN                       0x0064
+#define SIRFSOC_TIMER_64COUNTER_CTRL                    0x0068
+#define SIRFSOC_TIMER_64COUNTER_LO                      0x006c
+#define SIRFSOC_TIMER_64COUNTER_HI                      0x0070
+#define SIRFSOC_TIMER_64COUNTER_LOAD_LO                 0x0074
+#define SIRFSOC_TIMER_64COUNTER_LOAD_HI                 0x0078
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO             0x007c
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI             0x0080
+#define SIRFSOC_TIMER_REG_CNT 6
+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
+        SIRFSOC_TIMER_WATCHDOG_EN,
+        SIRFSOC_TIMER_32COUNTER_0_CTRL,
+        SIRFSOC_TIMER_32COUNTER_1_CTRL,
+        SIRFSOC_TIMER_64COUNTER_CTRL,
+        SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
+        SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
+};
+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
+static void __iomem *sirfsoc_timer_base;
+static void __init sirfsoc_of_timer_map(void);
+/* disable count and interrupt */
+static inline void sirfsoc_timer_count_disable(int idx)
+{
+        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
+                sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
+}
+/* enable count and interrupt */
+static inline void sirfsoc_timer_count_enable(int idx)
+{
+        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
+                sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
+}
+/* timer interrupt handler */
+static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *ce = dev_id;
+        int cpu = smp_processor_id();
+        /* clear timer interrupt */
+        writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+        if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
+                sirfsoc_timer_count_disable(cpu);
+        ce->event_handler(ce);
+        return IRQ_HANDLED;
+}
+/* read 64-bit timer counter */
+static cycle_t sirfsoc_timer_read(struct clocksource *cs)
+{
+        u64 cycles;
+        writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+                        BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+        cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
+        cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
+        return cycles;
+}
+static int sirfsoc_timer_set_next_event(unsigned long delta,
+        struct clock_event_device *ce)
+{
+        int cpu = smp_processor_id();
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
+                4 * cpu);
+        writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
+                4 * cpu);
+        /* enable the tick */
+        sirfsoc_timer_count_enable(cpu);
+        return 0;
+}
+static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *ce)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* enable in set_next_event */
+                break;
+        default:
+                break;
+        }
+        sirfsoc_timer_count_disable(smp_processor_id());
+}
+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
+{
+        int i;
+        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+                sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+}
+static void sirfsoc_clocksource_resume(struct clocksource *cs)
+{
+        int i;
+        for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
+                writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
+                sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
+                sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+                BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+}
+static struct clock_event_device sirfsoc_clockevent = {
+        .name = "sirfsoc_clockevent",
+        .rating = 200,
+        .features = CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = sirfsoc_timer_set_mode,
+        .set_next_event = sirfsoc_timer_set_next_event,
+};
+static struct clocksource sirfsoc_clocksource = {
+        .name = "sirfsoc_clocksource",
+        .rating = 200,
+        .mask = CLOCKSOURCE_MASK(64),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+        .read = sirfsoc_timer_read,
+        .suspend = sirfsoc_clocksource_suspend,
+        .resume = sirfsoc_clocksource_resume,
+};
+static struct irqaction sirfsoc_timer_irq = {
+        .name = "sirfsoc_timer0",
+        .flags = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler = sirfsoc_timer_interrupt,
+        .dev_id = &sirfsoc_clockevent,
+};
+#ifdef CONFIG_LOCAL_TIMERS
+static struct irqaction sirfsoc_timer1_irq = {
+        .name = "sirfsoc_timer1",
+        .flags = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler = sirfsoc_timer_interrupt,
+};
+static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
+{
+        /* Use existing clock_event for cpu 0 */
+        if (!smp_processor_id())
+                return 0;
+        ce->irq = sirfsoc_timer1_irq.irq;
+        ce->name = "local_timer";
+        ce->features = sirfsoc_clockevent.features;
+        ce->rating = sirfsoc_clockevent.rating;
+        ce->set_mode = sirfsoc_timer_set_mode;
+        ce->set_next_event = sirfsoc_timer_set_next_event;
+        ce->shift = sirfsoc_clockevent.shift;
+        ce->mult = sirfsoc_clockevent.mult;
+        ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
+        ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
+        sirfsoc_timer1_irq.dev_id = ce;
+        BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
+        irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
+        clockevents_register_device(ce);
+        return 0;
+}
+static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
+{
+        sirfsoc_timer_count_disable(1);
+        remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
+}
+static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
+        .setup  = sirfsoc_local_timer_setup,
+        .stop   = sirfsoc_local_timer_stop,
+};
+#endif /* CONFIG_LOCAL_TIMERS */
+static void __init sirfsoc_clockevent_init(void)
+{
+        clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
+        sirfsoc_clockevent.max_delta_ns =
+                clockevent_delta2ns(-2, &sirfsoc_clockevent);
+        sirfsoc_clockevent.min_delta_ns =
+                clockevent_delta2ns(2, &sirfsoc_clockevent);
+        sirfsoc_clockevent.cpumask = cpumask_of(0);
+        clockevents_register_device(&sirfsoc_clockevent);
+#ifdef CONFIG_LOCAL_TIMERS
+        local_timer_register(&sirfsoc_local_timer_ops);
+#endif
+}
+/* initialize the kernel jiffy timer source */
+void __init sirfsoc_marco_timer_init(void)
+{
+        unsigned long rate;
+        u32 timer_div;
+        struct clk *clk;
+        /* initialize clocking early, we want to set the OS timer */
+        sirfsoc_of_clk_init();
+        /* timer's input clock is io clock */
+        clk = clk_get_sys("io", NULL);
+        BUG_ON(IS_ERR(clk));
+        rate = clk_get_rate(clk);
+        BUG_ON(rate < CLOCK_TICK_RATE);
+        BUG_ON(rate % CLOCK_TICK_RATE);
+        sirfsoc_of_timer_map();
+        /* Initialize the timer dividers */
+        timer_div = rate / CLOCK_TICK_RATE - 1;
+        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
+        /* Initialize timer counters to 0 */
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+                BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
+        /* Clear all interrupts */
+        writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+        BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
+        sirfsoc_clockevent_init();
+}
+static struct of_device_id timer_ids[] = {
+        { .compatible = "sirf,marco-tick" },
+        {},
+};
+static void __init sirfsoc_of_timer_map(void)
+{
+        struct device_node *np;
+        np = of_find_matching_node(NULL, timer_ids);
+        if (!np)
+                return;
+        sirfsoc_timer_base = of_iomap(np, 0);
+        if (!sirfsoc_timer_base)
+                panic("unable to map timer cpu registers\n");
+        sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
+        if (!sirfsoc_timer_irq.irq)
+                panic("No irq passed for timer0 via DT\n");
+#ifdef CONFIG_LOCAL_TIMERS
+        sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
+        if (!sirfsoc_timer1_irq.irq)
+                panic("No irq passed for timer1 via DT\n");
+#endif
+        of_node_put(np);
+}
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer-prima2.c
index d95bf252f694..6da584f8a949 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer-prima2.c
@@ -175,19 +175,13 @@ static u32 notrace sirfsoc_read_sched_clock(void)
 static void __init sirfsoc_clockevent_init(void)
 {
-        clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
-        sirfsoc_clockevent.max_delta_ns =
-                clockevent_delta2ns(-2, &sirfsoc_clockevent);
-        sirfsoc_clockevent.min_delta_ns =
-                clockevent_delta2ns(2, &sirfsoc_clockevent);
        sirfsoc_clockevent.cpumask = cpumask_of(0);
-        clockevents_register_device(&sirfsoc_clockevent);
+        clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
+                                        2, -2);
 }
 /* initialize the kernel jiffy timer source */
-static void __init sirfsoc_timer_init(void)
+void __init sirfsoc_prima2_timer_init(void)
 {
        unsigned long rate;
        struct clk *clk;
@@ -233,7 +227,7 @@ static void __init sirfsoc_of_timer_map(void)
        np = of_find_matching_node(NULL, timer_ids);
        if (!np)
-                panic("unable to find compatible timer node in dtb\n");
+                return;
        sirfsoc_timer_base = of_iomap(np, 0);
        if (!sirfsoc_timer_base)
                panic("unable to map timer cpu registers\n");
@@ -245,7 +239,3 @@ static void __init sirfsoc_of_timer_map(void)
        of_node_put(np);
 }
-struct sys_timer sirfsoc_timer = {
-        .init = sirfsoc_timer_init,
-};
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 208229342514..2f71b3fbd319 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -822,7 +822,7 @@ MACHINE_START(BALLOON3, "Balloon3")
        .nr_irqs        = BALLOON3_NR_IRQS,
        .init_irq       = balloon3_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = balloon3_init,
        .atag_offset    = 0x100,
        .restart        = pxa_restart,
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 9a8760b72913..c092730749b9 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -153,7 +153,7 @@ MACHINE_START(CAPC7117,
        .nr_irqs = PXA_NR_IRQS,
        .init_irq = pxa3xx_init_irq,
        .handle_irq = pxa3xx_handle_irq,
-        .timer = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine = capc7117_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index a103c8ffea9f..bb99f59a36d8 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -520,7 +520,7 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
        .init_irq       = cmx2xx_init_irq,
        /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = cmx2xx_init,
 #ifdef CONFIG_PCI
        .dma_zone_size  = SZ_64M,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index cc2b23afcaaf..8091aac89edf 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -854,7 +854,7 @@ MACHINE_START(CM_X300, "CM-X300 module")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = cm_x300_init,
        .fixup          = cm_x300_fixup,
        .restart        = pxa_restart,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index b2f227d36125..5f9d9303b346 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -313,7 +313,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -324,7 +324,7 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index a9c9c163dd95..f1a1ac1fbd85 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -189,7 +189,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index 25515cd7e68f..f6cc8b0ab82f 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -259,7 +259,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 7c83f52c549c..a5b8fead7d61 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -733,7 +733,7 @@ MACHINE_START(CORGI, "SHARP Corgi")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = corgi_restart,
 MACHINE_END
 #endif
@@ -746,7 +746,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = corgi_restart,
 MACHINE_END
 #endif
@@ -759,7 +759,7 @@ MACHINE_START(HUSKY, "SHARP Husky")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = corgi_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 7039f44b3647..fadfff8feaef 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -278,6 +278,6 @@ MACHINE_START(CSB726, "Cogent CSB726")
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
        .init_machine   = csb726_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 1b6411439ec8..446563a7d1ad 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1298,7 +1298,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = em_x270_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -1309,7 +1309,7 @@ MACHINE_START(EXEDA, "Compulab eXeda")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = em_x270_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index be2ee9bf5c6e..8280ebcaab9f 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -195,7 +195,7 @@ MACHINE_START(E330, "Toshiba e330")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e330_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -246,7 +246,7 @@ MACHINE_START(E350, "Toshiba e350")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e350_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -370,7 +370,7 @@ MACHINE_START(E400, "Toshiba e400")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e400_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -566,7 +566,7 @@ MACHINE_START(E740, "Toshiba e740")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e740_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -765,7 +765,7 @@ MACHINE_START(E750, "Toshiba e750")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e750_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -977,7 +977,7 @@ MACHINE_START(E800, "Toshiba e800")
        .handle_irq     = pxa25x_handle_irq,
        .fixup          = eseries_fixup,
        .init_machine   = e800_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index dc58fa0edb66..dca10709be8f 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -802,7 +802,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = a780_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -869,7 +869,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = e680_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -936,7 +936,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = a1200_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -1128,7 +1128,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = a910_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -1195,7 +1195,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = e6_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -1236,7 +1236,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
        .nr_irqs        = EZX_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = e2_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 42d5cca66257..fd7ea39b78c0 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -10,9 +10,8 @@
 */
 struct irq_data;
-struct sys_timer;
-extern struct sys_timer pxa_timer;
+extern void pxa_timer_init(void);
 extern void __init pxa_map_io(void);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 60755a6bb1c6..00b92dad7b81 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -238,7 +238,7 @@ MACHINE_START(GUMSTIX, "Gumstix")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = gumstix_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index e7dec589f014..875ec3351499 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -208,7 +208,7 @@ MACHINE_START(H5400, "HP iPAQ H5000")
        .nr_irqs = PXA_NR_IRQS,
        .init_irq = pxa25x_init_irq,
        .handle_irq = pxa25x_handle_irq,
-        .timer = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine = h5000_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index 2962de898da9..7a8d749a07b8 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -164,6 +164,6 @@ MACHINE_START(HIMALAYA, "HTC Himalaya")
        .init_irq = pxa25x_init_irq,
        .handle_irq = pxa25x_handle_irq,
        .init_machine = himalaya_init,
-        .timer = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index e2c6391863fe..133109ec7332 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -900,6 +900,6 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
        .init_irq     = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine = hx4700_init,
-        .timer        = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 1d02eabc9c65..fe31bfcbb8df 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -196,7 +196,7 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = icontrol_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 64507cdd2e8f..343c4e3a7c5d 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -279,7 +279,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = idp_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h
index 2d3f14e3be29..714b6574393e 100644
--- a/arch/arm/mach-pxa/include/mach/palmtreo.h
+++ b/arch/arm/mach-pxa/include/mach/palmtreo.h
@@ -38,13 +38,14 @@
 #define GPIO_NR_TREO_LCD_POWER  25
 /* Treo680 specific GPIOs */
-#ifdef CONFIG_MACH_TREO680
 #define GPIO_NR_TREO680_SD_READONLY     33
 #define GPIO_NR_TREO680_SD_POWER        42
 #define GPIO_NR_TREO680_VIBRATE_EN      44
 #define GPIO_NR_TREO680_KEYB_BL         24
 #define GPIO_NR_TREO680_BT_EN           43
-#endif /* CONFIG_MACH_TREO680 */
+#define GPIO_NR_TREO680_LCD_POWER       77
+#define GPIO_NR_TREO680_LCD_EN          86
+#define GPIO_NR_TREO680_LCD_EN_N        25
 /* Centro685 specific GPIOs */
 #define GPIO_NR_CENTRO_SD_POWER         21
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
index b7de471b273a..b802f285fe00 100644
--- a/arch/arm/mach-pxa/include/mach/smemc.h
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -37,6 +37,7 @@
 #define CSADRCFG1       (SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
 #define CSADRCFG2       (SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
 #define CSADRCFG3       (SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
+#define CSMSADRCFG      (SMEMC_VIRT + 0xA0)  /* Chip Select Configuration Register */
 /*
 * More handy macros for PCMCIA
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 5519a34b667f..8c27757e68ff 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -72,8 +72,3 @@ static inline void arch_decomp_setup(void)
                uart_is_pxa = 0;
        }
 }
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 402874f9021f..e848c4607baf 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -443,7 +443,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
        .nr_irqs        = LITTLETON_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = littleton_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 1a63eaa89867..1255ee00f3d1 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -503,7 +503,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
        .nr_irqs        = LPD270_NR_IRQS,
        .init_irq       = lpd270_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = lpd270_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 553056d9a3c5..d8a1be619f21 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -650,7 +650,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
        .nr_irqs        = LUBBOCK_NR_IRQS,
        .init_irq       = lubbock_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = lubbock_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index f7922404d941..f44532fc648b 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -774,6 +774,6 @@ MACHINE_START(MAGICIAN, "HTC Magician")
        .init_irq = pxa27x_init_irq,
        .handle_irq = pxa27x_handle_irq,
        .init_machine = magician_init,
-        .timer = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index f27a61ee7ac7..7a12c1ba90ff 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -714,7 +714,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
        .nr_irqs        = MAINSTONE_NR_IRQS,
        .init_irq       = mainstone_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = mainstone_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 2831308dba68..f8979b943cbf 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -762,6 +762,6 @@ MACHINE_START(MIOA701, "MIO A701")
        .init_irq       = &pxa27x_init_irq,
        .handle_irq     = &pxa27x_handle_irq,
        .init_machine   = mioa701_machine_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = mioa701_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 152efbf093f6..854f1f562d6b 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -93,7 +93,7 @@ static void __init mp900c_init(void)
 /* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
 MACHINE_START(NEC_MP900, "MobilePro900/C")
        .atag_offset    = 0x220100,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .map_io         = pxa25x_map_io,
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 8bcc96e3b0db..909b713e5789 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -347,7 +347,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmld_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5ca7b904a30e..5033fd07968f 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -208,7 +208,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmt5_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index ca924cfedfc0..100b176f7e88 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -542,7 +542,7 @@ MACHINE_START(PALMTC, "Palm Tungsten|C")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmtc_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 32e0d7998355..0742721ced2d 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -363,7 +363,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmte2_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 3f3c48f2f7ce..d82a50b4a803 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -98,9 +98,6 @@ static unsigned long treo_pin_config[] __initdata = {
        GPIO96_KP_MKOUT_6,
        GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,        /* Hotsync button */
-        /* LCD */
-        GPIOxx_LCD_TFT_16BPP,
        /* Quick Capture Interface */
        GPIO84_CIF_FV,
        GPIO85_CIF_LV,
@@ -140,6 +137,12 @@ static unsigned long treo680_pin_config[] __initdata = {
        /* MATRIX KEYPAD - different wake up source */
        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
        GPIO99_KP_MKIN_5,
+        /* LCD... L_BIAS alt fn not configured on Treo680; is GPIO instead */
+        GPIOxx_LCD_16BPP,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
 };
 #endif /* CONFIG_MACH_TREO680 */
@@ -155,13 +158,16 @@ static unsigned long centro685_pin_config[] __initdata = {
        /* MATRIX KEYPAD - different wake up source */
        GPIO100_KP_MKIN_0,
        GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+        /* LCD */
+        GPIOxx_LCD_TFT_16BPP,
 };
 #endif /* CONFIG_MACH_CENTRO */
 /******************************************************************************
 * GPIO keyboard
 ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_PXA27x)
 static unsigned int treo680_matrix_keys[] = {
        KEY(0, 0, KEY_F8),              /* Red/Off/Power */
        KEY(0, 1, KEY_LEFT),
@@ -309,7 +315,7 @@ static inline void palmtreo_kpc_init(void) {}
 /******************************************************************************
 * USB host
 ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
 static struct pxaohci_platform_data treo680_ohci_info = {
        .port_mode    = PMM_PERPORT_MODE,
        .flags        = ENABLE_PORT1 | ENABLE_PORT3,
@@ -328,7 +334,6 @@ static inline void palmtreo_uhc_init(void) {}
 /******************************************************************************
 * Vibra and LEDs
 ******************************************************************************/
-#ifdef CONFIG_MACH_TREO680
 static struct gpio_led treo680_gpio_leds[] = {
        {
                .name                   = "treo680:vibra:vibra",
@@ -379,20 +384,46 @@ static struct gpio_led_platform_data centro_gpio_led_info = {
 static struct platform_device palmtreo_leds = {
        .name   = "leds-gpio",
        .id     = -1,
-        .dev    = {
-                .platform_data  = &treo680_gpio_led_info,
-        }
 };
 static void __init palmtreo_leds_init(void)
 {
        if (machine_is_centro())
                palmtreo_leds.dev.platform_data = &centro_gpio_led_info;
+        else if (machine_is_treo680())
+                palmtreo_leds.dev.platform_data = &treo680_gpio_led_info;
        platform_device_register(&palmtreo_leds);
 }
+/******************************************************************************
+ * diskonchip docg4 flash
+ ******************************************************************************/
+#if defined(CONFIG_MACH_TREO680)
+/* REVISIT: does the centro have this device also? */
+#if IS_ENABLED(CONFIG_MTD_NAND_DOCG4)
+static struct resource docg4_resources[] = {
+        {
+                .start  = 0x00000000,
+                .end    = 0x00001FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device treo680_docg4_flash = {
+        .name   = "docg4",
+        .id     = -1,
+        .resource = docg4_resources,
+        .num_resources = ARRAY_SIZE(docg4_resources),
+};
+static void __init treo680_docg4_flash_init(void)
+{
+        platform_device_register(&treo680_docg4_flash);
+}
 #else
-static inline void palmtreo_leds_init(void) {}
+static inline void treo680_docg4_flash_init(void) {}
+#endif
 #endif
 /******************************************************************************
@@ -424,12 +455,62 @@ static void __init palmphone_common_init(void)
 }
 #ifdef CONFIG_MACH_TREO680
+void __init treo680_gpio_init(void)
+{
+        unsigned int gpio;
+        /* drive all three lcd gpios high initially */
+        const unsigned long lcd_flags = GPIOF_INIT_HIGH | GPIOF_DIR_OUT;
+        /*
+         * LCD GPIO initialization...
+         */
+        /*
+         * This is likely the power to the lcd.  Toggling it low/high appears to
+         * turn the lcd off/on.  Can be toggled after lcd is initialized without
+         * any apparent adverse effects to the lcd operation.  Note that this
+         * gpio line is used by the lcd controller as the L_BIAS signal, but
+         * treo680 configures it as gpio.
+         */
+        gpio = GPIO_NR_TREO680_LCD_POWER;
+        if (gpio_request_one(gpio, lcd_flags, "LCD power") < 0)
+                goto fail;
+        /*
+         * These two are called "enables", for lack of a better understanding.
+         * If either of these are toggled after the lcd is initialized, the
+         * image becomes degraded.  N.B. The IPL shipped with the treo
+         * configures GPIO_NR_TREO680_LCD_EN_N as output and drives it high.  If
+         * the IPL is ever reprogrammed, this initialization may be need to be
+         * revisited.
+         */
+        gpio = GPIO_NR_TREO680_LCD_EN;
+        if (gpio_request_one(gpio, lcd_flags, "LCD enable") < 0)
+                goto fail;
+        gpio = GPIO_NR_TREO680_LCD_EN_N;
+        if (gpio_request_one(gpio, lcd_flags, "LCD enable_n") < 0)
+                goto fail;
+        /* driving this low turns LCD on */
+        gpio_set_value(GPIO_NR_TREO680_LCD_EN_N, 0);
+        return;
+ fail:
+        pr_err("gpio %d initialization failed\n", gpio);
+        gpio_free(GPIO_NR_TREO680_LCD_POWER);
+        gpio_free(GPIO_NR_TREO680_LCD_EN);
+        gpio_free(GPIO_NR_TREO680_LCD_EN_N);
+}
 static void __init treo680_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
        palmphone_common_init();
+        treo680_gpio_init();
        palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
                        GPIO_NR_TREO680_SD_POWER, 0);
+        treo680_docg4_flash_init();
 }
 #endif
@@ -451,7 +532,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = treo680_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -465,7 +546,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq       = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = centro_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 8b4366628a12..627c93a7364c 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -366,7 +366,7 @@ MACHINE_START(PALMTX, "Palm T|X")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmtx_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 8cdd4f58e253..18b7fcd98592 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -404,7 +404,7 @@ MACHINE_START(PALMZ72, "Palm Zire72")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = palmz72_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index fe9054435b6f..69918c7e3f1f 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -263,7 +263,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
        .nr_irqs        = PCM027_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = pcm027_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 2910bb935c75..50ccd5f1d560 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -469,7 +469,7 @@ MACHINE_START(POODLE, "SHARP Poodle")
        .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = poodle_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
index c9192cea0033..3835979a0dd3 100644
--- a/arch/arm/mach-pxa/pxa-dt.c
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -55,7 +55,7 @@ DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
        .map_io         = pxa3xx_map_io,
        .init_irq       = pxa3xx_dt_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
        .init_machine   = pxa3xx_dt_init,
        .dt_compat      = pxa3xx_dt_board_compat,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 616cb87b6179..3203a9f5b4a2 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -53,17 +53,25 @@ static unsigned long ac97_reset_config[] = {
        GPIO95_AC97_nRESET,
 };
-void pxa27x_assert_ac97reset(int reset_gpio, int on)
+void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
 {
+        /*
+         * This helper function is used to work around a bug in the pxa27x's
+         * ac97 controller during a warm reset.  The configuration of the
+         * reset_gpio is changed as follows:
+         * to_gpio == true: configured to generic output gpio and driven high
+         * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
+         */
        if (reset_gpio == 113)
-                pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
+                pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
-                                       &ac97_reset_config[1], 1);
+                                  &ac97_reset_config[1], 1);
        if (reset_gpio == 95)
-                pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
+                pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
-                                       &ac97_reset_config[3], 1);
+                                  &ac97_reset_config[3], 1);
 }
-EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
+EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
 /* Crystal clock: 13MHz */
 #define BASE_CLK        13000000
@@ -230,6 +238,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
        INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
        INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 25b08bfa997b..af41888acbd6 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1095,7 +1095,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1108,7 +1108,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1121,7 +1121,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 08d87a5d2639..710c493eac89 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -601,7 +601,7 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq       = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = saar_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index 79923058d10f..f38aa890b2c9 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void)
        __raw_writel(csadrcfg[1], CSADRCFG1);
        __raw_writel(csadrcfg[2], CSADRCFG2);
        __raw_writel(csadrcfg[3], CSADRCFG3);
+        /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
+        __raw_writel(0x2, CSMSADRCFG);
 }
 static struct syscore_ops smemc_syscore_ops = {
@@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = {
 static int __init smemc_init(void)
 {
-        if (cpu_is_pxa3xx())
+        if (cpu_is_pxa3xx()) {
+                /*
+                 * The only documentation we have on the
+                 * Chip Select Configuration Register (CSMSADRCFG) is that
+                 * it must be programmed to 0x2.
+                 * Moreover, in the bit definitions, the second bit
+                 * (CSMSADRCFG[1]) is called "SETALWAYS".
+                 * Other bits are reserved in this register.
+                 */
+                __raw_writel(0x2, CSMSADRCFG);
                register_syscore_ops(&smemc_syscore_ops);
+        }
        return 0;
 }
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 2073f0e6db0d..362726c49c70 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -732,7 +732,7 @@ static inline void spitz_lcd_init(void) {}
 #endif
 /******************************************************************************
- * Framebuffer
+ * NAND Flash
 ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
 static struct mtd_partition spitz_nand_partitions[] = {
@@ -858,7 +858,7 @@ static inline void spitz_nor_init(void) {}
 #endif
 /******************************************************************************
- * GPIO expander
+ * I2C devices
 ******************************************************************************/
 #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
 static struct pca953x_platform_data akita_pca953x_pdata = {
@@ -986,7 +986,7 @@ MACHINE_START(SPITZ, "SHARP Spitz")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = spitz_restart,
 MACHINE_END
 #endif
@@ -1000,7 +1000,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = spitz_restart,
 MACHINE_END
 #endif
@@ -1014,7 +1014,7 @@ MACHINE_START(AKITA, "SHARP Akita")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = spitz_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 456560b5aad4..88fde43c948c 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -1006,7 +1006,7 @@ MACHINE_START(INTELMOTE2, "IMOTE 2")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = imote2_init,
        .atag_offset    = 0x100,
        .restart        = pxa_restart,
@@ -1019,7 +1019,7 @@ MACHINE_START(STARGATE2, "Stargate 2")
        .nr_irqs = STARGATE_NR_IRQS,
        .init_irq = pxa27x_init_irq,
        .handle_irq = pxa27x_handle_irq,
-        .timer = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine = stargate2_init,
        .atag_offset = 0x100,
        .restart        = pxa_restart,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 1a25f8a7b0ce..f55979c09a5f 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -494,7 +494,7 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq       = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = tavorevb_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 4bc47d63698b..8f1ee92aea30 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -89,48 +89,10 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
        }
 }
-static struct clock_event_device ckevt_pxa_osmr0 = {
-        .name           = "osmr0",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_next_event = pxa_osmr0_set_next_event,
-        .set_mode       = pxa_osmr0_set_mode,
-};
-static struct irqaction pxa_ost0_irq = {
-        .name           = "ost0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = pxa_ost0_interrupt,
-        .dev_id         = &ckevt_pxa_osmr0,
-};
-static void __init pxa_timer_init(void)
-{
-        unsigned long clock_tick_rate = get_clock_tick_rate();
-        writel_relaxed(0, OIER);
-        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
-        setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
-        clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
-        ckevt_pxa_osmr0.max_delta_ns =
-                clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
-        ckevt_pxa_osmr0.min_delta_ns =
-                clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
-        ckevt_pxa_osmr0.cpumask = cpumask_of(0);
-        setup_irq(IRQ_OST0, &pxa_ost0_irq);
-        clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
-                clocksource_mmio_readl_up);
-        clockevents_register_device(&ckevt_pxa_osmr0);
-}
 #ifdef CONFIG_PM
 static unsigned long osmr[4], oier, oscr;
-static void pxa_timer_suspend(void)
+static void pxa_timer_suspend(struct clock_event_device *cedev)
 {
        osmr[0] = readl_relaxed(OSMR0);
        osmr[1] = readl_relaxed(OSMR1);
@@ -140,7 +102,7 @@ static void pxa_timer_suspend(void)
        oscr = readl_relaxed(OSCR);
 }
-static void pxa_timer_resume(void)
+static void pxa_timer_resume(struct clock_event_device *cedev)
 {
        /*
         * Ensure that we have at least MIN_OSCR_DELTA between match
@@ -163,8 +125,38 @@ static void pxa_timer_resume(void)
 #define pxa_timer_resume NULL
 #endif
-struct sys_timer pxa_timer = {
+static struct clock_event_device ckevt_pxa_osmr0 = {
-        .init           = pxa_timer_init,
+        .name           = "osmr0",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .set_next_event = pxa_osmr0_set_next_event,
+        .set_mode       = pxa_osmr0_set_mode,
        .suspend        = pxa_timer_suspend,
        .resume         = pxa_timer_resume,
 };
+static struct irqaction pxa_ost0_irq = {
+        .name           = "ost0",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = pxa_ost0_interrupt,
+        .dev_id         = &ckevt_pxa_osmr0,
+};
+void __init pxa_timer_init(void)
+{
+        unsigned long clock_tick_rate = get_clock_tick_rate();
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
+        setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
+        ckevt_pxa_osmr0.cpumask = cpumask_of(0);
+        setup_irq(IRQ_OST0, &pxa_ost0_irq);
+        clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
+                clocksource_mmio_readl_up);
+        clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
+                MIN_OSCR_DELTA * 2, 0x7fffffff);
+}
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 233629edf7ee..3d91d2e5bf3a 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -927,8 +927,6 @@ static void tosa_restart(char mode, const char *cmd)
 static void __init tosa_init(void)
 {
-        int dummy;
        pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
        pxa_set_ffuart_info(NULL);
@@ -947,10 +945,6 @@ static void __init tosa_init(void)
        /* enable batt_fault */
        PMCR = 0x01;
-        dummy = gpiochip_reserve(TOSA_SCOOP_GPIO_BASE, 12);
-        dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12);
-        dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
        pxa_set_mci_info(&tosa_mci_platform_data);
        pxa_set_ficp_info(&tosa_ficp_platform_data);
        pxa_set_i2c_info(NULL);
@@ -982,6 +976,6 @@ MACHINE_START(TOSA, "SHARP Tosa")
        .init_irq       = pxa25x_init_irq,
        .handle_irq       = pxa25x_handle_irq,
        .init_machine   = tosa_init,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = tosa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index fbbcbed4d1d4..c58043462acd 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -561,7 +561,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
@@ -573,6 +573,6 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index c773e4dded64..9c363c081d3f 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -997,7 +997,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = viper_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = viper_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 491b6c9a2a9b..aa89488f961e 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -719,7 +719,7 @@ MACHINE_START(VPAC270, "Voipac PXA270")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = vpac270_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 4275713ccd10..13b1d4586d7d 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -185,7 +185,7 @@ MACHINE_START(XCEP, "Iskratel XCEP")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 97529face7aa..989903a7e467 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -722,7 +722,7 @@ MACHINE_START(ZIPIT2, "Zipit Z2")
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = z2_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index abd3aa145083..f5d436434566 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -910,7 +910,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
        .nr_irqs        = ZEUS_NR_IRQS,
        .init_irq       = zeus_init_irq,
        .handle_irq     = pxa27x_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = zeus_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 226279fac9d4..1f00d650ac27 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -428,7 +428,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
        .nr_irqs        = ZYLONITE_NR_IRQS,
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
+        .init_time      = pxa_timer_init,
        .init_machine   = zylonite_init,
        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 682467480588..1d5ee5c9a1dc 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -42,7 +42,6 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/hardware/gic.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index d6b5073692d2..44754230fdcc 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -115,7 +115,7 @@
 /*
 * Only define NR_IRQS if less than NR_IRQS_EB
 */
-#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
+#define NR_IRQS_EB              (IRQ_EB_GIC_START + 128)
 #if defined(CONFIG_MACH_REALVIEW_EB) \
        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h
index 83050378ffd2..cfa30d21783b 100644
--- a/arch/arm/mach-realview/include/mach/uncompress.h
+++ b/arch/arm/mach-realview/include/mach/uncompress.h
@@ -75,4 +75,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 300f7064465d..98e3052b7933 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -14,7 +14,6 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
@@ -59,8 +58,6 @@ static void __init realview_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 28511d43637a..5b1c8bfe6fa9 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -27,13 +27,13 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/smp_twd.h>
@@ -418,10 +418,6 @@ static void __init realview_eb_timer_init(void)
        realview_eb_twd_init();
 }
-static struct sys_timer realview_eb_timer = {
-        .init           = realview_eb_timer_init,
-};
 static void realview_eb_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
@@ -472,8 +468,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
        .map_io         = realview_eb_map_io,
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
-        .timer          = &realview_eb_timer,
+        .init_time      = realview_eb_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 07d6672ddae7..d5e83a1f6982 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -29,13 +29,13 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -329,10 +329,6 @@ static void __init realview_pb1176_timer_init(void)
        realview_timer_init(IRQ_DC1176_TIMER0);
 }
-static struct sys_timer realview_pb1176_timer = {
-        .init           = realview_pb1176_timer_init,
-};
 static void realview_pb1176_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
@@ -384,8 +380,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
        .map_io         = realview_pb1176_map_io,
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
-        .timer          = &realview_pb1176_timer,
+        .init_time      = realview_pb1176_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 7ed53d75350f..c3cfe213b5e6 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -27,13 +27,13 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/smp_twd.h>
@@ -316,10 +316,6 @@ static void __init realview_pb11mp_timer_init(void)
        realview_pb11mp_twd_init();
 }
-static struct sys_timer realview_pb11mp_timer = {
-        .init           = realview_pb11mp_timer_init,
-};
 static void realview_pb11mp_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
@@ -367,8 +363,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
        .map_io         = realview_pb11mp_map_io,
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
-        .timer          = &realview_pb11mp_timer,
+        .init_time      = realview_pb11mp_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 9992431b8a15..dde652a59620 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -27,12 +27,12 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -264,10 +264,6 @@ static void __init realview_pba8_timer_init(void)
        realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
-static struct sys_timer realview_pba8_timer = {
-        .init           = realview_pba8_timer_init,
-};
 static void realview_pba8_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
@@ -308,8 +304,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
        .map_io         = realview_pba8_map_io,
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
-        .timer          = &realview_pba8_timer,
+        .init_time      = realview_pba8_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 4f486f05108a..54f0185b01e3 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -26,13 +26,13 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -324,10 +324,6 @@ static void __init realview_pbx_timer_init(void)
        realview_pbx_twd_init();
 }
-static struct sys_timer realview_pbx_timer = {
-        .init           = realview_pbx_timer_init,
-};
 static void realview_pbx_fixup(struct tag *tags, char **from,
                               struct meminfo *meminfo)
 {
@@ -404,8 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
        .map_io         = realview_pbx_map_io,
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
-        .timer          = &realview_pbx_timer,
+        .init_time      = realview_pbx_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 9cd9bcdad6cc..0fd4b0b8ef22 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -189,8 +189,3 @@ static void arch_decomp_setup(void)
        if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
 }
 #endif
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index f3fa259ce01f..a302cf5e0fc7 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -211,7 +211,7 @@ static void rpc_restart(char mode, const char *cmd)
        soft_restart(0);
 }
-extern struct sys_timer ioc_timer;
+void ioc_timer_init(void);
 MACHINE_START(RISCPC, "Acorn-RiscPC")
        /* Maintainer: Russell King */
@@ -220,6 +220,6 @@ MACHINE_START(RISCPC, "Acorn-RiscPC")
        .reserve_lp1    = 1,
        .map_io         = rpc_map_io,
        .init_irq       = rpc_init_irq,
-        .timer          = &ioc_timer,
+        .init_time      = ioc_timer_init,
        .restart        = rpc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index 581fca934bb3..9a6def14df01 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -24,7 +24,7 @@
 #include <asm/mach/time.h>
-unsigned long ioc_timer_gettimeoffset(void)
+static u32 ioc_timer_gettimeoffset(void)
 {
        unsigned int count1, count2, status;
        long offset;
@@ -56,7 +56,7 @@ unsigned long ioc_timer_gettimeoffset(void)
        }
        offset = (LATCH - offset) * (tick_nsec / 1000);
-        return (offset + LATCH/2) / LATCH;
+        return ((offset + LATCH/2) / LATCH) * 1000;
 }
 void __init ioctime_init(void)
@@ -82,14 +82,9 @@ static struct irqaction ioc_timer_irq = {
 /*
 * Set up timer interrupt.
 */
-static void __init ioc_timer_init(void)
+void __init ioc_timer_init(void)
 {
+        arch_gettimeoffset = ioc_timer_gettimeoffset;
        ioctime_init();
        setup_irq(IRQ_TIMER0, &ioc_timer_irq);
 }
-struct sys_timer ioc_timer = {
-        .init           = ioc_timer_init,
-        .offset         = ioc_timer_gettimeoffset,
-};
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
deleted file mode 100644
index 68d89cb96af0..000000000000
--- a/arch/arm/mach-s3c2410/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-# cpu frequency scaling support
-config S3C2410_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2410
-config S3C2410_PLLTABLE
-        bool
-        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
-        default y
-        help
-          Select the PLL table for the S3C2410
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
deleted file mode 100644
index 6b9a316e0041..000000000000
--- a/arch/arm/mach-s3c2410/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# arch/arm/mach-s3c2410/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
-obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
deleted file mode 100644
index 495f6928cbaa..000000000000
--- a/arch/arm/mach-s3c2412/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-# Note, the S3C2412 IOtiming support is in plat-s3c24xx
-config S3C2412_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
-        default y
-        select S3C2412_IOTIMING
-        help
-          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
deleted file mode 100644
index 41a6c279fb2f..000000000000
--- a/arch/arm/mach-s3c2412/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# arch/arm/mach-s3c2412/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
deleted file mode 100644
index 4526f6ba31a8..000000000000
--- a/arch/arm/mach-s3c2412/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/gpio.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * http://armlinux.simtec.co.uk/.
- *
- * S3C2412/S3C2413 specific GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/hardware.h>
-#include <plat/gpio-core.h>
-int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-        unsigned long flags;
-        unsigned long slpcon;
-        offs *= 2;
-        if (pin < S3C2410_GPB(0))
-                return -EINVAL;
-        if (pin >= S3C2410_GPF(0) &&
-            pin <= S3C2410_GPG(16))
-                return -EINVAL;
-        if (pin > S3C2410_GPH(16))
-                return -EINVAL;
-        local_irq_save(flags);
-        slpcon = __raw_readl(chip->base + 0x0C);
-        slpcon &= ~(3 << offs);
-        slpcon |= state << offs;
-        __raw_writel(slpcon, chip->base + 0x0C);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
deleted file mode 100644
index a4d7fd27bec5..000000000000
--- a/arch/arm/mach-s3c2440/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-config S3C2440_CPUFREQ
-        bool "S3C2440/S3C2442 CPU Frequency scaling support"
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
-        default y
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
-config S3C2440_XTAL_12000000
-        bool
-        help
-          Indicate that the build needs to support 12MHz system
-          crystal.
-config S3C2440_XTAL_16934400
-        bool
-        help
-          Indicate that the build needs to support 16.9344MHz system
-          crystal.
-config S3C2440_PLL_12000000
-        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
-        default y if CPU_FREQ_S3C24XX_PLL
-        help
-          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
-config S3C2440_PLL_16934400
-        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
-        default y if CPU_FREQ_S3C24XX_PLL
-        help
-          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
deleted file mode 100644
index c46092439814..000000000000
--- a/arch/arm/mach-s3c2440/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# arch/arm/mach-s3c2440/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-obj-$(CONFIG_CPU_S3C2440)       += dsc.o
-obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
-obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
-obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
deleted file mode 100644
index 9ea66e31f626..000000000000
--- a/arch/arm/mach-s3c2440/dsc.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/dsc.c
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C2440 Drive Strength Control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
-#include <plat/cpu.h>
-#include <plat/s3c244x.h>
-int s3c2440_set_dsc(unsigned int pin, unsigned int value)
-{
-        void __iomem *base;
-        unsigned long val;
-        unsigned long flags;
-        unsigned long mask;
-        base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
-        mask = 3 << S3C2440_DSC_GETSHIFT(pin);
-        local_irq_save(flags);
-        val = __raw_readl(base);
-        val &= ~mask;
-        val |= value & mask;
-        __raw_writel(val, base);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(s3c2440_set_dsc);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 25df14a9e268..37f513d1588e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -9,6 +9,15 @@
 if ARCH_S3C24XX
+config PLAT_S3C24XX
+        def_bool y
+        select ARCH_REQUIRE_GPIOLIB
+        select NO_IOPORT
+        select S3C_DEV_NAND
+        select IRQ_DOMAIN
+        help
+          Base platform code for any Samsung S3C24XX device
 menu "SAMSUNG S3C24XX SoCs Support"
 comment "S3C24XX SoCs"
@@ -83,6 +92,17 @@ config CPU_S3C2443
 # common code
+config S3C2410_CLOCK
+        bool
+        help
+          Clock code for the S3C2410, and similar processors which
+          is currently includes the S3C2410, S3C2440, S3C2442.
+config S3C24XX_DCLK
+        bool
+        help
+          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
 config S3C24XX_SMDK
        bool
        help
@@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
        help
          Compile in platform device definition for Samsung TouchScreen.
+config S3C24XX_DMA
+        bool "S3C2410 DMA support"
+        depends on ARCH_S3C24XX
+        select S3C_DMA
+        help
+          S3C2410 DMA support. This is needed for drivers like sound which
+          use the S3C2410's DMA system to move data to and from the
+          peripheral blocks.
+config S3C2410_DMA_DEBUG
+        bool "S3C2410 DMA support debug"
+        depends on ARCH_S3C24XX && S3C2410_DMA
+        help
+          Enable debugging output for the DMA code. This option sends info
+          to the kernel log, at priority KERN_DEBUG.
 config S3C2410_DMA
        bool
        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -123,10 +159,92 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
+# low-level serial option nodes
+config CPU_LLSERIAL_S3C2410_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
+config CPU_LLSERIAL_S3C2440_ONLY
+        bool
+        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
+config CPU_LLSERIAL_S3C2410
+        bool
+        help
+          Selected if there is an S3C2410 (or register compatible) serial
+          low-level implementation needed
+config CPU_LLSERIAL_S3C2440
+        bool
+        help
+          Selected if there is an S3C2440 (or register compatible) serial
+          low-level implementation needed
+# gpio configurations
+config S3C24XX_GPIO_EXTRA
+        int
+        default 128 if S3C24XX_GPIO_EXTRA128
+        default 64 if S3C24XX_GPIO_EXTRA64
+        default 16 if ARCH_H1940
+        default 0
+config S3C24XX_GPIO_EXTRA64
+        bool
+        help
+          Add an extra 64 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+config S3C24XX_GPIO_EXTRA128
+        bool
+        help
+          Add an extra 128 gpio numbers to the available GPIO pool. This is
+          available for boards that need extra gpios for external devices.
+# cpu frequency items common between s3c2410 and s3c2440/s3c2442
+config S3C2410_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select io timing code that is common to the s3c2410
+          and s3c2440/s3c2442 cpu frequency support.
+config S3C2410_CPUFREQ_UTILS
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select timing code that is common to the s3c2410
+          and s3c2440/s3c244 cpu frequency support.
+# cpu frequency support common to s3c2412, s3c2413 and s3c2442
+config S3C2412_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        help
+          Intel node to select io timing code that is common to the s3c2412
+          and the s3c2443.
 # cpu-specific sections
 if CPU_S3C2410
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+config S3C2410_PLL
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
 config S3C24XX_SIMTEC_NOR
        bool
        help
@@ -226,6 +344,7 @@ config MACH_QT2410
 config ARCH_SMDK2410
        bool "SMDK2410/A9M2410"
        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the SMDK2410 or the derived module A9M2410
          <http://www.fsforth.de>
@@ -266,6 +385,14 @@ config CPU_S3C2412_ONLY
                   !CPU_S3C2443 && CPU_S3C2412
        default y
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        default y
+        select S3C2412_IOTIMING
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
 config S3C2412_DMA
        bool
        help
@@ -273,6 +400,7 @@ config S3C2412_DMA
 config S3C2412_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2412 power management
@@ -291,8 +419,8 @@ config MACH_JIVE
          Say Y here if you are using the Logitech Jive.
 config MACH_JIVE_SHOW_BOOTLOADER
-        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
+        bool "Allow access to bootloader partitions in MTD"
-        depends on MACH_JIVE && EXPERIMENTAL
+        depends on MACH_JIVE
 config MACH_S3C2413
        bool
@@ -365,11 +493,45 @@ endif	# CPU_S3C2416
 if CPU_S3C2440
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        default y
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
 config S3C2440_DMA
        bool
        help
          Support for S3C2440 specific DMA code5A
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
 comment "S3C2440 Boards"
 #
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 0ab6ab15da4c..af53d27d5c36 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,26 +14,32 @@ obj-				:=
 # core
-obj-y                           += common.o
+obj-y                           += common.o irq.o
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o irq-s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o clock-s3c2443.o
 # PM
@@ -41,9 +47,21 @@ obj-$(CONFIG_PM)		+= pm.o irq-pm.o sleep.o
 # common code
+obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
+obj-$(CONFIG_S3C24XX_DMA)       += dma.o
+obj-$(CONFIG_S3C2410_CLOCK)     += clock-s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
+obj-$(CONFIG_S3C2410_IOTIMING)  += iotiming-s3c2410.o
+obj-$(CONFIG_S3C2412_IOTIMING)  += iotiming-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpufreq.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
 #
 # machine support
 # following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c24xx/anubis.h
new file mode 100644
index 000000000000..2691665f27d9
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/anubis.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ * ANUBIS - IRQ Number definitions
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_ANUBIS_H
+#define __MACH_S3C24XX_ANUBIS_H __FILE__
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+/* IDREG - revision */
+#define ANUBIS_IDREG_REVMASK            (0x7)
+/* irq */
+#define ANUBIS_IRQ_IDE0                 IRQ_EINT2
+#define ANUBIS_IRQ_IDE1                 IRQ_EINT3
+#define ANUBIS_IRQ_ASIX                 IRQ_EINT1
+/* map */
+/* start peripherals off after the S3C2410 */
+#define ANUBIS_IOADDR(x)                (S3C2410_ADDR((x) + 0x01800000))
+#define ANUBIS_PA_CPLD                  (S3C2410_CS1 | (1<<26))
+/* we put the CPLD registers next, to get them out of the way */
+#define ANUBIS_VA_CTRL1                 ANUBIS_IOADDR(0x00000000)
+#define ANUBIS_PA_CTRL1                 ANUBIS_PA_CPLD
+#define ANUBIS_VA_IDREG                 ANUBIS_IOADDR(0x00300000)
+#define ANUBIS_PA_IDREG                 (ANUBIS_PA_CPLD + (3 << 23))
+#define ANUBIS_IDEPRI                   ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX                ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC                   ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX                ANUBIS_IOADDR(0x01300000)
+#endif /* __MACH_S3C24XX_ANUBIS_H */
diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index ba02cf8d80a2..3f0288f2f542 100644
--- a/arch/arm/mach-s3c24xx/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
@@ -25,8 +25,8 @@
 #include <asm/mach/irq.h>
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
+#include "bast.h"
 /* IDE ports */
@@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = {
        .ioport_shift   = 5,
 };
-#define IDE_CS  S3C2410_CS5
 static struct resource bast_ide0_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
 };
 static struct platform_device bast_device_ide0 = {
@@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = {
 };
 static struct resource bast_ide1_resource[] = {
-        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
+        [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
-        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
+        [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE1),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
 };
 static struct platform_device bast_device_ide1 = {
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index ac7b2ad5c405..c0daa9590b4c 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -27,27 +27,20 @@
 #include <linux/device.h>
 #include <linux/io.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/irq.h>
+#include <mach/hardware.h>
 #include <mach/regs-irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
 #include <plat/irq.h>
-#if 0
+#include "bast.h"
-#include <asm/debug-ll.h>
-#endif
 #define irqdbf(x...)
 #define irqdbf2(x...)
 /* handle PC104 ISA interrupts from the system CPLD */
 /* table of ISA irq nos to the relevant mask... zero means
@@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data)
 static void
 bast_pc104_maskack(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_desc + IRQ_ISA;
+        struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
        bast_pc104_mask(data);
        desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq,
        if (unlikely(stat == 0)) {
                /* ack if we get an irq with nothing (ie, startup) */
-                desc = irq_desc + IRQ_ISA;
+                desc = irq_desc + BAST_IRQ_ISA;
                desc->irq_data.chip->irq_ack(&desc->irq_data);
        } else {
                /* handle the IRQ */
@@ -147,7 +140,7 @@ static __init int bast_irq_init(void)
                __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
-                irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
+                irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
                /* register our IRQs */
diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c24xx/bast.h
new file mode 100644
index 000000000000..5c7534bae92d
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/bast.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ * BAST - IRQ Number definitions
+ * BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_BAST_H
+#define __MACH_S3C24XX_BAST_H __FILE__
+/* CTRL1 - Audio LR routing */
+#define BAST_CPLD_CTRL1_LRCOFF          (0x00)
+#define BAST_CPLD_CTRL1_LRCADC          (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC          (0x02)
+#define BAST_CPLD_CTRL1_LRCARM          (0x03)
+#define BAST_CPLD_CTRL1_LRMASK          (0x03)
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+#define BAST_CPLD_CTRL2_WNAND           (0x04)
+#define BAST_CPLD_CTLR2_IDERST          (0x08)
+/* CTRL3 - rom write control, CPLD identity */
+#define BAST_CPLD_CTRL3_IDMASK          (0x0e)
+#define BAST_CPLD_CTRL3_ROMWEN          (0x01)
+/* CTRL4 - 8bit LCD interface control/status */
+#define BAST_CPLD_CTRL4_LLAT            (0x01)
+#define BAST_CPLD_CTRL4_LCDRW           (0x02)
+#define BAST_CPLD_CTRL4_LCDCMD          (0x04)
+#define BAST_CPLD_CTRL4_LCDE2           (0x01)
+/* CTRL5 - DMA routing */
+#define BAST_CPLD_DMA0_PRIIDE           (0)
+#define BAST_CPLD_DMA0_SECIDE           (1)
+#define BAST_CPLD_DMA0_ISA15            (2)
+#define BAST_CPLD_DMA0_ISA36            (3)
+#define BAST_CPLD_DMA1_PRIIDE           (0 << 2)
+#define BAST_CPLD_DMA1_SECIDE           (1 << 2)
+#define BAST_CPLD_DMA1_ISA15            (2 << 2)
+#define BAST_CPLD_DMA1_ISA36            (3 << 2)
+/* irq numbers to onboard peripherals */
+#define BAST_IRQ_USBOC                  IRQ_EINT18
+#define BAST_IRQ_IDE0                   IRQ_EINT16
+#define BAST_IRQ_IDE1                   IRQ_EINT17
+#define BAST_IRQ_PCSERIAL1              IRQ_EINT15
+#define BAST_IRQ_PCSERIAL2              IRQ_EINT14
+#define BAST_IRQ_PCPARALLEL             IRQ_EINT13
+#define BAST_IRQ_ASIX                   IRQ_EINT11
+#define BAST_IRQ_DM9000                 IRQ_EINT10
+#define BAST_IRQ_ISA                    IRQ_EINT9
+#define BAST_IRQ_SMALERT                IRQ_EINT8
+/* map */
+/*
+ * ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+#define BAST_IOADDR(x)                  (S3C2410_ADDR((x) + 0x01300000))
+/* we put the CPLD registers next, to get them out of the way */
+#define BAST_VA_CTRL1                   BAST_IOADDR(0x00000000)
+#define BAST_PA_CTRL1                   (S3C2410_CS5 | 0x7800000)
+#define BAST_VA_CTRL2                   BAST_IOADDR(0x00100000)
+#define BAST_PA_CTRL2                   (S3C2410_CS1 | 0x6000000)
+#define BAST_VA_CTRL3                   BAST_IOADDR(0x00200000)
+#define BAST_PA_CTRL3                   (S3C2410_CS1 | 0x6800000)
+#define BAST_VA_CTRL4                   BAST_IOADDR(0x00300000)
+#define BAST_PA_CTRL4                   (S3C2410_CS1 | 0x7000000)
+/* next, we have the PC104 ISA interrupt registers */
+#define BAST_PA_PC104_IRQREQ            (S3C2410_CS5 | 0x6000000)
+#define BAST_VA_PC104_IRQREQ            BAST_IOADDR(0x00400000)
+#define BAST_PA_PC104_IRQRAW            (S3C2410_CS5 | 0x6800000)
+#define BAST_VA_PC104_IRQRAW            BAST_IOADDR(0x00500000)
+#define BAST_PA_PC104_IRQMASK           (S3C2410_CS5 | 0x7000000)
+#define BAST_VA_PC104_IRQMASK           BAST_IOADDR(0x00600000)
+#define BAST_PA_LCD_RCMD1               (0x8800000)
+#define BAST_VA_LCD_RCMD1               BAST_IOADDR(0x00700000)
+#define BAST_PA_LCD_WCMD1               (0x8000000)
+#define BAST_VA_LCD_WCMD1               BAST_IOADDR(0x00800000)
+#define BAST_PA_LCD_RDATA1              (0x9800000)
+#define BAST_VA_LCD_RDATA1              BAST_IOADDR(0x00900000)
+#define BAST_PA_LCD_WDATA1              (0x9000000)
+#define BAST_VA_LCD_WDATA1              BAST_IOADDR(0x00A00000)
+#define BAST_PA_LCD_RCMD2               (0xA800000)
+#define BAST_VA_LCD_RCMD2               BAST_IOADDR(0x00B00000)
+#define BAST_PA_LCD_WCMD2               (0xA000000)
+#define BAST_VA_LCD_WCMD2               BAST_IOADDR(0x00C00000)
+#define BAST_PA_LCD_RDATA2              (0xB800000)
+#define BAST_VA_LCD_RDATA2              BAST_IOADDR(0x00D00000)
+#define BAST_PA_LCD_WDATA2              (0xB000000)
+#define BAST_VA_LCD_WDATA2              BAST_IOADDR(0x00E00000)
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+#define BAST_VA_MULTISPACE              (0xE0000000)
+#define BAST_VA_ISAIO                   (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM                  (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI                  (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX               (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC                  (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX               (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET                 (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000                  (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO                 (BAST_VA_MULTISPACE + 0x02600000)
+#define BAST_VAM_CS2                    (0x00000000)
+#define BAST_VAM_CS3                    (0x04000000)
+#define BAST_VAM_CS4                    (0x08000000)
+#define BAST_VAM_CS5                    (0x0C000000)
+/* physical offset addresses for the peripherals */
+#define BAST_PA_ISAIO                   (0x00000000)
+#define BAST_PA_ASIXNET                 (0x01000000)
+#define BAST_PA_SUPERIO                 (0x01800000)
+#define BAST_PA_IDEPRI                  (0x02000000)
+#define BAST_PA_IDEPRIAUX               (0x02800000)
+#define BAST_PA_IDESEC                  (0x03000000)
+#define BAST_PA_IDESECAUX               (0x03800000)
+#define BAST_PA_ISAMEM                  (0x04000000)
+#define BAST_PA_DM9000                  (0x05000000)
+/* some configurations for the peripherals */
+#define BAST_PCSIO                      (BAST_VA_SUPERIO + BAST_VAM_CS2)
+#define BAST_ASIXNET_CS                 BAST_VAM_CS5
+#define BAST_DM9000_CS                  BAST_VAM_CS4
+#define BAST_IDE_CS     S3C2410_CS5
+#endif /* __MACH_S3C24XX_BAST_H */
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
index f95d3268ae1f..1edd9b2369c5 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/mach-s3c24xx/clock-dclk.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
+/*
- *
 * Copyright (c) 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 25dc4d4397b1..641266f3d152 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/clock.c
+/*
- *
 * Copyright (c) 2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeb4a24ff3ed..f6b9f2ef01bd 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -132,7 +132,7 @@ static struct clk *clk_msysclk_sources[] = {
        [3] = &clk_mpllref,
 };
-struct clksrc_clk clk_msysclk = {
+static struct clksrc_clk clk_msysclk = {
        .clk    = {
                .name           = "msysclk",
                .parent         = &clk_xtal,
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 0c9e9a785ef6..6bcf87f65f9e 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
 static void s3c24xx_default_idle(void)
 {
-        unsigned long tmp;
+        unsigned long tmp = 0;
        int i;
        /* idle the system by using the idle mode which will wait for an
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index c2f596e7bc2d..ed6276fcaa3b 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -15,4 +15,6 @@
 void s3c2410_restart(char mode, const char *cmd);
 void s3c244x_restart(char mode, const char *cmd);
+extern struct syscore_ops s3c24xx_irq_syscore_ops;
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
index c7adad0e8de0..9b7b4289d66c 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+/*
- *
 * Copyright (c) 2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
index 5404535da1a5..cfa0dd8723ec 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/cpu-freq.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -81,7 +80,7 @@ static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
        cfg->divs.p_divisor = pdiv;
        cfg->divs.h_divisor = hdiv;
-        return 0      ;
+        return 0;
 }
 static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
@@ -131,7 +130,6 @@ static int __init s3c2410_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2410_cpufreq_interface);
 }
 arch_initcall(s3c2410_cpufreq_init);
 static int s3c2410a_cpufreq_add(struct device *dev,
@@ -159,5 +157,4 @@ static int __init s3c2410a_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2410a_cpufreq_interface);
 }
 arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
index 125be7d5fa60..8bf0f3a77476 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2412/cpu-freq.c
+/*
- *
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -26,12 +25,13 @@
 #include <asm/mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-s3c2412-mem.h>
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/cpu-freq-core.h>
+#include "s3c2412.h"
 /* our clock resources. */
 static struct clk *xtal;
 static struct clk *fclk;
@@ -111,7 +111,7 @@ static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
        return 0;
- invalid:
+invalid:
        return -EINVAL;
 }
@@ -255,5 +255,4 @@ static int s3c2412_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2412_cpufreq_interface);
 }
 arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
index 61776764d9f4..72b2cc8a5a85 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+/*
- *
 * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -310,5 +309,4 @@ static int s3c2442_cpufreq_init(void)
 {
        return subsys_interface_register(&s3c2442_cpufreq_interface);
 }
 subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 43ea80190d87..ddd8280e3875 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+/*
- *
 * Copyright (c) 2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -17,11 +16,12 @@
 #include <linux/io.h>
 #include <mach/map.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu-freq-core.h>
+#include "regs-mem.h"
 /**
 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
 * @cfg: The frequency configuration
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq.c
index 468079938884..5f181e733eee 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56e..25d085adc93c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920ff..d2408ba372cb 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84f..0b86e74d104f 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 2d94228d2866..05536254a3f8 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -27,7 +27,6 @@
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index ba3e76c95504..aab64909e9a3 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/dma.c
+/*
- *
 * Copyright 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/gta02.h
index 217393482153..9430a71e9184 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/gta02.h
@@ -1,5 +1,13 @@
-#ifndef _GTA02_H
+/*
-#define _GTA02_H
+ * GTA02 header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_GTA02_H
+#define __MACH_S3C24XX_GTA02_H __FILE__
 #include <mach/regs-gpio.h>
@@ -12,4 +20,4 @@
 #define GTA02_IRQ_PCF50633      IRQ_EINT9
-#endif /* _GTA02_H */
+#endif /* __MACH_S3C24XX_GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index 3f40c61b6e02..5b98bfd1df43 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -19,10 +19,10 @@
 #include <linux/gpio.h>
 #include <linux/rfkill.h>
-#include <mach/regs-gpio.h>
 #include <mach/hardware.h>
-#include <mach/h1940-latch.h>
+#include <mach/regs-gpio.h>
-#include <mach/h1940.h>
+#include "h1940.h"
 #define DRV_NAME "h1940-bt"
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/h1940.h
index fc897d3a056c..2950cc466840 100644
--- a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c24xx/h1940.h
@@ -1,20 +1,30 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+/*
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
 *
 * Copyright (c) 2005 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
- *  iPAQ H1940 series - latch definitions
+ * iPAQ H1940 series definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_H1940_LATCH_H
+#ifndef __MACH_S3C24XX_H1940_H
-#define __ASM_ARCH_H1940_LATCH_H
+#define __MACH_S3C24XX_H1940_H __FILE__
-#include <asm/gpio.h>
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+extern void h1940_pm_return(void);
+extern int h1940_led_blink_set(unsigned gpio, int state,
+                               unsigned long *delay_on,
+                               unsigned long *delay_off);
+#include <linux/gpio.h>
 #define H1940_LATCH_GPIO(x)             (S3C_GPIO_END + (x))
@@ -40,4 +50,4 @@
 #define H1940_LATCH_LED_GREEN           H1940_LATCH_GPIO(14)
 #define H1940_LATCH_LED_FLASH           H1940_LATCH_GPIO(15)
-#endif /* __ASM_ARCH_H1940_LATCH_H */
+#endif /* __MACH_S3C24XX_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
deleted file mode 100644
index 1b614d5a81f3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_ANUBISCPLD_H
-#define __ASM_ARCH_ANUBISCPLD_H
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-#define ANUBIS_CTRL1_NANDSEL            (0x3)
-/* IDREG - revision */
-#define ANUBIS_IDREG_REVMASK            (0x7)
-#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
deleted file mode 100644
index a2a328134e34..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  ANUBIS - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_ANUBISIRQ_H
-#define __ASM_ARCH_ANUBISIRQ_H
-#define IRQ_IDE0       IRQ_EINT2
-#define IRQ_IDE1       IRQ_EINT3
-#define IRQ_ASIX       IRQ_EINT1
-#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
deleted file mode 100644
index c9deb3a5b2c3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-#ifndef __ASM_ARCH_ANUBISMAP_H
-#define __ASM_ARCH_ANUBISMAP_H
-/* start peripherals off after the S3C2410 */
-#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
-#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
-/* we put the CPLD registers next, to get them out of the way */
-#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
-#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
-#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
-#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
-#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
-#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
-#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
deleted file mode 100644
index bee2a7a932a0..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * BAST - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_BASTCPLD_H
-#define __ASM_ARCH_BASTCPLD_H
-/* CTRL1 - Audio LR routing */
-#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
-#define BAST_CPLD_CTRL1_LRCADC      (0x01)
-#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
-#define BAST_CPLD_CTRL1_LRCARM      (0x03)
-#define BAST_CPLD_CTRL1_LRMASK      (0x03)
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-#define BAST_CPLD_CTRL2_WNAND       (0x04)
-#define BAST_CPLD_CTLR2_IDERST      (0x08)
-/* CTRL3 - rom write control, CPLD identity */
-#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
-#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
-/* CTRL4 - 8bit LCD interface control/status */
-#define BAST_CPLD_CTRL4_LLAT        (0x01)
-#define BAST_CPLD_CTRL4_LCDRW       (0x02)
-#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
-#define BAST_CPLD_CTRL4_LCDE2       (0x01)
-/* CTRL5 - DMA routing */
-#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
-#define BAST_CPLD_DMA0_SECIDE      (1<<0)
-#define BAST_CPLD_DMA0_ISA15       (2<<0)
-#define BAST_CPLD_DMA0_ISA36       (3<<0)
-#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
-#define BAST_CPLD_DMA1_SECIDE      (1<<2)
-#define BAST_CPLD_DMA1_ISA15       (2<<2)
-#define BAST_CPLD_DMA1_ISA36       (3<<2)
-#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
deleted file mode 100644
index cac428c42e7f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_BASTIRQ_H
-#define __ASM_ARCH_BASTIRQ_H
-/* irq numbers to onboard peripherals */
-#define IRQ_USBOC      IRQ_EINT18
-#define IRQ_IDE0       IRQ_EINT16
-#define IRQ_IDE1       IRQ_EINT17
-#define IRQ_PCSERIAL1  IRQ_EINT15
-#define IRQ_PCSERIAL2  IRQ_EINT14
-#define IRQ_PCPARALLEL IRQ_EINT13
-#define IRQ_ASIX       IRQ_EINT11
-#define IRQ_DM9000     IRQ_EINT10
-#define IRQ_ISA        IRQ_EINT9
-#define IRQ_SMALERT    IRQ_EINT8
-#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
deleted file mode 100644
index eecea2a50f8f..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-map.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-map.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-#ifndef __ASM_ARCH_BASTMAP_H
-#define __ASM_ARCH_BASTMAP_H
-#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
-/* we put the CPLD registers next, to get them out of the way */
-#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
-#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
-#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
-#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
-#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
-#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
-#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
-#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
-/* next, we have the PC104 ISA interrupt registers */
-#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
-#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
-#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
-#define BAST_PA_LCD_RCMD1     (0x8800000)
-#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
-#define BAST_PA_LCD_WCMD1     (0x8000000)
-#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
-#define BAST_PA_LCD_RDATA1    (0x9800000)
-#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
-#define BAST_PA_LCD_WDATA1    (0x9000000)
-#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
-#define BAST_PA_LCD_RCMD2     (0xA800000)
-#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
-#define BAST_PA_LCD_WCMD2     (0xA000000)
-#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
-#define BAST_PA_LCD_RDATA2    (0xB800000)
-#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
-#define BAST_PA_LCD_WDATA2    (0xB000000)
-#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x00000000 to 0x01000000 16MB ISA IO space
- * 0x01000000 to 0x02000000 16MB ISA memory space
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
- * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-#define BAST_VA_MULTISPACE (0xE0000000)
-#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
-#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
-#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
-#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
-#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
-#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
-#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
-#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
-#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
-#define BAST_VA_MULTISPACE (0xE0000000)
-#define BAST_VAM_CS2 (0x00000000)
-#define BAST_VAM_CS3 (0x04000000)
-#define BAST_VAM_CS4 (0x08000000)
-#define BAST_VAM_CS5 (0x0C000000)
-/* physical offset addresses for the peripherals */
-#define BAST_PA_ISAIO     (0x00000000)
-#define BAST_PA_ASIXNET   (0x01000000)
-#define BAST_PA_SUPERIO   (0x01800000)
-#define BAST_PA_IDEPRI    (0x02000000)
-#define BAST_PA_IDEPRIAUX (0x02800000)
-#define BAST_PA_IDESEC    (0x03000000)
-#define BAST_PA_IDESECAUX (0x03800000)
-#define BAST_PA_ISAMEM    (0x04000000)
-#define BAST_PA_DM9000    (0x05000000)
-/* some configurations for the peripherals */
-#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
-/*  */
-#define BAST_ASIXNET_CS  BAST_VAM_CS5
-#define BAST_IDE_CS      BAST_VAM_CS5
-#define BAST_DM9000_CS   BAST_VAM_CS4
-#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 4135de87d1f7..13ed33c69113 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -40,17 +40,17 @@
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
 1004:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                moveq   \rd, \rd, lsr #SHIFT_2440TXF
                tst     \rd, #S3C2410_UFSTAT_TXFULL
        .endm
        .macro  fifo_full_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S3C2410_UFSTAT_TXFULL
        .endm
@@ -68,18 +68,18 @@
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
 10000:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
        .endm
        .macro fifo_level_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
index 7615a14773fa..6a21beeba1da 100644
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -31,10 +31,10 @@
                @@ try the interrupt offset register, since it is there
-                ldr     \irqstat, [ \base, #INTPND ]
+                ldr     \irqstat, [\base, #INTPND ]
                teq     \irqstat, #0
                beq     1002f
-                ldr     \irqnr, [ \base, #INTOFFSET ]
+                ldr     \irqnr, [\base, #INTOFFSET ]
                mov     \tmp, #1
                tst     \irqstat, \tmp, lsl \irqnr
                bne     1001f
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
deleted file mode 100644
index c53ad34c6579..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
deleted file mode 100644
index 3890a05948fb..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - GPIO bank numbering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __MACH_GPIONRS_H
-#define __MACH_GPIONRS_H
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-#define S3C2410_GPIO_BANKG   (32*6)
-#define S3C2410_GPIO_BANKH   (32*7)
-/* GPIO sizes for various SoCs:
- *
- *             2442
- *   2410 2412 2440 2443 2416
- *   ---- ---- ---- ---- ----
- * A 23   22   25   16   25
- * B 11   11   11   11   9
- * C 16   15   16   16   16
- * D 16   16   16   16   16
- * E 16   16   16   16   16
- * F 8    8    8    8    8
- * G 16   16   16   16   8
- * H 11   11   9    15   15
- * J --   --   13   16   --
- * K --   --   --   --   16
- * L --   --   --   15   7
- * M --   --   --   2    2
- */
-/* GPIO bank sizes */
-#define S3C2410_GPIO_A_NR       (32)
-#define S3C2410_GPIO_B_NR       (32)
-#define S3C2410_GPIO_C_NR       (32)
-#define S3C2410_GPIO_D_NR       (32)
-#define S3C2410_GPIO_E_NR       (32)
-#define S3C2410_GPIO_F_NR       (32)
-#define S3C2410_GPIO_G_NR       (32)
-#define S3C2410_GPIO_H_NR       (32)
-#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
-#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
-#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
-#if CONFIG_S3C_GPIO_SPACE != 0
-#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
-#endif
-#define S3C2410_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
-#ifndef __ASSEMBLY__
-enum s3c_gpio_number {
-        S3C2410_GPIO_A_START = 0,
-        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
-        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
-        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
-        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
-        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
-        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
-        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
-        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
-        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
-        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
-        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
-};
-#endif /* __ASSEMBLY__ */
-/* S3C2410 GPIO number definitions. */
-#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
-#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
-#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
-#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
-#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
-#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
-#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
-#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
-#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
-#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
-#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
-#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
-#endif /* __MACH_GPIONRS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
deleted file mode 100644
index c410a078622c..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C2410 - GPIO core support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_GPIO_CORE_H
-#define __ASM_ARCH_GPIO_CORE_H __FILE__
-#include <mach/regs-gpio.h>
-extern struct samsung_gpio_chip s3c24xx_gpios[];
-static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip;
-        if (pin > S3C_GPIO_END)
-                return NULL;
-        chip = &s3c24xx_gpios[pin/32];
-        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
-}
-#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
index 6fac70f3484e..14591563ca70 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio.h
+/*
- *
 * Copyright (c) 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -15,6 +14,9 @@
 * devices that need GPIO.
 */
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H __FILE__
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
 #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
@@ -23,8 +25,83 @@
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
-#include <mach/gpio-nrs.h>
+/*
-#include <mach/gpio-fns.h>
+ * GPIO sizes for various SoCs:
+ *
+ *   2410 2412 2440 2443 2416
+ *             2442
+ *   ---- ---- ---- ---- ----
+ * A  23   22   25   16   25
+ * B  11   11   11   11   9
+ * C  16   15   16   16   16
+ * D  16   16   16   16   16
+ * E  16   16   16   16   16
+ * F  8    8    8    8    8
+ * G  16   16   16   16   8
+ * H  11   11   9    15   15
+ * J  --   --   13   16   --
+ * K  --   --   --   --   16
+ * L  --   --   --   15   7
+ * M  --   --   --   2    2
+ */
+/* GPIO bank sizes */
+#define S3C2410_GPIO_A_NR       (32)
+#define S3C2410_GPIO_B_NR       (32)
+#define S3C2410_GPIO_C_NR       (32)
+#define S3C2410_GPIO_D_NR       (32)
+#define S3C2410_GPIO_E_NR       (32)
+#define S3C2410_GPIO_F_NR       (32)
+#define S3C2410_GPIO_G_NR       (32)
+#define S3C2410_GPIO_H_NR       (32)
+#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
+#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
+#if CONFIG_S3C_GPIO_SPACE != 0
+#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
+#endif
+#define S3C2410_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
+#ifndef __ASSEMBLY__
+enum s3c_gpio_number {
+        S3C2410_GPIO_A_START = 0,
+        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
+        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
+        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
+        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
+        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
+        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
+        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
+        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
+        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
+        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
+};
+#endif /* __ASSEMBLY__ */
+/* S3C2410 GPIO number definitions. */
+#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
+#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
+#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
+#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
+#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
+#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
+#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
+#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
+#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
+#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
+#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
+#include <plat/gpio-cfg.h>
 #ifdef CONFIG_CPU_S3C244X
 #define S3C_GPIO_END    (S3C2410_GPJ(0) + 32)
@@ -33,3 +110,5 @@
 #else
 #define S3C_GPIO_END    (S3C2410_GPH(0) + 32)
 #endif
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
deleted file mode 100644
index 2aa683c8d3d6..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/h1940.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/h1940.h
- *
- * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
- *
- * H1940 definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_H1940_H
-#define __ASM_ARCH_H1940_H
-#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
-#define H1940_SUSPEND_RESUMEAT          (0x30081000)
-#define H1940_SUSPEND_CHECK             (0x30080000)
-extern void h1940_pm_return(void);
-extern int h1940_led_blink_set(unsigned gpio, int state,
-        unsigned long *delay_on, unsigned long *delay_off);
-#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac58..a6cc14a092fc 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -23,12 +23,6 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 #endif /* CONFIG_CPU_S3C2440 */
-#ifdef CONFIG_CPU_S3C2412
-extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
-#endif /* CONFIG_CPU_S3C2412 */
 #endif /* __ASSEMBLY__ */
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
deleted file mode 100644
index e9ddd706b16e..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/idle.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/idle.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU Idle controls
-*/
-#ifndef __ASM_ARCH_IDLE_H
-#define __ASM_ARCH_IDLE_H __FILE__
-/* This allows the over-ride of the default idle code, in case there
- * is any other things to be done over idle (like DVS)
-*/
-extern void (*s3c24xx_idle)(void);
-extern void s3c24xx_default_idle(void);
-#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
deleted file mode 100644
index e9e36b0abbac..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
- *
- * Copyright 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * OSIRIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_OSIRISCPLD_H
-#define __ASM_ARCH_OSIRISCPLD_H
-/* CTRL0 - NAND WP control */
-#define OSIRIS_CTRL0_NANDSEL            (0x3)
-#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
-#define OSIRIS_CTRL0_PCMCIA             (1<<4)
-#define OSIRIS_CTRL0_FIX8               (1<<5)
-#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
-#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
-#define OSIRIS_CTRL1_FIX8               (1<<0)
-#define OSIRIS_ID_REVMASK               (0x7)
-#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index a11a638bd599..c2ef016032ab 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -14,8 +14,6 @@
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H
-#include <mach/gpio-nrs.h>
 #define S3C24XX_MISCCR          S3C24XX_GPIOREG2(0x80)
 /* general configuration options */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Memory Control register definitions
-*/
-#ifndef __ASM_ARM_MEMREGS_H
-#define __ASM_ARM_MEMREGS_H
-#ifndef S3C2410_MEMREG
-#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-/* bus width, and wait state control */
-#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
-/* bank zero config - note, pinstrapped from OM pins! */
-#define S3C2410_BWSCON_DW0_16           (1<<1)
-#define S3C2410_BWSCON_DW0_32           (2<<1)
-/* bank one configs */
-#define S3C2410_BWSCON_DW1_8            (0<<4)
-#define S3C2410_BWSCON_DW1_16           (1<<4)
-#define S3C2410_BWSCON_DW1_32           (2<<4)
-#define S3C2410_BWSCON_WS1              (1<<6)
-#define S3C2410_BWSCON_ST1              (1<<7)
-/* bank 2 configurations */
-#define S3C2410_BWSCON_DW2_8            (0<<8)
-#define S3C2410_BWSCON_DW2_16           (1<<8)
-#define S3C2410_BWSCON_DW2_32           (2<<8)
-#define S3C2410_BWSCON_WS2              (1<<10)
-#define S3C2410_BWSCON_ST2              (1<<11)
-/* bank 3 configurations */
-#define S3C2410_BWSCON_DW3_8            (0<<12)
-#define S3C2410_BWSCON_DW3_16           (1<<12)
-#define S3C2410_BWSCON_DW3_32           (2<<12)
-#define S3C2410_BWSCON_WS3              (1<<14)
-#define S3C2410_BWSCON_ST3              (1<<15)
-/* bank 4 configurations */
-#define S3C2410_BWSCON_DW4_8            (0<<16)
-#define S3C2410_BWSCON_DW4_16           (1<<16)
-#define S3C2410_BWSCON_DW4_32           (2<<16)
-#define S3C2410_BWSCON_WS4              (1<<18)
-#define S3C2410_BWSCON_ST4              (1<<19)
-/* bank 5 configurations */
-#define S3C2410_BWSCON_DW5_8            (0<<20)
-#define S3C2410_BWSCON_DW5_16           (1<<20)
-#define S3C2410_BWSCON_DW5_32           (2<<20)
-#define S3C2410_BWSCON_WS5              (1<<22)
-#define S3C2410_BWSCON_ST5              (1<<23)
-/* bank 6 configurations */
-#define S3C2410_BWSCON_DW6_8            (0<<24)
-#define S3C2410_BWSCON_DW6_16           (1<<24)
-#define S3C2410_BWSCON_DW6_32           (2<<24)
-#define S3C2410_BWSCON_WS6              (1<<26)
-#define S3C2410_BWSCON_ST6              (1<<27)
-/* bank 7 configurations */
-#define S3C2410_BWSCON_DW7_8            (0<<28)
-#define S3C2410_BWSCON_DW7_16           (1<<28)
-#define S3C2410_BWSCON_DW7_32           (2<<28)
-#define S3C2410_BWSCON_WS7              (1<<30)
-#define S3C2410_BWSCON_ST7              (1<<31)
-/* accesor functions for getting BANK(n) configuration. (n != 0) */
-#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
-#define S3C2410_BWSCON_DW8              (0)
-#define S3C2410_BWSCON_DW16             (1)
-#define S3C2410_BWSCON_DW32             (2)
-#define S3C2410_BWSCON_WS               (1 << 2)
-#define S3C2410_BWSCON_ST               (1 << 3)
-/* memory set (rom, ram) */
-#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
-#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
-#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
-#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
-#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
-#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
-#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
-#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
-/* bank configuration registers */
-#define S3C2410_BANKCON_PMCnorm         (0x00)
-#define S3C2410_BANKCON_PMC4            (0x01)
-#define S3C2410_BANKCON_PMC8            (0x02)
-#define S3C2410_BANKCON_PMC16           (0x03)
-/* bank configurations for banks 0..7, note banks
- * 6 and 7 have different configurations depending on
- * the memory type bits */
-#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
-#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
-#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
-#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
-#define S3C2410_BANKCON_Tacp_SHIFT      (2)
-#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
-#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
-#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
-#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
-#define S3C2410_BANKCON_Tcah_SHIFT      (4)
-#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
-#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
-#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
-#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
-#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
-#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
-#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
-#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
-#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
-#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
-#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
-#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
-#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
-#define S3C2410_BANKCON_Tacc_SHIFT      (8)
-#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
-#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
-#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
-#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
-#define S3C2410_BANKCON_Tcos_SHIFT      (11)
-#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
-#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
-#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
-#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
-#define S3C2410_BANKCON_Tacs_SHIFT      (13)
-#define S3C2410_BANKCON_SRAM            (0x0 << 15)
-#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
-/* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trcd2           (0x00 << 2)
-#define S3C2410_BANKCON_Trcd3           (0x01 << 2)
-#define S3C2410_BANKCON_Trcd4           (0x02 << 2)
-/* control column address select */
-#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
-#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
-#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
-#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
-#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
-#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
-#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
-/* refresh control */
-#define S3C2410_REFRESH_REFEN           (1<<23)
-#define S3C2410_REFRESH_SELF            (1<<22)
-#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
-#define S3C2410_REFRESH_TRP_MASK        (3<<20)
-#define S3C2410_REFRESH_TRP_2clk        (0<<20)
-#define S3C2410_REFRESH_TRP_3clk        (1<<20)
-#define S3C2410_REFRESH_TRP_4clk        (2<<20)
-#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
-#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
-#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
-#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
-#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
-/* mode select register(s) */
-#define  S3C2410_MRSRB_CL1              (0x00 << 4)
-#define  S3C2410_MRSRB_CL2              (0x02 << 4)
-#define  S3C2410_MRSRB_CL3              (0x03 << 4)
-/* bank size register */
-#define S3C2410_BANKSIZE_128M           (0x2 << 0)
-#define S3C2410_BANKSIZE_64M            (0x1 << 0)
-#define S3C2410_BANKSIZE_32M            (0x0 << 0)
-#define S3C2410_BANKSIZE_16M            (0x7 << 0)
-#define S3C2410_BANKSIZE_8M             (0x6 << 0)
-#define S3C2410_BANKSIZE_4M             (0x5 << 0)
-#define S3C2410_BANKSIZE_2M             (0x4 << 0)
-#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
-#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
-#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
-#define S3C2410_BANKSIZE_BURST          (1<<7)
-#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-power.h
- *
- * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX power control register definitions
-*/
-#ifndef __ASM_ARM_REGS_PWR
-#define __ASM_ARM_REGS_PWR __FILE__
-#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
-#define S3C2412_PWRMODECON      S3C24XX_PWRREG(0x20)
-#define S3C2412_PWRCFG          S3C24XX_PWRREG(0x24)
-#define S3C2412_INFORM0         S3C24XX_PWRREG(0x70)
-#define S3C2412_INFORM1         S3C24XX_PWRREG(0x74)
-#define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
-#define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
-#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
-#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
-#define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
-#define S3C2412_PWRCFG_BATF_MASK                (3<<0)
-#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3<<6)
-#define S3C2412_PWRCFG_RTC_MASKIRQ              (1<<8)
-#define S3C2412_PWRCFG_NAND_NORST               (1<<9)
-#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 memory register definitions
-*/
-#ifndef __ASM_ARM_REGS_S3C2412_MEM
-#define __ASM_ARM_REGS_S3C2412_MEM
-#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
-#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
-#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
-#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
-#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
-#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
-#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
-#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
-#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
-/* EBI control registers */
-#define S3C2412_EBI_PR                  S3C2412_EBIREG(0x00)
-#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x04)
-/* SSMC control registers */
-#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMIDCYR(x)              S3C2412_SSMC(x, 0x00)
-#define S3C2412_SMBWSTRD(x)             S3C2412_SSMC(x, 0x04)
-#define S3C2412_SMBWSTWRR(x)            S3C2412_SSMC(x, 0x08)
-#define S3C2412_SMBWSTOENR(x)           S3C2412_SSMC(x, 0x0C)
-#define S3C2412_SMBWSTWENR(x)           S3C2412_SSMC(x, 0x10)
-#define S3C2412_SMBCR(x)                S3C2412_SSMC(x, 0x14)
-#define S3C2412_SMBSR(x)                S3C2412_SSMC(x, 0x18)
-#define S3C2412_SMBWSTBRDR(x)           S3C2412_SSMC(x, 0x1C)
-#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
deleted file mode 100644
index aa69dc79bc38..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
- *
- * Copyright 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 specific register definitions
-*/
-#ifndef __ASM_ARCH_REGS_S3C2412_H
-#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
-#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
-#define S3C2412_SWRST_RESET     (0x533C2412)
-/* see regs-power.h for the other registers in the power block. */
-#endif  /* __ASM_ARCH_REGS_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
deleted file mode 100644
index 2f31b74974af..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 memory register definitions
-*/
-#ifndef __ASM_ARM_REGS_S3C2416_MEM
-#define __ASM_ARM_REGS_S3C2416_MEM
-#ifndef S3C2416_MEMREG
-#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-#define S3C2416_BANKCFG                 S3C2416_MEMREG(0x00)
-#define S3C2416_BANKCON1                S3C2416_MEMREG(0x04)
-#define S3C2416_BANKCON2                S3C2416_MEMREG(0x08)
-#define S3C2416_BANKCON3                S3C2416_MEMREG(0x0C)
-#define S3C2416_REFRESH                 S3C2416_MEMREG(0x10)
-#define S3C2416_TIMEOUT                 S3C2416_MEMREG(0x14)
-#endif /*  __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
deleted file mode 100644
index e443167efb87..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2416 specific register definitions
-*/
-#ifndef __ASM_ARCH_REGS_S3C2416_H
-#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
-#define S3C2416_SWRST           (S3C24XX_VA_CLKPWR + 0x44)
-#define S3C2416_SWRST_RESET     (0x533C2416)
-/* see regs-power.h for the other registers in the power block. */
-#endif  /* __ASM_ARCH_REGS_S3C2416_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
deleted file mode 100644
index e4119913d7c5..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * VR1000 - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VR1000CPLD_H
-#define __ASM_ARCH_VR1000CPLD_H
-#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
-#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
deleted file mode 100644
index 47add133b8ee..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VR1000IRQ_H
-#define __ASM_ARCH_VR1000IRQ_H
-/* irq numbers to onboard peripherals */
-#define IRQ_USBOC            IRQ_EINT19
-#define IRQ_IDE0             IRQ_EINT16
-#define IRQ_IDE1             IRQ_EINT17
-#define IRQ_VR1000_SERIAL    IRQ_EINT12
-#define IRQ_VR1000_DM9000A   IRQ_EINT10
-#define IRQ_VR1000_DM9000N   IRQ_EINT9
-#define IRQ_SMALERT          IRQ_EINT8
-#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
deleted file mode 100644
index 28376e56dd3b..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* needs arch/map.h including with this */
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-#ifndef __ASM_ARCH_VR1000MAP_H
-#define __ASM_ARCH_VR1000MAP_H
-#include <mach/bast-map.h>
-#define VR1000_IOADDR(x) BAST_IOADDR(x)
-/* we put the CPLD registers next, to get them out of the way */
-#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
-#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
-#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
-#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
-#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
-#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
-#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
-#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
-/* next, we have the PC104 ISA interrupt registers */
-#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
-#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
-#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
-/* 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
- * 0x02600000 to 0x02700000 1MB
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-#define VR1000_VA_MULTISPACE (0xE0000000)
-#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
-#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
-#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
-#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
-#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
-#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
-#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
-#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
-#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
-/* physical offset addresses for the peripherals */
-#define VR1000_PA_IDEPRI           (0x02000000)
-#define VR1000_PA_IDEPRIAUX        (0x02800000)
-#define VR1000_PA_IDESEC           (0x03000000)
-#define VR1000_PA_IDESECAUX        (0x03800000)
-#define VR1000_PA_DM9000           (0x05000000)
-#define VR1000_PA_SERIAL           (0x11800000)
-#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
-/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
-#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
-/* some configurations for the peripherals */
-#define VR1000_DM9000_CS         VR1000_VAM_CS4
-#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
index b1908e56da1b..4cd13ab6496b 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+/*
- *
 * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -20,11 +19,12 @@
 #include <linux/slab.h>
 #include <mach/map.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu-freq-core.h>
+#include "regs-mem.h"
 #define print_ns(x) ((x) / 10), ((x) % 10)
 /**
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 48eee39ab369..663436d9db01 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -28,12 +27,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/regs-s3c2412-mem.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq-core.h>
 #include <plat/clock.h>
+#include "s3c2412.h"
 #define print_ns(x) ((x) / 10), ((x) % 10)
 /**
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index 0efb2e2848c8..e1199599873e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/syscore_ops.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -29,18 +30,18 @@
 * set bit to 1 in allow bitfield to enable the wakeup settings on it
 */
-unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
+unsigned long s3c_irqwake_intallow      = 1L << 30 | 0xfL;
 unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
-        unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
+        unsigned long irqbit = 1 << data->hwirq;
        if (!(s3c_irqwake_intallow & irqbit))
                return -ENOENT;
-        printk(KERN_INFO "wake %s for irq %d\n",
+        pr_info("wake %s for hwirq %lu\n",
-               state ? "enabled" : "disabled", data->irq);
+                state ? "enabled" : "disabled", data->hwirq);
        if (!state)
                s3c_irqwake_intmask |= irqbit;
@@ -64,7 +65,7 @@ static unsigned long save_extint[3];
 static unsigned long save_eintflt[4];
 static unsigned long save_eintmask;
-int s3c24xx_irq_suspend(void)
+static int s3c24xx_irq_suspend(void)
 {
        unsigned int i;
@@ -80,7 +81,7 @@ int s3c24xx_irq_suspend(void)
        return 0;
 }
-void s3c24xx_irq_resume(void)
+static void s3c24xx_irq_resume(void)
 {
        unsigned int i;
@@ -93,3 +94,31 @@ void s3c24xx_irq_resume(void)
        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
        __raw_writel(save_eintmask, S3C24XX_EINTMASK);
 }
+struct syscore_ops s3c24xx_irq_syscore_ops = {
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+#ifdef CONFIG_CPU_S3C2416
+static struct sleep_save s3c2416_irq_save[] = {
+        SAVE_ITEM(S3C2416_INTMSK2),
+};
+static int s3c2416_irq_suspend(void)
+{
+        s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+        return 0;
+}
+static void s3c2416_irq_resume(void)
+{
+        s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
+}
+struct syscore_ops s3c2416_irq_syscore_ops = {
+        .suspend        = s3c2416_irq_suspend,
+        .resume         = s3c2416_irq_resume,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbccc..67d763178d3f 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
@@ -33,12 +33,13 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-power.h>
 #include <plat/cpu.h>
 #include <plat/irq.h>
 #include <plat/pm.h>
+#include "s3c2412-power.h"
 #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
 #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
deleted file mode 100644
index ff141b0af26b..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/irq.c
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
- *      as part of OpenInkpot project
- * Copyright (c) 2009 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-        end = len + irq;
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-                subsrc >>= 1;
-        }
-}
-/* WDT/AC97 sub interrupts */
-static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static struct irq_chip s3c2416_irq_wdtac97 = {
-        .irq_mask       = s3c2416_irq_wdtac97_mask,
-        .irq_unmask     = s3c2416_irq_wdtac97_unmask,
-        .irq_ack        = s3c2416_irq_wdtac97_ack,
-};
-/* LCD sub interrupts */
-static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-static void s3c2416_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static void s3c2416_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-static void s3c2416_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static struct irq_chip s3c2416_irq_lcd = {
-        .irq_mask       = s3c2416_irq_lcd_mask,
-        .irq_unmask     = s3c2416_irq_lcd_unmask,
-        .irq_ack        = s3c2416_irq_lcd_ack,
-};
-/* DMA sub interrupts */
-static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-static void s3c2416_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static void s3c2416_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-static void s3c2416_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static struct irq_chip s3c2416_irq_dma = {
-        .irq_mask       = s3c2416_irq_dma_mask,
-        .irq_unmask     = s3c2416_irq_dma_unmask,
-        .irq_ack        = s3c2416_irq_dma_ack,
-};
-/* UART3 sub interrupts */
-static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-static void s3c2416_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static void s3c2416_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-static void s3c2416_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static struct irq_chip s3c2416_irq_uart3 = {
-        .irq_mask       = s3c2416_irq_uart3_mask,
-        .irq_unmask     = s3c2416_irq_uart3_unmask,
-        .irq_ack        = s3c2416_irq_uart3_ack,
-};
-/* second interrupt register */
-static inline void s3c2416_irq_ack_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        __raw_writel(bitval, S3C2416_SRCPND2);
-        __raw_writel(bitval, S3C2416_INTPND2);
-}
-static void s3c2416_irq_mask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask |= bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-static void s3c2416_irq_unmask_second(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
-        unsigned long mask;
-        mask = __raw_readl(S3C2416_INTMSK2);
-        mask &= ~bitval;
-        __raw_writel(mask, S3C2416_INTMSK2);
-}
-struct irq_chip s3c2416_irq_second = {
-        .irq_ack        = s3c2416_irq_ack_second,
-        .irq_mask       = s3c2416_irq_mask_second,
-        .irq_unmask     = s3c2416_irq_unmask_second,
-};
-/* IRQ initialisation code */
-static int s3c2416_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        return 0;
-}
-static void s3c2416_irq_add_second(void)
-{
-        unsigned long pend;
-        unsigned long last;
-        int irqno;
-        int i;
-        /* first, clear all interrupts pending... */
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2416_INTPND2);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C2416_SRCPND2);
-                __raw_writel(pend, S3C2416_INTPND2);
-                printk(KERN_INFO "irq: clearing pending status %08x\n",
-                       (int)pend);
-                last = pend;
-        }
-        for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
-                switch (irqno) {
-                case IRQ_S3C2416_RESERVED2:
-                case IRQ_S3C2416_RESERVED3:
-                        /* no IRQ here */
-                        break;
-                default:
-                        irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
-                                                 handle_edge_irq);
-                        set_irq_flags(irqno, IRQF_VALID);
-                }
-        }
-}
-static int s3c2416_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk(KERN_INFO "S3C2416: IRQ Support\n");
-        s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
-                        IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
-        s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
-                        &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-        s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
-                        &s3c2416_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-        s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
-                        &s3c2416_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-        s3c2416_irq_add_second();
-        return 0;
-}
-static struct subsys_interface s3c2416_irq_interface = {
-        .name           = "s3c2416_irq",
-        .subsys         = &s3c2416_subsys,
-        .add_dev        = s3c2416_irq_add,
-};
-static int __init s3c2416_irq_init(void)
-{
-        return subsys_interface_register(&s3c2416_irq_interface);
-}
-arch_initcall(s3c2416_irq_init);
-#ifdef CONFIG_PM
-static struct sleep_save irq_save[] = {
-        SAVE_ITEM(S3C2416_INTMSK2),
-};
-int s3c2416_irq_suspend(void)
-{
-        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-        return 0;
-}
-void s3c2416_irq_resume(void)
-{
-        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-}
-struct syscore_ops s3c2416_irq_syscore_ops = {
-        .suspend        = s3c2416_irq_suspend,
-        .resume         = s3c2416_irq_resume,
-};
-#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
deleted file mode 100644
index 5e69109c0928..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* linux/arch/arm/mach-s3c2443/irq.c
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
-{
-        unsigned int subsrc, submsk;
-        unsigned int end;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc  &= ~submsk;
-        subsrc >>= (irq - S3C2410_IRQSUB(0));
-        subsrc  &= (1 << len)-1;
-        end = len + irq;
-        for (; irq < end && subsrc; irq++) {
-                if (subsrc & 1)
-                        generic_handle_irq(irq);
-                subsrc >>= 1;
-        }
-}
-/* WDT/AC97 sub interrupts */
-static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
-}
-#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
-#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
-static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
-}
-static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
-}
-static struct irq_chip s3c2443_irq_wdtac97 = {
-        .irq_mask       = s3c2443_irq_wdtac97_mask,
-        .irq_unmask     = s3c2443_irq_wdtac97_unmask,
-        .irq_ack        = s3c2443_irq_wdtac97_ack,
-};
-/* LCD sub interrupts */
-static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
-}
-#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
-#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
-static void s3c2443_irq_lcd_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static void s3c2443_irq_lcd_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
-}
-static void s3c2443_irq_lcd_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
-}
-static struct irq_chip s3c2443_irq_lcd = {
-        .irq_mask       = s3c2443_irq_lcd_mask,
-        .irq_unmask     = s3c2443_irq_lcd_unmask,
-        .irq_ack        = s3c2443_irq_lcd_ack,
-};
-/* DMA sub interrupts */
-static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
-}
-#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
-#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
-static void s3c2443_irq_dma_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static void s3c2443_irq_dma_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
-}
-static void s3c2443_irq_dma_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
-}
-static struct irq_chip s3c2443_irq_dma = {
-        .irq_mask       = s3c2443_irq_dma_mask,
-        .irq_unmask     = s3c2443_irq_dma_unmask,
-        .irq_ack        = s3c2443_irq_dma_ack,
-};
-/* UART3 sub interrupts */
-static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
-}
-#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
-#define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
-static void s3c2443_irq_uart3_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static void s3c2443_irq_uart3_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
-}
-static void s3c2443_irq_uart3_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
-}
-static struct irq_chip s3c2443_irq_uart3 = {
-        .irq_mask       = s3c2443_irq_uart3_mask,
-        .irq_unmask     = s3c2443_irq_uart3_unmask,
-        .irq_ack        = s3c2443_irq_uart3_ack,
-};
-/* CAM sub interrupts */
-static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
-{
-        s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
-}
-#define INTMSK_CAM      (1UL << (IRQ_CAM - IRQ_EINT0))
-#define SUBMSK_CAM      INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
-static void s3c2443_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-static void s3c2443_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-static void s3c2443_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
-}
-static struct irq_chip s3c2443_irq_cam = {
-        .irq_mask       = s3c2443_irq_cam_mask,
-        .irq_unmask     = s3c2443_irq_cam_unmask,
-        .irq_ack        = s3c2443_irq_cam_ack,
-};
-/* IRQ initialisation code */
-static int s3c2443_add_sub(unsigned int base,
-                                   void (*demux)(unsigned int,
-                                                 struct irq_desc *),
-                                   struct irq_chip *chip,
-                                   unsigned int start, unsigned int end)
-{
-        unsigned int irqno;
-        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
-        irq_set_chained_handler(base, demux);
-        for (irqno = start; irqno <= end; irqno++) {
-                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        return 0;
-}
-static int s3c2443_irq_add(struct device *dev,
-                                  struct subsys_interface *sif)
-{
-        printk("S3C2443: IRQ Support\n");
-        s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
-                        IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
-        s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
-                        IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
-        s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
-                        &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
-        s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
-                        &s3c2443_irq_uart3,
-                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
-        s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
-                        &s3c2443_irq_wdtac97,
-                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
-        return 0;
-}
-static struct subsys_interface s3c2443_irq_interface = {
-        .name           = "s3c2443_irq",
-        .subsys         = &s3c2443_subsys,
-        .add_dev        = s3c2443_irq_add,
-};
-static int __init s3c2443_irq_init(void)
-{
-        return subsys_interface_register(&s3c2443_irq_interface);
-}
-arch_initcall(s3c2443_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
new file mode 100644
index 000000000000..cb9f5e011e73
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -0,0 +1,822 @@
+/*
+ * S3C24XX IRQ handling
+ *
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/irq.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/regs-irqtype.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+#define S3C_IRQTYPE_NONE        0
+#define S3C_IRQTYPE_EINT        1
+#define S3C_IRQTYPE_EDGE        2
+#define S3C_IRQTYPE_LEVEL       3
+struct s3c_irq_data {
+        unsigned int type;
+        unsigned long parent_irq;
+        /* data gets filled during init */
+        struct s3c_irq_intc *intc;
+        unsigned long sub_bits;
+        struct s3c_irq_intc *sub_intc;
+};
+/*
+ * Sructure holding the controller data
+ * @reg_pending         register holding pending irqs
+ * @reg_intpnd          special register intpnd in main intc
+ * @reg_mask            mask register
+ * @domain              irq_domain of the controller
+ * @parent              parent controller for ext and sub irqs
+ * @irqs                irq-data, always s3c_irq_data[32]
+ */
+struct s3c_irq_intc {
+        void __iomem            *reg_pending;
+        void __iomem            *reg_intpnd;
+        void __iomem            *reg_mask;
+        struct irq_domain       *domain;
+        struct s3c_irq_intc     *parent;
+        struct s3c_irq_data     *irqs;
+};
+static void s3c_irq_mask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        struct s3c_irq_data *parent_data;
+        unsigned long mask;
+        unsigned int irqno;
+        mask = __raw_readl(intc->reg_mask);
+        mask |= (1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+        if (parent_intc && irq_data->parent_irq) {
+                parent_data = &parent_intc->irqs[irq_data->parent_irq];
+                /* check to see if we need to mask the parent IRQ */
+                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
+                        irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                        s3c_irq_mask(irq_get_irq_data(irqno));
+                }
+        }
+}
+static void s3c_irq_unmask(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
+        unsigned long mask;
+        unsigned int irqno;
+        mask = __raw_readl(intc->reg_mask);
+        mask &= ~(1UL << data->hwirq);
+        __raw_writel(mask, intc->reg_mask);
+        if (parent_intc && irq_data->parent_irq) {
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                s3c_irq_unmask(irq_get_irq_data(irqno));
+        }
+}
+static inline void s3c_irq_ack(struct irq_data *data)
+{
+        struct s3c_irq_intc *intc = data->domain->host_data;
+        unsigned long bitval = 1UL << data->hwirq;
+        __raw_writel(bitval, intc->reg_pending);
+        if (intc->reg_intpnd)
+                __raw_writel(bitval, intc->reg_intpnd);
+}
+static int s3c_irqext_type_set(void __iomem *gpcon_reg,
+                               void __iomem *extint_reg,
+                               unsigned long gpcon_offset,
+                               unsigned long extint_offset,
+                               unsigned int type)
+{
+        unsigned long newvalue = 0, value;
+        /* Set the GPIO to external interrupt mode */
+        value = __raw_readl(gpcon_reg);
+        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
+        __raw_writel(value, gpcon_reg);
+        /* Set the external interrupt to pointed trigger type */
+        switch (type)
+        {
+                case IRQ_TYPE_NONE:
+                        pr_warn("No edge setting!\n");
+                        break;
+                case IRQ_TYPE_EDGE_RISING:
+                        newvalue = S3C2410_EXTINT_RISEEDGE;
+                        break;
+                case IRQ_TYPE_EDGE_FALLING:
+                        newvalue = S3C2410_EXTINT_FALLEDGE;
+                        break;
+                case IRQ_TYPE_EDGE_BOTH:
+                        newvalue = S3C2410_EXTINT_BOTHEDGE;
+                        break;
+                case IRQ_TYPE_LEVEL_LOW:
+                        newvalue = S3C2410_EXTINT_LOWLEV;
+                        break;
+                case IRQ_TYPE_LEVEL_HIGH:
+                        newvalue = S3C2410_EXTINT_HILEV;
+                        break;
+                default:
+                        pr_err("No such irq type %d", type);
+                        return -EINVAL;
+        }
+        value = __raw_readl(extint_reg);
+        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
+        __raw_writel(value, extint_reg);
+        return 0;
+}
+/* FIXME: make static when it's out of plat-samsung/irq.h */
+int s3c_irqext_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT1;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 8) * 4;
+        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
+                gpcon_reg = S3C2410_GPGCON;
+                extint_reg = S3C24XX_EXTINT2;
+                gpcon_offset = (data->hwirq - 8) * 2;
+                extint_offset = (data->hwirq - 16) * 4;
+        } else {
+                return -EINVAL;
+        }
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *extint_reg;
+        void __iomem *gpcon_reg;
+        unsigned long gpcon_offset, extint_offset;
+        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
+                gpcon_reg = S3C2410_GPFCON;
+                extint_reg = S3C24XX_EXTINT0;
+                gpcon_offset = (data->hwirq) * 2;
+                extint_offset = (data->hwirq) * 4;
+        } else {
+                return -EINVAL;
+        }
+        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+                                   extint_offset, type);
+}
+struct irq_chip s3c_irq_chip = {
+        .name           = "s3c",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake
+};
+struct irq_chip s3c_irq_level_chip = {
+        .name           = "s3c-level",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+};
+static struct irq_chip s3c_irqext_chip = {
+        .name           = "s3c-ext",
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_ack        = s3c_irq_ack,
+        .irq_set_type   = s3c_irqext_type,
+        .irq_set_wake   = s3c_irqext_wake
+};
+static struct irq_chip s3c_irq_eint0t4 = {
+        .name           = "s3c-ext0",
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext0_type,
+};
+static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
+        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
+        unsigned long src;
+        unsigned long msk;
+        unsigned int n;
+        chained_irq_enter(chip, desc);
+        src = __raw_readl(sub_intc->reg_pending);
+        msk = __raw_readl(sub_intc->reg_mask);
+        src &= ~msk;
+        src &= irq_data->sub_bits;
+        while (src) {
+                n = __ffs(src);
+                src &= ~(1 << n);
+                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+        }
+        chained_irq_exit(chip, desc);
+}
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ */
+int s3c24xx_set_fiq(unsigned int irq, bool on)
+{
+        u32 intmod;
+        unsigned offs;
+        if (on) {
+                offs = irq - FIQ_START;
+                if (offs > 31)
+                        return -EINVAL;
+                intmod = 1 << offs;
+        } else {
+                intmod = 0;
+        }
+        __raw_writel(intmod, S3C2410_INTMOD);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
+#endif
+static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct s3c_irq_intc *intc = h->host_data;
+        struct s3c_irq_data *irq_data = &intc->irqs[hw];
+        struct s3c_irq_intc *parent_intc;
+        struct s3c_irq_data *parent_irq_data;
+        unsigned int irqno;
+        if (!intc) {
+                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+        if (!irq_data) {
+                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
+                return -EINVAL;
+        }
+        /* attach controller pointer to irq_data */
+        irq_data->intc = intc;
+        /* set handler and flags */
+        switch (irq_data->type) {
+        case S3C_IRQTYPE_NONE:
+                return 0;
+        case S3C_IRQTYPE_EINT:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_EDGE:
+                if (irq_data->parent_irq ||
+                    intc->reg_pending == S3C2416_SRCPND2)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_edge_irq);
+                break;
+        case S3C_IRQTYPE_LEVEL:
+                if (irq_data->parent_irq)
+                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                                 handle_level_irq);
+                else
+                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
+                                                 handle_level_irq);
+                break;
+        default:
+                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
+                return -EINVAL;
+        }
+        set_irq_flags(virq, IRQF_VALID);
+        if (irq_data->parent_irq) {
+                parent_intc = intc->parent;
+                if (!parent_intc) {
+                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+                if (!irq_data) {
+                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
+                               hw);
+                        goto err;
+                }
+                parent_irq_data->sub_intc = intc;
+                parent_irq_data->sub_bits |= (1UL << hw);
+                /* attach the demuxer to the parent irq */
+                irqno = irq_find_mapping(parent_intc->domain,
+                                         irq_data->parent_irq);
+                if (!irqno) {
+                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
+                               irq_data->parent_irq);
+                        goto err;
+                }
+                irq_set_chained_handler(irqno, s3c_irq_demux);
+        }
+        return 0;
+err:
+        set_irq_flags(virq, 0);
+        /* the only error can result from bad mapping data*/
+        return -EINVAL;
+}
+static struct irq_domain_ops s3c24xx_irq_ops = {
+        .map = s3c24xx_irq_map,
+        .xlate = irq_domain_xlate_twocell,
+};
+static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
+{
+        void __iomem *reg_source;
+        unsigned long pend;
+        unsigned long last;
+        int i;
+        /* if intpnd is set, read the next pending irq from there */
+        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
+        last = 0;
+        for (i = 0; i < 4; i++) {
+                pend = __raw_readl(reg_source);
+                if (pend == 0 || pend == last)
+                        break;
+                __raw_writel(pend, intc->reg_pending);
+                if (intc->reg_intpnd)
+                        __raw_writel(pend, intc->reg_intpnd);
+                pr_info("irq: clearing pending status %08x\n", (int)pend);
+                last = pend;
+        }
+}
+struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
+                                       struct s3c_irq_data *irq_data,
+                                       struct s3c_irq_intc *parent,
+                                       unsigned long address)
+{
+        struct s3c_irq_intc *intc;
+        void __iomem *base = (void *)0xf6000000; /* static mapping */
+        int irq_num;
+        int irq_start;
+        int irq_offset;
+        int ret;
+        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+        if (!intc)
+                return ERR_PTR(-ENOMEM);
+        intc->irqs = irq_data;
+        if (parent)
+                intc->parent = parent;
+        /* select the correct data for the controller.
+         * Need to hard code the irq num start and offset
+         * to preserve the static mapping for now
+         */
+        switch (address) {
+        case 0x4a000000:
+                pr_debug("irq: found main intc\n");
+                intc->reg_pending = base;
+                intc->reg_mask = base + 0x08;
+                intc->reg_intpnd = base + 0x10;
+                irq_num = 32;
+                irq_start = S3C2410_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000018:
+                pr_debug("irq: found subintc\n");
+                intc->reg_pending = base + 0x18;
+                intc->reg_mask = base + 0x1c;
+                irq_num = 29;
+                irq_start = S3C2410_IRQSUB(0);
+                irq_offset = 0;
+                break;
+        case 0x4a000040:
+                pr_debug("irq: found intc2\n");
+                intc->reg_pending = base + 0x40;
+                intc->reg_mask = base + 0x48;
+                intc->reg_intpnd = base + 0x50;
+                irq_num = 8;
+                irq_start = S3C2416_IRQ(0);
+                irq_offset = 0;
+                break;
+        case 0x560000a4:
+                pr_debug("irq: found eintc\n");
+                base = (void *)0xfd000000;
+                intc->reg_mask = base + 0xa4;
+                intc->reg_pending = base + 0x08;
+                irq_num = 20;
+                irq_start = S3C2410_IRQ(32);
+                irq_offset = 4;
+                break;
+        default:
+                pr_err("irq: unsupported controller address\n");
+                ret = -EINVAL;
+                goto err;
+        }
+        /* now that all the data is complete, init the irq-domain */
+        s3c24xx_clear_intc(intc);
+        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
+                                             irq_offset, &s3c24xx_irq_ops,
+                                             intc);
+        if (!intc->domain) {
+                pr_err("irq: could not create irq-domain\n");
+                ret = -EINVAL;
+                goto err;
+        }
+        return intc;
+err:
+        kfree(intc);
+        return ERR_PTR(ret);
+}
+/* s3c24xx_init_irq
+ *
+ * Initialise S3C2410 IRQ system
+*/
+static struct s3c_irq_data init_base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_eint[32] = {
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
+static struct s3c_irq_data init_subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+};
+void __init s3c24xx_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+}
+#ifdef CONFIG_CPU_S3C2416
+static struct s3c_irq_data init_s3c2416base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_NONE, },
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_s3c2416subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+static struct s3c_irq_data init_s3c2416_second[32] = {
+        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
+        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
+        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
+};
+void __init s3c2416_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+        pr_info("S3C2416: IRQ Support\n");
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
+}
+#endif
+#ifdef CONFIG_CPU_S3C2443
+static struct s3c_irq_data init_s3c2443base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+static struct s3c_irq_data init_s3c2443subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+void __init s3c2443_init_irq(void)
+{
+        struct s3c_irq_intc *main_intc;
+        pr_info("S3C2443: IRQ Support\n");
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
+        if (IS_ERR(main_intc)) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
+}
+#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index f4ad99c1e476..0e0279e79150 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -237,6 +237,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
        .map_io         = amlm5900_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = amlm5900_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 1ee8c4638743..bb595f15ce36 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -28,17 +28,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/anubis-map.h>
-#include <mach/anubis-irq.h>
-#include <mach/anubis-cpld.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -55,8 +50,9 @@
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include "simtec.h"
+#include "anubis.h"
 #include "common.h"
+#include "simtec.h"
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
@@ -237,7 +233,7 @@ static struct pata_platform_info anubis_ide_platdata = {
 static struct resource anubis_ide0_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
        [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
-        [3] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 static struct platform_device anubis_device_ide0 = {
@@ -254,7 +250,7 @@ static struct platform_device anubis_device_ide0 = {
 static struct resource anubis_ide1_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
        [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
-        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
+        [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
 };
 static struct platform_device anubis_device_ide1 = {
@@ -279,7 +275,7 @@ static struct ax_plat_data anubis_asix_platdata = {
 static struct resource anubis_asix_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
-        [1] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
 };
 static struct platform_device anubis_device_asix = {
@@ -448,6 +444,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
        .map_io         = anubis_map_io,
        .init_machine   = anubis_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 00381fe5de32..b4bc60c78ebb 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/timer.h>
@@ -34,7 +35,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -210,6 +210,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
        .map_io         = at2440evb_map_io,
        .init_machine   = at2440evb_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 6a30ce7e4aa7..ca6618081041 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -24,48 +24,41 @@
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <net/ax88796.h>
+#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
 #include <asm/mach-types.h>
-//#include <asm/debug-ll.h>
+#include <mach/fb.h>
-#include <plat/regs-serial.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <linux/platform_data/hwmon-s3c.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/fb.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-#include <linux/serial_8250.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/regs-serial.h>
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
@@ -312,7 +305,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
 static struct resource bast_dm9k_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
                                        | IORESOURCE_IRQ_HIGHLEVEL),
 };
@@ -343,7 +336,7 @@ static struct platform_device bast_device_dm9k = {
 static struct plat_serial8250_port bast_sio_data[] = {
        [0] = {
                .mapbase        = SERIAL_BASE + 0x2f8,
-                .irq            = IRQ_PCSERIAL1,
+                .irq            = BAST_IRQ_PCSERIAL1,
                .flags          = SERIAL_FLAGS,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -351,7 +344,7 @@ static struct plat_serial8250_port bast_sio_data[] = {
        },
        [1] = {
                .mapbase        = SERIAL_BASE + 0x3f8,
-                .irq            = IRQ_PCSERIAL2,
+                .irq            = BAST_IRQ_PCSERIAL2,
                .flags          = SERIAL_FLAGS,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -390,7 +383,7 @@ static struct ax_plat_data bast_asix_platdata = {
 static struct resource bast_asix_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
-        [2] = DEFINE_RES_IRQ(IRQ_ASIX),
+        [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
 };
 static struct platform_device bast_device_asix = {
@@ -612,6 +605,6 @@ MACHINE_START(BAST, "Simtec-BAST")
        .map_io         = bast_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = bast_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 973b87ca87f4..a25e8c5a7b4c 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-s3c2442/mach-gta02.c
- *
 * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
 *
 * Copyright (C) 2006-2009 by Openmoko, Inc.
@@ -23,7 +21,6 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
- *
 */
 #include <linux/kernel.h>
@@ -34,62 +31,59 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/workqueue.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/spi/spi.h>
+#include <linux/input.h>
-#include <linux/spi/s3c24xx.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
 #include <linux/mmc/host.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/backlight.h>
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/pmic.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
 #include <linux/regulator/machine.h>
-#include <linux/mfd/pcf50633/core.h>
+#include <linux/spi/spi.h>
-#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/spi/s3c24xx.h>
-#include <linux/mfd/pcf50633/adc.h>
-#include <linux/mfd/pcf50633/gpio.h>
-#include <linux/mfd/pcf50633/pmic.h>
-#include <linux/mfd/pcf50633/backlight.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <asm/irq.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/fb.h>
-#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <mach/regs-mem.h>
 #include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
-#include <mach/gta02.h>
-#include <plat/regs-serial.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
+#include <plat/devs.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/pm.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/regs-serial.h>
 #include "common.h"
+#include "gta02.h"
 static struct pcf50633 *gta02_pcf;
@@ -595,6 +589,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
        .map_io         = gta02_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = gta02_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index b23dd1b106e8..79bc0830d740 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-h1940.c
+/*
- *
 * Copyright (c) 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
@@ -37,40 +36,36 @@
 #include <linux/mmc/host.h>
 #include <linux/export.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <asm/irq.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
+#include <sound/uda1380.h>
-#include <mach/gpio-fns.h>
-#include <mach/gpio-nrs.h>
-#include <mach/h1940.h>
-#include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <mach/hardware.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/regs-serial.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <sound/uda1380.h>
 #include "common.h"
+#include "h1940.h"
 #define H1940_LATCH             ((void __force __iomem *)0xF8000000)
@@ -746,6 +741,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
        .reserve        = h1940_reserve,
        .init_irq       = h1940_init_irq,
        .init_machine   = h1940_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index c9954e26b492..54e83c1f780c 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -35,9 +35,7 @@
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/fb.h>
@@ -56,6 +54,8 @@
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include "s3c2412-power.h"
 static struct map_desc jive_iodesc[] __initdata = {
 };
@@ -661,6 +661,6 @@ MACHINE_START(JIVE, "JIVE")
        .init_irq       = s3c24xx_init_irq,
        .map_io         = jive_map_io,
        .init_machine   = jive_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index a31d5b83e5f7..2865e5919f2c 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -40,7 +40,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
@@ -688,6 +687,6 @@ MACHINE_START(MINI2440, "MINI2440")
        .map_io         = mini2440_map_io,
        .init_machine   = mini2440_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index c53a9bfe1417..d9d04b240295 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -589,7 +589,7 @@ MACHINE_START(N30, "Acer-N30")
                                Ben Dooks <ben-linux@fluff.org>
        */
        .atag_offset    = 0x100,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .init_machine   = n30_init,
        .init_irq       = s3c24xx_init_irq,
        .map_io         = n30_map_io,
@@ -600,7 +600,7 @@ MACHINE_START(N35, "Acer-N35")
        /* Maintainer: Christer Weinigel <christer@weinigel.se>
        */
        .atag_offset    = 0x100,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .init_machine   = n30_init,
        .init_irq       = s3c24xx_init_irq,
        .map_io         = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a2b92b0898e2..a454e2461860 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
        .map_io         = nexcoder_map_io,
        .init_machine   = nexcoder_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index bb36d832bd3d..ae2cbdf3e3ca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-osiris.c
+/*
- *
 * Copyright (c) 2005-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -22,25 +21,16 @@
 #include <linux/clk.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/i2c/tps65010.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/osiris-map.h>
-#include <mach/osiris-cpld.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <plat/cpu-freq.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
-#include <mach/regs-lcd.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -49,12 +39,20 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
-#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 #include "common.h"
+#include "osiris.h"
+#include "regs-mem.h"
 /* onboard perihperal map */
@@ -428,6 +426,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
        .map_io         = osiris_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = osiris_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bca39f0232b3..40a47d6c6a85 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-otom.c
+/*
 *
 * Copyright (c) 2004 Nex Vision
 *   Guillaume GOURAT <guillaume.gourat@nexvision.fr>
@@ -6,7 +6,6 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
- *
 */
 #include <linux/kernel.h>
@@ -19,26 +18,25 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/otom-map.h>
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+#include <plat/s3c2410.h>
 #include "common.h"
+#include "otom.h"
 static struct map_desc otom11_iodesc[] __initdata = {
  /* Device area */
@@ -118,6 +116,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
        .map_io         = otom11_map_io,
        .init_machine   = otom11_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 7b6ba13d7285..56175f0941b1 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -343,6 +343,6 @@ MACHINE_START(QT2410, "QT2410")
        .map_io         = qt2410_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = qt2410_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 0606f2faaa5c..1f9ba2ae5288 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
+/*
- *
 * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
 * Copyright (c) 2007-2010 Vasily Khoruzhick
 *
@@ -37,31 +36,31 @@
 #include <linux/mmc/host.h>
+#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mmc-s3cmci.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <sound/uda1380.h>
+#include <mach/fb.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/h1940.h>
-#include <mach/fb.h>
 #include <plat/clock.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-iic.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/regs-iic.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
+#include <plat/regs-serial.h>
-#include <sound/uda1380.h>
 #include "common.h"
+#include "h1940.h"
 #define LCD_PWM_PERIOD 192960
 #define LCD_PWM_DUTY 127353
@@ -814,6 +813,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
        .reserve        = rx1950_reserve,
        .init_irq = s3c24xx_init_irq,
        .init_machine = rx1950_init_machine,
-        .timer = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index dacbb9a2122a..f20418a2fb1b 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -31,27 +31,27 @@
 #include <linux/mtd/partitions.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
+#include <mach/fb.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/h1940.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <mach/fb.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/regs-serial.h>
 #include "common.h"
+#include "h1940.h"
 static struct map_desc rx3715_iodesc[] __initdata = {
        /* dump ISA space somewhere unused */
@@ -212,6 +212,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
        .reserve        = rx3715_reserve,
        .init_irq       = rx3715_init_irq,
        .init_machine   = rx3715_init_machine,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index 82796b97cb04..e184bfa9613a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -117,6 +117,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
        .map_io         = smdk2410_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = smdk2410_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index ce99fd8bbbc5..86d7847c9d45 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -37,7 +37,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
@@ -133,7 +132,7 @@ MACHINE_START(S3C2413, "S3C2413")
        .init_irq       = s3c24xx_init_irq,
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2412_restart,
 MACHINE_END
@@ -145,7 +144,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
        .init_irq       = s3c24xx_init_irq,
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2412_restart,
 MACHINE_END
@@ -157,6 +156,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
        .init_irq       = s3c24xx_init_irq,
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index f30d7fccbfee..ebb2e61f3d07 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -39,7 +39,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/regs-s3c2443-clock.h>
-#include <mach/idle.h>
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -251,9 +250,9 @@ MACHINE_START(SMDK2416, "SMDK2416")
        /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
        .atag_offset    = 0x100,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2416_init_irq,
        .map_io         = smdk2416_map_io,
        .init_machine   = smdk2416_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index b7ff882c6ce6..08cc38c8a4ae 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -182,6 +181,6 @@ MACHINE_START(S3C2440, "SMDK2440")
        .init_irq       = s3c24xx_init_irq,
        .map_io         = smdk2440_map_io,
        .init_machine   = smdk2440_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 2568656f046f..fc65d74d3c73 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -35,7 +35,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -141,9 +140,9 @@ MACHINE_START(SMDK2443, "SMDK2443")
        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
        .atag_offset    = 0x100,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2443_init_irq,
        .map_io         = smdk2443_map_io,
        .init_machine   = smdk2443_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 495bf5cf52e9..24b3d79e7b2c 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -149,6 +149,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
        .map_io         = tct_hammer_map_io,
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = tct_hammer_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 14d5b12e388c..ec42d1e4e465 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
+/*
- *
 * Copyright (c) 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
@@ -32,27 +31,25 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/vr1000-map.h>
-#include <mach/vr1000-irq.h>
-#include <mach/vr1000-cpld.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
 #include <plat/clock.h>
-#include <plat/devs.h>
 #include <plat/cpu.h>
-#include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/devs.h>
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/regs-serial.h>
-#include "simtec.h"
+#include "bast.h"
 #include "common.h"
+#include "simtec.h"
+#include "vr1000.h"
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 static struct plat_serial8250_port serial_platform_data[] = {
        [0] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(0),
-                .irq            = IRQ_VR1000_SERIAL + 0,
+                .irq            = VR1000_IRQ_SERIAL + 0,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [1] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(1),
-                .irq            = IRQ_VR1000_SERIAL + 1,
+                .irq            = VR1000_IRQ_SERIAL + 1,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [2] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(2),
-                .irq            = IRQ_VR1000_SERIAL + 2,
+                .irq            = VR1000_IRQ_SERIAL + 2,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        [3] = {
                .mapbase        = VR1000_SERIAL_MAPBASE(3),
-                .irq            = IRQ_VR1000_SERIAL + 3,
+                .irq            = VR1000_IRQ_SERIAL + 3,
                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
                .iotype         = UPIO_MEM,
                .regshift       = 0,
@@ -189,14 +186,14 @@ static struct platform_device serial_device = {
 static struct resource vr1000_dm9k0_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \
                                                | IORESOURCE_IRQ_HIGHLEVEL),
 };
 static struct resource vr1000_dm9k1_resource[] = {
        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
-        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \
                                                | IORESOURCE_IRQ_HIGHLEVEL),
 };
@@ -357,6 +354,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
        .map_io         = vr1000_map_io,
        .init_machine   = vr1000_init,
        .init_irq       = s3c24xx_init_irq,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index f1d44ae11833..3e2bfddc9df1 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -36,7 +36,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
-#include <mach/idle.h>
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
@@ -161,6 +160,6 @@ MACHINE_START(VSTMS, "VSTMS")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = vstms_init,
        .map_io         = vstms_map_io,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/osiris.h
index 17380f848428..b8d56074abac 100644
--- a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c24xx/osiris.h
@@ -1,9 +1,9 @@
-/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
+/*
- *
 * Copyright 2005 Simtec Electronics
 *      http://www.simtec.co.uk/products/
 *      Ben Dooks <ben@simtec.co.uk>
 *
+ * OSIRIS - CPLD control constants
 * OSIRIS - Memory map definitions
 *
 * This program is free software; you can redistribute it and/or modify
@@ -11,10 +11,21 @@
 * published by the Free Software Foundation.
 */
-/* needs arch/map.h including with this */
+#ifndef __MACH_S3C24XX_OSIRIS_H
+#define __MACH_S3C24XX_OSIRIS_H __FILE__
+/* CTRL0 - NAND WP control */
+#define OSIRIS_CTRL0_NANDSEL            (0x3)
+#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
+#define OSIRIS_CTRL0_PCMCIA             (1<<4)
+#define OSIRIS_CTRL0_FIX8               (1<<5)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
+#define OSIRIS_CTRL1_FIX8               (1<<0)
-#ifndef __ASM_ARCH_OSIRISMAP_H
+#define OSIRIS_ID_REVMASK               (0x7)
-#define __ASM_ARCH_OSIRISMAP_H
 /* start peripherals off after the S3C2410 */
@@ -39,4 +50,4 @@
 #define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
 #define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
-#endif /* __ASM_ARCH_OSIRISMAP_H */
+#endif /* __MACH_S3C24XX_OSIRIS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/otom.h
index f9277a52c145..321b7be1c0f7 100644
--- a/arch/arm/mach-s3c24xx/include/mach/otom-map.h
+++ b/arch/arm/mach-s3c24xx/otom.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/otom-map.h
+/*
- *
 * (c) 2005 Guillaume GOURAT / NexVision
 *          guillaume.gourat@nexvision.fr
 *
@@ -10,21 +9,20 @@
 * published by the Free Software Foundation.
 */
-/* needs arch/map.h including with this */
+/*
+ * ok, we've used up to 0x01300000, now we need to find space for the
-/* ok, we've used up to 0x01300000, now we need to find space for the
 * peripherals that live in the nGCS[x] areas, which are quite numerous
 * in their space.
 */
-#ifndef __ASM_ARCH_OTOMMAP_H
+#ifndef __MACH_S3C24XX_OTOM_H
-#define __ASM_ARCH_OTOMMAP_H
+#define __MACH_S3C24XX_OTOM_H __FILE__
-#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
+#define OTOM_PA_CS8900A_BASE    (S3C2410_CS3 + 0x01000000)      /* nGCS3 +0x01000000 */
-#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
+#define OTOM_VA_CS8900A_BASE    S3C2410_ADDR(0x04000000)        /* 0xF4000000 */
 /* physical offset addresses for the peripherals */
-#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
+#define OTOM_PA_FLASH0_BASE     (S3C2410_CS0)
-#endif /* __ASM_ARCH_OTOMMAP_H */
+#endif /* __MACH_S3C24XX_OTOM_H */
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index e0b3b347da82..dcf3420a3271 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/pll.c
+/*
- *
 * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -82,7 +81,6 @@ static int __init s3c2410_pll_init(void)
        return subsys_interface_register(&s3c2410_plls_interface);
 }
 arch_initcall(s3c2410_pll_init);
 static struct subsys_interface s3c2410a_plls_interface = {
@@ -95,5 +93,4 @@ static int __init s3c2410a_pll_init(void)
 {
        return subsys_interface_register(&s3c2410a_plls_interface);
 }
 arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 551fb433be87..673781758319 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+/*
- *
 * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -83,7 +82,6 @@ static int __init s3c2440_pll_12mhz(void)
        return subsys_interface_register(&s3c2440_plls12_interface);
 }
 arch_initcall(s3c2440_pll_12mhz);
 static struct subsys_interface s3c2442_plls12_interface = {
@@ -97,5 +95,4 @@ static int __init s3c2442_pll_12mhz(void)
        return subsys_interface_register(&s3c2442_plls12_interface);
 }
 arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index 3f15bcf64290..debfa106289b 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+/*
- *
 * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
@@ -111,7 +110,6 @@ static int __init s3c2440_pll_16934400(void)
 {
        return subsys_interface_register(&s3c2440_plls169344_interface);
 }
 arch_initcall(s3c2440_pll_16934400);
 static struct subsys_interface s3c2442_plls169344_interface = {
@@ -124,5 +122,4 @@ static int __init s3c2442_pll_16934400(void)
 {
        return subsys_interface_register(&s3c2442_plls169344_interface);
 }
 arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S
index c93bf2db9f4d..6183a688012b 100644
--- a/arch/arm/mach-s3c24xx/pm-h1940.S
+++ b/arch/arm/mach-s3c24xx/pm-h1940.S
@@ -30,4 +30,4 @@
 h1940_pm_return:
        mov     r0, #S3C2410_PA_GPIO
-        ldr     pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
+        ldr     pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 949ae05e07c5..2d82c4f116cd 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -29,16 +29,16 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/h1940.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "h1940.h"
 static void s3c2410_pm_prepare(void)
 {
        /* ensure at least GSTATUS3 has the resume address */
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index c60f67a75aff..668a78a8b195 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -21,19 +21,19 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <asm/cacheflush.h>
 #include <asm/irq.h>
-#include <mach/regs-power.h>
+#include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/s3c2412.h>
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
 extern void s3c2412_sleep_enter(void);
 static int s3c2412_cpu_suspend(unsigned long arg)
@@ -48,7 +48,8 @@ static int s3c2412_cpu_suspend(unsigned long arg)
        s3c2412_sleep_enter();
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 static void s3c2412_pm_prepare(void)
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1bd4817b8eb8..44923895f558 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -16,12 +16,13 @@
 #include <asm/cacheflush.h>
-#include <mach/regs-power.h>
 #include <mach/regs-s3c2443-clock.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "s3c2412-power.h"
 extern void s3c2412_sleep_enter(void);
 static int s3c2416_cpu_suspend(unsigned long arg)
@@ -34,7 +35,8 @@ static int s3c2416_cpu_suspend(unsigned long arg)
        s3c2412_sleep_enter();
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 static void s3c2416_pm_prepare(void)
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 724755f0b0f5..caa5b7211380 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -38,7 +38,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-irq.h>
 #include <asm/mach/time.h>
@@ -46,6 +45,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
+#include "regs-mem.h"
 #define PFX "s3c24xx-pm: "
 static struct sleep_save core_save[] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h
index 98fd4a05587c..98fd4a05587c 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/regs-dsc.h
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h
new file mode 100644
index 000000000000..86b1258368c2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/regs-mem.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
+#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
+#define S3C2410_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+#define S3C2410_BWSCON                  S3C2410_MEMREG(0x00)
+#define S3C2410_BANKCON0                S3C2410_MEMREG(0x04)
+#define S3C2410_BANKCON1                S3C2410_MEMREG(0x08)
+#define S3C2410_BANKCON2                S3C2410_MEMREG(0x0C)
+#define S3C2410_BANKCON3                S3C2410_MEMREG(0x10)
+#define S3C2410_BANKCON4                S3C2410_MEMREG(0x14)
+#define S3C2410_BANKCON5                S3C2410_MEMREG(0x18)
+#define S3C2410_BANKCON6                S3C2410_MEMREG(0x1C)
+#define S3C2410_BANKCON7                S3C2410_MEMREG(0x20)
+#define S3C2410_REFRESH                 S3C2410_MEMREG(0x24)
+#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x28)
+#define S3C2410_BWSCON_ST1              (1 << 7)
+#define S3C2410_BWSCON_ST2              (1 << 11)
+#define S3C2410_BWSCON_ST3              (1 << 15)
+#define S3C2410_BWSCON_ST4              (1 << 19)
+#define S3C2410_BWSCON_ST5              (1 << 23)
+#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
+#define S3C2410_BWSCON_WS               (1 << 2)
+#define S3C2410_BANKCON_PMC16           (0x3)
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
+#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
+#define S3C2410_REFRESH_SELF            (1 << 22)
+#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
+#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index a3c5cb086ee2..9ebef95da721 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -49,6 +49,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 /* Initial IO mappings */
 static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -182,8 +184,8 @@ int __init s3c2410_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
        return device_register(&s3c2410_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c24xx/s3c2412-power.h
new file mode 100644
index 000000000000..1b02c5ddb31b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412-power.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
+#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
+#define S3C24XX_PWRREG(x)                       ((x) + S3C24XX_VA_CLKPWR)
+#define S3C2412_PWRMODECON                      S3C24XX_PWRREG(0x20)
+#define S3C2412_PWRCFG                          S3C24XX_PWRREG(0x24)
+#define S3C2412_INFORM0                         S3C24XX_PWRREG(0x70)
+#define S3C2412_INFORM1                         S3C24XX_PWRREG(0x74)
+#define S3C2412_INFORM2                         S3C24XX_PWRREG(0x78)
+#define S3C2412_INFORM3                         S3C24XX_PWRREG(0x7C)
+#define S3C2412_PWRCFG_BATF_IRQ                 (1 << 0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2 << 0)
+#define S3C2412_PWRCFG_BATF_SLEEP               (3 << 0)
+#define S3C2412_PWRCFG_BATF_MASK                (3 << 0)
+#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3 << 6)
+#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3 << 6)
+#define S3C2412_PWRCFG_RTC_MASKIRQ              (1 << 8)
+#define S3C2412_PWRCFG_NAND_NORST               (1 << 9)
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 6c5f4031ff0c..0d592159a5c3 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s3c2412/s3c2412.c
+/*
- *
 * Copyright (c) 2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -28,28 +27,31 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
-#include <plat/cpu-freq.h>
+#include <mach/hardware.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
-#include <plat/regs-spi.h>
-#include <mach/regs-s3c2412.h>
-#include <plat/s3c2412.h>
+#include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
 #include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/pm.h>
-#include <plat/pll.h>
 #include <plat/nand-core.h>
+#include <plat/pll.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-spi.h>
+#include <plat/s3c2412.h>
+#include "common.h"
+#include "regs-dsc.h"
+#include "s3c2412-power.h"
+#define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
+#define S3C2412_SWRST_RESET             (0x533C2412)
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -244,8 +246,8 @@ int __init s3c2412_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2412_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
        return device_register(&s3c2412_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h
new file mode 100644
index 000000000000..548ced42cbb7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
+#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
+#define S3C2412_MEMREG(x)               (S3C24XX_VA_MEMCTRL + (x))
+#define S3C2412_EBIREG(x)               (S3C2412_VA_EBI + (x))
+#define S3C2412_SSMCREG(x)              (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o)              (S3C2412_SSMCREG((x * 0x20) + (o)))
+#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
+#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x4)
+#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x0)
+#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 77ee0b732237..e30476db0295 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -63,6 +63,8 @@
 #include <plat/rtc-core.h>
 #include <plat/spi-core.h>
+#include "common.h"
 static struct map_desc s3c2416_iodesc[] __initdata = {
        IODESC_ENT(WATCHDOG),
        IODESC_ENT(CLKPWR),
@@ -105,9 +107,9 @@ int __init s3c2416_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2416_pm_syscore_ops);
-#endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        register_syscore_ops(&s3c2416_irq_syscore_ops);
+#endif
        return device_register(&s3c2416_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 2b3dddb49af7..559e394e8989 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -40,6 +40,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 static struct device s3c2440_dev = {
        .bus            = &s3c2440_subsys,
 };
@@ -57,9 +59,9 @@ int __init s3c2440_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        /* register our system device for everything else */
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 22cb7c94a8c8..f732826c2359 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -51,6 +51,8 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
+#include "common.h"
 /* S3C2442 extended clock support */
 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -172,9 +174,9 @@ int __init s3c2442_init(void)
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2410_pm_syscore_ops);
+        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 #endif
        register_syscore_ops(&s3c244x_pm_syscore_ops);
-        register_syscore_ops(&s3c24xx_irq_syscore_ops);
        return device_register(&s3c2442_dev);
 }
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index b0b60a1154d6..ad2671baa910 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -36,7 +36,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-dsc.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
@@ -48,6 +47,8 @@
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
+#include "regs-dsc.h"
 static struct map_desc s3c244x_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
        IODESC_ENT(TIMER),
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index fd0ef05763a9..67cb5120dfeb 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -17,16 +17,13 @@
 #include <linux/device.h>
 #include <linux/io.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
-#include <mach/bast-cpld.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include <plat/devs.h>
+#include "bast.h"
 #include "simtec.h"
 /* platform ops for audio */
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index 029744fcaacb..8884bffa619a 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -27,9 +27,8 @@
 #include <asm/mach/irq.h>
 #include <mach/map.h>
-#include <mach/bast-map.h>
-#include <mach/bast-cpld.h>
+#include "bast.h"
 #include "simtec.h"
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f93171297..38a2f1fdebab 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
@@ -28,12 +28,13 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <asm/mach-types.h>
 #include <plat/pm.h>
+#include "regs-mem.h"
 #define COPYRIGHT ", Copyright 2005 Simtec Electronics"
 /* pm_simtec_init
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index ddf7a3c743ac..2ed2e32430dc 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -28,15 +28,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/bast-map.h>
-#include <mach/bast-irq.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/devs.h>
+#include "bast.h"
 #include "simtec.h"
 /* control power and monitor over-current events on various Simtec
@@ -79,7 +77,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
        int ret;
        if (on) {
-                ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
+                ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
                                  IRQF_DISABLED | IRQF_TRIGGER_RISING |
                                   IRQF_TRIGGER_FALLING,
                                  "USB Over-current", info);
@@ -87,7 +85,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
                        printk(KERN_ERR "failed to request usb oc irq\n");
                }
        } else {
-                free_irq(IRQ_USBOC, info);
+                free_irq(BAST_IRQ_USBOC, info);
        }
 }
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..dd47c8fa07fa 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -31,9 +31,10 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
+#include "regs-mem.h"
        /* s3c2410_cpu_suspend
         *
         * put the cpu into sleep mode
@@ -45,9 +46,9 @@ ENTRY(s3c2410_cpu_suspend)
        ldr     r4, =S3C2410_REFRESH
        ldr     r5, =S3C24XX_MISCCR
        ldr     r6, =S3C2410_CLKCON
-        ldr     r7, [ r4 ]              @ get REFRESH (and ensure in TLB)
+        ldr     r7, [r4]                @ get REFRESH (and ensure in TLB)
-        ldr     r8, [ r5 ]              @ get MISCCR (and ensure in TLB)
+        ldr     r8, [r5]                @ get MISCCR (and ensure in TLB)
-        ldr     r9, [ r6 ]              @ get CLKCON (and ensure in TLB)
+        ldr     r9, [r6]                @ get CLKCON (and ensure in TLB)
        orr     r7, r7, #S3C2410_REFRESH_SELF   @ SDRAM sleep command
        orr     r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
@@ -61,8 +62,8 @@ ENTRY(s3c2410_cpu_suspend)
        @@ align next bit of code to cache line
        .align  5
 s3c2410_do_sleep:
-        streq   r7, [ r4 ]                      @ SDRAM sleep command
+        streq   r7, [r4]                        @ SDRAM sleep command
-        streq   r8, [ r5 ]                      @ SDRAM power-down config
+        streq   r8, [r5]                        @ SDRAM power-down config
-        streq   r9, [ r6 ]                      @ CPU sleep
+        streq   r9, [r6]                        @ CPU sleep
 1:      beq     1b
        mov     pc, r14
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
index c82418ed714d..5adaceb7da13 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
@@ -57,12 +57,12 @@ s3c2412_sleep_enter1:
         * retry, as simply returning causes the system to lock.
        */
-        ldrne   r9, [ r1 ]
+        ldrne   r9, [r1]
-        strne   r9, [ r1 ]
+        strne   r9, [r1]
-        ldrne   r9, [ r2 ]
+        ldrne   r9, [r2]
-        strne   r9, [ r2 ]
+        strne   r9, [r2]
-        ldrne   r9, [ r3 ]
+        ldrne   r9, [r3]
-        strne   r9, [ r3 ]
+        strne   r9, [r3]
        bne     s3c2412_sleep_enter1
        mov     pc, r14
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index c56612569b40..7f378b662da6 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -31,7 +31,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
 #include <plat/regs-serial.h>
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c24xx/vr1000.h
new file mode 100644
index 000000000000..7fcd2c2f183c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/vr1000.h
@@ -0,0 +1,118 @@
+/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ * Machine VR1000 - IRQ Number definitions
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C24XX_VR1000_H
+#define __MACH_S3C24XX_VR1000_H __FILE__
+#define VR1000_CPLD_CTRL2_RAMWEN        (0x04)  /* SRAM Write Enable */
+/* irq numbers to onboard peripherals */
+#define VR1000_IRQ_USBOC                IRQ_EINT19
+#define VR1000_IRQ_IDE0                 IRQ_EINT16
+#define VR1000_IRQ_IDE1                 IRQ_EINT17
+#define VR1000_IRQ_SERIAL               IRQ_EINT12
+#define VR1000_IRQ_DM9000A              IRQ_EINT10
+#define VR1000_IRQ_DM9000N              IRQ_EINT9
+#define VR1000_IRQ_SMALERT              IRQ_EINT8
+/* map */
+#define VR1000_IOADDR(x)                (S3C2410_ADDR((x) + 0x01300000))
+/* we put the CPLD registers next, to get them out of the way */
+#define VR1000_VA_CTRL1                 VR1000_IOADDR(0x00000000) /* 0x01300000 */
+#define VR1000_PA_CTRL1                 (S3C2410_CS5 | 0x7800000)
+#define VR1000_VA_CTRL2                 VR1000_IOADDR(0x00100000) /* 0x01400000 */
+#define VR1000_PA_CTRL2                 (S3C2410_CS1 | 0x6000000)
+#define VR1000_VA_CTRL3                 VR1000_IOADDR(0x00200000) /* 0x01500000 */
+#define VR1000_PA_CTRL3                 (S3C2410_CS1 | 0x6800000)
+#define VR1000_VA_CTRL4                 VR1000_IOADDR(0x00300000) /* 0x01600000 */
+#define VR1000_PA_CTRL4                 (S3C2410_CS1 | 0x7000000)
+/* next, we have the PC104 ISA interrupt registers */
+#define VR1000_PA_PC104_IRQREQ          (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ          VR1000_IOADDR(0x00400000)
+#define VR1000_PA_PC104_IRQRAW          (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW          VR1000_IOADDR(0x00500000)
+#define VR1000_PA_PC104_IRQMASK         (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK         VR1000_IOADDR(0x00600000)
+/*
+ * 0xE0000000 contains the IO space that is split by speed and
+ * whether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+#define VR1000_VA_MULTISPACE    (0xE0000000)
+#define VR1000_VA_ISAIO         (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM        (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI        (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX     (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC        (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX     (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET       (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000        (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO       (VR1000_VA_MULTISPACE + 0x02600000)
+/* physical offset addresses for the peripherals */
+#define VR1000_PA_IDEPRI        (0x02000000)
+#define VR1000_PA_IDEPRIAUX     (0x02800000)
+#define VR1000_PA_IDESEC        (0x03000000)
+#define VR1000_PA_IDESECAUX     (0x03800000)
+#define VR1000_PA_DM9000        (0x05000000)
+#define VR1000_PA_SERIAL        (0x11800000)
+#define VR1000_VA_SERIAL        (VR1000_IOADDR(0x00700000))
+/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
+#define VR1000_PA_SRAM          (S3C2410_CS1 | 0x05000000)
+/* some configurations for the peripherals */
+#define VR1000_DM9000_CS        VR1000_VAM_CS4
+#endif /* __MACH_S3C24XX_VR1000_H */
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 803711e283b2..8499415be9cd 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu.h>
@@ -33,6 +32,8 @@
 #include <plat/clock-clksrc.h>
 #include <plat/pll.h>
+#include "regs-sys.h"
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
 * ext_xtal_mux for want of an actual name from the manual.
 */
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index aef303b8997e..0b9c0ba44834 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -25,10 +25,10 @@
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
+#include <linux/irqchip/arm-vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/hardware/vic.h>
 #include <asm/system_misc.h>
 #include <mach/map.h>
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
index acb197ccf3f7..ead5fab0dbb5 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -20,8 +20,8 @@
 #include <mach/map.h>
-#include <mach/regs-sys.h>
+#include "regs-sys.h"
-#include <mach/regs-syscon-power.h>
+#include "regs-syscon-power.h"
 static int s3c64xx_enter_idle(struct cpuidle_device *dev,
                              struct cpuidle_driver *drv,
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/crag6410.h
index 4c3c9994fc2c..4c3c9994fc2c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/crag6410.h
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index f2a7a1725596..6af1aa1ef213 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -23,14 +23,13 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/amba/pl080.h>
 #include <mach/dma.h>
 #include <mach/map.h>
 #include <mach/irqs.h>
-#include <mach/regs-sys.h>
+#include "regs-sys.h"
-#include <asm/hardware/pl080.h>
 /* dma channel state information */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
index bcce68a0bb75..6a1127891c87 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
@@ -15,6 +15,5 @@
 #ifndef __ASM_ARCH_REGS_IRQ_H
 #define __ASM_ARCH_REGS_IRQ_H __FILE__
-#include <asm/hardware/vic.h>
 #endif /* __ASM_ARCH_6400_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
deleted file mode 100644
index b91e02093289..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX system register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_SYS_H
-#define __PLAT_REGS_SYS_H __FILE__
-#define S3C_SYSREG(x)           (S3C_VA_SYS + (x))
-#define S3C64XX_AHB_CON0        S3C_SYSREG(0x100)
-#define S3C64XX_AHB_CON1        S3C_SYSREG(0x104)
-#define S3C64XX_AHB_CON2        S3C_SYSREG(0x108)
-#define S3C64XX_SDMA_SEL        S3C_SYSREG(0x110)
-#define S3C64XX_OTHERS          S3C_SYSREG(0x900)
-#define S3C64XX_OTHERS_USBMASK  (1 << 16)
-#define S3C64XX_OTHERS_SYNCMUXSEL       (1 << 6)
-#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h
index ebe18a9469b8..db9c1b1d56a4 100644
--- a/arch/arm/mach-s3c64xx/include/mach/tick.h
+++ b/arch/arm/mach-s3c64xx/include/mach/tick.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARCH_TICK_H
 #define __ASM_ARCH_TICK_H __FILE__
+#include <linux/irqchip/arm-vic.h>
 /* note, the timer interrutps turn up in 2 places, the vic and then
 * the timer block. We take the VIC as the base at the moment.
 */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 99e82ac81b69..728eef3296b2 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -31,7 +31,6 @@
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -50,9 +49,9 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
 #include "common.h"
+#include "regs-modem.h"
 /* DM9000 */
 #define ANW6410_PA_DM9000       (0x18000000)
@@ -230,10 +229,9 @@ MACHINE_START(ANW6410, "A&W6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = anw6410_map_io,
        .init_machine   = anw6410_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 755c0bb119f4..bf3d1c09b085 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/spi-s3c64xx.h>
-#include <mach/crag6410.h>
+#include "crag6410.h"
 static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
        .line = S3C64XX_GPC(3),
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index bf6311a28f3d..1acf02bace57 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -42,7 +42,6 @@
 #include <sound/wm1250-ev1.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -50,12 +49,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/crag6410.h>
-#include <mach/regs-gpio-memport.h>
 #include <plat/regs-serial.h>
 #include <plat/fb.h>
@@ -72,6 +66,10 @@
 #include <plat/pm.h>
 #include "common.h"
+#include "crag6410.h"
+#include "regs-gpio-memport.h"
+#include "regs-modem.h"
+#include "regs-sys.h"
 /* serial port setup */
@@ -867,10 +865,9 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
        /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = crag6410_map_io,
        .init_machine   = crag6410_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 2b144893ddc4..7212eb9cfeb9 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -273,10 +272,9 @@ MACHINE_START(HMT, "Airgoo-HMT")
        /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = hmt_map_io,
        .init_machine   = hmt_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 07c349cca333..4b41fcdaa7b6 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -24,15 +24,12 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/regs-srom.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
@@ -46,6 +43,8 @@
 #include <video/samsung_fimd.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -352,10 +351,9 @@ MACHINE_START(MINI6410, "MINI6410")
        /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = mini6410_map_io,
        .init_machine   = mini6410_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index e5f9a79b535d..8d3cedd995ff 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -26,7 +26,6 @@
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -101,10 +100,9 @@ MACHINE_START(NCP, "NCP")
        /* Maintainer: Samsung Electronics */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = ncp_map_io,
        .init_machine   = ncp_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 7476f7c722ab..fa12bd21ad82 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -25,15 +25,12 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
-#include <mach/regs-srom.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
@@ -47,6 +44,8 @@
 #include <video/samsung_fimd.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -331,10 +330,9 @@ MACHINE_START(REAL6410, "REAL6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = real6410_map_io,
        .init_machine   = real6410_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index c6d7390939ae..fc3e9b32e26f 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -25,7 +25,6 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-modem.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -41,6 +40,7 @@
 #include <video/platform_lcd.h>
 #include "common.h"
+#include "regs-modem.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 96d6da2b6b5f..ca2afcfce573 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -17,7 +17,6 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -153,10 +152,9 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq5_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 7d1167bdc921..37bb0c632a5e 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -17,7 +17,6 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -169,10 +168,9 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq7_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a928fae5694e..a392869c8342 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -22,7 +22,6 @@
 #include <asm/mach-types.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -90,10 +89,9 @@ MACHINE_START(SMDK6400, "SMDK6400")
        .atag_offset    = 0x100,
        .init_irq       = s3c6400_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6400_map_io,
        .init_machine   = smdk6400_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 574a9eef588d..ba7544e2d04d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -45,7 +45,6 @@
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -57,10 +56,7 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <mach/regs-modem.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-sys.h>
-#include <mach/regs-srom.h>
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
@@ -75,6 +71,9 @@
 #include <plat/backlight.h>
 #include "common.h"
+#include "regs-modem.h"
+#include "regs-srom.h"
+#include "regs-sys.h"
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -700,10 +699,9 @@ MACHINE_START(SMDK6410, "SMDK6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6410_map_io,
        .init_machine   = smdk6410_machine_init,
        .init_late      = s3c64xx_init_late,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index d2e1a16690bd..6a1f91fea678 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -26,12 +26,13 @@
 #include <plat/pm.h>
 #include <plat/wakeup-mask.h>
-#include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-syscon-power.h>
-#include <mach/regs-gpio-memport.h>
+#include "regs-gpio-memport.h"
-#include <mach/regs-modem.h>
+#include "regs-modem.h"
+#include "regs-sys.h"
+#include "regs-syscon-power.h"
 struct s3c64xx_pm_domain {
        char *const name;
@@ -296,7 +297,8 @@ static int s3c64xx_cpu_suspend(unsigned long arg)
        /* we should never get past here */
-        panic("sleep resumed to originator?");
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
 }
 /* mapping of interrupts to parts of the wakeup mask */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/regs-gpio-memport.h
index 82342f6fd27d..b927593019f5 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
+++ b/arch/arm/mach-s3c64xx/regs-gpio-memport.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
@@ -8,8 +7,8 @@
 * S3C64XX - GPIO memory port register definitions
 */
-#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#ifndef __MACH_S3C64XX_REGS_GPIO_MEMPORT_H
-#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+#define __MACH_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
 #define S3C64XX_MEM0CONSTOP     S3C64XX_GPIOREG(0x1B0)
 #define S3C64XX_MEM1CONSTOP     S3C64XX_GPIOREG(0x1B4)
@@ -21,5 +20,5 @@
 #define S3C64XX_MEM0DRVCON      S3C64XX_GPIOREG(0x1D0)
 #define S3C64XX_MEM1DRVCON      S3C64XX_GPIOREG(0x1D4)
-#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+#endif /* __MACH_S3C64XX_REGS_GPIO_MEMPORT_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/regs-modem.h
index 49f7759dedfa..073cdd3a03be 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
+++ b/arch/arm/mach-s3c64xx/regs-modem.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
@@ -12,10 +11,10 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#ifndef __MACH_S3C64XX_REGS_MODEM_H
-#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+#define __MACH_S3C64XX_REGS_MODEM_H __FILE__
-#define S3C64XX_MODEMREG(x)     (S3C64XX_VA_MODEM + (x))
+#define S3C64XX_MODEMREG(x)                     (S3C64XX_VA_MODEM + (x))
 #define S3C64XX_MODEM_INT2AP                    S3C64XX_MODEMREG(0x0)
 #define S3C64XX_MODEM_INT2MODEM                 S3C64XX_MODEMREG(0x4)
@@ -28,4 +27,4 @@
 #define MIFPCON_INT2M_LEVEL                     (1 << 4)
 #define MIFPCON_LCD_BYPASS                      (1 << 3)
-#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
+#endif /* __MACH_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/regs-srom.h
index 756731b36297..d56f3386eb00 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
+++ b/arch/arm/mach-s3c64xx/regs-srom.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
+/*
- *
 * Copyright 2009 Andy Green <andy@warmcat.com>
 *
 * S3C64XX SROM definitions
@@ -9,8 +8,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_REGS_SROM_H
+#ifndef __MACH_S3C64XX_REGS_SROM_H
-#define __PLAT_REGS_SROM_H __FILE__
+#define __MACH_S3C64XX_REGS_SROM_H __FILE__
 #define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
@@ -29,7 +28,7 @@
 #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
 #define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
 #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
-#define S3C64XX_SROM_BW__CS_MASK 0xf
+#define S3C64XX_SROM_BW__CS_MASK                0xf
 #define S3C64XX_SROM_BW__NCS0__SHIFT    0
 #define S3C64XX_SROM_BW__NCS1__SHIFT    4
@@ -56,4 +55,4 @@
 #define S3C64XX_SROM_BCX__TACS__SHIFT   28
 #define S3C64XX_SROM_BCX__TACS__MASK    0xf
-#endif /* _PLAT_REGS_SROM_H */
+#endif /* __MACH_S3C64XX_REGS_SROM_H */
diff --git a/arch/arm/mach-s3c64xx/regs-sys.h b/arch/arm/mach-s3c64xx/regs-sys.h
new file mode 100644
index 000000000000..8c411fbb0cd9
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/regs-sys.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX system register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __MACH_S3C64XX_REGS_SYS_H
+#define __MACH_S3C64XX_REGS_SYS_H __FILE__
+#define S3C_SYSREG(x)                   (S3C_VA_SYS + (x))
+#define S3C64XX_AHB_CON0                S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1                S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2                S3C_SYSREG(0x108)
+#define S3C64XX_SDMA_SEL                S3C_SYSREG(0x110)
+#define S3C64XX_OTHERS                  S3C_SYSREG(0x900)
+#define S3C64XX_OTHERS_USBMASK          (1 << 16)
+#define S3C64XX_OTHERS_SYNCMUXSEL       (1 << 6)
+#endif /* __MACH_S3C64XX_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/regs-syscon-power.h
index 270d96ac9705..6e16b3404da9 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
+++ b/arch/arm/mach-s3c64xx/regs-syscon-power.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
@@ -12,8 +11,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
-#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
 #define S3C64XX_PWR_CFG                         S3C_SYSREG(0x804)
@@ -113,4 +112,4 @@
 #define S3C64XX_INFORM2                         S3C_SYSREG(0xA08)
 #define S3C64XX_INFORM3                         S3C_SYSREG(0xA0C)
-#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
+#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e02d7db..c8174d95339b 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -15,11 +15,12 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <plat/cpu.h>
 #include <plat/regs-usb-hsotg-phy.h>
 #include <plat/usb-phy.h>
+#include "regs-sys.h"
 static int s3c_usb_otgphy_init(struct platform_device *pdev)
 {
        struct clk *xusbxti;
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 5112371079d0..3537815247f1 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/s5p64x0-clock.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -32,6 +31,7 @@
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include "clock.h"
 #include "common.h"
 static u32 epll_div[][5] = {
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 154dea702d70..af384ddd2dcf 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -23,7 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/s5p64x0-clock.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -32,6 +31,7 @@
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include "clock.h"
 #include "common.h"
 static struct clksrc_clk clk_mout_dpll = {
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/clock.h
index 0ef47d1b7670..28b8e3c6bd24 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/clock.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+/*
- *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
@@ -10,8 +9,8 @@
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_CLOCK_H
+#ifndef __MACH_S5P64X0_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
+#define __MACH_S5P64X0_CLOCK_H __FILE__
 #include <linux/clk.h>
@@ -36,4 +35,4 @@ extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
 extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
-#endif /* __ASM_ARCH_CLOCK_H */
+#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
deleted file mode 100644
index 700dac6c43f3..000000000000
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/gpiolib.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-/*
- * S5P6440 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * F    2       2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    8       2Bit    Yes     8
- * R    15      4Bit[2] Yes     8
- *
- * S5P6450 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    8       4Bit    Yes     None
- * F    2       2Bit    Yes     None
- * G    14      4Bit[2] Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    5       4Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    11      2Bit    Yes     8
- * Q    14      2Bit    Yes     None
- * R    15      4Bit[2] Yes     None
- * S    8       2Bit    Yes     None
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
-                                             unsigned int offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long flags;
-        switch (offset) {
-        case 6:
-                offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                offset -= 7;
-                break;
-        }
-        s3c_gpio_lock(ourchip, flags);
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
-                                              unsigned int offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned long flags;
-        unsigned con_offset  = offset;
-        switch (con_offset) {
-        case 6:
-                con_offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                con_offset -= 7;
-                break;
-        }
-        s3c_gpio_lock(ourchip, flags);
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-        dat = __raw_readl(base + GPIODAT_OFF);
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
-                                   unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift;
-        u32 con;
-        switch (off) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                shift = (off & 7) * 4;
-                reg -= 4;
-                break;
-        case 6:
-                shift = ((off + 1) & 7) * 4;
-                reg -= 4;
-        default:
-                shift = ((off + 1) & 7) * 4;
-                break;
-        }
-        if (s3c_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-        return 0;
-}
-static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
-        {
-                .cfg_eint       = 0,
-        }, {
-                .cfg_eint       = 7,
-        }, {
-                .cfg_eint       = 3,
-                .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
-        }, {
-                .cfg_eint       = 0,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        }, {
-                .cfg_eint       = 2,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        }, {
-                .cfg_eint       = 3,
-                .set_config     = s3c_gpio_setcfg_s3c24xx,
-                .get_config     = s3c_gpio_getcfg_s3c24xx,
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
-        {
-                .base   = S5P64X0_GPA_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPA(0),
-                        .ngpio  = S5P6440_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .base   = S5P64X0_GPB_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPB(0),
-                        .ngpio  = S5P6440_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .base   = S5P64X0_GPC_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPC(0),
-                        .ngpio  = S5P6440_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P64X0_GPG_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPG(0),
-                        .ngpio  = S5P6440_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
-        {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6440_GPH(0),
-                        .ngpio  = S5P6440_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[2],
-                .chip   = {
-                        .base   = S5P6440_GPR(0),
-                        .ngpio  = S5P6440_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPF(0),
-                        .ngpio  = S5P6440_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6440_GPI(0),
-                        .ngpio  = S5P6440_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6440_GPJ(0),
-                        .ngpio  = S5P6440_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPN(0),
-                        .ngpio  = S5P6440_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPP(0),
-                        .ngpio  = S5P6440_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
-        {
-                .base   = S5P64X0_GPA_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPA(0),
-                        .ngpio  = S5P6450_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .base   = S5P64X0_GPB_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPB(0),
-                        .ngpio  = S5P6450_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .base   = S5P64X0_GPC_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPC(0),
-                        .ngpio  = S5P6450_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P6450_GPD_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPD(0),
-                        .ngpio  = S5P6450_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .base   = S5P6450_GPK_BASE,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPK(0),
-                        .ngpio  = S5P6450_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
-        {
-                .base   = S5P64X0_GPG_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPG(0),
-                        .ngpio  = S5P6450_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S5P6450_GPH(0),
-                        .ngpio  = S5P6450_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfgs[2],
-                .chip   = {
-                        .base   = S5P6450_GPR(0),
-                        .ngpio  = S5P6450_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-};
-static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPF(0),
-                        .ngpio  = S5P6450_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6450_GPI(0),
-                        .ngpio  = S5P6450_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &s5p64x0_gpio_cfgs[3],
-                .chip   = {
-                        .base   = S5P6450_GPJ(0),
-                        .ngpio  = S5P6450_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPN(0),
-                        .ngpio  = S5P6450_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPP(0),
-                        .ngpio  = S5P6450_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .base   = S5P6450_GPQ_BASE,
-                .config = &s5p64x0_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPQ(0),
-                        .ngpio  = S5P6450_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        }, {
-                .base   = S5P6450_GPS_BASE,
-                .config = &s5p64x0_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPS(0),
-                        .ngpio  = S5P6450_GPIO_S_NR,
-                        .label  = "GPS",
-                },
-        },
-};
-void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chipcfg++) {
-                if (!chipcfg->set_config)
-                        chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
-                if (!chipcfg->get_config)
-                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
-                if (!chipcfg->set_pull)
-                        chipcfg->set_pull       = s3c_gpio_setpull_updown;
-                if (!chipcfg->get_pull)
-                        chipcfg->get_pull       = s3c_gpio_getpull_updown;
-        }
-}
-static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
-                                                int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
-                chip->chip.direction_output =
-                                        s5p64x0_gpiolib_rbank_4bit2_output;
-                s3c_gpiolib_add(chip);
-        }
-}
-static int __init s5p64x0_gpiolib_init(void)
-{
-        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
-                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
-        if (soc_is_s5p6450()) {
-                samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
-                                        ARRAY_SIZE(s5p6450_gpio_2bit));
-                samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
-                                        ARRAY_SIZE(s5p6450_gpio_4bit));
-                samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
-                                        ARRAY_SIZE(s5p6450_gpio_4bit2));
-                s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
-                                        ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
-        } else {
-                samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
-                                        ARRAY_SIZE(s5p6440_gpio_2bit));
-                samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
-                                        ARRAY_SIZE(s5p6440_gpio_4bit));
-                samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
-                                        ARRAY_SIZE(s5p6440_gpio_4bit2));
-                s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
-                                        ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
-        }
-        return 0;
-}
-core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
index 887d25209e8e..1e5bb4ea200d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/i2c.h
+++ b/arch/arm/mach-s5p64x0/i2c.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
+/*
- *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index 4aaebdace55f..d60397d1ff40 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_ARCH_REGS_IRQ_H
 #define __ASM_ARCH_REGS_IRQ_H __FILE__
-#include <asm/hardware/vic.h>
 #include <mach/map.h>
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
deleted file mode 100644
index 00aa7f1d8e51..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/tick.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S5P64X0 - Timer tick support definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TICK_H
-#define __ASM_ARCH_TICK_H __FILE__
-static inline u32 s3c24xx_ostimer_pending(void)
-{
-        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
-        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
-}
-#define TICK_MAX        (0xffffffff)
-#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 1608faf870ff..19e0d64d78c5 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -116,33 +116,6 @@ static inline void flush(void)
                *((volatile unsigned int __force *)(ad)) = (d); \
        } while (0)
-/*
- * CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
- */
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-#define WDOG_COUNT (0xff00)
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
@@ -192,7 +165,6 @@ static void arch_decomp_setup(void)
         */
        arch_detect_cpu();
-        arch_decomp_wdog_start();
        /*
         * Enable the UART FIFOs if they where not enabled and our
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 1af823558c60..e23723a5a214 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -29,7 +29,6 @@
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -38,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/i2c.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
@@ -56,6 +54,7 @@
 #include <plat/sdhci.h>
 #include "common.h"
+#include "i2c.h"
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
@@ -272,9 +271,8 @@ MACHINE_START(SMDK6440, "SMDK6440")
        .atag_offset    = 0x100,
        .init_irq       = s5p6440_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6440_map_io,
        .init_machine   = smdk6440_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 62526ccf6b70..ca10963a959e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -29,7 +29,6 @@
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -38,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/i2c.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
@@ -56,6 +54,7 @@
 #include <plat/sdhci.h>
 #include "common.h"
+#include "i2c.h"
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
@@ -291,9 +290,8 @@ MACHINE_START(SMDK6450, "SMDK6450")
        .atag_offset    = 0x100,
        .init_irq       = s5p6450_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6450_map_io,
        .init_machine   = smdk6450_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 9cba18bfe47b..97c2a08ad490 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -103,8 +103,8 @@ static int s5p64x0_cpu_suspend(unsigned long arg)
            "mcr p15, 0, %0, c7, c10, 4\n\t"
            "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 /* mapping of interrupts to parts of the wakeup mask */
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index a32edc545e6c..569b76ac98cb 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/i2c.h>
+#include "i2c.h"
 void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index ca2c5c7f8aa6..867374e6d0bc 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/i2c.h>
+#include "i2c.h"
 void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 4d9036d0f288..761627897f30 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -14,6 +14,5 @@
 #define __ASM_ARCH_REGS_IRQ_H __FILE__
 #include <mach/map.h>
-#include <asm/hardware/vic.h>
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index 20f68730ed18..0af8e41230ed 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARCH_TICK_H
 #define __ASM_ARCH_TICK_H __FILE__
+#include <linux/irqchip/arm-vic.h>
 /* note, the timer interrutps turn up in 2 places, the vic and then
 * the timer block. We take the VIC as the base at the moment.
 */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 9abe95e806ab..185a19583898 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -25,7 +25,6 @@
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -254,9 +253,8 @@ MACHINE_START(SMDKC100, "SMDKC100")
        /* Maintainer: Byungho Min <bhmin@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pc100_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc100_map_io,
        .init_machine   = smdkc100_machine_init,
-        .timer          = &s3c24xx_timer,
+        .init_time      = s3c24xx_timer_init,
        .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index addfb165c13d..2d67361ef431 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,7 +18,8 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
-#include <mach/regs-audss.h>
+#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
 static int s5pv210_cfg_i2s(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
deleted file mode 100644
index eacc1f790807..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-audss.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
- *
- * Copyright (c) 2011 Samsung Electronics
- *              http://www.samsung.com
- *
- * S5PV210 Audio SubSystem clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_REGS_AUDSS_H
-#define __PLAT_REGS_AUDSS_H __FILE__
-#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
-#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
index 5c3b104a7c86..d8bc1e6c7aaa 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_ARCH_REGS_IRQ_H
 #define __ASM_ARCH_REGS_IRQ_H __FILE__
-#include <asm/hardware/vic.h>
 #include <mach/map.h>
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
deleted file mode 100644
index cccb1eddaa38..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-sys.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - System registers definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
-#define S5PV210_USB_PHY0_EN     (1 << 0)
-#define S5PV210_USB_PHY1_EN     (1 << 1)
diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h
deleted file mode 100644
index 7993b3603ccf..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/tick.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/tick.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s3c6400/include/mach/tick.h
- *
- * S5PV210 - Timer tick support definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TICK_H
-#define __ASM_ARCH_TICK_H __FILE__
-static inline u32 s3c24xx_ostimer_pending(void)
-{
-        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
-        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
-}
-#define TICK_MAX        (0xffffffff)
-#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index 08ff2fda1fb9..ef977ea8546d 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -19,6 +19,8 @@
 static void arch_detect_cpu(void)
 {
        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S5PV210_UFSTAT_TXMASK;
+        fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index ee9fa5c2ef2c..11900a8e88a3 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -22,7 +22,6 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -685,9 +684,8 @@ MACHINE_START(AQUILA, "Aquila")
           Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = aquila_map_io,
        .init_machine   = aquila_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index c72b31078c99..3a38f7b34b94 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -29,7 +29,6 @@
 #include <linux/interrupt.h>
 #include <linux/platform_data/s3c-hsotg.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -841,12 +840,12 @@ static struct i2c_board_info noon010pc30_board_info = {
        .platform_data = &noon010pc30_pldata,
 };
-static struct s5p_fimc_isp_info goni_camera_sensors[] = {
+static struct fimc_source_info goni_camera_sensors[] = {
        {
                .mux_id         = 0,
                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .bus_type       = FIMC_ITU_601,
+                .bus_type       = FIMC_BUS_TYPE_ITU_601,
                .board_info     = &noon010pc30_board_info,
                .i2c_bus_num    = 0,
                .clk_frequency  = 16000000UL,
@@ -854,7 +853,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
 };
 static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
-        .isp_info       = goni_camera_sensors,
+        .source_info    = goni_camera_sensors,
        .num_clients    = ARRAY_SIZE(goni_camera_sensors),
 };
@@ -972,10 +971,9 @@ MACHINE_START(GONI, "GONI")
        /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = goni_map_io,
        .init_machine   = goni_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .reserve        = &goni_reserve,
        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index f1f3bd37ecda..28bd0248a3e2 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -15,7 +15,6 @@
 #include <linux/i2c.h>
 #include <linux/device.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -152,10 +151,9 @@ MACHINE_START(SMDKC110, "SMDKC110")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc110_map_io,
        .init_machine   = smdkc110_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5pv210_restart,
        .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 6bc8404bf678..3c73f36869bb 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -21,7 +21,6 @@
 #include <linux/pwm_backlight.h>
 #include <linux/platform_data/s3c-hsotg.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -328,10 +327,9 @@ MACHINE_START(SMDKV210, "SMDKV210")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = smdkv210_map_io,
        .init_machine   = smdkv210_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5pv210_restart,
        .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 18785cb5e1ef..2d4c5531819c 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -129,9 +128,8 @@ MACHINE_START(TORBRECK, "TORBRECK")
        /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
-        .handle_irq     = vic_handle_irq,
        .map_io         = torbreck_map_io,
        .init_machine   = torbreck_machine_init,
-        .timer          = &s5p_timer,
+        .init_time      = s5p_timer_init,
        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 736bfb103cbc..2b68a67b6e95 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -104,8 +104,8 @@ static int s5pv210_cpu_suspend(unsigned long arg)
            "mcr p15, 0, %0, c7, c10, 4\n\t"
            "wfi" : : "r" (tmp));
-        /* we should never get past here */
+        pr_info("Failed to suspend the system\n");
-        panic("sleep resumed to originator?");
+        return 1; /* Aborting suspend */
 }
 static void s5pv210_pm_prepare(void)
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
index be39cf4aa91b..356a0900af03 100644
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ b/arch/arm/mach-s5pv210/setup-usb-phy.c
@@ -12,12 +12,17 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <mach/map.h>
-#include <mach/regs-sys.h>
 #include <plat/cpu.h>
 #include <plat/regs-usb-hsotg-phy.h>
 #include <plat/usb-phy.h>
+#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
+#define S5PV210_USB_PHY0_EN     (1 << 0)
+#define S5PV210_USB_PHY1_EN     (1 << 1)
 static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
 {
        struct clk *xusbxti;
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 9a23739f7026..e838ba27e443 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -16,6 +16,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_data/sa11x0-serial.h>
 #include <linux/serial_core.h>
+#include <linux/platform_device.h>
 #include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -621,7 +622,7 @@ MACHINE_START(ASSABET, "Intel-Assabet")
        .map_io         = assabet_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = assabet_init,
        .init_late      = sa11x0_init_late,
 #ifdef CONFIG_SA1111
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b2dadf3ea3df..63361b6d04e9 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -336,7 +336,7 @@ MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
        .init_late      = sa11x0_init_late,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
 #ifdef CONFIG_SA1111
        .dma_zone_size  = SZ_1M,
 #endif
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 304bca4a07c0..2d25ececb415 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -174,7 +174,7 @@ MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
        .map_io         = cerf_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = cerf_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = cerf_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 45f424f5fca6..612a45689770 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -399,7 +399,7 @@ MACHINE_START(COLLIE, "Sharp-Collie")
        .map_io         = collie_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = collie_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index a5b7c13da3e3..2abc6a1f6e86 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -4,9 +4,7 @@
 * Author: Nicolas Pitre
 */
-struct sys_timer;
+extern void sa1100_timer_init(void);
-extern struct sys_timer sa1100_timer;
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index e1571eab08ae..b8f2b151539b 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -108,7 +108,7 @@ MACHINE_START(H3100, "Compaq iPAQ H3100")
        .map_io         = h3100_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = h3100_mach_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index ba7a2901ab88..b8dc5bd22623 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -158,7 +158,7 @@ MACHINE_START(H3600, "Compaq iPAQ H3600")
        .map_io         = h3600_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = h3600_mach_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index d005939c41fc..643d5f2d9af9 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -229,7 +229,7 @@ MACHINE_START(HACKKIT, "HackKit Cpu Board")
        .map_io         = hackkit_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = hackkit_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 5cf71da60e42..73093dc89829 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -49,4 +49,3 @@ static inline void flush(void)
 * Nothing to do for these
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 35cfc428b4d4..c0b1f5bafae4 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -346,7 +346,7 @@ MACHINE_START(JORNADA720, "HP Jornada 720")
        .map_io         = jornada720_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = jornada720_mach_init,
        .init_late      = sa11x0_init_late,
 #ifdef CONFIG_SA1111
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index f69f78fc3ddd..51b0eb52c014 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -24,9 +24,6 @@
 #include "generic.h"
-#warning "include/asm/arch-sa1100/ide.h needs fixing for lart"
 static struct mcp_plat_data lart_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
@@ -174,6 +171,6 @@ MACHINE_START(LART, "LART")
        .init_irq       = sa1100_init_irq,
        .init_machine   = lart_init,
        .init_late      = sa11x0_init_late,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 102e08f7b109..f1cb3784d525 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -110,7 +110,7 @@ MACHINE_START(NANOENGINE, "BSE nanoEngine")
        .map_io         = nanoengine_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = nanoengine_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index c51bb63f90fb..091261878eff 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -133,7 +133,7 @@ MACHINE_START(PLEB, "PLEB")
        .map_io         = pleb_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = pleb_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 6460d25fbb88..c8866bce7386 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -102,7 +102,7 @@ MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
        .map_io         = shannon_map_io,
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .init_machine   = shannon_init,
        .init_late      = sa11x0_init_late,
        .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 6d65f65fcb23..bcbc94540e45 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -396,6 +396,6 @@ MACHINE_START(SIMPAD, "Simpad")
        .nr_irqs        = SA1100_NR_IRQS,
        .init_irq       = sa1100_init_irq,
        .init_late      = sa11x0_init_late,
-        .timer          = &sa1100_timer,
+        .init_time      = sa1100_timer_init,
        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 80702c9ecc77..a59a13a665a6 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -69,46 +69,10 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
        }
 }
-static struct clock_event_device ckevt_sa1100_osmr0 = {
-        .name           = "osmr0",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_next_event = sa1100_osmr0_set_next_event,
-        .set_mode       = sa1100_osmr0_set_mode,
-};
-static struct irqaction sa1100_timer_irq = {
-        .name           = "ost0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = sa1100_ost0_interrupt,
-        .dev_id         = &ckevt_sa1100_osmr0,
-};
-static void __init sa1100_timer_init(void)
-{
-        writel_relaxed(0, OIER);
-        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
-        setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
-        clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
-        ckevt_sa1100_osmr0.max_delta_ns =
-                clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
-        ckevt_sa1100_osmr0.min_delta_ns =
-                clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
-        ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
-        setup_irq(IRQ_OST0, &sa1100_timer_irq);
-        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
-                clocksource_mmio_readl_up);
-        clockevents_register_device(&ckevt_sa1100_osmr0);
-}
 #ifdef CONFIG_PM
 unsigned long osmr[4], oier;
-static void sa1100_timer_suspend(void)
+static void sa1100_timer_suspend(struct clock_event_device *cedev)
 {
        osmr[0] = readl_relaxed(OSMR0);
        osmr[1] = readl_relaxed(OSMR1);
@@ -117,7 +81,7 @@ static void sa1100_timer_suspend(void)
        oier = readl_relaxed(OIER);
 }
-static void sa1100_timer_resume(void)
+static void sa1100_timer_resume(struct clock_event_device *cedev)
 {
        writel_relaxed(0x0f, OSSR);
        writel_relaxed(osmr[0], OSMR0);
@@ -136,8 +100,36 @@ static void sa1100_timer_resume(void)
 #define sa1100_timer_resume NULL
 #endif
-struct sys_timer sa1100_timer = {
+static struct clock_event_device ckevt_sa1100_osmr0 = {
-        .init           = sa1100_timer_init,
+        .name           = "osmr0",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .set_next_event = sa1100_osmr0_set_next_event,
+        .set_mode       = sa1100_osmr0_set_mode,
        .suspend        = sa1100_timer_suspend,
        .resume         = sa1100_timer_resume,
 };
+static struct irqaction sa1100_timer_irq = {
+        .name           = "ost0",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = sa1100_ost0_interrupt,
+        .dev_id         = &ckevt_sa1100_osmr0,
+};
+void __init sa1100_timer_init(void)
+{
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
+        setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
+        ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
+        setup_irq(IRQ_OST0, &sa1100_timer_irq);
+        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+                clocksource_mmio_readl_up);
+        clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
+                                        MIN_OSCR_DELTA * 2, 0x7fffffff);
+}
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 9ad2e9737fb5..b63dec848195 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -128,10 +128,6 @@ static void __init shark_timer_init(void)
        setup_irq(IRQ_TIMER, &shark_timer_irq);
 }
-static struct sys_timer shark_timer = {
-        .init           = shark_timer_init,
-};
 static void shark_init_early(void)
 {
        disable_hlt();
@@ -142,7 +138,7 @@ MACHINE_START(SHARK, "Shark")
        .atag_offset    = 0x3000,
        .init_early     = shark_init_early,
        .init_irq       = shark_init_irq,
-        .timer          = &shark_timer,
+        .init_time      = shark_timer_init,
        .dma_zone_size  = SZ_4M,
        .restart        = shark_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h
index 22ccab4c3c5e..a168435aecc9 100644
--- a/arch/arm/mach-shark/include/mach/uncompress.h
+++ b/arch/arm/mach-shark/include/mach/uncompress.h
@@ -48,4 +48,3 @@ static void putr()
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0b7147928aa3..e1fac57514b9 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -15,17 +15,10 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
 smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
-# Pinmux setup
-pfc-y                           :=
-pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
-pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
-pfc-$(CONFIG_ARCH_R8A7740)      += pfc-r8a7740.o
-pfc-$(CONFIG_ARCH_R8A7779)      += pfc-r8a7779.o
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 obj-$(CONFIG_ARCH_R8A7740)      += entry-intc.o
@@ -37,6 +30,7 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= pm-rmobile.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o
 obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
+obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 # Board objects
 obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
@@ -51,4 +45,3 @@ obj-$(CONFIG_MACH_KZM9G)	+= board-kzm9g.o
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
-obj-$(CONFIG_GENERIC_GPIO)      += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 032d10817e79..8ff53a19c48c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,6 +40,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
+#include <linux/irqchip/arm-gic.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
@@ -49,7 +50,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
@@ -479,11 +479,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
        static int power_gpio = -EINVAL;
        if (power_gpio < 0) {
-                int ret = gpio_request(GPIO_PORT114, "sdhi1_power");
+                int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
-                if (!ret) {
+                                           "sdhi1_power");
+                if (!ret)
                        power_gpio = GPIO_PORT114;
-                        gpio_direction_output(power_gpio, 0);
-                }
        }
        /*
@@ -604,14 +603,11 @@ static void __init ag5evm_init(void)
        gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
        gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
        gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
-        gpio_request(GPIO_PORT208, NULL); /* Reset */
+        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
-        gpio_direction_output(GPIO_PORT208, 1);
        /* enable SMSC911X */
-        gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
+        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_direction_input(GPIO_PORT144);
+        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-        gpio_request(GPIO_PORT145, NULL); /* RESET */
-        gpio_direction_output(GPIO_PORT145, 1);
        /* FSI A */
        gpio_request(GPIO_FN_FSIACK, NULL);
@@ -626,15 +622,13 @@ static void __init ag5evm_init(void)
        gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
        /* LCD panel */
-        gpio_request(GPIO_PORT217, NULL); /* RESET */
+        gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
-        gpio_direction_output(GPIO_PORT217, 0);
        mdelay(1);
        gpio_set_value(GPIO_PORT217, 1);
        mdelay(100);
        /* LCD backlight controller */
-        gpio_request(GPIO_PORT235, NULL); /* RESET */
+        gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
-        gpio_direction_output(GPIO_PORT235, 0);
        lcd_backlight_set_brightness(0);
        /* enable SDHI0 on CN15 [SD I/F] */
@@ -668,8 +662,7 @@ MACHINE_START(AG5EVM, "ag5evm")
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = ag5evm_init,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = sh73a0_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 99ef190d0909..38f1259a0daf 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -143,6 +143,10 @@
 *
 * SW41 :  ON : SH-Mobile AP4 Audio Mode
 *      : OFF : Bluetooth Audio Mode
+ *
+ * it needs amixer settings for playing
+ *
+ * amixer set "Headphone Enable" on
 */
 /*
@@ -657,14 +661,8 @@ static struct platform_device lcdc_device = {
 /* FSI */
 #define IRQ_FSI         evt2irq(0x1840)
 static struct sh_fsi_platform_info fsi_info = {
-        .port_a = {
-                .flags          = SH_FSI_BRS_INV,
-        },
        .port_b = {
-                .flags          = SH_FSI_BRS_INV |
+                .flags          = SH_FSI_CLK_CPG |
-                                  SH_FSI_BRM_INV |
-                                  SH_FSI_LRS_INV |
-                                  SH_FSI_CLK_CPG |
                                  SH_FSI_FMT_SPDIF,
        },
 };
@@ -692,21 +690,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4643_info = {
        .name           = "AK4643",
        .card           = "FSI2A-AK4643",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0013",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4643_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4643_device = {
@@ -815,18 +813,18 @@ static struct platform_device lcdc1_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
@@ -1042,9 +1040,7 @@ static int ts_get_pendown_state(void)
        gpio_free(GPIO_TSC_IRQ);
-        gpio_request(GPIO_TSC_PORT, NULL);
+        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_TSC_PORT);
        val = gpio_get_value(GPIO_TSC_PORT);
@@ -1125,18 +1121,10 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_IRQ6_39,   NULL);
        /* enable Debug switch (S6) */
-        gpio_request(GPIO_PORT32, NULL);
+        gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request(GPIO_PORT33, NULL);
+        gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request(GPIO_PORT34, NULL);
+        gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request(GPIO_PORT35, NULL);
+        gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_direction_input(GPIO_PORT32);
-        gpio_direction_input(GPIO_PORT33);
-        gpio_direction_input(GPIO_PORT34);
-        gpio_direction_input(GPIO_PORT35);
-        gpio_export(GPIO_PORT32, 0);
-        gpio_export(GPIO_PORT33, 0);
-        gpio_export(GPIO_PORT34, 0);
-        gpio_export(GPIO_PORT35, 0);
        /* SDHI0 */
        gpio_request(GPIO_FN_SDHICD0, NULL);
@@ -1184,8 +1172,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_FSIAILR,   NULL);
        gpio_request(GPIO_FN_FSIAISLD,  NULL);
        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request(GPIO_PORT161,      NULL);
+        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-        gpio_direction_output(GPIO_PORT161, 0); /* slave */
        gpio_request(GPIO_PORT9, NULL);
        gpio_request(GPIO_PORT10, NULL);
@@ -1193,8 +1180,7 @@ static void __init ap4evb_init(void)
        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
        /* card detect pin for MMC slot (CN7) */
-        gpio_request(GPIO_PORT41, NULL);
+        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_PORT41);
        /* setup FSI2 port B (HDMI) */
        gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1282,11 +1268,8 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_LCDDISP,  NULL);
        gpio_request(GPIO_FN_LCDDCK,   NULL);
-        gpio_request(GPIO_PORT189, NULL); /* backlight */
+        gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
-        gpio_direction_output(GPIO_PORT189, 1);
+        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        gpio_request(GPIO_PORT151, NULL); /* LCDDON */
-        gpio_direction_output(GPIO_PORT151, 1);
        lcdc_info.clock_source                  = LCDC_CLK_BUS;
        lcdc_info.ch[0].interface_type          = RGB18;
@@ -1350,5 +1333,5 @@ MACHINE_START(AP4EVB, "ap4evb")
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = ap4evb_init,
        .init_late      = sh7372_pm_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = sh7372_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 5353adf6b828..f2ec0777cfbe 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -124,6 +124,14 @@
 * this command is required when playback.
 *
 * # amixer set "Headphone" 50
+ *
+ * this command is required when capture.
+ *
+ * # amixer set "Input PGA" 15
+ * # amixer set "Left Input Mixer MicP" on
+ * # amixer set "Left Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicP" on
 */
 /*
@@ -700,9 +708,9 @@ static int mt9t111_power(struct device *dev, int mode)
                /* video1 (= CON1 camera) expect 24MHz */
                clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
                clk_enable(mclk);
-                gpio_direction_output(GPIO_PORT158, 1);
+                gpio_set_value(GPIO_PORT158, 1);
        } else {
-                gpio_direction_output(GPIO_PORT158, 0);
+                gpio_set_value(GPIO_PORT158, 0);
                clk_disable(mclk);
        }
@@ -806,21 +814,21 @@ static struct platform_device fsi_device = {
 };
 /* FSI-WM8978 */
-static struct asoc_simple_dai_init_info fsi_wm8978_init_info = {
-        .fmt            = SND_SOC_DAIFMT_I2S,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 12288000,
-};
 static struct asoc_simple_card_info fsi_wm8978_info = {
        .name           = "wm8978",
        .card           = "FSI2A-WM8978",
-        .cpu_dai        = "fsia-dai",
        .codec          = "wm8978.0-001a",
        .platform       = "sh_fsi2",
-        .codec_dai      = "wm8978-hifi",
+        .daifmt         = SND_SOC_DAIFMT_I2S,
-        .init           = &fsi_wm8978_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "wm8978-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
+                .sysclk = 12288000,
+        },
 };
 static struct platform_device fsi_wm8978_device = {
@@ -832,18 +840,18 @@ static struct platform_device fsi_wm8978_device = {
 };
 /* FSI-HDMI */
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+        },
+        .codec_dai = {
+                .name = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
@@ -992,16 +1000,12 @@ static void __init eva_init(void)
        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-        gpio_request(GPIO_PORT61, NULL); /* LCDDON */
+        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        gpio_direction_output(GPIO_PORT61, 1);
+        gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
-        gpio_request(GPIO_PORT202, NULL); /* LCD0_LED_CONT */
-        gpio_direction_output(GPIO_PORT202, 0);
        /* Touchscreen */
        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
-        gpio_request(GPIO_PORT166,      NULL); /* TP_RST_B */
+        gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
-        gpio_direction_output(GPIO_PORT166, 1);
        /* GETHER */
        gpio_request(GPIO_FN_ET_CRS,            NULL);
@@ -1024,12 +1028,10 @@ static void __init eva_init(void)
        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
-        gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+        gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
-        gpio_direction_output(GPIO_PORT18, 1);
        /* USB */
-        gpio_request(GPIO_PORT159, NULL); /* USB_DEVICE_MODE */
+        gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
-        gpio_direction_input(GPIO_PORT159);
        if (gpio_get_value(GPIO_PORT159)) {
                /* USB Host */
@@ -1043,8 +1045,7 @@ static void __init eva_init(void)
                 * and select GPIO_PORT209 here
                 */
                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
-                gpio_request(GPIO_PORT209, NULL);
+                gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
-                gpio_direction_input(GPIO_PORT209);
                platform_device_register(&usbhsf_device);
                usb = &usbhsf_device;
@@ -1059,12 +1060,9 @@ static void __init eva_init(void)
        gpio_request(GPIO_FN_SDHI0_D3, NULL);
        gpio_request(GPIO_FN_SDHI0_WP, NULL);
-        gpio_request(GPIO_PORT17, NULL);        /* SDHI0_18/33_B */
+        gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL);  /* SDHI0_18/33_B */
-        gpio_request(GPIO_PORT74, NULL);        /* SDHI0_PON */
+        gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
-        gpio_request(GPIO_PORT75, NULL);        /* SDSLOT1_PON */
+        gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
-        gpio_direction_output(GPIO_PORT17, 0);
-        gpio_direction_output(GPIO_PORT74, 1);
-        gpio_direction_output(GPIO_PORT75, 1);
        /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
@@ -1101,12 +1099,10 @@ static void __init eva_init(void)
        gpio_request(GPIO_FN_VIO_CKO,           NULL);
        /* CON1/CON15 Camera */
-        gpio_request(GPIO_PORT173, NULL); /* STANDBY */
+        gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
-        gpio_request(GPIO_PORT172, NULL); /* RST */
+        gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
-        gpio_request(GPIO_PORT158, NULL); /* CAM_PON */
+        /* see mt9t111_power() */
-        gpio_direction_output(GPIO_PORT173, 0);
+        gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
-        gpio_direction_output(GPIO_PORT172, 1);
-        gpio_direction_output(GPIO_PORT158, 0); /* see mt9t111_power() */
        /* FSI-WM8978 */
        gpio_request(GPIO_FN_FSIAIBT,           NULL);
@@ -1133,15 +1129,13 @@ static void __init eva_init(void)
         * DBGMD/LCDC0/FSIA MUX
         * DBGMD_SELECT_B should be set after setting PFC Function.
         */
-        gpio_request(GPIO_PORT176, NULL);
+        gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
-        gpio_direction_output(GPIO_PORT176, 1);
        /*
         * We can switch CON8/CON14 by SW1.5,
         * but it needs after DBGMD_SELECT_B
         */
-        gpio_request(GPIO_PORT6, NULL);
+        gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_PORT6);
        if (gpio_get_value(GPIO_PORT6)) {
                /* CON14 enable */
        } else {
@@ -1155,8 +1149,8 @@ static void __init eva_init(void)
                gpio_request(GPIO_FN_SDHI1_CD,  NULL);
                gpio_request(GPIO_FN_SDHI1_WP,  NULL);
-                gpio_request(GPIO_PORT16, NULL); /* SDSLOT2_PON */
+                /* SDSLOT2_PON */
-                gpio_direction_output(GPIO_PORT16, 1);
+                gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
                platform_device_register(&sdhi1_device);
        }
@@ -1175,26 +1169,26 @@ static void __init eva_init(void)
        platform_add_devices(eva_devices,
                             ARRAY_SIZE(eva_devices));
-        eva_clock_init();
        rmobile_add_device_to_domain("A4LC", &lcdc0_device);
        rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
        if (usb)
                rmobile_add_device_to_domain("A3SP", usb);
+        r8a7740_pm_init();
 }
 static void __init eva_earlytimer_init(void)
 {
        r8a7740_clock_init(MD_CK0 | MD_CK2);
        shmobile_earlytimer_init();
+        /* the rate of extal1 clock must be set before late_time_init */
+        eva_clock_init();
 }
 static void __init eva_add_early_devices(void)
 {
        r8a7740_add_early_devices();
-        /* override timer setup with board-specific code */
-        shmobile_timer.init = eva_earlytimer_init;
 }
 #define RESCNT2 IOMEM(0xe6188020)
@@ -1216,7 +1210,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = eva_init,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = eva_earlytimer_init,
        .dt_compat      = eva_boards_compat_dt,
        .restart        = eva_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index cb8c994e1430..e50f86691539 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -392,8 +392,7 @@ static void __init bonito_init(void)
        /*
         * base board settings
         */
-        gpio_request(GPIO_PORT176, NULL);
+        gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_PORT176);
        if (!gpio_get_value(GPIO_PORT176)) {
                u16 bsw2;
                u16 bsw3;
@@ -462,8 +461,8 @@ static void __init bonito_init(void)
                        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
                        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-                        gpio_request(GPIO_PORT61, NULL); /* LCDDON */
+                        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
-                        gpio_direction_output(GPIO_PORT61, 1);
+                                         NULL); /* LCDDON */
                        /* backlight on */
                        bonito_fpga_write(LCDCR, 1);
@@ -499,9 +498,6 @@ static void __init bonito_earlytimer_init(void)
 static void __init bonito_add_early_devices(void)
 {
        r8a7740_add_early_devices();
-        /* override timer setup with board-specific code */
-        shmobile_timer.init = bonito_earlytimer_init;
 }
 MACHINE_START(BONITO, "bonito")
@@ -511,5 +507,5 @@ MACHINE_START(BONITO, "bonito")
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = bonito_init,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = bonito_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index bf88f9a8b7ac..2ccc860403ef 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -35,6 +35,7 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/leds-renesas-tpu.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
@@ -47,7 +48,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
@@ -474,10 +474,8 @@ static void __init kota2_init(void)
        gpio_request(GPIO_FN_D15_NAF15, NULL);
        gpio_request(GPIO_FN_CS5A_, NULL);
        gpio_request(GPIO_FN_WE0__FWE, NULL);
-        gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
+        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_direction_input(GPIO_PORT144);
+        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-        gpio_request(GPIO_PORT145, NULL); /* RESET */
-        gpio_direction_output(GPIO_PORT145, 1);
        /* KEYSC */
        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
@@ -509,8 +507,7 @@ static void __init kota2_init(void)
        gpio_request(GPIO_FN_MMCD0_6, NULL);
        gpio_request(GPIO_FN_MMCD0_7, NULL);
        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request(GPIO_PORT208, NULL); /* Reset */
+        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
-        gpio_direction_output(GPIO_PORT208, 1);
        /* SDHI0 (microSD) */
        gpio_request(GPIO_FN_SDHICD0_PU, NULL);
@@ -550,8 +547,7 @@ MACHINE_START(KOTA2, "kota2")
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = kota2_init,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = sh73a0_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index b52bc0d1273f..c254782aa727 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -28,7 +28,6 @@
 #include <mach/emev2.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
@@ -89,9 +88,8 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
        .init_early     = emev2_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = emev2_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = kzm9d_add_standard_devices,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = shmobile_timer_init,
        .dt_compat      = kzm9d_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index c02448d6847f..7f3a6b7e7b7c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -25,6 +25,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/pcf857x.h>
 #include <linux/input.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
@@ -42,7 +43,6 @@
 #include <mach/sh73a0.h>
 #include <mach/common.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <video/sh_mobile_lcdc.h>
@@ -525,21 +525,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4648_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4648_info = {
        .name           = "AK4648",
        .card           = "FSI2A-AK4648",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0012",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4648_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4648_device = {
@@ -623,7 +623,7 @@ static int __init as3711_enable_lcdc_backlight(void)
                0x45, 0xf0,
        };
-        if (!machine_is_kzm9g())
+        if (!of_machine_is_compatible("renesas,kzm9g"))
                return 0;
        if (!a)
@@ -672,8 +672,7 @@ static void __init kzm_init(void)
        gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
        /* SMSC */
-        gpio_request(GPIO_PORT224, NULL); /* IRQ3 */
+        gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
-        gpio_direction_input(GPIO_PORT224);
        /* LCDC */
        gpio_request(GPIO_FN_LCDD23,    NULL);
@@ -703,14 +702,11 @@ static void __init kzm_init(void)
        gpio_request(GPIO_FN_LCDDISP,   NULL);
        gpio_request(GPIO_FN_LCDDCK,    NULL);
-        gpio_request(GPIO_PORT222,      NULL); /* LCDCDON */
+        gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
-        gpio_request(GPIO_PORT226,      NULL); /* SC */
+        gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
-        gpio_direction_output(GPIO_PORT222, 1);
-        gpio_direction_output(GPIO_PORT226, 1);
        /* Touchscreen */
-        gpio_request(GPIO_PORT223, NULL); /* IRQ8 */
+        gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
-        gpio_direction_input(GPIO_PORT223);
        /* enable MMCIF */
        gpio_request(GPIO_FN_MMCCLK0,           NULL);
@@ -734,8 +730,7 @@ static void __init kzm_init(void)
        gpio_request(GPIO_FN_SDHID0_1,          NULL);
        gpio_request(GPIO_FN_SDHID0_0,          NULL);
        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-        gpio_request(GPIO_PORT15, NULL);
+        gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-        gpio_direction_output(GPIO_PORT15, 1); /* power */
        /* enable Micro SD */
        gpio_request(GPIO_FN_SDHID2_0,          NULL);
@@ -744,8 +739,7 @@ static void __init kzm_init(void)
        gpio_request(GPIO_FN_SDHID2_3,          NULL);
        gpio_request(GPIO_FN_SDHICMD2,          NULL);
        gpio_request(GPIO_FN_SDHICLK2,          NULL);
-        gpio_request(GPIO_PORT14, NULL);
+        gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-        gpio_direction_output(GPIO_PORT14, 1); /* power */
        /* I2C 3 */
        gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
@@ -772,6 +766,8 @@ static void __init kzm_init(void)
        sh73a0_add_standard_devices();
        platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
+        sh73a0_pm_init();
 }
 static void kzm9g_restart(char mode, const char *cmd)
@@ -792,10 +788,9 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = kzm_init,
        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = sh73a0_earlytimer_init,
        .restart        = kzm9g_restart,
        .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 2fed62f66045..db968a585ff0 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -202,9 +202,7 @@
 *
 * it needs amixer settings for playing
 *
- * amixer set "Headphone" on
+ * amixer set "Headphone Enable" on
- * amixer set "HPOUTL Mixer DACH" on
- * amixer set "HPOUTR Mixer DACH" on
 */
 /* Fixed 3.3V and 1.8V regulators to be used by multiple devices */
@@ -502,18 +500,18 @@ static struct platform_device hdmi_lcdc_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
-};
 static struct asoc_simple_card_info fsi2_hdmi_info = {
        .name           = "HDMI",
        .card           = "FSI2B-HDMI",
-        .cpu_dai        = "fsib-dai",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
-        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .cpu_dai = {
-        .init           = &fsi2_hdmi_init_info,
+                .name   = "fsib-dai",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
+        },
+        .codec_dai = {
+                .name   = "sh_mobile_hdmi-hifi",
+        },
 };
 static struct platform_device fsi_hdmi_device = {
@@ -858,16 +856,12 @@ static struct platform_device leds_device = {
 #define IRQ_FSI evt2irq(0x1840)
 static struct sh_fsi_platform_info fsi_info = {
        .port_a = {
-                .flags = SH_FSI_BRS_INV,
                .tx_id = SHDMA_SLAVE_FSIA_TX,
                .rx_id = SHDMA_SLAVE_FSIA_RX,
        },
        .port_b = {
-                .flags = SH_FSI_BRS_INV |
+                .flags = SH_FSI_CLK_CPG |
-                        SH_FSI_BRM_INV  |
+                         SH_FSI_FMT_SPDIF,
-                        SH_FSI_LRS_INV  |
-                        SH_FSI_CLK_CPG  |
-                        SH_FSI_FMT_SPDIF,
        }
 };
@@ -896,21 +890,21 @@ static struct platform_device fsi_device = {
        },
 };
-static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
-        .fmt            = SND_SOC_DAIFMT_LEFT_J,
-        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
-        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
-        .sysclk         = 11289600,
-};
 static struct asoc_simple_card_info fsi2_ak4643_info = {
        .name           = "AK4643",
        .card           = "FSI2A-AK4643",
-        .cpu_dai        = "fsia-dai",
        .codec          = "ak4642-codec.0-0013",
        .platform       = "sh_fsi2",
-        .codec_dai      = "ak4642-hifi",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .init           = &fsi2_ak4643_init_info,
+        .cpu_dai = {
+                .name   = "fsia-dai",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
 };
 static struct platform_device fsi_ak4643_device = {
@@ -1408,11 +1402,10 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_LCDDISP,  NULL);
        gpio_request(GPIO_FN_LCDDCK,   NULL);
-        gpio_request(GPIO_PORT31, NULL); /* backlight */
+        /* backlight, off by default */
-        gpio_direction_output(GPIO_PORT31, 0); /* off by default */
+        gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
-        gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        gpio_direction_output(GPIO_PORT151, 1);
        /* USBHS0 */
        gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1428,8 +1421,7 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_FSIAILR,   NULL);
        gpio_request(GPIO_FN_FSIAISLD,  NULL);
        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request(GPIO_PORT161,      NULL);
+        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-        gpio_direction_output(GPIO_PORT161, 0); /* slave */
        gpio_request(GPIO_PORT9,  NULL);
        gpio_request(GPIO_PORT10, NULL);
@@ -1483,8 +1475,7 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_SDHID1_0, NULL);
 #endif
        /* card detect pin for MMC slot (CN7) */
-        gpio_request(GPIO_PORT41, NULL);
+        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_PORT41);
        /* enable SDHI2 */
        gpio_request(GPIO_FN_SDHICMD2, NULL);
@@ -1495,8 +1486,7 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_SDHID2_0, NULL);
        /* card detect pin for microSD slot (CN23) */
-        gpio_request(GPIO_PORT162, NULL);
+        gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
-        gpio_direction_input(GPIO_PORT162);
        /* MMCIF */
        gpio_request(GPIO_FN_MMCD0_0, NULL);
@@ -1593,6 +1583,6 @@ DT_MACHINE_START(MACKEREL_DT, "mackerel")
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = mackerel_init,
        .init_late      = sh7372_pm_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = sh7372_earlytimer_init,
        .dt_compat  = mackerel_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 449f9289567d..cdcb799e802f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -44,7 +44,6 @@
 #include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <asm/traps.h>
 /* Fixed 3.3V regulator to be used by SDHI0 */
@@ -382,8 +381,7 @@ MACHINE_START(MARZEN, "marzen")
        .init_early     = r8a7779_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = r8a7779_init_irq,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = marzen_init,
        .init_late      = marzen_init_late,
-        .timer          = &shmobile_timer,
+        .init_time      = r8a7779_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index eac49d59782f..19ce885a3b43 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -581,10 +581,14 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0",    &mstp_clks[MSTP100]),
-        CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP111]),
+        CLKDEV_DEV_ID("sh_tmu.3",               &mstp_clks[MSTP111]),
+        CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
+        CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
        CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
        CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
+        CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
+        CLKDEV_DEV_ID("sh_tmu.2",               &mstp_clks[MSTP125]),
        CLKDEV_DEV_ID("sh_mobile_ceu.0",        &mstp_clks[MSTP127]),
        CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index c019609da660..1db36537255c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -162,6 +162,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
+        CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 3ca6757b129a..45d21fe317f4 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -544,6 +544,7 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+        CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
        CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
@@ -556,6 +557,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+        CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
        CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
@@ -577,18 +579,25 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+        CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
        CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+        CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
        CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
+        CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
        CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
+        CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+        CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
        CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 516ff7f3e434..afa5423a0f93 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -264,17 +264,17 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
        SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
 static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
-        [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
+        [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
-        [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
+        [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-        [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
+        [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
-        [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
+        [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
-        [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
+        [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
-        [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
+        [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
-        [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+        [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
 };
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
@@ -525,6 +525,13 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
 };
+/* The lookups structure below includes duplicate entries for some clocks
+ * with alternate names.
+ * - The traditional name used when a device is initialised with platform data
+ * - The name used when a device is initialised using device tree
+ * The longer-term aim is to remove these duplicates, and indeed the
+ * lookups table entirely, by describing clocks using device tree.
+ */
 static struct clk_lookup lookups[] = {
        /* main clocks */
        CLKDEV_CON_ID("r_clk", &r_clk),
@@ -545,6 +552,7 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+        CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */
        CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
        CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
@@ -553,6 +561,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
@@ -569,17 +578,21 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
        CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
        CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
        CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
        CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
        CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
+        CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */
        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
+        CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 };
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-sh73a0.S
new file mode 100644
index 000000000000..bec4c0d9b713
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp-sh73a0.S
@@ -0,0 +1,50 @@
+/*
+ * SMP support for SoC sh73a0
+ *
+ * Copyright (C) 2012 Bastian Hecht
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+        __CPUINIT
+/*
+ * Reset vector for secondary CPUs.
+ *
+ * First we turn on L1 cache coherency for our CPU. Then we jump to
+ * shmobile_invalidate_start that invalidates the cache and hands over control
+ * to the common ARM startup code.
+ * This function will be mapped to address 0 by the SBAR register.
+ * A normal branch is out of range here so we need a long jump. We jump to
+ * the physical address as the MMU is still turned off.
+ */
+        .align  12
+ENTRY(sh73a0_secondary_vector)
+        mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
+        and     r0, r0, #3              @ mask out cpu ID
+        lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
+        mov     r1, #0xf0000000         @ SCU base address
+        ldr     r2, [r1, #8]            @ SCU Power Status Register
+        mov     r3, #3
+        bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
+        str     r2, [r1, #8]            @ write back
+        ldr     pc, 1f
+1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(sh73a0_secondary_vector)
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index b202c1272526..96001fd49b6c 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,54 +16,6 @@
        __CPUINIT
-/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
- *
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3      @ NumWays - 1
-        add     r2, r2, #1              @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4      @ SetShift
-        clz     r1, r3          @ WayShift
-        add     r4, r3, #1      @ NumWays
-1:      sub     r2, r2, #1      @ NumSets--
-        mov     r3, r4          @ Temp = NumWays
-2:      subs    r3, r3, #1      @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 ENTRY(shmobile_invalidate_start)
        bl      v7_invalidate_l1
        b       secondary_startup
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index b09a0bdbf813..a1524e3367b0 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -56,6 +56,12 @@ int shmobile_cpu_disable(unsigned int cpu)
        return cpu == 0 ? -EPERM : 0;
 }
+int shmobile_cpu_disable_any(unsigned int cpu)
+{
+        cpumask_clear_cpu(cpu, &dead_cpus);
+        return 0;
+}
 int shmobile_cpu_is_dead(unsigned int cpu)
 {
        return cpumask_test_cpu(cpu, &dead_cpus);
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index dfeca79e9e96..e48606d8a2be 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -2,7 +2,7 @@
 #define __ARCH_MACH_COMMON_H
 extern void shmobile_earlytimer_init(void);
-extern struct sys_timer shmobile_timer;
+extern void shmobile_timer_init(void);
 extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                         unsigned int mult, unsigned int div);
 struct twd_local_timer;
@@ -20,8 +20,11 @@ extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 extern void sh7372_init_irq(void);
 extern void sh7372_map_io(void);
+extern void sh7372_earlytimer_init(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
+extern void sh7372_add_early_devices_dt(void);
+extern void sh7372_add_standard_devices_dt(void);
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
 extern void sh7372_pm_init(void);
@@ -31,11 +34,17 @@ extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 extern void sh73a0_init_irq(void);
+extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
+extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
+extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
+extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
+extern void sh73a0_pm_init(void);
+extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
@@ -47,9 +56,11 @@ extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
+extern void r8a7740_pm_init(void);
 extern void r8a7779_init_irq(void);
 extern void r8a7779_map_io(void);
+extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_clock_init(void);
@@ -73,6 +84,7 @@ static inline int shmobile_cpuidle_init(void) { return 0; }
 extern void shmobile_cpu_die(unsigned int cpu);
 extern int shmobile_cpu_disable(unsigned int cpu);
+extern int shmobile_cpu_disable_any(unsigned int cpu);
 #ifdef CONFIG_HOTPLUG_CPU
 extern int shmobile_cpu_is_dead(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h
index 0bd7556b1387..f1aee56781e7 100644
--- a/arch/arm/mach-shmobile/include/mach/uncompress.h
+++ b/arch/arm/mach-shmobile/include/mach/uncompress.h
@@ -16,6 +16,4 @@ static void arch_decomp_setup(void)
 {
 }
-#define arch_decomp_wdog()
 #endif /* __ASM_MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index ef66f1a8aa2e..8807c27f71f9 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -22,10 +22,10 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/intc.h>
 #include <mach/r8a7779.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index f0c5e5190601..91faba666d46 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -23,10 +23,11 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/sh_intc.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/intc.h>
 #include <mach/irqs.h>
 #include <mach/sh73a0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -315,11 +316,6 @@ static int intca_gic_set_type(struct irq_data *data, unsigned int type)
        return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
 }
-static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
-{
-        return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
-}
 #ifdef CONFIG_SMP
 static int intca_gic_set_affinity(struct irq_data *data,
                                  const struct cpumask *cpumask,
@@ -339,7 +335,7 @@ struct irq_chip intca_gic_irq_chip = {
        .irq_disable            = intca_gic_disable,
        .irq_shutdown           = intca_gic_disable,
        .irq_set_type           = intca_gic_set_type,
-        .irq_set_wake           = intca_gic_set_wake,
+        .irq_set_wake           = sh73a0_set_wake,
 #ifdef CONFIG_SMP
        .irq_set_affinity       = intca_gic_set_affinity,
 #endif
@@ -464,3 +460,11 @@ void __init sh73a0_init_irq(void)
        sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
        setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
+#ifdef CONFIG_OF
+void __init sh73a0_init_irq_dt(void)
+{
+        irqchip_init();
+        gic_arch_extn.irq_set_wake = sh73a0_set_wake;
+}
+#endif
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
deleted file mode 100644
index 134d1b9a8821..000000000000
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ /dev/null
@@ -1,2617 +0,0 @@
-/*
- * R8A7740 processor support
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/r8a7740.h>
-#include <mach/irqs.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                                      \
-        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx),          \
-        PORT_10(fn, pfx##10, sfx),      PORT_90(fn, pfx##1, sfx),       \
-        PORT_10(fn, pfx##20, sfx),                                      \
-        PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        /* PORT0_DATA -> PORT211_DATA */
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),
-        PINMUX_DATA_END,
-        /* PORT0_IN -> PORT211_IN */
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),
-        PINMUX_INPUT_END,
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-        /* PORT0_OUT -> PORT211_OUT */
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),        /* PORT0_FN_IN -> PORT211_FN_IN */
-        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT211_FN_OUT */
-        PORT_ALL(FN0),          /* PORT0_FN0 -> PORT211_FN0 */
-        PORT_ALL(FN1),          /* PORT0_FN1 -> PORT211_FN1 */
-        PORT_ALL(FN2),          /* PORT0_FN2 -> PORT211_FN2 */
-        PORT_ALL(FN3),          /* PORT0_FN3 -> PORT211_FN3 */
-        PORT_ALL(FN4),          /* PORT0_FN4 -> PORT211_FN4 */
-        PORT_ALL(FN5),          /* PORT0_FN5 -> PORT211_FN5 */
-        PORT_ALL(FN6),          /* PORT0_FN6 -> PORT211_FN6 */
-        PORT_ALL(FN7),          /* PORT0_FN7 -> PORT211_FN7 */
-        MSEL1CR_31_0,   MSEL1CR_31_1,
-        MSEL1CR_30_0,   MSEL1CR_30_1,
-        MSEL1CR_29_0,   MSEL1CR_29_1,
-        MSEL1CR_28_0,   MSEL1CR_28_1,
-        MSEL1CR_27_0,   MSEL1CR_27_1,
-        MSEL1CR_26_0,   MSEL1CR_26_1,
-        MSEL1CR_16_0,   MSEL1CR_16_1,
-        MSEL1CR_15_0,   MSEL1CR_15_1,
-        MSEL1CR_14_0,   MSEL1CR_14_1,
-        MSEL1CR_13_0,   MSEL1CR_13_1,
-        MSEL1CR_12_0,   MSEL1CR_12_1,
-        MSEL1CR_9_0,    MSEL1CR_9_1,
-        MSEL1CR_7_0,    MSEL1CR_7_1,
-        MSEL1CR_6_0,    MSEL1CR_6_1,
-        MSEL1CR_5_0,    MSEL1CR_5_1,
-        MSEL1CR_4_0,    MSEL1CR_4_1,
-        MSEL1CR_3_0,    MSEL1CR_3_1,
-        MSEL1CR_2_0,    MSEL1CR_2_1,
-        MSEL1CR_0_0,    MSEL1CR_0_1,
-        MSEL3CR_15_0,   MSEL3CR_15_1, /* Trace / Debug ? */
-        MSEL3CR_6_0,    MSEL3CR_6_1,
-        MSEL4CR_19_0,   MSEL4CR_19_1,
-        MSEL4CR_18_0,   MSEL4CR_18_1,
-        MSEL4CR_15_0,   MSEL4CR_15_1,
-        MSEL4CR_10_0,   MSEL4CR_10_1,
-        MSEL4CR_6_0,    MSEL4CR_6_1,
-        MSEL4CR_4_0,    MSEL4CR_4_1,
-        MSEL4CR_1_0,    MSEL4CR_1_1,
-        MSEL5CR_31_0,   MSEL5CR_31_1, /* irq/fiq output */
-        MSEL5CR_30_0,   MSEL5CR_30_1,
-        MSEL5CR_29_0,   MSEL5CR_29_1,
-        MSEL5CR_27_0,   MSEL5CR_27_1,
-        MSEL5CR_25_0,   MSEL5CR_25_1,
-        MSEL5CR_23_0,   MSEL5CR_23_1,
-        MSEL5CR_21_0,   MSEL5CR_21_1,
-        MSEL5CR_19_0,   MSEL5CR_19_1,
-        MSEL5CR_17_0,   MSEL5CR_17_1,
-        MSEL5CR_15_0,   MSEL5CR_15_1,
-        MSEL5CR_14_0,   MSEL5CR_14_1,
-        MSEL5CR_13_0,   MSEL5CR_13_1,
-        MSEL5CR_12_0,   MSEL5CR_12_1,
-        MSEL5CR_11_0,   MSEL5CR_11_1,
-        MSEL5CR_10_0,   MSEL5CR_10_1,
-        MSEL5CR_8_0,    MSEL5CR_8_1,
-        MSEL5CR_7_0,    MSEL5CR_7_1,
-        MSEL5CR_6_0,    MSEL5CR_6_1,
-        MSEL5CR_5_0,    MSEL5CR_5_1,
-        MSEL5CR_4_0,    MSEL5CR_4_1,
-        MSEL5CR_3_0,    MSEL5CR_3_1,
-        MSEL5CR_2_0,    MSEL5CR_2_1,
-        MSEL5CR_0_0,    MSEL5CR_0_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* IRQ */
-        IRQ0_PORT2_MARK,        IRQ0_PORT13_MARK,
-        IRQ1_MARK,
-        IRQ2_PORT11_MARK,       IRQ2_PORT12_MARK,
-        IRQ3_PORT10_MARK,       IRQ3_PORT14_MARK,
-        IRQ4_PORT15_MARK,       IRQ4_PORT172_MARK,
-        IRQ5_PORT0_MARK,        IRQ5_PORT1_MARK,
-        IRQ6_PORT121_MARK,      IRQ6_PORT173_MARK,
-        IRQ7_PORT120_MARK,      IRQ7_PORT209_MARK,
-        IRQ8_MARK,
-        IRQ9_PORT118_MARK,      IRQ9_PORT210_MARK,
-        IRQ10_MARK,
-        IRQ11_MARK,
-        IRQ12_PORT42_MARK,      IRQ12_PORT97_MARK,
-        IRQ13_PORT64_MARK,      IRQ13_PORT98_MARK,
-        IRQ14_PORT63_MARK,      IRQ14_PORT99_MARK,
-        IRQ15_PORT62_MARK,      IRQ15_PORT100_MARK,
-        IRQ16_PORT68_MARK,      IRQ16_PORT211_MARK,
-        IRQ17_MARK,
-        IRQ18_MARK,
-        IRQ19_MARK,
-        IRQ20_MARK,
-        IRQ21_MARK,
-        IRQ22_MARK,
-        IRQ23_MARK,
-        IRQ24_MARK,
-        IRQ25_MARK,
-        IRQ26_PORT58_MARK,      IRQ26_PORT81_MARK,
-        IRQ27_PORT57_MARK,      IRQ27_PORT168_MARK,
-        IRQ28_PORT56_MARK,      IRQ28_PORT169_MARK,
-        IRQ29_PORT50_MARK,      IRQ29_PORT170_MARK,
-        IRQ30_PORT49_MARK,      IRQ30_PORT171_MARK,
-        IRQ31_PORT41_MARK,      IRQ31_PORT167_MARK,
-        /* Function */
-        /* DBGT */
-        DBGMDT2_MARK,   DBGMDT1_MARK,   DBGMDT0_MARK,
-        DBGMD10_MARK,   DBGMD11_MARK,   DBGMD20_MARK,
-        DBGMD21_MARK,
-        /* FSI-A */
-        FSIAISLD_PORT0_MARK,    /* FSIAISLD Port 0/5 */
-        FSIAISLD_PORT5_MARK,
-        FSIASPDIF_PORT9_MARK,   /* FSIASPDIF Port 9/18 */
-        FSIASPDIF_PORT18_MARK,
-        FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
-        FSIAOBT_MARK,   FSIAOSLD_MARK,  FSIAOMC_MARK,
-        FSIACK_MARK,    FSIAILR_MARK,   FSIAIBT_MARK,
-        /* FSI-B */
-        FSIBCK_MARK,
-        /* FMSI */
-        FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
-        FMSISLD_PORT6_MARK,
-        FMSIILR_MARK,   FMSIIBT_MARK,   FMSIOLR_MARK,   FMSIOBT_MARK,
-        FMSICK_MARK,    FMSOILR_MARK,   FMSOIBT_MARK,   FMSOOLR_MARK,
-        FMSOOBT_MARK,   FMSOSLD_MARK,   FMSOCK_MARK,
-        /* SCIFA0 */
-        SCIFA0_SCK_MARK,        SCIFA0_CTS_MARK,        SCIFA0_RTS_MARK,
-        SCIFA0_RXD_MARK,        SCIFA0_TXD_MARK,
-        /* SCIFA1 */
-        SCIFA1_CTS_MARK,        SCIFA1_SCK_MARK,        SCIFA1_RXD_MARK,
-        SCIFA1_TXD_MARK,        SCIFA1_RTS_MARK,
-        /* SCIFA2 */
-        SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
-        SCIFA2_SCK_PORT199_MARK,
-        SCIFA2_RXD_MARK,        SCIFA2_TXD_MARK,
-        SCIFA2_CTS_MARK,        SCIFA2_RTS_MARK,
-        /* SCIFA3 */
-        SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
-        SCIFA3_SCK_PORT116_MARK,
-        SCIFA3_CTS_PORT117_MARK,
-        SCIFA3_RXD_PORT174_MARK,
-        SCIFA3_TXD_PORT175_MARK,
-        SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
-        SCIFA3_SCK_PORT158_MARK,
-        SCIFA3_CTS_PORT162_MARK,
-        SCIFA3_RXD_PORT159_MARK,
-        SCIFA3_TXD_PORT160_MARK,
-        /* SCIFA4 */
-        SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
-        SCIFA4_TXD_PORT13_MARK,
-        SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
-        SCIFA4_TXD_PORT203_MARK,
-        SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
-        SCIFA4_TXD_PORT93_MARK,
-        SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
-        SCIFA4_SCK_PORT205_MARK,
-        /* SCIFA5 */
-        SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
-        SCIFA5_RXD_PORT10_MARK,
-        SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
-        SCIFA5_TXD_PORT208_MARK,
-        SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
-        SCIFA5_RXD_PORT92_MARK,
-        SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
-        SCIFA5_SCK_PORT206_MARK,
-        /* SCIFA6 */
-        SCIFA6_SCK_MARK,        SCIFA6_RXD_MARK,        SCIFA6_TXD_MARK,
-        /* SCIFA7 */
-        SCIFA7_TXD_MARK,        SCIFA7_RXD_MARK,
-        /* SCIFAB */
-        SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
-        SCIFB_RXD_PORT191_MARK,
-        SCIFB_TXD_PORT192_MARK,
-        SCIFB_RTS_PORT186_MARK,
-        SCIFB_CTS_PORT187_MARK,
-        SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
-        SCIFB_RXD_PORT3_MARK,
-        SCIFB_TXD_PORT4_MARK,
-        SCIFB_RTS_PORT172_MARK,
-        SCIFB_CTS_PORT173_MARK,
-        /* LCD0 */
-        LCDC0_SELECT_MARK,
-        LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
-        LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
-        LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
-        LCD0_D12_MARK,  LCD0_D13_MARK,  LCD0_D14_MARK,  LCD0_D15_MARK,
-        LCD0_D16_MARK,  LCD0_D17_MARK,
-        LCD0_DON_MARK,  LCD0_VCPWC_MARK,        LCD0_VEPWC_MARK,
-        LCD0_DCK_MARK,  LCD0_VSYN_MARK, /* for RGB */
-        LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
-        LCD0_WR_MARK,   LCD0_RD_MARK,   /* for SYS */
-        LCD0_CS_MARK,   LCD0_RS_MARK,   /* for SYS */
-        LCD0_D21_PORT158_MARK,  LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
-        LCD0_D22_PORT160_MARK,  LCD0_D20_PORT161_MARK,
-        LCD0_D19_PORT162_MARK,  LCD0_D18_PORT163_MARK,
-        LCD0_LCLK_PORT165_MARK,
-        LCD0_D18_PORT40_MARK,   LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
-        LCD0_D23_PORT1_MARK,    LCD0_D21_PORT2_MARK,
-        LCD0_D20_PORT3_MARK,    LCD0_D19_PORT4_MARK,
-        LCD0_LCLK_PORT102_MARK,
-        /* LCD1 */
-        LCDC1_SELECT_MARK,
-        LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
-        LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
-        LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
-        LCD1_D12_MARK,  LCD1_D13_MARK,  LCD1_D14_MARK,  LCD1_D15_MARK,
-        LCD1_D16_MARK,  LCD1_D17_MARK,  LCD1_D18_MARK,  LCD1_D19_MARK,
-        LCD1_D20_MARK,  LCD1_D21_MARK,  LCD1_D22_MARK,  LCD1_D23_MARK,
-        LCD1_DON_MARK,  LCD1_VCPWC_MARK,
-        LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
-        LCD1_DCK_MARK,  LCD1_VSYN_MARK, /* for RGB */
-        LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
-        LCD1_RS_MARK,   LCD1_CS_MARK,   /* for SYS */
-        LCD1_RD_MARK,   LCD1_WR_MARK,   /* for SYS */
-        /* RSPI */
-        RSPI_SSL0_A_MARK,       RSPI_SSL1_A_MARK,       RSPI_SSL2_A_MARK,
-        RSPI_SSL3_A_MARK,       RSPI_CK_A_MARK,         RSPI_MOSI_A_MARK,
-        RSPI_MISO_A_MARK,
-        /* VIO CKO */
-        VIO_CKO1_MARK, /* needs fixup */
-        VIO_CKO2_MARK,
-        VIO_CKO_1_MARK,
-        VIO_CKO_MARK,
-        /* VIO0 */
-        VIO0_D0_MARK,   VIO0_D1_MARK,   VIO0_D2_MARK,   VIO0_D3_MARK,
-        VIO0_D4_MARK,   VIO0_D5_MARK,   VIO0_D6_MARK,   VIO0_D7_MARK,
-        VIO0_D8_MARK,   VIO0_D9_MARK,   VIO0_D10_MARK,  VIO0_D11_MARK,
-        VIO0_D12_MARK,  VIO0_VD_MARK,   VIO0_HD_MARK,   VIO0_CLK_MARK,
-        VIO0_FIELD_MARK,
-        VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
-        VIO0_D14_PORT25_MARK,
-        VIO0_D15_PORT24_MARK,
-        VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
-        VIO0_D14_PORT95_MARK,
-        VIO0_D15_PORT96_MARK,
-        /* VIO1 */
-        VIO1_D0_MARK,   VIO1_D1_MARK,   VIO1_D2_MARK,   VIO1_D3_MARK,
-        VIO1_D4_MARK,   VIO1_D5_MARK,   VIO1_D6_MARK,   VIO1_D7_MARK,
-        VIO1_VD_MARK,   VIO1_HD_MARK,   VIO1_CLK_MARK,  VIO1_FIELD_MARK,
-        /* TPU0 */
-        TPU0TO0_MARK,   TPU0TO1_MARK,   TPU0TO3_MARK,
-        TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
-        TPU0TO2_PORT202_MARK,
-        /* SSP1 0 */
-        STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
-        STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
-        STP0_IPEN_MARK, STP0_IPCLK_MARK,        STP0_IPSYNC_MARK,
-        /* SSP1 1 */
-        STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
-        STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
-        STP1_IPSYNC_MARK,
-        STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
-        STP1_IPEN_PORT187_MARK,
-        STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
-        STP1_IPEN_PORT193_MARK,
-        /* SIM */
-        SIM_RST_MARK,   SIM_CLK_MARK,
-        SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
-        SIM_D_PORT199_MARK,
-        /* SDHI0 */
-        SDHI0_D0_MARK,  SDHI0_D1_MARK,  SDHI0_D2_MARK,  SDHI0_D3_MARK,
-        SDHI0_CD_MARK,  SDHI0_WP_MARK,  SDHI0_CMD_MARK, SDHI0_CLK_MARK,
-        /* SDHI1 */
-        SDHI1_D0_MARK,  SDHI1_D1_MARK,  SDHI1_D2_MARK,  SDHI1_D3_MARK,
-        SDHI1_CD_MARK,  SDHI1_WP_MARK,  SDHI1_CMD_MARK, SDHI1_CLK_MARK,
-        /* SDHI2 */
-        SDHI2_D0_MARK,  SDHI2_D1_MARK,  SDHI2_D2_MARK,  SDHI2_D3_MARK,
-        SDHI2_CLK_MARK, SDHI2_CMD_MARK,
-        SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
-        SDHI2_WP_PORT25_MARK,
-        SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
-        SDHI2_CD_PORT202_MARK,
-        /* MSIOF2 */
-        MSIOF2_TXD_MARK,        MSIOF2_RXD_MARK,        MSIOF2_TSCK_MARK,
-        MSIOF2_SS2_MARK,        MSIOF2_TSYNC_MARK,      MSIOF2_SS1_MARK,
-        MSIOF2_MCK1_MARK,       MSIOF2_MCK0_MARK,       MSIOF2_RSYNC_MARK,
-        MSIOF2_RSCK_MARK,
-        /* KEYSC */
-        KEYIN4_MARK,    KEYIN5_MARK,    KEYIN6_MARK,    KEYIN7_MARK,
-        KEYOUT0_MARK,   KEYOUT1_MARK,   KEYOUT2_MARK,   KEYOUT3_MARK,
-        KEYOUT4_MARK,   KEYOUT5_MARK,   KEYOUT6_MARK,   KEYOUT7_MARK,
-        KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
-        KEYIN1_PORT44_MARK,
-        KEYIN2_PORT45_MARK,
-        KEYIN3_PORT46_MARK,
-        KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
-        KEYIN1_PORT57_MARK,
-        KEYIN2_PORT56_MARK,
-        KEYIN3_PORT55_MARK,
-        /* VOU */
-        DV_D0_MARK,     DV_D1_MARK,     DV_D2_MARK,     DV_D3_MARK,
-        DV_D4_MARK,     DV_D5_MARK,     DV_D6_MARK,     DV_D7_MARK,
-        DV_D8_MARK,     DV_D9_MARK,     DV_D10_MARK,    DV_D11_MARK,
-        DV_D12_MARK,    DV_D13_MARK,    DV_D14_MARK,    DV_D15_MARK,
-        DV_CLK_MARK,    DV_VSYNC_MARK,  DV_HSYNC_MARK,
-        /* MEMC */
-        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,  MEMC_AD3_MARK,
-        MEMC_AD4_MARK,  MEMC_AD5_MARK,  MEMC_AD6_MARK,  MEMC_AD7_MARK,
-        MEMC_AD8_MARK,  MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
-        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
-        MEMC_CS0_MARK,  MEMC_INT_MARK,  MEMC_NWE_MARK,  MEMC_NOE_MARK,
-        MEMC_CS1_MARK, /* MSEL4CR_6_0 */
-        MEMC_ADV_MARK,
-        MEMC_WAIT_MARK,
-        MEMC_BUSCLK_MARK,
-        MEMC_A1_MARK, /* MSEL4CR_6_1 */
-        MEMC_DREQ0_MARK,
-        MEMC_DREQ1_MARK,
-        MEMC_A0_MARK,
-        /* MMC */
-        MMC0_D0_PORT68_MARK,    MMC0_D1_PORT69_MARK,    MMC0_D2_PORT70_MARK,
-        MMC0_D3_PORT71_MARK,    MMC0_D4_PORT72_MARK,    MMC0_D5_PORT73_MARK,
-        MMC0_D6_PORT74_MARK,    MMC0_D7_PORT75_MARK,    MMC0_CLK_PORT66_MARK,
-        MMC0_CMD_PORT67_MARK,   /* MSEL4CR_15_0 */
-        MMC1_D0_PORT149_MARK,   MMC1_D1_PORT148_MARK,   MMC1_D2_PORT147_MARK,
-        MMC1_D3_PORT146_MARK,   MMC1_D4_PORT145_MARK,   MMC1_D5_PORT144_MARK,
-        MMC1_D6_PORT143_MARK,   MMC1_D7_PORT142_MARK,   MMC1_CLK_PORT103_MARK,
-        MMC1_CMD_PORT104_MARK,  /* MSEL4CR_15_1 */
-        /* MSIOF0 */
-        MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,        MSIOF0_RXD_MARK,
-        MSIOF0_TXD_MARK,        MSIOF0_MCK0_MARK,       MSIOF0_MCK1_MARK,
-        MSIOF0_RSYNC_MARK,      MSIOF0_RSCK_MARK,       MSIOF0_TSCK_MARK,
-        MSIOF0_TSYNC_MARK,
-        /* MSIOF1 */
-        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
-        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
-        MSIOF1_SS2_PORT116_MARK,        MSIOF1_SS1_PORT117_MARK,
-        MSIOF1_RXD_PORT118_MARK,        MSIOF1_TXD_PORT119_MARK,
-        MSIOF1_TSYNC_PORT120_MARK,
-        MSIOF1_TSCK_PORT121_MARK,       /* MSEL4CR_10_0 */
-        MSIOF1_SS1_PORT67_MARK,         MSIOF1_TSCK_PORT72_MARK,
-        MSIOF1_TSYNC_PORT73_MARK,       MSIOF1_TXD_PORT74_MARK,
-        MSIOF1_RXD_PORT75_MARK,
-        MSIOF1_SS2_PORT202_MARK,        /* MSEL4CR_10_1 */
-        /* GPIO */
-        GPO0_MARK,      GPI0_MARK,      GPO1_MARK,      GPI1_MARK,
-        /* USB0 */
-        USB0_OCI_MARK,  USB0_PPON_MARK, VBUS_MARK,
-        /* USB1 */
-        USB1_OCI_MARK,  USB1_PPON_MARK,
-        /* BBIF1 */
-        BBIF1_RXD_MARK,         BBIF1_TXD_MARK,         BBIF1_TSYNC_MARK,
-        BBIF1_TSCK_MARK,        BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
-        BBIF1_FLOW_MARK,        BBIF1_RX_FLOW_N_MARK,
-        /* BBIF2 */
-        BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
-        BBIF2_RXD2_PORT60_MARK,
-        BBIF2_TSYNC2_PORT6_MARK,
-        BBIF2_TSCK2_PORT59_MARK,
-        BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
-        BBIF2_TXD2_PORT183_MARK,
-        BBIF2_TSCK2_PORT89_MARK,
-        BBIF2_TSYNC2_PORT184_MARK,
-        /* BSC / FLCTL / PCMCIA */
-        CS0_MARK,       CS2_MARK,       CS4_MARK,
-        CS5B_MARK,      CS6A_MARK,
-        CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
-        CS5A_PORT19_MARK,
-        IOIS16_MARK, /* ? */
-        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
-        A4_FOE_MARK,    /* share with FLCTL */
-        A5_FCDE_MARK,   /* share with FLCTL */
-        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
-        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
-        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
-        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
-        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
-        A26_MARK,
-        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   /* share with FLCTL */
-        D3_NAF3_MARK,   D4_NAF4_MARK,   D5_NAF5_MARK,   /* share with FLCTL */
-        D6_NAF6_MARK,   D7_NAF7_MARK,   D8_NAF8_MARK,   /* share with FLCTL */
-        D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
-        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
-        D15_NAF15_MARK,                                 /* share with FLCTL */
-        D16_MARK,       D17_MARK,       D18_MARK,       D19_MARK,
-        D20_MARK,       D21_MARK,       D22_MARK,       D23_MARK,
-        D24_MARK,       D25_MARK,       D26_MARK,       D27_MARK,
-        D28_MARK,       D29_MARK,       D30_MARK,       D31_MARK,
-        WE0_FWE_MARK,   /* share with FLCTL */
-        WE1_MARK,
-        WE2_ICIORD_MARK,        /* share with PCMCIA */
-        WE3_ICIOWR_MARK,        /* share with PCMCIA */
-        CKO_MARK,       BS_MARK,        RDWR_MARK,
-        RD_FSC_MARK,    /* share with FLCTL */
-        WAIT_PORT177_MARK, /* WAIT Port 90/177 */
-        WAIT_PORT90_MARK,
-        FCE0_MARK,      FCE1_MARK,      FRB_MARK, /* FLCTL */
-        /* IRDA */
-        IRDA_FIRSEL_MARK,       IRDA_IN_MARK,   IRDA_OUT_MARK,
-        /* ATAPI */
-        IDE_D0_MARK,    IDE_D1_MARK,    IDE_D2_MARK,    IDE_D3_MARK,
-        IDE_D4_MARK,    IDE_D5_MARK,    IDE_D6_MARK,    IDE_D7_MARK,
-        IDE_D8_MARK,    IDE_D9_MARK,    IDE_D10_MARK,   IDE_D11_MARK,
-        IDE_D12_MARK,   IDE_D13_MARK,   IDE_D14_MARK,   IDE_D15_MARK,
-        IDE_A0_MARK,    IDE_A1_MARK,    IDE_A2_MARK,    IDE_CS0_MARK,
-        IDE_CS1_MARK,   IDE_IOWR_MARK,  IDE_IORD_MARK,  IDE_IORDY_MARK,
-        IDE_INT_MARK,           IDE_RST_MARK,           IDE_DIRECTION_MARK,
-        IDE_EXBUF_ENB_MARK,     IDE_IODACK_MARK,        IDE_IODREQ_MARK,
-        /* RMII */
-        RMII_CRS_DV_MARK,       RMII_RX_ER_MARK,        RMII_RXD0_MARK,
-        RMII_RXD1_MARK,         RMII_TX_EN_MARK,        RMII_TXD0_MARK,
-        RMII_MDC_MARK,          RMII_TXD1_MARK,         RMII_MDIO_MARK,
-        RMII_REF50CK_MARK,      /* for RMII */
-        RMII_REF125CK_MARK,     /* for GMII */
-        /* GEther */
-        ET_TX_CLK_MARK, ET_TX_EN_MARK,  ET_ETXD0_MARK,  ET_ETXD1_MARK,
-        ET_ETXD2_MARK,  ET_ETXD3_MARK,
-        ET_ETXD4_MARK,  ET_ETXD5_MARK, /* for GEther */
-        ET_ETXD6_MARK,  ET_ETXD7_MARK, /* for GEther */
-        ET_COL_MARK,    ET_TX_ER_MARK,  ET_RX_CLK_MARK, ET_RX_DV_MARK,
-        ET_ERXD0_MARK,  ET_ERXD1_MARK,  ET_ERXD2_MARK,  ET_ERXD3_MARK,
-        ET_ERXD4_MARK,  ET_ERXD5_MARK, /* for GEther */
-        ET_ERXD6_MARK,  ET_ERXD7_MARK, /* for GEther */
-        ET_RX_ER_MARK,  ET_CRS_MARK,            ET_MDC_MARK,    ET_MDIO_MARK,
-        ET_LINK_MARK,   ET_PHY_INT_MARK,        ET_WOL_MARK,    ET_GTX_CLK_MARK,
-        /* DMA0 */
-        DREQ0_MARK,     DACK0_MARK,
-        /* DMA1 */
-        DREQ1_MARK,     DACK1_MARK,
-        /* SYSC */
-        RESETOUTS_MARK,         RESETP_PULLUP_MARK,     RESETP_PLAIN_MARK,
-        /* IRREM */
-        IROUT_MARK,
-        /* SDENC */
-        SDENC_CPG_MARK,         SDENC_DV_CLKI_MARK,
-        /* HDMI */
-        HDMI_HPD_MARK, HDMI_CEC_MARK,
-        /* DEBUG */
-        EDEBGREQ_PULLUP_MARK,   /* for JTAG */
-        EDEBGREQ_PULLDOWN_MARK,
-        TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
-        TRACEAUD_FROM_LCDC0_MARK,
-        TRACEAUD_FROM_MEMC_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
-        /* Port0 */
-        PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
-        PINMUX_DATA(FSIAISLD_PORT0_MARK,        PORT0_FN2,      MSEL5CR_3_0),
-        PINMUX_DATA(FSIAOSLD1_MARK,             PORT0_FN3),
-        PINMUX_DATA(LCD0_D22_PORT0_MARK,        PORT0_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(SCIFA7_RXD_MARK,            PORT0_FN6),
-        PINMUX_DATA(LCD1_D4_MARK,               PORT0_FN7),
-        PINMUX_DATA(IRQ5_PORT0_MARK,            PORT0_FN0,      MSEL1CR_5_0),
-        /* Port1 */
-        PINMUX_DATA(DBGMDT1_MARK,               PORT1_FN1),
-        PINMUX_DATA(FMSISLD_PORT1_MARK,         PORT1_FN2,      MSEL5CR_5_0),
-        PINMUX_DATA(FSIAOSLD2_MARK,             PORT1_FN3),
-        PINMUX_DATA(LCD0_D23_PORT1_MARK,        PORT1_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(SCIFA7_TXD_MARK,            PORT1_FN6),
-        PINMUX_DATA(LCD1_D3_MARK,               PORT1_FN7),
-        PINMUX_DATA(IRQ5_PORT1_MARK,            PORT1_FN0,      MSEL1CR_5_1),
-        /* Port2 */
-        PINMUX_DATA(DBGMDT0_MARK,               PORT2_FN1),
-        PINMUX_DATA(SCIFB_SCK_PORT2_MARK,       PORT2_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D21_PORT2_MARK,        PORT2_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D2_MARK,               PORT2_FN7),
-        PINMUX_DATA(IRQ0_PORT2_MARK,            PORT2_FN0,      MSEL1CR_0_1),
-        /* Port3 */
-        PINMUX_DATA(DBGMD21_MARK,               PORT3_FN1),
-        PINMUX_DATA(SCIFB_RXD_PORT3_MARK,       PORT3_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D20_PORT3_MARK,        PORT3_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D1_MARK,               PORT3_FN7),
-        /* Port4 */
-        PINMUX_DATA(DBGMD20_MARK,               PORT4_FN1),
-        PINMUX_DATA(SCIFB_TXD_PORT4_MARK,       PORT4_FN2,      MSEL5CR_17_1),
-        PINMUX_DATA(LCD0_D19_PORT4_MARK,        PORT4_FN4,      MSEL5CR_6_0),
-        PINMUX_DATA(LCD1_D0_MARK,               PORT4_FN7),
-        /* Port5 */
-        PINMUX_DATA(DBGMD11_MARK,               PORT5_FN1),
-        PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,      PORT5_FN2,      MSEL5CR_0_0),
-        PINMUX_DATA(FSIAISLD_PORT5_MARK,        PORT5_FN4,      MSEL5CR_3_1),
-        PINMUX_DATA(RSPI_SSL0_A_MARK,           PORT5_FN6),
-        PINMUX_DATA(LCD1_VCPWC_MARK,            PORT5_FN7),
-        /* Port6 */
-        PINMUX_DATA(DBGMD10_MARK,               PORT6_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,    PORT6_FN2,      MSEL5CR_0_0),
-        PINMUX_DATA(FMSISLD_PORT6_MARK,         PORT6_FN4,      MSEL5CR_5_1),
-        PINMUX_DATA(RSPI_SSL1_A_MARK,           PORT6_FN6),
-        PINMUX_DATA(LCD1_VEPWC_MARK,            PORT6_FN7),
-        /* Port7 */
-        PINMUX_DATA(FSIAOLR_MARK,               PORT7_FN1),
-        /* Port8 */
-        PINMUX_DATA(FSIAOBT_MARK,               PORT8_FN1),
-        /* Port9 */
-        PINMUX_DATA(FSIAOSLD_MARK,              PORT9_FN1),
-        PINMUX_DATA(FSIASPDIF_PORT9_MARK,       PORT9_FN2,      MSEL5CR_4_0),
-        /* Port10 */
-        PINMUX_DATA(FSIAOMC_MARK,               PORT10_FN1),
-        PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,     PORT10_FN3,     MSEL5CR_14_0,   MSEL5CR_15_0),
-        PINMUX_DATA(IRQ3_PORT10_MARK,           PORT10_FN0,     MSEL1CR_3_0),
-        /* Port11 */
-        PINMUX_DATA(FSIACK_MARK,                PORT11_FN1),
-        PINMUX_DATA(FSIBCK_MARK,                PORT11_FN2),
-        PINMUX_DATA(IRQ2_PORT11_MARK,           PORT11_FN0,     MSEL1CR_2_0),
-        /* Port12 */
-        PINMUX_DATA(FSIAILR_MARK,               PORT12_FN1),
-        PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,     PORT12_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
-        PINMUX_DATA(LCD1_RS_MARK,               PORT12_FN6),
-        PINMUX_DATA(LCD1_DISP_MARK,             PORT12_FN7),
-        PINMUX_DATA(IRQ2_PORT12_MARK,           PORT12_FN0,     MSEL1CR_2_1),
-        /* Port13 */
-        PINMUX_DATA(FSIAIBT_MARK,               PORT13_FN1),
-        PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,     PORT13_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
-        PINMUX_DATA(LCD1_RD_MARK,               PORT13_FN7),
-        PINMUX_DATA(IRQ0_PORT13_MARK,           PORT13_FN0,     MSEL1CR_0_0),
-        /* Port14 */
-        PINMUX_DATA(FMSOILR_MARK,               PORT14_FN1),
-        PINMUX_DATA(FMSIILR_MARK,               PORT14_FN2),
-        PINMUX_DATA(VIO_CKO1_MARK,              PORT14_FN3),
-        PINMUX_DATA(LCD1_D23_MARK,              PORT14_FN7),
-        PINMUX_DATA(IRQ3_PORT14_MARK,           PORT14_FN0,     MSEL1CR_3_1),
-        /* Port15 */
-        PINMUX_DATA(FMSOIBT_MARK,               PORT15_FN1),
-        PINMUX_DATA(FMSIIBT_MARK,               PORT15_FN2),
-        PINMUX_DATA(VIO_CKO2_MARK,              PORT15_FN3),
-        PINMUX_DATA(LCD1_D22_MARK,              PORT15_FN7),
-        PINMUX_DATA(IRQ4_PORT15_MARK,           PORT15_FN0,     MSEL1CR_4_0),
-        /* Port16 */
-        PINMUX_DATA(FMSOOLR_MARK,               PORT16_FN1),
-        PINMUX_DATA(FMSIOLR_MARK,               PORT16_FN2),
-        /* Port17 */
-        PINMUX_DATA(FMSOOBT_MARK,               PORT17_FN1),
-        PINMUX_DATA(FMSIOBT_MARK,               PORT17_FN2),
-        /* Port18 */
-        PINMUX_DATA(FMSOSLD_MARK,               PORT18_FN1),
-        PINMUX_DATA(FSIASPDIF_PORT18_MARK,      PORT18_FN2,     MSEL5CR_4_1),
-        /* Port19 */
-        PINMUX_DATA(FMSICK_MARK,                PORT19_FN1),
-        PINMUX_DATA(CS5A_PORT19_MARK,           PORT19_FN7,     MSEL5CR_2_1),
-        PINMUX_DATA(IRQ10_MARK,                 PORT19_FN0),
-        /* Port20 */
-        PINMUX_DATA(FMSOCK_MARK,                PORT20_FN1),
-        PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,     PORT20_FN3,     MSEL5CR_15_0,   MSEL5CR_14_0),
-        PINMUX_DATA(IRQ1_MARK,                  PORT20_FN0),
-        /* Port21 */
-        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT21_FN1),
-        PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,     PORT21_FN2,     MSEL5CR_10_0),
-        PINMUX_DATA(TPU0TO1_MARK,               PORT21_FN4),
-        PINMUX_DATA(VIO1_FIELD_MARK,            PORT21_FN5),
-        PINMUX_DATA(STP0_IPD5_MARK,             PORT21_FN6),
-        PINMUX_DATA(LCD1_D10_MARK,              PORT21_FN7),
-        /* Port22 */
-        PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,     PORT22_FN1,     MSEL5CR_7_0),
-        PINMUX_DATA(SIM_D_PORT22_MARK,          PORT22_FN4,     MSEL5CR_21_0),
-        PINMUX_DATA(VIO0_D13_PORT22_MARK,       PORT22_FN7,     MSEL5CR_27_1),
-        /* Port23 */
-        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT23_FN1),
-        PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,     PORT23_FN3,     MSEL5CR_13_0),
-        PINMUX_DATA(TPU0TO0_MARK,               PORT23_FN4),
-        PINMUX_DATA(VIO_CKO_1_MARK,             PORT23_FN5),
-        PINMUX_DATA(STP0_IPD2_MARK,             PORT23_FN6),
-        PINMUX_DATA(LCD1_D7_MARK,               PORT23_FN7),
-        /* Port24 */
-        PINMUX_DATA(VIO0_D15_PORT24_MARK,       PORT24_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D7_MARK,               PORT24_FN5),
-        PINMUX_DATA(SCIFA6_SCK_MARK,            PORT24_FN6),
-        PINMUX_DATA(SDHI2_CD_PORT24_MARK,       PORT24_FN7,     MSEL5CR_19_0),
-        /* Port25 */
-        PINMUX_DATA(VIO0_D14_PORT25_MARK,       PORT25_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D6_MARK,               PORT25_FN5),
-        PINMUX_DATA(SCIFA6_RXD_MARK,            PORT25_FN6),
-        PINMUX_DATA(SDHI2_WP_PORT25_MARK,       PORT25_FN7,     MSEL5CR_19_0),
-        /* Port26 */
-        PINMUX_DATA(VIO0_D13_PORT26_MARK,       PORT26_FN1,     MSEL5CR_27_0),
-        PINMUX_DATA(VIO1_D5_MARK,               PORT26_FN5),
-        PINMUX_DATA(SCIFA6_TXD_MARK,            PORT26_FN6),
-        /* Port27 - Port39 Function */
-        PINMUX_DATA(VIO0_D7_MARK,               PORT27_FN1),
-        PINMUX_DATA(VIO0_D6_MARK,               PORT28_FN1),
-        PINMUX_DATA(VIO0_D5_MARK,               PORT29_FN1),
-        PINMUX_DATA(VIO0_D4_MARK,               PORT30_FN1),
-        PINMUX_DATA(VIO0_D3_MARK,               PORT31_FN1),
-        PINMUX_DATA(VIO0_D2_MARK,               PORT32_FN1),
-        PINMUX_DATA(VIO0_D1_MARK,               PORT33_FN1),
-        PINMUX_DATA(VIO0_D0_MARK,               PORT34_FN1),
-        PINMUX_DATA(VIO0_CLK_MARK,              PORT35_FN1),
-        PINMUX_DATA(VIO_CKO_MARK,               PORT36_FN1),
-        PINMUX_DATA(VIO0_HD_MARK,               PORT37_FN1),
-        PINMUX_DATA(VIO0_FIELD_MARK,            PORT38_FN1),
-        PINMUX_DATA(VIO0_VD_MARK,               PORT39_FN1),
-        /* Port38 IRQ */
-        PINMUX_DATA(IRQ25_MARK,                 PORT38_FN0),
-        /* Port40 */
-        PINMUX_DATA(LCD0_D18_PORT40_MARK,       PORT40_FN4,     MSEL5CR_6_0),
-        PINMUX_DATA(RSPI_CK_A_MARK,             PORT40_FN6),
-        PINMUX_DATA(LCD1_LCLK_MARK,             PORT40_FN7),
-        /* Port41 */
-        PINMUX_DATA(LCD0_D17_MARK,              PORT41_FN1),
-        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT41_FN2),
-        PINMUX_DATA(IRQ31_PORT41_MARK,          PORT41_FN0,     MSEL1CR_31_1),
-        /* Port42 */
-        PINMUX_DATA(LCD0_D16_MARK,              PORT42_FN1),
-        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT42_FN2),
-        PINMUX_DATA(IRQ12_PORT42_MARK,          PORT42_FN0,     MSEL1CR_12_1),
-        /* Port43 */
-        PINMUX_DATA(LCD0_D15_MARK,              PORT43_FN1),
-        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT43_FN2),
-        PINMUX_DATA(KEYIN0_PORT43_MARK,         PORT43_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D15_MARK,                PORT43_FN6),
-        /* Port44 */
-        PINMUX_DATA(LCD0_D14_MARK,              PORT44_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT44_FN2),
-        PINMUX_DATA(KEYIN1_PORT44_MARK,         PORT44_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D14_MARK,                PORT44_FN6),
-        /* Port45 */
-        PINMUX_DATA(LCD0_D13_MARK,              PORT45_FN1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT45_FN2),
-        PINMUX_DATA(KEYIN2_PORT45_MARK,         PORT45_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D13_MARK,                PORT45_FN6),
-        /* Port46 */
-        PINMUX_DATA(LCD0_D12_MARK,              PORT46_FN1),
-        PINMUX_DATA(KEYIN3_PORT46_MARK,         PORT46_FN3,     MSEL4CR_18_0),
-        PINMUX_DATA(DV_D12_MARK,                PORT46_FN6),
-        /* Port47 */
-        PINMUX_DATA(LCD0_D11_MARK,              PORT47_FN1),
-        PINMUX_DATA(KEYIN4_MARK,                PORT47_FN3),
-        PINMUX_DATA(DV_D11_MARK,                PORT47_FN6),
-        /* Port48 */
-        PINMUX_DATA(LCD0_D10_MARK,              PORT48_FN1),
-        PINMUX_DATA(KEYIN5_MARK,                PORT48_FN3),
-        PINMUX_DATA(DV_D10_MARK,                PORT48_FN6),
-        /* Port49 */
-        PINMUX_DATA(LCD0_D9_MARK,               PORT49_FN1),
-        PINMUX_DATA(KEYIN6_MARK,                PORT49_FN3),
-        PINMUX_DATA(DV_D9_MARK,                 PORT49_FN6),
-        PINMUX_DATA(IRQ30_PORT49_MARK,          PORT49_FN0,     MSEL1CR_30_1),
-        /* Port50 */
-        PINMUX_DATA(LCD0_D8_MARK,               PORT50_FN1),
-        PINMUX_DATA(KEYIN7_MARK,                PORT50_FN3),
-        PINMUX_DATA(DV_D8_MARK,                 PORT50_FN6),
-        PINMUX_DATA(IRQ29_PORT50_MARK,          PORT50_FN0,     MSEL1CR_29_1),
-        /* Port51 */
-        PINMUX_DATA(LCD0_D7_MARK,               PORT51_FN1),
-        PINMUX_DATA(KEYOUT0_MARK,               PORT51_FN3),
-        PINMUX_DATA(DV_D7_MARK,                 PORT51_FN6),
-        /* Port52 */
-        PINMUX_DATA(LCD0_D6_MARK,               PORT52_FN1),
-        PINMUX_DATA(KEYOUT1_MARK,               PORT52_FN3),
-        PINMUX_DATA(DV_D6_MARK,                 PORT52_FN6),
-        /* Port53 */
-        PINMUX_DATA(LCD0_D5_MARK,               PORT53_FN1),
-        PINMUX_DATA(KEYOUT2_MARK,               PORT53_FN3),
-        PINMUX_DATA(DV_D5_MARK,                 PORT53_FN6),
-        /* Port54 */
-        PINMUX_DATA(LCD0_D4_MARK,               PORT54_FN1),
-        PINMUX_DATA(KEYOUT3_MARK,               PORT54_FN3),
-        PINMUX_DATA(DV_D4_MARK,                 PORT54_FN6),
-        /* Port55 */
-        PINMUX_DATA(LCD0_D3_MARK,               PORT55_FN1),
-        PINMUX_DATA(KEYOUT4_MARK,               PORT55_FN3),
-        PINMUX_DATA(KEYIN3_PORT55_MARK,         PORT55_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D3_MARK,                 PORT55_FN6),
-        /* Port56 */
-        PINMUX_DATA(LCD0_D2_MARK,               PORT56_FN1),
-        PINMUX_DATA(KEYOUT5_MARK,               PORT56_FN3),
-        PINMUX_DATA(KEYIN2_PORT56_MARK,         PORT56_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D2_MARK,                 PORT56_FN6),
-        PINMUX_DATA(IRQ28_PORT56_MARK,          PORT56_FN0,     MSEL1CR_28_1),
-        /* Port57 */
-        PINMUX_DATA(LCD0_D1_MARK,               PORT57_FN1),
-        PINMUX_DATA(KEYOUT6_MARK,               PORT57_FN3),
-        PINMUX_DATA(KEYIN1_PORT57_MARK,         PORT57_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D1_MARK,                 PORT57_FN6),
-        PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
-        /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
-        PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
-        PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
-        PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
-        PINMUX_DATA(IRQ26_PORT58_MARK,          PORT58_FN0,     MSEL1CR_26_1),
-        /* Port59 */
-        PINMUX_DATA(LCD0_VCPWC_MARK,            PORT59_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,    PORT59_FN2,     MSEL5CR_0_0),
-        PINMUX_DATA(RSPI_MOSI_A_MARK,           PORT59_FN6),
-        /* Port60 */
-        PINMUX_DATA(LCD0_VEPWC_MARK,            PORT60_FN1),
-        PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,     PORT60_FN2,     MSEL5CR_0_0),
-        PINMUX_DATA(RSPI_MISO_A_MARK,           PORT60_FN6),
-        /* Port61 */
-        PINMUX_DATA(LCD0_DON_MARK,              PORT61_FN1),
-        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT61_FN2),
-        /* Port62 */
-        PINMUX_DATA(LCD0_DCK_MARK,              PORT62_FN1),
-        PINMUX_DATA(LCD0_WR_MARK,               PORT62_FN4),
-        PINMUX_DATA(DV_CLK_MARK,                PORT62_FN6),
-        PINMUX_DATA(IRQ15_PORT62_MARK,          PORT62_FN0,     MSEL1CR_15_1),
-        /* Port63 */
-        PINMUX_DATA(LCD0_VSYN_MARK,             PORT63_FN1),
-        PINMUX_DATA(DV_VSYNC_MARK,              PORT63_FN6),
-        PINMUX_DATA(IRQ14_PORT63_MARK,          PORT63_FN0,     MSEL1CR_14_1),
-        /* Port64 */
-        PINMUX_DATA(LCD0_HSYN_MARK,             PORT64_FN1),
-        PINMUX_DATA(LCD0_CS_MARK,               PORT64_FN4),
-        PINMUX_DATA(DV_HSYNC_MARK,              PORT64_FN6),
-        PINMUX_DATA(IRQ13_PORT64_MARK,          PORT64_FN0,     MSEL1CR_13_1),
-        /* Port65 */
-        PINMUX_DATA(LCD0_DISP_MARK,             PORT65_FN1),
-        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT65_FN2),
-        PINMUX_DATA(LCD0_RS_MARK,               PORT65_FN4),
-        /* Port66 */
-        PINMUX_DATA(MEMC_INT_MARK,              PORT66_FN1),
-        PINMUX_DATA(TPU0TO2_PORT66_MARK,        PORT66_FN3,     MSEL5CR_25_0),
-        PINMUX_DATA(MMC0_CLK_PORT66_MARK,       PORT66_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(SDHI1_CLK_MARK,             PORT66_FN6),
-        /* Port67 - Port73 Function1 */
-        PINMUX_DATA(MEMC_CS0_MARK,              PORT67_FN1),
-        PINMUX_DATA(MEMC_AD8_MARK,              PORT68_FN1),
-        PINMUX_DATA(MEMC_AD9_MARK,              PORT69_FN1),
-        PINMUX_DATA(MEMC_AD10_MARK,             PORT70_FN1),
-        PINMUX_DATA(MEMC_AD11_MARK,             PORT71_FN1),
-        PINMUX_DATA(MEMC_AD12_MARK,             PORT72_FN1),
-        PINMUX_DATA(MEMC_AD13_MARK,             PORT73_FN1),
-        /* Port67 - Port73 Function2 */
-        PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,     PORT67_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT68_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT69_FN2),
-        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT70_FN2),
-        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT71_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,    PORT72_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,   PORT73_FN2,     MSEL4CR_10_1),
-        /* Port67 - Port73 Function4 */
-        PINMUX_DATA(MMC0_CMD_PORT67_MARK,       PORT67_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D0_PORT68_MARK,        PORT68_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D1_PORT69_MARK,        PORT69_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D2_PORT70_MARK,        PORT70_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D3_PORT71_MARK,        PORT71_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D4_PORT72_MARK,        PORT72_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(MMC0_D5_PORT73_MARK,        PORT73_FN4,     MSEL4CR_15_0),
-        /* Port67 - Port73 Function6 */
-        PINMUX_DATA(SDHI1_CMD_MARK,             PORT67_FN6),
-        PINMUX_DATA(SDHI1_D0_MARK,              PORT68_FN6),
-        PINMUX_DATA(SDHI1_D1_MARK,              PORT69_FN6),
-        PINMUX_DATA(SDHI1_D2_MARK,              PORT70_FN6),
-        PINMUX_DATA(SDHI1_D3_MARK,              PORT71_FN6),
-        PINMUX_DATA(SDHI1_CD_MARK,              PORT72_FN6),
-        PINMUX_DATA(SDHI1_WP_MARK,              PORT73_FN6),
-        /* Port67 - Port71 IRQ */
-        PINMUX_DATA(IRQ20_MARK,                 PORT67_FN0),
-        PINMUX_DATA(IRQ16_PORT68_MARK,          PORT68_FN0,     MSEL1CR_16_0),
-        PINMUX_DATA(IRQ17_MARK,                 PORT69_FN0),
-        PINMUX_DATA(IRQ18_MARK,                 PORT70_FN0),
-        PINMUX_DATA(IRQ19_MARK,                 PORT71_FN0),
-        /* Port74 */
-        PINMUX_DATA(MEMC_AD14_MARK,             PORT74_FN1),
-        PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,     PORT74_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MMC0_D6_PORT74_MARK,        PORT74_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(STP1_IPD7_MARK,             PORT74_FN6),
-        PINMUX_DATA(LCD1_D21_MARK,              PORT74_FN7),
-        /* Port75 */
-        PINMUX_DATA(MEMC_AD15_MARK,             PORT75_FN1),
-        PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,     PORT75_FN2,     MSEL4CR_10_1),
-        PINMUX_DATA(MMC0_D7_PORT75_MARK,        PORT75_FN4,     MSEL4CR_15_0),
-        PINMUX_DATA(STP1_IPD6_MARK,             PORT75_FN6),
-        PINMUX_DATA(LCD1_D20_MARK,              PORT75_FN7),
-        /* Port76 - Port80 Function */
-        PINMUX_DATA(SDHI0_CMD_MARK,             PORT76_FN1),
-        PINMUX_DATA(SDHI0_D0_MARK,              PORT77_FN1),
-        PINMUX_DATA(SDHI0_D1_MARK,              PORT78_FN1),
-        PINMUX_DATA(SDHI0_D2_MARK,              PORT79_FN1),
-        PINMUX_DATA(SDHI0_D3_MARK,              PORT80_FN1),
-        /* Port81 */
-        PINMUX_DATA(SDHI0_CD_MARK,              PORT81_FN1),
-        PINMUX_DATA(IRQ26_PORT81_MARK,          PORT81_FN0,     MSEL1CR_26_0),
-        /* Port82 - Port88 Function */
-        PINMUX_DATA(SDHI0_CLK_MARK,             PORT82_FN1),
-        PINMUX_DATA(SDHI0_WP_MARK,              PORT83_FN1),
-        PINMUX_DATA(RESETOUTS_MARK,             PORT84_FN1),
-        PINMUX_DATA(USB0_PPON_MARK,             PORT85_FN1),
-        PINMUX_DATA(USB0_OCI_MARK,              PORT86_FN1),
-        PINMUX_DATA(USB1_PPON_MARK,             PORT87_FN1),
-        PINMUX_DATA(USB1_OCI_MARK,              PORT88_FN1),
-        /* Port89 */
-        PINMUX_DATA(DREQ0_MARK,                 PORT89_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,    PORT89_FN2,     MSEL5CR_0_1),
-        PINMUX_DATA(RSPI_SSL3_A_MARK,           PORT89_FN6),
-        /* Port90 */
-        PINMUX_DATA(DACK0_MARK,                 PORT90_FN1),
-        PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,     PORT90_FN2,     MSEL5CR_0_1),
-        PINMUX_DATA(RSPI_SSL2_A_MARK,           PORT90_FN6),
-        PINMUX_DATA(WAIT_PORT90_MARK,           PORT90_FN7,     MSEL5CR_2_1),
-        /* Port91 */
-        PINMUX_DATA(MEMC_AD0_MARK,              PORT91_FN1),
-        PINMUX_DATA(BBIF1_RXD_MARK,             PORT91_FN2),
-        PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,     PORT91_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
-        PINMUX_DATA(LCD1_D5_MARK,               PORT91_FN7),
-        /* Port92 */
-        PINMUX_DATA(MEMC_AD1_MARK,              PORT92_FN1),
-        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT92_FN2),
-        PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,     PORT92_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
-        PINMUX_DATA(STP0_IPD1_MARK,             PORT92_FN6),
-        PINMUX_DATA(LCD1_D6_MARK,               PORT92_FN7),
-        /* Port93 */
-        PINMUX_DATA(MEMC_AD2_MARK,              PORT93_FN1),
-        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT93_FN2),
-        PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,     PORT93_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
-        PINMUX_DATA(STP0_IPD3_MARK,             PORT93_FN6),
-        PINMUX_DATA(LCD1_D8_MARK,               PORT93_FN7),
-        /* Port94 */
-        PINMUX_DATA(MEMC_AD3_MARK,              PORT94_FN1),
-        PINMUX_DATA(BBIF1_TXD_MARK,             PORT94_FN2),
-        PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,     PORT94_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
-        PINMUX_DATA(STP0_IPD4_MARK,             PORT94_FN6),
-        PINMUX_DATA(LCD1_D9_MARK,               PORT94_FN7),
-        /* Port95 */
-        PINMUX_DATA(MEMC_CS1_MARK,              PORT95_FN1,     MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_A1_MARK,               PORT95_FN1,     MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_CTS_MARK,            PORT95_FN2),
-        PINMUX_DATA(SIM_RST_MARK,               PORT95_FN4),
-        PINMUX_DATA(VIO0_D14_PORT95_MARK,       PORT95_FN7,     MSEL5CR_27_1),
-        PINMUX_DATA(IRQ22_MARK,                 PORT95_FN0),
-        /* Port96 */
-        PINMUX_DATA(MEMC_ADV_MARK,              PORT96_FN1,     MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_DREQ0_MARK,            PORT96_FN1,     MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_RTS_MARK,            PORT96_FN2),
-        PINMUX_DATA(SIM_CLK_MARK,               PORT96_FN4),
-        PINMUX_DATA(VIO0_D15_PORT96_MARK,       PORT96_FN7,     MSEL5CR_27_1),
-        PINMUX_DATA(IRQ23_MARK,                 PORT96_FN0),
-        /* Port97 */
-        PINMUX_DATA(MEMC_AD4_MARK,              PORT97_FN1),
-        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT97_FN2),
-        PINMUX_DATA(LCD1_CS_MARK,               PORT97_FN6),
-        PINMUX_DATA(LCD1_HSYN_MARK,             PORT97_FN7),
-        PINMUX_DATA(IRQ12_PORT97_MARK,          PORT97_FN0,     MSEL1CR_12_0),
-        /* Port98 */
-        PINMUX_DATA(MEMC_AD5_MARK,              PORT98_FN1),
-        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT98_FN2),
-        PINMUX_DATA(LCD1_VSYN_MARK,             PORT98_FN7),
-        PINMUX_DATA(IRQ13_PORT98_MARK,          PORT98_FN0,     MSEL1CR_13_0),
-        /* Port99 */
-        PINMUX_DATA(MEMC_AD6_MARK,              PORT99_FN1),
-        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT99_FN2),
-        PINMUX_DATA(LCD1_WR_MARK,               PORT99_FN6),
-        PINMUX_DATA(LCD1_DCK_MARK,              PORT99_FN7),
-        PINMUX_DATA(IRQ14_PORT99_MARK,          PORT99_FN0,     MSEL1CR_14_0),
-        /* Port100 */
-        PINMUX_DATA(MEMC_AD7_MARK,              PORT100_FN1),
-        PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,       PORT100_FN2),
-        PINMUX_DATA(LCD1_DON_MARK,              PORT100_FN7),
-        PINMUX_DATA(IRQ15_PORT100_MARK,         PORT100_FN0,    MSEL1CR_15_0),
-        /* Port101 */
-        PINMUX_DATA(FCE0_MARK,                  PORT101_FN1),
-        /* Port102 */
-        PINMUX_DATA(FRB_MARK,                   PORT102_FN1),
-        PINMUX_DATA(LCD0_LCLK_PORT102_MARK,     PORT102_FN4,    MSEL5CR_6_0),
-        /* Port103 */
-        PINMUX_DATA(CS5B_MARK,                  PORT103_FN1),
-        PINMUX_DATA(FCE1_MARK,                  PORT103_FN2),
-        PINMUX_DATA(MMC1_CLK_PORT103_MARK,      PORT103_FN3,    MSEL4CR_15_1),
-        /* Port104 */
-        PINMUX_DATA(CS6A_MARK,                  PORT104_FN1),
-        PINMUX_DATA(MMC1_CMD_PORT104_MARK,      PORT104_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(IRQ11_MARK,                 PORT104_FN0),
-        /* Port105 */
-        PINMUX_DATA(CS5A_PORT105_MARK,          PORT105_FN1,    MSEL5CR_2_0),
-        PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,    PORT105_FN4,    MSEL5CR_8_0),
-        /* Port106 */
-        PINMUX_DATA(IOIS16_MARK,                PORT106_FN1),
-        PINMUX_DATA(IDE_EXBUF_ENB_MARK,         PORT106_FN6),
-        /* Port107 - Port115 Function */
-        PINMUX_DATA(WE3_ICIOWR_MARK,            PORT107_FN1),
-        PINMUX_DATA(WE2_ICIORD_MARK,            PORT108_FN1),
-        PINMUX_DATA(CS0_MARK,                   PORT109_FN1),
-        PINMUX_DATA(CS2_MARK,                   PORT110_FN1),
-        PINMUX_DATA(CS4_MARK,                   PORT111_FN1),
-        PINMUX_DATA(WE1_MARK,                   PORT112_FN1),
-        PINMUX_DATA(WE0_FWE_MARK,               PORT113_FN1),
-        PINMUX_DATA(RDWR_MARK,                  PORT114_FN1),
-        PINMUX_DATA(RD_FSC_MARK,                PORT115_FN1),
-        /* Port116 */
-        PINMUX_DATA(A25_MARK,                   PORT116_FN1),
-        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT116_FN2),
-        PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,    PORT116_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,    PORT116_FN4,    MSEL5CR_8_0),
-        PINMUX_DATA(GPO1_MARK,                  PORT116_FN5),
-        /* Port117 */
-        PINMUX_DATA(A24_MARK,                   PORT117_FN1),
-        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT117_FN2),
-        PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,    PORT117_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,    PORT117_FN4,    MSEL5CR_8_0),
-        PINMUX_DATA(GPO0_MARK,                  PORT117_FN5),
-        /* Port118 */
-        PINMUX_DATA(A23_MARK,                   PORT118_FN1),
-        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT118_FN2),
-        PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,    PORT118_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(GPI1_MARK,                  PORT118_FN5),
-        PINMUX_DATA(IRQ9_PORT118_MARK,          PORT118_FN0,    MSEL1CR_9_0),
-        /* Port119 */
-        PINMUX_DATA(A22_MARK,                   PORT119_FN1),
-        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT119_FN2),
-        PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,    PORT119_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(GPI0_MARK,                  PORT119_FN5),
-        PINMUX_DATA(IRQ8_MARK,                  PORT119_FN0),
-        /* Port120 */
-        PINMUX_DATA(A21_MARK,                   PORT120_FN1),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT120_FN2),
-        PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,  PORT120_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_1),
-        /* Port121 */
-        PINMUX_DATA(A20_MARK,                   PORT121_FN1),
-        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT121_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,   PORT121_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(IRQ6_PORT121_MARK,          PORT121_FN0,    MSEL1CR_6_0),
-        /* Port122 */
-        PINMUX_DATA(A19_MARK,                   PORT122_FN1),
-        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT122_FN2),
-        /* Port123 */
-        PINMUX_DATA(A18_MARK,                   PORT123_FN1),
-        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT123_FN2),
-        /* Port124 */
-        PINMUX_DATA(A17_MARK,                   PORT124_FN1),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT124_FN2),
-        /* Port125 - Port141 Function */
-        PINMUX_DATA(A16_MARK,                   PORT125_FN1),
-        PINMUX_DATA(A15_MARK,                   PORT126_FN1),
-        PINMUX_DATA(A14_MARK,                   PORT127_FN1),
-        PINMUX_DATA(A13_MARK,                   PORT128_FN1),
-        PINMUX_DATA(A12_MARK,                   PORT129_FN1),
-        PINMUX_DATA(A11_MARK,                   PORT130_FN1),
-        PINMUX_DATA(A10_MARK,                   PORT131_FN1),
-        PINMUX_DATA(A9_MARK,                    PORT132_FN1),
-        PINMUX_DATA(A8_MARK,                    PORT133_FN1),
-        PINMUX_DATA(A7_MARK,                    PORT134_FN1),
-        PINMUX_DATA(A6_MARK,                    PORT135_FN1),
-        PINMUX_DATA(A5_FCDE_MARK,               PORT136_FN1),
-        PINMUX_DATA(A4_FOE_MARK,                PORT137_FN1),
-        PINMUX_DATA(A3_MARK,                    PORT138_FN1),
-        PINMUX_DATA(A2_MARK,                    PORT139_FN1),
-        PINMUX_DATA(A1_MARK,                    PORT140_FN1),
-        PINMUX_DATA(CKO_MARK,                   PORT141_FN1),
-        /* Port142 - Port157 Function1 */
-        PINMUX_DATA(D15_NAF15_MARK,             PORT142_FN1),
-        PINMUX_DATA(D14_NAF14_MARK,             PORT143_FN1),
-        PINMUX_DATA(D13_NAF13_MARK,             PORT144_FN1),
-        PINMUX_DATA(D12_NAF12_MARK,             PORT145_FN1),
-        PINMUX_DATA(D11_NAF11_MARK,             PORT146_FN1),
-        PINMUX_DATA(D10_NAF10_MARK,             PORT147_FN1),
-        PINMUX_DATA(D9_NAF9_MARK,               PORT148_FN1),
-        PINMUX_DATA(D8_NAF8_MARK,               PORT149_FN1),
-        PINMUX_DATA(D7_NAF7_MARK,               PORT150_FN1),
-        PINMUX_DATA(D6_NAF6_MARK,               PORT151_FN1),
-        PINMUX_DATA(D5_NAF5_MARK,               PORT152_FN1),
-        PINMUX_DATA(D4_NAF4_MARK,               PORT153_FN1),
-        PINMUX_DATA(D3_NAF3_MARK,               PORT154_FN1),
-        PINMUX_DATA(D2_NAF2_MARK,               PORT155_FN1),
-        PINMUX_DATA(D1_NAF1_MARK,               PORT156_FN1),
-        PINMUX_DATA(D0_NAF0_MARK,               PORT157_FN1),
-        /* Port142 - Port149 Function3 */
-        PINMUX_DATA(MMC1_D7_PORT142_MARK,       PORT142_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D6_PORT143_MARK,       PORT143_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D5_PORT144_MARK,       PORT144_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D4_PORT145_MARK,       PORT145_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D3_PORT146_MARK,       PORT146_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D2_PORT147_MARK,       PORT147_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D1_PORT148_MARK,       PORT148_FN3,    MSEL4CR_15_1),
-        PINMUX_DATA(MMC1_D0_PORT149_MARK,       PORT149_FN3,    MSEL4CR_15_1),
-        /* Port158 */
-        PINMUX_DATA(D31_MARK,                   PORT158_FN1),
-        PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,    PORT158_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(RMII_REF125CK_MARK,         PORT158_FN3),
-        PINMUX_DATA(LCD0_D21_PORT158_MARK,      PORT158_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT158_FN5),
-        PINMUX_DATA(IDE_D15_MARK,               PORT158_FN6),
-        /* Port159 */
-        PINMUX_DATA(D30_MARK,                   PORT159_FN1),
-        PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,    PORT159_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(RMII_REF50CK_MARK,          PORT159_FN3),
-        PINMUX_DATA(LCD0_D23_PORT159_MARK,      PORT159_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IDE_D14_MARK,               PORT159_FN6),
-        /* Port160 */
-        PINMUX_DATA(D29_MARK,                   PORT160_FN1),
-        PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,    PORT160_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(LCD0_D22_PORT160_MARK,      PORT160_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(VIO1_HD_MARK,               PORT160_FN5),
-        PINMUX_DATA(IDE_D13_MARK,               PORT160_FN6),
-        /* Port161 */
-        PINMUX_DATA(D28_MARK,                   PORT161_FN1),
-        PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,    PORT161_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(ET_RX_DV_MARK,              PORT161_FN3),
-        PINMUX_DATA(LCD0_D20_PORT161_MARK,      PORT161_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_IN_MARK,               PORT161_FN5),
-        PINMUX_DATA(IDE_D12_MARK,               PORT161_FN6),
-        /* Port162 */
-        PINMUX_DATA(D27_MARK,                   PORT162_FN1),
-        PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,    PORT162_FN2,    MSEL5CR_8_1),
-        PINMUX_DATA(LCD0_D19_PORT162_MARK,      PORT162_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IRDA_OUT_MARK,              PORT162_FN5),
-        PINMUX_DATA(IDE_D11_MARK,               PORT162_FN6),
-        /* Port163 */
-        PINMUX_DATA(D26_MARK,                   PORT163_FN1),
-        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT163_FN2),
-        PINMUX_DATA(ET_COL_MARK,                PORT163_FN3),
-        PINMUX_DATA(LCD0_D18_PORT163_MARK,      PORT163_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IROUT_MARK,                 PORT163_FN5),
-        PINMUX_DATA(IDE_D10_MARK,               PORT163_FN6),
-        /* Port164 */
-        PINMUX_DATA(D25_MARK,                   PORT164_FN1),
-        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT164_FN2),
-        PINMUX_DATA(ET_PHY_INT_MARK,            PORT164_FN3),
-        PINMUX_DATA(LCD0_RD_MARK,               PORT164_FN4),
-        PINMUX_DATA(IDE_D9_MARK,                PORT164_FN6),
-        /* Port165 */
-        PINMUX_DATA(D24_MARK,                   PORT165_FN1),
-        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT165_FN2),
-        PINMUX_DATA(LCD0_LCLK_PORT165_MARK,     PORT165_FN4,    MSEL5CR_6_1),
-        PINMUX_DATA(IDE_D8_MARK,                PORT165_FN6),
-        /* Port166 - Port171 Function1 */
-        PINMUX_DATA(D21_MARK,                   PORT166_FN1),
-        PINMUX_DATA(D20_MARK,                   PORT167_FN1),
-        PINMUX_DATA(D19_MARK,                   PORT168_FN1),
-        PINMUX_DATA(D18_MARK,                   PORT169_FN1),
-        PINMUX_DATA(D17_MARK,                   PORT170_FN1),
-        PINMUX_DATA(D16_MARK,                   PORT171_FN1),
-        /* Port166 - Port171 Function3 */
-        PINMUX_DATA(ET_ETXD5_MARK,              PORT166_FN3),
-        PINMUX_DATA(ET_ETXD4_MARK,              PORT167_FN3),
-        PINMUX_DATA(ET_ETXD3_MARK,              PORT168_FN3),
-        PINMUX_DATA(ET_ETXD2_MARK,              PORT169_FN3),
-        PINMUX_DATA(ET_ETXD1_MARK,              PORT170_FN3),
-        PINMUX_DATA(ET_ETXD0_MARK,              PORT171_FN3),
-        /* Port166 - Port171 Function6 */
-        PINMUX_DATA(IDE_D5_MARK,                PORT166_FN6),
-        PINMUX_DATA(IDE_D4_MARK,                PORT167_FN6),
-        PINMUX_DATA(IDE_D3_MARK,                PORT168_FN6),
-        PINMUX_DATA(IDE_D2_MARK,                PORT169_FN6),
-        PINMUX_DATA(IDE_D1_MARK,                PORT170_FN6),
-        PINMUX_DATA(IDE_D0_MARK,                PORT171_FN6),
-        /* Port167 - Port171 IRQ */
-        PINMUX_DATA(IRQ31_PORT167_MARK,         PORT167_FN0,    MSEL1CR_31_0),
-        PINMUX_DATA(IRQ27_PORT168_MARK,         PORT168_FN0,    MSEL1CR_27_0),
-        PINMUX_DATA(IRQ28_PORT169_MARK,         PORT169_FN0,    MSEL1CR_28_0),
-        PINMUX_DATA(IRQ29_PORT170_MARK,         PORT170_FN0,    MSEL1CR_29_0),
-        PINMUX_DATA(IRQ30_PORT171_MARK,         PORT171_FN0,    MSEL1CR_30_0),
-        /* Port172 */
-        PINMUX_DATA(D23_MARK,                   PORT172_FN1),
-        PINMUX_DATA(SCIFB_RTS_PORT172_MARK,     PORT172_FN2,    MSEL5CR_17_1),
-        PINMUX_DATA(ET_ETXD7_MARK,              PORT172_FN3),
-        PINMUX_DATA(IDE_D7_MARK,                PORT172_FN6),
-        PINMUX_DATA(IRQ4_PORT172_MARK,          PORT172_FN0,    MSEL1CR_4_1),
-        /* Port173 */
-        PINMUX_DATA(D22_MARK,                   PORT173_FN1),
-        PINMUX_DATA(SCIFB_CTS_PORT173_MARK,     PORT173_FN2,    MSEL5CR_17_1),
-        PINMUX_DATA(ET_ETXD6_MARK,              PORT173_FN3),
-        PINMUX_DATA(IDE_D6_MARK,                PORT173_FN6),
-        PINMUX_DATA(IRQ6_PORT173_MARK,          PORT173_FN0,    MSEL1CR_6_1),
-        /* Port174 */
-        PINMUX_DATA(A26_MARK,                   PORT174_FN1),
-        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT174_FN2),
-        PINMUX_DATA(ET_RX_CLK_MARK,             PORT174_FN3),
-        PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,    PORT174_FN4,    MSEL5CR_8_0),
-        /* Port175 */
-        PINMUX_DATA(A0_MARK,                    PORT175_FN1),
-        PINMUX_DATA(BS_MARK,                    PORT175_FN2),
-        PINMUX_DATA(ET_WOL_MARK,                PORT175_FN3),
-        PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,    PORT175_FN4,    MSEL5CR_8_0),
-        /* Port176 */
-        PINMUX_DATA(ET_GTX_CLK_MARK,            PORT176_FN3),
-        /* Port177 */
-        PINMUX_DATA(WAIT_PORT177_MARK,          PORT177_FN1,    MSEL5CR_2_0),
-        PINMUX_DATA(ET_LINK_MARK,               PORT177_FN3),
-        PINMUX_DATA(IDE_IOWR_MARK,              PORT177_FN6),
-        PINMUX_DATA(SDHI2_WP_PORT177_MARK,      PORT177_FN7,    MSEL5CR_19_1),
-        /* Port178 */
-        PINMUX_DATA(VIO0_D12_MARK,              PORT178_FN1),
-        PINMUX_DATA(VIO1_D4_MARK,               PORT178_FN5),
-        PINMUX_DATA(IDE_IORD_MARK,              PORT178_FN6),
-        /* Port179 */
-        PINMUX_DATA(VIO0_D11_MARK,              PORT179_FN1),
-        PINMUX_DATA(VIO1_D3_MARK,               PORT179_FN5),
-        PINMUX_DATA(IDE_IORDY_MARK,             PORT179_FN6),
-        /* Port180 */
-        PINMUX_DATA(VIO0_D10_MARK,              PORT180_FN1),
-        PINMUX_DATA(TPU0TO3_MARK,               PORT180_FN4),
-        PINMUX_DATA(VIO1_D2_MARK,               PORT180_FN5),
-        PINMUX_DATA(IDE_INT_MARK,               PORT180_FN6),
-        PINMUX_DATA(IRQ24_MARK,                 PORT180_FN0),
-        /* Port181 */
-        PINMUX_DATA(VIO0_D9_MARK,               PORT181_FN1),
-        PINMUX_DATA(VIO1_D1_MARK,               PORT181_FN5),
-        PINMUX_DATA(IDE_RST_MARK,               PORT181_FN6),
-        /* Port182 */
-        PINMUX_DATA(VIO0_D8_MARK,               PORT182_FN1),
-        PINMUX_DATA(VIO1_D0_MARK,               PORT182_FN5),
-        PINMUX_DATA(IDE_DIRECTION_MARK,         PORT182_FN6),
-        /* Port183 */
-        PINMUX_DATA(DREQ1_MARK,                 PORT183_FN1),
-        PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,    PORT183_FN2,    MSEL5CR_0_1),
-        PINMUX_DATA(ET_TX_EN_MARK,              PORT183_FN3),
-        /* Port184 */
-        PINMUX_DATA(DACK1_MARK,                 PORT184_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,  PORT184_FN2,    MSEL5CR_0_1),
-        PINMUX_DATA(ET_TX_CLK_MARK,             PORT184_FN3),
-        /* Port185 - Port192 Function1 */
-        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT185_FN1),
-        PINMUX_DATA(SCIFB_RTS_PORT186_MARK,     PORT186_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_CTS_PORT187_MARK,     PORT187_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT188_FN1),
-        PINMUX_DATA(SCIFB_SCK_PORT190_MARK,     PORT190_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_RXD_PORT191_MARK,     PORT191_FN1,    MSEL5CR_17_0),
-        PINMUX_DATA(SCIFB_TXD_PORT192_MARK,     PORT192_FN1,    MSEL5CR_17_0),
-        /* Port185 - Port192 Function3 */
-        PINMUX_DATA(ET_ERXD0_MARK,              PORT185_FN3),
-        PINMUX_DATA(ET_ERXD1_MARK,              PORT186_FN3),
-        PINMUX_DATA(ET_ERXD2_MARK,              PORT187_FN3),
-        PINMUX_DATA(ET_ERXD3_MARK,              PORT188_FN3),
-        PINMUX_DATA(ET_ERXD4_MARK,              PORT189_FN3),
-        PINMUX_DATA(ET_ERXD5_MARK,              PORT190_FN3),
-        PINMUX_DATA(ET_ERXD6_MARK,              PORT191_FN3),
-        PINMUX_DATA(ET_ERXD7_MARK,              PORT192_FN3),
-        /* Port185 - Port192 Function6 */
-        PINMUX_DATA(STP1_IPCLK_MARK,            PORT185_FN6),
-        PINMUX_DATA(STP1_IPD0_PORT186_MARK,     PORT186_FN6,    MSEL5CR_23_0),
-        PINMUX_DATA(STP1_IPEN_PORT187_MARK,     PORT187_FN6,    MSEL5CR_23_0),
-        PINMUX_DATA(STP1_IPSYNC_MARK,           PORT188_FN6),
-        PINMUX_DATA(STP0_IPCLK_MARK,            PORT189_FN6),
-        PINMUX_DATA(STP0_IPD0_MARK,             PORT190_FN6),
-        PINMUX_DATA(STP0_IPEN_MARK,             PORT191_FN6),
-        PINMUX_DATA(STP0_IPSYNC_MARK,           PORT192_FN6),
-        /* Port193 */
-        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT193_FN1),
-        PINMUX_DATA(RMII_CRS_DV_MARK,           PORT193_FN3),
-        PINMUX_DATA(STP1_IPEN_PORT193_MARK,     PORT193_FN6,    MSEL5CR_23_1), /* ? */
-        PINMUX_DATA(LCD1_D17_MARK,              PORT193_FN7),
-        /* Port194 */
-        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT194_FN1),
-        PINMUX_DATA(RMII_RX_ER_MARK,            PORT194_FN3),
-        PINMUX_DATA(STP1_IPD0_PORT194_MARK,     PORT194_FN6,    MSEL5CR_23_1), /* ? */
-        PINMUX_DATA(LCD1_D16_MARK,              PORT194_FN7),
-        /* Port195 */
-        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT195_FN1),
-        PINMUX_DATA(RMII_RXD0_MARK,             PORT195_FN3),
-        PINMUX_DATA(STP1_IPD3_MARK,             PORT195_FN6),
-        PINMUX_DATA(LCD1_D15_MARK,              PORT195_FN7),
-        /* Port196 */
-        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT196_FN1),
-        PINMUX_DATA(RMII_RXD1_MARK,             PORT196_FN3),
-        PINMUX_DATA(STP1_IPD2_MARK,             PORT196_FN6),
-        PINMUX_DATA(LCD1_D14_MARK,              PORT196_FN7),
-        /* Port197 */
-        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT197_FN1),
-        PINMUX_DATA(VIO1_CLK_MARK,              PORT197_FN5),
-        PINMUX_DATA(STP1_IPD5_MARK,             PORT197_FN6),
-        PINMUX_DATA(LCD1_D19_MARK,              PORT197_FN7),
-        /* Port198 */
-        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT198_FN1),
-        PINMUX_DATA(VIO1_VD_MARK,               PORT198_FN5),
-        PINMUX_DATA(STP1_IPD4_MARK,             PORT198_FN6),
-        PINMUX_DATA(LCD1_D18_MARK,              PORT198_FN7),
-        /* Port199 */
-        PINMUX_DATA(MEMC_NWE_MARK,              PORT199_FN1),
-        PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,    PORT199_FN2,    MSEL5CR_7_1),
-        PINMUX_DATA(RMII_TX_EN_MARK,            PORT199_FN3),
-        PINMUX_DATA(SIM_D_PORT199_MARK,         PORT199_FN4,    MSEL5CR_21_1),
-        PINMUX_DATA(STP1_IPD1_MARK,             PORT199_FN6),
-        PINMUX_DATA(LCD1_D13_MARK,              PORT199_FN7),
-        /* Port200 */
-        PINMUX_DATA(MEMC_NOE_MARK,              PORT200_FN1),
-        PINMUX_DATA(SCIFA2_RXD_MARK,            PORT200_FN2),
-        PINMUX_DATA(RMII_TXD0_MARK,             PORT200_FN3),
-        PINMUX_DATA(STP0_IPD7_MARK,             PORT200_FN6),
-        PINMUX_DATA(LCD1_D12_MARK,              PORT200_FN7),
-        /* Port201 */
-        PINMUX_DATA(MEMC_WAIT_MARK,             PORT201_FN1,    MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_DREQ1_MARK,            PORT201_FN1,    MSEL4CR_6_1),
-        PINMUX_DATA(SCIFA2_TXD_MARK,            PORT201_FN2),
-        PINMUX_DATA(RMII_TXD1_MARK,             PORT201_FN3),
-        PINMUX_DATA(STP0_IPD6_MARK,             PORT201_FN6),
-        PINMUX_DATA(LCD1_D11_MARK,              PORT201_FN7),
-        /* Port202 */
-        PINMUX_DATA(MEMC_BUSCLK_MARK,           PORT202_FN1,    MSEL4CR_6_0),
-        PINMUX_DATA(MEMC_A0_MARK,               PORT202_FN1,    MSEL4CR_6_1),
-        PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,    PORT202_FN2,    MSEL4CR_10_1),
-        PINMUX_DATA(RMII_MDC_MARK,              PORT202_FN3),
-        PINMUX_DATA(TPU0TO2_PORT202_MARK,       PORT202_FN4,    MSEL5CR_25_1),
-        PINMUX_DATA(IDE_CS0_MARK,               PORT202_FN6),
-        PINMUX_DATA(SDHI2_CD_PORT202_MARK,      PORT202_FN7,    MSEL5CR_19_1),
-        PINMUX_DATA(IRQ21_MARK,                 PORT202_FN0),
-        /* Port203 - Port208 Function1 */
-        PINMUX_DATA(SDHI2_CLK_MARK,             PORT203_FN1),
-        PINMUX_DATA(SDHI2_CMD_MARK,             PORT204_FN1),
-        PINMUX_DATA(SDHI2_D0_MARK,              PORT205_FN1),
-        PINMUX_DATA(SDHI2_D1_MARK,              PORT206_FN1),
-        PINMUX_DATA(SDHI2_D2_MARK,              PORT207_FN1),
-        PINMUX_DATA(SDHI2_D3_MARK,              PORT208_FN1),
-        /* Port203 - Port208 Function3 */
-        PINMUX_DATA(ET_TX_ER_MARK,              PORT203_FN3),
-        PINMUX_DATA(ET_RX_ER_MARK,              PORT204_FN3),
-        PINMUX_DATA(ET_CRS_MARK,                PORT205_FN3),
-        PINMUX_DATA(ET_MDC_MARK,                PORT206_FN3),
-        PINMUX_DATA(ET_MDIO_MARK,               PORT207_FN3),
-        PINMUX_DATA(RMII_MDIO_MARK,             PORT208_FN3),
-        /* Port203 - Port208 Function6 */
-        PINMUX_DATA(IDE_A2_MARK,                PORT203_FN6),
-        PINMUX_DATA(IDE_A1_MARK,                PORT204_FN6),
-        PINMUX_DATA(IDE_A0_MARK,                PORT205_FN6),
-        PINMUX_DATA(IDE_IODACK_MARK,            PORT206_FN6),
-        PINMUX_DATA(IDE_IODREQ_MARK,            PORT207_FN6),
-        PINMUX_DATA(IDE_CS1_MARK,               PORT208_FN6),
-        /* Port203 - Port208 Function7 */
-        PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,    PORT203_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
-        PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,    PORT204_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
-        PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,    PORT205_FN7,    MSEL5CR_10_1),
-        PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,    PORT206_FN7,    MSEL5CR_13_1),
-        PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,    PORT207_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
-        PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,    PORT208_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
-        /* Port209 */
-        PINMUX_DATA(VBUS_MARK,                  PORT209_FN1),
-        PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_0),
-        /* Port210 */
-        PINMUX_DATA(IRQ9_PORT210_MARK,          PORT210_FN0,    MSEL1CR_9_1),
-        PINMUX_DATA(HDMI_HPD_MARK,              PORT210_FN1),
-        /* Port211 */
-        PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
-        PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-        /* SDENC */
-        PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
-        PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
-        /* SYSC */
-        PINMUX_DATA(RESETP_PULLUP_MARK,                         MSEL4CR_4_0),
-        PINMUX_DATA(RESETP_PLAIN_MARK,                          MSEL4CR_4_1),
-        /* DEBUG */
-        PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,                     MSEL4CR_1_0),
-        PINMUX_DATA(EDEBGREQ_PULLUP_MARK,                       MSEL4CR_1_1),
-        PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,                     MSEL5CR_30_0,   MSEL5CR_29_0),
-        PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,                   MSEL5CR_30_0,   MSEL5CR_29_1),
-        PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* PORT */
-        GPIO_PORT_ALL(),
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-        /* Function */
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-        /* LCD0 */
-        GPIO_FN(LCD0_D0),       GPIO_FN(LCD0_D1),       GPIO_FN(LCD0_D2),
-        GPIO_FN(LCD0_D3),       GPIO_FN(LCD0_D4),       GPIO_FN(LCD0_D5),
-        GPIO_FN(LCD0_D6),       GPIO_FN(LCD0_D7),       GPIO_FN(LCD0_D8),
-        GPIO_FN(LCD0_D9),       GPIO_FN(LCD0_D10),      GPIO_FN(LCD0_D11),
-        GPIO_FN(LCD0_D12),      GPIO_FN(LCD0_D13),      GPIO_FN(LCD0_D14),
-        GPIO_FN(LCD0_D15),      GPIO_FN(LCD0_D16),      GPIO_FN(LCD0_D17),
-        GPIO_FN(LCD0_DON),      GPIO_FN(LCD0_VCPWC),    GPIO_FN(LCD0_VEPWC),
-        GPIO_FN(LCD0_DCK),      GPIO_FN(LCD0_VSYN),
-        GPIO_FN(LCD0_HSYN),     GPIO_FN(LCD0_DISP),
-        GPIO_FN(LCD0_WR),       GPIO_FN(LCD0_RD),
-        GPIO_FN(LCD0_CS),       GPIO_FN(LCD0_RS),
-        GPIO_FN(LCD0_D18_PORT163),      GPIO_FN(LCD0_D19_PORT162),
-        GPIO_FN(LCD0_D20_PORT161),      GPIO_FN(LCD0_D21_PORT158),
-        GPIO_FN(LCD0_D22_PORT160),      GPIO_FN(LCD0_D23_PORT159),
-        GPIO_FN(LCD0_LCLK_PORT165),     /* MSEL5CR_6_1 */
-        GPIO_FN(LCD0_D18_PORT40),       GPIO_FN(LCD0_D19_PORT4),
-        GPIO_FN(LCD0_D20_PORT3),        GPIO_FN(LCD0_D21_PORT2),
-        GPIO_FN(LCD0_D22_PORT0),        GPIO_FN(LCD0_D23_PORT1),
-        GPIO_FN(LCD0_LCLK_PORT102),     /* MSEL5CR_6_0 */
-        /* LCD1 */
-        GPIO_FN(LCD1_D0),       GPIO_FN(LCD1_D1),       GPIO_FN(LCD1_D2),
-        GPIO_FN(LCD1_D3),       GPIO_FN(LCD1_D4),       GPIO_FN(LCD1_D5),
-        GPIO_FN(LCD1_D6),       GPIO_FN(LCD1_D7),       GPIO_FN(LCD1_D8),
-        GPIO_FN(LCD1_D9),       GPIO_FN(LCD1_D10),      GPIO_FN(LCD1_D11),
-        GPIO_FN(LCD1_D12),      GPIO_FN(LCD1_D13),      GPIO_FN(LCD1_D14),
-        GPIO_FN(LCD1_D15),      GPIO_FN(LCD1_D16),      GPIO_FN(LCD1_D17),
-        GPIO_FN(LCD1_D18),      GPIO_FN(LCD1_D19),      GPIO_FN(LCD1_D20),
-        GPIO_FN(LCD1_D21),      GPIO_FN(LCD1_D22),      GPIO_FN(LCD1_D23),
-        GPIO_FN(LCD1_RS),       GPIO_FN(LCD1_RD),       GPIO_FN(LCD1_CS),
-        GPIO_FN(LCD1_WR),       GPIO_FN(LCD1_DCK),      GPIO_FN(LCD1_DON),
-        GPIO_FN(LCD1_VCPWC),    GPIO_FN(LCD1_LCLK),     GPIO_FN(LCD1_HSYN),
-        GPIO_FN(LCD1_VSYN),     GPIO_FN(LCD1_VEPWC),    GPIO_FN(LCD1_DISP),
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-        /* SDHI0 */
-        GPIO_FN(SDHI0_D0),      GPIO_FN(SDHI0_D1),      GPIO_FN(SDHI0_D2),
-        GPIO_FN(SDHI0_D3),      GPIO_FN(SDHI0_CD),      GPIO_FN(SDHI0_WP),
-        GPIO_FN(SDHI0_CMD),     GPIO_FN(SDHI0_CLK),
-        /* SDHI1 */
-        GPIO_FN(SDHI1_D0),      GPIO_FN(SDHI1_D1),      GPIO_FN(SDHI1_D2),
-        GPIO_FN(SDHI1_D3),      GPIO_FN(SDHI1_CD),      GPIO_FN(SDHI1_WP),
-        GPIO_FN(SDHI1_CMD),     GPIO_FN(SDHI1_CLK),
-        /* SDHI2 */
-        GPIO_FN(SDHI2_D0),      GPIO_FN(SDHI2_D1),      GPIO_FN(SDHI2_D2),
-        GPIO_FN(SDHI2_D3),      GPIO_FN(SDHI2_CLK),     GPIO_FN(SDHI2_CMD),
-        GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
-        GPIO_FN(SDHI2_WP_PORT25),
-        GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
-        GPIO_FN(SDHI2_CD_PORT202),
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-        /* MMC */
-        GPIO_FN(MMC0_D0_PORT68),        GPIO_FN(MMC0_D1_PORT69),
-        GPIO_FN(MMC0_D2_PORT70),        GPIO_FN(MMC0_D3_PORT71),
-        GPIO_FN(MMC0_D4_PORT72),        GPIO_FN(MMC0_D5_PORT73),
-        GPIO_FN(MMC0_D6_PORT74),        GPIO_FN(MMC0_D7_PORT75),
-        GPIO_FN(MMC0_CLK_PORT66),
-        GPIO_FN(MMC0_CMD_PORT67),       /* MSEL4CR_15_0 */
-        GPIO_FN(MMC1_D0_PORT149),       GPIO_FN(MMC1_D1_PORT148),
-        GPIO_FN(MMC1_D2_PORT147),       GPIO_FN(MMC1_D3_PORT146),
-        GPIO_FN(MMC1_D4_PORT145),       GPIO_FN(MMC1_D5_PORT144),
-        GPIO_FN(MMC1_D6_PORT143),       GPIO_FN(MMC1_D7_PORT142),
-        GPIO_FN(MMC1_CLK_PORT103),
-        GPIO_FN(MMC1_CMD_PORT104),      /* MSEL4CR_15_1 */
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-        /* IRREM */
-        GPIO_FN(IROUT),
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0,       0xe6050000), /* PORT0CR */
-        PORTCR(1,       0xe6050001), /* PORT1CR */
-        PORTCR(2,       0xe6050002), /* PORT2CR */
-        PORTCR(3,       0xe6050003), /* PORT3CR */
-        PORTCR(4,       0xe6050004), /* PORT4CR */
-        PORTCR(5,       0xe6050005), /* PORT5CR */
-        PORTCR(6,       0xe6050006), /* PORT6CR */
-        PORTCR(7,       0xe6050007), /* PORT7CR */
-        PORTCR(8,       0xe6050008), /* PORT8CR */
-        PORTCR(9,       0xe6050009), /* PORT9CR */
-        PORTCR(10,      0xe605000a), /* PORT10CR */
-        PORTCR(11,      0xe605000b), /* PORT11CR */
-        PORTCR(12,      0xe605000c), /* PORT12CR */
-        PORTCR(13,      0xe605000d), /* PORT13CR */
-        PORTCR(14,      0xe605000e), /* PORT14CR */
-        PORTCR(15,      0xe605000f), /* PORT15CR */
-        PORTCR(16,      0xe6050010), /* PORT16CR */
-        PORTCR(17,      0xe6050011), /* PORT17CR */
-        PORTCR(18,      0xe6050012), /* PORT18CR */
-        PORTCR(19,      0xe6050013), /* PORT19CR */
-        PORTCR(20,      0xe6050014), /* PORT20CR */
-        PORTCR(21,      0xe6050015), /* PORT21CR */
-        PORTCR(22,      0xe6050016), /* PORT22CR */
-        PORTCR(23,      0xe6050017), /* PORT23CR */
-        PORTCR(24,      0xe6050018), /* PORT24CR */
-        PORTCR(25,      0xe6050019), /* PORT25CR */
-        PORTCR(26,      0xe605001a), /* PORT26CR */
-        PORTCR(27,      0xe605001b), /* PORT27CR */
-        PORTCR(28,      0xe605001c), /* PORT28CR */
-        PORTCR(29,      0xe605001d), /* PORT29CR */
-        PORTCR(30,      0xe605001e), /* PORT30CR */
-        PORTCR(31,      0xe605001f), /* PORT31CR */
-        PORTCR(32,      0xe6050020), /* PORT32CR */
-        PORTCR(33,      0xe6050021), /* PORT33CR */
-        PORTCR(34,      0xe6050022), /* PORT34CR */
-        PORTCR(35,      0xe6050023), /* PORT35CR */
-        PORTCR(36,      0xe6050024), /* PORT36CR */
-        PORTCR(37,      0xe6050025), /* PORT37CR */
-        PORTCR(38,      0xe6050026), /* PORT38CR */
-        PORTCR(39,      0xe6050027), /* PORT39CR */
-        PORTCR(40,      0xe6050028), /* PORT40CR */
-        PORTCR(41,      0xe6050029), /* PORT41CR */
-        PORTCR(42,      0xe605002a), /* PORT42CR */
-        PORTCR(43,      0xe605002b), /* PORT43CR */
-        PORTCR(44,      0xe605002c), /* PORT44CR */
-        PORTCR(45,      0xe605002d), /* PORT45CR */
-        PORTCR(46,      0xe605002e), /* PORT46CR */
-        PORTCR(47,      0xe605002f), /* PORT47CR */
-        PORTCR(48,      0xe6050030), /* PORT48CR */
-        PORTCR(49,      0xe6050031), /* PORT49CR */
-        PORTCR(50,      0xe6050032), /* PORT50CR */
-        PORTCR(51,      0xe6050033), /* PORT51CR */
-        PORTCR(52,      0xe6050034), /* PORT52CR */
-        PORTCR(53,      0xe6050035), /* PORT53CR */
-        PORTCR(54,      0xe6050036), /* PORT54CR */
-        PORTCR(55,      0xe6050037), /* PORT55CR */
-        PORTCR(56,      0xe6050038), /* PORT56CR */
-        PORTCR(57,      0xe6050039), /* PORT57CR */
-        PORTCR(58,      0xe605003a), /* PORT58CR */
-        PORTCR(59,      0xe605003b), /* PORT59CR */
-        PORTCR(60,      0xe605003c), /* PORT60CR */
-        PORTCR(61,      0xe605003d), /* PORT61CR */
-        PORTCR(62,      0xe605003e), /* PORT62CR */
-        PORTCR(63,      0xe605003f), /* PORT63CR */
-        PORTCR(64,      0xe6050040), /* PORT64CR */
-        PORTCR(65,      0xe6050041), /* PORT65CR */
-        PORTCR(66,      0xe6050042), /* PORT66CR */
-        PORTCR(67,      0xe6050043), /* PORT67CR */
-        PORTCR(68,      0xe6050044), /* PORT68CR */
-        PORTCR(69,      0xe6050045), /* PORT69CR */
-        PORTCR(70,      0xe6050046), /* PORT70CR */
-        PORTCR(71,      0xe6050047), /* PORT71CR */
-        PORTCR(72,      0xe6050048), /* PORT72CR */
-        PORTCR(73,      0xe6050049), /* PORT73CR */
-        PORTCR(74,      0xe605004a), /* PORT74CR */
-        PORTCR(75,      0xe605004b), /* PORT75CR */
-        PORTCR(76,      0xe605004c), /* PORT76CR */
-        PORTCR(77,      0xe605004d), /* PORT77CR */
-        PORTCR(78,      0xe605004e), /* PORT78CR */
-        PORTCR(79,      0xe605004f), /* PORT79CR */
-        PORTCR(80,      0xe6050050), /* PORT80CR */
-        PORTCR(81,      0xe6050051), /* PORT81CR */
-        PORTCR(82,      0xe6050052), /* PORT82CR */
-        PORTCR(83,      0xe6050053), /* PORT83CR */
-        PORTCR(84,      0xe6051054), /* PORT84CR */
-        PORTCR(85,      0xe6051055), /* PORT85CR */
-        PORTCR(86,      0xe6051056), /* PORT86CR */
-        PORTCR(87,      0xe6051057), /* PORT87CR */
-        PORTCR(88,      0xe6051058), /* PORT88CR */
-        PORTCR(89,      0xe6051059), /* PORT89CR */
-        PORTCR(90,      0xe605105a), /* PORT90CR */
-        PORTCR(91,      0xe605105b), /* PORT91CR */
-        PORTCR(92,      0xe605105c), /* PORT92CR */
-        PORTCR(93,      0xe605105d), /* PORT93CR */
-        PORTCR(94,      0xe605105e), /* PORT94CR */
-        PORTCR(95,      0xe605105f), /* PORT95CR */
-        PORTCR(96,      0xe6051060), /* PORT96CR */
-        PORTCR(97,      0xe6051061), /* PORT97CR */
-        PORTCR(98,      0xe6051062), /* PORT98CR */
-        PORTCR(99,      0xe6051063), /* PORT99CR */
-        PORTCR(100,     0xe6051064), /* PORT100CR */
-        PORTCR(101,     0xe6051065), /* PORT101CR */
-        PORTCR(102,     0xe6051066), /* PORT102CR */
-        PORTCR(103,     0xe6051067), /* PORT103CR */
-        PORTCR(104,     0xe6051068), /* PORT104CR */
-        PORTCR(105,     0xe6051069), /* PORT105CR */
-        PORTCR(106,     0xe605106a), /* PORT106CR */
-        PORTCR(107,     0xe605106b), /* PORT107CR */
-        PORTCR(108,     0xe605106c), /* PORT108CR */
-        PORTCR(109,     0xe605106d), /* PORT109CR */
-        PORTCR(110,     0xe605106e), /* PORT110CR */
-        PORTCR(111,     0xe605106f), /* PORT111CR */
-        PORTCR(112,     0xe6051070), /* PORT112CR */
-        PORTCR(113,     0xe6051071), /* PORT113CR */
-        PORTCR(114,     0xe6051072), /* PORT114CR */
-        PORTCR(115,     0xe6052073), /* PORT115CR */
-        PORTCR(116,     0xe6052074), /* PORT116CR */
-        PORTCR(117,     0xe6052075), /* PORT117CR */
-        PORTCR(118,     0xe6052076), /* PORT118CR */
-        PORTCR(119,     0xe6052077), /* PORT119CR */
-        PORTCR(120,     0xe6052078), /* PORT120CR */
-        PORTCR(121,     0xe6052079), /* PORT121CR */
-        PORTCR(122,     0xe605207a), /* PORT122CR */
-        PORTCR(123,     0xe605207b), /* PORT123CR */
-        PORTCR(124,     0xe605207c), /* PORT124CR */
-        PORTCR(125,     0xe605207d), /* PORT125CR */
-        PORTCR(126,     0xe605207e), /* PORT126CR */
-        PORTCR(127,     0xe605207f), /* PORT127CR */
-        PORTCR(128,     0xe6052080), /* PORT128CR */
-        PORTCR(129,     0xe6052081), /* PORT129CR */
-        PORTCR(130,     0xe6052082), /* PORT130CR */
-        PORTCR(131,     0xe6052083), /* PORT131CR */
-        PORTCR(132,     0xe6052084), /* PORT132CR */
-        PORTCR(133,     0xe6052085), /* PORT133CR */
-        PORTCR(134,     0xe6052086), /* PORT134CR */
-        PORTCR(135,     0xe6052087), /* PORT135CR */
-        PORTCR(136,     0xe6052088), /* PORT136CR */
-        PORTCR(137,     0xe6052089), /* PORT137CR */
-        PORTCR(138,     0xe605208a), /* PORT138CR */
-        PORTCR(139,     0xe605208b), /* PORT139CR */
-        PORTCR(140,     0xe605208c), /* PORT140CR */
-        PORTCR(141,     0xe605208d), /* PORT141CR */
-        PORTCR(142,     0xe605208e), /* PORT142CR */
-        PORTCR(143,     0xe605208f), /* PORT143CR */
-        PORTCR(144,     0xe6052090), /* PORT144CR */
-        PORTCR(145,     0xe6052091), /* PORT145CR */
-        PORTCR(146,     0xe6052092), /* PORT146CR */
-        PORTCR(147,     0xe6052093), /* PORT147CR */
-        PORTCR(148,     0xe6052094), /* PORT148CR */
-        PORTCR(149,     0xe6052095), /* PORT149CR */
-        PORTCR(150,     0xe6052096), /* PORT150CR */
-        PORTCR(151,     0xe6052097), /* PORT151CR */
-        PORTCR(152,     0xe6052098), /* PORT152CR */
-        PORTCR(153,     0xe6052099), /* PORT153CR */
-        PORTCR(154,     0xe605209a), /* PORT154CR */
-        PORTCR(155,     0xe605209b), /* PORT155CR */
-        PORTCR(156,     0xe605209c), /* PORT156CR */
-        PORTCR(157,     0xe605209d), /* PORT157CR */
-        PORTCR(158,     0xe605209e), /* PORT158CR */
-        PORTCR(159,     0xe605209f), /* PORT159CR */
-        PORTCR(160,     0xe60520a0), /* PORT160CR */
-        PORTCR(161,     0xe60520a1), /* PORT161CR */
-        PORTCR(162,     0xe60520a2), /* PORT162CR */
-        PORTCR(163,     0xe60520a3), /* PORT163CR */
-        PORTCR(164,     0xe60520a4), /* PORT164CR */
-        PORTCR(165,     0xe60520a5), /* PORT165CR */
-        PORTCR(166,     0xe60520a6), /* PORT166CR */
-        PORTCR(167,     0xe60520a7), /* PORT167CR */
-        PORTCR(168,     0xe60520a8), /* PORT168CR */
-        PORTCR(169,     0xe60520a9), /* PORT169CR */
-        PORTCR(170,     0xe60520aa), /* PORT170CR */
-        PORTCR(171,     0xe60520ab), /* PORT171CR */
-        PORTCR(172,     0xe60520ac), /* PORT172CR */
-        PORTCR(173,     0xe60520ad), /* PORT173CR */
-        PORTCR(174,     0xe60520ae), /* PORT174CR */
-        PORTCR(175,     0xe60520af), /* PORT175CR */
-        PORTCR(176,     0xe60520b0), /* PORT176CR */
-        PORTCR(177,     0xe60520b1), /* PORT177CR */
-        PORTCR(178,     0xe60520b2), /* PORT178CR */
-        PORTCR(179,     0xe60520b3), /* PORT179CR */
-        PORTCR(180,     0xe60520b4), /* PORT180CR */
-        PORTCR(181,     0xe60520b5), /* PORT181CR */
-        PORTCR(182,     0xe60520b6), /* PORT182CR */
-        PORTCR(183,     0xe60520b7), /* PORT183CR */
-        PORTCR(184,     0xe60520b8), /* PORT184CR */
-        PORTCR(185,     0xe60520b9), /* PORT185CR */
-        PORTCR(186,     0xe60520ba), /* PORT186CR */
-        PORTCR(187,     0xe60520bb), /* PORT187CR */
-        PORTCR(188,     0xe60520bc), /* PORT188CR */
-        PORTCR(189,     0xe60520bd), /* PORT189CR */
-        PORTCR(190,     0xe60520be), /* PORT190CR */
-        PORTCR(191,     0xe60520bf), /* PORT191CR */
-        PORTCR(192,     0xe60520c0), /* PORT192CR */
-        PORTCR(193,     0xe60520c1), /* PORT193CR */
-        PORTCR(194,     0xe60520c2), /* PORT194CR */
-        PORTCR(195,     0xe60520c3), /* PORT195CR */
-        PORTCR(196,     0xe60520c4), /* PORT196CR */
-        PORTCR(197,     0xe60520c5), /* PORT197CR */
-        PORTCR(198,     0xe60520c6), /* PORT198CR */
-        PORTCR(199,     0xe60520c7), /* PORT199CR */
-        PORTCR(200,     0xe60520c8), /* PORT200CR */
-        PORTCR(201,     0xe60520c9), /* PORT201CR */
-        PORTCR(202,     0xe60520ca), /* PORT202CR */
-        PORTCR(203,     0xe60520cb), /* PORT203CR */
-        PORTCR(204,     0xe60520cc), /* PORT204CR */
-        PORTCR(205,     0xe60520cd), /* PORT205CR */
-        PORTCR(206,     0xe60520ce), /* PORT206CR */
-        PORTCR(207,     0xe60520cf), /* PORT207CR */
-        PORTCR(208,     0xe60520d0), /* PORT208CR */
-        PORTCR(209,     0xe60520d1), /* PORT209CR */
-        PORTCR(210,     0xe60530d2), /* PORT210CR */
-        PORTCR(211,     0xe60530d3), /* PORT211CR */
-        { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
-                        MSEL1CR_31_0,   MSEL1CR_31_1,
-                        MSEL1CR_30_0,   MSEL1CR_30_1,
-                        MSEL1CR_29_0,   MSEL1CR_29_1,
-                        MSEL1CR_28_0,   MSEL1CR_28_1,
-                        MSEL1CR_27_0,   MSEL1CR_27_1,
-                        MSEL1CR_26_0,   MSEL1CR_26_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL1CR_16_0,   MSEL1CR_16_1,
-                        MSEL1CR_15_0,   MSEL1CR_15_1,
-                        MSEL1CR_14_0,   MSEL1CR_14_1,
-                        MSEL1CR_13_0,   MSEL1CR_13_1,
-                        MSEL1CR_12_0,   MSEL1CR_12_1,
-                        0, 0, 0, 0,
-                        MSEL1CR_9_0,    MSEL1CR_9_1,
-                        0, 0,
-                        MSEL1CR_7_0,    MSEL1CR_7_1,
-                        MSEL1CR_6_0,    MSEL1CR_6_1,
-                        MSEL1CR_5_0,    MSEL1CR_5_1,
-                        MSEL1CR_4_0,    MSEL1CR_4_1,
-                        MSEL1CR_3_0,    MSEL1CR_3_1,
-                        MSEL1CR_2_0,    MSEL1CR_2_1,
-                        0, 0,
-                        MSEL1CR_0_0,    MSEL1CR_0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL3CR_15_0,   MSEL3CR_15_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL3CR_6_0,    MSEL3CR_6_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL4CR_19_0,   MSEL4CR_19_1,
-                        MSEL4CR_18_0,   MSEL4CR_18_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_15_0,   MSEL4CR_15_1,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL4CR_10_0,   MSEL4CR_10_1,
-                        0, 0, 0, 0, 0, 0,
-                        MSEL4CR_6_0,    MSEL4CR_6_1,
-                        0, 0,
-                        MSEL4CR_4_0,    MSEL4CR_4_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_1_0,    MSEL4CR_1_1,
-                        0, 0,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
-                        MSEL5CR_31_0,   MSEL5CR_31_1,
-                        MSEL5CR_30_0,   MSEL5CR_30_1,
-                        MSEL5CR_29_0,   MSEL5CR_29_1,
-                        0, 0,
-                        MSEL5CR_27_0,   MSEL5CR_27_1,
-                        0, 0,
-                        MSEL5CR_25_0,   MSEL5CR_25_1,
-                        0, 0,
-                        MSEL5CR_23_0,   MSEL5CR_23_1,
-                        0, 0,
-                        MSEL5CR_21_0,   MSEL5CR_21_1,
-                        0, 0,
-                        MSEL5CR_19_0,   MSEL5CR_19_1,
-                        0, 0,
-                        MSEL5CR_17_0,   MSEL5CR_17_1,
-                        0, 0,
-                        MSEL5CR_15_0,   MSEL5CR_15_1,
-                        MSEL5CR_14_0,   MSEL5CR_14_1,
-                        MSEL5CR_13_0,   MSEL5CR_13_1,
-                        MSEL5CR_12_0,   MSEL5CR_12_1,
-                        MSEL5CR_11_0,   MSEL5CR_11_1,
-                        MSEL5CR_10_0,   MSEL5CR_10_1,
-                        0, 0,
-                        MSEL5CR_8_0,    MSEL5CR_8_1,
-                        MSEL5CR_7_0,    MSEL5CR_7_1,
-                        MSEL5CR_6_0,    MSEL5CR_6_1,
-                        MSEL5CR_5_0,    MSEL5CR_5_1,
-                        MSEL5CR_4_0,    MSEL5CR_4_1,
-                        MSEL5CR_3_0,    MSEL5CR_3_1,
-                        MSEL5CR_2_0,    MSEL5CR_2_1,
-                        0, 0,
-                        MSEL5CR_0_0,    MSEL5CR_0_1,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
-                PORT31_DATA,    PORT30_DATA,    PORT29_DATA,    PORT28_DATA,
-                PORT27_DATA,    PORT26_DATA,    PORT25_DATA,    PORT24_DATA,
-                PORT23_DATA,    PORT22_DATA,    PORT21_DATA,    PORT20_DATA,
-                PORT19_DATA,    PORT18_DATA,    PORT17_DATA,    PORT16_DATA,
-                PORT15_DATA,    PORT14_DATA,    PORT13_DATA,    PORT12_DATA,
-                PORT11_DATA,    PORT10_DATA,    PORT9_DATA,     PORT8_DATA,
-                PORT7_DATA,     PORT6_DATA,     PORT5_DATA,     PORT4_DATA,
-                PORT3_DATA,     PORT2_DATA,     PORT1_DATA,     PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
-                PORT63_DATA,    PORT62_DATA,    PORT61_DATA,    PORT60_DATA,
-                PORT59_DATA,    PORT58_DATA,    PORT57_DATA,    PORT56_DATA,
-                PORT55_DATA,    PORT54_DATA,    PORT53_DATA,    PORT52_DATA,
-                PORT51_DATA,    PORT50_DATA,    PORT49_DATA,    PORT48_DATA,
-                PORT47_DATA,    PORT46_DATA,    PORT45_DATA,    PORT44_DATA,
-                PORT43_DATA,    PORT42_DATA,    PORT41_DATA,    PORT40_DATA,
-                PORT39_DATA,    PORT38_DATA,    PORT37_DATA,    PORT36_DATA,
-                PORT35_DATA,    PORT34_DATA,    PORT33_DATA,    PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                PORT83_DATA,    PORT82_DATA,    PORT81_DATA,    PORT80_DATA,
-                PORT79_DATA,    PORT78_DATA,    PORT77_DATA,    PORT76_DATA,
-                PORT75_DATA,    PORT74_DATA,    PORT73_DATA,    PORT72_DATA,
-                PORT71_DATA,    PORT70_DATA,    PORT69_DATA,    PORT68_DATA,
-                PORT67_DATA,    PORT66_DATA,    PORT65_DATA,    PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
-                PORT95_DATA,    PORT94_DATA,    PORT93_DATA,    PORT92_DATA,
-                PORT91_DATA,    PORT90_DATA,    PORT89_DATA,    PORT88_DATA,
-                PORT87_DATA,    PORT86_DATA,    PORT85_DATA,    PORT84_DATA,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0,              PORT114_DATA,   PORT113_DATA,   PORT112_DATA,
-                PORT111_DATA,   PORT110_DATA,   PORT109_DATA,   PORT108_DATA,
-                PORT107_DATA,   PORT106_DATA,   PORT105_DATA,   PORT104_DATA,
-                PORT103_DATA,   PORT102_DATA,   PORT101_DATA,   PORT100_DATA,
-                PORT99_DATA,    PORT98_DATA,    PORT97_DATA,    PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
-                PORT127_DATA,   PORT126_DATA,   PORT125_DATA,   PORT124_DATA,
-                PORT123_DATA,   PORT122_DATA,   PORT121_DATA,   PORT120_DATA,
-                PORT119_DATA,   PORT118_DATA,   PORT117_DATA,   PORT116_DATA,
-                PORT115_DATA,   0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
-                PORT159_DATA,   PORT158_DATA,   PORT157_DATA,   PORT156_DATA,
-                PORT155_DATA,   PORT154_DATA,   PORT153_DATA,   PORT152_DATA,
-                PORT151_DATA,   PORT150_DATA,   PORT149_DATA,   PORT148_DATA,
-                PORT147_DATA,   PORT146_DATA,   PORT145_DATA,   PORT144_DATA,
-                PORT143_DATA,   PORT142_DATA,   PORT141_DATA,   PORT140_DATA,
-                PORT139_DATA,   PORT138_DATA,   PORT137_DATA,   PORT136_DATA,
-                PORT135_DATA,   PORT134_DATA,   PORT133_DATA,   PORT132_DATA,
-                PORT131_DATA,   PORT130_DATA,   PORT129_DATA,   PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
-                PORT191_DATA,   PORT190_DATA,   PORT189_DATA,   PORT188_DATA,
-                PORT187_DATA,   PORT186_DATA,   PORT185_DATA,   PORT184_DATA,
-                PORT183_DATA,   PORT182_DATA,   PORT181_DATA,   PORT180_DATA,
-                PORT179_DATA,   PORT178_DATA,   PORT177_DATA,   PORT176_DATA,
-                PORT175_DATA,   PORT174_DATA,   PORT173_DATA,   PORT172_DATA,
-                PORT171_DATA,   PORT170_DATA,   PORT169_DATA,   PORT168_DATA,
-                PORT167_DATA,   PORT166_DATA,   PORT165_DATA,   PORT164_DATA,
-                PORT163_DATA,   PORT162_DATA,   PORT161_DATA,   PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0,                           PORT209_DATA,   PORT208_DATA,
-                PORT207_DATA,   PORT206_DATA,   PORT205_DATA,   PORT204_DATA,
-                PORT203_DATA,   PORT202_DATA,   PORT201_DATA,   PORT200_DATA,
-                PORT199_DATA,   PORT198_DATA,   PORT197_DATA,   PORT196_DATA,
-                PORT195_DATA,   PORT194_DATA,   PORT193_DATA,   PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                PORT211_DATA,   PORT210_DATA, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { },
-};
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0,   PORT13_FN0),   /* IRQ0A */
-        PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0),                /* IRQ1A */
-        PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0,  PORT12_FN0),   /* IRQ2A */
-        PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0,  PORT14_FN0),   /* IRQ3A */
-        PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0,  PORT172_FN0),  /* IRQ4A */
-        PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0,   PORT1_FN0),    /* IRQ5A */
-        PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0),  /* IRQ6A */
-        PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0),  /* IRQ7A */
-        PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0),               /* IRQ8A */
-        PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0),  /* IRQ9A */
-        PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0),                /* IRQ10A */
-        PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0),               /* IRQ11A */
-        PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0,  PORT97_FN0),   /* IRQ12A */
-        PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0,  PORT98_FN0),   /* IRQ13A */
-        PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0,  PORT99_FN0),   /* IRQ14A */
-        PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0,  PORT100_FN0),  /* IRQ15A */
-        PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0,  PORT211_FN0),  /* IRQ16A */
-        PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0),                /* IRQ17A */
-        PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0),                /* IRQ18A */
-        PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0),                /* IRQ19A */
-        PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0),                /* IRQ20A */
-        PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0),               /* IRQ21A */
-        PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0),                /* IRQ22A */
-        PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0),                /* IRQ23A */
-        PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0),               /* IRQ24A */
-        PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0),                /* IRQ25A */
-        PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0,  PORT81_FN0),   /* IRQ26A */
-        PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0,  PORT168_FN0),  /* IRQ27A */
-        PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0,  PORT169_FN0),  /* IRQ28A */
-        PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0,  PORT170_FN0),  /* IRQ29A */
-        PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0,  PORT171_FN0),  /* IRQ30A */
-        PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0,  PORT167_FN0),  /* IRQ31A */
-};
-static struct pinmux_info r8a7740_pinmux_info = {
-        .name           = "r8a7740_pfc",
-        .reserved_id    = PINMUX_RESERVED,
-        .data           = { PINMUX_DATA_BEGIN,
-                            PINMUX_DATA_END },
-        .input          = { PINMUX_INPUT_BEGIN,
-                            PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
-        .output         = { PINMUX_OUTPUT_BEGIN,
-                            PINMUX_OUTPUT_END },
-        .mark           = { PINMUX_MARK_BEGIN,
-                            PINMUX_MARK_END },
-        .function       = { PINMUX_FUNCTION_BEGIN,
-                            PINMUX_FUNCTION_END },
-        .first_gpio     = GPIO_PORT0,
-        .last_gpio      = GPIO_FN_TRACEAUD_FROM_MEMC,
-        .gpios          = pinmux_gpios,
-        .cfg_regs       = pinmux_config_regs,
-        .data_regs      = pinmux_data_regs,
-        .gpio_data      = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq       = pinmux_irqs,
-        .gpio_irq_size  = ARRAY_SIZE(pinmux_irqs),
-};
-void r8a7740_pinmux_init(void)
-{
-        register_pinmux(&r8a7740_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
deleted file mode 100644
index 9513234d322b..000000000000
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ /dev/null
@@ -1,2645 +0,0 @@
-/*
- * r8a7779 processor support - PFC hardware block
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <linux/ioport.h>
-#include <mach/r8a7779.h>
-#define CPU_32_PORT(fn, pfx, sfx)                               \
-        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
-        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
-        PORT_1(fn, pfx##31, sfx)
-#define CPU_32_PORT6(fn, pfx, sfx)                              \
-        PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
-        PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
-        PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),       \
-        PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),       \
-        PORT_1(fn, pfx##8, sfx)
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        CPU_32_PORT(fn, pfx##_0_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_1_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_2_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_3_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_4_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_5_, sfx),                         \
-        CPU_32_PORT6(fn, pfx##_6_, sfx)
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,    \
-                                       GP##pfx##_IN, GP##pfx##_OUT)
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-#define GP_ALL(str)     CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
-#define PORT_10_REV(fn, pfx, sfx)                               \
-        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
-        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
-        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
-        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
-        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-#define CPU_32_PORT_REV(fn, pfx, sfx)                                   \
-        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),             \
-        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
-        PORT_10_REV(fn, pfx, sfx)
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-                                                          FN_##ipsr, FN_##fn)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
-        PINMUX_INPUT_END,
-        PINMUX_OUTPUT_BEGIN,
-        GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
-        /* GPSR0 */
-        FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
-        FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
-        FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
-        FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
-        FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
-        FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
-        FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
-        FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
-        /* GPSR1 */
-        FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
-        FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
-        FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
-        FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
-        FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
-        FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
-        FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
-        FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
-        /* GPSR2 */
-        FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
-        FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
-        FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
-        FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
-        FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
-        FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
-        FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
-        FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
-        /* GPSR3 */
-        FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
-        FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
-        FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
-        FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
-        FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
-        FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
-        FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
-        FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
-        /* GPSR4 */
-        FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
-        FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
-        FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
-        FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
-        FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
-        FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-        FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
-        FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
-        /* GPSR5 */
-        FN_A1, FN_A2, FN_A3, FN_A4,
-        FN_A5, FN_A6, FN_A7, FN_A8,
-        FN_A9, FN_A10, FN_A11, FN_A12,
-        FN_A13, FN_A14, FN_A15, FN_A16,
-        FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
-        FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
-        FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
-        FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
-        /* GPSR6 */
-        FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
-        FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
-        FN_IP3_20,
-        /* IPSR0 */
-        FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-        FN_HRTS1, FN_RX4_C,
-        FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
-        FN_CS0, FN_HSPI_CS2_B,
-        FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
-        FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-        FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-        FN_CTS0_B,
-        FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-        FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
-        FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-        FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-        FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
-        FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
-        FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-        FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-        FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-        FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-        FN_SCIF_CLK, FN_TCLK0_C,
-        /* IPSR1 */
-        FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
-        FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
-        FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-        FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
-        FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
-        FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
-        FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-        FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-        FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
-        FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
-        FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
-        FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
-        FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
-        FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
-        FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
-        FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
-        /* IPSR2 */
-        FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-        FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-        FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
-        FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
-        FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
-        FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
-        FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
-        FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
-        FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
-        FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
-        FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
-        FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
-        FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
-        FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
-        FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
-        FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
-        FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
-        FN_DREQ1, FN_SCL2, FN_AUDATA2,
-        /* IPSR3 */
-        FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-        FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
-        FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
-        FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
-        FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
-        FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
-        FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
-        FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
-        FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
-        FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
-        FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
-        FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
-        FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-        FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
-        FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
-        FN_TX2_C, FN_SCL2_C, FN_REMOCON,
-        /* IPSR4 */
-        FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
-        FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-        FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
-        FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
-        FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
-        FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
-        FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
-        FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
-        FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
-        FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
-        FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
-        FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-        FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
-        FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
-        FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
-        FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
-        FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
-        FN_SCK0_D,
-        /* IPSR5 */
-        FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-        FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
-        FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
-        FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
-        FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
-        FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
-        FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
-        FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
-        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-        FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-        FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
-        FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-        FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-        FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
-        FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
-        FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
-        FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
-        FN_CAN_DEBUGOUT0, FN_MOUT0,
-        /* IPSR6 */
-        FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
-        FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
-        FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
-        FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
-        FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
-        FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
-        FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-        FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
-        FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
-        FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
-        FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
-        FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
-        FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-        /* IPSR7 */
-        FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
-        FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-        FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-        FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
-        FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
-        FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
-        FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
-        FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
-        FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
-        FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
-        FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
-        FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
-        FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
-        FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
-        /* IPSR8 */
-        FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-        FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-        FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
-        FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
-        FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
-        FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
-        FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
-        FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
-        FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
-        FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
-        FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
-        FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
-        FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
-        FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-        FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
-        FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
-        /* IPSR9 */
-        FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
-        FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-        FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-        FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
-        FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
-        FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
-        FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
-        FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
-        FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
-        FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
-        FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
-        FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
-        FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
-        FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-        /* IPSR10 */
-        FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-        FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
-        FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
-        FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-        FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
-        FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
-        FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
-        FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-        FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
-        FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
-        FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
-        FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
-        FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
-        FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-        FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
-        FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
-        /* IPSR11 */
-        FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-        FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
-        FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
-        FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
-        FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
-        FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-        FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
-        FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
-        FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-        FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
-        FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
-        FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
-        FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
-        FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
-        /* IPSR12 */
-        FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-        FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
-        FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
-        FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-        FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
-        FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
-        FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-        FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
-        FN_GPS_MAG, FN_FCE, FN_SCK4_B,
-        FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-        FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-        FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
-        FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
-        FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
-        FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
-        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
-        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-        FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
-        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
-        FN_SEL_VI0_0, FN_SEL_VI0_1,
-        FN_SEL_SD2_0, FN_SEL_SD2_1,
-        FN_SEL_INT3_0, FN_SEL_INT3_1,
-        FN_SEL_INT2_0, FN_SEL_INT2_1,
-        FN_SEL_INT1_0, FN_SEL_INT1_1,
-        FN_SEL_INT0_0, FN_SEL_INT0_1,
-        FN_SEL_IE_0, FN_SEL_IE_1,
-        FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
-        FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-        FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
-        FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
-        FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-        FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-        FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-        FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-        FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
-        FN_SEL_ADI_0, FN_SEL_ADI_1,
-        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-        FN_SEL_SIM_0, FN_SEL_SIM_1,
-        FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-        FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-        FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
-        A19_MARK,
-        RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
-        HRTS1_MARK, RX4_C_MARK,
-        CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
-        CS0_MARK, HSPI_CS2_B_MARK,
-        CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
-        A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
-        HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
-        A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
-        HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
-        A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
-        A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
-        A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
-        A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
-        A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
-        BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
-        ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
-        SCIF_CLK_MARK, TCLK0_C_MARK,
-        EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
-        FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
-        EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
-        ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
-        FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
-        HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
-        EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
-        ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
-        TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
-        SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
-        VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
-        SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
-        MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
-        PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
-        SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
-        CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
-        HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
-        SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
-        CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
-        MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
-        SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
-        CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
-        STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
-        SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
-        RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
-        CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
-        CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
-        GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
-        LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
-        AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
-        DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
-        DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
-        DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
-        DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
-        DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
-        AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
-        LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
-        LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
-        LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
-        SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
-        LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
-        AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
-        DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
-        DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
-        DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
-        TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
-        DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
-        SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
-        QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
-        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
-        TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
-        DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
-        DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
-        DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
-        VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
-        AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
-        PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
-        CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
-        VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
-        VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
-        VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
-        SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
-        DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
-        SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
-        VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
-        VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
-        VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
-        VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
-        SCK0_D_MARK,
-        DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
-        RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
-        DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
-        DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
-        DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
-        HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
-        SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
-        VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
-        VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
-        TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
-        VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
-        GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
-        QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
-        GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
-        RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
-        VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
-        GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
-        USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
-        SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
-        CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
-        MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
-        SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
-        CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
-        SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
-        SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
-        CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
-        SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
-        ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
-        SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
-        SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
-        SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
-        SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
-        SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
-        SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
-        HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
-        SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
-        IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
-        VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
-        ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
-        TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
-        RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
-        SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
-        TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
-        RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
-        RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
-        HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
-        CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
-        CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
-        AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
-        CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
-        CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
-        CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
-        CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
-        AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
-        CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
-        PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
-        VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
-        MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
-        VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
-        MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
-        RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
-        VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
-        VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
-        VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
-        MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
-        VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
-        MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
-        MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
-        IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
-        IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
-        MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
-        ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
-        VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
-        VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
-        VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
-        VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
-        VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
-        ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
-        DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
-        VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
-        ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
-        IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
-        SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
-        TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
-        HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
-        VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
-        TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
-        ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
-        TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
-        VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
-        PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
-        SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
-        VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
-        ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
-        SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
-        SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
-        VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
-        ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
-        SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
-        VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
-        HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
-        MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
-        SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
-        VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
-        DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
-        VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
-        DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
-        VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
-        SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
-        SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
-        VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
-        SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
-        GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
-        VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
-        RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
-        GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-        PINMUX_DATA(AVS1_MARK, FN_AVS1),
-        PINMUX_DATA(AVS1_MARK, FN_AVS1),
-        PINMUX_DATA(A17_MARK, FN_A17),
-        PINMUX_DATA(A18_MARK, FN_A18),
-        PINMUX_DATA(A19_MARK, FN_A19),
-        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP0_2_0, PWM1),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
-        PINMUX_IPSR_DATA(IP0_5_3, BS),
-        PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
-        PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
-        PINMUX_IPSR_DATA(IP0_5_3, FD2),
-        PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
-        PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
-        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
-        PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
-        PINMUX_IPSR_DATA(IP0_7_6, A0),
-        PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
-        PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
-        PINMUX_IPSR_DATA(IP0_7_6, FD3),
-        PINMUX_IPSR_DATA(IP0_9_8, A20),
-        PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
-        PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
-        PINMUX_IPSR_DATA(IP0_11_10, A21),
-        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
-        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, A22),
-        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
-        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
-        PINMUX_IPSR_DATA(IP0_15_14, A23),
-        PINMUX_IPSR_DATA(IP0_15_14, FCLE),
-        PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
-        PINMUX_IPSR_DATA(IP0_18_16, A24),
-        PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
-        PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
-        PINMUX_IPSR_DATA(IP0_18_16, FD4),
-        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
-        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
-        PINMUX_IPSR_DATA(IP0_22_19, A25),
-        PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
-        PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
-        PINMUX_IPSR_DATA(IP0_22_19, FD5),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
-        PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
-        PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
-        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
-        PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
-        PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
-        PINMUX_IPSR_DATA(IP0_25, CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
-        PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
-        PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
-        PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
-        PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
-        PINMUX_IPSR_DATA(IP0_30_28, FWE),
-        PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
-        PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
-        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
-        PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
-        PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
-        PINMUX_IPSR_DATA(IP1_1_0, FD6),
-        PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
-        PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
-        PINMUX_IPSR_DATA(IP1_3_2, FD7),
-        PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
-        PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
-        PINMUX_IPSR_DATA(IP1_6_4, FALE),
-        PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
-        PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
-        PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
-        PINMUX_IPSR_DATA(IP1_10_7, FRE),
-        PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
-        PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
-        PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
-        PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
-        PINMUX_IPSR_DATA(IP1_14_11, FD0),
-        PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
-        PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
-        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
-        PINMUX_IPSR_DATA(IP1_14_11, HTX1),
-        PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
-        PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
-        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
-        PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
-        PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
-        PINMUX_IPSR_DATA(IP1_18_15, FD1),
-        PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
-        PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
-        PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
-        PINMUX_IPSR_DATA(IP1_20_19, PWM2),
-        PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
-        PINMUX_IPSR_DATA(IP1_22_21, PWM3),
-        PINMUX_IPSR_DATA(IP1_22_21, TX4),
-        PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
-        PINMUX_IPSR_DATA(IP1_24_23, PWM4),
-        PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
-        PINMUX_IPSR_DATA(IP1_28_25, HTX0),
-        PINMUX_IPSR_DATA(IP1_28_25, TX1),
-        PINMUX_IPSR_DATA(IP1_28_25, SDATA),
-        PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
-        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
-        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
-        PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
-        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_7_4, MTS),
-        PINMUX_IPSR_DATA(IP2_7_4, PWM5),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
-        PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
-        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_11_8, STM),
-        PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
-        PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
-        PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
-        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
-        PINMUX_IPSR_DATA(IP2_15_12, MDATA),
-        PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
-        PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
-        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
-        PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
-        PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
-        PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
-        PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
-        PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
-        PINMUX_IPSR_DATA(IP2_21_19, DACK0),
-        PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
-        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
-        PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
-        PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
-        PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
-        PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
-        PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
-        PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
-        PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
-        PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
-        PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
-        PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
-        PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
-        PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
-        PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
-        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
-        PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
-        PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
-        PINMUX_IPSR_DATA(IP3_2_0, DACK1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
-        PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
-        PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
-        PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
-        PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
-        PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
-        PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
-        PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
-        PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
-        PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
-        PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
-        PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
-        PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
-        PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
-        PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
-        PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
-        PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
-        PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
-        PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
-        PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
-        PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
-        PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
-        PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
-        PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
-        PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
-        PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
-        PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
-        PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
-        PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
-        PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
-        PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
-        PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
-        PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
-        PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
-        PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
-        PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
-        PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
-        PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
-        PINMUX_IPSR_DATA(IP3_23, QCLK),
-        PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
-        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
-        PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
-        PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
-        PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
-        PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
-        PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
-        PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
-        PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
-        PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
-        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
-        PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
-        PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
-        PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
-        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
-        PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
-        PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
-        PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
-        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
-        PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
-        PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
-        PINMUX_IPSR_DATA(IP4_7_5, PWM6),
-        PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
-        PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
-        PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
-        PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
-        PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
-        PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
-        PINMUX_IPSR_DATA(IP4_10_8, PWM0),
-        PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
-        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
-        PINMUX_IPSR_DATA(IP4_11, VI2_G0),
-        PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
-        PINMUX_IPSR_DATA(IP4_12, VI2_G1),
-        PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
-        PINMUX_IPSR_DATA(IP4_13, VI2_G2),
-        PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
-        PINMUX_IPSR_DATA(IP4_14, VI2_G3),
-        PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
-        PINMUX_IPSR_DATA(IP4_15, VI2_G4),
-        PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
-        PINMUX_IPSR_DATA(IP4_16, VI2_G5),
-        PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
-        PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
-        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
-        PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
-        PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
-        PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
-        PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
-        PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
-        PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
-        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
-        PINMUX_IPSR_DATA(IP4_23, VI2_G6),
-        PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
-        PINMUX_IPSR_DATA(IP4_24, VI2_G7),
-        PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
-        PINMUX_IPSR_DATA(IP4_25, VI2_R0),
-        PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
-        PINMUX_IPSR_DATA(IP4_26, VI2_R1),
-        PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
-        PINMUX_IPSR_DATA(IP4_27, VI2_R2),
-        PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
-        PINMUX_IPSR_DATA(IP4_28, VI2_R3),
-        PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
-        PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
-        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
-        PINMUX_IPSR_DATA(IP4_31_29, TX5),
-        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
-        PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
-        PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
-        PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
-        PINMUX_IPSR_DATA(IP5_3, VI2_R4),
-        PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
-        PINMUX_IPSR_DATA(IP5_4, VI2_R5),
-        PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
-        PINMUX_IPSR_DATA(IP5_5, VI2_R6),
-        PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
-        PINMUX_IPSR_DATA(IP5_6, VI2_R7),
-        PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
-        PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
-        PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
-        PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
-        PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
-        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
-        PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
-        PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
-        PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
-        PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
-        PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
-        PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
-        PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
-        PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
-        PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
-        PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
-        PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
-        PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
-        PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
-        PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
-        PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
-        PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
-        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
-        PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
-        PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
-        PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
-        PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
-        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
-        PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
-        PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
-        PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
-        PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
-        PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
-        PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
-        PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
-        PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
-        PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
-        PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
-        PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
-        PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
-        PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
-        PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
-        PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
-        PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
-        PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
-        PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
-        PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
-        PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
-        PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
-        PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
-        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
-        PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
-        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
-        PINMUX_IPSR_DATA(IP6_14_12, IETX),
-        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
-        PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
-        PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
-        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
-        PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
-        PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
-        PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
-        PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
-        PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
-        PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
-        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
-        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
-        PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
-        PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
-        PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
-        PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
-        PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
-        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
-        PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
-        PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
-        PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
-        PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
-        PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
-        PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
-        PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
-        PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
-        PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
-        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
-        PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
-        PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
-        PINMUX_IPSR_DATA(IP7_14_13, VSP),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
-        PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
-        PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
-        PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
-        PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
-        PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
-        PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
-        PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
-        PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
-        PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
-        PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
-        PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
-        PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
-        PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
-        PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
-        PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
-        PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
-        PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
-        PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
-        PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
-        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
-        PINMUX_IPSR_DATA(IP7_30_29, DACK2),
-        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
-        PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
-        PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
-        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
-        PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
-        PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
-        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
-        PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, TX0),
-        PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
-        PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
-        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
-        PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
-        PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
-        PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
-        PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
-        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
-        PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
-        PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
-        PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
-        PINMUX_IPSR_DATA(IP8_18, BPFCLK),
-        PINMUX_IPSR_DATA(IP8_18, PCMWE),
-        PINMUX_IPSR_DATA(IP8_19, FMIN),
-        PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
-        PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
-        PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
-        PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
-        PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
-        PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
-        PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
-        PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
-        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
-        PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
-        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
-        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
-        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
-        PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
-        PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
-        PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
-        PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
-        PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
-        PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
-        PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
-        PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
-        PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
-        PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
-        PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
-        PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
-        PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
-        PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
-        PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
-        PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
-        PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
-        PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
-        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
-        PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
-        PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
-        PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
-        PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
-        PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
-        PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
-        PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
-        PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
-        PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
-        PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
-        PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
-        PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
-        PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
-        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
-        PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
-        PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
-        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
-        PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
-        PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
-        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
-        PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
-        PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
-        PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
-        PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
-        PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
-        PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
-        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
-        PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
-        PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
-        PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
-        PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
-        PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
-        PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
-        PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
-        PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
-        PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
-        PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
-        PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
-        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
-        PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
-        PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
-        PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
-        PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
-        PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
-        PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
-        PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
-        PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
-        PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
-        PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
-        PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
-        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
-        PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
-        PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
-        PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
-        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
-        PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
-        PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
-        PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
-        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
-        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
-        PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
-        PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
-        PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
-        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
-        PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
-        PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
-        PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
-        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
-        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
-        PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
-        PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
-        PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
-        PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
-        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
-        PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
-        PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
-        PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
-        PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
-        PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
-        PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
-        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
-        PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
-        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
-        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
-        PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
-        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
-        PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
-        PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
-        PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
-        PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
-        PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
-        PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
-        PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
-        PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
-        PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
-        PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
-        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
-        PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
-        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
-        PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
-        PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
-        PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
-        PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
-        PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
-        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
-        PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
-        PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
-        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
-        PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
-        PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
-        PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
-        PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
-        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
-        PINMUX_IPSR_DATA(IP11_26_24, TX2),
-        PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
-        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
-        PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
-        PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
-        PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
-        PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
-        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
-        PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
-        PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
-        PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
-        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
-        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
-        PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
-        PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
-        PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
-        PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
-        PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
-        PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
-        PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
-        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
-        PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
-        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
-        PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
-        PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
-        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_11_9, FSE),
-        PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
-        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
-        PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
-        PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
-        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_14_12, FRB),
-        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
-        PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
-        PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
-        PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
-        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
-        PINMUX_IPSR_DATA(IP12_17_15, FCE),
-        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        PINMUX_GPIO_GP_ALL(),
-        GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
-        GPIO_FN(A19),
-        /* IPSR0 */
-        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
-        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
-        GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
-        GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
-        GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
-        GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
-        GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
-        GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
-        GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
-        GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
-        GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
-        GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
-        GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
-        GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
-        GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
-        GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
-        GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
-        /* IPSR1 */
-        GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
-        GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
-        GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
-        GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
-        GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
-        GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
-        GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
-        GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
-        GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
-        GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
-        GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
-        GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
-        GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
-        GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
-        GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
-        GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
-        GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
-        GPIO_FN(CC5_STATE34),
-        /* IPSR2 */
-        GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
-        GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
-        GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
-        GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
-        GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
-        GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
-        GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
-        GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
-        GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
-        GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
-        GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
-        GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
-        GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
-        GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
-        GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
-        GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
-        GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
-        GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
-        GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
-        GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
-        GPIO_FN(AUDATA2),
-        /* IPSR3 */
-        GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
-        GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
-        GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
-        GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
-        GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
-        GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
-        GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
-        GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
-        GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
-        GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
-        GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
-        GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
-        GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
-        GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
-        GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
-        GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
-        GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
-        GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
-        GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
-        GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
-        GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
-        /* IPSR4 */
-        GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
-        GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
-        GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
-        GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
-        GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
-        GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
-        GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
-        GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
-        GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
-        GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
-        GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
-        GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
-        GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
-        GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
-        GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
-        GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
-        GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
-        GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
-        GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
-        GPIO_FN(TX5), GPIO_FN(SCK0_D),
-        /* IPSR5 */
-        GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
-        GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
-        GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
-        GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
-        GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
-        GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
-        GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
-        GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
-        GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
-        GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
-        GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
-        GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
-        GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
-        GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
-        GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
-        GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
-        GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
-        GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
-        GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
-        GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
-        GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
-        /* IPSR6 */
-        GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
-        GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
-        GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
-        GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
-        GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
-        GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
-        GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
-        GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
-        GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
-        GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
-        GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
-        GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
-        GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
-        GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
-        GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
-        GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
-        GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
-        /* IPSR7 */
-        GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
-        GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
-        GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
-        GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
-        GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
-        GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
-        GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
-        GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
-        GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
-        GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
-        GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
-        GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
-        GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
-        GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
-        GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
-        GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
-        GPIO_FN(CTS1_B),
-        /* IPSR8 */
-        GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
-        GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
-        GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
-        GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
-        GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
-        GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
-        GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
-        GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
-        GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
-        GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
-        GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
-        GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
-        GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
-        GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
-        GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
-        GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
-        GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
-        GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
-        GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
-        GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
-        /* IPSR9 */
-        GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
-        GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
-        GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
-        GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
-        GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
-        GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
-        GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
-        GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
-        GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
-        GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
-        GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
-        GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
-        GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
-        GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
-        GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
-        GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
-        GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
-        GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
-        /* IPSR10 */
-        GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
-        GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
-        GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
-        GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
-        GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
-        GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
-        GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
-        GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
-        GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
-        GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
-        GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
-        GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
-        GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
-        GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
-        GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
-        GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
-        GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
-        GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
-        GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
-        GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
-        GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
-        /* IPSR11 */
-        GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
-        GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
-        GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
-        GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
-        GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
-        GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
-        GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
-        GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
-        GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
-        GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
-        GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
-        GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
-        GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
-        GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
-        GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
-        GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
-        GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
-        GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
-        GPIO_FN(HRTS0_B),
-        /* IPSR12 */
-        GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
-        GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
-        GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
-        GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
-        GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
-        GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
-        GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
-        GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
-        GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
-        GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
-                GP_0_31_FN, FN_IP3_31_29,
-                GP_0_30_FN, FN_IP3_26_24,
-                GP_0_29_FN, FN_IP3_22_21,
-                GP_0_28_FN, FN_IP3_14_12,
-                GP_0_27_FN, FN_IP3_11_9,
-                GP_0_26_FN, FN_IP3_2_0,
-                GP_0_25_FN, FN_IP2_30_28,
-                GP_0_24_FN, FN_IP2_21_19,
-                GP_0_23_FN, FN_IP2_18_16,
-                GP_0_22_FN, FN_IP0_30_28,
-                GP_0_21_FN, FN_IP0_5_3,
-                GP_0_20_FN, FN_IP1_18_15,
-                GP_0_19_FN, FN_IP1_14_11,
-                GP_0_18_FN, FN_IP1_10_7,
-                GP_0_17_FN, FN_IP1_6_4,
-                GP_0_16_FN, FN_IP1_3_2,
-                GP_0_15_FN, FN_IP1_1_0,
-                GP_0_14_FN, FN_IP0_27_26,
-                GP_0_13_FN, FN_IP0_25,
-                GP_0_12_FN, FN_IP0_24_23,
-                GP_0_11_FN, FN_IP0_22_19,
-                GP_0_10_FN, FN_IP0_18_16,
-                GP_0_9_FN, FN_IP0_15_14,
-                GP_0_8_FN, FN_IP0_13_12,
-                GP_0_7_FN, FN_IP0_11_10,
-                GP_0_6_FN, FN_IP0_9_8,
-                GP_0_5_FN, FN_A19,
-                GP_0_4_FN, FN_A18,
-                GP_0_3_FN, FN_A17,
-                GP_0_2_FN, FN_IP0_7_6,
-                GP_0_1_FN, FN_AVS2,
-                GP_0_0_FN, FN_AVS1 }
-        },
-        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
-                GP_1_31_FN, FN_IP5_23_21,
-                GP_1_30_FN, FN_IP5_20_17,
-                GP_1_29_FN, FN_IP5_16_15,
-                GP_1_28_FN, FN_IP5_14_13,
-                GP_1_27_FN, FN_IP5_12_11,
-                GP_1_26_FN, FN_IP5_10_9,
-                GP_1_25_FN, FN_IP5_8,
-                GP_1_24_FN, FN_IP5_7,
-                GP_1_23_FN, FN_IP5_6,
-                GP_1_22_FN, FN_IP5_5,
-                GP_1_21_FN, FN_IP5_4,
-                GP_1_20_FN, FN_IP5_3,
-                GP_1_19_FN, FN_IP5_2_0,
-                GP_1_18_FN, FN_IP4_31_29,
-                GP_1_17_FN, FN_IP4_28,
-                GP_1_16_FN, FN_IP4_27,
-                GP_1_15_FN, FN_IP4_26,
-                GP_1_14_FN, FN_IP4_25,
-                GP_1_13_FN, FN_IP4_24,
-                GP_1_12_FN, FN_IP4_23,
-                GP_1_11_FN, FN_IP4_22_20,
-                GP_1_10_FN, FN_IP4_19_17,
-                GP_1_9_FN, FN_IP4_16,
-                GP_1_8_FN, FN_IP4_15,
-                GP_1_7_FN, FN_IP4_14,
-                GP_1_6_FN, FN_IP4_13,
-                GP_1_5_FN, FN_IP4_12,
-                GP_1_4_FN, FN_IP4_11,
-                GP_1_3_FN, FN_IP4_10_8,
-                GP_1_2_FN, FN_IP4_7_5,
-                GP_1_1_FN, FN_IP4_4_2,
-                GP_1_0_FN, FN_IP4_1_0 }
-        },
-        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
-                GP_2_31_FN, FN_IP10_28_26,
-                GP_2_30_FN, FN_IP10_25_24,
-                GP_2_29_FN, FN_IP10_23_21,
-                GP_2_28_FN, FN_IP10_20_18,
-                GP_2_27_FN, FN_IP10_17_15,
-                GP_2_26_FN, FN_IP10_14_12,
-                GP_2_25_FN, FN_IP10_11_9,
-                GP_2_24_FN, FN_IP10_8_6,
-                GP_2_23_FN, FN_IP10_5_3,
-                GP_2_22_FN, FN_IP10_2_0,
-                GP_2_21_FN, FN_IP9_29_28,
-                GP_2_20_FN, FN_IP9_27_26,
-                GP_2_19_FN, FN_IP9_25_24,
-                GP_2_18_FN, FN_IP9_23_22,
-                GP_2_17_FN, FN_IP9_21_19,
-                GP_2_16_FN, FN_IP9_18_16,
-                GP_2_15_FN, FN_IP9_15_14,
-                GP_2_14_FN, FN_IP9_13_12,
-                GP_2_13_FN, FN_IP9_11_10,
-                GP_2_12_FN, FN_IP9_9_8,
-                GP_2_11_FN, FN_IP9_7,
-                GP_2_10_FN, FN_IP9_6,
-                GP_2_9_FN, FN_IP9_5,
-                GP_2_8_FN, FN_IP9_4,
-                GP_2_7_FN, FN_IP9_3_2,
-                GP_2_6_FN, FN_IP9_1_0,
-                GP_2_5_FN, FN_IP8_30_28,
-                GP_2_4_FN, FN_IP8_27_25,
-                GP_2_3_FN, FN_IP8_24_23,
-                GP_2_2_FN, FN_IP8_22_21,
-                GP_2_1_FN, FN_IP8_20,
-                GP_2_0_FN, FN_IP5_27_24 }
-        },
-        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
-                GP_3_31_FN, FN_IP6_3_2,
-                GP_3_30_FN, FN_IP6_1_0,
-                GP_3_29_FN, FN_IP5_30_29,
-                GP_3_28_FN, FN_IP5_28,
-                GP_3_27_FN, FN_IP1_24_23,
-                GP_3_26_FN, FN_IP1_22_21,
-                GP_3_25_FN, FN_IP1_20_19,
-                GP_3_24_FN, FN_IP7_26_25,
-                GP_3_23_FN, FN_IP7_24_23,
-                GP_3_22_FN, FN_IP7_22_21,
-                GP_3_21_FN, FN_IP7_20_19,
-                GP_3_20_FN, FN_IP7_30_29,
-                GP_3_19_FN, FN_IP7_28_27,
-                GP_3_18_FN, FN_IP7_18_17,
-                GP_3_17_FN, FN_IP7_16_15,
-                GP_3_16_FN, FN_IP12_17_15,
-                GP_3_15_FN, FN_IP12_14_12,
-                GP_3_14_FN, FN_IP12_11_9,
-                GP_3_13_FN, FN_IP12_8_6,
-                GP_3_12_FN, FN_IP12_5_3,
-                GP_3_11_FN, FN_IP12_2_0,
-                GP_3_10_FN, FN_IP11_29_27,
-                GP_3_9_FN, FN_IP11_26_24,
-                GP_3_8_FN, FN_IP11_23_21,
-                GP_3_7_FN, FN_IP11_20_18,
-                GP_3_6_FN, FN_IP11_17_15,
-                GP_3_5_FN, FN_IP11_14_12,
-                GP_3_4_FN, FN_IP11_11_9,
-                GP_3_3_FN, FN_IP11_8_6,
-                GP_3_2_FN, FN_IP11_5_3,
-                GP_3_1_FN, FN_IP11_2_0,
-                GP_3_0_FN, FN_IP10_31_29 }
-        },
-        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
-                GP_4_31_FN, FN_IP8_19,
-                GP_4_30_FN, FN_IP8_18,
-                GP_4_29_FN, FN_IP8_17_16,
-                GP_4_28_FN, FN_IP0_2_0,
-                GP_4_27_FN, FN_USB_PENC1,
-                GP_4_26_FN, FN_USB_PENC0,
-                GP_4_25_FN, FN_IP8_15_12,
-                GP_4_24_FN, FN_IP8_11_8,
-                GP_4_23_FN, FN_IP8_7_4,
-                GP_4_22_FN, FN_IP8_3_0,
-                GP_4_21_FN, FN_IP2_3_0,
-                GP_4_20_FN, FN_IP1_28_25,
-                GP_4_19_FN, FN_IP2_15_12,
-                GP_4_18_FN, FN_IP2_11_8,
-                GP_4_17_FN, FN_IP2_7_4,
-                GP_4_16_FN, FN_IP7_14_13,
-                GP_4_15_FN, FN_IP7_12_10,
-                GP_4_14_FN, FN_IP7_9_7,
-                GP_4_13_FN, FN_IP7_6_4,
-                GP_4_12_FN, FN_IP7_3_2,
-                GP_4_11_FN, FN_IP7_1_0,
-                GP_4_10_FN, FN_IP6_30_29,
-                GP_4_9_FN, FN_IP6_26_25,
-                GP_4_8_FN, FN_IP6_24_23,
-                GP_4_7_FN, FN_IP6_22_20,
-                GP_4_6_FN, FN_IP6_19_18,
-                GP_4_5_FN, FN_IP6_17_15,
-                GP_4_4_FN, FN_IP6_14_12,
-                GP_4_3_FN, FN_IP6_11_9,
-                GP_4_2_FN, FN_IP6_8,
-                GP_4_1_FN, FN_IP6_7_6,
-                GP_4_0_FN, FN_IP6_5_4 }
-        },
-        { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
-                GP_5_31_FN, FN_IP3_5,
-                GP_5_30_FN, FN_IP3_4,
-                GP_5_29_FN, FN_IP3_3,
-                GP_5_28_FN, FN_IP2_27,
-                GP_5_27_FN, FN_IP2_26,
-                GP_5_26_FN, FN_IP2_25,
-                GP_5_25_FN, FN_IP2_24,
-                GP_5_24_FN, FN_IP2_23,
-                GP_5_23_FN, FN_IP2_22,
-                GP_5_22_FN, FN_IP3_28,
-                GP_5_21_FN, FN_IP3_27,
-                GP_5_20_FN, FN_IP3_23,
-                GP_5_19_FN, FN_EX_WAIT0,
-                GP_5_18_FN, FN_WE1,
-                GP_5_17_FN, FN_WE0,
-                GP_5_16_FN, FN_RD,
-                GP_5_15_FN, FN_A16,
-                GP_5_14_FN, FN_A15,
-                GP_5_13_FN, FN_A14,
-                GP_5_12_FN, FN_A13,
-                GP_5_11_FN, FN_A12,
-                GP_5_10_FN, FN_A11,
-                GP_5_9_FN, FN_A10,
-                GP_5_8_FN, FN_A9,
-                GP_5_7_FN, FN_A8,
-                GP_5_6_FN, FN_A7,
-                GP_5_5_FN, FN_A6,
-                GP_5_4_FN, FN_A5,
-                GP_5_3_FN, FN_A4,
-                GP_5_2_FN, FN_A3,
-                GP_5_1_FN, FN_A2,
-                GP_5_0_FN, FN_A1 }
-        },
-        { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                GP_6_8_FN, FN_IP3_20,
-                GP_6_7_FN, FN_IP3_19,
-                GP_6_6_FN, FN_IP3_18,
-                GP_6_5_FN, FN_IP3_17,
-                GP_6_4_FN, FN_IP3_16,
-                GP_6_3_FN, FN_IP3_15,
-                GP_6_2_FN, FN_IP3_8,
-                GP_6_1_FN, FN_IP3_7,
-                GP_6_0_FN, FN_IP3_6 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
-                             1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
-                /* IP0_31 [1] */
-                0, 0,
-                /* IP0_30_28 [3] */
-                FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
-                FN_HRTS1, FN_RX4_C, 0, 0,
-                /* IP0_27_26 [2] */
-                FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
-                /* IP0_25 [1] */
-                FN_CS0, FN_HSPI_CS2_B,
-                /* IP0_24_23 [2] */
-                FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
-                /* IP0_22_19 [4] */
-                FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
-                FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
-                FN_CTS0_B, 0, 0, 0,
-                0, 0, 0, 0,
-                /* IP0_18_16 [3] */
-                FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
-                FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
-                /* IP0_15_14 [2] */
-                FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
-                /* IP0_13_12 [2] */
-                FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
-                /* IP0_11_10 [2] */
-                FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
-                /* IP0_9_8 [2] */
-                FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
-                /* IP0_7_6 [2] */
-                FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
-                /* IP0_5_3 [3] */
-                FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
-                FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-                /* IP0_2_0 [3] */
-                FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
-                FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-                             3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
-                /* IP1_31_29 [3] */
-                0, 0, 0, 0, 0, 0, 0, 0,
-                /* IP1_28_25 [4] */
-                FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
-                FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
-                FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
-                0, 0, 0, 0,
-                /* IP1_24_23 [2] */
-                FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
-                /* IP1_22_21 [2] */
-                FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
-                /* IP1_20_19 [2] */
-                FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
-                /* IP1_18_15 [4] */
-                FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
-                FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
-                FN_RX0_B, FN_SSI_WS9, 0, 0,
-                0, 0, 0, 0,
-                /* IP1_14_11 [4] */
-                FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
-                FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
-                FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
-                0, 0, 0, 0,
-                /* IP1_10_7 [4] */
-                FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
-                FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
-                FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
-                0, 0, 0, 0,
-                /* IP1_6_4 [3] */
-                FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
-                FN_ATACS00, 0, 0, 0,
-                /* IP1_3_2 [2] */
-                FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
-                /* IP1_1_0 [2] */
-                FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
-                             1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
-                /* IP2_31 [1] */
-                0, 0,
-                /* IP2_30_28 [3] */
-                FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
-                FN_AUDATA2, 0, 0, 0,
-                /* IP2_27 [1] */
-                FN_DU0_DR7, FN_LCDOUT7,
-                /* IP2_26 [1] */
-                FN_DU0_DR6, FN_LCDOUT6,
-                /* IP2_25 [1] */
-                FN_DU0_DR5, FN_LCDOUT5,
-                /* IP2_24 [1] */
-                FN_DU0_DR4, FN_LCDOUT4,
-                /* IP2_23 [1] */
-                FN_DU0_DR3, FN_LCDOUT3,
-                /* IP2_22 [1] */
-                FN_DU0_DR2, FN_LCDOUT2,
-                /* IP2_21_19 [3] */
-                FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
-                FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
-                /* IP2_18_16 [3] */
-                FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
-                FN_AUDATA0, FN_TX5_C, 0, 0,
-                /* IP2_15_12 [4] */
-                FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
-                FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
-                FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
-                0, 0, 0, 0,
-                /* IP2_11_8 [4] */
-                FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
-                FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
-                FN_CC5_OSCOUT, 0, 0, 0,
-                0, 0, 0, 0,
-                /* IP2_7_4 [4] */
-                FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
-                FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
-                FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
-                0, 0, 0, 0,
-                /* IP2_3_0 [4] */
-                FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
-                FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
-                FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
-                0, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
-                             3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
-                             1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
-            /* IP3_31_29 [3] */
-            FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
-            FN_SCL2_C, FN_REMOCON, 0, 0,
-            /* IP3_28 [1] */
-            FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
-            /* IP3_27 [1] */
-            FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
-            /* IP3_26_24 [3] */
-            FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
-            FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
-            /* IP3_23 [1] */
-            FN_DU0_DOTCLKOUT0, FN_QCLK,
-            /* IP3_22_21 [2] */
-            FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
-            /* IP3_20 [1] */
-            FN_DU0_DB7, FN_LCDOUT23,
-            /* IP3_19 [1] */
-            FN_DU0_DB6, FN_LCDOUT22,
-            /* IP3_18 [1] */
-            FN_DU0_DB5, FN_LCDOUT21,
-            /* IP3_17 [1] */
-            FN_DU0_DB4, FN_LCDOUT20,
-            /* IP3_16 [1] */
-            FN_DU0_DB3, FN_LCDOUT19,
-            /* IP3_15 [1] */
-            FN_DU0_DB2, FN_LCDOUT18,
-            /* IP3_14_12 [3] */
-            FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
-            FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
-            /* IP3_11_9 [3] */
-            FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
-            FN_TCLK1, FN_AUDATA4, 0, 0,
-            /* IP3_8 [1] */
-            FN_DU0_DG7, FN_LCDOUT15,
-            /* IP3_7 [1] */
-            FN_DU0_DG6, FN_LCDOUT14,
-            /* IP3_6 [1] */
-            FN_DU0_DG5, FN_LCDOUT13,
-            /* IP3_5 [1] */
-            FN_DU0_DG4, FN_LCDOUT12,
-            /* IP3_4 [1] */
-            FN_DU0_DG3, FN_LCDOUT11,
-            /* IP3_3 [1] */
-            FN_DU0_DG2, FN_LCDOUT10,
-            /* IP3_2_0 [3] */
-            FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
-            FN_AUDATA3, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
-                             3, 1, 1, 1, 1, 1, 1, 3, 3,
-                             1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
-            /* IP4_31_29 [3] */
-            FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
-            FN_TX5, FN_SCK0_D, 0, 0,
-            /* IP4_28 [1] */
-            FN_DU1_DG7, FN_VI2_R3,
-            /* IP4_27 [1] */
-            FN_DU1_DG6, FN_VI2_R2,
-            /* IP4_26 [1] */
-            FN_DU1_DG5, FN_VI2_R1,
-            /* IP4_25 [1] */
-            FN_DU1_DG4, FN_VI2_R0,
-            /* IP4_24 [1] */
-            FN_DU1_DG3, FN_VI2_G7,
-            /* IP4_23 [1] */
-            FN_DU1_DG2, FN_VI2_G6,
-            /* IP4_22_20 [3] */
-            FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
-            FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
-            /* IP4_19_17 [3] */
-            FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
-            FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
-            /* IP4_16 [1] */
-            FN_DU1_DR7, FN_VI2_G5,
-            /* IP4_15 [1] */
-            FN_DU1_DR6, FN_VI2_G4,
-            /* IP4_14 [1] */
-            FN_DU1_DR5, FN_VI2_G3,
-            /* IP4_13 [1] */
-            FN_DU1_DR4, FN_VI2_G2,
-            /* IP4_12 [1] */
-            FN_DU1_DR3, FN_VI2_G1,
-            /* IP4_11 [1] */
-            FN_DU1_DR2, FN_VI2_G0,
-            /* IP4_10_8 [3] */
-            FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
-            FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
-            /* IP4_7_5 [3] */
-            FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
-            FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
-            /* IP4_4_2 [3] */
-            FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
-            FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
-            /* IP4_1_0 [2] */
-            FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
-                             1, 2, 1, 4, 3, 4, 2, 2,
-                             2, 2, 1, 1, 1, 1, 1, 1, 3) {
-            /* IP5_31 [1] */
-            0, 0,
-            /* IP5_30_29 [2] */
-            FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
-            /* IP5_28 [1] */
-            FN_AUDIO_CLKA, FN_CAN_TXCLK,
-            /* IP5_27_24 [4] */
-            FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
-            FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
-            FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
-            0, 0, 0, 0,
-            /* IP5_23_21 [3] */
-            FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
-            FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
-            /* IP5_20_17 [4] */
-            FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
-            FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
-            FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
-            0, 0, 0, 0,
-            /* IP5_16_15 [2] */
-            FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
-            /* IP5_14_13 [2] */
-            FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
-            /* IP5_12_11 [2] */
-            FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
-            /* IP5_10_9 [2] */
-            FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
-            /* IP5_8 [1] */
-            FN_DU1_DB7, FN_SDA2_D,
-            /* IP5_7 [1] */
-            FN_DU1_DB6, FN_SCL2_D,
-            /* IP5_6 [1] */
-            FN_DU1_DB5, FN_VI2_R7,
-            /* IP5_5 [1] */
-            FN_DU1_DB4, FN_VI2_R6,
-            /* IP5_4 [1] */
-            FN_DU1_DB3, FN_VI2_R5,
-            /* IP5_3 [1] */
-            FN_DU1_DB2, FN_VI2_R4,
-            /* IP5_2_0 [3] */
-            FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
-            FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
-                             1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
-            /* IP6_31 [1] */
-            0, 0,
-            /* IP6_30_29 [2] */
-            FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
-            /* IP_28_27 [2] */
-            0, 0, 0, 0,
-            /* IP6_26_25 [2] */
-            FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
-            /* IP6_24_23 [2] */
-            FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
-            /* IP6_22_20 [3] */
-            FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
-            FN_TCLK0_D, 0, 0, 0,
-            /* IP6_19_18 [2] */
-            FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
-            /* IP6_17_15 [3] */
-            FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
-            FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
-            /* IP6_14_12 [3] */
-            FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
-            FN_SSI_WS9_C, 0, 0, 0,
-            /* IP6_11_9 [3] */
-            FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
-            FN_SSI_SCK9_C, 0, 0, 0,
-            /* IP6_8 [1] */
-            FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
-            /* IP6_7_6 [2] */
-            FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
-            /* IP6_5_4 [2] */
-            FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
-            /* IP6_3_2 [2] */
-            FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
-            /* IP6_1_0 [2] */
-            FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
-                             1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
-            /* IP7_31 [1] */
-            0, 0,
-            /* IP7_30_29 [2] */
-            FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
-            /* IP7_28_27 [2] */
-            FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
-            /* IP7_26_25 [2] */
-            FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
-            /* IP7_24_23 [2] */
-            FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
-            /* IP7_22_21 [2] */
-            FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
-            /* IP7_20_19 [2] */
-            FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
-            /* IP7_18_17 [2] */
-            FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
-            /* IP7_16_15 [2] */
-            FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
-            /* IP7_14_13 [2] */
-            FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
-            /* IP7_12_10 [3] */
-            FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
-            FN_HSPI_TX1_C, 0, 0, 0,
-            /* IP7_9_7 [3] */
-            FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
-            FN_HSPI_CS1_C, 0, 0, 0,
-            /* IP7_6_4 [3] */
-            FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
-            FN_HSPI_CLK1_C, 0, 0, 0,
-            /* IP7_3_2 [2] */
-            FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
-            /* IP7_1_0 [2] */
-            FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
-                             1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
-            /* IP8_31 [1] */
-            0, 0,
-            /* IP8_30_28 [3] */
-            FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
-            FN_PWMFSW0_C, 0, 0, 0,
-            /* IP8_27_25 [3] */
-            FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
-            FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
-            /* IP8_24_23 [2] */
-            FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
-            /* IP8_22_21 [2] */
-            FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
-            /* IP8_20 [1] */
-            FN_VI0_CLK, FN_MMC1_CLK,
-            /* IP8_19 [1] */
-            FN_FMIN, FN_RDS_DATA,
-            /* IP8_18 [1] */
-            FN_BPFCLK, FN_PCMWE,
-            /* IP8_17_16 [2] */
-            FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
-            /* IP8_15_12 [4] */
-            FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
-            FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
-            FN_CC5_STATE39, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_11_8 [4] */
-            FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
-            FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
-            FN_CC5_STATE38, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_7_4 [4] */
-            FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
-            FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
-            FN_CC5_STATE37, 0, 0, 0,
-            0, 0, 0, 0,
-            /* IP8_3_0 [4] */
-            FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
-            FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
-            FN_CC5_STATE36, 0, 0, 0,
-            0, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
-                             2, 2, 2, 2, 2, 3, 3, 2, 2,
-                             2, 2, 1, 1, 1, 1, 2, 2) {
-            /* IP9_31_30 [2] */
-            0, 0, 0, 0,
-            /* IP9_29_28 [2] */
-            FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
-            /* IP9_27_26 [2] */
-            FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
-            /* IP9_25_24 [2] */
-            FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
-            /* IP9_23_22 [2] */
-            FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
-            /* IP9_21_19 [3] */
-            FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
-            FN_TS_SDAT0, 0, 0, 0,
-            /* IP9_18_16 [3] */
-            FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
-            FN_TS_SPSYNC0, 0, 0, 0,
-            /* IP9_15_14 [2] */
-            FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
-            /* IP9_13_12 [2] */
-            FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
-            /* IP9_11_10 [2] */
-            FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
-            /* IP9_9_8 [2] */
-            FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
-            /* IP9_7 [1] */
-            FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
-            /* IP9_6 [1] */
-            FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
-            /* IP9_5 [1] */
-            FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
-            /* IP9_4 [1] */
-            FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
-            /* IP9_3_2 [2] */
-            FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
-            /* IP9_1_0 [2] */
-            FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
-                             3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
-            /* IP10_31_29 [3] */
-            FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
-            FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
-            /* IP10_28_26 [3] */
-            FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
-            FN_PWMFSW0_E, 0, 0, 0,
-            /* IP10_25_24 [2] */
-            FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
-            /* IP10_23_21 [3] */
-            FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
-            FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
-            /* IP10_20_18 [3] */
-            FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
-            FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
-            /* IP10_17_15 [3] */
-            FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
-            FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
-            /* IP10_14_12 [3] */
-            FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
-            FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
-            /* IP10_11_9 [3] */
-            FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
-            FN_ARM_TRACEDATA_13, 0, 0, 0,
-            /* IP10_8_6 [3] */
-            FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
-            FN_ARM_TRACEDATA_12, 0, 0, 0,
-            /* IP10_5_3 [3] */
-            FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
-            FN_DACK0_C, FN_DRACK0_C, 0, 0,
-            /* IP10_2_0 [3] */
-            FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
-            FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
-                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
-            /* IP11_31_30 [2] */
-            0, 0, 0, 0,
-            /* IP11_29_27 [3] */
-            FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
-            FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
-            /* IP11_26_24 [3] */
-            FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
-            FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
-            /* IP11_23_21 [3] */
-            FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
-            FN_HSPI_RX1_D, 0, 0, 0,
-            /* IP11_20_18 [3] */
-            FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
-            FN_HSPI_TX1_D, 0, 0, 0,
-            /* IP11_17_15 [3] */
-            FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
-            FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
-            /* IP11_14_12 [3] */
-            FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
-            FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
-            /* IP11_11_9 [3] */
-            FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
-            FN_ADICHS0_B, 0, 0, 0,
-            /* IP11_8_6 [3] */
-            FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
-            FN_ADIDATA_B, 0, 0, 0,
-            /* IP11_5_3 [3] */
-            FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
-            FN_ADICS_B_SAMP_B, 0, 0, 0,
-            /* IP11_2_0 [3] */
-            FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
-            FN_ADICLK_B, 0, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
-                             4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
-            /* IP12_31_28 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_27_24 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_23_20 [4] */
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            /* IP12_19_18 [2] */
-            0, 0, 0, 0,
-            /* IP12_17_15 [3] */
-            FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
-            FN_SCK4_B, 0, 0, 0,
-            /* IP12_14_12 [3] */
-            FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
-            FN_RX4_B, FN_SIM_CLK_B, 0, 0,
-            /* IP12_11_9 [3] */
-            FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
-            FN_TX4_B, FN_SIM_D_B, 0, 0,
-            /* IP12_8_6 [3] */
-            FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
-            FN_SIM_RST_B, FN_HRX0_B, 0, 0,
-            /* IP12_5_3 [3] */
-            FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
-            FN_SCL1_C, FN_HTX0_B, 0, 0,
-            /* IP12_2_0 [3] */
-            FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
-            FN_SCK2, FN_HSCK0_B, 0, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
-                             2, 2, 3, 3, 2, 2, 2, 2, 2,
-                             1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
-            /* SEL_SCIF5 [2] */
-            FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
-            /* SEL_SCIF4 [2] */
-            FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
-            /* SEL_SCIF3 [3] */
-            FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
-            FN_SEL_SCIF3_4, 0, 0, 0,
-            /* SEL_SCIF2 [3] */
-            FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
-            FN_SEL_SCIF2_4, 0, 0, 0,
-            /* SEL_SCIF1 [2] */
-            FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
-            /* SEL_SCIF0 [2] */
-            FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
-            /* SEL_SSI9 [2] */
-            FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
-            /* SEL_SSI8 [2] */
-            FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
-            /* SEL_SSI7 [2] */
-            FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
-            /* SEL_VI0 [1] */
-            FN_SEL_VI0_0, FN_SEL_VI0_1,
-            /* SEL_SD2 [1] */
-            FN_SEL_SD2_0, FN_SEL_SD2_1,
-            /* SEL_INT3 [1] */
-            FN_SEL_INT3_0, FN_SEL_INT3_1,
-            /* SEL_INT2 [1] */
-            FN_SEL_INT2_0, FN_SEL_INT2_1,
-            /* SEL_INT1 [1] */
-            FN_SEL_INT1_0, FN_SEL_INT1_1,
-            /* SEL_INT0 [1] */
-            FN_SEL_INT0_0, FN_SEL_INT0_1,
-            /* SEL_IE [1] */
-            FN_SEL_IE_0, FN_SEL_IE_1,
-            /* SEL_EXBUS2 [2] */
-            FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
-            /* SEL_EXBUS1 [1] */
-            FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
-            /* SEL_EXBUS0 [2] */
-            FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
-        },
-        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
-                             2, 2, 2, 2, 1, 1, 1, 3, 1,
-                             2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
-            /* SEL_TMU1 [2] */
-            FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
-            /* SEL_TMU0 [2] */
-            FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
-            /* SEL_SCIF [2] */
-            FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
-            /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
-            /* SEL_CAN0 [1] */
-            FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-            /* SEL_HSCIF1 [1] */
-            FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-            /* SEL_HSCIF0 [1] */
-            FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-            /* SEL_PWMFSW [3] */
-            FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
-            FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
-            /* SEL_ADI [1] */
-            FN_SEL_ADI_0, FN_SEL_ADI_1,
-            /* [2] */
-            0, 0, 0, 0,
-            /* [2] */
-            0, 0, 0, 0,
-            /* [2] */
-            0, 0, 0, 0,
-            /* SEL_GPS [2] */
-            FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
-            /* SEL_SIM [1] */
-            FN_SEL_SIM_0, FN_SEL_SIM_1,
-            /* SEL_HSPI2 [1] */
-            FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
-            /* SEL_HSPI1 [2] */
-            FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
-            /* SEL_I2C3 [1] */
-            FN_SEL_I2C3_0, FN_SEL_I2C3_1,
-            /* SEL_I2C2 [2] */
-            FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
-            /* SEL_I2C1 [2] */
-            FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
-        },
-        { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
-        { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
-        { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
-        { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
-        { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
-        { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
-        { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                GP_6_8_IN, GP_6_8_OUT,
-                GP_6_7_IN, GP_6_7_OUT,
-                GP_6_6_IN, GP_6_6_OUT,
-                GP_6_5_IN, GP_6_5_OUT,
-                GP_6_4_IN, GP_6_4_OUT,
-                GP_6_3_IN, GP_6_3_OUT,
-                GP_6_2_IN, GP_6_2_OUT,
-                GP_6_1_IN, GP_6_1_OUT,
-                GP_6_0_IN, GP_6_0_OUT, }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
-        { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
-        { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
-        { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
-        { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
-        { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
-        { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
-                GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
-                GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
-        },
-        { },
-};
-static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xffc40000,
-                .end    = 0xffc46fff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct pinmux_info r8a7779_pinmux_info = {
-        .name = "r8a7779_pfc",
-        .resource = r8a7779_pfc_resources,
-        .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
-        .unlock_reg = 0xfffc0000, /* PMMR */
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_GP_0_0,
-        .last_gpio = GPIO_FN_SCK4_B,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-void r8a7779_pinmux_init(void)
-{
-        register_pinmux(&r8a7779_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
deleted file mode 100644
index 7a1525fd6ada..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ /dev/null
@@ -1,1663 +0,0 @@
-/*
- * sh7372 processor support - PFC hardware block
- *
- * Copyright (C) 2010  Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on
- * sh7367 processor support - PFC hardware block
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-#define CPU_ALL_PORT(fn, pfx, sfx) \
-        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx), \
-        PORT_10(fn, pfx##10, sfx),      PORT_10(fn, pfx##11, sfx), \
-        PORT_10(fn, pfx##12, sfx),      PORT_10(fn, pfx##13, sfx), \
-        PORT_10(fn, pfx##14, sfx),      PORT_10(fn, pfx##15, sfx), \
-        PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
-        PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        /* PORT0_DATA -> PORT190_DATA */
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),
-        PINMUX_DATA_END,
-        /* PORT0_IN -> PORT190_IN */
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),
-        PINMUX_INPUT_END,
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-        /* PORT0_OUT -> PORT190_OUT */
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),        /* PORT0_FN_IN  -> PORT190_FN_IN */
-        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT190_FN_OUT */
-        PORT_ALL(FN0),          /* PORT0_FN0    -> PORT190_FN0 */
-        PORT_ALL(FN1),          /* PORT0_FN1    -> PORT190_FN1 */
-        PORT_ALL(FN2),          /* PORT0_FN2    -> PORT190_FN2 */
-        PORT_ALL(FN3),          /* PORT0_FN3    -> PORT190_FN3 */
-        PORT_ALL(FN4),          /* PORT0_FN4    -> PORT190_FN4 */
-        PORT_ALL(FN5),          /* PORT0_FN5    -> PORT190_FN5 */
-        PORT_ALL(FN6),          /* PORT0_FN6    -> PORT190_FN6 */
-        PORT_ALL(FN7),          /* PORT0_FN7    -> PORT190_FN7 */
-        MSEL1CR_31_0,   MSEL1CR_31_1,
-        MSEL1CR_30_0,   MSEL1CR_30_1,
-        MSEL1CR_29_0,   MSEL1CR_29_1,
-        MSEL1CR_28_0,   MSEL1CR_28_1,
-        MSEL1CR_27_0,   MSEL1CR_27_1,
-        MSEL1CR_26_0,   MSEL1CR_26_1,
-        MSEL1CR_16_0,   MSEL1CR_16_1,
-        MSEL1CR_15_0,   MSEL1CR_15_1,
-        MSEL1CR_14_0,   MSEL1CR_14_1,
-        MSEL1CR_13_0,   MSEL1CR_13_1,
-        MSEL1CR_12_0,   MSEL1CR_12_1,
-        MSEL1CR_9_0,    MSEL1CR_9_1,
-        MSEL1CR_8_0,    MSEL1CR_8_1,
-        MSEL1CR_7_0,    MSEL1CR_7_1,
-        MSEL1CR_6_0,    MSEL1CR_6_1,
-        MSEL1CR_4_0,    MSEL1CR_4_1,
-        MSEL1CR_3_0,    MSEL1CR_3_1,
-        MSEL1CR_2_0,    MSEL1CR_2_1,
-        MSEL1CR_0_0,    MSEL1CR_0_1,
-        MSEL3CR_27_0,   MSEL3CR_27_1,
-        MSEL3CR_26_0,   MSEL3CR_26_1,
-        MSEL3CR_21_0,   MSEL3CR_21_1,
-        MSEL3CR_20_0,   MSEL3CR_20_1,
-        MSEL3CR_15_0,   MSEL3CR_15_1,
-        MSEL3CR_9_0,    MSEL3CR_9_1,
-        MSEL3CR_6_0,    MSEL3CR_6_1,
-        MSEL4CR_19_0,   MSEL4CR_19_1,
-        MSEL4CR_18_0,   MSEL4CR_18_1,
-        MSEL4CR_17_0,   MSEL4CR_17_1,
-        MSEL4CR_16_0,   MSEL4CR_16_1,
-        MSEL4CR_15_0,   MSEL4CR_15_1,
-        MSEL4CR_14_0,   MSEL4CR_14_1,
-        MSEL4CR_10_0,   MSEL4CR_10_1,
-        MSEL4CR_6_0,    MSEL4CR_6_1,
-        MSEL4CR_4_0,    MSEL4CR_4_1,
-        MSEL4CR_1_0,    MSEL4CR_1_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* IRQ */
-        IRQ0_6_MARK,    IRQ0_162_MARK,  IRQ1_MARK,      IRQ2_4_MARK,
-        IRQ2_5_MARK,    IRQ3_8_MARK,    IRQ3_16_MARK,   IRQ4_17_MARK,
-        IRQ4_163_MARK,  IRQ5_MARK,      IRQ6_39_MARK,   IRQ6_164_MARK,
-        IRQ7_40_MARK,   IRQ7_167_MARK,  IRQ8_41_MARK,   IRQ8_168_MARK,
-        IRQ9_42_MARK,   IRQ9_169_MARK,  IRQ10_MARK,     IRQ11_MARK,
-        IRQ12_80_MARK,  IRQ12_137_MARK, IRQ13_81_MARK,  IRQ13_145_MARK,
-        IRQ14_82_MARK,  IRQ14_146_MARK, IRQ15_83_MARK,  IRQ15_147_MARK,
-        IRQ16_84_MARK,  IRQ16_170_MARK, IRQ17_MARK,     IRQ18_MARK,
-        IRQ19_MARK,     IRQ20_MARK,     IRQ21_MARK,     IRQ22_MARK,
-        IRQ23_MARK,     IRQ24_MARK,     IRQ25_MARK,     IRQ26_121_MARK,
-        IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
-        IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
-        IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
-        /* MSIOF0 */
-        MSIOF0_TSYNC_MARK,      MSIOF0_TSCK_MARK,       MSIOF0_RXD_MARK,
-        MSIOF0_RSCK_MARK,       MSIOF0_RSYNC_MARK,      MSIOF0_MCK0_MARK,
-        MSIOF0_MCK1_MARK,       MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,
-        MSIOF0_TXD_MARK,
-        /* MSIOF1 */
-        MSIOF1_TSCK_39_MARK,    MSIOF1_TSYNC_40_MARK,
-        MSIOF1_TSCK_88_MARK,    MSIOF1_TSYNC_89_MARK,
-        MSIOF1_TXD_41_MARK,     MSIOF1_RXD_42_MARK,
-        MSIOF1_TXD_90_MARK,     MSIOF1_RXD_91_MARK,
-        MSIOF1_SS1_43_MARK,     MSIOF1_SS2_44_MARK,
-        MSIOF1_SS1_92_MARK,     MSIOF1_SS2_93_MARK,
-        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
-        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
-        /* MSIOF2 */
-        MSIOF2_RSCK_MARK,       MSIOF2_RSYNC_MARK,      MSIOF2_MCK0_MARK,
-        MSIOF2_MCK1_MARK,       MSIOF2_SS1_MARK,        MSIOF2_SS2_MARK,
-        MSIOF2_TSYNC_MARK,      MSIOF2_TSCK_MARK,       MSIOF2_RXD_MARK,
-        MSIOF2_TXD_MARK,
-        /* BBIF1 */
-        BBIF1_RXD_MARK,         BBIF1_TSYNC_MARK,       BBIF1_TSCK_MARK,
-        BBIF1_TXD_MARK,         BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
-        BBIF1_FLOW_MARK,        BB_RX_FLOW_N_MARK,
-        /* BBIF2 */
-        BBIF2_TSCK1_MARK,       BBIF2_TSYNC1_MARK,
-        BBIF2_TXD1_MARK,        BBIF2_RXD_MARK,
-        /* FSI */
-        FSIACK_MARK,    FSIBCK_MARK,            FSIAILR_MARK,   FSIAIBT_MARK,
-        FSIAISLD_MARK,  FSIAOMC_MARK,           FSIAOLR_MARK,   FSIAOBT_MARK,
-        FSIAOSLD_MARK,  FSIASPDIF_11_MARK,      FSIASPDIF_15_MARK,
-        /* FMSI */
-        FMSOCK_MARK,    FMSOOLR_MARK,   FMSIOLR_MARK,   FMSOOBT_MARK,
-        FMSIOBT_MARK,   FMSOSLD_MARK,   FMSOILR_MARK,   FMSIILR_MARK,
-        FMSOIBT_MARK,   FMSIIBT_MARK,   FMSISLD_MARK,   FMSICK_MARK,
-        /* SCIFA0 */
-        SCIFA0_TXD_MARK,        SCIFA0_RXD_MARK,        SCIFA0_SCK_MARK,
-        SCIFA0_RTS_MARK,        SCIFA0_CTS_MARK,
-        /* SCIFA1 */
-        SCIFA1_TXD_MARK,        SCIFA1_RXD_MARK,        SCIFA1_SCK_MARK,
-        SCIFA1_RTS_MARK,        SCIFA1_CTS_MARK,
-        /* SCIFA2 */
-        SCIFA2_CTS1_MARK,       SCIFA2_RTS1_MARK,       SCIFA2_TXD1_MARK,
-        SCIFA2_RXD1_MARK,       SCIFA2_SCK1_MARK,
-        /* SCIFA3 */
-        SCIFA3_CTS_43_MARK,     SCIFA3_CTS_140_MARK,    SCIFA3_RTS_44_MARK,
-        SCIFA3_RTS_141_MARK,    SCIFA3_SCK_MARK,        SCIFA3_TXD_MARK,
-        SCIFA3_RXD_MARK,
-        /* SCIFA4 */
-        SCIFA4_RXD_MARK,        SCIFA4_TXD_MARK,
-        /* SCIFA5 */
-        SCIFA5_RXD_MARK,        SCIFA5_TXD_MARK,
-        /* SCIFB */
-        SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
-        SCIFB_TXD_MARK, SCIFB_RXD_MARK,
-        /* CEU */
-        VIO_HD_MARK,    VIO_CKO1_MARK,  VIO_CKO2_MARK,  VIO_VD_MARK,
-        VIO_CLK_MARK,   VIO_FIELD_MARK, VIO_CKO_MARK,
-        VIO_D0_MARK,    VIO_D1_MARK,    VIO_D2_MARK,    VIO_D3_MARK,
-        VIO_D4_MARK,    VIO_D5_MARK,    VIO_D6_MARK,    VIO_D7_MARK,
-        VIO_D8_MARK,    VIO_D9_MARK,    VIO_D10_MARK,   VIO_D11_MARK,
-        VIO_D12_MARK,   VIO_D13_MARK,   VIO_D14_MARK,   VIO_D15_MARK,
-        /* USB0 */
-        IDIN_0_MARK,    EXTLP_0_MARK,   OVCN2_0_MARK,   PWEN_0_MARK,
-        OVCN_0_MARK,    VBUS0_0_MARK,
-        /* USB1 */
-        IDIN_1_18_MARK,         IDIN_1_113_MARK,
-        PWEN_1_115_MARK,        PWEN_1_138_MARK,
-        OVCN_1_114_MARK,        OVCN_1_162_MARK,
-        EXTLP_1_MARK,           OVCN2_1_MARK,
-        VBUS0_1_MARK,
-        /* GPIO */
-        GPI0_MARK,      GPI1_MARK,      GPO0_MARK,      GPO1_MARK,
-        /* BSC */
-        BS_MARK,        WE1_MARK,
-        CKO_MARK,       WAIT_MARK,      RDWR_MARK,
-        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
-        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
-        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
-        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
-        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
-        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
-        A26_MARK,
-        CS0_MARK,       CS2_MARK,       CS4_MARK,
-        CS5A_MARK,      CS5B_MARK,      CS6A_MARK,
-        /* BSC/FLCTL */
-        RD_FSC_MARK,    WE0_FWE_MARK,   A4_FOE_MARK,    A5_FCDE_MARK,
-        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   D3_NAF3_MARK,
-        D4_NAF4_MARK,   D5_NAF5_MARK,   D6_NAF6_MARK,   D7_NAF7_MARK,
-        D8_NAF8_MARK,   D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK,
-        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
-        /* MMCIF(1) */
-        MMCD0_0_MARK,   MMCD0_1_MARK,   MMCD0_2_MARK,   MMCD0_3_MARK,
-        MMCD0_4_MARK,   MMCD0_5_MARK,   MMCD0_6_MARK,   MMCD0_7_MARK,
-        MMCCMD0_MARK,   MMCCLK0_MARK,
-        /* MMCIF(2) */
-        MMCD1_0_MARK,   MMCD1_1_MARK,   MMCD1_2_MARK,   MMCD1_3_MARK,
-        MMCD1_4_MARK,   MMCD1_5_MARK,   MMCD1_6_MARK,   MMCD1_7_MARK,
-        MMCCLK1_MARK,   MMCCMD1_MARK,
-        /* SPU2 */
-        VINT_I_MARK,
-        /* FLCTL */
-        FCE1_MARK,      FCE0_MARK,      FRB_MARK,
-        /* HSI */
-        GP_RX_FLAG_MARK,        GP_RX_DATA_MARK,        GP_TX_READY_MARK,
-        GP_RX_WAKE_MARK,        MP_TX_FLAG_MARK,        MP_TX_DATA_MARK,
-        MP_RX_READY_MARK,       MP_TX_WAKE_MARK,
-        /* MFI */
-        MFIv6_MARK,
-        MFIv4_MARK,
-        MEMC_CS0_MARK,                  MEMC_BUSCLK_MEMC_A0_MARK,
-        MEMC_CS1_MEMC_A1_MARK,          MEMC_ADV_MEMC_DREQ0_MARK,
-        MEMC_WAIT_MEMC_DREQ1_MARK,      MEMC_NOE_MARK,
-        MEMC_NWE_MARK,                  MEMC_INT_MARK,
-        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,
-        MEMC_AD3_MARK,  MEMC_AD4_MARK,  MEMC_AD5_MARK,
-        MEMC_AD6_MARK,  MEMC_AD7_MARK,  MEMC_AD8_MARK,
-        MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
-        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
-        MEMC_AD15_MARK,
-        /* SIM */
-        SIM_RST_MARK,   SIM_CLK_MARK,   SIM_D_MARK,
-        /* TPU */
-        TPU0TO0_MARK,           TPU0TO1_MARK,
-        TPU0TO2_93_MARK,        TPU0TO2_99_MARK,
-        TPU0TO3_MARK,
-        /* I2C2 */
-        I2C_SCL2_MARK,  I2C_SDA2_MARK,
-        /* I2C3(1) */
-        I2C_SCL3_MARK,  I2C_SDA3_MARK,
-        /* I2C3(2) */
-        I2C_SCL3S_MARK, I2C_SDA3S_MARK,
-        /* I2C4(2) */
-        I2C_SCL4_MARK,  I2C_SDA4_MARK,
-        /* I2C4(2) */
-        I2C_SCL4S_MARK, I2C_SDA4S_MARK,
-        /* KEYSC */
-        KEYOUT0_MARK,   KEYIN0_121_MARK,        KEYIN0_136_MARK,
-        KEYOUT1_MARK,   KEYIN1_122_MARK,        KEYIN1_135_MARK,
-        KEYOUT2_MARK,   KEYIN2_123_MARK,        KEYIN2_134_MARK,
-        KEYOUT3_MARK,   KEYIN3_124_MARK,        KEYIN3_133_MARK,
-        KEYOUT4_MARK,   KEYIN4_MARK,
-        KEYOUT5_MARK,   KEYIN5_MARK,
-        KEYOUT6_MARK,   KEYIN6_MARK,
-        KEYOUT7_MARK,   KEYIN7_MARK,
-        /* LCDC */
-        LCDC0_SELECT_MARK,
-        LCDC1_SELECT_MARK,
-        LCDHSYN_MARK,   LCDCS_MARK,     LCDVSYN_MARK,   LCDDCK_MARK,
-        LCDWR_MARK,     LCDRD_MARK,     LCDDISP_MARK,   LCDRS_MARK,
-        LCDLCLK_MARK,   LCDDON_MARK,
-        LCDD0_MARK,     LCDD1_MARK,     LCDD2_MARK,     LCDD3_MARK,
-        LCDD4_MARK,     LCDD5_MARK,     LCDD6_MARK,     LCDD7_MARK,
-        LCDD8_MARK,     LCDD9_MARK,     LCDD10_MARK,    LCDD11_MARK,
-        LCDD12_MARK,    LCDD13_MARK,    LCDD14_MARK,    LCDD15_MARK,
-        LCDD16_MARK,    LCDD17_MARK,    LCDD18_MARK,    LCDD19_MARK,
-        LCDD20_MARK,    LCDD21_MARK,    LCDD22_MARK,    LCDD23_MARK,
-        /* IRDA */
-        IRDA_OUT_MARK,  IRDA_IN_MARK,   IRDA_FIRSEL_MARK,
-        IROUT_139_MARK, IROUT_140_MARK,
-        /* TSIF1 */
-        TS0_1SELECT_MARK,
-        TS0_2SELECT_MARK,
-        TS1_1SELECT_MARK,
-        TS1_2SELECT_MARK,
-        TS_SPSYNC1_MARK,        TS_SDAT1_MARK,
-        TS_SDEN1_MARK,          TS_SCK1_MARK,
-        /* TSIF2 */
-        TS_SPSYNC2_MARK,        TS_SDAT2_MARK,
-        TS_SDEN2_MARK,          TS_SCK2_MARK,
-        /* HDMI */
-        HDMI_HPD_MARK,  HDMI_CEC_MARK,
-        /* SDHI0 */
-        SDHICLK0_MARK,  SDHICD0_MARK,
-        SDHICMD0_MARK,  SDHIWP0_MARK,
-        SDHID0_0_MARK,  SDHID0_1_MARK,
-        SDHID0_2_MARK,  SDHID0_3_MARK,
-        /* SDHI1 */
-        SDHICLK1_MARK,  SDHICMD1_MARK,  SDHID1_0_MARK,
-        SDHID1_1_MARK,  SDHID1_2_MARK,  SDHID1_3_MARK,
-        /* SDHI2 */
-        SDHICLK2_MARK,  SDHICMD2_MARK,  SDHID2_0_MARK,
-        SDHID2_1_MARK,  SDHID2_2_MARK,  SDHID2_3_MARK,
-        /* SDENC */
-        SDENC_CPG_MARK,
-        SDENC_DV_CLKI_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-        PORT_DATA_IO_PU_PD(190),
-        /* IRQ */
-        PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
-        PINMUX_DATA(IRQ0_162_MARK,      PORT162_FN0,    MSEL1CR_0_1),
-        PINMUX_DATA(IRQ1_MARK,          PORT12_FN0),
-        PINMUX_DATA(IRQ2_4_MARK,        PORT4_FN0,      MSEL1CR_2_0),
-        PINMUX_DATA(IRQ2_5_MARK,        PORT5_FN0,      MSEL1CR_2_1),
-        PINMUX_DATA(IRQ3_8_MARK,        PORT8_FN0,      MSEL1CR_3_0),
-        PINMUX_DATA(IRQ3_16_MARK,       PORT16_FN0,     MSEL1CR_3_1),
-        PINMUX_DATA(IRQ4_17_MARK,       PORT17_FN0,     MSEL1CR_4_0),
-        PINMUX_DATA(IRQ4_163_MARK,      PORT163_FN0,    MSEL1CR_4_1),
-        PINMUX_DATA(IRQ5_MARK,          PORT18_FN0),
-        PINMUX_DATA(IRQ6_39_MARK,       PORT39_FN0,     MSEL1CR_6_0),
-        PINMUX_DATA(IRQ6_164_MARK,      PORT164_FN0,    MSEL1CR_6_1),
-        PINMUX_DATA(IRQ7_40_MARK,       PORT40_FN0,     MSEL1CR_7_1),
-        PINMUX_DATA(IRQ7_167_MARK,      PORT167_FN0,    MSEL1CR_7_0),
-        PINMUX_DATA(IRQ8_41_MARK,       PORT41_FN0,     MSEL1CR_8_1),
-        PINMUX_DATA(IRQ8_168_MARK,      PORT168_FN0,    MSEL1CR_8_0),
-        PINMUX_DATA(IRQ9_42_MARK,       PORT42_FN0,     MSEL1CR_9_0),
-        PINMUX_DATA(IRQ9_169_MARK,      PORT169_FN0,    MSEL1CR_9_1),
-        PINMUX_DATA(IRQ10_MARK,         PORT65_FN0,     MSEL1CR_9_1),
-        PINMUX_DATA(IRQ11_MARK,         PORT67_FN0),
-        PINMUX_DATA(IRQ12_80_MARK,      PORT80_FN0,     MSEL1CR_12_0),
-        PINMUX_DATA(IRQ12_137_MARK,     PORT137_FN0,    MSEL1CR_12_1),
-        PINMUX_DATA(IRQ13_81_MARK,      PORT81_FN0,     MSEL1CR_13_0),
-        PINMUX_DATA(IRQ13_145_MARK,     PORT145_FN0,    MSEL1CR_13_1),
-        PINMUX_DATA(IRQ14_82_MARK,      PORT82_FN0,     MSEL1CR_14_0),
-        PINMUX_DATA(IRQ14_146_MARK,     PORT146_FN0,    MSEL1CR_14_1),
-        PINMUX_DATA(IRQ15_83_MARK,      PORT83_FN0,     MSEL1CR_15_0),
-        PINMUX_DATA(IRQ15_147_MARK,     PORT147_FN0,    MSEL1CR_15_1),
-        PINMUX_DATA(IRQ16_84_MARK,      PORT84_FN0,     MSEL1CR_16_0),
-        PINMUX_DATA(IRQ16_170_MARK,     PORT170_FN0,    MSEL1CR_16_1),
-        PINMUX_DATA(IRQ17_MARK,         PORT85_FN0),
-        PINMUX_DATA(IRQ18_MARK,         PORT86_FN0),
-        PINMUX_DATA(IRQ19_MARK,         PORT87_FN0),
-        PINMUX_DATA(IRQ20_MARK,         PORT92_FN0),
-        PINMUX_DATA(IRQ21_MARK,         PORT93_FN0),
-        PINMUX_DATA(IRQ22_MARK,         PORT94_FN0),
-        PINMUX_DATA(IRQ23_MARK,         PORT95_FN0),
-        PINMUX_DATA(IRQ24_MARK,         PORT112_FN0),
-        PINMUX_DATA(IRQ25_MARK,         PORT119_FN0),
-        PINMUX_DATA(IRQ26_121_MARK,     PORT121_FN0,    MSEL1CR_26_1),
-        PINMUX_DATA(IRQ26_172_MARK,     PORT172_FN0,    MSEL1CR_26_0),
-        PINMUX_DATA(IRQ27_122_MARK,     PORT122_FN0,    MSEL1CR_27_1),
-        PINMUX_DATA(IRQ27_180_MARK,     PORT180_FN0,    MSEL1CR_27_0),
-        PINMUX_DATA(IRQ28_123_MARK,     PORT123_FN0,    MSEL1CR_28_1),
-        PINMUX_DATA(IRQ28_181_MARK,     PORT181_FN0,    MSEL1CR_28_0),
-        PINMUX_DATA(IRQ29_129_MARK,     PORT129_FN0,    MSEL1CR_29_1),
-        PINMUX_DATA(IRQ29_182_MARK,     PORT182_FN0,    MSEL1CR_29_0),
-        PINMUX_DATA(IRQ30_130_MARK,     PORT130_FN0,    MSEL1CR_30_1),
-        PINMUX_DATA(IRQ30_183_MARK,     PORT183_FN0,    MSEL1CR_30_0),
-        PINMUX_DATA(IRQ31_138_MARK,     PORT138_FN0,    MSEL1CR_31_1),
-        PINMUX_DATA(IRQ31_184_MARK,     PORT184_FN0,    MSEL1CR_31_0),
-        /* Function 1 */
-        PINMUX_DATA(BBIF2_TSCK1_MARK,           PORT0_FN1),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK,          PORT1_FN1),
-        PINMUX_DATA(BBIF2_TXD1_MARK,            PORT2_FN1),
-        PINMUX_DATA(BBIF2_RXD_MARK,             PORT3_FN1),
-        PINMUX_DATA(FSIACK_MARK,                PORT4_FN1),
-        PINMUX_DATA(FSIAILR_MARK,               PORT5_FN1),
-        PINMUX_DATA(FSIAIBT_MARK,               PORT6_FN1),
-        PINMUX_DATA(FSIAISLD_MARK,              PORT7_FN1),
-        PINMUX_DATA(FSIAOMC_MARK,               PORT8_FN1),
-        PINMUX_DATA(FSIAOLR_MARK,               PORT9_FN1),
-        PINMUX_DATA(FSIAOBT_MARK,               PORT10_FN1),
-        PINMUX_DATA(FSIAOSLD_MARK,              PORT11_FN1),
-        PINMUX_DATA(FMSOCK_MARK,                PORT12_FN1),
-        PINMUX_DATA(FMSOOLR_MARK,               PORT13_FN1),
-        PINMUX_DATA(FMSOOBT_MARK,               PORT14_FN1),
-        PINMUX_DATA(FMSOSLD_MARK,               PORT15_FN1),
-        PINMUX_DATA(FMSOILR_MARK,               PORT16_FN1),
-        PINMUX_DATA(FMSOIBT_MARK,               PORT17_FN1),
-        PINMUX_DATA(FMSISLD_MARK,               PORT18_FN1),
-        PINMUX_DATA(A0_MARK,                    PORT19_FN1),
-        PINMUX_DATA(A1_MARK,                    PORT20_FN1),
-        PINMUX_DATA(A2_MARK,                    PORT21_FN1),
-        PINMUX_DATA(A3_MARK,                    PORT22_FN1),
-        PINMUX_DATA(A4_FOE_MARK,                PORT23_FN1),
-        PINMUX_DATA(A5_FCDE_MARK,               PORT24_FN1),
-        PINMUX_DATA(A6_MARK,                    PORT25_FN1),
-        PINMUX_DATA(A7_MARK,                    PORT26_FN1),
-        PINMUX_DATA(A8_MARK,                    PORT27_FN1),
-        PINMUX_DATA(A9_MARK,                    PORT28_FN1),
-        PINMUX_DATA(A10_MARK,                   PORT29_FN1),
-        PINMUX_DATA(A11_MARK,                   PORT30_FN1),
-        PINMUX_DATA(A12_MARK,                   PORT31_FN1),
-        PINMUX_DATA(A13_MARK,                   PORT32_FN1),
-        PINMUX_DATA(A14_MARK,                   PORT33_FN1),
-        PINMUX_DATA(A15_MARK,                   PORT34_FN1),
-        PINMUX_DATA(A16_MARK,                   PORT35_FN1),
-        PINMUX_DATA(A17_MARK,                   PORT36_FN1),
-        PINMUX_DATA(A18_MARK,                   PORT37_FN1),
-        PINMUX_DATA(A19_MARK,                   PORT38_FN1),
-        PINMUX_DATA(A20_MARK,                   PORT39_FN1),
-        PINMUX_DATA(A21_MARK,                   PORT40_FN1),
-        PINMUX_DATA(A22_MARK,                   PORT41_FN1),
-        PINMUX_DATA(A23_MARK,                   PORT42_FN1),
-        PINMUX_DATA(A24_MARK,                   PORT43_FN1),
-        PINMUX_DATA(A25_MARK,                   PORT44_FN1),
-        PINMUX_DATA(A26_MARK,                   PORT45_FN1),
-        PINMUX_DATA(D0_NAF0_MARK,               PORT46_FN1),
-        PINMUX_DATA(D1_NAF1_MARK,               PORT47_FN1),
-        PINMUX_DATA(D2_NAF2_MARK,               PORT48_FN1),
-        PINMUX_DATA(D3_NAF3_MARK,               PORT49_FN1),
-        PINMUX_DATA(D4_NAF4_MARK,               PORT50_FN1),
-        PINMUX_DATA(D5_NAF5_MARK,               PORT51_FN1),
-        PINMUX_DATA(D6_NAF6_MARK,               PORT52_FN1),
-        PINMUX_DATA(D7_NAF7_MARK,               PORT53_FN1),
-        PINMUX_DATA(D8_NAF8_MARK,               PORT54_FN1),
-        PINMUX_DATA(D9_NAF9_MARK,               PORT55_FN1),
-        PINMUX_DATA(D10_NAF10_MARK,             PORT56_FN1),
-        PINMUX_DATA(D11_NAF11_MARK,             PORT57_FN1),
-        PINMUX_DATA(D12_NAF12_MARK,             PORT58_FN1),
-        PINMUX_DATA(D13_NAF13_MARK,             PORT59_FN1),
-        PINMUX_DATA(D14_NAF14_MARK,             PORT60_FN1),
-        PINMUX_DATA(D15_NAF15_MARK,             PORT61_FN1),
-        PINMUX_DATA(CS0_MARK,                   PORT62_FN1),
-        PINMUX_DATA(CS2_MARK,                   PORT63_FN1),
-        PINMUX_DATA(CS4_MARK,                   PORT64_FN1),
-        PINMUX_DATA(CS5A_MARK,                  PORT65_FN1),
-        PINMUX_DATA(CS5B_MARK,                  PORT66_FN1),
-        PINMUX_DATA(CS6A_MARK,                  PORT67_FN1),
-        PINMUX_DATA(FCE0_MARK,                  PORT68_FN1),
-        PINMUX_DATA(RD_FSC_MARK,                PORT69_FN1),
-        PINMUX_DATA(WE0_FWE_MARK,               PORT70_FN1),
-        PINMUX_DATA(WE1_MARK,                   PORT71_FN1),
-        PINMUX_DATA(CKO_MARK,                   PORT72_FN1),
-        PINMUX_DATA(FRB_MARK,                   PORT73_FN1),
-        PINMUX_DATA(WAIT_MARK,                  PORT74_FN1),
-        PINMUX_DATA(RDWR_MARK,                  PORT75_FN1),
-        PINMUX_DATA(MEMC_AD0_MARK,              PORT76_FN1),
-        PINMUX_DATA(MEMC_AD1_MARK,              PORT77_FN1),
-        PINMUX_DATA(MEMC_AD2_MARK,              PORT78_FN1),
-        PINMUX_DATA(MEMC_AD3_MARK,              PORT79_FN1),
-        PINMUX_DATA(MEMC_AD4_MARK,              PORT80_FN1),
-        PINMUX_DATA(MEMC_AD5_MARK,              PORT81_FN1),
-        PINMUX_DATA(MEMC_AD6_MARK,              PORT82_FN1),
-        PINMUX_DATA(MEMC_AD7_MARK,              PORT83_FN1),
-        PINMUX_DATA(MEMC_AD8_MARK,              PORT84_FN1),
-        PINMUX_DATA(MEMC_AD9_MARK,              PORT85_FN1),
-        PINMUX_DATA(MEMC_AD10_MARK,             PORT86_FN1),
-        PINMUX_DATA(MEMC_AD11_MARK,             PORT87_FN1),
-        PINMUX_DATA(MEMC_AD12_MARK,             PORT88_FN1),
-        PINMUX_DATA(MEMC_AD13_MARK,             PORT89_FN1),
-        PINMUX_DATA(MEMC_AD14_MARK,             PORT90_FN1),
-        PINMUX_DATA(MEMC_AD15_MARK,             PORT91_FN1),
-        PINMUX_DATA(MEMC_CS0_MARK,              PORT92_FN1),
-        PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK,   PORT93_FN1),
-        PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK,      PORT94_FN1),
-        PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK,   PORT95_FN1),
-        PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK,  PORT96_FN1),
-        PINMUX_DATA(MEMC_NOE_MARK,              PORT97_FN1),
-        PINMUX_DATA(MEMC_NWE_MARK,              PORT98_FN1),
-        PINMUX_DATA(MEMC_INT_MARK,              PORT99_FN1),
-        PINMUX_DATA(VIO_VD_MARK,                PORT100_FN1),
-        PINMUX_DATA(VIO_HD_MARK,                PORT101_FN1),
-        PINMUX_DATA(VIO_D0_MARK,                PORT102_FN1),
-        PINMUX_DATA(VIO_D1_MARK,                PORT103_FN1),
-        PINMUX_DATA(VIO_D2_MARK,                PORT104_FN1),
-        PINMUX_DATA(VIO_D3_MARK,                PORT105_FN1),
-        PINMUX_DATA(VIO_D4_MARK,                PORT106_FN1),
-        PINMUX_DATA(VIO_D5_MARK,                PORT107_FN1),
-        PINMUX_DATA(VIO_D6_MARK,                PORT108_FN1),
-        PINMUX_DATA(VIO_D7_MARK,                PORT109_FN1),
-        PINMUX_DATA(VIO_D8_MARK,                PORT110_FN1),
-        PINMUX_DATA(VIO_D9_MARK,                PORT111_FN1),
-        PINMUX_DATA(VIO_D10_MARK,               PORT112_FN1),
-        PINMUX_DATA(VIO_D11_MARK,               PORT113_FN1),
-        PINMUX_DATA(VIO_D12_MARK,               PORT114_FN1),
-        PINMUX_DATA(VIO_D13_MARK,               PORT115_FN1),
-        PINMUX_DATA(VIO_D14_MARK,               PORT116_FN1),
-        PINMUX_DATA(VIO_D15_MARK,               PORT117_FN1),
-        PINMUX_DATA(VIO_CLK_MARK,               PORT118_FN1),
-        PINMUX_DATA(VIO_FIELD_MARK,             PORT119_FN1),
-        PINMUX_DATA(VIO_CKO_MARK,               PORT120_FN1),
-        PINMUX_DATA(LCDD0_MARK,                 PORT121_FN1),
-        PINMUX_DATA(LCDD1_MARK,                 PORT122_FN1),
-        PINMUX_DATA(LCDD2_MARK,                 PORT123_FN1),
-        PINMUX_DATA(LCDD3_MARK,                 PORT124_FN1),
-        PINMUX_DATA(LCDD4_MARK,                 PORT125_FN1),
-        PINMUX_DATA(LCDD5_MARK,                 PORT126_FN1),
-        PINMUX_DATA(LCDD6_MARK,                 PORT127_FN1),
-        PINMUX_DATA(LCDD7_MARK,                 PORT128_FN1),
-        PINMUX_DATA(LCDD8_MARK,                 PORT129_FN1),
-        PINMUX_DATA(LCDD9_MARK,                 PORT130_FN1),
-        PINMUX_DATA(LCDD10_MARK,                PORT131_FN1),
-        PINMUX_DATA(LCDD11_MARK,                PORT132_FN1),
-        PINMUX_DATA(LCDD12_MARK,                PORT133_FN1),
-        PINMUX_DATA(LCDD13_MARK,                PORT134_FN1),
-        PINMUX_DATA(LCDD14_MARK,                PORT135_FN1),
-        PINMUX_DATA(LCDD15_MARK,                PORT136_FN1),
-        PINMUX_DATA(LCDD16_MARK,                PORT137_FN1),
-        PINMUX_DATA(LCDD17_MARK,                PORT138_FN1),
-        PINMUX_DATA(LCDD18_MARK,                PORT139_FN1),
-        PINMUX_DATA(LCDD19_MARK,                PORT140_FN1),
-        PINMUX_DATA(LCDD20_MARK,                PORT141_FN1),
-        PINMUX_DATA(LCDD21_MARK,                PORT142_FN1),
-        PINMUX_DATA(LCDD22_MARK,                PORT143_FN1),
-        PINMUX_DATA(LCDD23_MARK,                PORT144_FN1),
-        PINMUX_DATA(LCDHSYN_MARK,               PORT145_FN1),
-        PINMUX_DATA(LCDVSYN_MARK,               PORT146_FN1),
-        PINMUX_DATA(LCDDCK_MARK,                PORT147_FN1),
-        PINMUX_DATA(LCDRD_MARK,                 PORT148_FN1),
-        PINMUX_DATA(LCDDISP_MARK,               PORT149_FN1),
-        PINMUX_DATA(LCDLCLK_MARK,               PORT150_FN1),
-        PINMUX_DATA(LCDDON_MARK,                PORT151_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT152_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT153_FN1),
-        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT154_FN1),
-        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT155_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK,            PORT156_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK,              PORT157_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK,              PORT158_FN1),
-        PINMUX_DATA(TS_SCK1_MARK,               PORT159_FN1),
-        PINMUX_DATA(TPU0TO0_MARK,               PORT160_FN1),
-        PINMUX_DATA(TPU0TO1_MARK,               PORT161_FN1),
-        PINMUX_DATA(SCIFB_SCK_MARK,             PORT162_FN1),
-        PINMUX_DATA(SCIFB_RTS_MARK,             PORT163_FN1),
-        PINMUX_DATA(SCIFB_CTS_MARK,             PORT164_FN1),
-        PINMUX_DATA(SCIFB_TXD_MARK,             PORT165_FN1),
-        PINMUX_DATA(SCIFB_RXD_MARK,             PORT166_FN1),
-        PINMUX_DATA(VBUS0_0_MARK,               PORT167_FN1),
-        PINMUX_DATA(VBUS0_1_MARK,               PORT168_FN1),
-        PINMUX_DATA(HDMI_HPD_MARK,              PORT169_FN1),
-        PINMUX_DATA(HDMI_CEC_MARK,              PORT170_FN1),
-        PINMUX_DATA(SDHICLK0_MARK,              PORT171_FN1),
-        PINMUX_DATA(SDHICD0_MARK,               PORT172_FN1),
-        PINMUX_DATA(SDHID0_0_MARK,              PORT173_FN1),
-        PINMUX_DATA(SDHID0_1_MARK,              PORT174_FN1),
-        PINMUX_DATA(SDHID0_2_MARK,              PORT175_FN1),
-        PINMUX_DATA(SDHID0_3_MARK,              PORT176_FN1),
-        PINMUX_DATA(SDHICMD0_MARK,              PORT177_FN1),
-        PINMUX_DATA(SDHIWP0_MARK,               PORT178_FN1),
-        PINMUX_DATA(SDHICLK1_MARK,              PORT179_FN1),
-        PINMUX_DATA(SDHID1_0_MARK,              PORT180_FN1),
-        PINMUX_DATA(SDHID1_1_MARK,              PORT181_FN1),
-        PINMUX_DATA(SDHID1_2_MARK,              PORT182_FN1),
-        PINMUX_DATA(SDHID1_3_MARK,              PORT183_FN1),
-        PINMUX_DATA(SDHICMD1_MARK,              PORT184_FN1),
-        PINMUX_DATA(SDHICLK2_MARK,              PORT185_FN1),
-        PINMUX_DATA(SDHID2_0_MARK,              PORT186_FN1),
-        PINMUX_DATA(SDHID2_1_MARK,              PORT187_FN1),
-        PINMUX_DATA(SDHID2_2_MARK,              PORT188_FN1),
-        PINMUX_DATA(SDHID2_3_MARK,              PORT189_FN1),
-        PINMUX_DATA(SDHICMD2_MARK,              PORT190_FN1),
-        /* Function 2 */
-        PINMUX_DATA(FSIBCK_MARK,                PORT4_FN2),
-        PINMUX_DATA(SCIFA4_RXD_MARK,            PORT5_FN2),
-        PINMUX_DATA(SCIFA4_TXD_MARK,            PORT6_FN2),
-        PINMUX_DATA(SCIFA5_RXD_MARK,            PORT8_FN2),
-        PINMUX_DATA(FSIASPDIF_11_MARK,          PORT11_FN2),
-        PINMUX_DATA(SCIFA5_TXD_MARK,            PORT12_FN2),
-        PINMUX_DATA(FMSIOLR_MARK,               PORT13_FN2),
-        PINMUX_DATA(FMSIOBT_MARK,               PORT14_FN2),
-        PINMUX_DATA(FSIASPDIF_15_MARK,          PORT15_FN2),
-        PINMUX_DATA(FMSIILR_MARK,               PORT16_FN2),
-        PINMUX_DATA(FMSIIBT_MARK,               PORT17_FN2),
-        PINMUX_DATA(BS_MARK,                    PORT19_FN2),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT36_FN2),
-        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT37_FN2),
-        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT38_FN2),
-        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT39_FN2),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT40_FN2),
-        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT41_FN2),
-        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT42_FN2),
-        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT43_FN2),
-        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT44_FN2),
-        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT45_FN2),
-        PINMUX_DATA(FMSICK_MARK,                PORT65_FN2),
-        PINMUX_DATA(FCE1_MARK,                  PORT66_FN2),
-        PINMUX_DATA(BBIF1_RXD_MARK,             PORT76_FN2),
-        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT77_FN2),
-        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT78_FN2),
-        PINMUX_DATA(BBIF1_TXD_MARK,             PORT79_FN2),
-        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT80_FN2),
-        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT81_FN2),
-        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT82_FN2),
-        PINMUX_DATA(BB_RX_FLOW_N_MARK,          PORT83_FN2),
-        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT84_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT85_FN2),
-        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT86_FN2),
-        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT87_FN2),
-        PINMUX_DATA(MSIOF1_TSCK_88_MARK,        PORT88_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TSYNC_89_MARK,       PORT89_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_TXD_90_MARK,         PORT90_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_RXD_91_MARK,         PORT91_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_SS1_92_MARK,         PORT92_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(MSIOF1_SS2_93_MARK,         PORT93_FN2, MSEL4CR_10_1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK,           PORT94_FN2),
-        PINMUX_DATA(SCIFA2_RTS1_MARK,           PORT95_FN2),
-        PINMUX_DATA(SCIFA2_TXD1_MARK,           PORT96_FN2),
-        PINMUX_DATA(SCIFA2_RXD1_MARK,           PORT97_FN2),
-        PINMUX_DATA(SCIFA2_SCK1_MARK,           PORT98_FN2),
-        PINMUX_DATA(I2C_SCL2_MARK,              PORT110_FN2),
-        PINMUX_DATA(I2C_SDA2_MARK,              PORT111_FN2),
-        PINMUX_DATA(I2C_SCL3_MARK,              PORT114_FN2, MSEL4CR_16_1),
-        PINMUX_DATA(I2C_SDA3_MARK,              PORT115_FN2, MSEL4CR_16_1),
-        PINMUX_DATA(I2C_SCL4_MARK,              PORT116_FN2, MSEL4CR_17_1),
-        PINMUX_DATA(I2C_SDA4_MARK,              PORT117_FN2, MSEL4CR_17_1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT134_FN2),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT135_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT136_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT137_FN2),
-        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT138_FN2),
-        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT139_FN2),
-        PINMUX_DATA(SCIFA3_CTS_140_MARK,        PORT140_FN2, MSEL3CR_9_1),
-        PINMUX_DATA(SCIFA3_RTS_141_MARK,        PORT141_FN2),
-        PINMUX_DATA(SCIFA3_SCK_MARK,            PORT142_FN2),
-        PINMUX_DATA(SCIFA3_TXD_MARK,            PORT143_FN2),
-        PINMUX_DATA(SCIFA3_RXD_MARK,            PORT144_FN2),
-        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT148_FN2),
-        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT149_FN2),
-        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT150_FN2),
-        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT151_FN2),
-        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT156_FN2),
-        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT157_FN2),
-        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT158_FN2),
-        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT159_FN2),
-        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT160_FN2),
-        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT161_FN2),
-        /* Function 3 */
-        PINMUX_DATA(VIO_CKO1_MARK,              PORT16_FN3),
-        PINMUX_DATA(VIO_CKO2_MARK,              PORT17_FN3),
-        PINMUX_DATA(IDIN_1_18_MARK,             PORT18_FN3, MSEL4CR_14_1),
-        PINMUX_DATA(MSIOF1_TSCK_39_MARK,        PORT39_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_TSYNC_40_MARK,       PORT40_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_TXD_41_MARK,         PORT41_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_RXD_42_MARK,         PORT42_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_SS1_43_MARK,         PORT43_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MSIOF1_SS2_44_MARK,         PORT44_FN3, MSEL4CR_10_0),
-        PINMUX_DATA(MMCD1_0_MARK,               PORT54_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_1_MARK,               PORT55_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_2_MARK,               PORT56_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_3_MARK,               PORT57_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_4_MARK,               PORT58_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_5_MARK,               PORT59_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_6_MARK,               PORT60_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCD1_7_MARK,               PORT61_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(VINT_I_MARK,                PORT65_FN3),
-        PINMUX_DATA(MMCCLK1_MARK,               PORT66_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(MMCCMD1_MARK,               PORT67_FN3, MSEL4CR_15_1),
-        PINMUX_DATA(TPU0TO2_93_MARK,            PORT93_FN3),
-        PINMUX_DATA(TPU0TO2_99_MARK,            PORT99_FN3),
-        PINMUX_DATA(TPU0TO3_MARK,               PORT112_FN3),
-        PINMUX_DATA(IDIN_0_MARK,                PORT113_FN3),
-        PINMUX_DATA(EXTLP_0_MARK,               PORT114_FN3),
-        PINMUX_DATA(OVCN2_0_MARK,               PORT115_FN3),
-        PINMUX_DATA(PWEN_0_MARK,                PORT116_FN3),
-        PINMUX_DATA(OVCN_0_MARK,                PORT117_FN3),
-        PINMUX_DATA(KEYOUT7_MARK,               PORT121_FN3),
-        PINMUX_DATA(KEYOUT6_MARK,               PORT122_FN3),
-        PINMUX_DATA(KEYOUT5_MARK,               PORT123_FN3),
-        PINMUX_DATA(KEYOUT4_MARK,               PORT124_FN3),
-        PINMUX_DATA(KEYOUT3_MARK,               PORT125_FN3),
-        PINMUX_DATA(KEYOUT2_MARK,               PORT126_FN3),
-        PINMUX_DATA(KEYOUT1_MARK,               PORT127_FN3),
-        PINMUX_DATA(KEYOUT0_MARK,               PORT128_FN3),
-        PINMUX_DATA(KEYIN7_MARK,                PORT129_FN3),
-        PINMUX_DATA(KEYIN6_MARK,                PORT130_FN3),
-        PINMUX_DATA(KEYIN5_MARK,                PORT131_FN3),
-        PINMUX_DATA(KEYIN4_MARK,                PORT132_FN3),
-        PINMUX_DATA(KEYIN3_133_MARK,            PORT133_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN2_134_MARK,            PORT134_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN1_135_MARK,            PORT135_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(KEYIN0_136_MARK,            PORT136_FN3, MSEL4CR_18_0),
-        PINMUX_DATA(TS_SPSYNC2_MARK,            PORT137_FN3),
-        PINMUX_DATA(IROUT_139_MARK,             PORT139_FN3),
-        PINMUX_DATA(IRDA_OUT_MARK,              PORT140_FN3),
-        PINMUX_DATA(IRDA_IN_MARK,               PORT141_FN3),
-        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT142_FN3),
-        PINMUX_DATA(TS_SDAT2_MARK,              PORT145_FN3),
-        PINMUX_DATA(TS_SDEN2_MARK,              PORT146_FN3),
-        PINMUX_DATA(TS_SCK2_MARK,               PORT147_FN3),
-        /* Function 4 */
-        PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
-        PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
-        PINMUX_DATA(GP_RX_FLAG_MARK,    PORT76_FN4),
-        PINMUX_DATA(GP_RX_DATA_MARK,    PORT77_FN4),
-        PINMUX_DATA(GP_TX_READY_MARK,   PORT78_FN4),
-        PINMUX_DATA(GP_RX_WAKE_MARK,    PORT79_FN4),
-        PINMUX_DATA(MP_TX_FLAG_MARK,    PORT80_FN4),
-        PINMUX_DATA(MP_TX_DATA_MARK,    PORT81_FN4),
-        PINMUX_DATA(MP_RX_READY_MARK,   PORT82_FN4),
-        PINMUX_DATA(MP_TX_WAKE_MARK,    PORT83_FN4),
-        PINMUX_DATA(MMCD0_0_MARK,       PORT84_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_1_MARK,       PORT85_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_2_MARK,       PORT86_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_3_MARK,       PORT87_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_4_MARK,       PORT88_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_5_MARK,       PORT89_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_6_MARK,       PORT90_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCD0_7_MARK,       PORT91_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(MMCCMD0_MARK,       PORT92_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(SIM_RST_MARK,       PORT94_FN4),
-        PINMUX_DATA(SIM_CLK_MARK,       PORT95_FN4),
-        PINMUX_DATA(SIM_D_MARK,         PORT98_FN4),
-        PINMUX_DATA(MMCCLK0_MARK,       PORT99_FN4, MSEL4CR_15_0),
-        PINMUX_DATA(IDIN_1_113_MARK,    PORT113_FN4, MSEL4CR_14_0),
-        PINMUX_DATA(OVCN_1_114_MARK,    PORT114_FN4, MSEL4CR_14_0),
-        PINMUX_DATA(PWEN_1_115_MARK,    PORT115_FN4),
-        PINMUX_DATA(EXTLP_1_MARK,       PORT116_FN4),
-        PINMUX_DATA(OVCN2_1_MARK,       PORT117_FN4),
-        PINMUX_DATA(KEYIN0_121_MARK,    PORT121_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN1_122_MARK,    PORT122_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN2_123_MARK,    PORT123_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(KEYIN3_124_MARK,    PORT124_FN4, MSEL4CR_18_1),
-        PINMUX_DATA(PWEN_1_138_MARK,    PORT138_FN4),
-        PINMUX_DATA(IROUT_140_MARK,     PORT140_FN4),
-        PINMUX_DATA(LCDCS_MARK,         PORT145_FN4),
-        PINMUX_DATA(LCDWR_MARK,         PORT147_FN4),
-        PINMUX_DATA(LCDRS_MARK,         PORT149_FN4),
-        PINMUX_DATA(OVCN_1_162_MARK,    PORT162_FN4, MSEL4CR_14_1),
-        /* Function 5 */
-        PINMUX_DATA(GPI0_MARK,          PORT41_FN5),
-        PINMUX_DATA(GPI1_MARK,          PORT42_FN5),
-        PINMUX_DATA(GPO0_MARK,          PORT43_FN5),
-        PINMUX_DATA(GPO1_MARK,          PORT44_FN5),
-        PINMUX_DATA(I2C_SCL3S_MARK,     PORT137_FN5, MSEL4CR_16_0),
-        PINMUX_DATA(I2C_SDA3S_MARK,     PORT145_FN5, MSEL4CR_16_0),
-        PINMUX_DATA(I2C_SCL4S_MARK,     PORT146_FN5, MSEL4CR_17_0),
-        PINMUX_DATA(I2C_SDA4S_MARK,     PORT147_FN5, MSEL4CR_17_0),
-        /* Function select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,  MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,  MSEL3CR_6_1),
-        PINMUX_DATA(TS0_1SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_0),
-        PINMUX_DATA(TS0_2SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_1),
-        PINMUX_DATA(TS1_1SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_0),
-        PINMUX_DATA(TS1_2SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_1),
-        PINMUX_DATA(SDENC_CPG_MARK,     MSEL4CR_19_0),
-        PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
-        PINMUX_DATA(MFIv6_MARK,         MSEL4CR_6_0),
-        PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* PORT */
-        GPIO_PORT_ALL(),
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-        /* MMCIF(1) */
-        GPIO_FN(MMCD0_0),       GPIO_FN(MMCD0_1),       GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),       GPIO_FN(MMCD0_4),       GPIO_FN(MMCD0_5),
-        GPIO_FN(MMCD0_6),       GPIO_FN(MMCD0_7),       GPIO_FN(MMCCMD0),
-        GPIO_FN(MMCCLK0),
-        /* MMCIF(2) */
-        GPIO_FN(MMCD1_0),       GPIO_FN(MMCD1_1),       GPIO_FN(MMCD1_2),
-        GPIO_FN(MMCD1_3),       GPIO_FN(MMCD1_4),       GPIO_FN(MMCD1_5),
-        GPIO_FN(MMCD1_6),       GPIO_FN(MMCD1_7),       GPIO_FN(MMCCLK1),
-        GPIO_FN(MMCCMD1),
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-        /* SDHI0 */
-        GPIO_FN(SDHICLK0),      GPIO_FN(SDHICD0),       GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),       GPIO_FN(SDHID0_0),      GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),      GPIO_FN(SDHID0_3),
-        /* SDHI1 */
-        GPIO_FN(SDHICLK1),      GPIO_FN(SDHICMD1),      GPIO_FN(SDHID1_0),
-        GPIO_FN(SDHID1_1),      GPIO_FN(SDHID1_2),      GPIO_FN(SDHID1_3),
-        /* SDHI2 */
-        GPIO_FN(SDHICLK2),      GPIO_FN(SDHICMD2),      GPIO_FN(SDHID2_0),
-        GPIO_FN(SDHID2_1),      GPIO_FN(SDHID2_2),      GPIO_FN(SDHID2_3),
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0,       0xE6051000), /* PORT0CR */
-        PORTCR(1,       0xE6051001), /* PORT1CR */
-        PORTCR(2,       0xE6051002), /* PORT2CR */
-        PORTCR(3,       0xE6051003), /* PORT3CR */
-        PORTCR(4,       0xE6051004), /* PORT4CR */
-        PORTCR(5,       0xE6051005), /* PORT5CR */
-        PORTCR(6,       0xE6051006), /* PORT6CR */
-        PORTCR(7,       0xE6051007), /* PORT7CR */
-        PORTCR(8,       0xE6051008), /* PORT8CR */
-        PORTCR(9,       0xE6051009), /* PORT9CR */
-        PORTCR(10,      0xE605100A), /* PORT10CR */
-        PORTCR(11,      0xE605100B), /* PORT11CR */
-        PORTCR(12,      0xE605100C), /* PORT12CR */
-        PORTCR(13,      0xE605100D), /* PORT13CR */
-        PORTCR(14,      0xE605100E), /* PORT14CR */
-        PORTCR(15,      0xE605100F), /* PORT15CR */
-        PORTCR(16,      0xE6051010), /* PORT16CR */
-        PORTCR(17,      0xE6051011), /* PORT17CR */
-        PORTCR(18,      0xE6051012), /* PORT18CR */
-        PORTCR(19,      0xE6051013), /* PORT19CR */
-        PORTCR(20,      0xE6051014), /* PORT20CR */
-        PORTCR(21,      0xE6051015), /* PORT21CR */
-        PORTCR(22,      0xE6051016), /* PORT22CR */
-        PORTCR(23,      0xE6051017), /* PORT23CR */
-        PORTCR(24,      0xE6051018), /* PORT24CR */
-        PORTCR(25,      0xE6051019), /* PORT25CR */
-        PORTCR(26,      0xE605101A), /* PORT26CR */
-        PORTCR(27,      0xE605101B), /* PORT27CR */
-        PORTCR(28,      0xE605101C), /* PORT28CR */
-        PORTCR(29,      0xE605101D), /* PORT29CR */
-        PORTCR(30,      0xE605101E), /* PORT30CR */
-        PORTCR(31,      0xE605101F), /* PORT31CR */
-        PORTCR(32,      0xE6051020), /* PORT32CR */
-        PORTCR(33,      0xE6051021), /* PORT33CR */
-        PORTCR(34,      0xE6051022), /* PORT34CR */
-        PORTCR(35,      0xE6051023), /* PORT35CR */
-        PORTCR(36,      0xE6051024), /* PORT36CR */
-        PORTCR(37,      0xE6051025), /* PORT37CR */
-        PORTCR(38,      0xE6051026), /* PORT38CR */
-        PORTCR(39,      0xE6051027), /* PORT39CR */
-        PORTCR(40,      0xE6051028), /* PORT40CR */
-        PORTCR(41,      0xE6051029), /* PORT41CR */
-        PORTCR(42,      0xE605102A), /* PORT42CR */
-        PORTCR(43,      0xE605102B), /* PORT43CR */
-        PORTCR(44,      0xE605102C), /* PORT44CR */
-        PORTCR(45,      0xE605102D), /* PORT45CR */
-        PORTCR(46,      0xE605202E), /* PORT46CR */
-        PORTCR(47,      0xE605202F), /* PORT47CR */
-        PORTCR(48,      0xE6052030), /* PORT48CR */
-        PORTCR(49,      0xE6052031), /* PORT49CR */
-        PORTCR(50,      0xE6052032), /* PORT50CR */
-        PORTCR(51,      0xE6052033), /* PORT51CR */
-        PORTCR(52,      0xE6052034), /* PORT52CR */
-        PORTCR(53,      0xE6052035), /* PORT53CR */
-        PORTCR(54,      0xE6052036), /* PORT54CR */
-        PORTCR(55,      0xE6052037), /* PORT55CR */
-        PORTCR(56,      0xE6052038), /* PORT56CR */
-        PORTCR(57,      0xE6052039), /* PORT57CR */
-        PORTCR(58,      0xE605203A), /* PORT58CR */
-        PORTCR(59,      0xE605203B), /* PORT59CR */
-        PORTCR(60,      0xE605203C), /* PORT60CR */
-        PORTCR(61,      0xE605203D), /* PORT61CR */
-        PORTCR(62,      0xE605203E), /* PORT62CR */
-        PORTCR(63,      0xE605203F), /* PORT63CR */
-        PORTCR(64,      0xE6052040), /* PORT64CR */
-        PORTCR(65,      0xE6052041), /* PORT65CR */
-        PORTCR(66,      0xE6052042), /* PORT66CR */
-        PORTCR(67,      0xE6052043), /* PORT67CR */
-        PORTCR(68,      0xE6052044), /* PORT68CR */
-        PORTCR(69,      0xE6052045), /* PORT69CR */
-        PORTCR(70,      0xE6052046), /* PORT70CR */
-        PORTCR(71,      0xE6052047), /* PORT71CR */
-        PORTCR(72,      0xE6052048), /* PORT72CR */
-        PORTCR(73,      0xE6052049), /* PORT73CR */
-        PORTCR(74,      0xE605204A), /* PORT74CR */
-        PORTCR(75,      0xE605204B), /* PORT75CR */
-        PORTCR(76,      0xE605004C), /* PORT76CR */
-        PORTCR(77,      0xE605004D), /* PORT77CR */
-        PORTCR(78,      0xE605004E), /* PORT78CR */
-        PORTCR(79,      0xE605004F), /* PORT79CR */
-        PORTCR(80,      0xE6050050), /* PORT80CR */
-        PORTCR(81,      0xE6050051), /* PORT81CR */
-        PORTCR(82,      0xE6050052), /* PORT82CR */
-        PORTCR(83,      0xE6050053), /* PORT83CR */
-        PORTCR(84,      0xE6050054), /* PORT84CR */
-        PORTCR(85,      0xE6050055), /* PORT85CR */
-        PORTCR(86,      0xE6050056), /* PORT86CR */
-        PORTCR(87,      0xE6050057), /* PORT87CR */
-        PORTCR(88,      0xE6050058), /* PORT88CR */
-        PORTCR(89,      0xE6050059), /* PORT89CR */
-        PORTCR(90,      0xE605005A), /* PORT90CR */
-        PORTCR(91,      0xE605005B), /* PORT91CR */
-        PORTCR(92,      0xE605005C), /* PORT92CR */
-        PORTCR(93,      0xE605005D), /* PORT93CR */
-        PORTCR(94,      0xE605005E), /* PORT94CR */
-        PORTCR(95,      0xE605005F), /* PORT95CR */
-        PORTCR(96,      0xE6050060), /* PORT96CR */
-        PORTCR(97,      0xE6050061), /* PORT97CR */
-        PORTCR(98,      0xE6050062), /* PORT98CR */
-        PORTCR(99,      0xE6050063), /* PORT99CR */
-        PORTCR(100,     0xE6053064), /* PORT100CR */
-        PORTCR(101,     0xE6053065), /* PORT101CR */
-        PORTCR(102,     0xE6053066), /* PORT102CR */
-        PORTCR(103,     0xE6053067), /* PORT103CR */
-        PORTCR(104,     0xE6053068), /* PORT104CR */
-        PORTCR(105,     0xE6053069), /* PORT105CR */
-        PORTCR(106,     0xE605306A), /* PORT106CR */
-        PORTCR(107,     0xE605306B), /* PORT107CR */
-        PORTCR(108,     0xE605306C), /* PORT108CR */
-        PORTCR(109,     0xE605306D), /* PORT109CR */
-        PORTCR(110,     0xE605306E), /* PORT110CR */
-        PORTCR(111,     0xE605306F), /* PORT111CR */
-        PORTCR(112,     0xE6053070), /* PORT112CR */
-        PORTCR(113,     0xE6053071), /* PORT113CR */
-        PORTCR(114,     0xE6053072), /* PORT114CR */
-        PORTCR(115,     0xE6053073), /* PORT115CR */
-        PORTCR(116,     0xE6053074), /* PORT116CR */
-        PORTCR(117,     0xE6053075), /* PORT117CR */
-        PORTCR(118,     0xE6053076), /* PORT118CR */
-        PORTCR(119,     0xE6053077), /* PORT119CR */
-        PORTCR(120,     0xE6053078), /* PORT120CR */
-        PORTCR(121,     0xE6050079), /* PORT121CR */
-        PORTCR(122,     0xE605007A), /* PORT122CR */
-        PORTCR(123,     0xE605007B), /* PORT123CR */
-        PORTCR(124,     0xE605007C), /* PORT124CR */
-        PORTCR(125,     0xE605007D), /* PORT125CR */
-        PORTCR(126,     0xE605007E), /* PORT126CR */
-        PORTCR(127,     0xE605007F), /* PORT127CR */
-        PORTCR(128,     0xE6050080), /* PORT128CR */
-        PORTCR(129,     0xE6050081), /* PORT129CR */
-        PORTCR(130,     0xE6050082), /* PORT130CR */
-        PORTCR(131,     0xE6050083), /* PORT131CR */
-        PORTCR(132,     0xE6050084), /* PORT132CR */
-        PORTCR(133,     0xE6050085), /* PORT133CR */
-        PORTCR(134,     0xE6050086), /* PORT134CR */
-        PORTCR(135,     0xE6050087), /* PORT135CR */
-        PORTCR(136,     0xE6050088), /* PORT136CR */
-        PORTCR(137,     0xE6050089), /* PORT137CR */
-        PORTCR(138,     0xE605008A), /* PORT138CR */
-        PORTCR(139,     0xE605008B), /* PORT139CR */
-        PORTCR(140,     0xE605008C), /* PORT140CR */
-        PORTCR(141,     0xE605008D), /* PORT141CR */
-        PORTCR(142,     0xE605008E), /* PORT142CR */
-        PORTCR(143,     0xE605008F), /* PORT143CR */
-        PORTCR(144,     0xE6050090), /* PORT144CR */
-        PORTCR(145,     0xE6050091), /* PORT145CR */
-        PORTCR(146,     0xE6050092), /* PORT146CR */
-        PORTCR(147,     0xE6050093), /* PORT147CR */
-        PORTCR(148,     0xE6050094), /* PORT148CR */
-        PORTCR(149,     0xE6050095), /* PORT149CR */
-        PORTCR(150,     0xE6050096), /* PORT150CR */
-        PORTCR(151,     0xE6050097), /* PORT151CR */
-        PORTCR(152,     0xE6053098), /* PORT152CR */
-        PORTCR(153,     0xE6053099), /* PORT153CR */
-        PORTCR(154,     0xE605309A), /* PORT154CR */
-        PORTCR(155,     0xE605309B), /* PORT155CR */
-        PORTCR(156,     0xE605009C), /* PORT156CR */
-        PORTCR(157,     0xE605009D), /* PORT157CR */
-        PORTCR(158,     0xE605009E), /* PORT158CR */
-        PORTCR(159,     0xE605009F), /* PORT159CR */
-        PORTCR(160,     0xE60500A0), /* PORT160CR */
-        PORTCR(161,     0xE60500A1), /* PORT161CR */
-        PORTCR(162,     0xE60500A2), /* PORT162CR */
-        PORTCR(163,     0xE60500A3), /* PORT163CR */
-        PORTCR(164,     0xE60500A4), /* PORT164CR */
-        PORTCR(165,     0xE60500A5), /* PORT165CR */
-        PORTCR(166,     0xE60500A6), /* PORT166CR */
-        PORTCR(167,     0xE60520A7), /* PORT167CR */
-        PORTCR(168,     0xE60520A8), /* PORT168CR */
-        PORTCR(169,     0xE60520A9), /* PORT169CR */
-        PORTCR(170,     0xE60520AA), /* PORT170CR */
-        PORTCR(171,     0xE60520AB), /* PORT171CR */
-        PORTCR(172,     0xE60520AC), /* PORT172CR */
-        PORTCR(173,     0xE60520AD), /* PORT173CR */
-        PORTCR(174,     0xE60520AE), /* PORT174CR */
-        PORTCR(175,     0xE60520AF), /* PORT175CR */
-        PORTCR(176,     0xE60520B0), /* PORT176CR */
-        PORTCR(177,     0xE60520B1), /* PORT177CR */
-        PORTCR(178,     0xE60520B2), /* PORT178CR */
-        PORTCR(179,     0xE60520B3), /* PORT179CR */
-        PORTCR(180,     0xE60520B4), /* PORT180CR */
-        PORTCR(181,     0xE60520B5), /* PORT181CR */
-        PORTCR(182,     0xE60520B6), /* PORT182CR */
-        PORTCR(183,     0xE60520B7), /* PORT183CR */
-        PORTCR(184,     0xE60520B8), /* PORT184CR */
-        PORTCR(185,     0xE60520B9), /* PORT185CR */
-        PORTCR(186,     0xE60520BA), /* PORT186CR */
-        PORTCR(187,     0xE60520BB), /* PORT187CR */
-        PORTCR(188,     0xE60520BC), /* PORT188CR */
-        PORTCR(189,     0xE60520BD), /* PORT189CR */
-        PORTCR(190,     0xE60520BE), /* PORT190CR */
-        { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
-                        MSEL1CR_31_0,   MSEL1CR_31_1,
-                        MSEL1CR_30_0,   MSEL1CR_30_1,
-                        MSEL1CR_29_0,   MSEL1CR_29_1,
-                        MSEL1CR_28_0,   MSEL1CR_28_1,
-                        MSEL1CR_27_0,   MSEL1CR_27_1,
-                        MSEL1CR_26_0,   MSEL1CR_26_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        MSEL1CR_16_0,   MSEL1CR_16_1,
-                        MSEL1CR_15_0,   MSEL1CR_15_1,
-                        MSEL1CR_14_0,   MSEL1CR_14_1,
-                        MSEL1CR_13_0,   MSEL1CR_13_1,
-                        MSEL1CR_12_0,   MSEL1CR_12_1,
-                        0, 0, 0, 0,
-                        MSEL1CR_9_0,    MSEL1CR_9_1,
-                        MSEL1CR_8_0,    MSEL1CR_8_1,
-                        MSEL1CR_7_0,    MSEL1CR_7_1,
-                        MSEL1CR_6_0,    MSEL1CR_6_1,
-                        0, 0,
-                        MSEL1CR_4_0,    MSEL1CR_4_1,
-                        MSEL1CR_3_0,    MSEL1CR_3_1,
-                        MSEL1CR_2_0,    MSEL1CR_2_1,
-                        0, 0,
-                        MSEL1CR_0_0,    MSEL1CR_0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_27_0,   MSEL3CR_27_1,
-                        MSEL3CR_26_0,   MSEL3CR_26_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_21_0,   MSEL3CR_21_1,
-                        MSEL3CR_20_0,   MSEL3CR_20_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL3CR_15_0,   MSEL3CR_15_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL3CR_9_0,    MSEL3CR_9_1,
-                        0, 0, 0, 0,
-                        MSEL3CR_6_0,    MSEL3CR_6_1,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        MSEL4CR_19_0,   MSEL4CR_19_1,
-                        MSEL4CR_18_0,   MSEL4CR_18_1,
-                        MSEL4CR_17_0,   MSEL4CR_17_1,
-                        MSEL4CR_16_0,   MSEL4CR_16_1,
-                        MSEL4CR_15_0,   MSEL4CR_15_1,
-                        MSEL4CR_14_0,   MSEL4CR_14_1,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL4CR_10_0,   MSEL4CR_10_1,
-                        0, 0, 0, 0,
-                        0, 0,
-                        MSEL4CR_6_0,    MSEL4CR_6_1,
-                        0, 0,
-                        MSEL4CR_4_0,    MSEL4CR_4_1,
-                        0, 0, 0, 0,
-                        MSEL4CR_1_0,    MSEL4CR_1_1,
-                        0, 0,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
-                        PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
-                        PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        PORT99_DATA,  PORT98_DATA,  PORT97_DATA,  PORT96_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        0, 0, 0, 0,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0,            PORT166_DATA, PORT165_DATA, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA,  PORT8_DATA,
-                        PORT7_DATA,  PORT6_DATA,  PORT5_DATA,  PORT4_DATA,
-                        PORT3_DATA,  PORT2_DATA,  PORT1_DATA,  PORT0_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0,
-                        0,           0,           PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
-                }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
-                        0,            PORT190_DATA, PORT189_DATA, PORT188_DATA,
-                        PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
-                        PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
-                        PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
-                        PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
-                        PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
-                        PORT167_DATA, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT120_DATA,
-                        PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        0, 0, 0, 0,
-                }
-        },
-        { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
-                        0, 0, 0, 0,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                }
-        },
-        { },
-};
-#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
-#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
-};
-static struct pinmux_info sh7372_pinmux_info = {
-        .name = "sh7372_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_SDENC_DV_CLKI,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq = pinmux_irqs,
-        .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
-void sh7372_pinmux_init(void)
-{
-        register_pinmux(&sh7372_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
deleted file mode 100644
index b442f9d8c716..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ /dev/null
@@ -1,2803 +0,0 @@
-/*
- * sh73a0 processor support - PFC hardware block
- *
- * Copyright (C) 2010 Renesas Solutions Corp.
- * Copyright (C) 2010 NISHIMOTO Hiroki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh73a0.h>
-#include <mach/irqs.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx,    sfx), PORT_10(fn, pfx##1, sfx),     \
-        PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx),     \
-        PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx),     \
-        PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx),     \
-        PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx),     \
-        PORT_10(fn, pfx##10, sfx),                              \
-        PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),   \
-        PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),   \
-        PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),   \
-        PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),   \
-        PORT_1(fn, pfx##118, sfx),                              \
-        PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),   \
-        PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),   \
-        PORT_10(fn, pfx##15, sfx),                              \
-        PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),   \
-        PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),   \
-        PORT_1(fn, pfx##164, sfx),                              \
-        PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),   \
-        PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),   \
-        PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),   \
-        PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),   \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx),   \
-        PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx),   \
-        PORT_1(fn, pfx##282, sfx),                              \
-        PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx),   \
-        PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
-        PINMUX_INPUT_END,
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
-        PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
-        PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
-        PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
-        PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
-        PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
-        PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
-        PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
-        PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
-        PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
-        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* Hardware manual Table 25-1 (Function 0-7) */
-        VBUS_0_MARK,
-        GPI0_MARK,
-        GPI1_MARK,
-        GPI2_MARK,
-        GPI3_MARK,
-        GPI4_MARK,
-        GPI5_MARK,
-        GPI6_MARK,
-        GPI7_MARK,
-        SCIFA7_RXD_MARK,
-        SCIFA7_CTS__MARK,
-        GPO7_MARK, MFG0_OUT2_MARK,
-        GPO6_MARK, MFG1_OUT2_MARK,
-        GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
-        SCIFA0_TXD_MARK,
-        SCIFA7_TXD_MARK,
-        SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
-        GPO0_MARK,
-        GPO1_MARK,
-        GPO2_MARK, STATUS0_MARK,
-        GPO3_MARK, STATUS1_MARK,
-        GPO4_MARK, STATUS2_MARK,
-        VINT_MARK,
-        TCKON_MARK,
-        XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
-        MFG0_OUT1_MARK, PORT27_IROUT_MARK,
-        XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
-        PORT28_TPU1TO1_MARK,
-        SIM_RST_MARK, PORT29_TPU1TO1_MARK,
-        SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
-        SIM_D_MARK, PORT31_IROUT_MARK,
-        SCIFA4_TXD_MARK,
-        SCIFA4_RXD_MARK, XWUP_MARK,
-        SCIFA4_RTS__MARK,
-        SCIFA4_CTS__MARK,
-        FSIBOBT_MARK, FSIBIBT_MARK,
-        FSIBOLR_MARK, FSIBILR_MARK,
-        FSIBOSLD_MARK,
-        FSIBISLD_MARK,
-        VACK_MARK,
-        XTAL1L_MARK,
-        SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
-        SCIFA0_RXD_MARK,
-        SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
-        FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
-        FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
-        FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
-        FSICISLD_MARK, FSIDISLD_MARK,
-        FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
-        FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
-        FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
-        FSIAOSLD_MARK, BBIF2_TXD2_MARK,
-        FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
-        PORT53_FSICSPDIF_MARK,
-        FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
-        FSICCK_MARK, FSICOMC_MARK,
-        FSIAISLD_MARK, TPU0TO0_MARK,
-        A0_MARK, BS__MARK,
-        A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
-        A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
-        A14_MARK, KEYOUT5_MARK,
-        A15_MARK, KEYOUT4_MARK,
-        A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
-        A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
-        A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
-        A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
-        A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
-        A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
-        A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
-        A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
-        A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
-        A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, KEYIN6_MARK,
-        KEYIN7_MARK,
-        D0_NAF0_MARK,
-        D1_NAF1_MARK,
-        D2_NAF2_MARK,
-        D3_NAF3_MARK,
-        D4_NAF4_MARK,
-        D5_NAF5_MARK,
-        D6_NAF6_MARK,
-        D7_NAF7_MARK,
-        D8_NAF8_MARK,
-        D9_NAF9_MARK,
-        D10_NAF10_MARK,
-        D11_NAF11_MARK,
-        D12_NAF12_MARK,
-        D13_NAF13_MARK,
-        D14_NAF14_MARK,
-        D15_NAF15_MARK,
-        CS4__MARK,
-        CS5A__MARK, PORT91_RDWR_MARK,
-        CS5B__MARK, FCE1__MARK,
-        CS6B__MARK, DACK0_MARK,
-        FCE0__MARK, CS6A__MARK,
-        WAIT__MARK, DREQ0_MARK,
-        RD__FSC_MARK,
-        WE0__FWE_MARK, RDWR_FWE_MARK,
-        WE1__MARK,
-        FRB_MARK,
-        CKO_MARK,
-        NBRSTOUT__MARK,
-        NBRST__MARK,
-        BBIF2_TXD_MARK,
-        BBIF2_RXD_MARK,
-        BBIF2_SYNC_MARK,
-        BBIF2_SCK_MARK,
-        SCIFA3_CTS__MARK, MFG3_IN2_MARK,
-        SCIFA3_RXD_MARK, MFG3_IN1_MARK,
-        BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
-        SCIFA3_TXD_MARK,
-        HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
-        HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
-        HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
-        HSI_TX_READY_MARK, BBIF1_TXD_MARK,
-        HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
-        PORT115_I2C_SCL3_MARK,
-        HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
-        PORT116_I2C_SDA3_MARK,
-        HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
-        HSI_TX_FLAG_MARK,
-        VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
-        VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
-        VIO2_HD_MARK, LCD2D1_MARK,
-        VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
-        VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
-        PORT131_KEYOUT11_MARK, LCD2D11_MARK,
-        VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
-        PORT132_KEYOUT10_MARK, LCD2D12_MARK,
-        VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
-        VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
-        VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
-        VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
-        VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
-        VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
-        VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
-        VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
-        VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
-        VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
-        VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
-        VIO2_D5_MARK, LCD2D3_MARK,
-        VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
-        VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
-        PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
-        VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
-        LCD2D18_MARK,
-        VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
-        VIO_CKO_MARK,
-        A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
-        MFG0_IN2_MARK,
-        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
-        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
-        SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
-        SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
-        SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
-        SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
-        DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
-        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
-        PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
-        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
-        PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
-        LCDD0_MARK,
-        LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
-        LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
-        LCDD6_MARK,
-        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
-        LCDD8_MARK, D16_MARK,
-        LCDD9_MARK, D17_MARK,
-        LCDD10_MARK, D18_MARK,
-        LCDD11_MARK, D19_MARK,
-        LCDD12_MARK, D20_MARK,
-        LCDD13_MARK, D21_MARK,
-        LCDD14_MARK, D22_MARK,
-        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
-        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
-        LCDD17_MARK, D25_MARK,
-        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
-        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
-        LCDDCK_MARK, LCDWR__MARK,
-        LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
-        VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
-        LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
-        PORT218_VIO_CKOR_MARK,
-        LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
-        MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
-        LCDVSYN_MARK, LCDVSYN2_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
-        MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
-        VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
-        SCIFA1_TXD_MARK, OVCN2_MARK,
-        EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
-        SCIFA1_RTS__MARK, IDIN_MARK,
-        SCIFA1_RXD_MARK,
-        SCIFA1_CTS__MARK, MFG1_IN1_MARK,
-        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
-        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
-        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
-        MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
-        MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
-        MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
-        MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
-        MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
-        MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
-        SCIFA6_TXD_MARK,
-        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
-        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
-        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
-        PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
-        MSIOF2R_RXD_MARK,
-        PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
-        MSIOF2R_TXD_MARK,
-        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
-        TPU1TO0_MARK,
-        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
-        TPU3TO1_MARK,
-        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
-        TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
-        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
-        MSIOF2R_TSYNC_MARK,
-        SDHICLK0_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK,
-        SDHID0_1_MARK,
-        SDHID0_2_MARK,
-        SDHID0_3_MARK,
-        SDHICMD0_MARK,
-        SDHIWP0_MARK,
-        SDHICLK1_MARK,
-        SDHID1_0_MARK, TS_SPSYNC2_MARK,
-        SDHID1_1_MARK, TS_SDAT2_MARK,
-        SDHID1_2_MARK, TS_SDEN2_MARK,
-        SDHID1_3_MARK, TS_SCK2_MARK,
-        SDHICMD1_MARK,
-        SDHICLK2_MARK,
-        SDHID2_0_MARK, TS_SPSYNC4_MARK,
-        SDHID2_1_MARK, TS_SDAT4_MARK,
-        SDHID2_2_MARK, TS_SDEN4_MARK,
-        SDHID2_3_MARK, TS_SCK4_MARK,
-        SDHICMD2_MARK,
-        MMCCLK0_MARK,
-        MMCD0_0_MARK,
-        MMCD0_1_MARK,
-        MMCD0_2_MARK,
-        MMCD0_3_MARK,
-        MMCD0_4_MARK, TS_SPSYNC5_MARK,
-        MMCD0_5_MARK, TS_SDAT5_MARK,
-        MMCD0_6_MARK, TS_SDEN5_MARK,
-        MMCD0_7_MARK, TS_SCK5_MARK,
-        MMCCMD0_MARK,
-        RESETOUTS__MARK, EXTAL2OUT_MARK,
-        MCP_WAIT__MCP_FRB_MARK,
-        MCP_CKO_MARK, MMCCLK1_MARK,
-        MCP_D15_MCP_NAF15_MARK,
-        MCP_D14_MCP_NAF14_MARK,
-        MCP_D13_MCP_NAF13_MARK,
-        MCP_D12_MCP_NAF12_MARK,
-        MCP_D11_MCP_NAF11_MARK,
-        MCP_D10_MCP_NAF10_MARK,
-        MCP_D9_MCP_NAF9_MARK,
-        MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
-        MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
-        MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
-        MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
-        MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
-        MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
-        MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
-        MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
-        MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
-        MCP_NBRSTOUT__MARK,
-        MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
-        /* MSEL2 special cases */
-        TSIF2_TS_XX1_MARK,
-        TSIF2_TS_XX2_MARK,
-        TSIF2_TS_XX3_MARK,
-        TSIF2_TS_XX4_MARK,
-        TSIF2_TS_XX5_MARK,
-        TSIF1_TS_XX1_MARK,
-        TSIF1_TS_XX2_MARK,
-        TSIF1_TS_XX3_MARK,
-        TSIF1_TS_XX4_MARK,
-        TSIF1_TS_XX5_MARK,
-        TSIF0_TS_XX1_MARK,
-        TSIF0_TS_XX2_MARK,
-        TSIF0_TS_XX3_MARK,
-        TSIF0_TS_XX4_MARK,
-        TSIF0_TS_XX5_MARK,
-        MST1_TS_XX1_MARK,
-        MST1_TS_XX2_MARK,
-        MST1_TS_XX3_MARK,
-        MST1_TS_XX4_MARK,
-        MST1_TS_XX5_MARK,
-        MST0_TS_XX1_MARK,
-        MST0_TS_XX2_MARK,
-        MST0_TS_XX3_MARK,
-        MST0_TS_XX4_MARK,
-        MST0_TS_XX5_MARK,
-        /* MSEL3 special cases */
-        SDHI0_VCCQ_MC0_ON_MARK,
-        SDHI0_VCCQ_MC0_OFF_MARK,
-        DEBUG_MON_VIO_MARK,
-        DEBUG_MON_LCDD_MARK,
-        LCDC_LCDC0_MARK,
-        LCDC_LCDC1_MARK,
-        /* MSEL4 special cases */
-        IRQ9_MEM_INT_MARK,
-        IRQ9_MCP_INT_MARK,
-        A11_MARK,
-        KEYOUT8_MARK,
-        TPU4TO3_MARK,
-        RESETA_N_PU_ON_MARK,
-        RESETA_N_PU_OFF_MARK,
-        EDBGREQ_PD_MARK,
-        EDBGREQ_PU_MARK,
-        /* Functions with pull-ups */
-        KEYIN0_PU_MARK,
-        KEYIN1_PU_MARK,
-        KEYIN2_PU_MARK,
-        KEYIN3_PU_MARK,
-        KEYIN4_PU_MARK,
-        KEYIN5_PU_MARK,
-        KEYIN6_PU_MARK,
-        KEYIN7_PU_MARK,
-        SDHICD0_PU_MARK,
-        SDHID0_0_PU_MARK,
-        SDHID0_1_PU_MARK,
-        SDHID0_2_PU_MARK,
-        SDHID0_3_PU_MARK,
-        SDHICMD0_PU_MARK,
-        SDHIWP0_PU_MARK,
-        SDHID1_0_PU_MARK,
-        SDHID1_1_PU_MARK,
-        SDHID1_2_PU_MARK,
-        SDHID1_3_PU_MARK,
-        SDHICMD1_PU_MARK,
-        SDHID2_0_PU_MARK,
-        SDHID2_1_PU_MARK,
-        SDHID2_2_PU_MARK,
-        SDHID2_3_PU_MARK,
-        SDHICMD2_PU_MARK,
-        MMCCMD0_PU_MARK,
-        MMCCMD1_PU_MARK,
-        MMCD0_0_PU_MARK,
-        MMCD0_1_PU_MARK,
-        MMCD0_2_PU_MARK,
-        MMCD0_3_PU_MARK,
-        MMCD0_4_PU_MARK,
-        MMCD0_5_PU_MARK,
-        MMCD0_6_PU_MARK,
-        MMCD0_7_PU_MARK,
-        FSIBISLD_PU_MARK,
-        FSIACK_PU_MARK,
-        FSIAILR_PU_MARK,
-        FSIAIBT_PU_MARK,
-        FSIAISLD_PU_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* Table 25-1 (I/O and Pull U/D) */
-        PORT_DATA_I_PD(0),
-        PORT_DATA_I_PU(1),
-        PORT_DATA_I_PU(2),
-        PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4),
-        PORT_DATA_I_PU(5),
-        PORT_DATA_I_PU(6),
-        PORT_DATA_I_PU(7),
-        PORT_DATA_I_PU(8),
-        PORT_DATA_I_PD(9),
-        PORT_DATA_I_PD(10),
-        PORT_DATA_I_PU_PD(11),
-        PORT_DATA_IO_PU_PD(12),
-        PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PU_PD(14),
-        PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_IO_PD(16),
-        PORT_DATA_IO_PD(17),
-        PORT_DATA_IO_PU(18),
-        PORT_DATA_IO_PU(19),
-        PORT_DATA_O(20),
-        PORT_DATA_O(21),
-        PORT_DATA_O(22),
-        PORT_DATA_O(23),
-        PORT_DATA_O(24),
-        PORT_DATA_I_PD(25),
-        PORT_DATA_I_PD(26),
-        PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),
-        PORT_DATA_IO_PD(29),
-        PORT_DATA_IO_PD(30),
-        PORT_DATA_IO_PU(31),
-        PORT_DATA_IO_PD(32),
-        PORT_DATA_I_PU_PD(33),
-        PORT_DATA_IO_PD(34),
-        PORT_DATA_I_PU_PD(35),
-        PORT_DATA_IO_PD(36),
-        PORT_DATA_IO(37),
-        PORT_DATA_O(38),
-        PORT_DATA_I_PU(39),
-        PORT_DATA_I_PU_PD(40),
-        PORT_DATA_O(41),
-        PORT_DATA_IO_PD(42),
-        PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),
-        PORT_DATA_IO_PD(45),
-        PORT_DATA_IO_PD(46),
-        PORT_DATA_IO_PD(47),
-        PORT_DATA_I_PD(48),
-        PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PD(50),
-        PORT_DATA_IO_PD(51),
-        PORT_DATA_O(52),
-        PORT_DATA_IO_PU_PD(53),
-        PORT_DATA_IO_PU_PD(54),
-        PORT_DATA_IO_PD(55),
-        PORT_DATA_I_PU_PD(56),
-        PORT_DATA_IO(57),
-        PORT_DATA_IO(58),
-        PORT_DATA_IO(59),
-        PORT_DATA_IO(60),
-        PORT_DATA_IO(61),
-        PORT_DATA_IO_PD(62),
-        PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PU_PD(64),
-        PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),
-        PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),
-        PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70),
-        PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),
-        PORT_DATA_I_PU_PD(73),
-        PORT_DATA_IO_PU(74),
-        PORT_DATA_IO_PU(75),
-        PORT_DATA_IO_PU(76),
-        PORT_DATA_IO_PU(77),
-        PORT_DATA_IO_PU(78),
-        PORT_DATA_IO_PU(79),
-        PORT_DATA_IO_PU(80),
-        PORT_DATA_IO_PU(81),
-        PORT_DATA_IO_PU(82),
-        PORT_DATA_IO_PU(83),
-        PORT_DATA_IO_PU(84),
-        PORT_DATA_IO_PU(85),
-        PORT_DATA_IO_PU(86),
-        PORT_DATA_IO_PU(87),
-        PORT_DATA_IO_PU(88),
-        PORT_DATA_IO_PU(89),
-        PORT_DATA_O(90),
-        PORT_DATA_IO_PU(91),
-        PORT_DATA_O(92),
-        PORT_DATA_IO_PU(93),
-        PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO(96),
-        PORT_DATA_IO(97),
-        PORT_DATA_IO(98),
-        PORT_DATA_I_PU(99),
-        PORT_DATA_O(100),
-        PORT_DATA_O(101),
-        PORT_DATA_I_PU(102),
-        PORT_DATA_IO_PD(103),
-        PORT_DATA_I_PU_PD(104),
-        PORT_DATA_I_PD(105),
-        PORT_DATA_I_PD(106),
-        PORT_DATA_I_PU_PD(107),
-        PORT_DATA_I_PU_PD(108),
-        PORT_DATA_IO_PD(109),
-        PORT_DATA_IO_PD(110),
-        PORT_DATA_IO_PU_PD(111),
-        PORT_DATA_IO_PU_PD(112),
-        PORT_DATA_IO_PU_PD(113),
-        PORT_DATA_IO_PD(114),
-        PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),
-        PORT_DATA_IO_PU_PD(117),
-        PORT_DATA_IO_PU_PD(118),
-        PORT_DATA_IO_PD(128),
-        PORT_DATA_IO_PD(129),
-        PORT_DATA_IO_PU_PD(130),
-        PORT_DATA_IO_PD(131),
-        PORT_DATA_IO_PD(132),
-        PORT_DATA_IO_PD(133),
-        PORT_DATA_IO_PU_PD(134),
-        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PU_PD(136),
-        PORT_DATA_IO_PU_PD(137),
-        PORT_DATA_IO_PD(138),
-        PORT_DATA_IO_PD(139),
-        PORT_DATA_IO_PD(140),
-        PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),
-        PORT_DATA_IO_PD(143),
-        PORT_DATA_IO_PU_PD(144),
-        PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PU_PD(146),
-        PORT_DATA_IO_PU_PD(147),
-        PORT_DATA_IO_PU_PD(148),
-        PORT_DATA_IO_PU_PD(149),
-        PORT_DATA_I_PU_PD(150),
-        PORT_DATA_IO_PU_PD(151),
-        PORT_DATA_IO_PU_PD(152),
-        PORT_DATA_IO_PD(153),
-        PORT_DATA_IO_PD(154),
-        PORT_DATA_I_PU_PD(155),
-        PORT_DATA_IO_PU_PD(156),
-        PORT_DATA_I_PD(157),
-        PORT_DATA_IO_PD(158),
-        PORT_DATA_IO_PU_PD(159),
-        PORT_DATA_IO_PU_PD(160),
-        PORT_DATA_I_PU_PD(161),
-        PORT_DATA_I_PU_PD(162),
-        PORT_DATA_IO_PU_PD(163),
-        PORT_DATA_I_PU_PD(164),
-        PORT_DATA_IO_PD(192),
-        PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PD(194),
-        PORT_DATA_IO_PU_PD(195),
-        PORT_DATA_IO_PD(196),
-        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PD(198),
-        PORT_DATA_IO_PD(199),
-        PORT_DATA_IO_PU_PD(200),
-        PORT_DATA_IO_PU_PD(201),
-        PORT_DATA_IO_PU_PD(202),
-        PORT_DATA_IO_PU_PD(203),
-        PORT_DATA_IO_PU_PD(204),
-        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),
-        PORT_DATA_IO_PD(207),
-        PORT_DATA_IO_PD(208),
-        PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210),
-        PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212),
-        PORT_DATA_IO_PD(213),
-        PORT_DATA_IO_PU_PD(214),
-        PORT_DATA_IO_PU_PD(215),
-        PORT_DATA_IO_PD(216),
-        PORT_DATA_IO_PD(217),
-        PORT_DATA_O(218),
-        PORT_DATA_IO_PD(219),
-        PORT_DATA_IO_PD(220),
-        PORT_DATA_IO_PU_PD(221),
-        PORT_DATA_IO_PU_PD(222),
-        PORT_DATA_I_PU_PD(223),
-        PORT_DATA_I_PU_PD(224),
-        PORT_DATA_IO_PU_PD(225),
-        PORT_DATA_O(226),
-        PORT_DATA_IO_PU_PD(227),
-        PORT_DATA_I_PU_PD(228),
-        PORT_DATA_I_PD(229),
-        PORT_DATA_IO(230),
-        PORT_DATA_IO_PU_PD(231),
-        PORT_DATA_IO_PU_PD(232),
-        PORT_DATA_I_PU_PD(233),
-        PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_IO_PU_PD(235),
-        PORT_DATA_IO_PU_PD(236),
-        PORT_DATA_IO_PD(237),
-        PORT_DATA_IO_PU_PD(238),
-        PORT_DATA_IO_PU_PD(239),
-        PORT_DATA_IO_PU_PD(240),
-        PORT_DATA_O(241),
-        PORT_DATA_I_PD(242),
-        PORT_DATA_IO_PU_PD(243),
-        PORT_DATA_IO_PU_PD(244),
-        PORT_DATA_IO_PU_PD(245),
-        PORT_DATA_IO_PU_PD(246),
-        PORT_DATA_IO_PU_PD(247),
-        PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_IO_PU_PD(249),
-        PORT_DATA_IO_PU_PD(250),
-        PORT_DATA_IO_PU_PD(251),
-        PORT_DATA_IO_PU_PD(252),
-        PORT_DATA_IO_PU_PD(253),
-        PORT_DATA_IO_PU_PD(254),
-        PORT_DATA_IO_PU_PD(255),
-        PORT_DATA_IO_PU_PD(256),
-        PORT_DATA_IO_PU_PD(257),
-        PORT_DATA_IO_PU_PD(258),
-        PORT_DATA_IO_PU_PD(259),
-        PORT_DATA_IO_PU_PD(260),
-        PORT_DATA_IO_PU_PD(261),
-        PORT_DATA_IO_PU_PD(262),
-        PORT_DATA_IO_PU_PD(263),
-        PORT_DATA_IO_PU_PD(264),
-        PORT_DATA_IO_PU_PD(265),
-        PORT_DATA_IO_PU_PD(266),
-        PORT_DATA_IO_PU_PD(267),
-        PORT_DATA_IO_PU_PD(268),
-        PORT_DATA_IO_PU_PD(269),
-        PORT_DATA_IO_PU_PD(270),
-        PORT_DATA_IO_PU_PD(271),
-        PORT_DATA_IO_PU_PD(272),
-        PORT_DATA_IO_PU_PD(273),
-        PORT_DATA_IO_PU_PD(274),
-        PORT_DATA_IO_PU_PD(275),
-        PORT_DATA_IO_PU_PD(276),
-        PORT_DATA_IO_PU_PD(277),
-        PORT_DATA_IO_PU_PD(278),
-        PORT_DATA_IO_PU_PD(279),
-        PORT_DATA_IO_PU_PD(280),
-        PORT_DATA_O(281),
-        PORT_DATA_O(282),
-        PORT_DATA_I_PU(288),
-        PORT_DATA_IO_PU_PD(289),
-        PORT_DATA_IO_PU_PD(290),
-        PORT_DATA_IO_PU_PD(291),
-        PORT_DATA_IO_PU_PD(292),
-        PORT_DATA_IO_PU_PD(293),
-        PORT_DATA_IO_PU_PD(294),
-        PORT_DATA_IO_PU_PD(295),
-        PORT_DATA_IO_PU_PD(296),
-        PORT_DATA_IO_PU_PD(297),
-        PORT_DATA_IO_PU_PD(298),
-        PORT_DATA_IO_PU_PD(299),
-        PORT_DATA_IO_PU_PD(300),
-        PORT_DATA_IO_PU_PD(301),
-        PORT_DATA_IO_PU_PD(302),
-        PORT_DATA_IO_PU_PD(303),
-        PORT_DATA_IO_PU_PD(304),
-        PORT_DATA_IO_PU_PD(305),
-        PORT_DATA_O(306),
-        PORT_DATA_O(307),
-        PORT_DATA_I_PU(308),
-        PORT_DATA_O(309),
-        /* Table 25-1 (Function 0-7) */
-        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
-        PINMUX_DATA(GPI0_MARK, PORT1_FN1),
-        PINMUX_DATA(GPI1_MARK, PORT2_FN1),
-        PINMUX_DATA(GPI2_MARK, PORT3_FN1),
-        PINMUX_DATA(GPI3_MARK, PORT4_FN1),
-        PINMUX_DATA(GPI4_MARK, PORT5_FN1),
-        PINMUX_DATA(GPI5_MARK, PORT6_FN1),
-        PINMUX_DATA(GPI6_MARK, PORT7_FN1),
-        PINMUX_DATA(GPI7_MARK, PORT8_FN1),
-        PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
-        PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
-        PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
-        PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
-        PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
-        PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
-        PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
-        PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
-        PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
-        PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
-        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
-        PINMUX_DATA(GPO0_MARK, PORT20_FN1),
-        PINMUX_DATA(GPO1_MARK, PORT21_FN1),
-        PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(VINT_MARK, PORT25_FN1),
-        PINMUX_DATA(TCKON_MARK, PORT26_FN1),
-        PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
-        PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_1), \
-        PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_1), \
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
-        PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
-        PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
-        PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_1), \
-        PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_1), \
-        PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
-        PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
-        PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
-        PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
-        PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
-        PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
-        PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
-        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
-        PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
-        PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
-        PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
-        PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
-        PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
-        PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
-        PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
-        PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
-        PINMUX_DATA(VACK_MARK, PORT40_FN1),
-        PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
-        PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
-        PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
-        PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
-        PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
-        PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
-        PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
-        PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
-        PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
-        PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
-        PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
-        PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
-        PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
-        PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
-        PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
-        PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
-        PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
-        PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
-        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
-        PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
-        PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
-        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
-        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
-        PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
-        PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
-        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
-        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
-        PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
-        PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
-        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
-        PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
-        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
-        PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
-        PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
-        PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
-        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
-        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
-        PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
-        PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
-        PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
-        PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
-        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
-        PINMUX_DATA(A0_MARK, PORT57_FN1), \
-        PINMUX_DATA(BS__MARK, PORT57_FN2),
-        PINMUX_DATA(A12_MARK, PORT58_FN1), \
-        PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
-        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
-        PINMUX_DATA(A13_MARK, PORT59_FN1), \
-        PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
-        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
-        PINMUX_DATA(A14_MARK, PORT60_FN1), \
-        PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
-        PINMUX_DATA(A15_MARK, PORT61_FN1), \
-        PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
-        PINMUX_DATA(A16_MARK, PORT62_FN1), \
-        PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A17_MARK, PORT63_FN1), \
-        PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A18_MARK, PORT64_FN1), \
-        PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A19_MARK, PORT65_FN1), \
-        PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A20_MARK, PORT66_FN1), \
-        PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A21_MARK, PORT67_FN1), \
-        PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A22_MARK, PORT68_FN1), \
-        PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A23_MARK, PORT69_FN1), \
-        PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A24_MARK, PORT70_FN1), \
-        PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A25_MARK, PORT71_FN1), \
-        PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
-        PINMUX_DATA(A26_MARK, PORT72_FN1), \
-        PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
-        PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
-        PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
-        PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
-        PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
-        PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
-        PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
-        PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
-        PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
-        PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
-        PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
-        PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
-        PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
-        PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
-        PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
-        PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
-        PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
-        PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
-        PINMUX_DATA(CS4__MARK, PORT90_FN1),
-        PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
-        PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
-        PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
-        PINMUX_DATA(FCE1__MARK, PORT92_FN2),
-        PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
-        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
-        PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
-        PINMUX_DATA(CS6A__MARK, PORT94_FN2),
-        PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
-        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
-        PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
-        PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
-        PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
-        PINMUX_DATA(WE1__MARK, PORT98_FN1),
-        PINMUX_DATA(FRB_MARK, PORT99_FN1),
-        PINMUX_DATA(CKO_MARK, PORT100_FN1),
-        PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
-        PINMUX_DATA(NBRST__MARK, PORT102_FN1),
-        PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
-        PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
-        PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
-        PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
-        PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
-        PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
-        PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
-        PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
-        PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
-        PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
-        PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
-        PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
-        PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
-        PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
-        PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
-        PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
-        PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
-        PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
-        PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
-        PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
-        PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
-        PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
-        PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
-        PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
-        PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
-        PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
-        PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
-        PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
-        PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
-        PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
-        PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
-        PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
-        PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
-        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
-        PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
-        PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
-        PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
-        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
-        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
-                MSEL4CR_MSEL10_1), \
-        PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
-        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
-        PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
-        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
-        PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
-        PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
-        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
-        PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
-        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
-        PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
-        PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
-        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
-        PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
-        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
-        PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
-        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
-        PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
-        PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
-        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
-        PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
-        PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
-        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
-        PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
-        PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
-        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
-        PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
-        PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
-        PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
-        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
-        PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
-        PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
-        PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
-        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
-        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
-        PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
-        PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
-        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
-        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
-        PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
-        PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
-        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
-        PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
-        PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
-        PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
-        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
-        PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
-        PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
-        PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
-        PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
-        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
-        PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
-        PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
-        PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
-        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
-        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
-        PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
-        PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
-        PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
-        PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
-        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
-        PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
-        PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
-        PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
-        PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
-        PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
-        PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
-        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
-        PINMUX_DATA(A27_MARK, PORT149_FN1), \
-        PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
-        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
-        PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
-        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
-        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
-        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
-        PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
-        PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
-                MSEL4CR_MSEL10_0),
-        PINMUX_DATA(DINT__MARK, PORT158_FN1), \
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
-        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
-        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
-        PINMUX_DATA(NMI_MARK, PORT159_FN3),
-        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
-        PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
-        PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
-        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
-        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
-        PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
-        PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
-        PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
-        PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
-        PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
-        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
-        PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
-        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1),
-        PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
-        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_1), \
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
-        PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
-        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
-        PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
-        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
-        PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
-        PINMUX_DATA(D16_MARK, PORT200_FN6),
-        PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
-        PINMUX_DATA(D17_MARK, PORT201_FN6),
-        PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
-        PINMUX_DATA(D18_MARK, PORT202_FN6),
-        PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
-        PINMUX_DATA(D19_MARK, PORT203_FN6),
-        PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
-        PINMUX_DATA(D20_MARK, PORT204_FN6),
-        PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
-        PINMUX_DATA(D21_MARK, PORT205_FN6),
-        PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
-        PINMUX_DATA(D22_MARK, PORT206_FN6),
-        PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
-        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D23_MARK, PORT207_FN6),
-        PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
-        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D24_MARK, PORT208_FN6),
-        PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
-        PINMUX_DATA(D25_MARK, PORT209_FN6),
-        PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
-        PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
-        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D26_MARK, PORT210_FN6),
-        PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
-        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D27_MARK, PORT211_FN6),
-        PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D28_MARK, PORT212_FN6),
-        PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
-        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D29_MARK, PORT213_FN6),
-        PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
-        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D30_MARK, PORT214_FN6),
-        PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
-        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(D31_MARK, PORT215_FN6),
-        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
-        PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
-        PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
-        PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
-        PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
-        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
-        PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
-        PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
-        PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
-        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
-        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
-        PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
-        PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
-        PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
-        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
-        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
-        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
-        PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
-        PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
-        PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
-        PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
-        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
-        PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
-        PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
-        PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_1), \
-        PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
-        PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
-        PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
-        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
-        PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
-        PINMUX_DATA(IDIN_MARK, PORT227_FN4),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
-        PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
-        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
-        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
-        PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
-        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
-        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
-        PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
-        PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
-        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
-        PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
-        PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_0),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
-        PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
-                MSEL2CR_MSEL16_0),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
-        PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
-        PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
-                MSEL4CR_MSEL26_0), \
-        PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
-        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
-        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
-        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
-        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
-        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
-        PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
-        PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
-        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
-        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
-        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
-        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
-                MSEL4CR_MSEL20_0), \
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
-        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
-        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
-        PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
-        PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
-        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
-        PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
-        PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
-        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
-        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
-        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
-        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
-        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
-        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
-        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
-        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
-        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
-        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
-        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
-        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
-        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
-        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
-        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
-        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
-        PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
-        PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
-        PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
-        PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
-        PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
-        PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
-        PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
-        PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
-        PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
-        PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
-        PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
-        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
-        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
-        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
-                MSEL4CR_MSEL15_0), \
-        PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
-        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
-        PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
-        PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
-        PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
-        PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
-        PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
-        PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
-        PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
-        PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
-        PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
-        PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
-        PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
-        PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
-        PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
-        PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
-        PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
-        PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
-        PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
-        PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
-        PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
-        PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
-        PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
-        PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
-        /* MSEL2 special cases */
-        PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_1),
-        PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
-                MSEL2CR_MSEL12_1),
-        PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
-                MSEL2CR_MSEL12_0),
-        PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_1),
-        PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
-                MSEL2CR_MSEL9_1),
-        PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
-                MSEL2CR_MSEL9_0),
-        PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_1),
-        PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
-                MSEL2CR_MSEL6_1),
-        PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
-                MSEL2CR_MSEL6_0),
-        PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_1),
-        PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
-                MSEL2CR_MSEL3_1),
-        PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
-                MSEL2CR_MSEL3_0),
-        PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_0),
-        PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_1),
-        PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-                MSEL2CR_MSEL0_0),
-        PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
-                MSEL2CR_MSEL0_1),
-        PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
-                MSEL2CR_MSEL0_0),
-        /* MSEL3 special cases */
-        PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
-        PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
-        PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
-        PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
-        PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
-        PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
-        /* MSEL4 special cases */
-        PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
-        PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
-        PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
-        PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
-        PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
-        PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
-        PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
-        PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
-        PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
-        /* Functions with pull-ups */
-        PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
-        PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
-        PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
-        PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
-        PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
-        PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
-        PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
-        PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
-        PINMUX_DATA(SDHICD0_PU_MARK,  PORT251_FN1, PORT251_IN_PU),
-        PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
-        PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
-        PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
-        PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
-        PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHIWP0_PU_MARK,  PORT257_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
-        PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
-        PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
-        PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
-        PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
-        PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
-        PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
-        PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
-        PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
-        PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
-        PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
-                MSEL4CR_MSEL15_1),
-        PINMUX_DATA(MMCD0_0_PU_MARK,
-                    PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_PU_MARK,
-                    PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_PU_MARK,
-                    PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_PU_MARK,
-                    PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_PU_MARK,
-                    PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_5_PU_MARK,
-                    PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_6_PU_MARK,
-                    PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_7_PU_MARK,
-                    PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
-        PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
-        PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
-        PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
-        PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        GPIO_PORT_ALL(),
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(VBUS_0),
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(SCIFA7_RXD),
-        GPIO_FN(SCIFA7_CTS_),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(SCIFA0_SCK), \
-        GPIO_FN(FSICOSLDT3), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(SCIFA0_TXD),
-        GPIO_FN(SCIFA7_TXD),
-        GPIO_FN(SCIFA7_RTS_), \
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(PORT27_I2C_SCL2), \
-        GPIO_FN(PORT27_I2C_SCL3), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_I2C_SDA2), \
-        GPIO_FN(PORT28_I2C_SDA3), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(SCIFA4_TXD),
-        GPIO_FN(SCIFA4_RXD), \
-        GPIO_FN(XWUP),
-        GPIO_FN(SCIFA4_RTS_),
-        GPIO_FN(SCIFA4_CTS_),
-        GPIO_FN(FSIBOBT), \
-        GPIO_FN(FSIBIBT),
-        GPIO_FN(FSIBOLR), \
-        GPIO_FN(FSIBILR),
-        GPIO_FN(FSIBOSLD),
-        GPIO_FN(FSIBISLD),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(SCIFA0_RTS_), \
-        GPIO_FN(FSICOSLDT2),
-        GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(SCIFA0_CTS_), \
-        GPIO_FN(FSICOSLDT1),
-        GPIO_FN(FSICOBT), \
-        GPIO_FN(FSICIBT), \
-        GPIO_FN(FSIDOBT), \
-        GPIO_FN(FSIDIBT),
-        GPIO_FN(FSICOLR), \
-        GPIO_FN(FSICILR), \
-        GPIO_FN(FSIDOLR), \
-        GPIO_FN(FSIDILR),
-        GPIO_FN(FSICOSLD), \
-        GPIO_FN(PORT47_FSICSPDIF),
-        GPIO_FN(FSICISLD), \
-        GPIO_FN(FSIDISLD),
-        GPIO_FN(FSIACK), \
-        GPIO_FN(PORT49_IRDA_OUT), \
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAOBT), \
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(FSIAIBT),
-        GPIO_FN(FSIAOSLD), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(FSIASPDIF), \
-        GPIO_FN(PORT53_IRDA_IN), \
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(FSIBSPDIF), \
-        GPIO_FN(PORT53_FSICSPDIF),
-        GPIO_FN(FSIBCK), \
-        GPIO_FN(PORT54_IRDA_FIRSEL), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(FSIBOMC), \
-        GPIO_FN(FSICCK), \
-        GPIO_FN(FSICOMC),
-        GPIO_FN(FSIAISLD), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(PORT58_KEYOUT7), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(PORT59_KEYOUT6), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(KEYOUT5),
-        GPIO_FN(A15), \
-        GPIO_FN(KEYOUT4),
-        GPIO_FN(A16), \
-        GPIO_FN(KEYOUT3), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(KEYOUT2), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(KEYOUT1), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(KEYOUT0), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(KEYIN0), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(KEYIN1), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(KEYIN2), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(KEYIN3), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(KEYIN4), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(KEYIN5), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(KEYIN6),
-        GPIO_FN(KEYIN7),
-        GPIO_FN(D0_NAF0),
-        GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),
-        GPIO_FN(D3_NAF3),
-        GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),
-        GPIO_FN(D6_NAF6),
-        GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),
-        GPIO_FN(D9_NAF9),
-        GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),
-        GPIO_FN(D12_NAF12),
-        GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),
-        GPIO_FN(D15_NAF15),
-        GPIO_FN(CS4_),
-        GPIO_FN(CS5A_), \
-        GPIO_FN(PORT91_RDWR),
-        GPIO_FN(CS5B_), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(CS6B_), \
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(CS6A_),
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(RD__FSC),
-        GPIO_FN(WE0__FWE), \
-        GPIO_FN(RDWR_FWE),
-        GPIO_FN(WE1_),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(SCIFA3_CTS_), \
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(SCIFA3_RXD), \
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(SCIFA3_RTS_), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(PORT115_I2C_SCL2), \
-        GPIO_FN(PORT115_I2C_SCL3),
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(PORT116_I2C_SDA2), \
-        GPIO_FN(PORT116_I2C_SDA3),
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(PORT128_LCD2VSYN), \
-        GPIO_FN(VIO2_VD), \
-        GPIO_FN(LCD2D0),
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(PORT129_LCD2HSYN), \
-        GPIO_FN(PORT129_LCD2CS_), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(LCD2D1),
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(LCD2D10),
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_KEYOUT6), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(PORT131_KEYOUT11), \
-        GPIO_FN(LCD2D11),
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_KEYOUT7), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(PORT132_KEYOUT10), \
-        GPIO_FN(LCD2D12),
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(LCD2D13),
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(LCD2D14),
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(LCD2D15),
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(PORT136_KEYOUT8), \
-        GPIO_FN(LCD2D16),
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(PORT137_KEYOUT9), \
-        GPIO_FN(LCD2D17),
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(PORT138_KEYOUT8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(LCD2D6),
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(PORT139_KEYOUT9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(LCD2D7),
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(LCD2D8),
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(LCD2D9),
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(PORT142_KEYOUT10), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(LCD2D2),
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(PORT143_KEYOUT11), \
-        GPIO_FN(PORT143_KEYOUT6), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(LCD2D3),
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(PORT144_KEYOUT7), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(LCD2D4),
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(PORT145_LCD2DISP), \
-        GPIO_FN(PORT145_LCD2RS), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(LCD2D5),
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(LCD2DCK), \
-        GPIO_FN(PORT146_LCD2WR_), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(LCD2D18),
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(LCD2RD_), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(LCD2D19),
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(PORT149_RDWR), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(PORT149_KEYOUT9),
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(SCIFA2_TXD1), \
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(SCIFA2_RXD1), \
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(SCIFA2_RTS1_), \
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(SCIFA2_CTS1_), \
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(SCIFA2_SCK1), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(PORT159_SCIFB_SCK), \
-        GPIO_FN(PORT159_SCIFA5_SCK), \
-        GPIO_FN(NMI),
-        GPIO_FN(PORT160_SCIFB_TXD), \
-        GPIO_FN(PORT160_SCIFA5_TXD),
-        GPIO_FN(PORT161_SCIFB_CTS_), \
-        GPIO_FN(PORT161_SCIFA5_CTS_),
-        GPIO_FN(PORT162_SCIFB_RXD), \
-        GPIO_FN(PORT162_SCIFA5_RXD),
-        GPIO_FN(PORT163_SCIFB_RTS_), \
-        GPIO_FN(PORT163_SCIFA5_RTS_), \
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(LCDD0),
-        GPIO_FN(LCDD1), \
-        GPIO_FN(PORT193_SCIFA5_CTS_), \
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), \
-        GPIO_FN(PORT194_SCIFA5_RTS_), \
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), \
-        GPIO_FN(PORT195_SCIFA5_RXD), \
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), \
-        GPIO_FN(PORT196_SCIFA5_TXD),
-        GPIO_FN(LCDD5), \
-        GPIO_FN(PORT197_SCIFA5_SCK), \
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(LCDD6),
-        GPIO_FN(LCDD7), \
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(LCDD8), \
-        GPIO_FN(D16),
-        GPIO_FN(LCDD9), \
-        GPIO_FN(D17),
-        GPIO_FN(LCDD10), \
-        GPIO_FN(D18),
-        GPIO_FN(LCDD11), \
-        GPIO_FN(D19),
-        GPIO_FN(LCDD12), \
-        GPIO_FN(D20),
-        GPIO_FN(LCDD13), \
-        GPIO_FN(D21),
-        GPIO_FN(LCDD14), \
-        GPIO_FN(D22),
-        GPIO_FN(LCDD15), \
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(LCDD16), \
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(LCDD17), \
-        GPIO_FN(D25),
-        GPIO_FN(LCDD18), \
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(LCDD19), \
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(LCDD20), \
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(LCDD21), \
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(LCDD22), \
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(LCDD23), \
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(LCDDCK), \
-        GPIO_FN(LCDWR_),
-        GPIO_FN(LCDRD_), \
-        GPIO_FN(DACK2), \
-        GPIO_FN(PORT217_LCD2RS), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(PORT217_LCD2DISP),
-        GPIO_FN(LCDHSYN), \
-        GPIO_FN(LCDCS_), \
-        GPIO_FN(LCDCS2_), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(LCDDISP), \
-        GPIO_FN(LCDRS), \
-        GPIO_FN(PORT219_LCD2WR_), \
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(LCD2DCK_2),
-        GPIO_FN(LCDVSYN), \
-        GPIO_FN(LCDVSYN2),
-        GPIO_FN(LCDLCLK), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PORT221_LCD2CS_), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(PORT221_LCD2HSYN),
-        GPIO_FN(LCDDON), \
-        GPIO_FN(LCDDON2), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-        GPIO_FN(PORT222_LCD2VSYN),
-        GPIO_FN(SCIFA1_TXD), \
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(SCIFA1_SCK), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(SCIFA1_RTS_), \
-        GPIO_FN(IDIN),
-        GPIO_FN(SCIFA1_RXD),
-        GPIO_FN(SCIFA1_CTS_), \
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(SCIFA2_TXD2),
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(SCIFA2_CTS2_),
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(SCIFA2_SCK2),
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(SCIFA2_RXD2),
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(SCIFA2_RTS2_), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(LCD2D20),
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(LCD2D21),
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(PORT236_I2C_SDA2),
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(PORT237_I2C_SCL2),
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(LCD2D22),
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(LCD2D23),
-        GPIO_FN(SCIFA6_TXD),
-        GPIO_FN(PORT241_IRDA_OUT), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(PORT242_IRDA_IN), \
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_IRDA_FIRSEL), \
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(PORT244_SCIFA5_CTS_), \
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(PORT244_SCIFB_CTS_), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(PORT245_SCIFA5_RTS_), \
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(PORT245_SCIFB_RTS_), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(PORT246_SCIFA5_RXD), \
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(PORT246_SCIFB_RXD), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(PORT247_SCIFA5_TXD), \
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(PORT247_SCIFB_TXD), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(PORT248_SCIFA5_SCK), \
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(PORT248_SCIFB_SCK), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(PORT248_I2C_SCL3), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(PORT249_I2C_SDA3), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(KEYOUT8),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-        /* Functions with pull-ups */
-        GPIO_FN(KEYIN0_PU),
-        GPIO_FN(KEYIN1_PU),
-        GPIO_FN(KEYIN2_PU),
-        GPIO_FN(KEYIN3_PU),
-        GPIO_FN(KEYIN4_PU),
-        GPIO_FN(KEYIN5_PU),
-        GPIO_FN(KEYIN6_PU),
-        GPIO_FN(KEYIN7_PU),
-        GPIO_FN(SDHICD0_PU),
-        GPIO_FN(SDHID0_0_PU),
-        GPIO_FN(SDHID0_1_PU),
-        GPIO_FN(SDHID0_2_PU),
-        GPIO_FN(SDHID0_3_PU),
-        GPIO_FN(SDHICMD0_PU),
-        GPIO_FN(SDHIWP0_PU),
-        GPIO_FN(SDHID1_0_PU),
-        GPIO_FN(SDHID1_1_PU),
-        GPIO_FN(SDHID1_2_PU),
-        GPIO_FN(SDHID1_3_PU),
-        GPIO_FN(SDHICMD1_PU),
-        GPIO_FN(SDHID2_0_PU),
-        GPIO_FN(SDHID2_1_PU),
-        GPIO_FN(SDHID2_2_PU),
-        GPIO_FN(SDHID2_3_PU),
-        GPIO_FN(SDHICMD2_PU),
-        GPIO_FN(MMCCMD0_PU),
-        GPIO_FN(MMCCMD1_PU),
-        GPIO_FN(MMCD0_0_PU),
-        GPIO_FN(MMCD0_1_PU),
-        GPIO_FN(MMCD0_2_PU),
-        GPIO_FN(MMCD0_3_PU),
-        GPIO_FN(MMCD0_4_PU),
-        GPIO_FN(MMCD0_5_PU),
-        GPIO_FN(MMCD0_6_PU),
-        GPIO_FN(MMCD0_7_PU),
-        GPIO_FN(FSIACK_PU),
-        GPIO_FN(FSIAILR_PU),
-        GPIO_FN(FSIAIBT_PU),
-        GPIO_FN(FSIAISLD_PU),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6051020), /* PORT32CR */
-        PORTCR(33, 0xe6051021), /* PORT33CR */
-        PORTCR(34, 0xe6051022), /* PORT34CR */
-        PORTCR(35, 0xe6051023), /* PORT35CR */
-        PORTCR(36, 0xe6051024), /* PORT36CR */
-        PORTCR(37, 0xe6051025), /* PORT37CR */
-        PORTCR(38, 0xe6051026), /* PORT38CR */
-        PORTCR(39, 0xe6051027), /* PORT39CR */
-        PORTCR(40, 0xe6051028), /* PORT40CR */
-        PORTCR(41, 0xe6051029), /* PORT41CR */
-        PORTCR(42, 0xe605102a), /* PORT42CR */
-        PORTCR(43, 0xe605102b), /* PORT43CR */
-        PORTCR(44, 0xe605102c), /* PORT44CR */
-        PORTCR(45, 0xe605102d), /* PORT45CR */
-        PORTCR(46, 0xe605102e), /* PORT46CR */
-        PORTCR(47, 0xe605102f), /* PORT47CR */
-        PORTCR(48, 0xe6051030), /* PORT48CR */
-        PORTCR(49, 0xe6051031), /* PORT49CR */
-        PORTCR(50, 0xe6051032), /* PORT50CR */
-        PORTCR(51, 0xe6051033), /* PORT51CR */
-        PORTCR(52, 0xe6051034), /* PORT52CR */
-        PORTCR(53, 0xe6051035), /* PORT53CR */
-        PORTCR(54, 0xe6051036), /* PORT54CR */
-        PORTCR(55, 0xe6051037), /* PORT55CR */
-        PORTCR(56, 0xe6051038), /* PORT56CR */
-        PORTCR(57, 0xe6051039), /* PORT57CR */
-        PORTCR(58, 0xe605103a), /* PORT58CR */
-        PORTCR(59, 0xe605103b), /* PORT59CR */
-        PORTCR(60, 0xe605103c), /* PORT60CR */
-        PORTCR(61, 0xe605103d), /* PORT61CR */
-        PORTCR(62, 0xe605103e), /* PORT62CR */
-        PORTCR(63, 0xe605103f), /* PORT63CR */
-        PORTCR(64, 0xe6051040), /* PORT64CR */
-        PORTCR(65, 0xe6051041), /* PORT65CR */
-        PORTCR(66, 0xe6051042), /* PORT66CR */
-        PORTCR(67, 0xe6051043), /* PORT67CR */
-        PORTCR(68, 0xe6051044), /* PORT68CR */
-        PORTCR(69, 0xe6051045), /* PORT69CR */
-        PORTCR(70, 0xe6051046), /* PORT70CR */
-        PORTCR(71, 0xe6051047), /* PORT71CR */
-        PORTCR(72, 0xe6051048), /* PORT72CR */
-        PORTCR(73, 0xe6051049), /* PORT73CR */
-        PORTCR(74, 0xe605104a), /* PORT74CR */
-        PORTCR(75, 0xe605104b), /* PORT75CR */
-        PORTCR(76, 0xe605104c), /* PORT76CR */
-        PORTCR(77, 0xe605104d), /* PORT77CR */
-        PORTCR(78, 0xe605104e), /* PORT78CR */
-        PORTCR(79, 0xe605104f), /* PORT79CR */
-        PORTCR(80, 0xe6051050), /* PORT80CR */
-        PORTCR(81, 0xe6051051), /* PORT81CR */
-        PORTCR(82, 0xe6051052), /* PORT82CR */
-        PORTCR(83, 0xe6051053), /* PORT83CR */
-        PORTCR(84, 0xe6051054), /* PORT84CR */
-        PORTCR(85, 0xe6051055), /* PORT85CR */
-        PORTCR(86, 0xe6051056), /* PORT86CR */
-        PORTCR(87, 0xe6051057), /* PORT87CR */
-        PORTCR(88, 0xe6051058), /* PORT88CR */
-        PORTCR(89, 0xe6051059), /* PORT89CR */
-        PORTCR(90, 0xe605105a), /* PORT90CR */
-        PORTCR(91, 0xe605105b), /* PORT91CR */
-        PORTCR(92, 0xe605105c), /* PORT92CR */
-        PORTCR(93, 0xe605105d), /* PORT93CR */
-        PORTCR(94, 0xe605105e), /* PORT94CR */
-        PORTCR(95, 0xe605105f), /* PORT95CR */
-        PORTCR(96, 0xe6052060), /* PORT96CR */
-        PORTCR(97, 0xe6052061), /* PORT97CR */
-        PORTCR(98, 0xe6052062), /* PORT98CR */
-        PORTCR(99, 0xe6052063), /* PORT99CR */
-        PORTCR(100, 0xe6052064), /* PORT100CR */
-        PORTCR(101, 0xe6052065), /* PORT101CR */
-        PORTCR(102, 0xe6052066), /* PORT102CR */
-        PORTCR(103, 0xe6052067), /* PORT103CR */
-        PORTCR(104, 0xe6052068), /* PORT104CR */
-        PORTCR(105, 0xe6052069), /* PORT105CR */
-        PORTCR(106, 0xe605206a), /* PORT106CR */
-        PORTCR(107, 0xe605206b), /* PORT107CR */
-        PORTCR(108, 0xe605206c), /* PORT108CR */
-        PORTCR(109, 0xe605206d), /* PORT109CR */
-        PORTCR(110, 0xe605206e), /* PORT110CR */
-        PORTCR(111, 0xe605206f), /* PORT111CR */
-        PORTCR(112, 0xe6052070), /* PORT112CR */
-        PORTCR(113, 0xe6052071), /* PORT113CR */
-        PORTCR(114, 0xe6052072), /* PORT114CR */
-        PORTCR(115, 0xe6052073), /* PORT115CR */
-        PORTCR(116, 0xe6052074), /* PORT116CR */
-        PORTCR(117, 0xe6052075), /* PORT117CR */
-        PORTCR(118, 0xe6052076), /* PORT118CR */
-        PORTCR(128, 0xe6052080), /* PORT128CR */
-        PORTCR(129, 0xe6052081), /* PORT129CR */
-        PORTCR(130, 0xe6052082), /* PORT130CR */
-        PORTCR(131, 0xe6052083), /* PORT131CR */
-        PORTCR(132, 0xe6052084), /* PORT132CR */
-        PORTCR(133, 0xe6052085), /* PORT133CR */
-        PORTCR(134, 0xe6052086), /* PORT134CR */
-        PORTCR(135, 0xe6052087), /* PORT135CR */
-        PORTCR(136, 0xe6052088), /* PORT136CR */
-        PORTCR(137, 0xe6052089), /* PORT137CR */
-        PORTCR(138, 0xe605208a), /* PORT138CR */
-        PORTCR(139, 0xe605208b), /* PORT139CR */
-        PORTCR(140, 0xe605208c), /* PORT140CR */
-        PORTCR(141, 0xe605208d), /* PORT141CR */
-        PORTCR(142, 0xe605208e), /* PORT142CR */
-        PORTCR(143, 0xe605208f), /* PORT143CR */
-        PORTCR(144, 0xe6052090), /* PORT144CR */
-        PORTCR(145, 0xe6052091), /* PORT145CR */
-        PORTCR(146, 0xe6052092), /* PORT146CR */
-        PORTCR(147, 0xe6052093), /* PORT147CR */
-        PORTCR(148, 0xe6052094), /* PORT148CR */
-        PORTCR(149, 0xe6052095), /* PORT149CR */
-        PORTCR(150, 0xe6052096), /* PORT150CR */
-        PORTCR(151, 0xe6052097), /* PORT151CR */
-        PORTCR(152, 0xe6052098), /* PORT152CR */
-        PORTCR(153, 0xe6052099), /* PORT153CR */
-        PORTCR(154, 0xe605209a), /* PORT154CR */
-        PORTCR(155, 0xe605209b), /* PORT155CR */
-        PORTCR(156, 0xe605209c), /* PORT156CR */
-        PORTCR(157, 0xe605209d), /* PORT157CR */
-        PORTCR(158, 0xe605209e), /* PORT158CR */
-        PORTCR(159, 0xe605209f), /* PORT159CR */
-        PORTCR(160, 0xe60520a0), /* PORT160CR */
-        PORTCR(161, 0xe60520a1), /* PORT161CR */
-        PORTCR(162, 0xe60520a2), /* PORT162CR */
-        PORTCR(163, 0xe60520a3), /* PORT163CR */
-        PORTCR(164, 0xe60520a4), /* PORT164CR */
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60530e0), /* PORT224CR */
-        PORTCR(225, 0xe60530e1), /* PORT225CR */
-        PORTCR(226, 0xe60530e2), /* PORT226CR */
-        PORTCR(227, 0xe60530e3), /* PORT227CR */
-        PORTCR(228, 0xe60530e4), /* PORT228CR */
-        PORTCR(229, 0xe60530e5), /* PORT229CR */
-        PORTCR(230, 0xe60530e6), /* PORT230CR */
-        PORTCR(231, 0xe60530e7), /* PORT231CR */
-        PORTCR(232, 0xe60530e8), /* PORT232CR */
-        PORTCR(233, 0xe60530e9), /* PORT233CR */
-        PORTCR(234, 0xe60530ea), /* PORT234CR */
-        PORTCR(235, 0xe60530eb), /* PORT235CR */
-        PORTCR(236, 0xe60530ec), /* PORT236CR */
-        PORTCR(237, 0xe60530ed), /* PORT237CR */
-        PORTCR(238, 0xe60530ee), /* PORT238CR */
-        PORTCR(239, 0xe60530ef), /* PORT239CR */
-        PORTCR(240, 0xe60530f0), /* PORT240CR */
-        PORTCR(241, 0xe60530f1), /* PORT241CR */
-        PORTCR(242, 0xe60530f2), /* PORT242CR */
-        PORTCR(243, 0xe60530f3), /* PORT243CR */
-        PORTCR(244, 0xe60530f4), /* PORT244CR */
-        PORTCR(245, 0xe60530f5), /* PORT245CR */
-        PORTCR(246, 0xe60530f6), /* PORT246CR */
-        PORTCR(247, 0xe60530f7), /* PORT247CR */
-        PORTCR(248, 0xe60530f8), /* PORT248CR */
-        PORTCR(249, 0xe60530f9), /* PORT249CR */
-        PORTCR(250, 0xe60530fa), /* PORT250CR */
-        PORTCR(251, 0xe60530fb), /* PORT251CR */
-        PORTCR(252, 0xe60530fc), /* PORT252CR */
-        PORTCR(253, 0xe60530fd), /* PORT253CR */
-        PORTCR(254, 0xe60530fe), /* PORT254CR */
-        PORTCR(255, 0xe60530ff), /* PORT255CR */
-        PORTCR(256, 0xe6053100), /* PORT256CR */
-        PORTCR(257, 0xe6053101), /* PORT257CR */
-        PORTCR(258, 0xe6053102), /* PORT258CR */
-        PORTCR(259, 0xe6053103), /* PORT259CR */
-        PORTCR(260, 0xe6053104), /* PORT260CR */
-        PORTCR(261, 0xe6053105), /* PORT261CR */
-        PORTCR(262, 0xe6053106), /* PORT262CR */
-        PORTCR(263, 0xe6053107), /* PORT263CR */
-        PORTCR(264, 0xe6053108), /* PORT264CR */
-        PORTCR(265, 0xe6053109), /* PORT265CR */
-        PORTCR(266, 0xe605310a), /* PORT266CR */
-        PORTCR(267, 0xe605310b), /* PORT267CR */
-        PORTCR(268, 0xe605310c), /* PORT268CR */
-        PORTCR(269, 0xe605310d), /* PORT269CR */
-        PORTCR(270, 0xe605310e), /* PORT270CR */
-        PORTCR(271, 0xe605310f), /* PORT271CR */
-        PORTCR(272, 0xe6053110), /* PORT272CR */
-        PORTCR(273, 0xe6053111), /* PORT273CR */
-        PORTCR(274, 0xe6053112), /* PORT274CR */
-        PORTCR(275, 0xe6053113), /* PORT275CR */
-        PORTCR(276, 0xe6053114), /* PORT276CR */
-        PORTCR(277, 0xe6053115), /* PORT277CR */
-        PORTCR(278, 0xe6053116), /* PORT278CR */
-        PORTCR(279, 0xe6053117), /* PORT279CR */
-        PORTCR(280, 0xe6053118), /* PORT280CR */
-        PORTCR(281, 0xe6053119), /* PORT281CR */
-        PORTCR(282, 0xe605311a), /* PORT282CR */
-        PORTCR(288, 0xe6052120), /* PORT288CR */
-        PORTCR(289, 0xe6052121), /* PORT289CR */
-        PORTCR(290, 0xe6052122), /* PORT290CR */
-        PORTCR(291, 0xe6052123), /* PORT291CR */
-        PORTCR(292, 0xe6052124), /* PORT292CR */
-        PORTCR(293, 0xe6052125), /* PORT293CR */
-        PORTCR(294, 0xe6052126), /* PORT294CR */
-        PORTCR(295, 0xe6052127), /* PORT295CR */
-        PORTCR(296, 0xe6052128), /* PORT296CR */
-        PORTCR(297, 0xe6052129), /* PORT297CR */
-        PORTCR(298, 0xe605212a), /* PORT298CR */
-        PORTCR(299, 0xe605212b), /* PORT299CR */
-        PORTCR(300, 0xe605212c), /* PORT300CR */
-        PORTCR(301, 0xe605212d), /* PORT301CR */
-        PORTCR(302, 0xe605212e), /* PORT302CR */
-        PORTCR(303, 0xe605212f), /* PORT303CR */
-        PORTCR(304, 0xe6052130), /* PORT304CR */
-        PORTCR(305, 0xe6052131), /* PORT305CR */
-        PORTCR(306, 0xe6052132), /* PORT306CR */
-        PORTCR(307, 0xe6052133), /* PORT307CR */
-        PORTCR(308, 0xe6052134), /* PORT308CR */
-        PORTCR(309, 0xe6052135), /* PORT309CR */
-        { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
-                        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
-                        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
-                        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
-                        0, 0,
-                        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
-                        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
-                        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
-                        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
-                        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
-                        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
-                        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
-                        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
-                        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
-                        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
-                        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
-                        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
-                        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
-                        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
-                        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
-                        0, 0,
-                        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
-                        0, 0,
-                        0, 0,
-                }
-        },
-        { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
-                        0, 0,
-                        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
-                        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
-                        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
-                        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
-                        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
-                        0, 0,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
-                        0, 0,
-                        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
-                        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
-                        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
-                        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
-                        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
-                        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
-                        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
-                        0, 0,
-                        0, 0,
-                        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
-                        0, 0,
-                }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
-                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
-                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
-                        0, 0, 0, 0,
-                        0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
-                        PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
-                        PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
-                        PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-                        PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, PORT309_DATA, PORT308_DATA,
-                        PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
-                        PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
-                        PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
-                        PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
-                        PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
-        },
-        { },
-};
-/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
-#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
-#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
-};
-static struct pinmux_info sh73a0_pinmux_info = {
-        .name = "sh73a0_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_FSIAISLD_PU,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-        .gpio_irq = pinmux_irqs,
-        .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
-};
-void sh73a0_pinmux_init(void)
-{
-        register_pinmux(&sh73a0_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index ed8d2351915e..1f958d7b0bac 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -12,7 +12,6 @@
 */
 #include <linux/init.h>
 #include <linux/smp.h>
-#include <asm/hardware/gic.h>
 void __init shmobile_smp_init_cpus(unsigned int ncores)
 {
@@ -26,6 +25,4 @@ void __init shmobile_smp_init_cpus(unsigned int ncores)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 21e5316d2d88..40b87aa1d448 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -9,7 +9,9 @@
 * for more details.
 */
 #include <linux/console.h>
+#include <linux/suspend.h>
 #include <mach/pm-rmobile.h>
+#include <mach/common.h>
 #ifdef CONFIG_PM
 static int r8a7740_pd_a4s_suspend(void)
@@ -58,3 +60,23 @@ void __init r8a7740_init_pm_domains(void)
 }
 #endif /* CONFIG_PM */
+#ifdef CONFIG_SUSPEND
+static int r8a7740_enter_suspend(suspend_state_t suspend_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static void r8a7740_suspend_init(void)
+{
+        shmobile_suspend_ops.enter = r8a7740_enter_suspend;
+}
+#else
+static void r8a7740_suspend_init(void) {}
+#endif
+void __init r8a7740_pm_init(void)
+{
+        r8a7740_suspend_init();
+}
diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c
new file mode 100644
index 000000000000..99086e98fbbc
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-sh73a0.c
@@ -0,0 +1,32 @@
+/*
+ * sh73a0 Power management support
+ *
+ *  Copyright (C) 2012 Bastian Hecht <hechtb+renesas@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/suspend.h>
+#include <mach/common.h>
+#ifdef CONFIG_SUSPEND
+static int sh73a0_enter_suspend(suspend_state_t suspend_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static void sh73a0_suspend_init(void)
+{
+        shmobile_suspend_ops.enter = sh73a0_enter_suspend;
+}
+#else
+static void sh73a0_suspend_init(void) {}
+#endif
+void __init sh73a0_pm_init(void)
+{
+        sh73a0_suspend_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index a47beeb18283..47662a581c0a 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,13 +20,14 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
@@ -35,7 +36,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
 static struct map_desc emev2_io_desc[] __initdata = {
 #ifdef CONFIG_SMP
@@ -445,29 +445,18 @@ void __init emev2_add_standard_devices_dt(void)
                             emev2_auxdata_lookup, NULL);
 }
-static const struct of_device_id emev2_dt_irq_match[] = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {},
-};
 static const char *emev2_boards_compat_dt[] __initdata = {
        "renesas,emev2",
        NULL,
 };
-void __init emev2_init_irq_dt(void)
-{
-        of_irq_init(emev2_dt_irq_match);
-}
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
        .smp            = smp_ops(emev2_smp_ops),
        .init_early     = emev2_init_delay,
        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = emev2_init_irq_dt,
+        .init_irq       = irqchip_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = emev2_add_standard_devices_dt,
-        .timer          = &shmobile_timer,
+        .init_time      = shmobile_timer_init,
        .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 095222469d03..8b85d4d8fab6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -27,7 +27,7 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <linux/dma-mapping.h>
+#include <linux/platform_data/sh_ipmmu.h>
 #include <mach/dma-register.h>
 #include <mach/r8a7740.h>
 #include <mach/pm-rmobile.h>
@@ -68,6 +68,32 @@ void __init r8a7740_map_io(void)
        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
 }
+/* PFC */
+static struct resource r8a7740_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605800c,
+                .end    = 0xe605802b,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device r8a7740_pfc_device = {
+        .name           = "pfc-r8a7740",
+        .id             = -1,
+        .resource       = r8a7740_pfc_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+};
+void __init r8a7740_pinmux_init(void)
+{
+        platform_device_register(&r8a7740_pfc_device);
+}
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
@@ -262,6 +288,128 @@ static struct platform_device cmt10_device = {
        .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+        .name = "TMU00",
+        .channel_offset = 0x4,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+static struct resource tmu00_resources[] = {
+        [0] = {
+                .name   = "TMU00",
+                .start  = 0xfff80008,
+                .end    = 0xfff80014 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xe80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device tmu00_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu00_platform_data,
+        },
+        .resource       = tmu00_resources,
+        .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+static struct sh_timer_config tmu01_platform_data = {
+        .name = "TMU01",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+static struct resource tmu01_resources[] = {
+        [0] = {
+                .name   = "TMU01",
+                .start  = 0xfff80014,
+                .end    = 0xfff80020 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xea0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device tmu01_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu01_platform_data,
+        },
+        .resource       = tmu01_resources,
+        .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+static struct sh_timer_config tmu02_platform_data = {
+        .name = "TMU02",
+        .channel_offset = 0x1C,
+        .timer_bit = 2,
+        .clocksource_rating = 200,
+};
+static struct resource tmu02_resources[] = {
+        [0] = {
+                .name   = "TMU02",
+                .start  = 0xfff80020,
+                .end    = 0xfff8002C - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xec0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device tmu02_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu02_platform_data,
+        },
+        .resource       = tmu02_resources,
+        .num_resources  = ARRAY_SIZE(tmu02_resources),
+};
+/* IPMMUI (an IPMMU module for ICB/LMB) */
+static struct resource ipmmu_resources[] = {
+        [0] = {
+                .name   = "IPMMUI",
+                .start  = 0xfe951000,
+                .end    = 0xfe9510ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static const char * const ipmmu_dev_names[] = {
+        "sh_mobile_lcdc_fb.0",
+        "sh_mobile_lcdc_fb.1",
+        "sh_mobile_ceu.0",
+};
+static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
+        .dev_names = ipmmu_dev_names,
+        .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
+};
+static struct platform_device ipmmu_device = {
+        .name           = "ipmmu",
+        .id             = -1,
+        .dev = {
+                .platform_data = &ipmmu_platform_data,
+        },
+        .resource       = ipmmu_resources,
+        .num_resources  = ARRAY_SIZE(ipmmu_resources),
+};
 static struct platform_device *r8a7740_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -273,6 +421,10 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
        &scif7_device,
        &scifb_device,
        &cmt10_device,
+        &tmu00_device,
+        &tmu01_device,
+        &tmu02_device,
+        &ipmmu_device,
 };
 /* DMA */
@@ -705,12 +857,6 @@ void __init r8a7740_add_standard_devices(void)
        rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 }
-static void __init r8a7740_earlytimer_init(void)
-{
-        r8a7740_clock_init(0);
-        shmobile_earlytimer_init();
-}
 void __init r8a7740_add_early_devices(void)
 {
        early_platform_add_devices(r8a7740_early_devices,
@@ -718,9 +864,6 @@ void __init r8a7740_add_early_devices(void)
        /* setup early console here as well */
        shmobile_setup_console();
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = r8a7740_earlytimer_init;
 }
 #ifdef CONFIG_USE_OF
@@ -763,7 +906,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
        .init_irq       = r8a7740_init_irq,
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = r8a7740_add_standard_devices_dt,
-        .timer          = &shmobile_timer,
+        .init_time      = shmobile_timer_init,
        .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 7a1ad4f38539..c54ff9b29fe5 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -60,14 +60,38 @@ void __init r8a7779_map_io(void)
        iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
 }
+static struct resource r8a7779_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffc0000,
+                .end    = 0xfffc023b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffc40000,
+                .end    = 0xffc46fff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device r8a7779_pfc_device = {
+        .name           = "pfc-r8a7779",
+        .id             = -1,
+        .resource       = r8a7779_pfc_resources,
+        .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
+};
+void __init r8a7779_pinmux_init(void)
+{
+        platform_device_register(&r8a7779_pfc_device);
+}
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xffe40000,
        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(88), gic_spi(88),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(88)),
-                            gic_spi(88), gic_spi(88) },
 };
 static struct platform_device scif0_device = {
@@ -84,8 +108,7 @@ static struct plat_sci_port scif1_platform_data = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(89), gic_spi(89),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(89)),
-                            gic_spi(89), gic_spi(89) },
 };
 static struct platform_device scif1_device = {
@@ -102,8 +125,7 @@ static struct plat_sci_port scif2_platform_data = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(90), gic_spi(90),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(90)),
-                            gic_spi(90), gic_spi(90) },
 };
 static struct platform_device scif2_device = {
@@ -120,8 +142,7 @@ static struct plat_sci_port scif3_platform_data = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(91), gic_spi(91),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(91)),
-                            gic_spi(91), gic_spi(91) },
 };
 static struct platform_device scif3_device = {
@@ -138,8 +159,7 @@ static struct plat_sci_port scif4_platform_data = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(92), gic_spi(92),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(92)),
-                            gic_spi(92), gic_spi(92) },
 };
 static struct platform_device scif4_device = {
@@ -156,8 +176,7 @@ static struct plat_sci_port scif5_platform_data = {
        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
        .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
-        .irqs           = { gic_spi(93), gic_spi(93),
+        .irqs           = SCIx_IRQ_MUXED(gic_spi(93)),
-                            gic_spi(93), gic_spi(93) },
 };
 static struct platform_device scif5_device = {
@@ -339,7 +358,7 @@ void __init r8a7779_add_standard_devices(void)
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
-static void __init r8a7779_earlytimer_init(void)
+void __init r8a7779_earlytimer_init(void)
 {
        r8a7779_clock_init();
        shmobile_earlytimer_init();
@@ -366,7 +385,4 @@ void __init r8a7779_add_early_devices(void)
         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
         * command line in case of the marzen board.
         */
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = r8a7779_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index c917882424a7..59c7146bf66f 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,6 +33,7 @@
 #include <linux/sh_timer.h>
 #include <linux/pm_domain.h>
 #include <linux/dma-mapping.h>
+#include <linux/platform_data/sh_ipmmu.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -60,6 +61,32 @@ void __init sh7372_map_io(void)
        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
 }
+/* PFC */
+static struct resource sh7372_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605800c,
+                .end    = 0xe6058027,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device sh7372_pfc_device = {
+        .name           = "pfc-sh7372",
+        .id             = -1,
+        .resource       = sh7372_pfc_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
+};
+void __init sh7372_pinmux_init(void)
+{
+        platform_device_register(&sh7372_pfc_device);
+}
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
@@ -982,6 +1009,43 @@ static struct platform_device spu1_device = {
        .num_resources  = ARRAY_SIZE(spu1_resources),
 };
+/* IPMMUI (an IPMMU module for ICB/LMB) */
+static struct resource ipmmu_resources[] = {
+        [0] = {
+                .name   = "IPMMUI",
+                .start  = 0xfe951000,
+                .end    = 0xfe9510ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static const char * const ipmmu_dev_names[] = {
+        "sh_mobile_lcdc_fb.0",
+        "sh_mobile_lcdc_fb.1",
+        "sh_mobile_ceu.0",
+        "uio_pdrv_genirq.0",
+        "uio_pdrv_genirq.1",
+        "uio_pdrv_genirq.2",
+        "uio_pdrv_genirq.3",
+        "uio_pdrv_genirq.4",
+        "uio_pdrv_genirq.5",
+};
+static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
+        .dev_names = ipmmu_dev_names,
+        .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
+};
+static struct platform_device ipmmu_device = {
+        .name           = "ipmmu",
+        .id             = -1,
+        .dev = {
+                .platform_data = &ipmmu_platform_data,
+        },
+        .resource       = ipmmu_resources,
+        .num_resources  = ARRAY_SIZE(ipmmu_resources),
+};
 static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -993,6 +1057,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
        &cmt2_device,
        &tmu00_device,
        &tmu01_device,
+        &ipmmu_device,
 };
 static struct platform_device *sh7372_late_devices[] __initdata = {
@@ -1054,7 +1119,7 @@ void __init sh7372_add_standard_devices(void)
                                       ARRAY_SIZE(domain_devices));
 }
-static void __init sh7372_earlytimer_init(void)
+void __init sh7372_earlytimer_init(void)
 {
        sh7372_clock_init();
        shmobile_earlytimer_init();
@@ -1067,9 +1132,6 @@ void __init sh7372_add_early_devices(void)
        /* setup early console here as well */
        shmobile_setup_console();
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = sh7372_earlytimer_init;
 }
 #ifdef CONFIG_USE_OF
@@ -1113,7 +1175,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
        .init_irq       = sh7372_init_irq,
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = sh7372_add_standard_devices_dt,
-        .timer          = &shmobile_timer,
+        .init_time      = shmobile_timer_init,
        .dt_compat      = sh7372_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index db99a4ade80c..bdab575f88bc 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -30,6 +31,7 @@
 #include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <linux/platform_data/sh_ipmmu.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -57,6 +59,31 @@ void __init sh73a0_map_io(void)
        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
+static struct resource sh73a0_pfc_resources[] = {
+        [0] = {
+                .start  = 0xe6050000,
+                .end    = 0xe6057fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xe605801c,
+                .end    = 0xe6058027,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device sh73a0_pfc_device = {
+        .name           = "pfc-sh73a0",
+        .id             = -1,
+        .resource       = sh73a0_pfc_resources,
+        .num_resources  = ARRAY_SIZE(sh73a0_pfc_resources),
+};
+void __init sh73a0_pinmux_init(void)
+{
+        platform_device_register(&sh73a0_pfc_device);
+}
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
        .flags          = UPF_BOOT_AUTOCONF,
@@ -754,7 +781,36 @@ static struct platform_device pmu_device = {
        .resource       = pmu_resources,
 };
-static struct platform_device *sh73a0_early_devices[] __initdata = {
+/* an IPMMU module for ICB */
+static struct resource ipmmu_resources[] = {
+        [0] = {
+                .name   = "IPMMU",
+                .start  = 0xfe951000,
+                .end    = 0xfe9510ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static const char * const ipmmu_dev_names[] = {
+        "sh_mobile_lcdc_fb.0",
+};
+static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
+        .dev_names = ipmmu_dev_names,
+        .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
+};
+static struct platform_device ipmmu_device = {
+        .name           = "ipmmu",
+        .id             = -1,
+        .dev = {
+                .platform_data = &ipmmu_platform_data,
+        },
+        .resource       = ipmmu_resources,
+        .num_resources  = ARRAY_SIZE(ipmmu_resources),
+};
+static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
        &scif0_device,
        &scif1_device,
        &scif2_device,
@@ -765,8 +821,12 @@ static struct platform_device *sh73a0_early_devices[] __initdata = {
        &scif7_device,
        &scif8_device,
        &cmt10_device,
+};
+static struct platform_device *sh73a0_early_devices[] __initdata = {
        &tmu00_device,
        &tmu01_device,
+        &ipmmu_device,
 };
 static struct platform_device *sh73a0_late_devices[] __initdata = {
@@ -787,6 +847,8 @@ void __init sh73a0_add_standard_devices(void)
        /* Clear software reset bit on SY-DMAC module */
        __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
+        platform_add_devices(sh73a0_early_devices_dt,
+                            ARRAY_SIZE(sh73a0_early_devices_dt));
        platform_add_devices(sh73a0_early_devices,
                            ARRAY_SIZE(sh73a0_early_devices));
        platform_add_devices(sh73a0_late_devices,
@@ -796,7 +858,7 @@ void __init sh73a0_add_standard_devices(void)
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
-static void __init sh73a0_earlytimer_init(void)
+void __init sh73a0_earlytimer_init(void)
 {
        sh73a0_clock_init();
        shmobile_earlytimer_init();
@@ -805,12 +867,63 @@ static void __init sh73a0_earlytimer_init(void)
 void __init sh73a0_add_early_devices(void)
 {
+        early_platform_add_devices(sh73a0_early_devices_dt,
+                                   ARRAY_SIZE(sh73a0_early_devices_dt));
        early_platform_add_devices(sh73a0_early_devices,
                                   ARRAY_SIZE(sh73a0_early_devices));
        /* setup early console here as well */
        shmobile_setup_console();
+}
+#ifdef CONFIG_USE_OF
+/* Please note that the clock initialisation shcheme used in
+ * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
+ * does not work with SMP as there is a yet to be resolved lock-up in
+ * workqueue initialisation.
+ *
+ * CONFIG_SMP should be disabled when using this code.
+ */
+void __init sh73a0_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+        early_platform_add_devices(sh73a0_early_devices_dt,
+                                   ARRAY_SIZE(sh73a0_early_devices_dt));
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
-        /* override timer setup with soc-specific code */
+static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
-        shmobile_timer.init = sh73a0_earlytimer_init;
+        {},
+};
+void __init sh73a0_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        sh73a0_clock_init();
+        platform_add_devices(sh73a0_early_devices_dt,
+                             ARRAY_SIZE(sh73a0_early_devices_dt));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             sh73a0_auxdata_lookup, NULL);
 }
+static const char *sh73a0_boards_compat_dt[] __initdata = {
+        "renesas,sh73a0",
+        NULL,
+};
+DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices_dt,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = sh73a0_init_irq_dt,
+        .init_machine   = sh73a0_add_standard_devices_dt,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = sh73a0_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 1d564674451d..a9df53b69ab8 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -59,17 +59,19 @@ sh7372_do_idle_sysc:
        mcr     p15, 0, r0, c1, c0, 0
        isb
+        /*
+         * Clean and invalidate data cache again.
+         */
+        ldr     r1, kernel_flush
+        blx     r1
        /* disable L2 cache in the aux control register */
        mrc     p15, 0, r10, c1, c0, 1
        bic     r10, r10, #2
        mcr     p15, 0, r10, c1, c0, 1
+        isb
        /*
-         * Invalidate data cache again.
-         */
-        ldr     r1, kernel_flush
-        blx     r1
-        /*
         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
         * This sequence switches back to ARM.  Note that .align may insert a
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f67456286280..953eb1f9388d 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,11 +23,11 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/hardware/gic.h>
 #include <asm/cacheflush.h>
 #define EMEV2_SCU_BASE 0x1e000000
@@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
        /* Tell ROM loader about our vector (in headsmp.S) */
        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-        gic_raise_softirq(cpumask_of(cpu), 0);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        return 0;
 }
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 2ce6af9a6a37..3a4acf23edcf 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,12 +23,12 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
-#include <asm/hardware/gic.h>
 #define AVECR IOMEM(0xfe700040)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 624f00f70abf..acb46a94ccdf 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,12 +23,13 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <mach/sh73a0.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
-#include <asm/hardware/gic.h>
 #define WUPCR           IOMEM(0xe6151010)
 #define SRESCR          IOMEM(0xe6151018)
@@ -36,14 +37,13 @@
 #define SBAR            IOMEM(0xe6180020)
 #define APARMBAREA      IOMEM(0xe6f10020)
+#define PSTR_SHUTDOWN_MODE      3
 static void __iomem *scu_base_addr(void)
 {
        return (void __iomem *)0xf0000000;
 }
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
 void __init sh73a0_register_twd(void)
@@ -52,20 +52,6 @@ void __init sh73a0_register_twd(void)
 }
 #endif
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
 static unsigned int __init sh73a0_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
@@ -82,9 +68,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 {
        cpu = cpu_logical_map(cpu);
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
        if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
                __raw_writel(1 << cpu, WUPCR);  /* wake up */
        else
@@ -95,16 +78,14 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
        scu_enable(scu_base_addr());
-        /* Map the reset vector (in headsmp.S) */
+        /* Map the reset vector (in headsmp-sh73a0.S) */
        __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(shmobile_secondary_vector), SBAR);
+        __raw_writel(__pa(sh73a0_secondary_vector), SBAR);
-        /* enable cache coherency on CPU0 */
+        /* enable cache coherency on booting CPU */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
 }
 static void __init sh73a0_smp_init_cpus(void)
@@ -114,16 +95,20 @@ static void __init sh73a0_smp_init_cpus(void)
        shmobile_smp_init_cpus(ncores);
 }
-static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
+#ifdef CONFIG_HOTPLUG_CPU
+static int sh73a0_cpu_kill(unsigned int cpu)
 {
        int k;
+        u32 pstr;
-        /* this function is running on another CPU than the offline target,
+        /*
-         * here we need wait for shutdown code in platform_cpu_die() to
+         * wait until the power status register confirms the shutdown of the
-         * finish before asking SoC-specific code to power off the CPU core.
+         * offline target
         */
        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
+                pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3;
+                if (pstr == PSTR_SHUTDOWN_MODE)
                        return 1;
                mdelay(1);
@@ -132,6 +117,23 @@ static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
        return 0;
 }
+static void sh73a0_cpu_die(unsigned int cpu)
+{
+        /*
+         * The ARM MPcore does not issue a cache coherency request for the L1
+         * cache when powering off single CPUs. We must take care of this and
+         * further caches.
+         */
+        dsb();
+        flush_cache_all();
+        /* Set power off mode. This takes the CPU out of the MP cluster */
+        scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+        /* Enter shutdown mode */
+        cpu_do_idle();
+}
+#endif /* CONFIG_HOTPLUG_CPU */
 struct smp_operations sh73a0_smp_ops __initdata = {
        .smp_init_cpus          = sh73a0_smp_init_cpus,
@@ -140,7 +142,7 @@ struct smp_operations sh73a0_smp_ops __initdata = {
        .smp_boot_secondary     = sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_kill               = sh73a0_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
+        .cpu_die                = sh73a0_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
+        .cpu_disable            = shmobile_cpu_disable_any,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index a68919727e24..3d16d4dff01b 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -20,6 +20,7 @@
 */
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <asm/arch_timer.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
@@ -60,10 +61,8 @@ void __init shmobile_earlytimer_init(void)
        late_time_init = shmobile_late_time_init;
 }
-static void __init shmobile_timer_init(void)
+void __init shmobile_timer_init(void)
 {
+        arch_timer_of_register();
+        arch_timer_sched_clock_init();
 }
-struct sys_timer shmobile_timer = {
-        .init           = shmobile_timer_init,
-};
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 9941caa94931..315edff610f2 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
-extern void secondary_startup(void);
+extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 extern void socfpga_init_clocks(void);
@@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void);
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
+extern unsigned long cpu1start_addr;
 #define SOCFPGA_SCU_VIRT_BASE   0xfffec000
 #endif
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f09b1283ffca..9004bfb1756e 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,13 +13,21 @@
        __CPUINIT
        .arch   armv7-a
-#define CPU1_START_ADDR                 0xffd08010
 ENTRY(secondary_trampoline)
-        movw    r0, #:lower16:CPU1_START_ADDR
+        movw    r2, #:lower16:cpu1start_addr
-        movt  r0, #:upper16:CPU1_START_ADDR
+        movt  r2, #:upper16:cpu1start_addr
+        /* The socfpga VT cannot handle a 0xC0000000 page offset when loading
+                the cpu1start_addr, we bit clear it. Tested on HW and VT. */
+        bic     r2, r2, #0x40000000
+        ldr     r0, [r2]
        ldr     r1, [r0]
        bx      r1
 ENTRY(secondary_trampoline_end)
+ENTRY(socfpga_secondary_startup)
+       bl      v7_invalidate_l1
+       b       secondary_startup
+ENDPROC(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 68dd1b69512a..84c60fa8daa0 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -22,9 +22,9 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
@@ -47,16 +47,19 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 {
        int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
-        memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+        if (cpu1start_addr) {
+                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
-        __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+                __raw_writel(virt_to_phys(socfpga_secondary_startup),
+                        (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
-        flush_cache_all();
+                flush_cache_all();
-        smp_wmb();
+                smp_wmb();
-        outer_clean_range(0, trampoline_size);
+                outer_clean_range(0, trampoline_size);
-        /* This will release CPU #1 out of reset.*/
+                /* This will release CPU #1 out of reset.*/
-        __raw_writel(0, rst_manager_base_addr + 0x10);
+                __raw_writel(0, rst_manager_base_addr + 0x10);
+        }
        return 0;
 }
@@ -83,8 +86,6 @@ static void __init socfpga_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 6732924a5fee..1042c023cf24 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -15,12 +15,12 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 #include <linux/dw_apb_timer.h>
+#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -29,6 +29,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+unsigned long cpu1start_addr;
 static struct map_desc scu_io_desc __initdata = {
        .virtual        = SOCFPGA_SCU_VIRT_BASE,
@@ -62,25 +63,25 @@ static void __init socfpga_map_io(void)
        early_printk("Early printk initialized\n");
 }
-const static struct of_device_id irq_match[] = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {}
-};
 void __init socfpga_sysmgr_init(void)
 {
        struct device_node *np;
        np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+        if (of_property_read_u32(np, "cpu1-start-addr",
+                        (u32 *) &cpu1start_addr))
+                pr_err("SMP: Need cpu1-start-addr in device tree.\n");
        sys_manager_base_addr = of_iomap(np, 0);
        np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
        rst_manager_base_addr = of_iomap(np, 0);
 }
-static void __init gic_init_irq(void)
+static void __init socfpga_init_irq(void)
 {
-        of_irq_init(irq_match);
+        irqchip_init();
        socfpga_sysmgr_init();
 }
@@ -98,16 +99,14 @@ static void __init socfpga_cyclone5_init(void)
 static const char *altera_dt_match[] = {
        "altr,socfpga",
-        "altr,socfpga-cyclone5",
        NULL
 };
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
        .smp            = smp_ops(socfpga_smp_ops),
        .map_io         = socfpga_map_io,
-        .init_irq       = gic_init_irq,
+        .init_irq       = socfpga_init_irq,
-        .handle_irq     = gic_handle_irq,
+        .init_time      = dw_apb_timer_init,
-        .timer          = &dw_apb_timer,
        .init_machine   = socfpga_cyclone5_init,
        .restart        = socfpga_cyclone5_restart,
        .dt_compat      = altera_dt_match,
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index c33f4d9361bd..633e678e01a3 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -18,7 +18,7 @@
 #include <asm/mach/time.h>
 /* Add spear13xx structure declarations here */
-extern struct sys_timer spear13xx_timer;
+extern void spear13xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
 extern struct dw_dma_platform_data dmac_plat_data;
 extern struct dw_dma_slave cf_dma_priv;
@@ -28,7 +28,6 @@ extern struct dw_dma_slave nand_write_dma_priv;
 /* Add spear13xx family function declarations here */
 void __init spear_setup_of_timer(void);
 void __init spear13xx_map_io(void);
-void __init spear13xx_dt_init_irq(void);
 void __init spear13xx_l2x0_init(void);
 bool dw_dma_filter(struct dma_chan *chan, void *slave);
 void spear_restart(char, const char *);
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index 2eaa3fa7b432..af4ade61cd95 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -15,8 +15,8 @@
 #include <linux/jiffies.h>
 #include <linux/io.h>
 #include <linux/smp.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
 #include <mach/generic.h>
@@ -104,8 +104,6 @@ static void __init spear13xx_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 02f4724bb0d4..56214d1076ef 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -14,9 +14,9 @@
 #define pr_fmt(fmt) "SPEAr1310: " fmt
 #include <linux/amba/pl022.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/pata_arasan_cf_data.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/generic.h>
@@ -90,9 +90,8 @@ static void __init spear1310_map_io(void)
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear1310_map_io,
-        .init_irq       =       spear13xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       gic_handle_irq,
+        .init_time      =       spear13xx_timer_init,
-        .timer          =       &spear13xx_timer,
        .init_machine   =       spear1310_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear1310_dt_board_compat,
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
index 081014fb314a..9a28beb2a113 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -18,7 +18,7 @@
 #include <linux/delay.h>
 #include <linux/dw_dmac.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/gic.h>
+#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include <mach/dma.h>
 #include <mach/generic.h>
@@ -184,9 +184,8 @@ static const char * const spear1340_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear13xx_map_io,
-        .init_irq       =       spear13xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       gic_handle_irq,
+        .init_time      =       spear13xx_timer_init,
-        .timer          =       &spear13xx_timer,
        .init_machine   =       spear1340_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear1340_dt_board_compat,
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index c4af775a8451..c7d2b4a8d8cc 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -17,9 +17,8 @@
 #include <linux/clk.h>
 #include <linux/dw_dmac.h>
 #include <linux/err.h>
-#include <linux/of_irq.h>
+#include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/smp_twd.h>
 #include <mach/dma.h>
@@ -153,7 +152,7 @@ static void __init spear13xx_clk_init(void)
                pr_err("%s: Unknown machine\n", __func__);
 }
-static void __init spear13xx_timer_init(void)
+void __init spear13xx_timer_init(void)
 {
        char pclk_name[] = "osc_24m_clk";
        struct clk *gpt_clk, *pclk;
@@ -182,17 +181,3 @@ static void __init spear13xx_timer_init(void)
        spear_setup_of_timer();
        twd_local_timer_of_register();
 }
-struct sys_timer spear13xx_timer = {
-        .init = spear13xx_timer_init,
-};
-static const struct of_device_id gic_of_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-        { /* Sentinel */ }
-};
-void __init spear13xx_dt_init_irq(void)
-{
-        of_irq_init(gic_of_match);
-}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index ce19113ca791..df310799e416 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -22,7 +22,7 @@
 #include <asm/mach/map.h>
 /* Add spear3xx family device structure declarations here */
-extern struct sys_timer spear3xx_timer;
+extern void spear3xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
 extern struct pl08x_platform_data pl080_plat_data;
@@ -30,7 +30,6 @@ extern struct pl08x_platform_data pl080_plat_data;
 void __init spear_setup_of_timer(void);
 void __init spear3xx_clk_init(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_dt_init_irq(void);
 void spear_restart(char, const char *);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index a69cbfdb07ee..bbc9b7e9c62c 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -14,8 +14,8 @@
 #define pr_fmt(fmt) "SPEAr300: " fmt
 #include <linux/amba/pl08x.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -212,9 +212,8 @@ static void __init spear300_map_io(void)
 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
        .map_io         =       spear300_map_io,
-        .init_irq       =       spear3xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       vic_handle_irq,
+        .init_time      =       spear3xx_timer_init,
-        .timer          =       &spear3xx_timer,
        .init_machine   =       spear300_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear300_dt_board_compat,
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b963ebb10b56..c13a434a8195 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -15,8 +15,8 @@
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -254,9 +254,8 @@ static void __init spear310_map_io(void)
 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
        .map_io         =       spear310_map_io,
-        .init_irq       =       spear3xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       vic_handle_irq,
+        .init_time      =       spear3xx_timer_init,
-        .timer          =       &spear3xx_timer,
        .init_machine   =       spear310_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear310_dt_board_compat,
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 66e3a0c33e75..e1c77079a3e5 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -16,8 +16,8 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
+#include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -268,9 +268,8 @@ static void __init spear320_map_io(void)
 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
        .map_io         =       spear320_map_io,
-        .init_irq       =       spear3xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       vic_handle_irq,
+        .init_time      =       spear3xx_timer_init,
-        .timer          =       &spear3xx_timer,
        .init_machine   =       spear320_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear320_dt_board_compat,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 38fe95db31a7..f9d754f90c59 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -15,11 +15,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
-#include <linux/irqchip/spear-shirq.h>
-#include <linux/of_irq.h>
 #include <linux/io.h>
-#include <asm/hardware/pl080.h>
-#include <asm/hardware/vic.h>
 #include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -87,7 +83,7 @@ void __init spear3xx_map_io(void)
        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
 }
-static void __init spear3xx_timer_init(void)
+void __init spear3xx_timer_init(void)
 {
        char pclk_name[] = "pll3_clk";
        struct clk *gpt_clk, *pclk;
@@ -115,20 +111,3 @@ static void __init spear3xx_timer_init(void)
        spear_setup_of_timer();
 }
-struct sys_timer spear3xx_timer = {
-        .init = spear3xx_timer_init,
-};
-static const struct of_device_id vic_of_match[] __initconst = {
-        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
-        { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
-        { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
-        { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
-        { /* Sentinel */ }
-};
-void __init spear3xx_dt_init_irq(void)
-{
-        of_irq_init(vic_of_match);
-}
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 5a5a52db252b..8904d8a52d84 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -16,12 +16,11 @@
 #include <linux/amba/pl08x.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/pl080.h>
+#include <linux/amba/pl080.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
@@ -374,7 +373,7 @@ void __init spear6xx_map_io(void)
        iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
 }
-static void __init spear6xx_timer_init(void)
+void __init spear6xx_timer_init(void)
 {
        char pclk_name[] = "pll3_clk";
        struct clk *gpt_clk, *pclk;
@@ -403,10 +402,6 @@ static void __init spear6xx_timer_init(void)
        spear_setup_of_timer();
 }
-struct sys_timer spear6xx_timer = {
-        .init = spear6xx_timer_init,
-};
 /* Add auxdata to pass platform data */
 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
@@ -425,21 +420,10 @@ static const char *spear600_dt_board_compat[] = {
        NULL
 };
-static const struct of_device_id vic_of_match[] __initconst = {
-        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
-        { /* Sentinel */ }
-};
-static void __init spear6xx_dt_init_irq(void)
-{
-        of_irq_init(vic_of_match);
-}
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
        .map_io         =       spear6xx_map_io,
-        .init_irq       =       spear6xx_dt_init_irq,
+        .init_irq       =       irqchip_init,
-        .handle_irq     =       vic_handle_irq,
+        .init_time      =       spear6xx_timer_init,
-        .timer          =       &spear6xx_timer,
        .init_machine   =       spear600_dt_init,
        .restart        =       spear_restart,
        .dt_compat      =       spear600_dt_board_compat,
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3fdd0085e306..8709a39bd34c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -7,3 +7,4 @@ config ARCH_SUNXI
        select PINCTRL
        select SPARSE_IRQ
        select SUNXI_TIMER
+        select PINCTRL_SUNXI
+\ No newline at end of file
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1dc8a92e5a5f..23afb732cb40 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -21,15 +21,16 @@
 #include <linux/irqchip/sunxi.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include "sunxi.h"
 #define WATCHDOG_CTRL_REG       0x00
+#define WATCHDOG_CTRL_RESTART           (1 << 0)
 #define WATCHDOG_MODE_REG       0x04
+#define WATCHDOG_MODE_ENABLE            (1 << 0)
+#define WATCHDOG_MODE_RESET_ENABLE      (1 << 1)
 static void __iomem *wdt_base;
@@ -50,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd)
                return;
        /* Enable timer and set reset bit in the watchdog */
-        writel(3, wdt_base + WATCHDOG_MODE_REG);
+        writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-        writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
+                wdt_base + WATCHDOG_MODE_REG);
-        while(1) {
+        /*
+         * Restart the watchdog. The default (and lowest) interval
+         * value for the watchdog is 0.5s.
+         */
+        writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
+        while (1) {
                mdelay(5);
-                writel(3, wdt_base + WATCHDOG_MODE_REG);
+                writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
+                        wdt_base + WATCHDOG_MODE_REG);
        }
 }
@@ -91,6 +100,6 @@ DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
        .init_irq       = sunxi_init_irq,
        .handle_irq     = sunxi_handle_irq,
        .restart        = sunxi_restart,
-        .timer          = &sunxi_timer,
+        .init_time      = &sunxi_timer_init,
        .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b442f15fd01a..d1c4893894ce 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -4,11 +4,11 @@ comment "NVIDIA Tegra options"
 config ARCH_TEGRA_2x_SOC
        bool "Enable support for Tegra20 family"
-        select ARCH_REQUIRE_GPIOLIB
+        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
        select ARM_ERRATA_720789
-        select ARM_ERRATA_742230
+        select ARM_ERRATA_742230 if SMP
        select ARM_ERRATA_751472
-        select ARM_ERRATA_754327
+        select ARM_ERRATA_754327 if SMP
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
        select CPU_FREQ_TABLE if CPU_FREQ
@@ -26,7 +26,6 @@ config ARCH_TEGRA_2x_SOC
 config ARCH_TEGRA_3x_SOC
        bool "Enable support for Tegra30 family"
-        select ARCH_REQUIRE_GPIOLIB
        select ARM_ERRATA_743622
        select ARM_ERRATA_751472
        select ARM_ERRATA_754322
@@ -44,6 +43,18 @@ config ARCH_TEGRA_3x_SOC
          Support for NVIDIA Tegra T30 processor family, based on the
          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+config ARCH_TEGRA_114_SOC
+        bool "Enable support for Tegra114 family"
+        select ARM_ARCH_TIMER
+        select ARM_GIC
+        select ARM_L1_CACHE_SHIFT_6
+        select CPU_V7
+        select PINCTRL
+        select PINCTRL_TEGRA114
+        help
+          Support for NVIDIA Tegra T114 processor family, based on the
+          ARM CortexA15MP CPU
 config TEGRA_PCI
        bool "PCI Express support"
        depends on ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0979e8bba78a..f6b46ae2b7f8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,39 +1,38 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
-obj-y                                   += clock.o
-obj-y                                   += timer.o
 obj-y                                   += fuse.o
 obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
 obj-y                                   += powergate.o
 obj-y                                   += apbio.o
 obj-y                                   += pm.o
+obj-y                                   += reset.o
+obj-y                                   += reset-handler.o
+obj-y                                   += sleep.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
-obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-tegra20.o
 endif
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += cpuidle-tegra30.o
 endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
-obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += board-dt-tegra114.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
+endif
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-harmony-pcie.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index d091675ba376..d7aa52ea6cfc 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -38,7 +38,7 @@ static void tegra_apb_writel_direct(u32 value, unsigned long offset);
 static struct dma_chan *tegra_apb_dma_chan;
 static struct dma_slave_config dma_sconfig;
-bool tegra_apb_dma_init(void)
+static bool tegra_apb_dma_init(void)
 {
        dma_cap_mask_t mask;
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
new file mode 100644
index 000000000000..085d63637b62
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra114.c
@@ -0,0 +1,46 @@
+/*
+ * NVIDIA Tegra114 device tree board support
+ *
+ * Copyright (C) 2013 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <asm/mach/arch.h>
+#include "board.h"
+#include "common.h"
+static void __init tegra114_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char * const tegra114_dt_board_compat[] = {
+        "nvidia,tegra114",
+        NULL,
+};
+DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
+        .smp            = smp_ops(tegra_smp_ops),
+        .map_io         = tegra_map_common_io,
+        .init_early     = tegra114_init_early,
+        .init_irq       = tegra_dt_init_irq,
+        .init_time      = clocksource_of_init,
+        .init_machine   = tegra114_dt_init,
+        .init_late      = tegra_init_late,
+        .restart        = tegra_assert_system_reset,
+        .dt_compat      = tegra114_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 734d9cc87f2e..a0edf2510280 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -15,6 +15,7 @@
 *
 */
+#include <linux/clocksource.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
@@ -25,7 +26,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
 #include <linux/platform_data/tegra_usb.h>
@@ -34,106 +34,51 @@
 #include <linux/i2c-tegra.h>
 #include <linux/usb/tegra_usb_phy.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
-struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
        .operating_mode = TEGRA_USB_OTG,
        .power_down_on_bus_suspend = 1,
        .vbus_gpio = -1,
 };
-struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
        .reset_gpio = -1,
        .clk = "cdev2",
 };
-struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
        .phy_config = &tegra_ehci2_ulpi_phy_config,
        .operating_mode = TEGRA_USB_HOST,
        .power_down_on_bus_suspend = 1,
        .vbus_gpio = -1,
 };
-struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
        .operating_mode = TEGRA_USB_HOST,
        .power_down_on_bus_suspend = 1,
        .vbus_gpio = -1,
 };
-struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0",
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
                       &tegra_ehci1_pdata),
-        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1",
                       &tegra_ehci2_pdata),
-        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2",
                       &tegra_ehci3_pdata),
-        OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
        {}
 };
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "uartd",      "pll_p",        216000000,      true },
-        { "usbd",       "clk_m",        12000000,       false },
-        { "usb2",       "clk_m",        12000000,       false },
-        { "usb3",       "clk_m",        12000000,       false },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "blink",      "clk_32k",      32768,          true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "i2s2",       "pll_a_out0",   11289600,       false},
-        { "sdmmc1",     "pll_p",        48000000,       false},
-        { "sdmmc3",     "pll_p",        48000000,       false},
-        { "sdmmc4",     "pll_p",        48000000,       false},
-        { "spi",        "pll_p",        20000000,       false },
-        { "sbc1",       "pll_p",        100000000,      false },
-        { "sbc2",       "pll_p",        100000000,      false },
-        { "sbc3",       "pll_p",        100000000,      false },
-        { "sbc4",       "pll_p",        100000000,      false },
-        { "host1x",     "pll_c",        150000000,      false },
-        { "disp1",      "pll_p",        600000000,      false },
-        { "disp2",      "pll_p",        600000000,      false },
-        { NULL,         NULL,           0,              0},
-};
 static void __init tegra_dt_init(void)
 {
-        tegra_clk_init_from_table(tegra_dt_clk_init_table);
        /*
         * Finished with the static registrations now; fill in the missing
         * devices
@@ -202,8 +147,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
        .smp            = smp_ops(tegra_smp_ops),
        .init_early     = tegra20_init_early,
        .init_irq       = tegra_dt_init_irq,
-        .handle_irq     = gic_handle_irq,
+        .init_time      = clocksource_of_init,
-        .timer          = &tegra_sys_timer,
        .init_machine   = tegra_dt_init,
        .init_late      = tegra_dt_init_late,
        .restart        = tegra_assert_system_reset,
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 6497d1236b08..bf68567e549d 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -23,6 +23,7 @@
 *
 */
+#include <linux/clocksource.h>
 #include <linux/kernel.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -31,75 +32,14 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
-struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
-        {}
-};
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        408000000,      true },
-        { "pll_a",      "pll_p_out1",   564480000,      true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "extern1",    "pll_a_out0",   0,              true },
-        { "clk_out_1",  "extern1",      0,              true },
-        { "blink",      "clk_32k",      32768,          true },
-        { "i2s0",       "pll_a_out0",   11289600,       false},
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "i2s2",       "pll_a_out0",   11289600,       false},
-        { "i2s3",       "pll_a_out0",   11289600,       false},
-        { "i2s4",       "pll_a_out0",   11289600,       false},
-        { "sdmmc1",     "pll_p",        48000000,       false},
-        { "sdmmc3",     "pll_p",        48000000,       false},
-        { "sdmmc4",     "pll_p",        48000000,       false},
-        { "sbc1",       "pll_p",        100000000,      false},
-        { "sbc2",       "pll_p",        100000000,      false},
-        { "sbc3",       "pll_p",        100000000,      false},
-        { "sbc4",       "pll_p",        100000000,      false},
-        { "sbc5",       "pll_p",        100000000,      false},
-        { "sbc6",       "pll_p",        100000000,      false},
-        { "host1x",     "pll_c",        150000000,      false},
-        { "disp1",      "pll_p",        600000000,      false},
-        { "disp2",      "pll_p",        600000000,      false},
-        { NULL,         NULL,           0,              0},
-};
 static void __init tegra30_dt_init(void)
 {
-        tegra_clk_init_from_table(tegra_dt_clk_init_table);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra30_auxdata_lookup, NULL);
 }
 static const char *tegra30_dt_board_compat[] = {
@@ -112,8 +52,7 @@ DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
        .map_io         = tegra_map_common_io,
        .init_early     = tegra30_init_early,
        .init_irq       = tegra_dt_init_irq,
-        .handle_irq     = gic_handle_irq,
+        .init_time      = clocksource_of_init,
-        .timer          = &tegra_sys_timer,
        .init_machine   = tegra30_dt_init,
        .init_late      = tegra_init_late,
        .restart        = tegra_assert_system_reset,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 91fbe733a21e..86851c81a350 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -1,6 +1,7 @@
 /*
 * arch/arm/mach-tegra/board.h
 *
+ * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
@@ -27,6 +28,7 @@ void tegra_assert_system_reset(char mode, const char *cmd);
 void __init tegra20_init_early(void);
 void __init tegra30_init_early(void);
+void __init tegra114_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
@@ -55,5 +57,4 @@ static inline int harmony_pcie_init(void) { return 0; }
 void __init tegra_paz00_wifikill_init(void);
-extern struct sys_timer tegra_sys_timer;
 #endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
deleted file mode 100644
index 867bf8bf5561..000000000000
--- a/arch/arm/mach-tegra/clock.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-#include "board.h"
-#include "clock.h"
-#include "tegra_cpu_car.h"
-/* Global data of Tegra CPU CAR ops */
-struct tegra_cpu_car_ops *tegra_cpu_car_ops;
-/*
- * Locking:
- *
- * An additional mutex, clock_list_lock, is used to protect the list of all
- * clocks.
- *
- */
-static DEFINE_MUTEX(clock_list_lock);
-static LIST_HEAD(clocks);
-void tegra_clk_add(struct clk *clk)
-{
-        struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
-        mutex_lock(&clock_list_lock);
-        list_add(&c->node, &clocks);
-        mutex_unlock(&clock_list_lock);
-}
-struct clk *tegra_get_clock_by_name(const char *name)
-{
-        struct clk_tegra *c;
-        struct clk *ret = NULL;
-        mutex_lock(&clock_list_lock);
-        list_for_each_entry(c, &clocks, node) {
-                if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
-                        ret = c->hw.clk;
-                        break;
-                }
-        }
-        mutex_unlock(&clock_list_lock);
-        return ret;
-}
-static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
-{
-        struct clk *c;
-        struct clk *p;
-        struct clk *parent;
-        int ret = 0;
-        c = tegra_get_clock_by_name(table->name);
-        if (!c) {
-                pr_warn("Unable to initialize clock %s\n",
-                        table->name);
-                return -ENODEV;
-        }
-        parent = clk_get_parent(c);
-        if (table->parent) {
-                p = tegra_get_clock_by_name(table->parent);
-                if (!p) {
-                        pr_warn("Unable to find parent %s of clock %s\n",
-                                table->parent, table->name);
-                        return -ENODEV;
-                }
-                if (parent != p) {
-                        ret = clk_set_parent(c, p);
-                        if (ret) {
-                                pr_warn("Unable to set parent %s of clock %s: %d\n",
-                                        table->parent, table->name, ret);
-                                return -EINVAL;
-                        }
-                }
-        }
-        if (table->rate && table->rate != clk_get_rate(c)) {
-                ret = clk_set_rate(c, table->rate);
-                if (ret) {
-                        pr_warn("Unable to set clock %s to rate %lu: %d\n",
-                                table->name, table->rate, ret);
-                        return -EINVAL;
-                }
-        }
-        if (table->enabled) {
-                ret = clk_prepare_enable(c);
-                if (ret) {
-                        pr_warn("Unable to enable clock %s: %d\n",
-                                table->name, ret);
-                        return -EINVAL;
-                }
-        }
-        return 0;
-}
-void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
-{
-        for (; table->name; table++)
-                tegra_clk_init_one_from_table(table);
-}
-void tegra_periph_reset_deassert(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        BUG_ON(!clk->reset);
-        clk->reset(__clk_get_hw(c), false);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-void tegra_periph_reset_assert(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        BUG_ON(!clk->reset);
-        clk->reset(__clk_get_hw(c), true);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-/* Several extended clock configuration bits (e.g., clock routing, clock
- * phase control) are included in PLL and peripheral clock source
- * registers. */
-int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
-{
-        int ret = 0;
-        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        if (!clk->clk_cfg_ex) {
-                ret = -ENOSYS;
-                goto out;
-        }
-        ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
-out:
-        return ret;
-}
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
deleted file mode 100644
index 2aa37f5c44c0..000000000000
--- a/arch/arm/mach-tegra/clock.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/clock.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_CLOCK_H
-#define __MACH_TEGRA_CLOCK_H
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/list.h>
-#include <mach/clk.h>
-#define DIV_BUS                 (1 << 0)
-#define DIV_U71                 (1 << 1)
-#define DIV_U71_FIXED           (1 << 2)
-#define DIV_2                   (1 << 3)
-#define DIV_U16                 (1 << 4)
-#define PLL_FIXED               (1 << 5)
-#define PLL_HAS_CPCON           (1 << 6)
-#define MUX                     (1 << 7)
-#define PLLD                    (1 << 8)
-#define PERIPH_NO_RESET         (1 << 9)
-#define PERIPH_NO_ENB           (1 << 10)
-#define PERIPH_EMC_ENB          (1 << 11)
-#define PERIPH_MANUAL_RESET     (1 << 12)
-#define PLL_ALT_MISC_REG        (1 << 13)
-#define PLLU                    (1 << 14)
-#define PLLX                    (1 << 15)
-#define MUX_PWM                 (1 << 16)
-#define MUX8                    (1 << 17)
-#define DIV_U71_UART            (1 << 18)
-#define MUX_CLK_OUT             (1 << 19)
-#define PLLM                    (1 << 20)
-#define DIV_U71_INT             (1 << 21)
-#define DIV_U71_IDLE            (1 << 22)
-#define ENABLE_ON_INIT          (1 << 28)
-#define PERIPH_ON_APB           (1 << 29)
-struct clk_tegra;
-#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
-struct clk_mux_sel {
-        struct clk      *input;
-        u32             value;
-};
-struct clk_pll_freq_table {
-        unsigned long   input_rate;
-        unsigned long   output_rate;
-        u16             n;
-        u16             m;
-        u8              p;
-        u8              cpcon;
-};
-enum clk_state {
-        UNINITIALIZED = 0,
-        ON,
-        OFF,
-};
-struct clk_tegra {
-        /* node for master clocks list */
-        struct list_head        node;   /* node for list of all clocks */
-        struct clk_lookup       lookup;
-        struct clk_hw           hw;
-        bool                    set;
-        unsigned long           fixed_rate;
-        unsigned long           max_rate;
-        unsigned long           min_rate;
-        u32                     flags;
-        const char              *name;
-        enum clk_state          state;
-        u32                     div;
-        u32                     mul;
-        u32                             reg;
-        u32                             reg_shift;
-        struct list_head                shared_bus_list;
-        union {
-                struct {
-                        unsigned int                    clk_num;
-                } periph;
-                struct {
-                        unsigned long                   input_min;
-                        unsigned long                   input_max;
-                        unsigned long                   cf_min;
-                        unsigned long                   cf_max;
-                        unsigned long                   vco_min;
-                        unsigned long                   vco_max;
-                        const struct clk_pll_freq_table *freq_table;
-                        int                             lock_delay;
-                        unsigned long                   fixed_rate;
-                } pll;
-                struct {
-                        u32                             sel;
-                        u32                             reg_mask;
-                } mux;
-                struct {
-                        struct clk                      *main;
-                        struct clk                      *backup;
-                } cpu;
-                struct {
-                        struct list_head                node;
-                        bool                            enabled;
-                        unsigned long                   rate;
-                } shared_bus_user;
-        } u;
-        void (*reset)(struct clk_hw *, bool);
-        int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
-};
-struct clk_duplicate {
-        const char *name;
-        struct clk_lookup lookup;
-};
-struct tegra_clk_init_table {
-        const char *name;
-        const char *parent;
-        unsigned long rate;
-        bool enabled;
-};
-void tegra_clk_add(struct clk *c);
-void tegra2_init_clocks(void);
-void tegra30_init_clocks(void);
-struct clk *tegra_get_clock_by_name(const char *name);
-void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d54cfc54b9fe..5449a3f2977b 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,6 +1,7 @@
 /*
 * arch/arm/mach-tegra/common.c
 *
+ * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
@@ -21,15 +22,14 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+#include <linux/clk/tegra.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <mach/powergate.h>
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
@@ -37,6 +37,7 @@
 #include "apbio.h"
 #include "sleep.h"
 #include "pm.h"
+#include "reset.h"
 /*
 * Storage for debug-macro.S's state.
@@ -57,15 +58,11 @@ u32 tegra_uart_config[4] = {
 };
 #ifdef CONFIG_OF
-static const struct of_device_id tegra_dt_irq_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-        { }
-};
 void __init tegra_dt_init_irq(void)
 {
+        tegra_clocks_init();
        tegra_init_irq();
-        of_irq_init(tegra_dt_irq_match);
+        irqchip_init();
 }
 #endif
@@ -79,43 +76,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
        writel_relaxed(reg, reset);
 }
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "clk_m",      NULL,           0,              true },
-        { "pll_p",      "clk_m",        216000000,      true },
-        { "pll_p_out1", "pll_p",        28800000,       true },
-        { "pll_p_out2", "pll_p",        48000000,       true },
-        { "pll_p_out3", "pll_p",        72000000,       true },
-        { "pll_p_out4", "pll_p",        24000000,       true },
-        { "pll_c",      "clk_m",        600000000,      true },
-        { "pll_c_out1", "pll_c",        120000000,      true },
-        { "sclk",       "pll_c_out1",   120000000,      true },
-        { "hclk",       "sclk",         120000000,      true },
-        { "pclk",       "hclk",         60000000,       true },
-        { "csite",      NULL,           0,              true },
-        { "emc",        NULL,           0,              true },
-        { "cpu",        NULL,           0,              true },
-        { NULL,         NULL,           0,              0},
-};
-#endif
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "clk_m",      NULL,           0,              true },
-        { "pll_p",      "pll_ref",      408000000,      true },
-        { "pll_p_out1", "pll_p",        9600000,        true },
-        { "pll_p_out4", "pll_p",        102000000,      true },
-        { "sclk",       "pll_p_out4",   102000000,      true },
-        { "hclk",       "sclk",         102000000,      true },
-        { "pclk",       "hclk",         51000000,       true },
-        { "csite",      NULL,           0,              true },
-        { NULL,         NULL,           0,              0},
-};
-#endif
 static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -134,33 +94,39 @@ static void __init tegra_init_cache(void)
 }
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static void __init tegra_init_early(void)
-void __init tegra20_init_early(void)
 {
+        tegra_cpu_reset_handler_init();
        tegra_apb_io_init();
        tegra_init_fuse();
-        tegra2_init_clocks();
-        tegra_clk_init_from_table(tegra20_clk_init_table);
        tegra_init_cache();
        tegra_pmc_init();
        tegra_powergate_init();
+}
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
+{
+        tegra_init_early();
        tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
-        tegra_apb_io_init();
+        tegra_init_early();
-        tegra_init_fuse();
-        tegra30_init_clocks();
-        tegra_clk_init_from_table(tegra30_clk_init_table);
-        tegra_init_cache();
-        tegra_pmc_init();
-        tegra_powergate_init();
        tegra30_hotplug_init();
 }
 #endif
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void __init tegra114_init_early(void)
+{
+        tegra_init_early();
+}
+#endif
 void __init tegra_init_late(void)
 {
        tegra_powergate_debugfs_init();
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 02f71b4f1e51..32f8eb3fe344 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -1,4 +1,5 @@
 extern struct smp_operations tegra_smp_ops;
+extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
 extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index a74d3c7d2e26..e3d6e15ff188 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -214,24 +214,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
        if (policy->cpu >= NUM_CPUS)
                return -EINVAL;
-        cpu_clk = clk_get_sys(NULL, "cpu");
-        if (IS_ERR(cpu_clk))
-                return PTR_ERR(cpu_clk);
-        pll_x_clk = clk_get_sys(NULL, "pll_x");
-        if (IS_ERR(pll_x_clk))
-                return PTR_ERR(pll_x_clk);
-        pll_p_clk = clk_get_sys(NULL, "pll_p");
-        if (IS_ERR(pll_p_clk))
-                return PTR_ERR(pll_p_clk);
-        emc_clk = clk_get_sys("cpu", "emc");
-        if (IS_ERR(emc_clk)) {
-                clk_put(cpu_clk);
-                return PTR_ERR(emc_clk);
-        }
        clk_prepare_enable(emc_clk);
        clk_prepare_enable(cpu_clk);
@@ -243,8 +225,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
        /* FIXME: what's the actual transition time? */
        policy->cpuinfo.transition_latency = 300 * 1000;
-        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+        cpumask_copy(policy->cpus, cpu_possible_mask);
-        cpumask_copy(policy->related_cpus, cpu_possible_mask);
        if (policy->cpu == 0)
                register_pm_notifier(&tegra_cpu_pm_notifier);
@@ -256,8 +237,6 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy)
 {
        cpufreq_frequency_table_cpuinfo(policy, freq_table);
        clk_disable_unprepare(emc_clk);
-        clk_put(emc_clk);
-        clk_put(cpu_clk);
        return 0;
 }
@@ -278,12 +257,32 @@ static struct cpufreq_driver tegra_cpufreq_driver = {
 static int __init tegra_cpufreq_init(void)
 {
+        cpu_clk = clk_get_sys(NULL, "cpu");
+        if (IS_ERR(cpu_clk))
+                return PTR_ERR(cpu_clk);
+        pll_x_clk = clk_get_sys(NULL, "pll_x");
+        if (IS_ERR(pll_x_clk))
+                return PTR_ERR(pll_x_clk);
+        pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
+        if (IS_ERR(pll_p_clk))
+                return PTR_ERR(pll_p_clk);
+        emc_clk = clk_get_sys("cpu", "emc");
+        if (IS_ERR(emc_clk)) {
+                clk_put(cpu_clk);
+                return PTR_ERR(emc_clk);
+        }
        return cpufreq_register_driver(&tegra_cpufreq_driver);
 }
 static void __exit tegra_cpufreq_exit(void)
 {
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
+        clk_put(emc_clk);
+        clk_put(cpu_clk);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
new file mode 100644
index 000000000000..0f4e8c483b34
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+#include <asm/cpuidle.h>
+static struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+        .state_count = 1,
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+        },
+};
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+int __init tegra114_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index d32e8b0dbd4f..825ced4f7a40 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -22,21 +22,199 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
+#include <linux/clk/tegra.h>
 #include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+#include "pm.h"
+#include "sleep.h"
+#include "iomap.h"
+#include "irq.h"
+#include "flowctrl.h"
+#ifdef CONFIG_PM_SLEEP
+static bool abort_flag;
+static atomic_t abort_barrier;
+static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+                                    struct cpuidle_driver *drv,
+                                    int index);
+#endif
+static struct cpuidle_state tegra_idle_states[] = {
+        [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+        [1] = {
+                .enter                  = tegra20_idle_lp2_coupled,
+                .exit_latency           = 5000,
+                .target_residency       = 10000,
+                .power_usage            = 0,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID |
+                                          CPUIDLE_FLAG_COUPLED,
+                .name                   = "powered-down",
+                .desc                   = "CPU power gated",
+        },
+#endif
+};
 static struct cpuidle_driver tegra_idle_driver = {
        .name = "tegra_idle",
        .owner = THIS_MODULE,
        .en_core_tk_irqen = 1,
-        .state_count = 1,
-        .states = {
-                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-        },
 };
 static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_SMP
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static int tegra20_reset_sleeping_cpu_1(void)
+{
+        int ret = 0;
+        tegra_pen_lock();
+        if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
+                tegra20_cpu_shutdown(1);
+        else
+                ret = -EINVAL;
+        tegra_pen_unlock();
+        return ret;
+}
+static void tegra20_wake_cpu1_from_reset(void)
+{
+        tegra_pen_lock();
+        tegra20_cpu_clear_resettable();
+        /* enable cpu clock on cpu */
+        tegra_enable_cpu_clock(1);
+        /* take the CPU out of reset */
+        tegra_cpu_out_of_reset(1);
+        /* unhalt the cpu */
+        flowctrl_write_cpu_halt(1, 0);
+        tegra_pen_unlock();
+}
+static int tegra20_reset_cpu_1(void)
+{
+        if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
+                return 0;
+        tegra20_wake_cpu1_from_reset();
+        return -EBUSY;
+}
+#else
+static inline void tegra20_wake_cpu1_from_reset(void)
+{
+}
+static inline int tegra20_reset_cpu_1(void)
+{
+        return 0;
+}
+#endif
+static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
+                                           struct cpuidle_driver *drv,
+                                           int index)
+{
+        struct cpuidle_state *state = &drv->states[index];
+        u32 cpu_on_time = state->exit_latency;
+        u32 cpu_off_time = state->target_residency - state->exit_latency;
+        while (tegra20_cpu_is_resettable_soon())
+                cpu_relax();
+        if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
+                return false;
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+        if (cpu_online(1))
+                tegra20_wake_cpu1_from_reset();
+        return true;
+}
+#ifdef CONFIG_SMP
+static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+                                         struct cpuidle_driver *drv,
+                                         int index)
+{
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+        cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
+        tegra20_cpu_clear_resettable();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+        return true;
+}
+#else
+static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+                                                struct cpuidle_driver *drv,
+                                                int index)
+{
+        return true;
+}
+#endif
+static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+                                    struct cpuidle_driver *drv,
+                                    int index)
+{
+        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+        bool entered_lp2 = false;
+        if (tegra_pending_sgi())
+                ACCESS_ONCE(abort_flag) = true;
+        cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+        if (abort_flag) {
+                cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+                abort_flag = false;     /* clean flag for next coming */
+                return -EINTR;
+        }
+        local_fiq_disable();
+        tegra_set_cpu_in_lp2(cpu);
+        cpu_pm_enter();
+        if (cpu == 0)
+                entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
+        else
+                entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
+        cpu_pm_exit();
+        tegra_clear_cpu_in_lp2(cpu);
+        local_fiq_enable();
+        smp_rmb();
+        return entered_lp2 ? index : 0;
+}
+#endif
 int __init tegra20_cpuidle_init(void)
 {
        int ret;
@@ -44,6 +222,14 @@ int __init tegra20_cpuidle_init(void)
        struct cpuidle_device *dev;
        struct cpuidle_driver *drv = &tegra_idle_driver;
+#ifdef CONFIG_PM_SLEEP
+        tegra_tear_down_cpu = tegra20_tear_down_cpu;
+#endif
+        drv->state_count = ARRAY_SIZE(tegra_idle_states);
+        memcpy(drv->states, tegra_idle_states,
+                        drv->state_count * sizeof(drv->states[0]));
        ret = cpuidle_register_driver(&tegra_idle_driver);
        if (ret) {
                pr_err("CPUidle driver registration failed\n");
@@ -53,6 +239,9 @@ int __init tegra20_cpuidle_init(void)
        for_each_possible_cpu(cpu) {
                dev = &per_cpu(tegra_idle_device, cpu);
                dev->cpu = cpu;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+                dev->coupled_cpus = *cpu_possible_mask;
+#endif
                dev->state_count = drv->state_count;
                ret = cpuidle_register_device(dev);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 5e8cbf5b799f..8b50cf4ddd6f 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -24,6 +24,7 @@
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
 #include <linux/clockchips.h>
+#include <linux/clk/tegra.h>
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
@@ -32,7 +33,6 @@
 #include "pm.h"
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 #ifdef CONFIG_PM_SLEEP
 static int tegra30_idle_lp2(struct cpuidle_device *dev,
@@ -121,9 +121,9 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 }
 #endif
-static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
+static int tegra30_idle_lp2(struct cpuidle_device *dev,
-                                      struct cpuidle_driver *drv,
+                            struct cpuidle_driver *drv,
-                                      int index)
+                            int index)
 {
        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
        bool entered_lp2 = false;
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index d0651397aec7..4b744c4661e2 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -38,6 +38,9 @@ static int __init tegra_cpuidle_init(void)
        case TEGRA30:
                ret = tegra30_cpuidle_init();
                break;
+        case TEGRA114:
+                ret = tegra114_cpuidle_init();
+                break;
        default:
                ret = -ENODEV;
                break;
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index 496204d34e55..d733f75d0208 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -29,4 +29,10 @@ int tegra30_cpuidle_init(void);
 static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
 #endif
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+int tegra114_cpuidle_init(void);
+#else
+static inline int tegra114_cpuidle_init(void) { return -ENODEV; }
+#endif
 #endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index a2250ddae797..b477ef310dcd 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -25,15 +25,16 @@
 #include "flowctrl.h"
 #include "iomap.h"
+#include "fuse.h"
-u8 flowctrl_offset_halt_cpu[] = {
+static u8 flowctrl_offset_halt_cpu[] = {
        FLOW_CTRL_HALT_CPU0_EVENTS,
        FLOW_CTRL_HALT_CPU1_EVENTS,
        FLOW_CTRL_HALT_CPU1_EVENTS + 8,
        FLOW_CTRL_HALT_CPU1_EVENTS + 16,
 };
-u8 flowctrl_offset_cpu_csr[] = {
+static u8 flowctrl_offset_cpu_csr[] = {
        FLOW_CTRL_CPU0_CSR,
        FLOW_CTRL_CPU1_CSR,
        FLOW_CTRL_CPU1_CSR + 8,
@@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
        int i;
        reg = flowctrl_read_cpu_csr(cpuid);
-        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        switch (tegra_chip_id) {
-        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        case TEGRA20:
+                /* clear wfe bitmap */
+                reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+                /* clear wfi bitmap */
+                reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+                /* pwr gating on wfe */
+                reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
+                break;
+        case TEGRA30:
+                /* clear wfe bitmap */
+                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+                /* clear wfi bitmap */
+                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+                /* pwr gating on wfi */
+                reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
+                break;
+        }
        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr flag */
        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event flag */
-        reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
        reg |= FLOW_CTRL_CSR_ENABLE;                    /* pwr gating */
        flowctrl_write_cpu_csr(cpuid, reg);
@@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
        /* Disable powergating via flow controller for CPU0 */
        reg = flowctrl_read_cpu_csr(cpuid);
-        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        switch (tegra_chip_id) {
-        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        case TEGRA20:
+                /* clear wfe bitmap */
+                reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+                /* clear wfi bitmap */
+                reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+                break;
+        case TEGRA30:
+                /* clear wfe bitmap */
+                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+                /* clear wfi bitmap */
+                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+                break;
+        }
        reg &= ~FLOW_CTRL_CSR_ENABLE;                   /* clear enable */
        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr */
        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event */
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 0798dec1832d..67eab56699bd 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,6 +34,10 @@
 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
 #define FLOW_CTRL_CPU1_CSR              0x18
+#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0          (1 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP        (3 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP        0
 #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
 #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
 #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 8121742711fe..f7db0782a6b6 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -20,6 +20,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/export.h>
+#include <linux/tegra-soc.h>
 #include "fuse.h"
 #include "iomap.h"
@@ -105,6 +106,11 @@ static void tegra_get_process_id(void)
        tegra_core_process_id = (reg >> 12) & 3;
 }
+u32 tegra_read_chipid(void)
+{
+        return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+}
 void tegra_init_fuse(void)
 {
        u32 id;
@@ -119,7 +125,7 @@ void tegra_init_fuse(void)
        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
-        id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+        id = tegra_read_chipid();
        tegra_chip_id = (id >> 8) & 0xff;
        switch (tegra_chip_id) {
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index ff1383dd61a7..da78434678c7 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -37,6 +37,7 @@ enum tegra_revision {
 #define TEGRA20         0x20
 #define TEGRA30         0x30
+#define TEGRA114        0x35
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4a317fae6860..fd473f2b4c3d 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,66 +1,9 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/cache.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-#include "flowctrl.h"
-#include "iomap.h"
-#include "reset.h"
 #include "sleep.h"
-#define APB_MISC_GP_HIDREV      0x804
-#define PMC_SCRATCH41   0x140
-#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
        .section ".text.head", "ax"
-        __CPUINIT
-/*
- * Tegra specific entry point for secondary CPUs.
- *   The secondary kernel init calls v7_flush_dcache_all before it enables
- *   the L1; however, the L1 comes out of reset in an undefined state, so
- *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- *   of cache lines with uninitialized data and uninitialized tags to get
- *   written out to memory, which does really unpleasant things to the main
- *   processor.  We fix this by performing an invalidate, rather than a
- *   clean + invalidate, before jumping into the kernel.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3  @ NumWays - 1
-        add     r2, r2, #1          @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4          @ SetShift
-        clz     r1, r3              @ WayShift
-        add     r4, r3, #1          @ NumWays
-1:      sub     r2, r2, #1          @ NumSets--
-        mov     r3, r4              @ Temp = NumWays
-2:      subs    r3, r3, #1          @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 ENTRY(tegra_secondary_startup)
        bl      v7_invalidate_l1
@@ -69,210 +12,3 @@ ENTRY(tegra_secondary_startup)
        mcr     p14, 0, r0, c7, c12, 6
        b       secondary_startup
 ENDPROC(tegra_secondary_startup)
-#ifdef CONFIG_PM_SLEEP
-/*
- *      tegra_resume
- *
- *        CPU boot vector when restarting the a CPU following
- *        an LP2 transition. Also branched to by LP0 and LP1 resume after
- *        re-enabling sdram.
- */
-ENTRY(tegra_resume)
-        bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
-        cpu_id  r0
-        cmp     r0, #0                          @ CPU0?
-        bne     cpu_resume                      @ no
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-        /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
-        beq     1f                              @ Yes
-        /* Clear the flow controller flags for this CPU. */
-        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
-        ldr     r1, [r2]
-        /* Clear event & intr flag */
-        orr     r1, r1, \
-                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
-        bic     r1, r1, r0
-        str     r1, [r2]
-1:
-#endif
-#ifdef CONFIG_HAVE_ARM_SCU
-        /* enable SCU */
-        mov32   r0, TEGRA_ARM_PERIF_BASE
-        ldr     r1, [r0]
-        orr     r1, r1, #1
-        str     r1, [r0]
-#endif
-        /* L2 cache resume & re-enable */
-        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
-        b       cpu_resume
-ENDPROC(tegra_resume)
-#endif
-#ifdef CONFIG_CACHE_L2X0
-        .globl  l2x0_saved_regs_addr
-l2x0_saved_regs_addr:
-        .long   0
-#endif
-        .align L1_CACHE_SHIFT
-ENTRY(__tegra_cpu_reset_handler_start)
-/*
- * __tegra_cpu_reset_handler:
- *
- * Common handler for all CPU reset events.
- *
- * Register usage within the reset handler:
- *
- *      R7  = CPU present (to the OS) mask
- *      R8  = CPU in LP1 state mask
- *      R9  = CPU in LP2 state mask
- *      R10 = CPU number
- *      R11 = CPU mask
- *      R12 = pointer to reset handler data
- *
- * NOTE: This code is copied to IRAM. All code and data accesses
- *       must be position-independent.
- */
-        .align L1_CACHE_SHIFT
-ENTRY(__tegra_cpu_reset_handler)
-        cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
-        mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
-        and     r10, r10, #0x3                  @ R10 = CPU number
-        mov     r11, #1
-        mov     r11, r11, lsl r10               @ R11 = CPU mask
-        adr     r12, __tegra_cpu_reset_handler_data
-#ifdef CONFIG_SMP
-        /* Does the OS know about this CPU? */
-        ldr     r7, [r12, #RESET_DATA(MASK_PRESENT)]
-        tst     r7, r11                         @ if !present
-        bleq    __die                           @ CPU not present (to OS)
-#endif
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
-        bne     1f
-        /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r6, TEGRA_PMC_BASE
-        mov     r0, #0
-        cmp     r10, #0
-        strne   r0, [r6, #PMC_SCRATCH41]
-1:
-#endif
-        /* Waking up from LP2? */
-        ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
-        tst     r9, r11                         @ if in_lp2
-        beq     __is_not_lp2
-        ldr     lr, [r12, #RESET_DATA(STARTUP_LP2)]
-        cmp     lr, #0
-        bleq    __die                           @ no LP2 startup handler
-        bx      lr
-__is_not_lp2:
-#ifdef CONFIG_SMP
-        /*
-         * Can only be secondary boot (initial or hotplug) but CPU 0
-         * cannot be here.
-         */
-        cmp     r10, #0
-        bleq    __die                           @ CPU0 cannot be here
-        ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
-        cmp     lr, #0
-        bleq    __die                           @ no secondary startup handler
-        bx      lr
-#endif
-/*
- * We don't know why the CPU reset. Just kill it.
- * The LR register will contain the address we died at + 4.
- */
-__die:
-        sub     lr, lr, #4
-        mov32   r7, TEGRA_PMC_BASE
-        str     lr, [r7, #PMC_SCRATCH41]
-        mov32   r7, TEGRA_CLK_RESET_BASE
-        /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
-        bne     1f
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        mov32   r0, 0x1111
-        mov     r1, r0, lsl r10
-        str     r1, [r7, #0x340]                @ CLK_RST_CPU_CMPLX_SET
-#endif
-1:
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-        mov32   r6, TEGRA_FLOW_CTRL_BASE
-        cmp     r10, #0
-        moveq   r1, #FLOW_CTRL_HALT_CPU0_EVENTS
-        moveq   r2, #FLOW_CTRL_CPU0_CSR
-        movne   r1, r10, lsl #3
-        addne   r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
-        addne   r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
-        /* Clear CPU "event" and "interrupt" flags and power gate
-           it when halting but not before it is in the "WFI" state. */
-        ldr     r0, [r6, +r2]
-        orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
-        str     r0, [r6, +r2]
-        /* Unconditionally halt this CPU */
-        mov     r0, #FLOW_CTRL_WAITEVENT
-        str     r0, [r6, +r1]
-        ldr     r0, [r6, +r1]                   @ memory barrier
-        dsb
-        isb
-        wfi                                     @ CPU should be power gated here
-        /* If the CPU didn't power gate above just kill it's clock. */
-        mov     r0, r11, lsl #8
-        str     r0, [r7, #348]                  @ CLK_CPU_CMPLX_SET
-#endif
-        /* If the CPU still isn't dead, just spin here. */
-        b       .
-ENDPROC(__tegra_cpu_reset_handler)
-        .align L1_CACHE_SHIFT
-        .type   __tegra_cpu_reset_handler_data, %object
-        .globl  __tegra_cpu_reset_handler_data
-__tegra_cpu_reset_handler_data:
-        .rept   TEGRA_RESET_DATA_SIZE
-        .long   0
-        .endr
-        .align L1_CACHE_SHIFT
-ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index dca5141a2c31..a599f6e36dea 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -10,15 +10,26 @@
 */
 #include <linux/kernel.h>
 #include <linux/smp.h>
+#include <linux/clk/tegra.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 static void (*tegra_hotplug_shutdown)(void);
+int tegra_cpu_kill(unsigned cpu)
+{
+        cpu = cpu_logical_map(cpu);
+        /* Clock gate the CPU */
+        tegra_wait_cpu_in_reset(cpu);
+        tegra_disable_cpu_clock(cpu);
+        return 1;
+}
 /*
 * platform-specific code to shutdown a CPU
 *
@@ -26,18 +37,12 @@ static void (*tegra_hotplug_shutdown)(void);
 */
 void __ref tegra_cpu_die(unsigned int cpu)
 {
-        cpu = cpu_logical_map(cpu);
+        /* Clean L1 data cache */
+        tegra_disable_clean_inv_dcache();
-        /* Flush the L1 data cache. */
-        flush_cache_all();
        /* Shut down the current CPU. */
        tegra_hotplug_shutdown();
-        /* Clock gate the CPU */
-        tegra_wait_cpu_in_reset(cpu);
-        tegra_disable_cpu_clock(cpu);
        /* Should never return here. */
        BUG();
 }
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
deleted file mode 100644
index 95f3a547c770..000000000000
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/clk.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_CLK_H
-#define __MACH_CLK_H
-struct clk;
-enum tegra_clk_ex_param {
-        TEGRA_CLK_VI_INP_SEL,
-        TEGRA_CLK_DTV_INVERT,
-        TEGRA_CLK_NAND_PAD_DIV2_ENB,
-        TEGRA_CLK_PLLD_CSI_OUT_ENB,
-        TEGRA_CLK_PLLD_DSI_OUT_ENB,
-        TEGRA_CLK_PLLD_MIPI_MUX_SEL,
-};
-void tegra_periph_reset_deassert(struct clk *c);
-void tegra_periph_reset_assert(struct clk *c);
-#ifndef CONFIG_COMMON_CLK
-unsigned long clk_get_rate_all_locked(struct clk *c);
-#endif
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
-int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 485003f9b636..08386418196f 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -172,8 +172,4 @@ static inline void arch_decomp_setup(void)
        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
 }
-static inline void arch_decomp_wdog(void)
-{
-}
 #endif
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index db8be51cad80..399fbca27102 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -240,15 +240,6 @@
 #define TEGRA_CSITE_BASE                0x70040000
 #define TEGRA_CSITE_SIZE                SZ_256K
-#define TEGRA_USB_BASE                  0xC5000000
-#define TEGRA_USB_SIZE                  SZ_16K
-#define TEGRA_USB2_BASE                 0xC5004000
-#define TEGRA_USB2_SIZE                 SZ_16K
-#define TEGRA_USB3_BASE                 0xC5008000
-#define TEGRA_USB3_SIZE                 SZ_16K
 #define TEGRA_SDMMC1_BASE               0xC8000000
 #define TEGRA_SDMMC1_SIZE               SZ_512
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index b7886f183511..1952e82797cc 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -22,8 +22,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/irqchip/arm-gic.h>
-#include <asm/hardware/gic.h>
 #include "board.h"
 #include "iomap.h"
@@ -45,6 +44,8 @@
 #define FIRST_LEGACY_IRQ 32
+#define SGI_MASK 0xFFFF
 static int num_ictlrs;
 static void __iomem *ictlr_reg_base[] = {
@@ -55,6 +56,19 @@ static void __iomem *ictlr_reg_base[] = {
        IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
+bool tegra_pending_sgi(void)
+{
+        u32 pending_set;
+        void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+        pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
+        if (pending_set & SGI_MASK)
+                return true;
+        return false;
+}
 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
 {
        void __iomem *base;
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
new file mode 100644
index 000000000000..5142649bba05
--- /dev/null
+++ b/arch/arm/mach-tegra/irq.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __TEGRA_IRQ_H
+#define __TEGRA_IRQ_H
+bool tegra_pending_sgi(void);
+#endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index bffcd643d7a3..b60165f1ca02 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -33,11 +33,11 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/export.h>
+#include <linux/clk/tegra.h>
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
-#include <mach/clk.h>
 #include <mach/powergate.h>
 #include "board.h"
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1b926df99c4b..2c6b3d55213b 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,25 +18,26 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/clk/tegra.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
 #include <mach/powergate.h>
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
-#include "tegra_cpu_car.h"
 #include "common.h"
 #include "iomap.h"
 extern void tegra_secondary_startup(void);
-static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
+static cpumask_t tegra_cpu_init_mask;
 #define EVP_CPU_RESET_VECTOR \
        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
@@ -50,6 +51,7 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu)
         */
        gic_secondary_init(0);
+        cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
 static int tegra20_power_up_cpu(unsigned int cpu)
@@ -72,14 +74,42 @@ static int tegra30_power_up_cpu(unsigned int cpu)
        if (pwrgateid < 0)
                return pwrgateid;
-        /* If this is the first boot, toggle powergates directly. */
+        /*
+         * The power up sequence of cold boot CPU and warm boot CPU
+         * was different.
+         *
+         * For warm boot CPU that was resumed from CPU hotplug, the
+         * power will be resumed automatically after un-halting the
+         * flow controller of the warm boot CPU. We need to wait for
+         * the confirmaiton that the CPU is powered then removing
+         * the IO clamps.
+         * For cold boot CPU, do not wait. After the cold boot CPU be
+         * booted, it will run to tegra_secondary_init() and set
+         * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
+         * next time around.
+         */
+        if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+                timeout = jiffies + msecs_to_jiffies(50);
+                do {
+                        if (!tegra_powergate_is_powered(pwrgateid))
+                                goto remove_clamps;
+                        udelay(10);
+                } while (time_before(jiffies, timeout));
+        }
+        /*
+         * The power status of the cold boot CPU is power gated as
+         * default. To power up the cold boot CPU, the power should
+         * be un-gated by un-toggling the power gate register
+         * manually.
+         */
        if (!tegra_powergate_is_powered(pwrgateid)) {
                ret = tegra_powergate_power_on(pwrgateid);
                if (ret)
                        return ret;
                /* Wait for the power to come up. */
-                timeout = jiffies + 10*HZ;
+                timeout = jiffies + msecs_to_jiffies(100);
                while (tegra_powergate_is_powered(pwrgateid)) {
                        if (time_after(jiffies, timeout))
                                return -ETIMEDOUT;
@@ -87,6 +117,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
                }
        }
+remove_clamps:
        /* CPU partition is powered. Enable the CPU clock. */
        tegra_enable_cpu_clock(cpu);
        udelay(10);
@@ -105,6 +136,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *
 {
        int status;
+        cpu = cpu_logical_map(cpu);
        /*
         * Force the CPU into reset. The CPU must remain in reset when the
         * flow controller state is cleared (which will cause the flow
@@ -143,38 +176,21 @@ done:
        return status;
 }
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init tegra_smp_init_cpus(void)
-{
-        unsigned int i, ncores = scu_get_core_count(scu_base);
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                        ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
-}
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
 {
-        tegra_cpu_reset_handler_init();
+        /* Always mark the boot CPU (CPU0) as initialized. */
-        scu_enable(scu_base);
+        cpumask_set_cpu(0, &tegra_cpu_init_mask);
+        if (scu_a9_has_base())
+                scu_enable(IO_ADDRESS(scu_a9_get_base()));
 }
 struct smp_operations tegra_smp_ops __initdata = {
-        .smp_init_cpus          = tegra_smp_init_cpus,
        .smp_prepare_cpus       = tegra_smp_prepare_cpus,
        .smp_secondary_init     = tegra_secondary_init,
        .smp_boot_secondary     = tegra_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = tegra_cpu_kill,
        .cpu_die                = tegra_cpu_die,
        .cpu_disable            = tegra_cpu_disable,
 #endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 1b11707eaca0..523604de666f 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
 #include <linux/cpu_pm.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/clk/tegra.h>
 #include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
@@ -35,8 +36,8 @@
 #include "iomap.h"
 #include "reset.h"
 #include "flowctrl.h"
+#include "fuse.h"
 #include "sleep.h"
-#include "tegra_cpu_car.h"
 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
@@ -148,7 +149,7 @@ static void suspend_cpu_complex(void)
        save_cpu_arch_register();
 }
-void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
+void tegra_clear_cpu_in_lp2(int phy_cpu_id)
 {
        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -160,7 +161,7 @@ void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
        spin_unlock(&tegra_lp2_lock);
 }
-bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
+bool tegra_set_cpu_in_lp2(int phy_cpu_id)
 {
        bool last_cpu = false;
        cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
@@ -173,6 +174,8 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
        if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
                last_cpu = true;
+        else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
+                tegra20_cpu_set_resettable_soon();
        spin_unlock(&tegra_lp2_lock);
        return last_cpu;
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 2cc1185d902e..c6bc8f85759c 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -26,8 +26,8 @@
 #include <linux/io.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
+#include <linux/clk/tegra.h>
-#include <mach/clk.h>
 #include <mach/powergate.h>
 #include "fuse.h"
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
new file mode 100644
index 000000000000..54382ceade4a
--- /dev/null
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/cache.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "flowctrl.h"
+#include "iomap.h"
+#include "reset.h"
+#include "sleep.h"
+#define APB_MISC_GP_HIDREV      0x804
+#define PMC_SCRATCH41   0x140
+#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
+#ifdef CONFIG_PM_SLEEP
+/*
+ *      tegra_resume
+ *
+ *        CPU boot vector when restarting the a CPU following
+ *        an LP2 transition. Also branched to by LP0 and LP1 resume after
+ *        re-enabling sdram.
+ */
+ENTRY(tegra_resume)
+        bl      v7_invalidate_l1
+        /* Enable coresight */
+        mov32   r0, 0xC5ACCE55
+        mcr     p14, 0, r0, c7, c12, 6
+        cpu_id  r0
+        cmp     r0, #0                          @ CPU0?
+        bne     cpu_resume                      @ no
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        beq     1f                              @ Yes
+        /* Clear the flow controller flags for this CPU. */
+        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
+        ldr     r1, [r2]
+        /* Clear event & intr flag */
+        orr     r1, r1, \
+                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        bic     r1, r1, r0
+        str     r1, [r2]
+1:
+#endif
+#ifdef CONFIG_HAVE_ARM_SCU
+        /* enable SCU */
+        mov32   r0, TEGRA_ARM_PERIF_BASE
+        ldr     r1, [r0]
+        orr     r1, r1, #1
+        str     r1, [r0]
+#endif
+        /* L2 cache resume & re-enable */
+        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+        b       cpu_resume
+ENDPROC(tegra_resume)
+#endif
+#ifdef CONFIG_CACHE_L2X0
+        .globl  l2x0_saved_regs_addr
+l2x0_saved_regs_addr:
+        .long   0
+#endif
+        .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler_start)
+/*
+ * __tegra_cpu_reset_handler:
+ *
+ * Common handler for all CPU reset events.
+ *
+ * Register usage within the reset handler:
+ *
+ *      R7  = CPU present (to the OS) mask
+ *      R8  = CPU in LP1 state mask
+ *      R9  = CPU in LP2 state mask
+ *      R10 = CPU number
+ *      R11 = CPU mask
+ *      R12 = pointer to reset handler data
+ *
+ * NOTE: This code is copied to IRAM. All code and data accesses
+ *       must be position-independent.
+ */
+        .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler)
+        cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+        mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
+        and     r10, r10, #0x3                  @ R10 = CPU number
+        mov     r11, #1
+        mov     r11, r11, lsl r10               @ R11 = CPU mask
+        adr     r12, __tegra_cpu_reset_handler_data
+#ifdef CONFIG_SMP
+        /* Does the OS know about this CPU? */
+        ldr     r7, [r12, #RESET_DATA(MASK_PRESENT)]
+        tst     r7, r11                         @ if !present
+        bleq    __die                           @ CPU not present (to OS)
+#endif
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        bne     1f
+        /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
+        mov32   r6, TEGRA_PMC_BASE
+        mov     r0, #0
+        cmp     r10, #0
+        strne   r0, [r6, #PMC_SCRATCH41]
+1:
+#endif
+        /* Waking up from LP2? */
+        ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
+        tst     r9, r11                         @ if in_lp2
+        beq     __is_not_lp2
+        ldr     lr, [r12, #RESET_DATA(STARTUP_LP2)]
+        cmp     lr, #0
+        bleq    __die                           @ no LP2 startup handler
+        bx      lr
+__is_not_lp2:
+#ifdef CONFIG_SMP
+        /*
+         * Can only be secondary boot (initial or hotplug) but CPU 0
+         * cannot be here.
+         */
+        cmp     r10, #0
+        bleq    __die                           @ CPU0 cannot be here
+        ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
+        cmp     lr, #0
+        bleq    __die                           @ no secondary startup handler
+        bx      lr
+#endif
+/*
+ * We don't know why the CPU reset. Just kill it.
+ * The LR register will contain the address we died at + 4.
+ */
+__die:
+        sub     lr, lr, #4
+        mov32   r7, TEGRA_PMC_BASE
+        str     lr, [r7, #PMC_SCRATCH41]
+        mov32   r7, TEGRA_CLK_RESET_BASE
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        bne     1f
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        mov32   r0, 0x1111
+        mov     r1, r0, lsl r10
+        str     r1, [r7, #0x340]                @ CLK_RST_CPU_CMPLX_SET
+#endif
+1:
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+        cmp     r10, #0
+        moveq   r1, #FLOW_CTRL_HALT_CPU0_EVENTS
+        moveq   r2, #FLOW_CTRL_CPU0_CSR
+        movne   r1, r10, lsl #3
+        addne   r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
+        addne   r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
+        /* Clear CPU "event" and "interrupt" flags and power gate
+           it when halting but not before it is in the "WFI" state. */
+        ldr     r0, [r6, +r2]
+        orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
+        str     r0, [r6, +r2]
+        /* Unconditionally halt this CPU */
+        mov     r0, #FLOW_CTRL_WAITEVENT
+        str     r0, [r6, +r1]
+        ldr     r0, [r6, +r1]                   @ memory barrier
+        dsb
+        isb
+        wfi                                     @ CPU should be power gated here
+        /* If the CPU didn't power gate above just kill it's clock. */
+        mov     r0, r11, lsl #8
+        str     r0, [r7, #348]                  @ CLK_CPU_CMPLX_SET
+#endif
+        /* If the CPU still isn't dead, just spin here. */
+        b       .
+ENDPROC(__tegra_cpu_reset_handler)
+        .align L1_CACHE_SHIFT
+        .type   __tegra_cpu_reset_handler_data, %object
+        .globl  __tegra_cpu_reset_handler_data
+__tegra_cpu_reset_handler_data:
+        .rept   TEGRA_RESET_DATA_SIZE
+        .long   0
+        .endr
+        .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 3fd89ecd158e..1ac434e0068f 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -75,7 +75,7 @@ void __init tegra_cpu_reset_handler_init(void)
 #ifdef CONFIG_SMP
        __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
-                *((u32 *)cpu_present_mask);
+                *((u32 *)cpu_possible_mask);
        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
                virt_to_phys((void *)tegra_secondary_startup);
 #endif
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 72ce709799da..9f6bfafdd512 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -21,6 +21,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/proc-fns.h>
+#include <asm/cp15.h>
 #include "sleep.h"
 #include "flowctrl.h"
@@ -33,9 +35,6 @@
 * should never return
 */
 ENTRY(tegra20_hotplug_shutdown)
-        /* Turn off SMP coherency */
-        exit_smp r4, r5
        /* Put this CPU down */
        cpu_id  r0
        bl      tegra20_cpu_shutdown
@@ -58,6 +57,9 @@ ENDPROC(tegra20_hotplug_shutdown)
 ENTRY(tegra20_cpu_shutdown)
        cmp     r0, #0
        moveq   pc, lr                  @ must not be called for CPU 0
+        mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+        mov     r12, #CPU_RESETTABLE
+        str     r12, [r1]
        cpu_to_halt_reg r1, r0
        ldr     r3, =TEGRA_FLOW_CTRL_VIRT
@@ -78,3 +80,198 @@ ENTRY(tegra20_cpu_shutdown)
        mov     pc, lr
 ENDPROC(tegra20_cpu_shutdown)
 #endif
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * The reference link of Peterson's algorithm:
+ * http://en.wikipedia.org/wiki/Peterson's_algorithm
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * r2 = flag[0] (in SCRATCH38)
+ * r3 = flag[1] (in SCRATCH39)
+ * on cpu1:
+ * r2 = flag[1] (in SCRATCH39)
+ * r3 = flag[0] (in SCRATCH38)
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+        mov32   r3, TEGRA_PMC_VIRT
+        cpu_id  r0
+        add     r1, r3, #PMC_SCRATCH37
+        cmp     r0, #0
+        addeq   r2, r3, #PMC_SCRATCH38
+        addeq   r3, r3, #PMC_SCRATCH39
+        addne   r2, r3, #PMC_SCRATCH39
+        addne   r3, r3, #PMC_SCRATCH38
+        mov     r12, #1
+        str     r12, [r2]               @ flag[cpu] = 1
+        dsb
+        str     r12, [r1]               @ !turn = cpu
+1:      dsb
+        ldr     r12, [r3]
+        cmp     r12, #1                 @ flag[!cpu] == 1?
+        ldreq   r12, [r1]
+        cmpeq   r12, r0                 @ !turn == cpu?
+        beq     1b                      @ while !turn == cpu && flag[!cpu] == 1
+        mov     pc, lr                  @ locked
+ENDPROC(tegra_pen_lock)
+ENTRY(tegra_pen_unlock)
+        dsb
+        mov32   r3, TEGRA_PMC_VIRT
+        cpu_id  r0
+        cmp     r0, #0
+        addeq   r2, r3, #PMC_SCRATCH38
+        addne   r2, r3, #PMC_SCRATCH39
+        mov     r12, #0
+        str     r12, [r2]
+        mov     pc, lr
+ENDPROC(tegra_pen_unlock)
+/*
+ * tegra20_cpu_clear_resettable(void)
+ *
+ * Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_clear_resettable)
+        mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+        mov     r12, #CPU_NOT_RESETTABLE
+        str     r12, [r1]
+        mov     pc, lr
+ENDPROC(tegra20_cpu_clear_resettable)
+/*
+ * tegra20_cpu_set_resettable_soon(void)
+ *
+ * Called to set the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_set_resettable_soon)
+        mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+        mov     r12, #CPU_RESETTABLE_SOON
+        str     r12, [r1]
+        mov     pc, lr
+ENDPROC(tegra20_cpu_set_resettable_soon)
+/*
+ * tegra20_cpu_is_resettable_soon(void)
+ *
+ * Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
+ * set because it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_is_resettable_soon)
+        mov32   r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+        ldr     r12, [r1]
+        cmp     r12, #CPU_RESETTABLE_SOON
+        moveq   r0, #1
+        movne   r0, #0
+        mov     pc, lr
+ENDPROC(tegra20_cpu_is_resettable_soon)
+/*
+ * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters WFI on secondary CPU by exiting coherency.
+ */
+ENTRY(tegra20_sleep_cpu_secondary_finish)
+        stmfd   sp!, {r4-r11, lr}
+        mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
+        /* Flush and disable the L1 data cache */
+        bl      tegra_disable_clean_inv_dcache
+        mov32   r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
+        mov     r3, #CPU_RESETTABLE
+        str     r3, [r0]
+        bl      cpu_do_idle
+        /*
+         * cpu may be reset while in wfi, which will return through
+         * tegra_resume to cpu_resume
+         * or interrupt may wake wfi, which will return here
+         * cpu state is unchanged - MMU is on, cache is on, coherency
+         * is off, and the data cache is off
+         *
+         * r11 contains the original actlr
+         */
+        bl      tegra_pen_lock
+        mov32   r3, TEGRA_PMC_VIRT
+        add     r0, r3, #PMC_SCRATCH41
+        mov     r3, #CPU_NOT_RESETTABLE
+        str     r3, [r0]
+        bl      tegra_pen_unlock
+        /* Re-enable the data cache */
+        mrc     p15, 0, r10, c1, c0, 0
+        orr     r10, r10, #CR_C
+        mcr     p15, 0, r10, c1, c0, 0
+        isb
+        mcr     p15, 0, r11, c1, c0, 1  @ reenable coherency
+        /* Invalidate the TLBs & BTAC */
+        mov     r1, #0
+        mcr     p15, 0, r1, c8, c3, 0   @ invalidate shared TLBs
+        mcr     p15, 0, r1, c7, c1, 6   @ invalidate shared BTAC
+        dsb
+        isb
+        /* the cpu was running with coherency disabled,
+         * caches may be out of date */
+        bl      v7_flush_kern_cache_louis
+        ldmfd   sp!, {r4 - r11, pc}
+ENDPROC(tegra20_sleep_cpu_secondary_finish)
+/*
+ * tegra20_tear_down_cpu
+ *
+ * Switches the CPU cluster to PLL-P and enters sleep.
+ */
+ENTRY(tegra20_tear_down_cpu)
+        bl      tegra_switch_cpu_to_pllp
+        b       tegra20_enter_sleep
+ENDPROC(tegra20_tear_down_cpu)
+/*
+ * tegra20_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ */
+tegra20_enter_sleep:
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+        mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+        orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+        cpu_id  r1
+        cpu_to_halt_reg r1, r1
+        str     r0, [r6, r1]
+        dsb
+        ldr     r0, [r6, r1] /* memory barrier */
+halted:
+        dsb
+        wfe     /* CPU should be power gated here */
+        isb
+        b       halted
+#endif
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 562a8e7e413d..63a15bd9b653 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -32,9 +32,6 @@
 * Should never return.
 */
 ENTRY(tegra30_hotplug_shutdown)
-        /* Turn off SMP coherency */
-        exit_smp r4, r5
        /* Powergate this CPU */
        mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
        bl      tegra30_cpu_shutdown
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 26afa7cbed11..364d84523fba 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -34,7 +34,10 @@
 #include "flowctrl.h"
 #include "sleep.h"
-#ifdef CONFIG_PM_SLEEP
+#define CLK_RESET_CCLK_BURST    0x20
+#define CLK_RESET_CCLK_DIVIDER  0x24
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
 /*
 * tegra_disable_clean_inv_dcache
 *
@@ -60,7 +63,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
        ldmfd   sp!, {r0, r4-r5, r7, r9-r11, pc}
 ENDPROC(tegra_disable_clean_inv_dcache)
+#endif
+#ifdef CONFIG_PM_SLEEP
 /*
 * tegra_sleep_cpu_finish(unsigned long v2p)
 *
@@ -108,4 +113,20 @@ ENTRY(tegra_shut_off_mmu)
        mov     pc, r0
 ENDPROC(tegra_shut_off_mmu)
        .popsection
+/*
+ * tegra_switch_cpu_to_pllp
+ *
+ * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
+ */
+ENTRY(tegra_switch_cpu_to_pllp)
+        /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
+        mov32   r5, TEGRA_CLK_RESET_BASE
+        mov     r0, #(2 << 28)                  @ burst policy = run mode
+        orr     r0, r0, #(4 << 4)               @ use PLLP in run mode burst
+        str     r0, [r5, #CLK_RESET_CCLK_BURST]
+        mov     r0, #0
+        str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+        mov     pc, lr
+ENDPROC(tegra_switch_cpu_to_pllp)
 #endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 9821ee725420..4ffae541726e 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,19 @@
                                        + IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
                                        + IO_PPSB_VIRT)
+#define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
+/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
+#define PMC_SCRATCH37   0x130
+#define PMC_SCRATCH38   0x134
+#define PMC_SCRATCH39   0x138
+#define PMC_SCRATCH41   0x140
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define CPU_RESETTABLE          2
+#define CPU_RESETTABLE_SOON     1
+#define CPU_NOT_RESETTABLE      0
+#endif
 #ifdef __ASSEMBLY__
 /* returns the offset of the flow controller halt register for a cpu */
@@ -104,8 +117,11 @@ exit_l2_resume:
 .endm
 #endif /* CONFIG_CACHE_L2X0 */
 #else
+void tegra_pen_lock(void);
+void tegra_pen_unlock(void);
 void tegra_resume(void);
 int tegra_sleep_cpu_finish(unsigned long);
+void tegra_disable_clean_inv_dcache(void);
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_init(void);
@@ -115,6 +131,17 @@ static inline void tegra20_hotplug_init(void) {}
 static inline void tegra30_hotplug_init(void) {}
 #endif
+void tegra20_cpu_shutdown(int cpu);
+int tegra20_cpu_is_resettable_soon(void);
+void tegra20_cpu_clear_resettable(void);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_cpu_set_resettable_soon(void);
+#else
+static inline void tegra20_cpu_set_resettable_soon(void) {}
+#endif
+int tegra20_sleep_cpu_secondary_finish(unsigned long);
+void tegra20_tear_down_cpu(void);
 int tegra30_sleep_cpu_secondary_finish(unsigned long);
 void tegra30_tear_down_cpu(void);
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
deleted file mode 100644
index 4eb6bc81a87b..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ /dev/null
@@ -1,1623 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra20_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include "clock.h"
-#include "fuse.h"
-#include "iomap.h"
-#include "tegra2_emc.h"
-#include "tegra_cpu_car.h"
-#define RST_DEVICES                     0x004
-#define RST_DEVICES_SET                 0x300
-#define RST_DEVICES_CLR                 0x304
-#define RST_DEVICES_NUM                 3
-#define CLK_OUT_ENB                     0x010
-#define CLK_OUT_ENB_SET                 0x320
-#define CLK_OUT_ENB_CLR                 0x324
-#define CLK_OUT_ENB_NUM                 3
-#define CLK_MASK_ARM                    0x44
-#define MISC_CLK_ENB                    0x48
-#define OSC_CTRL                        0x50
-#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
-#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
-#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
-#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
-#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-#define OSC_FREQ_DET                    0x58
-#define OSC_FREQ_DET_TRIG               (1<<31)
-#define OSC_FREQ_DET_STATUS             0x5C
-#define OSC_FREQ_DET_BUSY               (1<<31)
-#define OSC_FREQ_DET_CNT_MASK           0xFFFF
-#define PERIPH_CLK_SOURCE_I2S1          0x100
-#define PERIPH_CLK_SOURCE_EMC           0x19c
-#define PERIPH_CLK_SOURCE_OSC           0x1fc
-#define PERIPH_CLK_SOURCE_NUM \
-        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-#define PERIPH_CLK_SOURCE_MASK          (3<<30)
-#define PERIPH_CLK_SOURCE_SHIFT         30
-#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
-#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
-#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
-#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
-#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
-#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
-#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
-#define PLL_BASE                        0x0
-#define PLL_BASE_BYPASS                 (1<<31)
-#define PLL_BASE_ENABLE                 (1<<30)
-#define PLL_BASE_REF_ENABLE             (1<<29)
-#define PLL_BASE_OVERRIDE               (1<<28)
-#define PLL_BASE_DIVP_MASK              (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT             20
-#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT             8
-#define PLL_BASE_DIVM_MASK              (0x1F)
-#define PLL_BASE_DIVM_SHIFT             0
-#define PLL_OUT_RATIO_MASK              (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT             8
-#define PLL_OUT_OVERRIDE                (1<<2)
-#define PLL_OUT_CLKEN                   (1<<1)
-#define PLL_OUT_RESET_DISABLE           (1<<0)
-#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-#define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_CPCON_SHIFT            8
-#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT            4
-#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT           0
-#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
-#define PLLU_BASE_POST_DIV              (1<<20)
-#define PLLD_MISC_CLKENABLE             (1<<30)
-#define PLLD_MISC_DIV_RST               (1<<23)
-#define PLLD_MISC_DCCON_SHIFT           12
-#define PLLE_MISC_READY                 (1 << 15)
-#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
-#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
-#define SUPER_CLK_MUX                   0x00
-#define SUPER_STATE_SHIFT               28
-#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_SOURCE_MASK               0xF
-#define SUPER_FIQ_SOURCE_SHIFT          12
-#define SUPER_IRQ_SOURCE_SHIFT          8
-#define SUPER_RUN_SOURCE_SHIFT          4
-#define SUPER_IDLE_SOURCE_SHIFT         0
-#define SUPER_CLK_DIVIDER               0x04
-#define BUS_CLK_DISABLE                 (1<<3)
-#define BUS_CLK_DIV_MASK                0x3
-#define PMC_CTRL                        0x0
- #define PMC_CTRL_BLINK_ENB             (1 << 7)
-#define PMC_DPD_PADS_ORIDE              0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
-#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
-#define PMC_BLINK_TIMER_ENB             (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
-/* Tegra CPU clock and reset control regs */
-#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
-#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
-#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
-#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
-#define CPU_RESET(cpu)  (0x1111ul << (cpu))
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-/*
- * Some clocks share a register with other clocks.  Any clock op that
- * non-atomically modifies a register used by another clock must lock
- * clock_register_lock first.
- */
-static DEFINE_SPINLOCK(clock_register_lock);
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
- */
-static int tegra_periph_clk_enable_refcount[3 * 32];
-#define clk_writel(value, reg) \
-        __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
-        __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-static unsigned long clk_measure_input_freq(void)
-{
-        u32 clock_autodetect;
-        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
-        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
-        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
-        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
-                return 12000000;
-        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
-                return 13000000;
-        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
-                return 19200000;
-        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
-                return 26000000;
-        } else {
-                pr_err("%s: Unexpected clock autodetect value %d",
-                                                __func__, clock_autodetect);
-                BUG();
-                return 0;
-        }
-}
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u71 = parent_rate * 2;
-        divider_u71 += rate - 1;
-        do_div(divider_u71, rate);
-        if (divider_u71 - 2 < 0)
-                return 0;
-        if (divider_u71 - 2 > 255)
-                return -EINVAL;
-        return divider_u71 - 2;
-}
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u16;
-        divider_u16 = parent_rate;
-        divider_u16 += rate - 1;
-        do_div(divider_u16, rate);
-        if (divider_u16 - 1 < 0)
-                return 0;
-        if (divider_u16 - 1 > 0xFFFF)
-                return -EINVAL;
-        return divider_u16 - 1;
-}
-static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        return to_clk_tegra(hw)->fixed_rate;
-}
-struct clk_ops tegra_clk_32k_ops = {
-        .recalc_rate = tegra_clk_fixed_recalc_rate,
-};
-/* clk_m functions */
-static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        if (!to_clk_tegra(hw)->fixed_rate)
-                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
-        return to_clk_tegra(hw)->fixed_rate;
-}
-static void tegra20_clk_m_init(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 osc_ctrl = clk_readl(OSC_CTRL);
-        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
-        switch (c->fixed_rate) {
-        case 12000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
-                break;
-        case 13000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
-                break;
-        case 19200000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
-                break;
-        case 26000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
-                break;
-        default:
-                BUG();
-        }
-        clk_writel(auto_clock_control, OSC_CTRL);
-}
-struct clk_ops tegra_clk_m_ops = {
-        .init = tegra20_clk_m_init,
-        .recalc_rate = tegra20_clk_m_recalc_rate,
-};
-/* super clock functions */
-/* "super clocks" on tegra have two-stage muxes and a clock skipping
- * super divider.  We will ignore the clock skipping divider, since we
- * can't lower the voltage when using the clock skip, but we can if we
- * lower the PLL frequency.
- */
-static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        c->state = ON;
-        return c->state;
-}
-static int tegra20_super_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
-        return 0;
-}
-static void tegra20_super_clk_disable(struct clk_hw *hw)
-{
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        int val = clk_readl(c->reg + SUPER_CLK_MUX);
-        int source;
-        int shift;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        return source;
-}
-static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
-        int shift;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        val &= ~(SUPER_SOURCE_MASK << shift);
-        val |= index << shift;
-        clk_writel(val, c->reg);
-        return 0;
-}
-/* FIX ME: Need to switch parents to change the source PLL rate */
-static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        return prate;
-}
-static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        return *prate;
-}
-static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        return 0;
-}
-struct clk_ops tegra_super_ops = {
-        .is_enabled = tegra20_super_clk_is_enabled,
-        .enable = tegra20_super_clk_enable,
-        .disable = tegra20_super_clk_disable,
-        .set_parent = tegra20_super_clk_set_parent,
-        .get_parent = tegra20_super_clk_get_parent,
-        .set_rate = tegra20_super_clk_set_rate,
-        .round_rate = tegra20_super_clk_round_rate,
-        .recalc_rate = tegra20_super_clk_recalc_rate,
-};
-static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra_twd_ops = {
-        .recalc_rate = tegra20_twd_clk_recalc_rate,
-};
-static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
-{
-        return 0;
-}
-struct clk_ops tegra_cop_ops = {
-        .get_parent = tegra20_cop_clk_get_parent,
-};
-/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
- * reset the COP block (i.e. AVP) */
-void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
-{
-        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
-        clk_writel(1 << 1, reg);
-}
-/* bus clock functions */
-static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-        return c->state;
-}
-static int tegra20_bus_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        u32 val;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
-        clk_writel(val, c->reg);
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return 0;
-}
-static void tegra20_bus_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        u32 val;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        val |= BUS_CLK_DISABLE << c->reg_shift;
-        clk_writel(val, c->reg);
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        u64 rate = prate;
-        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-        c->mul = 1;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        int ret = -EINVAL;
-        unsigned long flags;
-        u32 val;
-        int i;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        for (i = 1; i <= 4; i++) {
-                if (rate == parent_rate / i) {
-                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
-                        val |= (i - 1) << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = i;
-                        c->mul = 1;
-                        ret = 0;
-                        break;
-                }
-        }
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return ret;
-}
-static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        unsigned long parent_rate = *prate;
-        s64 divider;
-        if (rate >= parent_rate)
-                return rate;
-        divider = parent_rate;
-        divider += rate - 1;
-        do_div(divider, rate);
-        if (divider < 0)
-                return divider;
-        if (divider > 4)
-                divider = 4;
-        do_div(parent_rate, divider);
-        return parent_rate;
-}
-struct clk_ops tegra_bus_ops = {
-        .is_enabled = tegra20_bus_clk_is_enabled,
-        .enable = tegra20_bus_clk_enable,
-        .disable = tegra20_bus_clk_disable,
-        .set_rate = tegra20_bus_clk_set_rate,
-        .round_rate = tegra20_bus_clk_round_rate,
-        .recalc_rate = tegra20_bus_clk_recalc_rate,
-};
-/* Blink output functions */
-static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        return c->state;
-}
-static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = prate;
-        u32 val;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static int tegra20_blink_clk_enable(struct clk_hw *hw)
-{
-        u32 val;
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        return 0;
-}
-static void tegra20_blink_clk_disable(struct clk_hw *hw)
-{
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (rate >= parent_rate) {
-                c->div = 1;
-                pmc_writel(0, c->reg);
-        } else {
-                unsigned int on_off;
-                u32 val;
-                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
-                c->div = on_off * 8;
-                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
-                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
-                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val |= on_off;
-                val |= PMC_BLINK_TIMER_ENB;
-                pmc_writel(val, c->reg);
-        }
-        return 0;
-}
-static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        int div;
-        int mul;
-        long round_rate = *prate;
-        mul = 1;
-        if (rate >= *prate) {
-                div = 1;
-        } else {
-                div = DIV_ROUND_UP(*prate / 8, rate);
-                div *= 8;
-        }
-        round_rate *= mul;
-        round_rate += div - 1;
-        do_div(round_rate, div);
-        return round_rate;
-}
-struct clk_ops tegra_blink_clk_ops = {
-        .is_enabled = tegra20_blink_clk_is_enabled,
-        .enable = tegra20_blink_clk_enable,
-        .disable = tegra20_blink_clk_disable,
-        .set_rate = tegra20_blink_clk_set_rate,
-        .round_rate = tegra20_blink_clk_round_rate,
-        .recalc_rate = tegra20_blink_clk_recalc_rate,
-};
-/* PLL Functions */
-static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
-{
-        udelay(c->u.pll.lock_delay);
-        return 0;
-}
-static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg + PLL_BASE);
-        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-        return c->state;
-}
-static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
-                                unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg + PLL_BASE);
-        u64 rate = prate;
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                const struct clk_pll_freq_table *sel;
-                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                        if (sel->input_rate == prate &&
-                                sel->output_rate == c->u.pll.fixed_rate) {
-                                c->mul = sel->n;
-                                c->div = sel->m * sel->p;
-                                break;
-                        }
-                }
-                pr_err("Clock %s has unknown fixed frequency\n",
-                        __clk_get_name(hw->clk));
-                BUG();
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static int tegra20_pll_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLL_BASE_BYPASS;
-        val |= PLL_BASE_ENABLE;
-        clk_writel(val, c->reg + PLL_BASE);
-        tegra20_pll_clk_wait_for_lock(c);
-        return 0;
-}
-static void tegra20_pll_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        val = clk_readl(c->reg);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        clk_writel(val, c->reg);
-}
-static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long input_rate = parent_rate;
-        const struct clk_pll_freq_table *sel;
-        u32 val;
-        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
-        if (c->flags & PLL_FIXED) {
-                int ret = 0;
-                if (rate != c->u.pll.fixed_rate) {
-                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-                                __func__, __clk_get_name(hw->clk),
-                                c->u.pll.fixed_rate, rate);
-                        ret = -EINVAL;
-                }
-                return ret;
-        }
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        c->mul = sel->n;
-                        c->div = sel->m * sel->p;
-                        val = clk_readl(c->reg + PLL_BASE);
-                        if (c->flags & PLL_FIXED)
-                                val |= PLL_BASE_OVERRIDE;
-                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
-                                 PLL_BASE_DIVM_MASK);
-                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
-                                (sel->n << PLL_BASE_DIVN_SHIFT);
-                        BUG_ON(sel->p < 1 || sel->p > 2);
-                        if (c->flags & PLLU) {
-                                if (sel->p == 1)
-                                        val |= PLLU_BASE_POST_DIV;
-                        } else {
-                                if (sel->p == 2)
-                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
-                        }
-                        clk_writel(val, c->reg + PLL_BASE);
-                        if (c->flags & PLL_HAS_CPCON) {
-                                val = clk_readl(c->reg + PLL_MISC(c));
-                                val &= ~PLL_MISC_CPCON_MASK;
-                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
-                                clk_writel(val, c->reg + PLL_MISC(c));
-                        }
-                        if (c->state == ON)
-                                tegra20_pll_clk_enable(hw);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        const struct clk_pll_freq_table *sel;
-        unsigned long input_rate = *prate;
-        u64 output_rate = *prate;
-        int mul;
-        int div;
-        if (c->flags & PLL_FIXED)
-                return c->u.pll.fixed_rate;
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        mul = sel->n;
-                        div = sel->m * sel->p;
-                        break;
-                }
-        if (sel->input_rate == 0)
-                return -EINVAL;
-        output_rate *= mul;
-        output_rate += div - 1; /* round up */
-        do_div(output_rate, div);
-        return output_rate;
-}
-struct clk_ops tegra_pll_ops = {
-        .is_enabled = tegra20_pll_clk_is_enabled,
-        .enable = tegra20_pll_clk_enable,
-        .disable = tegra20_pll_clk_disable,
-        .set_rate = tegra20_pll_clk_set_rate,
-        .recalc_rate = tegra20_pll_clk_recalc_rate,
-        .round_rate = tegra20_pll_clk_round_rate,
-};
-static void tegra20_pllx_clk_init(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (tegra_sku_id == 7)
-                c->max_rate = 750000000;
-}
-struct clk_ops tegra_pllx_ops = {
-        .init = tegra20_pllx_clk_init,
-        .is_enabled = tegra20_pll_clk_is_enabled,
-        .enable = tegra20_pll_clk_enable,
-        .disable = tegra20_pll_clk_disable,
-        .set_rate = tegra20_pll_clk_set_rate,
-        .recalc_rate = tegra20_pll_clk_recalc_rate,
-        .round_rate = tegra20_pll_clk_round_rate,
-};
-static int tegra20_plle_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        mdelay(1);
-        val = clk_readl(c->reg + PLL_BASE);
-        if (!(val & PLLE_MISC_READY))
-                return -EBUSY;
-        val = clk_readl(c->reg + PLL_BASE);
-        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
-        clk_writel(val, c->reg + PLL_BASE);
-        return 0;
-}
-struct clk_ops tegra_plle_ops = {
-        .is_enabled = tegra20_pll_clk_is_enabled,
-        .enable = tegra20_plle_clk_enable,
-        .set_rate = tegra20_pll_clk_set_rate,
-        .recalc_rate = tegra20_pll_clk_recalc_rate,
-        .round_rate = tegra20_pll_clk_round_rate,
-};
-/* Clock divider ops */
-static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        val >>= c->reg_shift;
-        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
-        if (!(val & PLL_OUT_RESET_DISABLE))
-                c->state = OFF;
-        return c->state;
-}
-static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = prate;
-        u32 val = clk_readl(c->reg);
-        u32 divu71;
-        val >>= c->reg_shift;
-        if (c->flags & DIV_U71) {
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->div = 2;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-        rate *= c->mul;
-        rate += c->div - 1; /* round up */
-        do_div(rate, c->div);
-        return rate;
-}
-static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        u32 new_val;
-        u32 val;
-        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val &= ~PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        }
-        return -EINVAL;
-}
-static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        u32 new_val;
-        u32 val;
-        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val |= PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        }
-}
-static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        int divider_u71;
-        u32 new_val;
-        u32 val;
-        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
-        if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(parent_rate, rate);
-                if (divider_u71 >= 0) {
-                        spin_lock_irqsave(&clock_register_lock, flags);
-                        val = clk_readl(c->reg);
-                        new_val = val >> c->reg_shift;
-                        new_val &= 0xFFFF;
-                        if (c->flags & DIV_U71_FIXED)
-                                new_val |= PLL_OUT_OVERRIDE;
-                        new_val &= ~PLL_OUT_RATIO_MASK;
-                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-                        val &= ~(0xFFFF << c->reg_shift);
-                        val |= new_val << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = divider_u71 + 2;
-                        c->mul = 2;
-                        spin_unlock_irqrestore(&clock_register_lock, flags);
-                        return 0;
-                }
-        } else if (c->flags & DIV_2) {
-                if (parent_rate == rate * 2)
-                        return 0;
-        }
-        return -EINVAL;
-}
-static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long parent_rate = *prate;
-        int divider;
-        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2) {
-                return DIV_ROUND_UP(parent_rate, 2);
-        }
-        return -EINVAL;
-}
-struct clk_ops tegra_pll_div_ops = {
-        .is_enabled = tegra20_pll_div_clk_is_enabled,
-        .enable = tegra20_pll_div_clk_enable,
-        .disable = tegra20_pll_div_clk_disable,
-        .set_rate = tegra20_pll_div_clk_set_rate,
-        .round_rate = tegra20_pll_div_clk_round_rate,
-        .recalc_rate = tegra20_pll_div_clk_recalc_rate,
-};
-/* Periph clk ops */
-static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        c->state = ON;
-        if (!c->u.periph.clk_num)
-                goto out;
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-        if (!(c->flags & PERIPH_NO_RESET))
-                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
-                                PERIPH_CLK_TO_ENB_BIT(c))
-                        c->state = OFF;
-out:
-        return c->state;
-}
-static int tegra20_periph_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        if (!c->u.periph.clk_num)
-                return 0;
-        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
-                return 0;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (c->flags & PERIPH_EMC_ENB) {
-                /* The EMC peripheral clock has 2 extra enable bits */
-                /* FIXME: Do they need to be disabled? */
-                val = clk_readl(c->reg);
-                val |= 0x3 << 24;
-                clk_writel(val, c->reg);
-        }
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return 0;
-}
-static void tegra20_periph_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long flags;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        if (!c->u.periph.clk_num)
-                return;
-        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
-                return;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-        pr_debug("%s %s on clock %s\n", __func__,
-                assert ? "assert" : "deassert", __clk_get_name(hw->clk));
-        BUG_ON(!c->u.periph.clk_num);
-        if (!(c->flags & PERIPH_NO_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        u32 mask;
-        u32 shift;
-        pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-        val = clk_readl(c->reg);
-        val &= ~mask;
-        val |= (index) << shift;
-        clk_writel(val, c->reg);
-        return 0;
-}
-static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        u32 mask;
-        u32 shift;
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-        if (c->flags & MUX)
-                return (val & mask) >> shift;
-        else
-                return 0;
-}
-static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long rate = prate;
-        u32 val = clk_readl(c->reg);
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-                return rate;
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        int divider;
-        val = clk_readl(c->reg);
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 2;
-                        c->mul = 2;
-                        return 0;
-                }
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 1;
-                        c->mul = 1;
-                        return 0;
-                }
-        } else if (parent_rate <= rate) {
-                c->div = 1;
-                c->mul = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
-        unsigned long rate, unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
-        int divider;
-        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
-        if (prate)
-                parent_rate = *prate;
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate, divider + 1);
-        }
-        return -EINVAL;
-}
-struct clk_ops tegra_periph_clk_ops = {
-        .is_enabled = tegra20_periph_clk_is_enabled,
-        .enable = tegra20_periph_clk_enable,
-        .disable = tegra20_periph_clk_disable,
-        .set_parent = tegra20_periph_clk_set_parent,
-        .get_parent = tegra20_periph_clk_get_parent,
-        .set_rate = tegra20_periph_clk_set_rate,
-        .round_rate = tegra20_periph_clk_round_rate,
-        .recalc_rate = tegra20_periph_clk_recalc_rate,
-};
-/* External memory controller clock ops */
-static void tegra20_emc_clk_init(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        c->max_rate = __clk_get_rate(hw->clk);
-}
-static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        long emc_rate;
-        long clk_rate;
-        /*
-         * The slowest entry in the EMC clock table that is at least as
-         * fast as rate.
-         */
-        emc_rate = tegra_emc_round_rate(rate);
-        if (emc_rate < 0)
-                return c->max_rate;
-        /*
-         * The fastest rate the PLL will generate that is at most the
-         * requested rate.
-         */
-        clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
-        /*
-         * If this fails, and emc_rate > clk_rate, it's because the maximum
-         * rate in the EMC tables is larger than the maximum rate of the EMC
-         * clock. The EMC clock's max rate is the rate it was running when the
-         * kernel booted. Such a mismatch is probably due to using the wrong
-         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
-         */
-        WARN_ONCE(emc_rate != clk_rate,
-                "emc_rate %ld != clk_rate %ld",
-                emc_rate, clk_rate);
-        return emc_rate;
-}
-static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        int ret;
-        /*
-         * The Tegra2 memory controller has an interlock with the clock
-         * block that allows memory shadowed registers to be updated,
-         * and then transfer them to the main registers at the same
-         * time as the clock update without glitches.
-         */
-        ret = tegra_emc_set_rate(rate);
-        if (ret < 0)
-                return ret;
-        ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
-        udelay(1);
-        return ret;
-}
-struct clk_ops tegra_emc_clk_ops = {
-        .init = tegra20_emc_clk_init,
-        .is_enabled = tegra20_periph_clk_is_enabled,
-        .enable = tegra20_periph_clk_enable,
-        .disable = tegra20_periph_clk_disable,
-        .set_parent = tegra20_periph_clk_set_parent,
-        .get_parent = tegra20_periph_clk_get_parent,
-        .set_rate = tegra20_emc_clk_set_rate,
-        .round_rate = tegra20_emc_clk_round_rate,
-        .recalc_rate = tegra20_periph_clk_recalc_rate,
-};
-/* Clock doubler ops */
-static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        c->state = ON;
-        if (!c->u.periph.clk_num)
-                goto out;
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-out:
-        return c->state;
-};
-static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = prate;
-        c->mul = 2;
-        c->div = 1;
-        rate *= c->mul;
-        rate += c->div - 1; /* round up */
-        do_div(rate, c->div);
-        return rate;
-}
-static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        unsigned long output_rate = *prate;
-        do_div(output_rate, 2);
-        return output_rate;
-}
-static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        if (rate != 2 * parent_rate)
-                return -EINVAL;
-        return 0;
-}
-struct clk_ops tegra_clk_double_ops = {
-        .is_enabled = tegra20_clk_double_is_enabled,
-        .enable = tegra20_periph_clk_enable,
-        .disable = tegra20_periph_clk_disable,
-        .set_rate = tegra20_clk_double_set_rate,
-        .recalc_rate = tegra20_clk_double_recalc_rate,
-        .round_rate = tegra20_clk_double_round_rate,
-};
-/* Audio sync clock ops */
-static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        c->state = (val & (1<<4)) ? OFF : ON;
-        return c->state;
-}
-static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        clk_writel(0, c->reg);
-        return 0;
-}
-static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        clk_writel(1, c->reg);
-}
-static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        int source;
-        source = val & 0xf;
-        return source;
-}
-static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg);
-        val &= ~0xf;
-        val |= index;
-        clk_writel(val, c->reg);
-        return 0;
-}
-struct clk_ops tegra_audio_sync_clk_ops = {
-        .is_enabled = tegra20_audio_sync_clk_is_enabled,
-        .enable = tegra20_audio_sync_clk_enable,
-        .disable = tegra20_audio_sync_clk_disable,
-        .set_parent = tegra20_audio_sync_clk_set_parent,
-        .get_parent = tegra20_audio_sync_clk_get_parent,
-};
-/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
-static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
-         * currently done in the pinmux code. */
-        c->state = ON;
-        BUG_ON(!c->u.periph.clk_num);
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-        return c->state;
-}
-static int tegra20_cdev_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        BUG_ON(!c->u.periph.clk_num);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        return 0;
-}
-static void tegra20_cdev_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        BUG_ON(!c->u.periph.clk_num);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        return to_clk_tegra(hw)->fixed_rate;
-}
-struct clk_ops tegra_cdev_clk_ops = {
-        .is_enabled = tegra20_cdev_clk_is_enabled,
-        .enable = tegra20_cdev_clk_enable,
-        .disable = tegra20_cdev_clk_disable,
-        .recalc_rate = tegra20_cdev_recalc_rate,
-};
-/* Tegra20 CPU clock and reset control functions */
-static void tegra20_wait_cpu_in_reset(u32 cpu)
-{
-        unsigned int reg;
-        do {
-                reg = readl(reg_clk_base +
-                            TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-                cpu_relax();
-        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
-        return;
-}
-static void tegra20_put_cpu_in_reset(u32 cpu)
-{
-        writel(CPU_RESET(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-        dmb();
-}
-static void tegra20_cpu_out_of_reset(u32 cpu)
-{
-        writel(CPU_RESET(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-        wmb();
-}
-static void tegra20_enable_cpu_clock(u32 cpu)
-{
-        unsigned int reg;
-        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg & ~CPU_CLOCK(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        barrier();
-        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-}
-static void tegra20_disable_cpu_clock(u32 cpu)
-{
-        unsigned int reg;
-        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg | CPU_CLOCK(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-}
-static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
-        .wait_for_reset = tegra20_wait_cpu_in_reset,
-        .put_in_reset   = tegra20_put_cpu_in_reset,
-        .out_of_reset   = tegra20_cpu_out_of_reset,
-        .enable_clock   = tegra20_enable_cpu_clock,
-        .disable_clock  = tegra20_disable_cpu_clock,
-};
-void __init tegra20_cpu_car_ops_init(void)
-{
-        tegra_cpu_car_ops = &tegra20_cpu_car_ops;
-}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
deleted file mode 100644
index 8bfd31bcc490..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __MACH_TEGRA20_CLOCK_H
-#define __MACH_TEGRA20_CLOCK_H
-extern struct clk_ops tegra_clk_32k_ops;
-extern struct clk_ops tegra_pll_ops;
-extern struct clk_ops tegra_clk_m_ops;
-extern struct clk_ops tegra_pll_div_ops;
-extern struct clk_ops tegra_pllx_ops;
-extern struct clk_ops tegra_plle_ops;
-extern struct clk_ops tegra_clk_double_ops;
-extern struct clk_ops tegra_cdev_clk_ops;
-extern struct clk_ops tegra_audio_sync_clk_ops;
-extern struct clk_ops tegra_super_ops;
-extern struct clk_ops tegra_cpu_ops;
-extern struct clk_ops tegra_twd_ops;
-extern struct clk_ops tegra_cop_ops;
-extern struct clk_ops tegra_bus_ops;
-extern struct clk_ops tegra_blink_clk_ops;
-extern struct clk_ops tegra_emc_clk_ops;
-extern struct clk_ops tegra_periph_clk_ops;
-extern struct clk_ops tegra_clk_shared_bus_ops;
-void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
-void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
-#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
deleted file mode 100644
index a23a0734e352..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ /dev/null
@@ -1,1143 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra2_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clk-private.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include "clock.h"
-#include "fuse.h"
-#include "tegra2_emc.h"
-#include "tegra20_clocks.h"
-#include "tegra_cpu_car.h"
-/* Clock definitions */
-#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
-                   _parent_names, _parents, _parent)            \
-        static struct clk tegra_##_name = {                     \
-                .hw = &tegra_##_name##_hw.hw,                   \
-                .name = #_name,                                 \
-                .rate = _rate,                                  \
-                .ops = _ops,                                    \
-                .flags = _flags,                                \
-                .parent_names = _parent_names,                  \
-                .parents = _parents,                            \
-                .num_parents = ARRAY_SIZE(_parent_names),       \
-                .parent = _parent,                              \
-        };
-static struct clk tegra_clk_32k;
-static struct clk_tegra tegra_clk_32k_hw = {
-        .hw = {
-                .clk = &tegra_clk_32k,
-        },
-        .fixed_rate = 32768,
-};
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops = &tegra_clk_32k_ops,
-        .hw = &tegra_clk_32k_hw.hw,
-        .flags = CLK_IS_ROOT,
-};
-static struct clk tegra_clk_m;
-static struct clk_tegra tegra_clk_m_hw = {
-        .hw = {
-                .clk = &tegra_clk_m,
-        },
-        .flags = ENABLE_ON_INIT,
-        .reg = 0x1fc,
-        .reg_shift = 28,
-        .max_rate = 26000000,
-        .fixed_rate = 0,
-};
-static struct clk tegra_clk_m = {
-        .name = "clk_m",
-        .ops = &tegra_clk_m_ops,
-        .hw = &tegra_clk_m_hw.hw,
-        .flags = CLK_IS_ROOT,
-};
-#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
-                   _input_max, _cf_min, _cf_max, _vco_min,      \
-                   _vco_max, _freq_table, _lock_delay, _ops,    \
-                   _fixed_rate, _parent)                        \
-        static const char *tegra_##_name##_parent_names[] = {   \
-                #_parent,                                       \
-        };                                                      \
-        static struct clk *tegra_##_name##_parents[] = {        \
-                &tegra_##_parent,                               \
-        };                                                      \
-        static struct clk tegra_##_name;                        \
-        static struct clk_tegra tegra_##_name##_hw = {          \
-                .hw = {                                         \
-                        .clk = &tegra_##_name,                  \
-                },                                              \
-                .flags = _flags,                                \
-                .reg = _reg,                                    \
-                .max_rate = _max_rate,                          \
-                .u.pll = {                                      \
-                        .input_min = _input_min,                \
-                        .input_max = _input_max,                \
-                        .cf_min = _cf_min,                      \
-                        .cf_max = _cf_max,                      \
-                        .vco_min = _vco_min,                    \
-                        .vco_max = _vco_max,                    \
-                        .freq_table = _freq_table,              \
-                        .lock_delay = _lock_delay,              \
-                        .fixed_rate = _fixed_rate,              \
-                },                                              \
-        };                                                      \
-        static struct clk tegra_##_name = {                     \
-                .name = #_name,                                 \
-                .ops = &_ops,                                   \
-                .hw = &tegra_##_name##_hw.hw,                   \
-                .parent = &tegra_##_parent,                     \
-                .parent_names = tegra_##_name##_parent_names,   \
-                .parents = tegra_##_name##_parents,             \
-                .num_parents = 1,                               \
-        };
-#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
-                _max_rate, _ops, _parent, _clk_flags)           \
-        static const char *tegra_##_name##_parent_names[] = {   \
-                #_parent,                                       \
-        };                                                      \
-        static struct clk *tegra_##_name##_parents[] = {        \
-                &tegra_##_parent,                               \
-        };                                                      \
-        static struct clk tegra_##_name;                        \
-        static struct clk_tegra tegra_##_name##_hw = {          \
-                .hw = {                                         \
-                        .clk = &tegra_##_name,                  \
-                },                                              \
-                .flags = _flags,                                \
-                .reg = _reg,                                    \
-                .max_rate = _max_rate,                          \
-                .reg_shift = _reg_shift,                        \
-        };                                                      \
-        static struct clk tegra_##_name = {                     \
-                .name = #_name,                                 \
-                .ops = &tegra_pll_div_ops,                      \
-                .hw = &tegra_##_name##_hw.hw,                   \
-                .parent = &tegra_##_parent,                     \
-                .parent_names = tegra_##_name##_parent_names,   \
-                .parents = tegra_##_name##_parents,             \
-                .num_parents = 1,                               \
-                .flags = _clk_flags,                            \
-        };
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
-        {32768, 12000000, 366, 1, 1, 0},
-        {32768, 13000000, 397, 1, 1, 0},
-        {32768, 19200000, 586, 1, 1, 0},
-        {32768, 26000000, 793, 1, 1, 0},
-        {0, 0, 0, 0, 0, 0},
-};
-DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
-                0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
-                tegra_pll_ops, 0, clk_32k);
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
-                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
-                tegra_pll_ops, 0, clk_m);
-DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
-                tegra_pll_div_ops, pll_c, 0);
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
-                6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
-                tegra_pll_ops, 0, clk_m);
-DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
-                tegra_pll_div_ops, pll_m, 0);
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
-                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
-                tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
-DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
-                432000000, tegra_pll_div_ops, pll_p, 0);
-DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
-                432000000, tegra_pll_div_ops, pll_p, 0);
-DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
-                432000000, tegra_pll_div_ops, pll_p, 0);
-DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
-                432000000, tegra_pll_div_ops, pll_p, 0);
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
-                6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
-                tegra_pll_ops, 0, pll_p_out1);
-DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
-                tegra_pll_div_ops, pll_a, 0);
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
-        { 12000000, 297000000,  99,  4, 1, 4 },
-        { 12000000, 339000000, 113,  4, 1, 4 },
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-        { 12000000, 616000000, 616, 12, 1, 8},
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
-                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
-                1000, tegra_pll_ops, 0, clk_m);
-DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
-                tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
-                48000000, 960000000, tegra_pll_u_freq_table, 1000,
-                tegra_pll_ops, 0, clk_m);
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
-        /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
-        /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
-        /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
-        /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
-        /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
-        /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
-                31000000, 1000000, 6000000, 20000000, 1200000000,
-                tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
-                0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
-static const char *tegra_common_parent_names[] = {
-        "clk_m",
-};
-static struct clk *tegra_common_parents[] = {
-        &tegra_clk_m,
-};
-static struct clk tegra_clk_d;
-static struct clk_tegra tegra_clk_d_hw = {
-        .hw = {
-                .clk = &tegra_clk_d,
-        },
-        .flags = PERIPH_NO_RESET,
-        .reg = 0x34,
-        .reg_shift = 12,
-        .max_rate = 52000000,
-        .u.periph = {
-                .clk_num = 90,
-        },
-};
-static struct clk tegra_clk_d = {
-        .name = "clk_d",
-        .hw = &tegra_clk_d_hw.hw,
-        .ops = &tegra_clk_double_ops,
-        .parent = &tegra_clk_m,
-        .parent_names = tegra_common_parent_names,
-        .parents = tegra_common_parents,
-        .num_parents = ARRAY_SIZE(tegra_common_parent_names),
-};
-static struct clk tegra_cdev1;
-static struct clk_tegra tegra_cdev1_hw = {
-        .hw = {
-                .clk = &tegra_cdev1,
-        },
-        .fixed_rate = 26000000,
-        .u.periph = {
-                .clk_num = 94,
-        },
-};
-static struct clk tegra_cdev1 = {
-        .name = "cdev1",
-        .hw = &tegra_cdev1_hw.hw,
-        .ops = &tegra_cdev_clk_ops,
-        .flags = CLK_IS_ROOT,
-};
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_cdev2;
-static struct clk_tegra tegra_cdev2_hw = {
-        .hw = {
-                .clk = &tegra_cdev2,
-        },
-        .fixed_rate = 26000000,
-        .u.periph = {
-                .clk_num  = 93,
-        },
-};
-static struct clk tegra_cdev2 = {
-        .name = "cdev2",
-        .hw = &tegra_cdev2_hw.hw,
-        .ops = &tegra_cdev_clk_ops,
-        .flags = CLK_IS_ROOT,
-};
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
-        const char *name;
-        int value;
-} mux_audio_sync_clk_sources[] = {
-        { .name = "spdif_in", .value = 0 },
-        { .name = "i2s1", .value = 1 },
-        { .name = "i2s2", .value = 2 },
-        { .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
-        { .name = "ac97", .value = 3 },
-        { .name = "ext_audio_clk2", .value = 5 },
-        { .name = "ext_audio_clk1", .value = 6 },
-        { .name = "ext_vimclk", .value = 7 },
-#endif
-        { NULL, 0 }
-};
-static const char *audio_parent_names[] = {
-        "spdif_in",
-        "i2s1",
-        "i2s2",
-        "dummy",
-        "pll_a_out0",
-        "dummy",
-        "dummy",
-        "dummy",
-};
-static struct clk *audio_parents[] = {
-        NULL,
-        NULL,
-        NULL,
-        NULL,
-        NULL,
-        NULL,
-        NULL,
-        NULL,
-};
-static struct clk tegra_audio;
-static struct clk_tegra tegra_audio_hw = {
-        .hw = {
-                .clk = &tegra_audio,
-        },
-        .reg = 0x38,
-        .max_rate = 73728000,
-};
-DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
-                audio_parents, NULL);
-static const char *audio_2x_parent_names[] = {
-        "audio",
-};
-static struct clk *audio_2x_parents[] = {
-        &tegra_audio,
-};
-static struct clk tegra_audio_2x;
-static struct clk_tegra tegra_audio_2x_hw = {
-        .hw = {
-                .clk = &tegra_audio_2x,
-        },
-        .flags = PERIPH_NO_RESET,
-        .max_rate = 48000000,
-        .reg = 0x34,
-        .reg_shift = 8,
-        .u.periph = {
-                .clk_num = 89,
-        },
-};
-DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
-                audio_2x_parents, &tegra_audio);
-static struct clk_lookup tegra_audio_clk_lookups[] = {
-        { .con_id = "audio", .clk = &tegra_audio },
-        { .con_id = "audio_2x", .clk = &tegra_audio_2x }
-};
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-static void init_audio_sync_clock_mux(void)
-{
-        int i;
-        struct clk_mux_sel *sel = mux_audio_sync_clk;
-        const struct audio_sources *src = mux_audio_sync_clk_sources;
-        struct clk_lookup *lookup;
-        for (i = 0; src->name; i++, sel++, src++) {
-                sel->input = tegra_get_clock_by_name(src->name);
-                if (!sel->input)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                                src->name);
-                audio_parents[src->value] = sel->input;
-                sel->value = src->value;
-        }
-        lookup = tegra_audio_clk_lookups;
-        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-                struct clk *c = lookup->clk;
-                struct clk_tegra *clk = to_clk_tegra(c->hw);
-                __clk_init(NULL, c);
-                INIT_LIST_HEAD(&clk->shared_bus_list);
-                clk->lookup.con_id = lookup->con_id;
-                clk->lookup.clk = c;
-                clkdev_add(&clk->lookup);
-                tegra_clk_add(c);
-        }
-}
-static const char *mux_cclk[] = {
-        "clk_m",
-        "pll_c",
-        "clk_32k",
-        "pll_m",
-        "pll_p",
-        "pll_p_out4",
-        "pll_p_out3",
-        "clk_d",
-        "pll_x",
-};
-static struct clk *mux_cclk_p[] = {
-        &tegra_clk_m,
-        &tegra_pll_c,
-        &tegra_clk_32k,
-        &tegra_pll_m,
-        &tegra_pll_p,
-        &tegra_pll_p_out4,
-        &tegra_pll_p_out3,
-        &tegra_clk_d,
-        &tegra_pll_x,
-};
-static const char *mux_sclk[] = {
-        "clk_m",
-        "pll_c_out1",
-        "pll_p_out4",
-        "pllp_p_out3",
-        "pll_p_out2",
-        "clk_d",
-        "clk_32k",
-        "pll_m_out1",
-};
-static struct clk *mux_sclk_p[] = {
-        &tegra_clk_m,
-        &tegra_pll_c_out1,
-        &tegra_pll_p_out4,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out2,
-        &tegra_clk_d,
-        &tegra_clk_32k,
-        &tegra_pll_m_out1,
-};
-static struct clk tegra_cclk;
-static struct clk_tegra tegra_cclk_hw = {
-        .hw = {
-                .clk = &tegra_cclk,
-        },
-        .reg = 0x20,
-        .max_rate = 1000000000,
-};
-DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
-                mux_cclk_p, NULL);
-static const char *mux_twd[] = {
-        "cclk",
-};
-static struct clk *mux_twd_p[] = {
-        &tegra_cclk,
-};
-static struct clk tegra_clk_twd;
-static struct clk_tegra tegra_clk_twd_hw = {
-        .hw = {
-                .clk = &tegra_clk_twd,
-        },
-        .max_rate = 1000000000,
-        .mul = 1,
-        .div = 4,
-};
-static struct clk tegra_clk_twd = {
-        .name = "twd",
-        .ops = &tegra_twd_ops,
-        .hw = &tegra_clk_twd_hw.hw,
-        .parent = &tegra_cclk,
-        .parent_names = mux_twd,
-        .parents = mux_twd_p,
-        .num_parents = ARRAY_SIZE(mux_twd),
-};
-static struct clk tegra_sclk;
-static struct clk_tegra tegra_sclk_hw = {
-        .hw = {
-                .clk = &tegra_sclk,
-        },
-        .reg = 0x28,
-        .max_rate = 240000000,
-        .min_rate = 120000000,
-};
-DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
-                mux_sclk_p, NULL);
-static const char *tegra_cop_parent_names[] = {
-        "tegra_sclk",
-};
-static struct clk *tegra_cop_parents[] = {
-        &tegra_sclk,
-};
-static struct clk tegra_cop;
-static struct clk_tegra tegra_cop_hw = {
-        .hw = {
-                .clk = &tegra_cop,
-        },
-        .max_rate  = 240000000,
-        .reset = &tegra2_cop_clk_reset,
-};
-DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
-                tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
-static const char *tegra_hclk_parent_names[] = {
-        "tegra_sclk",
-};
-static struct clk *tegra_hclk_parents[] = {
-        &tegra_sclk,
-};
-static struct clk tegra_hclk;
-static struct clk_tegra tegra_hclk_hw = {
-        .hw = {
-                .clk = &tegra_hclk,
-        },
-        .flags = DIV_BUS,
-        .reg = 0x30,
-        .reg_shift = 4,
-        .max_rate = 240000000,
-};
-DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
-                tegra_hclk_parents, &tegra_sclk);
-static const char *tegra_pclk_parent_names[] = {
-        "tegra_hclk",
-};
-static struct clk *tegra_pclk_parents[] = {
-        &tegra_hclk,
-};
-static struct clk tegra_pclk;
-static struct clk_tegra tegra_pclk_hw = {
-        .hw = {
-                .clk = &tegra_pclk,
-        },
-        .flags = DIV_BUS,
-        .reg = 0x30,
-        .reg_shift = 0,
-        .max_rate = 120000000,
-};
-DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
-                tegra_pclk_parents, &tegra_hclk);
-static const char *tegra_blink_parent_names[] = {
-        "clk_32k",
-};
-static struct clk *tegra_blink_parents[] = {
-        &tegra_clk_32k,
-};
-static struct clk tegra_blink;
-static struct clk_tegra tegra_blink_hw = {
-        .hw = {
-                .clk = &tegra_blink,
-        },
-        .reg = 0x40,
-        .max_rate = 32768,
-};
-DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
-                tegra_blink_parents, &tegra_clk_32k);
-static const char *mux_pllm_pllc_pllp_plla[] = {
-        "pll_m",
-        "pll_c",
-        "pll_p",
-        "pll_a_out0",
-};
-static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
-        &tegra_pll_m,
-        &tegra_pll_c,
-        &tegra_pll_p,
-        &tegra_pll_a_out0,
-};
-static const char *mux_pllm_pllc_pllp_clkm[] = {
-        "pll_m",
-        "pll_c",
-        "pll_p",
-        "clk_m",
-};
-static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
-        &tegra_pll_m,
-        &tegra_pll_c,
-        &tegra_pll_p,
-        &tegra_clk_m,
-};
-static const char *mux_pllp_pllc_pllm_clkm[] = {
-        "pll_p",
-        "pll_c",
-        "pll_m",
-        "clk_m",
-};
-static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_pll_m,
-        &tegra_clk_m,
-};
-static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
-        "pll_a_out0",
-        "audio_2x",
-        "pll_p",
-        "clk_m",
-};
-static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
-        &tegra_pll_a_out0,
-        &tegra_audio_2x,
-        &tegra_pll_p,
-        &tegra_clk_m,
-};
-static const char *mux_pllp_plld_pllc_clkm[] = {
-        "pllp",
-        "pll_d_out0",
-        "pll_c",
-        "clk_m",
-};
-static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_d_out0,
-        &tegra_pll_c,
-        &tegra_clk_m,
-};
-static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
-        "pll_p",
-        "pll_c",
-        "audio",
-        "clk_m",
-        "clk_32k",
-};
-static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_audio,
-        &tegra_clk_m,
-        &tegra_clk_32k,
-};
-static const char *mux_pllp_pllc_pllm[] = {
-        "pll_p",
-        "pll_c",
-        "pll_m"
-};
-static struct clk *mux_pllp_pllc_pllm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_pll_m,
-};
-static const char *mux_clk_m[] = {
-        "clk_m",
-};
-static struct clk *mux_clk_m_p[] = {
-        &tegra_clk_m,
-};
-static const char *mux_pllp_out3[] = {
-        "pll_p_out3",
-};
-static struct clk *mux_pllp_out3_p[] = {
-        &tegra_pll_p_out3,
-};
-static const char *mux_plld[] = {
-        "pll_d",
-};
-static struct clk *mux_plld_p[] = {
-        &tegra_pll_d,
-};
-static const char *mux_clk_32k[] = {
-        "clk_32k",
-};
-static struct clk *mux_clk_32k_p[] = {
-        &tegra_clk_32k,
-};
-static const char *mux_pclk[] = {
-        "pclk",
-};
-static struct clk *mux_pclk_p[] = {
-        &tegra_pclk,
-};
-static struct clk tegra_emc;
-static struct clk_tegra tegra_emc_hw = {
-        .hw = {
-                .clk = &tegra_emc,
-        },
-        .reg = 0x19c,
-        .max_rate = 800000000,
-        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
-        .reset = &tegra2_periph_clk_reset,
-        .u.periph = {
-                .clk_num = 57,
-        },
-};
-DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
-                mux_pllm_pllc_pllp_clkm_p, NULL);
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
-                _max, _inputs, _flags)                  \
-        static struct clk tegra_##_name;                \
-        static struct clk_tegra tegra_##_name##_hw = {  \
-                .hw = {                                 \
-                        .clk = &tegra_##_name,          \
-                },                                      \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id = _con,                 \
-                },                                      \
-                .reg = _reg,                            \
-                .flags = _flags,                        \
-                .max_rate = _max,                       \
-                .u.periph = {                           \
-                        .clk_num = _clk_num,            \
-                },                                      \
-                .reset = tegra2_periph_clk_reset,       \
-        };                                              \
-        static struct clk tegra_##_name = {             \
-                .name = #_name,                         \
-                .ops = &tegra_periph_clk_ops,           \
-                .hw = &tegra_##_name##_hw.hw,           \
-                .parent_names = _inputs,                \
-                .parents = _inputs##_p,                 \
-                .num_parents = ARRAY_SIZE(_inputs),     \
-        };
-PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0);
-PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET);
-PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
-PERIPH_CLK(i2s1,        "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
-PERIPH_CLK(i2s2,        "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
-PERIPH_CLK(spdif_out,   "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
-PERIPH_CLK(spdif_in,    "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71);
-PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM);
-PERIPH_CLK(spi,         "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(xio,         "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(twc,         "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(ide,         "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(vde,         "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
-/* FIXME: what is la? */
-PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(dvc,         "tegra-i2c.3",          "div-clk", 47,  0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
-PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
-PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
-PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
-PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
-PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
-PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
-PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
-PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
-PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
-PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(dsi,         "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0); /* scales with voltage */
-PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0);
-PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
-PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
-PERIPH_CLK(pex,         NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
-PERIPH_CLK(afi,         NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
-PERIPH_CLK(pcie_xclk,   NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
-static struct clk *tegra_list_clks[] = {
-        &tegra_apbdma,
-        &tegra_rtc,
-        &tegra_timer,
-        &tegra_i2s1,
-        &tegra_i2s2,
-        &tegra_spdif_out,
-        &tegra_spdif_in,
-        &tegra_pwm,
-        &tegra_spi,
-        &tegra_xio,
-        &tegra_twc,
-        &tegra_sbc1,
-        &tegra_sbc2,
-        &tegra_sbc3,
-        &tegra_sbc4,
-        &tegra_ide,
-        &tegra_ndflash,
-        &tegra_vfir,
-        &tegra_sdmmc1,
-        &tegra_sdmmc2,
-        &tegra_sdmmc3,
-        &tegra_sdmmc4,
-        &tegra_vcp,
-        &tegra_bsea,
-        &tegra_bsev,
-        &tegra_vde,
-        &tegra_csite,
-        &tegra_la,
-        &tegra_owr,
-        &tegra_nor,
-        &tegra_mipi,
-        &tegra_i2c1,
-        &tegra_i2c2,
-        &tegra_i2c3,
-        &tegra_dvc,
-        &tegra_uarta,
-        &tegra_uartb,
-        &tegra_uartc,
-        &tegra_uartd,
-        &tegra_uarte,
-        &tegra_3d,
-        &tegra_2d,
-        &tegra_vi,
-        &tegra_vi_sensor,
-        &tegra_epp,
-        &tegra_mpe,
-        &tegra_host1x,
-        &tegra_cve,
-        &tegra_tvo,
-        &tegra_hdmi,
-        &tegra_tvdac,
-        &tegra_disp1,
-        &tegra_disp2,
-        &tegra_usbd,
-        &tegra_usb2,
-        &tegra_usb3,
-        &tegra_dsi,
-        &tegra_csi,
-        &tegra_isp,
-        &tegra_csus,
-        &tegra_pex,
-        &tegra_afi,
-        &tegra_pcie_xclk,
-};
-#define CLK_DUPLICATE(_name, _dev, _con)        \
-        {                                       \
-                .name   = _name,                \
-                .lookup = {                     \
-                        .dev_id = _dev,         \
-                        .con_id = _con,         \
-                },                              \
-        }
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
-        CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
-        CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
-        CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
-        CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
-        CLK_DUPLICATE("mpe",    "tegra_grhost", "mpe"),
-        CLK_DUPLICATE("cop",    "tegra-avp",    "cop"),
-        CLK_DUPLICATE("vde",    "tegra-aes",    "vde"),
-        CLK_DUPLICATE("cclk",   NULL,           "cpu"),
-        CLK_DUPLICATE("twd",    "smp_twd",      NULL),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
-        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
-        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
-        CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
-};
-#define CLK(dev, con, ck)       \
-        {                       \
-                .dev_id = dev,  \
-                .con_id = con,  \
-                .clk    = ck,   \
-        }
-static struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_pll_s,
-        &tegra_clk_m,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_e,
-        &tegra_cclk,
-        &tegra_clk_twd,
-        &tegra_sclk,
-        &tegra_hclk,
-        &tegra_pclk,
-        &tegra_clk_d,
-        &tegra_cdev1,
-        &tegra_cdev2,
-        &tegra_blink,
-        &tegra_cop,
-        &tegra_emc,
-};
-static void tegra2_init_one_clock(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(c->hw);
-        int ret;
-        ret = __clk_init(NULL, c);
-        if (ret)
-                pr_err("clk init failed %s\n", __clk_get_name(c));
-        INIT_LIST_HEAD(&clk->shared_bus_list);
-        if (!clk->lookup.dev_id && !clk->lookup.con_id)
-                clk->lookup.con_id = c->name;
-        clk->lookup.clk = c;
-        clkdev_add(&clk->lookup);
-        tegra_clk_add(c);
-}
-void __init tegra2_init_clocks(void)
-{
-        int i;
-        struct clk *c;
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra2_init_one_clock(tegra_ptr_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra2_init_one_clock(tegra_list_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-        init_audio_sync_clock_mux();
-        tegra20_cpu_car_ops_init();
-}
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index e18aa2f83ebf..ce7ce42a1ac9 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -312,11 +312,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
                return -ENOMEM;
        }
-        emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
+        emc_regbase = devm_ioremap_resource(&pdev->dev, res);
-        if (!emc_regbase) {
+        if (IS_ERR(emc_regbase))
-                dev_err(&pdev->dev, "failed to remap registers\n");
+                return PTR_ERR(emc_regbase);
-                return -ENOMEM;
-        }
        pdata = pdev->dev.platform_data;
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
deleted file mode 100644
index d7147779f8ea..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ /dev/null
@@ -1,2506 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra30_clocks.c
- *
- * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/syscore_ops.h>
-#include <asm/clkdev.h>
-#include <mach/powergate.h>
-#include "clock.h"
-#include "fuse.h"
-#include "iomap.h"
-#include "tegra_cpu_car.h"
-#define USE_PLL_LOCK_BITS 0
-#define RST_DEVICES_L                   0x004
-#define RST_DEVICES_H                   0x008
-#define RST_DEVICES_U                   0x00C
-#define RST_DEVICES_V                   0x358
-#define RST_DEVICES_W                   0x35C
-#define RST_DEVICES_SET_L               0x300
-#define RST_DEVICES_CLR_L               0x304
-#define RST_DEVICES_SET_V               0x430
-#define RST_DEVICES_CLR_V               0x434
-#define RST_DEVICES_NUM                 5
-#define CLK_OUT_ENB_L                   0x010
-#define CLK_OUT_ENB_H                   0x014
-#define CLK_OUT_ENB_U                   0x018
-#define CLK_OUT_ENB_V                   0x360
-#define CLK_OUT_ENB_W                   0x364
-#define CLK_OUT_ENB_SET_L               0x320
-#define CLK_OUT_ENB_CLR_L               0x324
-#define CLK_OUT_ENB_SET_V               0x440
-#define CLK_OUT_ENB_CLR_V               0x444
-#define CLK_OUT_ENB_NUM                 5
-#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
-#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN  (0x1 << 1)
-#define PERIPH_CLK_TO_BIT(c)            (1 << (c->u.periph.clk_num % 32))
-#define PERIPH_CLK_TO_RST_REG(c)        \
-        periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
-#define PERIPH_CLK_TO_RST_SET_REG(c)    \
-        periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
-#define PERIPH_CLK_TO_RST_CLR_REG(c)    \
-        periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
-#define PERIPH_CLK_TO_ENB_REG(c)        \
-        periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c)    \
-        periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
-#define PERIPH_CLK_TO_ENB_CLR_REG(c)    \
-        periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
-#define CLK_MASK_ARM                    0x44
-#define MISC_CLK_ENB                    0x48
-#define OSC_CTRL                        0x50
-#define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
-#define OSC_CTRL_OSC_FREQ_13MHZ         (0x0<<28)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ       (0x4<<28)
-#define OSC_CTRL_OSC_FREQ_12MHZ         (0x8<<28)
-#define OSC_CTRL_OSC_FREQ_26MHZ         (0xC<<28)
-#define OSC_CTRL_OSC_FREQ_16_8MHZ       (0x1<<28)
-#define OSC_CTRL_OSC_FREQ_38_4MHZ       (0x5<<28)
-#define OSC_CTRL_OSC_FREQ_48MHZ         (0x9<<28)
-#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-#define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
-#define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
-#define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
-#define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
-#define OSC_FREQ_DET                    0x58
-#define OSC_FREQ_DET_TRIG               (1<<31)
-#define OSC_FREQ_DET_STATUS             0x5C
-#define OSC_FREQ_DET_BUSY               (1<<31)
-#define OSC_FREQ_DET_CNT_MASK           0xFFFF
-#define PERIPH_CLK_SOURCE_I2S1          0x100
-#define PERIPH_CLK_SOURCE_EMC           0x19c
-#define PERIPH_CLK_SOURCE_OSC           0x1fc
-#define PERIPH_CLK_SOURCE_NUM1 \
-        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-#define PERIPH_CLK_SOURCE_G3D2          0x3b0
-#define PERIPH_CLK_SOURCE_SE            0x42c
-#define PERIPH_CLK_SOURCE_NUM2 \
-        ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
-#define AUDIO_DLY_CLK                   0x49c
-#define AUDIO_SYNC_CLK_SPDIF            0x4b4
-#define PERIPH_CLK_SOURCE_NUM3 \
-        ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
-#define PERIPH_CLK_SOURCE_NUM           (PERIPH_CLK_SOURCE_NUM1 + \
-                                         PERIPH_CLK_SOURCE_NUM2 + \
-                                         PERIPH_CLK_SOURCE_NUM3)
-#define CPU_SOFTRST_CTRL                0x380
-#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
-#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
-#define PERIPH_CLK_SOURCE_DIVIDLE_VAL   50
-#define PERIPH_CLK_UART_DIV_ENB         (1<<24)
-#define PERIPH_CLK_VI_SEL_EX_SHIFT      24
-#define PERIPH_CLK_VI_SEL_EX_MASK       (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
-#define PERIPH_CLK_NAND_DIV_EX_ENB      (1<<8)
-#define PERIPH_CLK_DTV_POLARITY_INV     (1<<25)
-#define AUDIO_SYNC_SOURCE_MASK          0x0F
-#define AUDIO_SYNC_DISABLE_BIT          0x10
-#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c)  ((c->reg_shift - 24) * 4)
-#define PLL_BASE                        0x0
-#define PLL_BASE_BYPASS                 (1<<31)
-#define PLL_BASE_ENABLE                 (1<<30)
-#define PLL_BASE_REF_ENABLE             (1<<29)
-#define PLL_BASE_OVERRIDE               (1<<28)
-#define PLL_BASE_LOCK                   (1<<27)
-#define PLL_BASE_DIVP_MASK              (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT             20
-#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT             8
-#define PLL_BASE_DIVM_MASK              (0x1F)
-#define PLL_BASE_DIVM_SHIFT             0
-#define PLL_OUT_RATIO_MASK              (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT             8
-#define PLL_OUT_OVERRIDE                (1<<2)
-#define PLL_OUT_CLKEN                   (1<<1)
-#define PLL_OUT_RESET_DISABLE           (1<<0)
-#define PLL_MISC(c)                     \
-        (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-#define PLL_MISC_LOCK_ENABLE(c) \
-        (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
-#define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_CPCON_SHIFT            8
-#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT            4
-#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT           0
-#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
-#define PLLD_MISC_CLKENABLE             (1<<30)
-#define PLLU_BASE_POST_DIV              (1<<20)
-#define PLLD_BASE_DSIB_MUX_SHIFT        25
-#define PLLD_BASE_DSIB_MUX_MASK         (1<<PLLD_BASE_DSIB_MUX_SHIFT)
-#define PLLD_BASE_CSI_CLKENABLE         (1<<26)
-#define PLLD_MISC_DSI_CLKENABLE         (1<<30)
-#define PLLD_MISC_DIV_RST               (1<<23)
-#define PLLD_MISC_DCCON_SHIFT           12
-#define PLLDU_LFCON_SET_DIVN            600
-/* FIXME: OUT_OF_TABLE_CPCON per pll */
-#define OUT_OF_TABLE_CPCON              0x8
-#define SUPER_CLK_MUX                   0x00
-#define SUPER_STATE_SHIFT               28
-#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_LP_DIV2_BYPASS            (0x1 << 16)
-#define SUPER_SOURCE_MASK               0xF
-#define SUPER_FIQ_SOURCE_SHIFT          12
-#define SUPER_IRQ_SOURCE_SHIFT          8
-#define SUPER_RUN_SOURCE_SHIFT          4
-#define SUPER_IDLE_SOURCE_SHIFT         0
-#define SUPER_CLK_DIVIDER               0x04
-#define SUPER_CLOCK_DIV_U71_SHIFT       16
-#define SUPER_CLOCK_DIV_U71_MASK        (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
-/* guarantees safe cpu backup */
-#define SUPER_CLOCK_DIV_U71_MIN         0x2
-#define BUS_CLK_DISABLE                 (1<<3)
-#define BUS_CLK_DIV_MASK                0x3
-#define PMC_CTRL                        0x0
- #define PMC_CTRL_BLINK_ENB             (1 << 7)
-#define PMC_DPD_PADS_ORIDE              0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
-#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
-#define PMC_BLINK_TIMER_ENB             (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
-#define PMC_PLLP_WB0_OVERRIDE                           0xf8
-#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE               (1 << 12)
-#define UTMIP_PLL_CFG2                                  0x488
-#define UTMIP_PLL_CFG2_STABLE_COUNT(x)                  (((x) & 0xfff) << 6)
-#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)              (((x) & 0x3f) << 18)
-#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN        (1 << 0)
-#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN        (1 << 2)
-#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN        (1 << 4)
-#define UTMIP_PLL_CFG1                                  0x484
-#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)              (((x) & 0x1f) << 27)
-#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x)               (((x) & 0xfff) << 0)
-#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN       (1 << 14)
-#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN       (1 << 12)
-#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN             (1 << 16)
-#define PLLE_BASE_CML_ENABLE            (1<<31)
-#define PLLE_BASE_ENABLE                (1<<30)
-#define PLLE_BASE_DIVCML_SHIFT          24
-#define PLLE_BASE_DIVCML_MASK           (0xf<<PLLE_BASE_DIVCML_SHIFT)
-#define PLLE_BASE_DIVP_SHIFT            16
-#define PLLE_BASE_DIVP_MASK             (0x3f<<PLLE_BASE_DIVP_SHIFT)
-#define PLLE_BASE_DIVN_SHIFT            8
-#define PLLE_BASE_DIVN_MASK             (0xFF<<PLLE_BASE_DIVN_SHIFT)
-#define PLLE_BASE_DIVM_SHIFT            0
-#define PLLE_BASE_DIVM_MASK             (0xFF<<PLLE_BASE_DIVM_SHIFT)
-#define PLLE_BASE_DIV_MASK              \
-        (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
-         PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
-#define PLLE_BASE_DIV(m, n, p, cml)             \
-         (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
-          ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
-#define PLLE_MISC_SETUP_BASE_SHIFT      16
-#define PLLE_MISC_SETUP_BASE_MASK       (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
-#define PLLE_MISC_READY                 (1<<15)
-#define PLLE_MISC_LOCK                  (1<<11)
-#define PLLE_MISC_LOCK_ENABLE           (1<<9)
-#define PLLE_MISC_SETUP_EX_SHIFT        2
-#define PLLE_MISC_SETUP_EX_MASK         (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
-#define PLLE_MISC_SETUP_MASK            \
-          (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
-#define PLLE_MISC_SETUP_VALUE           \
-          ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
-#define PLLE_SS_CTRL                    0x68
-#define PLLE_SS_INCINTRV_SHIFT          24
-#define PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
-#define PLLE_SS_INC_SHIFT               16
-#define PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
-#define PLLE_SS_MAX_SHIFT               0
-#define PLLE_SS_MAX_MASK                (0x1ff<<PLLE_SS_MAX_SHIFT)
-#define PLLE_SS_COEFFICIENTS_MASK       \
-        (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
-#define PLLE_SS_COEFFICIENTS_12MHZ      \
-        ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
-         (0x24<<PLLE_SS_MAX_SHIFT))
-#define PLLE_SS_DISABLE                 ((1<<12) | (1<<11) | (1<<10))
-#define PLLE_AUX                        0x48c
-#define PLLE_AUX_PLLP_SEL               (1<<2)
-#define PLLE_AUX_CML_SATA_ENABLE        (1<<1)
-#define PLLE_AUX_CML_PCIE_ENABLE        (1<<0)
-#define PMC_SATA_PWRGT                  0x1ac
-#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE  (1<<5)
-#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL  (1<<4)
-#define ROUND_DIVIDER_UP        0
-#define ROUND_DIVIDER_DOWN      1
-/* FIXME: recommended safety delay after lock is detected */
-#define PLL_POST_LOCK_DELAY             100
-/* Tegra CPU clock and reset control regs */
-#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
-#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
-#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
-#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
-#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
-#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
-#define CPU_RESET(cpu)  (0x1111ul << (cpu))
-#define CLK_RESET_CCLK_BURST    0x20
-#define CLK_RESET_CCLK_DIVIDER  0x24
-#define CLK_RESET_PLLX_BASE     0xe0
-#define CLK_RESET_PLLX_MISC     0xe4
-#define CLK_RESET_SOURCE_CSITE  0x1d4
-#define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
-#define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
-#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
-#define CLK_RESET_CCLK_IDLE_POLICY              1
-#define CLK_RESET_CCLK_RUN_POLICY               2
-#define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
-#ifdef CONFIG_PM_SLEEP
-static struct cpu_clk_suspend_context {
-        u32 pllx_misc;
-        u32 pllx_base;
-        u32 cpu_burst;
-        u32 clk_csite_src;
-        u32 cclk_divider;
-} tegra30_cpu_clk_sctx;
-#endif
-/**
-* Structure defining the fields for USB UTMI clocks Parameters.
-*/
-struct utmi_clk_param {
-        /* Oscillator Frequency in KHz */
-        u32 osc_frequency;
-        /* UTMIP PLL Enable Delay Count  */
-        u8 enable_delay_count;
-        /* UTMIP PLL Stable count */
-        u8 stable_count;
-        /*  UTMIP PLL Active delay count */
-        u8 active_delay_count;
-        /* UTMIP PLL Xtal frequency count */
-        u8 xtal_freq_count;
-};
-static const struct utmi_clk_param utmi_parameters[] = {
-        {
-                .osc_frequency = 13000000,
-                .enable_delay_count = 0x02,
-                .stable_count = 0x33,
-                .active_delay_count = 0x05,
-                .xtal_freq_count = 0x7F
-        },
-        {
-                .osc_frequency = 19200000,
-                .enable_delay_count = 0x03,
-                .stable_count = 0x4B,
-                .active_delay_count = 0x06,
-                .xtal_freq_count = 0xBB},
-        {
-                .osc_frequency = 12000000,
-                .enable_delay_count = 0x02,
-                .stable_count = 0x2F,
-                .active_delay_count = 0x04,
-                .xtal_freq_count = 0x76
-        },
-        {
-                .osc_frequency = 26000000,
-                .enable_delay_count = 0x04,
-                .stable_count = 0x66,
-                .active_delay_count = 0x09,
-                .xtal_freq_count = 0xFE
-        },
-        {
-                .osc_frequency = 16800000,
-                .enable_delay_count = 0x03,
-                .stable_count = 0x41,
-                .active_delay_count = 0x0A,
-                .xtal_freq_count = 0xA4
-        },
-};
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
-#define MISC_GP_HIDREV                  0x804
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
- */
-static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
-#define clk_writel(value, reg) \
-        __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
-        __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-#define chipid_readl() \
-        __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
-#define clk_writel_delay(value, reg)                                    \
-        do {                                                            \
-                __raw_writel((value), reg_clk_base + (reg));    \
-                udelay(2);                                              \
-        } while (0)
-static inline int clk_set_div(struct clk_tegra *c, u32 n)
-{
-        struct clk *clk = c->hw.clk;
-        return clk_set_rate(clk,
-                        (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
-}
-static inline u32 periph_clk_to_reg(
-        struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
-{
-        u32 reg = c->u.periph.clk_num / 32;
-        BUG_ON(reg >= RST_DEVICES_NUM);
-        if (reg < 3)
-                reg = reg_L + (reg * offs);
-        else
-                reg = reg_V + ((reg - 3) * offs);
-        return reg;
-}
-static unsigned long clk_measure_input_freq(void)
-{
-        u32 clock_autodetect;
-        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
-        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
-        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
-        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
-                return 12000000;
-        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
-                return 13000000;
-        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
-                return 19200000;
-        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
-                return 26000000;
-        } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
-                return 16800000;
-        } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
-                return 38400000;
-        } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
-                return 48000000;
-        } else {
-                pr_err("%s: Unexpected clock autodetect value %d", __func__,
-                        clock_autodetect);
-                BUG();
-                return 0;
-        }
-}
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
-                                 u32 flags, u32 round_mode)
-{
-        s64 divider_u71 = parent_rate;
-        if (!rate)
-                return -EINVAL;
-        if (!(flags & DIV_U71_INT))
-                divider_u71 *= 2;
-        if (round_mode == ROUND_DIVIDER_UP)
-                divider_u71 += rate - 1;
-        do_div(divider_u71, rate);
-        if (flags & DIV_U71_INT)
-                divider_u71 *= 2;
-        if (divider_u71 - 2 < 0)
-                return 0;
-        if (divider_u71 - 2 > 255)
-                return -EINVAL;
-        return divider_u71 - 2;
-}
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u16;
-        divider_u16 = parent_rate;
-        if (!rate)
-                return -EINVAL;
-        divider_u16 += rate - 1;
-        do_div(divider_u16, rate);
-        if (divider_u16 - 1 < 0)
-                return 0;
-        if (divider_u16 - 1 > 0xFFFF)
-                return -EINVAL;
-        return divider_u16 - 1;
-}
-static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        return to_clk_tegra(hw)->fixed_rate;
-}
-struct clk_ops tegra30_clk_32k_ops = {
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-/* clk_m functions */
-static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        if (!to_clk_tegra(hw)->fixed_rate)
-                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
-        return to_clk_tegra(hw)->fixed_rate;
-}
-static void tegra30_clk_m_init(struct clk_hw *hw)
-{
-        u32 osc_ctrl = clk_readl(OSC_CTRL);
-        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
-        u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
-        switch (to_clk_tegra(hw)->fixed_rate) {
-        case 12000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
-                break;
-        case 13000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
-                break;
-        case 19200000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
-                break;
-        case 26000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
-                break;
-        case 16800000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
-                break;
-        case 38400000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
-                break;
-        case 48000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
-                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
-                break;
-        default:
-                pr_err("%s: Unexpected clock rate %ld", __func__,
-                                to_clk_tegra(hw)->fixed_rate);
-                BUG();
-        }
-        clk_writel(auto_clock_control, OSC_CTRL);
-}
-struct clk_ops tegra30_clk_m_ops = {
-        .init = tegra30_clk_m_init,
-        .recalc_rate = tegra30_clk_m_recalc_rate,
-};
-static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra_clk_m_div_ops = {
-        .recalc_rate = tegra30_clk_m_div_recalc_rate,
-};
-/* PLL reference divider functions */
-static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
-                        unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long rate = parent_rate;
-        u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
-        switch (pll_ref_div) {
-        case OSC_CTRL_PLL_REF_DIV_1:
-                c->div = 1;
-                break;
-        case OSC_CTRL_PLL_REF_DIV_2:
-                c->div = 2;
-                break;
-        case OSC_CTRL_PLL_REF_DIV_4:
-                c->div = 4;
-                break;
-        default:
-                pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
-                BUG();
-        }
-        c->mul = 1;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra_pll_ref_ops = {
-        .recalc_rate = tegra30_pll_ref_recalc_rate,
-};
-/* super clock functions */
-/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
- * clock skipping super divider.  We will ignore the clock skipping divider,
- * since we can't lower the voltage when using the clock skip, but we can if
- * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
- * only when its parent is a fixed rate PLL, since we can't change PLL rate
- * in this case.
- */
-static void tegra30_super_clk_init(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        struct clk_tegra *p =
-                        to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
-        c->state = ON;
-        if (c->flags & DIV_U71) {
-                /* Init safe 7.1 divider value (does not affect PLLX path) */
-                clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
-                           c->reg + SUPER_CLK_DIVIDER);
-                c->mul = 2;
-                c->div = 2;
-                if (!(p->flags & PLLX))
-                        c->div += SUPER_CLOCK_DIV_U71_MIN;
-        } else
-                clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
-}
-static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        int source;
-        int shift;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        if (c->flags & DIV_2)
-                source |= val & SUPER_LP_DIV2_BYPASS;
-        return source;
-}
-static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        struct clk_tegra *p =
-                        to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
-        u32 val;
-        int shift;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        /* For LP mode super-clock switch between PLLX direct
-           and divided-by-2 outputs is allowed only when other
-           than PLLX clock source is current parent */
-        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
-            ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
-                if (p->flags & PLLX)
-                        return -EINVAL;
-                val ^= SUPER_LP_DIV2_BYPASS;
-                clk_writel_delay(val, c->reg);
-        }
-        val &= ~(SUPER_SOURCE_MASK << shift);
-        val |= (index & SUPER_SOURCE_MASK) << shift;
-        /* 7.1 divider for CPU super-clock does not affect
-           PLLX path */
-        if (c->flags & DIV_U71) {
-                u32 div = 0;
-                if (!(p->flags & PLLX)) {
-                        div = clk_readl(c->reg +
-                                        SUPER_CLK_DIVIDER);
-                        div &= SUPER_CLOCK_DIV_U71_MASK;
-                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
-                }
-                c->div = div + 2;
-                c->mul = 2;
-        }
-        clk_writel_delay(val, c->reg);
-        return 0;
-}
-/*
- * Do not use super clocks "skippers", since dividing using a clock skipper
- * does not allow the voltage to be scaled down. Instead adjust the rate of
- * the parent clock. This requires that the parent of a super clock have no
- * other children, otherwise the rate will change underneath the other
- * children. Special case: if fixed rate PLL is CPU super clock parent the
- * rate of this PLL can't be changed, and it has many other children. In
- * this case use 7.1 fractional divider to adjust the super clock rate.
- */
-static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        struct clk *parent = __clk_get_parent(hw->clk);
-        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
-        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
-                int div = clk_div71_get_divider(parent_rate,
-                                        rate, c->flags, ROUND_DIVIDER_DOWN);
-                div = max(div, SUPER_CLOCK_DIV_U71_MIN);
-                clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
-                           c->reg + SUPER_CLK_DIVIDER);
-                c->div = div + 2;
-                c->mul = 2;
-                return 0;
-        }
-        return 0;
-}
-static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        struct clk *parent = __clk_get_parent(hw->clk);
-        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
-        int mul = 2;
-        int div;
-        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
-                div = clk_div71_get_divider(*prate,
-                                rate, c->flags, ROUND_DIVIDER_DOWN);
-                div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
-                rate = *prate * mul;
-                rate += div - 1; /* round up */
-                do_div(rate, c->div);
-                return rate;
-        }
-        return *prate;
-}
-struct clk_ops tegra30_super_ops = {
-        .init = tegra30_super_clk_init,
-        .set_parent = tegra30_super_clk_set_parent,
-        .get_parent = tegra30_super_clk_get_parent,
-        .recalc_rate = tegra30_super_clk_recalc_rate,
-        .round_rate = tegra30_super_clk_round_rate,
-        .set_rate = tegra30_super_clk_set_rate,
-};
-static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra30_twd_ops = {
-        .recalc_rate = tegra30_twd_clk_recalc_rate,
-};
-/* bus clock functions */
-static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-        return c->state;
-}
-static int tegra30_bus_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg);
-        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
-        clk_writel(val, c->reg);
-        return 0;
-}
-static void tegra30_bus_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg);
-        val |= BUS_CLK_DISABLE << c->reg_shift;
-        clk_writel(val, c->reg);
-}
-static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        u64 rate = prate;
-        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-        c->mul = 1;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        int ret = -EINVAL;
-        u32 val;
-        int i;
-        val = clk_readl(c->reg);
-        for (i = 1; i <= 4; i++) {
-                if (rate == parent_rate / i) {
-                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
-                        val |= (i - 1) << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = i;
-                        c->mul = 1;
-                        ret = 0;
-                        break;
-                }
-        }
-        return ret;
-}
-static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        unsigned long parent_rate = *prate;
-        s64 divider;
-        if (rate >= parent_rate)
-                return parent_rate;
-        divider = parent_rate;
-        divider += rate - 1;
-        do_div(divider, rate);
-        if (divider < 0)
-                return divider;
-        if (divider > 4)
-                divider = 4;
-        do_div(parent_rate, divider);
-        return parent_rate;
-}
-struct clk_ops tegra30_bus_ops = {
-        .is_enabled = tegra30_bus_clk_is_enabled,
-        .enable = tegra30_bus_clk_enable,
-        .disable = tegra30_bus_clk_disable,
-        .set_rate = tegra30_bus_clk_set_rate,
-        .round_rate = tegra30_bus_clk_round_rate,
-        .recalc_rate = tegra30_bus_clk_recalc_rate,
-};
-/* Blink output functions */
-static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        return c->state;
-}
-static int tegra30_blink_clk_enable(struct clk_hw *hw)
-{
-        u32 val;
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        return 0;
-}
-static void tegra30_blink_clk_disable(struct clk_hw *hw)
-{
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (rate >= parent_rate) {
-                c->div = 1;
-                pmc_writel(0, c->reg);
-        } else {
-                unsigned int on_off;
-                u32 val;
-                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
-                c->div = on_off * 8;
-                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
-                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
-                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val |= on_off;
-                val |= PMC_BLINK_TIMER_ENB;
-                pmc_writel(val, c->reg);
-        }
-        return 0;
-}
-static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        u32 val;
-        u32 mul;
-        u32 div;
-        u32 on_off;
-        mul = 1;
-        val = pmc_readl(c->reg);
-        if (val & PMC_BLINK_TIMER_ENB) {
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                div = on_off * 4;
-        } else {
-                div = 1;
-        }
-        if (mul != 0 && div != 0) {
-                rate *= mul;
-                rate += div - 1; /* round up */
-                do_div(rate, div);
-        }
-        return rate;
-}
-static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        int div;
-        int mul;
-        long round_rate = *prate;
-        mul = 1;
-        if (rate >= *prate) {
-                div = 1;
-        } else {
-                div = DIV_ROUND_UP(*prate / 8, rate);
-                div *= 8;
-        }
-        round_rate *= mul;
-        round_rate += div - 1;
-        do_div(round_rate, div);
-        return round_rate;
-}
-struct clk_ops tegra30_blink_clk_ops = {
-        .is_enabled = tegra30_blink_clk_is_enabled,
-        .enable = tegra30_blink_clk_enable,
-        .disable = tegra30_blink_clk_disable,
-        .recalc_rate = tegra30_blink_clk_recalc_rate,
-        .round_rate = tegra30_blink_clk_round_rate,
-        .set_rate = tegra30_blink_clk_set_rate,
-};
-static void tegra30_utmi_param_configure(struct clk_hw *hw)
-{
-        unsigned long main_rate =
-                __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
-        u32 reg;
-        int i;
-        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
-                if (main_rate == utmi_parameters[i].osc_frequency)
-                        break;
-        }
-        if (i >= ARRAY_SIZE(utmi_parameters)) {
-                pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
-                return;
-        }
-        reg = clk_readl(UTMIP_PLL_CFG2);
-        /* Program UTMIP PLL stable and active counts */
-        /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
-        reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
-        reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
-                        utmi_parameters[i].stable_count);
-        reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
-        reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
-                        utmi_parameters[i].active_delay_count);
-        /* Remove power downs from UTMIP PLL control bits */
-        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
-        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
-        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
-        clk_writel(reg, UTMIP_PLL_CFG2);
-        /* Program UTMIP PLL delay and oscillator frequency counts */
-        reg = clk_readl(UTMIP_PLL_CFG1);
-        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
-        reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
-                utmi_parameters[i].enable_delay_count);
-        reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
-        reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
-                utmi_parameters[i].xtal_freq_count);
-        /* Remove power downs from UTMIP PLL control bits */
-        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
-        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
-        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
-        clk_writel(reg, UTMIP_PLL_CFG1);
-}
-/* PLL Functions */
-static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
-                                         u32 lock_bit)
-{
-        int ret = 0;
-#if USE_PLL_LOCK_BITS
-        int i;
-        for (i = 0; i < c->u.pll.lock_delay; i++) {
-                if (clk_readl(lock_reg) & lock_bit) {
-                        udelay(PLL_POST_LOCK_DELAY);
-                        return 0;
-                }
-                udelay(2);      /* timeout = 2 * lock time */
-        }
-        pr_err("Timed out waiting for lock bit on pll %s",
-                                        __clk_get_name(hw->clk));
-        ret = -1;
-#else
-        udelay(c->u.pll.lock_delay);
-#endif
-        return ret;
-}
-static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg + PLL_BASE);
-        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-        return c->state;
-}
-static void tegra30_pll_clk_init(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (c->flags & PLLU)
-                tegra30_utmi_param_configure(hw);
-}
-static int tegra30_pll_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-#if USE_PLL_LOCK_BITS
-        val = clk_readl(c->reg + PLL_MISC(c));
-        val |= PLL_MISC_LOCK_ENABLE(c);
-        clk_writel(val, c->reg + PLL_MISC(c));
-#endif
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLL_BASE_BYPASS;
-        val |= PLL_BASE_ENABLE;
-        clk_writel(val, c->reg + PLL_BASE);
-        if (c->flags & PLLM) {
-                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
-                val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
-                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
-        }
-        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
-        return 0;
-}
-static void tegra30_pll_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
-        val = clk_readl(c->reg);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        clk_writel(val, c->reg);
-        if (c->flags & PLLM) {
-                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
-                val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
-                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
-        }
-}
-static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val, p_div, old_base;
-        unsigned long input_rate;
-        const struct clk_pll_freq_table *sel;
-        struct clk_pll_freq_table cfg;
-        if (c->flags & PLL_FIXED) {
-                int ret = 0;
-                if (rate != c->u.pll.fixed_rate) {
-                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-                               __func__, __clk_get_name(hw->clk),
-                                c->u.pll.fixed_rate, rate);
-                        ret = -EINVAL;
-                }
-                return ret;
-        }
-        if (c->flags & PLLM) {
-                if (rate != __clk_get_rate(hw->clk)) {
-                        pr_err("%s: Can not change memory %s rate in flight\n",
-                                __func__, __clk_get_name(hw->clk));
-                        return -EINVAL;
-                }
-        }
-        p_div = 0;
-        input_rate = parent_rate;
-        /* Check if the target rate is tabulated */
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        if (c->flags & PLLU) {
-                                BUG_ON(sel->p < 1 || sel->p > 2);
-                                if (sel->p == 1)
-                                        p_div = PLLU_BASE_POST_DIV;
-                        } else {
-                                BUG_ON(sel->p < 1);
-                                for (val = sel->p; val > 1; val >>= 1)
-                                        p_div++;
-                                p_div <<= PLL_BASE_DIVP_SHIFT;
-                        }
-                        break;
-                }
-        }
-        /* Configure out-of-table rate */
-        if (sel->input_rate == 0) {
-                unsigned long cfreq;
-                BUG_ON(c->flags & PLLU);
-                sel = &cfg;
-                switch (input_rate) {
-                case 12000000:
-                case 26000000:
-                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
-                        break;
-                case 13000000:
-                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
-                        break;
-                case 16800000:
-                case 19200000:
-                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
-                        break;
-                default:
-                        pr_err("%s: Unexpected reference rate %lu\n",
-                               __func__, input_rate);
-                        BUG();
-                }
-                /* Raise VCO to guarantee 0.5% accuracy */
-                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
-                      cfg.output_rate <<= 1)
-                        p_div++;
-                cfg.p = 0x1 << p_div;
-                cfg.m = input_rate / cfreq;
-                cfg.n = cfg.output_rate / cfreq;
-                cfg.cpcon = OUT_OF_TABLE_CPCON;
-                if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
-                    (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
-                    (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
-                    (cfg.output_rate > c->u.pll.vco_max)) {
-                        pr_err("%s: Failed to set %s out-of-table rate %lu\n",
-                               __func__, __clk_get_name(hw->clk), rate);
-                        return -EINVAL;
-                }
-                p_div <<= PLL_BASE_DIVP_SHIFT;
-        }
-        c->mul = sel->n;
-        c->div = sel->m * sel->p;
-        old_base = val = clk_readl(c->reg + PLL_BASE);
-        val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
-                 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
-        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
-                (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
-        if (val == old_base)
-                return 0;
-        if (c->state == ON) {
-                tegra30_pll_clk_disable(hw);
-                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        }
-        clk_writel(val, c->reg + PLL_BASE);
-        if (c->flags & PLL_HAS_CPCON) {
-                val = clk_readl(c->reg + PLL_MISC(c));
-                val &= ~PLL_MISC_CPCON_MASK;
-                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
-                if (c->flags & (PLLU | PLLD)) {
-                        val &= ~PLL_MISC_LFCON_MASK;
-                        if (sel->n >= PLLDU_LFCON_SET_DIVN)
-                                val |= 0x1 << PLL_MISC_LFCON_SHIFT;
-                } else if (c->flags & (PLLX | PLLM)) {
-                        val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
-                        if (rate >= (c->u.pll.vco_max >> 1))
-                                val |= 0x1 << PLL_MISC_DCCON_SHIFT;
-                }
-                clk_writel(val, c->reg + PLL_MISC(c));
-        }
-        if (c->state == ON)
-                tegra30_pll_clk_enable(hw);
-        c->u.pll.fixed_rate = rate;
-        return 0;
-}
-static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long input_rate = *prate;
-        u64 output_rate = *prate;
-        const struct clk_pll_freq_table *sel;
-        struct clk_pll_freq_table cfg;
-        int mul;
-        int div;
-        u32 p_div;
-        u32 val;
-        if (c->flags & PLL_FIXED)
-                return c->u.pll.fixed_rate;
-        if (c->flags & PLLM)
-                return __clk_get_rate(hw->clk);
-        p_div = 0;
-        /* Check if the target rate is tabulated */
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        if (c->flags & PLLU) {
-                                BUG_ON(sel->p < 1 || sel->p > 2);
-                                if (sel->p == 1)
-                                        p_div = PLLU_BASE_POST_DIV;
-                        } else {
-                                BUG_ON(sel->p < 1);
-                                for (val = sel->p; val > 1; val >>= 1)
-                                        p_div++;
-                                p_div <<= PLL_BASE_DIVP_SHIFT;
-                        }
-                        break;
-                }
-        }
-        if (sel->input_rate == 0) {
-                unsigned long cfreq;
-                BUG_ON(c->flags & PLLU);
-                sel = &cfg;
-                switch (input_rate) {
-                case 12000000:
-                case 26000000:
-                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
-                        break;
-                case 13000000:
-                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
-                        break;
-                case 16800000:
-                case 19200000:
-                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
-                        break;
-                default:
-                        pr_err("%s: Unexpected reference rate %lu\n",
-                               __func__, input_rate);
-                        BUG();
-                }
-                /* Raise VCO to guarantee 0.5% accuracy */
-                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
-                      cfg.output_rate <<= 1)
-                        p_div++;
-                cfg.p = 0x1 << p_div;
-                cfg.m = input_rate / cfreq;
-                cfg.n = cfg.output_rate / cfreq;
-        }
-        mul = sel->n;
-        div = sel->m * sel->p;
-        output_rate *= mul;
-        output_rate += div - 1; /* round up */
-        do_div(output_rate, div);
-        return output_rate;
-}
-static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        u32 val = clk_readl(c->reg + PLL_BASE);
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                const struct clk_pll_freq_table *sel;
-                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                        if (sel->input_rate == parent_rate &&
-                                sel->output_rate == c->u.pll.fixed_rate) {
-                                c->mul = sel->n;
-                                c->div = sel->m * sel->p;
-                                break;
-                        }
-                }
-                pr_err("Clock %s has unknown fixed frequency\n",
-                                                __clk_get_name(hw->clk));
-                BUG();
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
-                                        PLL_BASE_DIVP_SHIFT));
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra30_pll_ops = {
-        .is_enabled = tegra30_pll_clk_is_enabled,
-        .init = tegra30_pll_clk_init,
-        .enable = tegra30_pll_clk_enable,
-        .disable = tegra30_pll_clk_disable,
-        .recalc_rate = tegra30_pll_recalc_rate,
-        .round_rate = tegra30_pll_round_rate,
-        .set_rate = tegra30_pll_clk_set_rate,
-};
-int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val, mask, reg;
-        switch (p) {
-        case TEGRA_CLK_PLLD_CSI_OUT_ENB:
-                mask = PLLD_BASE_CSI_CLKENABLE;
-                reg = c->reg + PLL_BASE;
-                break;
-        case TEGRA_CLK_PLLD_DSI_OUT_ENB:
-                mask = PLLD_MISC_DSI_CLKENABLE;
-                reg = c->reg + PLL_MISC(c);
-                break;
-        case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
-                if (!(c->flags & PLL_ALT_MISC_REG)) {
-                        mask = PLLD_BASE_DSIB_MUX_MASK;
-                        reg = c->reg + PLL_BASE;
-                        break;
-                }
-        /* fall through - error since PLLD2 does not have MUX_SEL control */
-        default:
-                return -EINVAL;
-        }
-        val = clk_readl(reg);
-        if (setting)
-                val |= mask;
-        else
-                val &= ~mask;
-        clk_writel(val, reg);
-        return 0;
-}
-static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg + PLL_BASE);
-        c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
-        return c->state;
-}
-static void tegra30_plle_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
-        clk_writel(val, c->reg + PLL_BASE);
-}
-static void tegra30_plle_training(struct clk_tegra *c)
-{
-        u32 val;
-        /* PLLE is already disabled, and setup cleared;
-         * create falling edge on PLLE IDDQ input */
-        val = pmc_readl(PMC_SATA_PWRGT);
-        val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
-        pmc_writel(val, PMC_SATA_PWRGT);
-        val = pmc_readl(PMC_SATA_PWRGT);
-        val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
-        pmc_writel(val, PMC_SATA_PWRGT);
-        val = pmc_readl(PMC_SATA_PWRGT);
-        val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
-        pmc_writel(val, PMC_SATA_PWRGT);
-        do {
-                val = clk_readl(c->reg + PLL_MISC(c));
-        } while (!(val & PLLE_MISC_READY));
-}
-static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        struct clk *parent = __clk_get_parent(hw->clk);
-        const struct clk_pll_freq_table *sel;
-        u32 val;
-        unsigned long rate = c->u.pll.fixed_rate;
-        unsigned long input_rate = __clk_get_rate(parent);
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate)
-                        break;
-        }
-        if (sel->input_rate == 0)
-                return -ENOSYS;
-        /* disable PLLE, clear setup fiels */
-        tegra30_plle_clk_disable(hw);
-        val = clk_readl(c->reg + PLL_MISC(c));
-        val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
-        clk_writel(val, c->reg + PLL_MISC(c));
-        /* training */
-        val = clk_readl(c->reg + PLL_MISC(c));
-        if (force_training || (!(val & PLLE_MISC_READY)))
-                tegra30_plle_training(c);
-        /* configure dividers, setup, disable SS */
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLLE_BASE_DIV_MASK;
-        val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
-        clk_writel(val, c->reg + PLL_BASE);
-        c->mul = sel->n;
-        c->div = sel->m * sel->p;
-        val = clk_readl(c->reg + PLL_MISC(c));
-        val |= PLLE_MISC_SETUP_VALUE;
-        val |= PLLE_MISC_LOCK_ENABLE;
-        clk_writel(val, c->reg + PLL_MISC(c));
-        val = clk_readl(PLLE_SS_CTRL);
-        val |= PLLE_SS_DISABLE;
-        clk_writel(val, PLLE_SS_CTRL);
-        /* enable and lock PLLE*/
-        val = clk_readl(c->reg + PLL_BASE);
-        val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
-        clk_writel(val, c->reg + PLL_BASE);
-        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
-        return 0;
-}
-static int tegra30_plle_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        return tegra30_plle_configure(hw, !c->set);
-}
-static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
-                        unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long rate = parent_rate;
-        u32 val;
-        val = clk_readl(c->reg + PLL_BASE);
-        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
-        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
-        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra30_plle_ops = {
-        .is_enabled = tegra30_plle_clk_is_enabled,
-        .enable = tegra30_plle_clk_enable,
-        .disable = tegra30_plle_clk_disable,
-        .recalc_rate = tegra30_plle_clk_recalc_rate,
-};
-/* Clock divider ops */
-static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (c->flags & DIV_U71) {
-                u32 val = clk_readl(c->reg);
-                val >>= c->reg_shift;
-                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
-                if (!(val & PLL_OUT_RESET_DISABLE))
-                        c->state = OFF;
-        } else {
-                c->state = ON;
-        }
-        return c->state;
-}
-static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        u32 new_val;
-        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
-        if (c->flags & DIV_U71) {
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel_delay(val, c->reg);
-                return 0;
-        } else if (c->flags & DIV_2) {
-                return 0;
-        }
-        return -EINVAL;
-}
-static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        u32 new_val;
-        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
-        if (c->flags & DIV_U71) {
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel_delay(val, c->reg);
-        }
-}
-static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        u32 new_val;
-        int divider_u71;
-        if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(
-                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
-                if (divider_u71 >= 0) {
-                        val = clk_readl(c->reg);
-                        new_val = val >> c->reg_shift;
-                        new_val &= 0xFFFF;
-                        if (c->flags & DIV_U71_FIXED)
-                                new_val |= PLL_OUT_OVERRIDE;
-                        new_val &= ~PLL_OUT_RATIO_MASK;
-                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-                        val &= ~(0xFFFF << c->reg_shift);
-                        val |= new_val << c->reg_shift;
-                        clk_writel_delay(val, c->reg);
-                        c->div = divider_u71 + 2;
-                        c->mul = 2;
-                        c->fixed_rate = rate;
-                        return 0;
-                }
-        } else if (c->flags & DIV_2) {
-                c->fixed_rate = rate;
-                return 0;
-        }
-        return -EINVAL;
-}
-static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        if (c->flags & DIV_U71) {
-                u32 divu71;
-                u32 val = clk_readl(c->reg);
-                val >>= c->reg_shift;
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                if (c->flags & (PLLD | PLLX)) {
-                        c->div = 2;
-                        c->mul = 1;
-                } else
-                        BUG();
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
-                                unsigned long rate, unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
-        int divider;
-        if (prate)
-                parent_rate = *prate;
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(
-                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2) {
-                *prate = rate * 2;
-                return rate;
-        }
-        return -EINVAL;
-}
-struct clk_ops tegra30_pll_div_ops = {
-        .is_enabled = tegra30_pll_div_clk_is_enabled,
-        .enable = tegra30_pll_div_clk_enable,
-        .disable = tegra30_pll_div_clk_disable,
-        .set_rate = tegra30_pll_div_clk_set_rate,
-        .recalc_rate = tegra30_pll_div_clk_recalc_rate,
-        .round_rate = tegra30_pll_div_clk_round_rate,
-};
-/* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk_tegra *c)
-{
-        if (c->flags & MUX8)
-                return 7 << 29;
-        else if (c->flags & MUX_PWM)
-                return 3 << 28;
-        else if (c->flags & MUX_CLK_OUT)
-                return 3 << (c->u.periph.clk_num + 4);
-        else if (c->flags & PLLD)
-                return PLLD_BASE_DSIB_MUX_MASK;
-        else
-                return 3 << 30;
-}
-static inline u32 periph_clk_source_shift(struct clk_tegra *c)
-{
-        if (c->flags & MUX8)
-                return 29;
-        else if (c->flags & MUX_PWM)
-                return 28;
-        else if (c->flags & MUX_CLK_OUT)
-                return c->u.periph.clk_num + 4;
-        else if (c->flags & PLLD)
-                return PLLD_BASE_DSIB_MUX_SHIFT;
-        else
-                return 30;
-}
-static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        c->state = ON;
-        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
-                c->state = OFF;
-        if (!(c->flags & PERIPH_NO_RESET))
-                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
-                        c->state = OFF;
-        return c->state;
-}
-static int tegra30_periph_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
-                return 0;
-        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (!(c->flags & PERIPH_NO_RESET) &&
-                 !(c->flags & PERIPH_MANUAL_RESET)) {
-                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
-                         PERIPH_CLK_TO_BIT(c)) {
-                        udelay(5);      /* reset propagation delay */
-                        clk_writel(PERIPH_CLK_TO_BIT(c),
-                                 PERIPH_CLK_TO_RST_CLR_REG(c));
-                }
-        }
-        return 0;
-}
-static void tegra30_periph_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long val;
-        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
-                return;
-        /* If peripheral is in the APB bus then read the APB bus to
-         * flush the write operation in apb bus. This will avoid the
-         * peripheral access after disabling clock*/
-        if (c->flags & PERIPH_ON_APB)
-                val = chipid_readl();
-        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-}
-void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long val;
-        if (!(c->flags & PERIPH_NO_RESET)) {
-                if (assert) {
-                        /* If peripheral is in the APB bus then read the APB
-                         * bus to flush the write operation in apb bus. This
-                         * will avoid the peripheral access after disabling
-                         * clock */
-                        if (c->flags & PERIPH_ON_APB)
-                                val = chipid_readl();
-                        clk_writel(PERIPH_CLK_TO_BIT(c),
-                                   PERIPH_CLK_TO_RST_SET_REG(c));
-                } else
-                        clk_writel(PERIPH_CLK_TO_BIT(c),
-                                   PERIPH_CLK_TO_RST_CLR_REG(c));
-        }
-}
-static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        if (!(c->flags & MUX))
-                return (index == 0) ? 0 : (-EINVAL);
-        val = clk_readl(c->reg);
-        val &= ~periph_clk_source_mask(c);
-        val |= (index << periph_clk_source_shift(c));
-        clk_writel_delay(val, c->reg);
-        return 0;
-}
-static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        int source  = (val & periph_clk_source_mask(c)) >>
-                                        periph_clk_source_shift(c);
-        if (!(c->flags & MUX))
-                return 0;
-        return source;
-}
-static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        int divider;
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(
-                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
-                        val |= divider;
-                        if (c->flags & DIV_U71_UART) {
-                                if (divider)
-                                        val |= PERIPH_CLK_UART_DIV_ENB;
-                                else
-                                        val &= ~PERIPH_CLK_UART_DIV_ENB;
-                        }
-                        clk_writel_delay(val, c->reg);
-                        c->div = divider + 2;
-                        c->mul = 2;
-                        return 0;
-                }
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
-                        val |= divider;
-                        clk_writel_delay(val, c->reg);
-                        c->div = divider + 1;
-                        c->mul = 1;
-                        return 0;
-                }
-        } else if (parent_rate <= rate) {
-                c->div = 1;
-                c->mul = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
-        int divider;
-        if (prate)
-                parent_rate = *prate;
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(
-                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate, divider + 1);
-        }
-        return -EINVAL;
-}
-static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        u32 val = clk_readl(c->reg);
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                if ((c->flags & DIV_U71_UART) &&
-                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
-                        divu71 = 0;
-                }
-                if (c->flags & DIV_U71_IDLE) {
-                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        clk_writel(val, c->reg);
-                }
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-struct clk_ops tegra30_periph_clk_ops = {
-        .is_enabled = tegra30_periph_clk_is_enabled,
-        .enable = tegra30_periph_clk_enable,
-        .disable = tegra30_periph_clk_disable,
-        .set_parent = tegra30_periph_clk_set_parent,
-        .get_parent = tegra30_periph_clk_get_parent,
-        .set_rate = tegra30_periph_clk_set_rate,
-        .round_rate = tegra30_periph_clk_round_rate,
-        .recalc_rate = tegra30_periph_clk_recalc_rate,
-};
-static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk *d = clk_get_sys(NULL, "pll_d");
-        /* The DSIB parent selection bit is in PLLD base register */
-        tegra_clk_cfg_ex(
-                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
-        return 0;
-}
-struct clk_ops tegra30_dsib_clk_ops = {
-        .is_enabled = tegra30_periph_clk_is_enabled,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_dsib_clk_set_parent,
-        .get_parent             = &tegra30_periph_clk_get_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .recalc_rate            = &tegra30_periph_clk_recalc_rate,
-};
-/* Periph extended clock configuration ops */
-int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (p == TEGRA_CLK_VI_INP_SEL) {
-                u32 val = clk_readl(c->reg);
-                val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
-                val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
-                        PERIPH_CLK_VI_SEL_EX_MASK;
-                clk_writel(val, c->reg);
-                return 0;
-        }
-        return -EINVAL;
-}
-int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
-                u32 val = clk_readl(c->reg);
-                if (setting)
-                        val |= PERIPH_CLK_NAND_DIV_EX_ENB;
-                else
-                        val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
-                clk_writel(val, c->reg);
-                return 0;
-        }
-        return -EINVAL;
-}
-int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        if (p == TEGRA_CLK_DTV_INVERT) {
-                u32 val = clk_readl(c->reg);
-                if (setting)
-                        val |= PERIPH_CLK_DTV_POLARITY_INV;
-                else
-                        val &= ~PERIPH_CLK_DTV_POLARITY_INV;
-                clk_writel(val, c->reg);
-                return 0;
-        }
-        return -EINVAL;
-}
-/* Output clock ops */
-static DEFINE_SPINLOCK(clk_out_lock);
-static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = pmc_readl(c->reg);
-        c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
-        c->mul = 1;
-        c->div = 1;
-        return c->state;
-}
-static int tegra30_clk_out_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        unsigned long flags;
-        spin_lock_irqsave(&clk_out_lock, flags);
-        val = pmc_readl(c->reg);
-        val |= (0x1 << c->u.periph.clk_num);
-        pmc_writel(val, c->reg);
-        spin_unlock_irqrestore(&clk_out_lock, flags);
-        return 0;
-}
-static void tegra30_clk_out_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        unsigned long flags;
-        spin_lock_irqsave(&clk_out_lock, flags);
-        val = pmc_readl(c->reg);
-        val &= ~(0x1 << c->u.periph.clk_num);
-        pmc_writel(val, c->reg);
-        spin_unlock_irqrestore(&clk_out_lock, flags);
-}
-static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        unsigned long flags;
-        spin_lock_irqsave(&clk_out_lock, flags);
-        val = pmc_readl(c->reg);
-        val &= ~periph_clk_source_mask(c);
-        val |= (index << periph_clk_source_shift(c));
-        pmc_writel(val, c->reg);
-        spin_unlock_irqrestore(&clk_out_lock, flags);
-        return 0;
-}
-static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = pmc_readl(c->reg);
-        int source;
-        source = (val & periph_clk_source_mask(c)) >>
-                                periph_clk_source_shift(c);
-        return source;
-}
-struct clk_ops tegra_clk_out_ops = {
-        .is_enabled = tegra30_clk_out_is_enabled,
-        .enable = tegra30_clk_out_enable,
-        .disable = tegra30_clk_out_disable,
-        .set_parent = tegra30_clk_out_set_parent,
-        .get_parent = tegra30_clk_out_get_parent,
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-/* Clock doubler ops */
-static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        c->state = ON;
-        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
-                c->state = OFF;
-        return c->state;
-};
-static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        if (rate == parent_rate) {
-                val = clk_readl(c->reg) | (0x1 << c->reg_shift);
-                clk_writel(val, c->reg);
-                c->mul = 1;
-                c->div = 1;
-                return 0;
-        } else if (rate == 2 * parent_rate) {
-                val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
-                clk_writel(val, c->reg);
-                c->mul = 2;
-                c->div = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u64 rate = parent_rate;
-        u32 val = clk_readl(c->reg);
-        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
-        c->div = 1;
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
-{
-        unsigned long output_rate = *prate;
-        do_div(output_rate, 2);
-        return output_rate;
-}
-struct clk_ops tegra30_clk_double_ops = {
-        .is_enabled = tegra30_clk_double_is_enabled,
-        .enable = tegra30_periph_clk_enable,
-        .disable = tegra30_periph_clk_disable,
-        .recalc_rate = tegra30_clk_double_recalc_rate,
-        .round_rate = tegra30_clk_double_round_rate,
-        .set_rate = tegra30_clk_double_set_rate,
-};
-/* Audio sync clock ops */
-struct clk_ops tegra_sync_source_ops = {
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
-        return c->state;
-}
-static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
-        return 0;
-}
-static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
-}
-static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val;
-        val = clk_readl(c->reg);
-        val &= ~AUDIO_SYNC_SOURCE_MASK;
-        val |= index;
-        clk_writel(val, c->reg);
-        return 0;
-}
-static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        int source;
-        source = val & AUDIO_SYNC_SOURCE_MASK;
-        return source;
-}
-struct clk_ops tegra30_audio_sync_clk_ops = {
-        .is_enabled = tegra30_audio_sync_clk_is_enabled,
-        .enable = tegra30_audio_sync_clk_enable,
-        .disable = tegra30_audio_sync_clk_disable,
-        .set_parent = tegra30_audio_sync_clk_set_parent,
-        .get_parent = tegra30_audio_sync_clk_get_parent,
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-/* cml0 (pcie), and cml1 (sata) clock ops */
-static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
-        return c->state;
-}
-static int tegra30_cml_clk_enable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        val |= (0x1 << c->u.periph.clk_num);
-        clk_writel(val, c->reg);
-        return 0;
-}
-static void tegra30_cml_clk_disable(struct clk_hw *hw)
-{
-        struct clk_tegra *c = to_clk_tegra(hw);
-        u32 val = clk_readl(c->reg);
-        val &= ~(0x1 << c->u.periph.clk_num);
-        clk_writel(val, c->reg);
-}
-struct clk_ops tegra_cml_clk_ops = {
-        .is_enabled = tegra30_cml_clk_is_enabled,
-        .enable = tegra30_cml_clk_enable,
-        .disable = tegra30_cml_clk_disable,
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-struct clk_ops tegra_pciex_clk_ops = {
-        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-};
-/* Tegra30 CPU clock and reset control functions */
-static void tegra30_wait_cpu_in_reset(u32 cpu)
-{
-        unsigned int reg;
-        do {
-                reg = readl(reg_clk_base +
-                            TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
-                cpu_relax();
-        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
-        return;
-}
-static void tegra30_put_cpu_in_reset(u32 cpu)
-{
-        writel(CPU_RESET(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-        dmb();
-}
-static void tegra30_cpu_out_of_reset(u32 cpu)
-{
-        writel(CPU_RESET(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-        wmb();
-}
-static void tegra30_enable_cpu_clock(u32 cpu)
-{
-        unsigned int reg;
-        writel(CPU_CLOCK(cpu),
-               reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-        reg = readl(reg_clk_base +
-                    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-}
-static void tegra30_disable_cpu_clock(u32 cpu)
-{
-        unsigned int reg;
-        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg | CPU_CLOCK(cpu),
-               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-}
-#ifdef CONFIG_PM_SLEEP
-static bool tegra30_cpu_rail_off_ready(void)
-{
-        unsigned int cpu_rst_status;
-        int cpu_pwr_status;
-        cpu_rst_status = readl(reg_clk_base +
-                               TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
-        cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
-                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
-                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
-        if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
-                return false;
-        return true;
-}
-static void tegra30_cpu_clock_suspend(void)
-{
-        /* switch coresite to clk_m, save off original source */
-        tegra30_cpu_clk_sctx.clk_csite_src =
-                                readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
-        writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
-        tegra30_cpu_clk_sctx.cpu_burst =
-                                readl(reg_clk_base + CLK_RESET_CCLK_BURST);
-        tegra30_cpu_clk_sctx.pllx_base =
-                                readl(reg_clk_base + CLK_RESET_PLLX_BASE);
-        tegra30_cpu_clk_sctx.pllx_misc =
-                                readl(reg_clk_base + CLK_RESET_PLLX_MISC);
-        tegra30_cpu_clk_sctx.cclk_divider =
-                                readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
-}
-static void tegra30_cpu_clock_resume(void)
-{
-        unsigned int reg, policy;
-        /* Is CPU complex already running on PLLX? */
-        reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
-        policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
-        if (policy == CLK_RESET_CCLK_IDLE_POLICY)
-                reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
-        else if (policy == CLK_RESET_CCLK_RUN_POLICY)
-                reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
-        else
-                BUG();
-        if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
-                /* restore PLLX settings if CPU is on different PLL */
-                writel(tegra30_cpu_clk_sctx.pllx_misc,
-                                        reg_clk_base + CLK_RESET_PLLX_MISC);
-                writel(tegra30_cpu_clk_sctx.pllx_base,
-                                        reg_clk_base + CLK_RESET_PLLX_BASE);
-                /* wait for PLL stabilization if PLLX was enabled */
-                if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
-                        udelay(300);
-        }
-        /*
-         * Restore original burst policy setting for calls resulting from CPU
-         * LP2 in idle or system suspend.
-         */
-        writel(tegra30_cpu_clk_sctx.cclk_divider,
-                                        reg_clk_base + CLK_RESET_CCLK_DIVIDER);
-        writel(tegra30_cpu_clk_sctx.cpu_burst,
-                                        reg_clk_base + CLK_RESET_CCLK_BURST);
-        writel(tegra30_cpu_clk_sctx.clk_csite_src,
-                                        reg_clk_base + CLK_RESET_SOURCE_CSITE);
-}
-#endif
-static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
-        .wait_for_reset = tegra30_wait_cpu_in_reset,
-        .put_in_reset   = tegra30_put_cpu_in_reset,
-        .out_of_reset   = tegra30_cpu_out_of_reset,
-        .enable_clock   = tegra30_enable_cpu_clock,
-        .disable_clock  = tegra30_disable_cpu_clock,
-#ifdef CONFIG_PM_SLEEP
-        .rail_off_ready = tegra30_cpu_rail_off_ready,
-        .suspend        = tegra30_cpu_clock_suspend,
-        .resume         = tegra30_cpu_clock_resume,
-#endif
-};
-void __init tegra30_cpu_car_ops_init(void)
-{
-        tegra_cpu_car_ops = &tegra30_cpu_car_ops;
-}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
deleted file mode 100644
index 7a34adb2f72d..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __MACH_TEGRA30_CLOCK_H
-#define __MACH_TEGRA30_CLOCK_H
-extern struct clk_ops tegra30_clk_32k_ops;
-extern struct clk_ops tegra30_clk_m_ops;
-extern struct clk_ops tegra_clk_m_div_ops;
-extern struct clk_ops tegra_pll_ref_ops;
-extern struct clk_ops tegra30_pll_ops;
-extern struct clk_ops tegra30_pll_div_ops;
-extern struct clk_ops tegra_plld_ops;
-extern struct clk_ops tegra30_plle_ops;
-extern struct clk_ops tegra_cml_clk_ops;
-extern struct clk_ops tegra_pciex_clk_ops;
-extern struct clk_ops tegra_sync_source_ops;
-extern struct clk_ops tegra30_audio_sync_clk_ops;
-extern struct clk_ops tegra30_clk_double_ops;
-extern struct clk_ops tegra_clk_out_ops;
-extern struct clk_ops tegra30_super_ops;
-extern struct clk_ops tegra30_blink_clk_ops;
-extern struct clk_ops tegra30_twd_ops;
-extern struct clk_ops tegra30_bus_ops;
-extern struct clk_ops tegra30_periph_clk_ops;
-extern struct clk_ops tegra30_dsib_clk_ops;
-extern struct clk_ops tegra_nand_clk_ops;
-extern struct clk_ops tegra_vi_clk_ops;
-extern struct clk_ops tegra_dtv_clk_ops;
-extern struct clk_ops tegra_clk_shared_bus_ops;
-int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting);
-void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
-int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting);
-int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting);
-int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
-                                enum tegra_clk_ex_param p, u32 setting);
-#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
deleted file mode 100644
index 6942c7add3bb..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ /dev/null
@@ -1,1425 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra30_clocks.c
- *
- * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- */
-#include <linux/clk-private.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include "clock.h"
-#include "fuse.h"
-#include "tegra30_clocks.h"
-#include "tegra_cpu_car.h"
-#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
-                   _parent_names, _parents, _parent)            \
-        static struct clk tegra_##_name = {                     \
-                .hw = &tegra_##_name##_hw.hw,                   \
-                .name = #_name,                                 \
-                .rate = _rate,                                  \
-                .ops = _ops,                                    \
-                .flags = _flags,                                \
-                .parent_names = _parent_names,                  \
-                .parents = _parents,                            \
-                .num_parents = ARRAY_SIZE(_parent_names),       \
-                .parent = _parent,                              \
-        };
-static struct clk tegra_clk_32k;
-static struct clk_tegra tegra_clk_32k_hw = {
-        .hw = {
-                .clk = &tegra_clk_32k,
-        },
-        .fixed_rate = 32768,
-};
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .hw = &tegra_clk_32k_hw.hw,
-        .ops = &tegra30_clk_32k_ops,
-        .flags = CLK_IS_ROOT,
-};
-static struct clk tegra_clk_m;
-static struct clk_tegra tegra_clk_m_hw = {
-        .hw = {
-                .clk = &tegra_clk_m,
-        },
-        .flags = ENABLE_ON_INIT,
-        .reg = 0x1fc,
-        .reg_shift = 28,
-        .max_rate = 48000000,
-};
-static struct clk tegra_clk_m = {
-        .name = "clk_m",
-        .hw = &tegra_clk_m_hw.hw,
-        .ops = &tegra30_clk_m_ops,
-        .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
-};
-static const char *clk_m_div_parent_names[] = {
-        "clk_m",
-};
-static struct clk *clk_m_div_parents[] = {
-        &tegra_clk_m,
-};
-static struct clk tegra_clk_m_div2;
-static struct clk_tegra tegra_clk_m_div2_hw = {
-        .hw = {
-                .clk = &tegra_clk_m_div2,
-        },
-        .mul = 1,
-        .div = 2,
-        .max_rate = 24000000,
-};
-DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
-                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
-static struct clk tegra_clk_m_div4;
-static struct clk_tegra tegra_clk_m_div4_hw = {
-        .hw = {
-                .clk = &tegra_clk_m_div4,
-        },
-        .mul = 1,
-        .div = 4,
-        .max_rate = 12000000,
-};
-DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
-                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
-static struct clk tegra_pll_ref;
-static struct clk_tegra tegra_pll_ref_hw = {
-        .hw = {
-                .clk = &tegra_pll_ref,
-        },
-        .flags = ENABLE_ON_INIT,
-        .max_rate = 26000000,
-};
-DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
-                clk_m_div_parents, &tegra_clk_m);
-#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
-                   _input_max, _cf_min, _cf_max, _vco_min,      \
-                   _vco_max, _freq_table, _lock_delay, _ops,    \
-                   _fixed_rate, _clk_cfg_ex, _parent)           \
-        static struct clk tegra_##_name;                        \
-        static const char *_name##_parent_names[] = {           \
-                #_parent,                                       \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                &tegra_##_parent,                               \
-        };                                                      \
-        static struct clk_tegra tegra_##_name##_hw = {          \
-                .hw = {                                         \
-                        .clk = &tegra_##_name,                  \
-                },                                              \
-                .flags = _flags,                                \
-                .reg = _reg,                                    \
-                .max_rate = _max_rate,                          \
-                .u.pll = {                                      \
-                        .input_min = _input_min,                \
-                        .input_max = _input_max,                \
-                        .cf_min = _cf_min,                      \
-                        .cf_max = _cf_max,                      \
-                        .vco_min = _vco_min,                    \
-                        .vco_max = _vco_max,                    \
-                        .freq_table = _freq_table,              \
-                        .lock_delay = _lock_delay,              \
-                        .fixed_rate = _fixed_rate,              \
-                },                                              \
-                .clk_cfg_ex = _clk_cfg_ex,                      \
-        };                                                      \
-        DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,    \
-                         _name##_parent_names, _name##_parents, \
-                        &tegra_##_parent);
-#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
-                _max_rate, _ops, _parent, _clk_flags)           \
-        static const char *_name##_parent_names[] = {           \
-                #_parent,                                       \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                &tegra_##_parent,                               \
-        };                                                      \
-        static struct clk tegra_##_name;                        \
-        static struct clk_tegra tegra_##_name##_hw = {          \
-                .hw = {                                         \
-                        .clk = &tegra_##_name,                  \
-                },                                              \
-                .flags = _flags,                                \
-                .reg = _reg,                                    \
-                .max_rate = _max_rate,                          \
-                .reg_shift = _reg_shift,                        \
-        };                                                      \
-        DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,        \
-                _clk_flags,  _name##_parent_names,              \
-                _name##_parents, &tegra_##_parent);
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
-                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
-                tegra30_pll_ops, 0, NULL, pll_ref);
-DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
-                tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
-                1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
-                300, tegra30_pll_ops, 0, NULL, pll_ref);
-DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
-                tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
-                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
-                tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
-                pll_ref);
-DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
-                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
-DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
-                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
-DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
-                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
-DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
-                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
-                6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
-                300, tegra30_pll_ops, 0, NULL, pll_p_out1);
-DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
-                pll_a, CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
-                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
-                1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
-DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
-                pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
-DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
-                2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
-                tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
-                pll_ref);
-DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
-                pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
-                1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
-                1000, tegra30_pll_ops, 0, NULL, pll_ref);
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
-        /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
-        /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
-        /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
-        /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
-        /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
-        /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
-                2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
-                tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
-DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
-                pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        /* PLLE special case: use cpcon field to store cml divider value */
-        { 12000000,  100000000, 150, 1,  18, 11},
-        { 216000000, 100000000, 200, 18, 24, 13},
-        { 0, 0, 0, 0, 0, 0 },
-};
-DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
-                12000000, 12000000, 1200000000, 2400000000U,
-                tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
-                pll_ref);
-static const char *mux_plle[] = {
-        "pll_e",
-};
-static struct clk *mux_plle_p[] = {
-        &tegra_pll_e,
-};
-static struct clk tegra_cml0;
-static struct clk_tegra tegra_cml0_hw = {
-        .hw = {
-                .clk = &tegra_cml0,
-        },
-        .reg = 0x48c,
-        .fixed_rate = 100000000,
-        .u.periph = {
-                .clk_num = 0,
-        },
-};
-DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
-                mux_plle_p, &tegra_pll_e);
-static struct clk tegra_cml1;
-static struct clk_tegra tegra_cml1_hw = {
-        .hw = {
-                .clk = &tegra_cml1,
-        },
-        .reg = 0x48c,
-        .fixed_rate = 100000000,
-        .u.periph = {
-                .clk_num = 1,
-        },
-};
-DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
-                mux_plle_p, &tegra_pll_e);
-static struct clk tegra_pciex;
-static struct clk_tegra tegra_pciex_hw = {
-        .hw = {
-                .clk = &tegra_pciex,
-        },
-        .reg = 0x48c,
-        .fixed_rate = 100000000,
-        .reset = tegra30_periph_clk_reset,
-        .u.periph = {
-                .clk_num = 74,
-        },
-};
-DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
-                mux_plle_p, &tegra_pll_e);
-#define SYNC_SOURCE(_name)                                      \
-        static struct clk tegra_##_name##_sync;                 \
-        static struct clk_tegra tegra_##_name##_sync_hw = {     \
-                .hw = {                                         \
-                        .clk = &tegra_##_name##_sync,           \
-                },                                              \
-                .max_rate = 24000000,                           \
-                .fixed_rate = 24000000,                         \
-        };                                                      \
-        static struct clk tegra_##_name##_sync = {              \
-                .name = #_name "_sync",                         \
-                .hw = &tegra_##_name##_sync_hw.hw,              \
-                .ops = &tegra_sync_source_ops,                  \
-                .flags = CLK_IS_ROOT,                           \
-        };
-SYNC_SOURCE(spdif_in);
-SYNC_SOURCE(i2s0);
-SYNC_SOURCE(i2s1);
-SYNC_SOURCE(i2s2);
-SYNC_SOURCE(i2s3);
-SYNC_SOURCE(i2s4);
-SYNC_SOURCE(vimclk);
-static struct clk *tegra_sync_source_list[] = {
-        &tegra_spdif_in_sync,
-        &tegra_i2s0_sync,
-        &tegra_i2s1_sync,
-        &tegra_i2s2_sync,
-        &tegra_i2s3_sync,
-        &tegra_i2s4_sync,
-        &tegra_vimclk_sync,
-};
-static const char *mux_audio_sync_clk[] = {
-        "spdif_in_sync",
-        "i2s0_sync",
-        "i2s1_sync",
-        "i2s2_sync",
-        "i2s3_sync",
-        "i2s4_sync",
-        "vimclk_sync",
-};
-#define AUDIO_SYNC_CLK(_name, _index)                           \
-        static struct clk tegra_##_name;                        \
-        static struct clk_tegra tegra_##_name##_hw = {          \
-                .hw = {                                         \
-                        .clk = &tegra_##_name,                  \
-                },                                              \
-                .max_rate = 24000000,                           \
-                .reg = 0x4A0 + (_index) * 4,                    \
-        };                                                      \
-        static struct clk tegra_##_name = {                     \
-                .name = #_name,                                 \
-                .ops = &tegra30_audio_sync_clk_ops,             \
-                .hw = &tegra_##_name##_hw.hw,                   \
-                .parent_names = mux_audio_sync_clk,             \
-                .parents = tegra_sync_source_list,              \
-                .num_parents = ARRAY_SIZE(mux_audio_sync_clk),  \
-        };
-AUDIO_SYNC_CLK(audio0, 0);
-AUDIO_SYNC_CLK(audio1, 1);
-AUDIO_SYNC_CLK(audio2, 2);
-AUDIO_SYNC_CLK(audio3, 3);
-AUDIO_SYNC_CLK(audio4, 4);
-AUDIO_SYNC_CLK(audio5, 5);
-static struct clk *tegra_clk_audio_list[] = {
-        &tegra_audio0,
-        &tegra_audio1,
-        &tegra_audio2,
-        &tegra_audio3,
-        &tegra_audio4,
-        &tegra_audio5,  /* SPDIF */
-};
-#define AUDIO_SYNC_2X_CLK(_name, _index)                        \
-        static const char *_name##_parent_names[] = {           \
-                "tegra_" #_name,                                \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                &tegra_##_name,                                 \
-        };                                                      \
-        static struct clk tegra_##_name##_2x;                   \
-        static struct clk_tegra tegra_##_name##_2x_hw = {       \
-                .hw = {                                         \
-                        .clk = &tegra_##_name##_2x,             \
-                },                                              \
-                .flags = PERIPH_NO_RESET,                       \
-                .max_rate = 48000000,                           \
-                .reg = 0x49C,                                   \
-                .reg_shift = 24 + (_index),                     \
-                .u.periph = {                                   \
-                        .clk_num = 113 + (_index),              \
-                },                                              \
-        };                                                      \
-        static struct clk tegra_##_name##_2x = {                \
-                .name = #_name "_2x",                           \
-                .ops = &tegra30_clk_double_ops,                 \
-                .hw = &tegra_##_name##_2x_hw.hw,                \
-                .parent_names = _name##_parent_names,           \
-                .parents = _name##_parents,                     \
-                .parent = &tegra_##_name,                       \
-                .num_parents = 1,                               \
-        };
-AUDIO_SYNC_2X_CLK(audio0, 0);
-AUDIO_SYNC_2X_CLK(audio1, 1);
-AUDIO_SYNC_2X_CLK(audio2, 2);
-AUDIO_SYNC_2X_CLK(audio3, 3);
-AUDIO_SYNC_2X_CLK(audio4, 4);
-AUDIO_SYNC_2X_CLK(audio5, 5);   /* SPDIF */
-static struct clk *tegra_clk_audio_2x_list[] = {
-        &tegra_audio0_2x,
-        &tegra_audio1_2x,
-        &tegra_audio2_2x,
-        &tegra_audio3_2x,
-        &tegra_audio4_2x,
-        &tegra_audio5_2x,       /* SPDIF */
-};
-#define MUX_I2S_SPDIF(_id)                                      \
-static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {      \
-        "pll_a_out0",                                           \
-        #_id "_2x",                                             \
-        "pll_p",                                                \
-        "clk_m",                                                \
-};                                                              \
-static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {    \
-        &tegra_pll_a_out0,                                      \
-        &tegra_##_id##_2x,                                      \
-        &tegra_pll_p,                                           \
-        &tegra_clk_m,                                           \
-};
-MUX_I2S_SPDIF(audio0);
-MUX_I2S_SPDIF(audio1);
-MUX_I2S_SPDIF(audio2);
-MUX_I2S_SPDIF(audio3);
-MUX_I2S_SPDIF(audio4);
-MUX_I2S_SPDIF(audio5);          /* SPDIF */
-static struct clk tegra_extern1;
-static struct clk tegra_extern2;
-static struct clk tegra_extern3;
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)                                     \
-static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {       \
-        "clk_m",                                                \
-        "clk_m_div2",                                           \
-        "clk_m_div4",                                           \
-        "extern" #_id,                                          \
-};                                                              \
-static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {   \
-        &tegra_clk_m,                                           \
-        &tegra_clk_m_div2,                                      \
-        &tegra_clk_m_div4,                                      \
-        &tegra_extern##_id,                                     \
-};
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-#define CLK_OUT_CLK(_name, _index)                                      \
-        static struct clk tegra_##_name;                                \
-        static struct clk_tegra tegra_##_name##_hw = {                  \
-                .hw = {                                                 \
-                        .clk = &tegra_##_name,                          \
-                },                                                      \
-                .lookup = {                                             \
-                        .dev_id = #_name,                               \
-                        .con_id = "extern" #_index,                     \
-                },                                                      \
-                .flags = MUX_CLK_OUT,                                   \
-                .fixed_rate = 216000000,                                        \
-                .reg = 0x1a8,                                           \
-                .u.periph = {                                           \
-                        .clk_num = (_index - 1) * 8 + 2,                \
-                },                                                      \
-        };                                                              \
-        static struct clk tegra_##_name = {                             \
-                .name = #_name,                                         \
-                .ops = &tegra_clk_out_ops,                              \
-                .hw = &tegra_##_name##_hw.hw,                           \
-                .parent_names = mux_clkm_clkm2_clkm4_extern##_index,    \
-                .parents = mux_clkm_clkm2_clkm4_extern##_index##_p,     \
-                .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
-        };
-CLK_OUT_CLK(clk_out_1, 1);
-CLK_OUT_CLK(clk_out_2, 2);
-CLK_OUT_CLK(clk_out_3, 3);
-static struct clk *tegra_clk_out_list[] = {
-        &tegra_clk_out_1,
-        &tegra_clk_out_2,
-        &tegra_clk_out_3,
-};
-static const char *mux_sclk[] = {
-        "clk_m",
-        "pll_c_out1",
-        "pll_p_out4",
-        "pll_p_out3",
-        "pll_p_out2",
-        "dummy",
-        "clk_32k",
-        "pll_m_out1",
-};
-static struct clk *mux_sclk_p[] = {
-        &tegra_clk_m,
-        &tegra_pll_c_out1,
-        &tegra_pll_p_out4,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out2,
-        NULL,
-        &tegra_clk_32k,
-        &tegra_pll_m_out1,
-};
-static struct clk tegra_clk_sclk;
-static struct clk_tegra tegra_clk_sclk_hw = {
-        .hw = {
-                .clk = &tegra_clk_sclk,
-        },
-        .reg = 0x28,
-        .max_rate = 334000000,
-        .min_rate = 40000000,
-};
-static struct clk tegra_clk_sclk = {
-        .name = "sclk",
-        .ops = &tegra30_super_ops,
-        .hw = &tegra_clk_sclk_hw.hw,
-        .parent_names = mux_sclk,
-        .parents = mux_sclk_p,
-        .num_parents = ARRAY_SIZE(mux_sclk),
-};
-static const char *tegra_hclk_parent_names[] = {
-        "tegra_sclk",
-};
-static struct clk *tegra_hclk_parents[] = {
-        &tegra_clk_sclk,
-};
-static struct clk tegra_hclk;
-static struct clk_tegra tegra_hclk_hw = {
-        .hw = {
-                .clk = &tegra_hclk,
-        },
-        .flags = DIV_BUS,
-        .reg = 0x30,
-        .reg_shift = 4,
-        .max_rate = 378000000,
-        .min_rate = 12000000,
-};
-DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
-                tegra_hclk_parents, &tegra_clk_sclk);
-static const char *tegra_pclk_parent_names[] = {
-        "tegra_hclk",
-};
-static struct clk *tegra_pclk_parents[] = {
-        &tegra_hclk,
-};
-static struct clk tegra_pclk;
-static struct clk_tegra tegra_pclk_hw = {
-        .hw = {
-                .clk = &tegra_pclk,
-        },
-        .flags = DIV_BUS,
-        .reg = 0x30,
-        .reg_shift = 0,
-        .max_rate = 167000000,
-        .min_rate = 12000000,
-};
-DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
-                tegra_pclk_parents, &tegra_hclk);
-static const char *mux_blink[] = {
-        "clk_32k",
-};
-static struct clk *mux_blink_p[] = {
-        &tegra_clk_32k,
-};
-static struct clk tegra_clk_blink;
-static struct clk_tegra tegra_clk_blink_hw = {
-        .hw = {
-                .clk = &tegra_clk_blink,
-        },
-        .reg = 0x40,
-        .max_rate = 32768,
-};
-static struct clk tegra_clk_blink = {
-        .name = "blink",
-        .ops = &tegra30_blink_clk_ops,
-        .hw = &tegra_clk_blink_hw.hw,
-        .parent = &tegra_clk_32k,
-        .parent_names = mux_blink,
-        .parents = mux_blink_p,
-        .num_parents = ARRAY_SIZE(mux_blink),
-};
-static const char *mux_pllm_pllc_pllp_plla[] = {
-        "pll_m",
-        "pll_c",
-        "pll_p",
-        "pll_a_out0",
-};
-static const char *mux_pllp_pllc_pllm_clkm[] = {
-        "pll_p",
-        "pll_c",
-        "pll_m",
-        "clk_m",
-};
-static const char *mux_pllp_clkm[] = {
-        "pll_p",
-        "dummy",
-        "dummy",
-        "clk_m",
-};
-static const char *mux_pllp_plld_pllc_clkm[] = {
-        "pll_p",
-        "pll_d_out0",
-        "pll_c",
-        "clk_m",
-};
-static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-        "pll_p",
-        "pll_m",
-        "pll_d_out0",
-        "pll_a_out0",
-        "pll_c",
-        "pll_d2_out0",
-        "clk_m",
-};
-static const char *mux_plla_pllc_pllp_clkm[] = {
-        "pll_a_out0",
-        "dummy",
-        "pll_p",
-        "clk_m"
-};
-static const char *mux_pllp_pllc_clk32_clkm[] = {
-        "pll_p",
-        "pll_c",
-        "clk_32k",
-        "clk_m",
-};
-static const char *mux_pllp_pllc_clkm_clk32[] = {
-        "pll_p",
-        "pll_c",
-        "clk_m",
-        "clk_32k",
-};
-static const char *mux_pllp_pllc_pllm[] = {
-        "pll_p",
-        "pll_c",
-        "pll_m",
-};
-static const char *mux_clk_m[] = {
-        "clk_m",
-};
-static const char *mux_pllp_out3[] = {
-        "pll_p_out3",
-};
-static const char *mux_plld_out0[] = {
-        "pll_d_out0",
-};
-static const char *mux_plld_out0_plld2_out0[] = {
-        "pll_d_out0",
-        "pll_d2_out0",
-};
-static const char *mux_clk_32k[] = {
-        "clk_32k",
-};
-static const char *mux_plla_clk32_pllp_clkm_plle[] = {
-        "pll_a_out0",
-        "clk_32k",
-        "pll_p",
-        "clk_m",
-        "pll_e",
-};
-static const char *mux_cclk_g[] = {
-        "clk_m",
-        "pll_c",
-        "clk_32k",
-        "pll_m",
-        "pll_p",
-        "pll_p_out4",
-        "pll_p_out3",
-        "dummy",
-        "pll_x",
-};
-static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
-        &tegra_pll_m,
-        &tegra_pll_c,
-        &tegra_pll_p,
-        &tegra_pll_a_out0,
-};
-static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_pll_m,
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_clkm_p[] = {
-        &tegra_pll_p,
-        NULL,
-        NULL,
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_d_out0,
-        &tegra_pll_c,
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_m,
-        &tegra_pll_d_out0,
-        &tegra_pll_a_out0,
-        &tegra_pll_c,
-        &tegra_pll_d2_out0,
-        &tegra_clk_m,
-};
-static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
-        &tegra_pll_a_out0,
-        NULL,
-        &tegra_pll_p,
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_clk_32k,
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_clk_m,
-        &tegra_clk_32k,
-};
-static struct clk *mux_pllp_pllc_pllm_p[] = {
-        &tegra_pll_p,
-        &tegra_pll_c,
-        &tegra_pll_m,
-};
-static struct clk *mux_clk_m_p[] = {
-        &tegra_clk_m,
-};
-static struct clk *mux_pllp_out3_p[] = {
-        &tegra_pll_p_out3,
-};
-static struct clk *mux_plld_out0_p[] = {
-        &tegra_pll_d_out0,
-};
-static struct clk *mux_plld_out0_plld2_out0_p[] = {
-        &tegra_pll_d_out0,
-        &tegra_pll_d2_out0,
-};
-static struct clk *mux_clk_32k_p[] = {
-        &tegra_clk_32k,
-};
-static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
-        &tegra_pll_a_out0,
-        &tegra_clk_32k,
-        &tegra_pll_p,
-        &tegra_clk_m,
-        &tegra_pll_e,
-};
-static struct clk *mux_cclk_g_p[] = {
-        &tegra_clk_m,
-        &tegra_pll_c,
-        &tegra_clk_32k,
-        &tegra_pll_m,
-        &tegra_pll_p,
-        &tegra_pll_p_out4,
-        &tegra_pll_p_out3,
-        NULL,
-        &tegra_pll_x,
-};
-static struct clk tegra_clk_cclk_g;
-static struct clk_tegra tegra_clk_cclk_g_hw = {
-        .hw = {
-                .clk = &tegra_clk_cclk_g,
-        },
-        .flags = DIV_U71 | DIV_U71_INT,
-        .reg = 0x368,
-        .max_rate = 1700000000,
-};
-static struct clk tegra_clk_cclk_g = {
-        .name = "cclk_g",
-        .ops = &tegra30_super_ops,
-        .hw = &tegra_clk_cclk_g_hw.hw,
-        .parent_names = mux_cclk_g,
-        .parents = mux_cclk_g_p,
-        .num_parents = ARRAY_SIZE(mux_cclk_g),
-};
-static const char *mux_twd[] = {
-        "cclk_g",
-};
-static struct clk *mux_twd_p[] = {
-        &tegra_clk_cclk_g,
-};
-static struct clk tegra30_clk_twd;
-static struct clk_tegra tegra30_clk_twd_hw = {
-        .hw = {
-                .clk = &tegra30_clk_twd,
-        },
-        .max_rate = 1400000000,
-        .mul = 1,
-        .div = 2,
-};
-static struct clk tegra30_clk_twd = {
-        .name = "twd",
-        .ops = &tegra30_twd_ops,
-        .hw = &tegra30_clk_twd_hw.hw,
-        .parent = &tegra_clk_cclk_g,
-        .parent_names = mux_twd,
-        .parents = mux_twd_p,
-        .num_parents = ARRAY_SIZE(mux_twd),
-};
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
-                _max, _inputs, _flags)                  \
-        static struct clk tegra_##_name;                \
-        static struct clk_tegra tegra_##_name##_hw = {  \
-                .hw = {                                 \
-                        .clk = &tegra_##_name,          \
-                },                                      \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id = _con,                 \
-                },                                      \
-                .reg = _reg,                            \
-                .flags = _flags,                        \
-                .max_rate = _max,                       \
-                .u.periph = {                           \
-                        .clk_num = _clk_num,            \
-                },                                      \
-                .reset = &tegra30_periph_clk_reset,     \
-        };                                              \
-        static struct clk tegra_##_name = {             \
-                .name = #_name,                         \
-                .ops = &tegra30_periph_clk_ops,         \
-                .hw = &tegra_##_name##_hw.hw,           \
-                .parent_names = _inputs,                \
-                .parents = _inputs##_p,                 \
-                .num_parents = ARRAY_SIZE(_inputs),     \
-        };
-PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0);
-PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
-PERIPH_CLK(kbc,         "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
-PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
-PERIPH_CLK(kfuse,       "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0);
-PERIPH_CLK(fuse,        "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB);
-PERIPH_CLK(fuse_burn,   "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB);
-PERIPH_CLK(apbif,       "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0);
-PERIPH_CLK(i2s0,        "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(i2s1,        "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(i2s2,        "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(i2s3,        "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(i2s4,        "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(spdif_out,   "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio5_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(spdif_in,    "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(d_audio,     "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
-PERIPH_CLK(dam0,        "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
-PERIPH_CLK(dam1,        "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
-PERIPH_CLK(dam2,        "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
-PERIPH_CLK(hda,         "tegra30-hda",          "hda",  125,    0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(hda2codec_2x,        "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(hda2hdmi,    "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0);
-PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc5,        "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc6,        "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sata_oob,    "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sata,        "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(sata_cold,   "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0);
-PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(ndspeed,     "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(vde,         "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
-PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
-PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
-PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
-PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c4,        "tegra-i2c.3",          "div-clk", 103, 0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c5,        "tegra-i2c.4",          "div-clk", 47,  0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
-PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
-PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
-PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
-PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
-PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
-PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
-PERIPH_CLK(3d2,         "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
-PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
-PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET);
-PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
-PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
-PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
-PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(dtv,         "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0);
-PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71);
-PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
-PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
-PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
-PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
-PERIPH_CLK(dsia,        "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0);
-PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0);
-PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
-PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
-PERIPH_CLK(tsensor,     "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71);
-PERIPH_CLK(actmon,      "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71);
-PERIPH_CLK(extern1,     "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
-PERIPH_CLK(extern2,     "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
-PERIPH_CLK(extern3,     "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
-PERIPH_CLK(i2cslow,     "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(pcie,        "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(afi,         "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0);
-PERIPH_CLK(se,          "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
-static struct clk tegra_dsib;
-static struct clk_tegra tegra_dsib_hw = {
-        .hw = {
-                .clk = &tegra_dsib,
-        },
-        .lookup = {
-                .dev_id = "tegradc.1",
-                .con_id = "dsib",
-        },
-        .reg = 0xd0,
-        .flags = MUX | PLLD,
-        .max_rate = 500000000,
-        .u.periph = {
-                .clk_num = 82,
-        },
-        .reset = &tegra30_periph_clk_reset,
-};
-static struct clk tegra_dsib = {
-        .name = "dsib",
-        .ops = &tegra30_dsib_clk_ops,
-        .hw = &tegra_dsib_hw.hw,
-        .parent_names = mux_plld_out0_plld2_out0,
-        .parents = mux_plld_out0_plld2_out0_p,
-        .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
-};
-struct clk *tegra_list_clks[] = {
-        &tegra_apbdma,
-        &tegra_rtc,
-        &tegra_kbc,
-        &tegra_timer,
-        &tegra_kfuse,
-        &tegra_fuse,
-        &tegra_fuse_burn,
-        &tegra_apbif,
-        &tegra_i2s0,
-        &tegra_i2s1,
-        &tegra_i2s2,
-        &tegra_i2s3,
-        &tegra_i2s4,
-        &tegra_spdif_out,
-        &tegra_spdif_in,
-        &tegra_pwm,
-        &tegra_d_audio,
-        &tegra_dam0,
-        &tegra_dam1,
-        &tegra_dam2,
-        &tegra_hda,
-        &tegra_hda2codec_2x,
-        &tegra_hda2hdmi,
-        &tegra_sbc1,
-        &tegra_sbc2,
-        &tegra_sbc3,
-        &tegra_sbc4,
-        &tegra_sbc5,
-        &tegra_sbc6,
-        &tegra_sata_oob,
-        &tegra_sata,
-        &tegra_sata_cold,
-        &tegra_ndflash,
-        &tegra_ndspeed,
-        &tegra_vfir,
-        &tegra_sdmmc1,
-        &tegra_sdmmc2,
-        &tegra_sdmmc3,
-        &tegra_sdmmc4,
-        &tegra_vcp,
-        &tegra_bsea,
-        &tegra_bsev,
-        &tegra_vde,
-        &tegra_csite,
-        &tegra_la,
-        &tegra_owr,
-        &tegra_nor,
-        &tegra_mipi,
-        &tegra_i2c1,
-        &tegra_i2c2,
-        &tegra_i2c3,
-        &tegra_i2c4,
-        &tegra_i2c5,
-        &tegra_uarta,
-        &tegra_uartb,
-        &tegra_uartc,
-        &tegra_uartd,
-        &tegra_uarte,
-        &tegra_vi,
-        &tegra_3d,
-        &tegra_3d2,
-        &tegra_2d,
-        &tegra_vi_sensor,
-        &tegra_epp,
-        &tegra_mpe,
-        &tegra_host1x,
-        &tegra_cve,
-        &tegra_tvo,
-        &tegra_dtv,
-        &tegra_hdmi,
-        &tegra_tvdac,
-        &tegra_disp1,
-        &tegra_disp2,
-        &tegra_usbd,
-        &tegra_usb2,
-        &tegra_usb3,
-        &tegra_dsia,
-        &tegra_dsib,
-        &tegra_csi,
-        &tegra_isp,
-        &tegra_csus,
-        &tegra_tsensor,
-        &tegra_actmon,
-        &tegra_extern1,
-        &tegra_extern2,
-        &tegra_extern3,
-        &tegra_i2cslow,
-        &tegra_pcie,
-        &tegra_afi,
-        &tegra_se,
-};
-#define CLK_DUPLICATE(_name, _dev, _con)        \
-        {                                       \
-                .name   = _name,                \
-                .lookup = {                     \
-                        .dev_id = _dev,         \
-                        .con_id = _con,         \
-                },                              \
-        }
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
-        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
-        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
-        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
-        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
-        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
-        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
-        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
-        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
-        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
-        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
-        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
-        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
-        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
-        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
-        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
-        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
-        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
-        CLK_DUPLICATE("twd", "smp_twd", NULL),
-        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
-        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
-        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
-        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
-        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
-        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
-        CLK_DUPLICATE("dam0", NULL, "dam0"),
-        CLK_DUPLICATE("dam1", NULL, "dam1"),
-        CLK_DUPLICATE("dam2", NULL, "dam2"),
-        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
-        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
-        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
-        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
-        CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
-};
-struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_clk_m,
-        &tegra_clk_m_div2,
-        &tegra_clk_m_div4,
-        &tegra_pll_ref,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_d2,
-        &tegra_pll_d2_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_x_out0,
-        &tegra_pll_e,
-        &tegra_clk_cclk_g,
-        &tegra_cml0,
-        &tegra_cml1,
-        &tegra_pciex,
-        &tegra_clk_sclk,
-        &tegra_hclk,
-        &tegra_pclk,
-        &tegra_clk_blink,
-        &tegra30_clk_twd,
-};
-static void tegra30_init_one_clock(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(c->hw);
-        __clk_init(NULL, c);
-        INIT_LIST_HEAD(&clk->shared_bus_list);
-        if (!clk->lookup.dev_id && !clk->lookup.con_id)
-                clk->lookup.con_id = c->name;
-        clk->lookup.clk = c;
-        clkdev_add(&clk->lookup);
-        tegra_clk_add(c);
-}
-void __init tegra30_init_clocks(void)
-{
-        int i;
-        struct clk *c;
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra30_init_one_clock(tegra_ptr_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra30_init_one_clock(tegra_list_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
-                tegra30_init_one_clock(tegra_sync_source_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
-                tegra30_init_one_clock(tegra_clk_audio_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-                tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
-                tegra30_init_one_clock(tegra_clk_out_list[i]);
-        tegra30_cpu_car_ops_init();
-}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
deleted file mode 100644
index 9764d31032b7..000000000000
--- a/arch/arm/mach-tegra/tegra_cpu_car.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __MACH_TEGRA_CPU_CAR_H
-#define __MACH_TEGRA_CPU_CAR_H
-/*
- * Tegra CPU clock and reset control ops
- *
- * wait_for_reset:
- *      keep waiting until the CPU in reset state
- * put_in_reset:
- *      put the CPU in reset state
- * out_of_reset:
- *      release the CPU from reset state
- * enable_clock:
- *      CPU clock un-gate
- * disable_clock:
- *      CPU clock gate
- * rail_off_ready:
- *      CPU is ready for rail off
- * suspend:
- *      save the clock settings when CPU go into low-power state
- * resume:
- *      restore the clock settings when CPU exit low-power state
- */
-struct tegra_cpu_car_ops {
-        void (*wait_for_reset)(u32 cpu);
-        void (*put_in_reset)(u32 cpu);
-        void (*out_of_reset)(u32 cpu);
-        void (*enable_clock)(u32 cpu);
-        void (*disable_clock)(u32 cpu);
-#ifdef CONFIG_PM_SLEEP
-        bool (*rail_off_ready)(void);
-        void (*suspend)(void);
-        void (*resume)(void);
-#endif
-};
-extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
-static inline void tegra_wait_cpu_in_reset(u32 cpu)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
-                return;
-        tegra_cpu_car_ops->wait_for_reset(cpu);
-}
-static inline void tegra_put_cpu_in_reset(u32 cpu)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
-                return;
-        tegra_cpu_car_ops->put_in_reset(cpu);
-}
-static inline void tegra_cpu_out_of_reset(u32 cpu)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
-                return;
-        tegra_cpu_car_ops->out_of_reset(cpu);
-}
-static inline void tegra_enable_cpu_clock(u32 cpu)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
-                return;
-        tegra_cpu_car_ops->enable_clock(cpu);
-}
-static inline void tegra_disable_cpu_clock(u32 cpu)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
-                return;
-        tegra_cpu_car_ops->disable_clock(cpu);
-}
-#ifdef CONFIG_PM_SLEEP
-static inline bool tegra_cpu_rail_off_ready(void)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
-                return false;
-        return tegra_cpu_car_ops->rail_off_ready();
-}
-static inline void tegra_cpu_clock_suspend(void)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->suspend))
-                return;
-        tegra_cpu_car_ops->suspend();
-}
-static inline void tegra_cpu_clock_resume(void)
-{
-        if (WARN_ON(!tegra_cpu_car_ops->resume))
-                return;
-        tegra_cpu_car_ops->resume();
-}
-#endif
-void tegra20_cpu_car_ops_init(void);
-void tegra30_cpu_car_ops_init(void);
-#endif /* __MACH_TEGRA_CPU_CAR_H */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
deleted file mode 100644
index e4863f3e9ee7..000000000000
--- a/arch/arm/mach-tegra/timer.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * arch/arch/mach-tegra/timer.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/mach/time.h>
-#include <asm/smp_twd.h>
-#include <asm/sched_clock.h>
-#include "board.h"
-#define RTC_SECONDS            0x08
-#define RTC_SHADOW_SECONDS     0x0c
-#define RTC_MILLISECONDS       0x10
-#define TIMERUS_CNTR_1US 0x10
-#define TIMERUS_USEC_CFG 0x14
-#define TIMERUS_CNTR_FREEZE 0x4c
-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-static void __iomem *timer_reg_base;
-static void __iomem *rtc_base;
-static struct timespec persistent_ts;
-static u64 persistent_ms, last_persistent_ms;
-#define timer_writel(value, reg) \
-        __raw_writel(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
-        __raw_readl(timer_reg_base + (reg))
-static int tegra_timer_set_next_event(unsigned long cycles,
-                                         struct clock_event_device *evt)
-{
-        u32 reg;
-        reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-        timer_writel(reg, TIMER3_BASE + TIMER_PTV);
-        return 0;
-}
-static void tegra_timer_set_mode(enum clock_event_mode mode,
-                                    struct clock_event_device *evt)
-{
-        u32 reg;
-        timer_writel(0, TIMER3_BASE + TIMER_PTV);
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                reg = 0xC0000000 | ((1000000/HZ)-1);
-                timer_writel(reg, TIMER3_BASE + TIMER_PTV);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-static struct clock_event_device tegra_clockevent = {
-        .name           = "timer0",
-        .rating         = 300,
-        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-        .set_next_event = tegra_timer_set_next_event,
-        .set_mode       = tegra_timer_set_mode,
-};
-static u32 notrace tegra_read_sched_clock(void)
-{
-        return timer_readl(TIMERUS_CNTR_1US);
-}
-/*
- * tegra_rtc_read - Reads the Tegra RTC registers
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-static u64 tegra_rtc_read_ms(void)
-{
-        u32 ms = readl(rtc_base + RTC_MILLISECONDS);
-        u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
-        return (u64)s * MSEC_PER_SEC + ms;
-}
-/*
- * tegra_read_persistent_clock -  Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer.  Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec.
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-static void tegra_read_persistent_clock(struct timespec *ts)
-{
-        u64 delta;
-        struct timespec *tsp = &persistent_ts;
-        last_persistent_ms = persistent_ms;
-        persistent_ms = tegra_rtc_read_ms();
-        delta = persistent_ms - last_persistent_ms;
-        timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
-        *ts = *tsp;
-}
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-        timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-static struct irqaction tegra_timer_irq = {
-        .name           = "timer0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
-        .handler        = tegra_timer_interrupt,
-        .dev_id         = &tegra_clockevent,
-};
-static const struct of_device_id timer_match[] __initconst = {
-        { .compatible = "nvidia,tegra20-timer" },
-        {}
-};
-static const struct of_device_id rtc_match[] __initconst = {
-        { .compatible = "nvidia,tegra20-rtc" },
-        {}
-};
-static void __init tegra_init_timer(void)
-{
-        struct device_node *np;
-        struct clk *clk;
-        unsigned long rate;
-        int ret;
-        np = of_find_matching_node(NULL, timer_match);
-        if (!np) {
-                pr_err("Failed to find timer DT node\n");
-                BUG();
-        }
-        timer_reg_base = of_iomap(np, 0);
-        if (!timer_reg_base) {
-                pr_err("Can't map timer registers");
-                BUG();
-        }
-        tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
-        if (tegra_timer_irq.irq <= 0) {
-                pr_err("Failed to map timer IRQ\n");
-                BUG();
-        }
-        clk = clk_get_sys("timer", NULL);
-        if (IS_ERR(clk)) {
-                pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
-                rate = 12000000;
-        } else {
-                clk_prepare_enable(clk);
-                rate = clk_get_rate(clk);
-        }
-        of_node_put(np);
-        np = of_find_matching_node(NULL, rtc_match);
-        if (!np) {
-                pr_err("Failed to find RTC DT node\n");
-                BUG();
-        }
-        rtc_base = of_iomap(np, 0);
-        if (!rtc_base) {
-                pr_err("Can't map RTC registers");
-                BUG();
-        }
-        /*
-         * rtc registers are used by read_persistent_clock, keep the rtc clock
-         * enabled
-         */
-        clk = clk_get_sys("rtc-tegra", NULL);
-        if (IS_ERR(clk))
-                pr_warn("Unable to get rtc-tegra clock\n");
-        else
-                clk_prepare_enable(clk);
-        of_node_put(np);
-        switch (rate) {
-        case 12000000:
-                timer_writel(0x000b, TIMERUS_USEC_CFG);
-                break;
-        case 13000000:
-                timer_writel(0x000c, TIMERUS_USEC_CFG);
-                break;
-        case 19200000:
-                timer_writel(0x045f, TIMERUS_USEC_CFG);
-                break;
-        case 26000000:
-                timer_writel(0x0019, TIMERUS_USEC_CFG);
-                break;
-        default:
-                WARN(1, "Unknown clock rate");
-        }
-        setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
-        if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-                "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
-                pr_err("Failed to register clocksource\n");
-                BUG();
-        }
-        ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-        if (ret) {
-                pr_err("Failed to register timer IRQ: %d\n", ret);
-                BUG();
-        }
-        clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
-        tegra_clockevent.max_delta_ns =
-                clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
-        tegra_clockevent.min_delta_ns =
-                clockevent_delta2ns(0x1, &tegra_clockevent);
-        tegra_clockevent.cpumask = cpu_all_mask;
-        tegra_clockevent.irq = tegra_timer_irq.irq;
-        clockevents_register_device(&tegra_clockevent);
-#ifdef CONFIG_HAVE_ARM_TWD
-        twd_local_timer_of_register();
-#endif
-        register_persistent_clock(NULL, tegra_read_persistent_clock);
-}
-struct sys_timer tegra_sys_timer = {
-        .init = tegra_init_timer,
-};
-#ifdef CONFIG_PM
-static u32 usec_config;
-void tegra_timer_suspend(void)
-{
-        usec_config = timer_readl(TIMERUS_USEC_CFG);
-}
-void tegra_timer_resume(void)
-{
-        timer_writel(usec_config, TIMERUS_USEC_CFG);
-}
-#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 4ce77cdc31cc..a683d17b2ce4 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -31,16 +31,16 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
 #include <linux/platform_data/pinctrl-coh901.h>
+#include <linux/platform_data/dma-coh901318.h>
+#include <linux/irqchip/arm-vic.h>
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include <mach/irqs.h>
@@ -49,7 +49,6 @@
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
-#include "dma_channels.h"
 /*
 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -327,1089 +326,6 @@ static struct resource dma_resource[] = {
        }
 };
-/* points out all dma slave channels.
- * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
- * Select all channels from A to B, end of list is marked with -1,-1
- */
-static int dma_slave_channels[] = {
-        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
-        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
-/* points out all dma memcpy channels. */
-static int dma_memcpy_channels[] = {
-        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-/** register dma for memory access
- *
- * active  1 means dma intends to access memory
- *         0 means dma wont access memory
- */
-static void coh901318_access_memory_state(struct device *dev, bool active)
-{
-}
-#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
-                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
-                        COH901318_CX_CFG_LCR_DISABLE | \
-                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
-                        COH901318_CX_CFG_BE_IRQ_ENABLE)
-#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
-                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                        COH901318_CX_CTRL_TCP_DISABLE | \
-                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
-                        COH901318_CX_CTRL_HSP_DISABLE | \
-                        COH901318_CX_CTRL_HSS_DISABLE | \
-                        COH901318_CX_CTRL_DDMA_LEGACY | \
-                        COH901318_CX_CTRL_PRDD_SOURCE)
-const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
-        {
-                .number = U300_DMA_MSL_TX_0,
-                .name = "MSL TX 0",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_TX_1,
-                .name = "MSL TX 1",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_2,
-                .name = "MSL TX 2",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .desc_nbr_max = 10,
-        },
-        {
-                .number = U300_DMA_MSL_TX_3,
-                .name = "MSL TX 3",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_4,
-                .name = "MSL TX 4",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_MSL_TX_5,
-                .name = "MSL TX 5",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_TX_6,
-                .name = "MSL TX 6",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
-        },
-        {
-                .number = U300_DMA_MSL_RX_0,
-                .name = "MSL RX 0",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
-        },
-        {
-                .number = U300_DMA_MSL_RX_1,
-                .name = "MSL RX 1",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_2,
-                .name = "MSL RX 2",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_3,
-                .name = "MSL RX 3",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_4,
-                .name = "MSL RX 4",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_5,
-                .name = "MSL RX 5",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_MSL_RX_6,
-                .name = "MSL RX 6",
-                .priority_high = 0,
-                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_MMCSD_RX_TX,
-                .name = "MMCSD RX TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_MSPRO_TX,
-                .name = "MSPRO TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_MSPRO_RX,
-                .name = "MSPRO RX",
-                .priority_high = 0,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_UART0_TX,
-                .name = "UART0 TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_UART0_RX,
-                .name = "UART0 RX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_APEX_TX,
-                .name = "APEX TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_APEX_RX,
-                .name = "APEX RX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_PCM_I2S0_TX,
-                .name = "PCM I2S0 TX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_PCM_I2S0_RX,
-                .name = "PCM I2S0 RX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_PCM_I2S1_TX,
-                .name = "PCM I2S1 TX",
-                .priority_high = 1,
-                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_SOURCE,
-        },
-        {
-                .number = U300_DMA_PCM_I2S1_RX,
-                .name = "PCM I2S1 RX",
-                .priority_high = 1,
-                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY |
-                                COH901318_CX_CTRL_PRDD_DEST,
-        },
-        {
-                .number = U300_DMA_XGAM_CDI,
-                .name = "XGAM CDI",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_XGAM_PDI,
-                .name = "XGAM PDI",
-                .priority_high = 0,
-        },
-        /*
-         * Don't set up device address, burst count or size of src
-         * or dst bus for this peripheral - handled by PrimeCell
-         * DMA extension.
-         */
-        {
-                .number = U300_DMA_SPI_TX,
-                .name = "SPI TX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_SPI_RX,
-                .name = "SPI RX",
-                .priority_high = 0,
-                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                                COH901318_CX_CFG_LCR_DISABLE |
-                                COH901318_CX_CFG_TC_IRQ_ENABLE |
-                                COH901318_CX_CFG_BE_IRQ_ENABLE,
-                .param.ctrl_lli_chained = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-                .param.ctrl_lli_last = 0 |
-                                COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                                COH901318_CX_CTRL_TCP_DISABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                                COH901318_CX_CTRL_HSP_ENABLE |
-                                COH901318_CX_CTRL_HSS_DISABLE |
-                                COH901318_CX_CTRL_DDMA_LEGACY,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_0,
-                .name = "GENERAL 00",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_1,
-                .name = "GENERAL 01",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_2,
-                .name = "GENERAL 02",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_3,
-                .name = "GENERAL 03",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_4,
-                .name = "GENERAL 04",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_5,
-                .name = "GENERAL 05",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_6,
-                .name = "GENERAL 06",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_7,
-                .name = "GENERAL 07",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_8,
-                .name = "GENERAL 08",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_UART1_TX,
-                .name = "UART1 TX",
-                .priority_high = 0,
-        },
-        {
-                .number = U300_DMA_UART1_RX,
-                .name = "UART1 RX",
-                .priority_high = 0,
-        }
-};
-static struct coh901318_platform coh901318_platform = {
-        .chans_slave = dma_slave_channels,
-        .chans_memcpy = dma_memcpy_channels,
-        .access_memory_state = coh901318_access_memory_state,
-        .chan_conf = chan_config,
-        .max_channels = U300_DMA_CHANNELS,
-};
 static struct resource pinctrl_resources[] = {
        {
@@ -1521,7 +437,6 @@ static struct platform_device dma_device = {
        .resource       = dma_resource,
        .num_resources  = ARRAY_SIZE(dma_resource),
        .dev = {
-                .platform_data = &coh901318_platform,
                .coherent_dma_mask = ~0,
        },
 };
@@ -1779,8 +694,7 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
        .map_io         = u300_map_io,
        .nr_irqs        = 0,
        .init_irq       = u300_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = u300_timer_init,
-        .timer          = &u300_timer,
        .init_machine   = u300_init_machine,
        .restart        = u300_restart,
 MACHINE_END
diff --git a/arch/arm/mach-u300/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
deleted file mode 100644
index 4e8a88fbca49..000000000000
--- a/arch/arm/mach-u300/dma_channels.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/dma_channels.h
- *
- *
- * Copyright (C) 2007-2012 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * Map file for the U300 dma driver.
- * Author: Per Friden <per.friden@stericsson.com>
- */
-#ifndef DMA_CHANNELS_H
-#define DMA_CHANNELS_H
-#define U300_DMA_MSL_TX_0             0
-#define U300_DMA_MSL_TX_1             1
-#define U300_DMA_MSL_TX_2             2
-#define U300_DMA_MSL_TX_3             3
-#define U300_DMA_MSL_TX_4             4
-#define U300_DMA_MSL_TX_5             5
-#define U300_DMA_MSL_TX_6             6
-#define U300_DMA_MSL_RX_0             7
-#define U300_DMA_MSL_RX_1             8
-#define U300_DMA_MSL_RX_2             9
-#define U300_DMA_MSL_RX_3             10
-#define U300_DMA_MSL_RX_4             11
-#define U300_DMA_MSL_RX_5             12
-#define U300_DMA_MSL_RX_6             13
-#define U300_DMA_MMCSD_RX_TX          14
-#define U300_DMA_MSPRO_TX             15
-#define U300_DMA_MSPRO_RX             16
-#define U300_DMA_UART0_TX             17
-#define U300_DMA_UART0_RX             18
-#define U300_DMA_APEX_TX              19
-#define U300_DMA_APEX_RX              20
-#define U300_DMA_PCM_I2S0_TX          21
-#define U300_DMA_PCM_I2S0_RX          22
-#define U300_DMA_PCM_I2S1_TX          23
-#define U300_DMA_PCM_I2S1_RX          24
-#define U300_DMA_XGAM_CDI             25
-#define U300_DMA_XGAM_PDI             26
-#define U300_DMA_SPI_TX               27
-#define U300_DMA_SPI_RX               28
-#define U300_DMA_GENERAL_PURPOSE_0    29
-#define U300_DMA_GENERAL_PURPOSE_1    30
-#define U300_DMA_GENERAL_PURPOSE_2    31
-#define U300_DMA_GENERAL_PURPOSE_3    32
-#define U300_DMA_GENERAL_PURPOSE_4    33
-#define U300_DMA_GENERAL_PURPOSE_5    34
-#define U300_DMA_GENERAL_PURPOSE_6    35
-#define U300_DMA_GENERAL_PURPOSE_7    36
-#define U300_DMA_GENERAL_PURPOSE_8    37
-#define U300_DMA_UART1_TX             38
-#define U300_DMA_UART1_RX             39
-#define U300_DMA_DEVICE_CHANNELS      32
-#define U300_DMA_CHANNELS             40
-#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
deleted file mode 100644
index 7c3b2b2d25b6..000000000000
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- *
- * include/linux/coh901318.h
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * DMA driver for COH 901 318
- * Author: Per Friden <per.friden@stericsson.com>
- */
-#ifndef COH901318_H
-#define COH901318_H
-#include <linux/device.h>
-#include <linux/dmaengine.h>
-#define MAX_DMA_PACKET_SIZE_SHIFT 11
-#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
-/**
- * struct coh901318_lli - linked list item for DMAC
- * @control: control settings for DMAC
- * @src_addr: transfer source address
- * @dst_addr: transfer destination address
- * @link_addr:  physical address to next lli
- * @virt_link_addr: virtual address of next lli (only used by pool_free)
- * @phy_this: physical address of current lli (only used by pool_free)
- */
-struct coh901318_lli {
-        u32 control;
-        dma_addr_t src_addr;
-        dma_addr_t dst_addr;
-        dma_addr_t link_addr;
-        void *virt_link_addr;
-        dma_addr_t phy_this;
-};
-/**
- * struct coh901318_params - parameters for DMAC configuration
- * @config: DMA config register
- * @ctrl_lli_last: DMA control register for the last lli in the list
- * @ctrl_lli: DMA control register for an lli
- * @ctrl_lli_chained: DMA control register for a chained lli
- */
-struct coh901318_params {
-        u32 config;
-        u32 ctrl_lli_last;
-        u32 ctrl_lli;
-        u32 ctrl_lli_chained;
-};
-/**
- * struct coh_dma_channel - dma channel base
- * @name: ascii name of dma channel
- * @number: channel id number
- * @desc_nbr_max: number of preallocated descriptors
- * @priority_high: prio of channel, 0 low otherwise high.
- * @param: configuration parameters
- * @dev_addr: physical address of periphal connected to channel
- */
-struct coh_dma_channel {
-        const char name[32];
-        const int number;
-        const int desc_nbr_max;
-        const int priority_high;
-        const struct coh901318_params param;
-        const dma_addr_t dev_addr;
-};
-/**
- * dma_access_memory_state_t - register dma for memory access
- *
- * @dev: The dma device
- * @active:  1 means dma intends to access memory
- *           0 means dma wont access memory
- */
-typedef void (*dma_access_memory_state_t)(struct device *dev,
-                                          bool active);
-/**
- * struct powersave - DMA power save structure
- * @lock: lock protecting data in this struct
- * @started_channels: bit mask indicating active dma channels
- */
-struct powersave {
-        spinlock_t lock;
-        u64 started_channels;
-};
-/**
- * struct coh901318_platform - platform arch structure
- * @chans_slave: specifying dma slave channels
- * @chans_memcpy: specifying dma memcpy channels
- * @access_memory_state: requesting DMA memory access (on / off)
- * @chan_conf: dma channel configurations
- * @max_channels: max number of dma chanenls
- */
-struct coh901318_platform {
-        const int *chans_slave;
-        const int *chans_memcpy;
-        const dma_access_memory_state_t access_memory_state;
-        const struct coh_dma_channel *chan_conf;
-        const int max_channels;
-};
-#ifdef CONFIG_COH901318
-/**
- * coh901318_filter_id() - DMA channel filter function
- * @chan: dma channel handle
- * @chan_id: id of dma channel to be filter out
- *
- * In dma_request_channel() it specifies what channel id to be requested
- */
-bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
-#else
-static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
-{
-        return false;
-}
-#endif
-/*
- * DMA Controller - this access the static mappings of the coh901318 dma.
- *
- */
-#define COH901318_MOD32_MASK                                    (0x1F)
-#define COH901318_WORD_MASK                                     (0xFFFFFFFF)
-/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
-#define COH901318_INT_STATUS1                                   (0x0000)
-#define COH901318_INT_STATUS2                                   (0x0004)
-/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_TC_INT_STATUS1                                (0x0008)
-#define COH901318_TC_INT_STATUS2                                (0x000C)
-/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
-#define COH901318_TC_INT_CLEAR1                                 (0x0010)
-#define COH901318_TC_INT_CLEAR2                                 (0x0014)
-/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_RAW_TC_INT_STATUS1                            (0x0018)
-#define COH901318_RAW_TC_INT_STATUS2                            (0x001C)
-/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
-#define COH901318_BE_INT_STATUS1                                (0x0020)
-#define COH901318_BE_INT_STATUS2                                (0x0024)
-/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
-#define COH901318_BE_INT_CLEAR1                                 (0x0028)
-#define COH901318_BE_INT_CLEAR2                                 (0x002C)
-/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
-#define COH901318_RAW_BE_INT_STATUS1                            (0x0030)
-#define COH901318_RAW_BE_INT_STATUS2                            (0x0034)
-/*
- * CX_CFG - Channel Configuration Registers 32bit (R/W)
- */
-#define COH901318_CX_CFG                                        (0x0100)
-#define COH901318_CX_CFG_SPACING                                (0x04)
-/* Channel enable activates tha dma job */
-#define COH901318_CX_CFG_CH_ENABLE                              (0x00000001)
-#define COH901318_CX_CFG_CH_DISABLE                             (0x00000000)
-/* Request Mode */
-#define COH901318_CX_CFG_RM_MASK                                (0x00000006)
-#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY                    (0x0 << 1)
-#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY                   (0x1 << 1)
-#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY                   (0x1 << 1)
-#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY                (0x3 << 1)
-#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY                (0x3 << 1)
-/* Linked channel request field. RM must == 11 */
-#define COH901318_CX_CFG_LCRF_SHIFT                             3
-#define COH901318_CX_CFG_LCRF_MASK                              (0x000001F8)
-#define COH901318_CX_CFG_LCR_DISABLE                            (0x00000000)
-/* Terminal Counter Interrupt Request Mask */
-#define COH901318_CX_CFG_TC_IRQ_ENABLE                          (0x00000200)
-#define COH901318_CX_CFG_TC_IRQ_DISABLE                         (0x00000000)
-/* Bus Error interrupt Mask */
-#define COH901318_CX_CFG_BE_IRQ_ENABLE                          (0x00000400)
-#define COH901318_CX_CFG_BE_IRQ_DISABLE                         (0x00000000)
-/*
- * CX_STAT - Channel Status Registers 32bit (R/-)
- */
-#define COH901318_CX_STAT                                       (0x0200)
-#define COH901318_CX_STAT_SPACING                               (0x04)
-#define COH901318_CX_STAT_RBE_IRQ_IND                           (0x00000008)
-#define COH901318_CX_STAT_RTC_IRQ_IND                           (0x00000004)
-#define COH901318_CX_STAT_ACTIVE                                (0x00000002)
-#define COH901318_CX_STAT_ENABLED                               (0x00000001)
-/*
- * CX_CTRL - Channel Control Registers 32bit (R/W)
- */
-#define COH901318_CX_CTRL                                       (0x0400)
-#define COH901318_CX_CTRL_SPACING                               (0x10)
-/* Transfer Count Enable */
-#define COH901318_CX_CTRL_TC_ENABLE                             (0x00001000)
-#define COH901318_CX_CTRL_TC_DISABLE                            (0x00000000)
-/* Transfer Count Value 0 - 4095 */
-#define COH901318_CX_CTRL_TC_VALUE_MASK                         (0x00000FFF)
-/* Burst count */
-#define COH901318_CX_CTRL_BURST_COUNT_MASK                      (0x0000E000)
-#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES                  (0x7 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES                  (0x6 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES                  (0x5 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES                  (0x4 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES                   (0x3 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES                   (0x2 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES                   (0x1 << 13)
-#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE                    (0x0 << 13)
-/* Source bus size  */
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK                     (0x00030000)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS                  (0x2 << 16)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS                  (0x1 << 16)
-#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS                   (0x0 << 16)
-/* Source address increment */
-#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE                   (0x00040000)
-#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE                  (0x00000000)
-/* Destination Bus Size */
-#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK                     (0x00180000)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS                  (0x2 << 19)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS                  (0x1 << 19)
-#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS                   (0x0 << 19)
-/* Destination address increment */
-#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE                   (0x00200000)
-#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE                  (0x00000000)
-/* Master Mode (Master2 is only connected to MSL) */
-#define COH901318_CX_CTRL_MASTER_MODE_MASK                      (0x00C00000)
-#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W                   (0x3 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W                   (0x2 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M2RW                      (0x1 << 22)
-#define COH901318_CX_CTRL_MASTER_MODE_M1RW                      (0x0 << 22)
-/* Terminal Count flag to PER enable */
-#define COH901318_CX_CTRL_TCP_ENABLE                            (0x01000000)
-#define COH901318_CX_CTRL_TCP_DISABLE                           (0x00000000)
-/* Terminal Count flags to CPU enable */
-#define COH901318_CX_CTRL_TC_IRQ_ENABLE                         (0x02000000)
-#define COH901318_CX_CTRL_TC_IRQ_DISABLE                        (0x00000000)
-/* Hand shake to peripheral */
-#define COH901318_CX_CTRL_HSP_ENABLE                            (0x04000000)
-#define COH901318_CX_CTRL_HSP_DISABLE                           (0x00000000)
-#define COH901318_CX_CTRL_HSS_ENABLE                            (0x08000000)
-#define COH901318_CX_CTRL_HSS_DISABLE                           (0x00000000)
-/* DMA mode */
-#define COH901318_CX_CTRL_DDMA_MASK                             (0x30000000)
-#define COH901318_CX_CTRL_DDMA_LEGACY                           (0x0 << 28)
-#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1                      (0x1 << 28)
-#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2                      (0x2 << 28)
-/* Primary Request Data Destination */
-#define COH901318_CX_CTRL_PRDD_MASK                             (0x40000000)
-#define COH901318_CX_CTRL_PRDD_DEST                             (0x1 << 30)
-#define COH901318_CX_CTRL_PRDD_SOURCE                           (0x0 << 30)
-/*
- * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
- */
-#define COH901318_CX_SRC_ADDR                                   (0x0404)
-#define COH901318_CX_SRC_ADDR_SPACING                           (0x10)
-/*
- * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
- */
-#define COH901318_CX_DST_ADDR                                   (0x0408)
-#define COH901318_CX_DST_ADDR_SPACING                           (0x10)
-/*
- * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
- */
-#define COH901318_CX_LNK_ADDR                                   (0x040C)
-#define COH901318_CX_LNK_ADDR_SPACING                           (0x10)
-#define COH901318_CX_LNK_LINK_IMMEDIATE                         (0x00000001)
-#endif /* COH901318_H */
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
index 29acb718acf7..783e7e60101b 100644
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ b/arch/arm/mach-u300/include/mach/uncompress.h
@@ -43,4 +43,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 02e6659286d5..910698293d64 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -10,9 +10,8 @@
 #include <linux/amba/bus.h>
 #include <linux/spi/spi.h>
 #include <linux/amba/pl022.h>
+#include <linux/platform_data/dma-coh901318.h>
 #include <linux/err.h>
-#include <mach/coh901318.h>
-#include "dma_channels.h"
 /*
 * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 1da10e20e996..d9e73209c9b8 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -349,7 +349,7 @@ static u32 notrace u300_read_sched_clock(void)
 /*
 * This sets up the system timers, clock source and clock event.
 */
-static void __init u300_timer_init(void)
+void __init u300_timer_init(void)
 {
        struct clk *clk;
        unsigned long rate;
@@ -413,11 +413,3 @@ static void __init u300_timer_init(void)
         * used by hrtimers!
         */
 }
-/*
- * Very simple system timer that only register the clock event and
- * clock source.
- */
-struct sys_timer u300_timer = {
-        .init           = u300_timer_init,
-};
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
index b5e9791762e0..d34287bc34f5 100644
--- a/arch/arm/mach-u300/timer.h
+++ b/arch/arm/mach-u300/timer.h
@@ -1 +1 @@
-extern struct sys_timer u300_timer;
+extern void u300_timer_init(void);
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5dea90636d94..3e5bbd0e5b23 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
        select COMMON_CLK
        select PINCTRL
        select PINCTRL_NOMADIK
+        select PINCTRL_ABX500
        select PL310_ERRATA_753970 if CACHE_PL310
 config UX500_SOC_DB8500
@@ -18,6 +19,11 @@ config UX500_SOC_DB8500
        select CPU_FREQ_TABLE if CPU_FREQ
        select MFD_DB8500_PRCMU
        select PINCTRL_DB8500
+        select PINCTRL_DB8540
+        select PINCTRL_AB8500
+        select PINCTRL_AB8505
+        select PINCTRL_AB9540
+        select PINCTRL_AB8540
        select REGULATOR
        select REGULATOR_DB8500_PRCMU
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 1f47d962e3a1..7037d3687e9f 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -13,6 +13,7 @@
 #include <mach/hardware.h>
 #include "board-mop500.h"
+#include "id.h"
 enum mop500_uib {
        STUIB,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index d453522edb0d..b03457881c4b 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -28,7 +28,7 @@
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
 #include <linux/mfd/abx500/ab8500-codec.h>
-#include <linux/leds-lp5521.h>
+#include <linux/platform_data/leds-lp55xx.h>
 #include <linux/input.h>
 #include <linux/smsc911x.h>
 #include <linux/gpio_keys.h>
@@ -40,7 +40,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -90,26 +89,8 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
       },
 };
-static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
+static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
-        .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
-        /* config_reg is the initial configuration of ab8500 pins.
-         * The pins can be configured as GPIO or alt functions based
-         * on value present in GpioSel1 to GpioSel6 and AlternatFunction
-         * register. This is the array of 7 configuration settings.
-         * One has to compile time decide these settings. Below is the
-         * explanation of these setting
-         * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
-         * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
-         * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
-         * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
-         * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
-         * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
-         * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
-         * as GPIO then this register selectes the alternate fucntions
-         */
-        .config_reg             = {0x00, 0x1E, 0x80, 0x01,
-                                        0x7A, 0x00, 0x00},
 };
 /* ab8500-codec */
@@ -215,7 +196,7 @@ static struct platform_device snowball_sbnet_dev = {
        },
 };
-static struct ab8500_platform_data ab8500_platdata = {
+struct ab8500_platform_data ab8500_platdata = {
        .irq_base       = MOP500_AB8500_IRQ_BASE,
        .regulator_reg_init = ab8500_regulator_reg_init,
        .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
@@ -320,7 +301,7 @@ static struct tc3589x_platform_data mop500_tc35892_data = {
        .irq_base       = MOP500_EGPIO_IRQ_BASE,
 };
-static struct lp5521_led_config lp5521_pri_led[] = {
+static struct lp55xx_led_config lp5521_pri_led[] = {
       [0] = {
               .chan_nr = 0,
               .led_current = 0x2f,
@@ -338,14 +319,14 @@ static struct lp5521_led_config lp5521_pri_led[] = {
       },
 };
-static struct lp5521_platform_data __initdata lp5521_pri_data = {
+static struct lp55xx_platform_data __initdata lp5521_pri_data = {
       .label = "lp5521_pri",
       .led_config     = &lp5521_pri_led[0],
       .num_channels   = 3,
-       .clock_mode     = LP5521_CLOCK_EXT,
+       .clock_mode     = LP55XX_CLOCK_EXT,
 };
-static struct lp5521_led_config lp5521_sec_led[] = {
+static struct lp55xx_led_config lp5521_sec_led[] = {
       [0] = {
               .chan_nr = 0,
               .led_current = 0x2f,
@@ -363,11 +344,11 @@ static struct lp5521_led_config lp5521_sec_led[] = {
       },
 };
-static struct lp5521_platform_data __initdata lp5521_sec_data = {
+static struct lp55xx_platform_data __initdata lp5521_sec_data = {
       .label = "lp5521_sec",
       .led_config     = &lp5521_sec_led[0],
       .num_channels   = 3,
-       .clock_mode     = LP5521_CLOCK_EXT,
+       .clock_mode     = LP55XX_CLOCK_EXT,
 };
 static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
@@ -651,6 +632,7 @@ static void __init mop500_init_machine(void)
        int i2c0_devs;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
        mop500_pinmaps_init();
@@ -685,6 +667,7 @@ static void __init snowball_init_machine(void)
        struct device *parent = NULL;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        snowball_pinmaps_init();
        parent = u8500_init_devices(&ab8500_platdata);
@@ -710,6 +693,7 @@ static void __init hrefv60_init_machine(void)
        int i2c0_devs;
        int i;
+        platform_device_register(&db8500_prcmu_device);
        /*
         * The HREFv60 board removed a GPIO expander and routed
         * all these GPIO pins to the internal GPIO controller
@@ -751,8 +735,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
-        .timer          = &ux500_timer,
+        .init_time      = ux500_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = mop500_init_machine,
        .init_late      = ux500_init_late,
 MACHINE_END
@@ -761,8 +744,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
        .atag_offset    = 0x100,
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
-        .timer          = &ux500_timer,
+        .init_time      = ux500_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = mop500_init_machine,
        .init_late      = ux500_init_late,
 MACHINE_END
@@ -772,8 +754,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
-        .timer          = &ux500_timer,
+        .init_time      = ux500_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = hrefv60_init_machine,
        .init_late      = ux500_init_late,
 MACHINE_END
@@ -784,8 +765,7 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
-        .timer          = &ux500_timer,
+        .init_time      = ux500_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = snowball_init_machine,
        .init_late      = NULL,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 75d5b512a3d5..1c1609da76ce 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -10,7 +10,8 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/hardware.h>
-#include <mach/id.h>
+#include "id.h"
 static void __iomem *l2x0_base;
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 5b286e06474c..19235cf7bbe3 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -27,7 +27,6 @@
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -37,7 +36,9 @@
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
+#include "id.h"
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -137,14 +138,9 @@ static struct platform_device db8500_pmu_device = {
        .dev.platform_data      = &db8500_pmu_platdata,
 };
-static struct platform_device db8500_prcmu_device = {
-        .name                   = "db8500-prcmu",
-};
 static struct platform_device *platform_devs[] __initdata = {
        &u8500_dma40_device,
        &db8500_pmu_device,
-        &db8500_prcmu_device,
 };
 static resource_size_t __initdata db8500_gpio_base[] = {
@@ -284,8 +280,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
+                        &db8500_prcmu_pdata),
        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE,
+        OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
                "pinctrl-db8500", NULL),
        /* Requires clock name and DMA bindings. */
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
@@ -341,8 +339,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
-        .timer          = &ux500_timer,
+        .init_time      = ux500_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = u8500_init_machine,
        .init_late      = NULL,
        .dt_compat      = stericsson_dt_platform_compat,
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 721e7b4275f3..537870d3fea8 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -17,9 +17,10 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-ux500.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
@@ -27,6 +28,7 @@
 #include <mach/devices.h>
 #include "board-mop500.h"
+#include "id.h"
 void __iomem *_PRCMU_BASE;
@@ -42,11 +44,6 @@ void __iomem *_PRCMU_BASE;
 * This feels fragile because it depends on the gpio device getting probed
 * _before_ any device uses the gpio interrupts.
 */
-static const struct of_device_id ux500_dt_irq_match[] = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {},
-};
 void __init ux500_init_irq(void)
 {
        void __iomem *dist_base;
@@ -62,7 +59,7 @@ void __init ux500_init_irq(void)
 #ifdef CONFIG_OF
        if (of_have_populated_dt())
-                of_irq_init(ux500_dt_irq_match);
+                irqchip_init();
        else
 #endif
                gic_init(0, 29, dist_base, cpu_base);
@@ -71,13 +68,11 @@ void __init ux500_init_irq(void)
         * Init clocks here so that they are available for system timer
         * initialization.
         */
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_u9540())
                db8500_prcmu_early_init();
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_u9540())
                u8500_clk_init();
-        else if (cpu_is_u9540())
-                u9540_clk_init();
        else if (cpu_is_u8540())
                u8540_clk_init();
 }
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index b54884bd2549..ce9149302cc3 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -40,8 +40,10 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev,
                        goto wfi;
                /* decouple the gic from the A9 cores */
-                if (prcmu_gic_decouple())
+                if (prcmu_gic_decouple()) {
+                        spin_unlock(&master_lock);
                        goto out;
+                }
                /* If an error occur, we will have to recouple the gic
                 * manually */
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 318d49020894..f3d9419f75d3 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -13,11 +13,13 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/platform_data/dma-ste-dma40.h>
+#include <linux/mfd/dbx500-prcmu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
+#include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
 static struct resource dma40_resources[] = {
@@ -194,3 +196,45 @@ struct platform_device u8500_ske_keypad_device = {
        .num_resources = ARRAY_SIZE(keypad_resources),
        .resource = keypad_resources,
 };
+struct prcmu_pdata db8500_prcmu_pdata = {
+        .ab_platdata    = &ab8500_platdata,
+        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
+        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
+};
+static struct resource db8500_prcmu_res[] = {
+        {
+                .name  = "prcmu",
+                .start = U8500_PRCMU_BASE,
+                .end   = U8500_PRCMU_BASE + SZ_8K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "prcmu-tcdm",
+                .start = U8500_PRCMU_TCDM_BASE,
+                .end   = U8500_PRCMU_TCDM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "irq",
+                .start = IRQ_DB8500_PRCMU1,
+                .end   = IRQ_DB8500_PRCMU1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "prcmu-tcpm",
+                .start = U8500_PRCMU_TCPM_BASE,
+                .end   = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device db8500_prcmu_device = {
+        .name                   = "db8500-prcmu",
+        .resource               = db8500_prcmu_res,
+        .num_resources          = ARRAY_SIZE(db8500_prcmu_res),
+        .dev = {
+                .platform_data = &db8500_prcmu_pdata,
+        },
+};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index a5e05f6e256f..dbcb35c48f06 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -14,6 +14,11 @@
 struct ske_keypad_platform_data;
 struct pl022_ssp_controller;
+struct platform_device;
+extern struct ab8500_platform_data ab8500_platdata;
+extern struct prcmu_pdata db8500_prcmu_pdata;
+extern struct platform_device db8500_prcmu_device;
 static inline struct platform_device *
 db8500_add_ske_keypad(struct device *parent,
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index d1579920139f..9f951842e1e5 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -17,6 +17,8 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
+#include "id.h"
 struct dbx500_asic_id dbx500_id;
 static unsigned int ux500_read_asicid(phys_addr_t addr)
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/id.h
index 9c42642ab168..bcc58a8cccbc 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/id.h
@@ -61,9 +61,14 @@ static inline bool __attribute_const__ cpu_is_u8540(void)
        return dbx500_partnumber() == 0x8540;
 }
+static inline bool __attribute_const__ cpu_is_u8580(void)
+{
+        return dbx500_partnumber() == 0x8580;
+}
 static inline bool cpu_is_ux540_family(void)
 {
-        return cpu_is_u9540() || cpu_is_u8540();
+        return cpu_is_u9540() || cpu_is_u8540() || cpu_is_u8580();
 }
 /*
@@ -115,6 +120,20 @@ static inline bool cpu_is_u8500v20_or_later(void)
        return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
+/*
+ * 8540 revisions
+ */
+static inline bool __attribute_const__ cpu_is_u8540v10(void)
+{
+        return cpu_is_u8540() && dbx500_revision() == 0xA0;
+}
+static inline bool __attribute_const__ cpu_is_u8580v10(void)
+{
+        return cpu_is_u8580() && dbx500_revision() == 0xA0;
+}
 static inline bool ux500_is_svp(void)
 {
        return false;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 28d16e744bfd..5201ddace503 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -39,7 +39,6 @@
 #ifndef __ASSEMBLY__
-#include <mach/id.h>
 extern void __iomem *_PRCMU_BASE;
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 7d34c52798b5..d526dd8e87d3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -38,15 +38,7 @@
 #define MOP500_STMPE1601_IRQ_END        \
        MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
-/* AB8500 virtual gpio IRQ */
+#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ_END
-#define AB8500_VIR_GPIO_NR_IRQS                 16
-#define MOP500_AB8500_VIR_GPIO_IRQ_BASE         \
-        MOP500_STMPE1601_IRQ_END
-#define MOP500_AB8500_VIR_GPIO_IRQ_END          \
-        (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS)
-#define MOP500_NR_IRQS          MOP500_AB8500_VIR_GPIO_IRQ_END
 #define MOP500_IRQ_END          MOP500_NR_IRQS
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 6be4c4d2ab88..bddce2b49372 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -28,8 +28,7 @@ extern struct device *ux500_soc_device_init(const char *soc_id);
 struct amba_device;
 extern void __init amba_add_devices(struct amba_device *devs[], int num);
-struct sys_timer;
+extern void ux500_timer_init(void);
-extern struct sys_timer ux500_timer;
 #define __IO_DEV_DESC(x, sz)    {               \
        .virtual        = IO_ADDRESS(x),        \
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index d60ecd1753f0..36969d52e53a 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -54,6 +54,4 @@ static inline void arch_decomp_setup(void)
        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
 }
-#define arch_decomp_wdog() /* nothing to do here */
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 3db7782f3afb..18f7af339dc9 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,14 +16,17 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
+#include "id.h"
 /* This is called from headsmp.S to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
@@ -91,7 +94,7 @@ static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *
         */
        write_pen_release(cpu_logical_map(cpu));
-        smp_send_reschedule(cpu);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
@@ -155,8 +158,6 @@ static void __init ux500_smp_init_cpus(void)
        for (i = 0; i < ncores; i++)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 875309acb022..a6af0b8732ba 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -17,6 +17,8 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include "id.h"
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
                              U8500_TWD_BASE, IRQ_LOCALTIMER);
@@ -46,7 +48,7 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = {
        { },
 };
-static void __init ux500_timer_init(void)
+void __init ux500_timer_init(void)
 {
        void __iomem *mtu_timer_base;
        void __iomem *prcmu_timer_base;
@@ -99,14 +101,3 @@ dt_fail:
        clksrc_dbx500_prcmu_init(prcmu_timer_base);
        ux500_twd_init();
 }
-static void ux500_timer_reset(void)
-{
-        nmdk_clkevt_reset();
-        nmdk_clksrc_reset();
-}
-struct sys_timer ux500_timer = {
-        .init           = ux500_timer_init,
-        .resume         = ux500_timer_reset,
-};
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index 63d8e9f81b99..1dba3688275f 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -25,4 +25,9 @@ config MACH_VERSATILE_DT
          Include support for the ARM(R) Versatile/PB platform,
          using the device tree for discovery
+config MACH_VERSATILE_AUTO
+        def_bool y
+        depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB
+        select MACH_VERSATILE_DT
 endmenu
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 5d5929450366..25160aeaa3b7 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,15 +32,16 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-vic.h>
 #include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
+#include <linux/bitops.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -65,16 +66,28 @@
 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
+/* These PIC IRQs are valid in each configuration */
+#define PIC_VALID_ALL   BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
+                        BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
+                        BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
+                        BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
+                        BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
+                        BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
+                        BIT(SIC_INT_PCI3)
 #if 1
 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 #define IRQ_AACI        IRQ_VICSOURCE24
 #define IRQ_ETH         IRQ_VICSOURCE25
 #define PIC_MASK        0xFFD00000
+#define PIC_VALID       PIC_VALID_ALL
 #else
 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 #define IRQ_AACI        IRQ_SIC_AACI
 #define IRQ_ETH         IRQ_SIC_ETH
 #define PIC_MASK        0
+#define PIC_VALID       PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
+                        BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
+                        BIT(SIC_INT_ETH)
 #endif
 /* Lookup table for finding a DT node that represents the vic instance */
@@ -102,7 +115,7 @@ void __init versatile_init_irq(void)
                                              VERSATILE_SIC_BASE);
        fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                IRQ_VICSOURCE31, ~PIC_MASK, np);
+                IRQ_VICSOURCE31, PIC_VALID, np);
        /*
         * Interrupts on secondary controller from 0 to 8 are routed to
@@ -114,7 +127,7 @@ void __init versatile_init_irq(void)
        writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 }
-static struct map_desc versatile_io_desc[] __initdata = {
+static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
        {
                .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
                .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
@@ -770,7 +783,7 @@ void __init versatile_init(void)
 /*
 * Set up timer interrupt, and return the current time in seconds.
 */
-static void __init versatile_timer_init(void)
+void __init versatile_timer_init(void)
 {
        u32 val;
@@ -797,8 +810,3 @@ static void __init versatile_timer_init(void)
        sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
        sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
 }
-struct sys_timer versatile_timer = {
-        .init           = versatile_timer_init,
-};
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 683e60776a85..5c1b87d1da6b 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -29,7 +29,7 @@ extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
-extern struct sys_timer versatile_timer;
+extern void versatile_timer_init(void);
 extern void versatile_restart(char, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
diff --git a/arch/arm/mach-versatile/include/mach/uncompress.h b/arch/arm/mach-versatile/include/mach/uncompress.h
index 3dd0048afb34..986e3d303f3c 100644
--- a/arch/arm/mach-versatile/include/mach/uncompress.h
+++ b/arch/arm/mach-versatile/include/mach/uncompress.h
@@ -43,4 +43,3 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 2f84f4094f13..e92e5e0705bc 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -327,12 +328,12 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        int irq;
        /* slot,  pin,  irq
-         *  24     1     27
+         *  24     1     IRQ_SIC_PCI0
-         *  25     1     28
+         *  25     1     IRQ_SIC_PCI1
-         *  26     1     29
+         *  26     1     IRQ_SIC_PCI2
-         *  27     1     30
+         *  27     1     IRQ_SIC_PCI3
         */
-        irq = 27 + ((slot - 24 + pin - 1) & 3);
+        irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
        return irq;
 }
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index 98f65493177a..1caef1093793 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -26,7 +26,6 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,8 +38,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = versatile_timer_init,
-        .timer          = &versatile_timer,
        .init_machine   = versatile_init,
        .restart        = versatile_restart,
 MACHINE_END
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index ae5ad3c8f3dd..2558f2e957c3 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -24,7 +24,6 @@
 #include <linux/init.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -46,8 +45,7 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = versatile_timer_init,
-        .timer          = &versatile_timer,
        .init_machine   = versatile_dt_init,
        .dt_compat      = versatile_dt_match,
        .restart        = versatile_restart,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 19738331bd3d..611d140c8695 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -27,7 +27,6 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -107,8 +106,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
        .map_io         = versatile_map_io,
        .init_early     = versatile_init_early,
        .init_irq       = versatile_init_irq,
-        .handle_irq     = vic_handle_irq,
+        .init_time      = versatile_timer_init,
-        .timer          = &versatile_timer,
        .init_machine   = versatile_pb_init,
        .restart        = versatile_restart,
 MACHINE_END
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 60838ddb8564..6f34497a4245 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -10,10 +10,10 @@
 #include <linux/amba/clcd.h>
 #include <linux/clkdev.h>
 #include <linux/vexpress.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
@@ -182,8 +182,6 @@ static void __init ct_ca9x4_init_cpu_map(void)
        for (i = 0; i < ncores; ++i)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index c5d70de9bb4e..dc1ace55d557 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -16,7 +16,6 @@
 #include <linux/vexpress.h>
 #include <asm/smp_scu.h>
-#include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <mach/motherboard.h>
@@ -128,8 +127,6 @@ static void __init vexpress_dt_smp_init_cpus(void)
        for (i = 0; i < ncores; ++i)
                set_cpu_possible(i, true);
-        set_smp_cross_call(gic_raise_softirq);
 }
 static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 011661a6c5cb..915683cb67d6 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -7,6 +7,7 @@
 #include <linux/io.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
@@ -30,7 +31,6 @@
 #include <asm/mach/time.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/timer-sp.h>
 #include <mach/ct-ca9x4.h>
@@ -291,10 +291,6 @@ static void __init v2m_timer_init(void)
        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
 }
-static struct sys_timer v2m_timer = {
-        .init   = v2m_timer_init,
-};
 static void __init v2m_init_early(void)
 {
        if (ct_desc->init_early)
@@ -376,8 +372,7 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .map_io         = v2m_map_io,
        .init_early     = v2m_init_early,
        .init_irq       = v2m_init_irq,
-        .timer          = &v2m_timer,
+        .init_time      = v2m_timer_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = v2m_init,
        .restart        = vexpress_restart,
 MACHINE_END
@@ -434,16 +429,6 @@ void __init v2m_dt_init_early(void)
        }
 }
-static  struct of_device_id vexpress_irq_match[] __initdata = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        {}
-};
-static void __init v2m_dt_init_irq(void)
-{
-        of_irq_init(vexpress_irq_match);
-}
 static void __init v2m_dt_timer_init(void)
 {
        struct device_node *node = NULL;
@@ -468,10 +453,6 @@ static void __init v2m_dt_timer_init(void)
                                24000000);
 }
-static struct sys_timer v2m_dt_timer = {
-        .init = v2m_dt_timer_init,
-};
 static const struct of_device_id v2m_dt_bus_match[] __initconst = {
        { .compatible = "simple-bus", },
        { .compatible = "arm,amba-bus", },
@@ -497,9 +478,8 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .smp            = smp_ops(vexpress_smp_ops),
        .map_io         = v2m_dt_map_io,
        .init_early     = v2m_dt_init_early,
-        .init_irq       = v2m_dt_init_irq,
+        .init_irq       = irqchip_init,
-        .timer          = &v2m_dt_timer,
+        .init_time      = v2m_dt_timer_init,
        .init_machine   = v2m_dt_init,
-        .handle_irq     = gic_handle_irq,
        .restart        = vexpress_restart,
 MACHINE_END
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
new file mode 100644
index 000000000000..8958f0d896bc
--- /dev/null
+++ b/arch/arm/mach-virt/Kconfig
@@ -0,0 +1,10 @@
+config ARCH_VIRT
+        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_GIC
+        select ARM_ARCH_TIMER
+        select ARM_PSCI
+        select HAVE_SMP
+        select CPU_V7
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
new file mode 100644
index 000000000000..042afc1f8c44
--- /dev/null
+++ b/arch/arm/mach-virt/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the linux kernel.
+#
+obj-y                                   := virt.o
+obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
new file mode 100644
index 000000000000..8badaabe70a1
--- /dev/null
+++ b/arch/arm/mach-virt/platsmp.c
@@ -0,0 +1,58 @@
+/*
+ * Dummy Virtual Machine - does what it says on the tin.
+ *
+ * Copyright (C) 2012 ARM Ltd
+ * Author: Will Deacon <will.deacon@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+extern void secondary_startup(void);
+static void __init virt_smp_init_cpus(void)
+{
+}
+static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+static int __cpuinit virt_boot_secondary(unsigned int cpu,
+                                         struct task_struct *idle)
+{
+        if (psci_ops.cpu_on)
+                return psci_ops.cpu_on(cpu_logical_map(cpu),
+                                       __pa(secondary_startup));
+        return -ENODEV;
+}
+static void __cpuinit virt_secondary_init(unsigned int cpu)
+{
+        gic_secondary_init(0);
+}
+struct smp_operations __initdata virt_smp_ops = {
+        .smp_init_cpus          = virt_smp_init_cpus,
+        .smp_prepare_cpus       = virt_smp_prepare_cpus,
+        .smp_secondary_init     = virt_secondary_init,
+        .smp_boot_secondary     = virt_boot_secondary,
+};
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
new file mode 100644
index 000000000000..31666f6b4373
--- /dev/null
+++ b/arch/arm/mach-virt/virt.c
@@ -0,0 +1,54 @@
+/*
+ * Dummy Virtual Machine - does what it says on the tin.
+ *
+ * Copyright (C) 2012 ARM Ltd
+ * Authors: Will Deacon <will.deacon@arm.com>,
+ *          Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/smp.h>
+#include <asm/arch_timer.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+static void __init virt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static void __init virt_timer_init(void)
+{
+        WARN_ON(arch_timer_of_register() != 0);
+        WARN_ON(arch_timer_sched_clock_init() != 0);
+}
+static const char *virt_dt_match[] = {
+        "linux,dummy-virt",
+        NULL
+};
+extern struct smp_operations virt_smp_ops;
+DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
+        .init_irq       = irqchip_init,
+        .init_time      = virt_timer_init,
+        .init_machine   = virt_init,
+        .smp            = smp_ops(virt_smp_ops),
+        .dt_compat      = virt_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2ed0b7d95db6..e3e94b2fa145 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,12 +1,34 @@
 config ARCH_VT8500
-        bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5
+        bool
-        default ARCH_VT8500_SINGLE
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
-        select CPU_ARM926T
+        select CLKSRC_OF
        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
        select HAVE_CLK
+        select VT8500_TIMER
        help
          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+config ARCH_WM8505
+        bool "VIA/Wondermedia 85xx and WM8650"
+        depends on ARCH_MULTI_V5
+        select ARCH_VT8500
+        select CPU_ARM926T
+        help
+config ARCH_WM8750
+        bool "WonderMedia WM8750"
+        depends on ARCH_MULTI_V6
+        select ARCH_VT8500
+        select CPU_V6
+        help
+          Support for WonderMedia WM8750 System-on-Chip.
+config ARCH_WM8850
+        bool "WonderMedia WM8850"
+        depends on ARCH_MULTI_V7
+        select ARCH_VT8500
+        select CPU_V7
+        help
+          Support for WonderMedia WM8850 System-on-Chip.
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index e035251cda48..92ceb2436b60 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o
+obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
index 6f2b843115db..77611a6968d6 100644
--- a/arch/arm/mach-vt8500/common.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -18,7 +18,6 @@
 #include <linux/of.h>
-void __init vt8500_timer_init(void);
 int __init vt8500_irq_init(struct device_node *node,
                                struct device_node *parent);
diff --git a/arch/arm/mach-vt8500/include/mach/timex.h b/arch/arm/mach-vt8500/include/mach/timex.h
deleted file mode 100644
index 8487e4c690b7..000000000000
--- a/arch/arm/mach-vt8500/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/timex.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef MACH_TIMEX_H
-#define MACH_TIMEX_H
-#define CLOCK_TICK_RATE         (3000000)
-#endif /* MACH_TIMEX_H */
diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h
deleted file mode 100644
index e6e81fdaf109..000000000000
--- a/arch/arm/mach-vt8500/include/mach/uncompress.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* arch/arm/mach-vt8500/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Based on arch/arm/mach-dove/include/mach/uncompress.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#define UART0_PHYS      0xd8200000
-#define UART0_ADDR(x)   *(volatile unsigned char *)(UART0_PHYS + x)
-static void putc(const char c)
-{
-        while (UART0_ADDR(0x1c) & 0x2)
-                /* Tx busy, wait and poll */;
-        UART0_ADDR(0) = c;
-}
-static void flush(void)
-{
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
deleted file mode 100644
index 3dd21a47881f..000000000000
--- a/arch/arm/mach-vt8500/timer.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/timer.c
- *
- *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * This file is copied and modified from the original timer.c provided by
- * Alexey Charkov. Minor changes have been made for Device Tree Support.
- */
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/delay.h>
-#include <asm/mach/time.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#define VT8500_TIMER_OFFSET     0x0100
-#define VT8500_TIMER_HZ         3000000
-#define TIMER_MATCH_VAL         0x0000
-#define TIMER_COUNT_VAL         0x0010
-#define TIMER_STATUS_VAL        0x0014
-#define TIMER_IER_VAL           0x001c          /* interrupt enable */
-#define TIMER_CTRL_VAL          0x0020
-#define TIMER_AS_VAL            0x0024          /* access status */
-#define TIMER_COUNT_R_ACTIVE    (1 << 5)        /* not ready for read */
-#define TIMER_COUNT_W_ACTIVE    (1 << 4)        /* not ready for write */
-#define TIMER_MATCH_W_ACTIVE    (1 << 0)        /* not ready for write */
-#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
-static void __iomem *regbase;
-static cycle_t vt8500_timer_read(struct clocksource *cs)
-{
-        int loops = msecs_to_loops(10);
-        writel(3, regbase + TIMER_CTRL_VAL);
-        while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
-                                                && --loops)
-                cpu_relax();
-        return readl(regbase + TIMER_COUNT_VAL);
-}
-static struct clocksource clocksource = {
-        .name           = "vt8500_timer",
-        .rating         = 200,
-        .read           = vt8500_timer_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-static int vt8500_timer_set_next_event(unsigned long cycles,
-                                    struct clock_event_device *evt)
-{
-        int loops = msecs_to_loops(10);
-        cycle_t alarm = clocksource.read(&clocksource) + cycles;
-        while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
-                                                && --loops)
-                cpu_relax();
-        writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
-        if ((signed)(alarm - clocksource.read(&clocksource)) <= 16)
-                return -ETIME;
-        writel(1, regbase + TIMER_IER_VAL);
-        return 0;
-}
-static void vt8500_timer_set_mode(enum clock_event_mode mode,
-                              struct clock_event_device *evt)
-{
-        switch (mode) {
-        case CLOCK_EVT_MODE_RESUME:
-        case CLOCK_EVT_MODE_PERIODIC:
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                writel(readl(regbase + TIMER_CTRL_VAL) | 1,
-                        regbase + TIMER_CTRL_VAL);
-                writel(0, regbase + TIMER_IER_VAL);
-                break;
-        }
-}
-static struct clock_event_device clockevent = {
-        .name           = "vt8500_timer",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_next_event = vt8500_timer_set_next_event,
-        .set_mode       = vt8500_timer_set_mode,
-};
-static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-        writel(0xf, regbase + TIMER_STATUS_VAL);
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-static struct irqaction irq = {
-        .name    = "vt8500_timer",
-        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler = vt8500_timer_interrupt,
-        .dev_id  = &clockevent,
-};
-static struct of_device_id vt8500_timer_ids[] = {
-        { .compatible = "via,vt8500-timer" },
-        { }
-};
-void __init vt8500_timer_init(void)
-{
-        struct device_node *np;
-        int timer_irq;
-        np = of_find_matching_node(NULL, vt8500_timer_ids);
-        if (!np) {
-                pr_err("%s: Timer description missing from Device Tree\n",
-                                                                __func__);
-                return;
-        }
-        regbase = of_iomap(np, 0);
-        if (!regbase) {
-                pr_err("%s: Missing iobase description in Device Tree\n",
-                                                                __func__);
-                of_node_put(np);
-                return;
-        }
-        timer_irq = irq_of_parse_and_map(np, 0);
-        if (!timer_irq) {
-                pr_err("%s: Missing irq description in Device Tree\n",
-                                                                __func__);
-                of_node_put(np);
-                return;
-        }
-        writel(1, regbase + TIMER_CTRL_VAL);
-        writel(0xf, regbase + TIMER_STATUS_VAL);
-        writel(~0, regbase + TIMER_MATCH_VAL);
-        if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-                pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
-                                        __func__, clocksource.name);
-        clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
-        /* copy-pasted from mach-msm; no idea */
-        clockevent.max_delta_ns =
-                clockevent_delta2ns(0xf0000000, &clockevent);
-        clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
-        clockevent.cpumask = cpumask_of(0);
-        if (setup_irq(timer_irq, &irq))
-                pr_err("%s: setup_irq failed for %s\n", __func__,
-                                                        clockevent.name);
-        clockevents_register_device(&clockevent);
-}
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 3c66d48ea082..49e80053d828 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -18,6 +18,7 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/clocksource.h>
 #include <linux/io.h>
 #include <linux/pm.h>
@@ -175,22 +176,20 @@ static void __init vt8500_init_irq(void)
        of_irq_init(vt8500_irq_match);
 };
-static struct sys_timer vt8500_timer = {
-        .init = vt8500_timer_init,
-};
 static const char * const vt8500_dt_compat[] = {
        "via,vt8500",
        "wm,wm8650",
        "wm,wm8505",
+        "wm,wm8750",
+        "wm,wm8850",
 };
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
        .dt_compat      = vt8500_dt_compat,
        .map_io         = vt8500_map_io,
        .init_irq       = vt8500_init_irq,
-        .timer          = &vt8500_timer,
        .init_machine   = vt8500_init,
+        .init_time      = clocksource_of_init,
        .restart        = vt8500_restart,
        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S
index e286daca6827..0ff612ac95ba 100644
--- a/arch/arm/mach-w90x900/include/mach/entry-macro.S
+++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S
@@ -19,8 +19,8 @@
                mov     \base, #AIC_BA
-                ldr     \irqnr, [ \base, #AIC_IPER]
+                ldr     \irqnr, [\base, #AIC_IPER]
-                ldr     \irqnr, [ \base, #AIC_ISNR]
+                ldr     \irqnr, [\base, #AIC_ISNR]
                cmp     \irqnr, #0
        .endm
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 03130212ace2..4b7c324ff664 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -24,8 +24,6 @@
 #include <mach/map.h>
 #include <linux/serial_reg.h>
-#define arch_decomp_wdog()
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
 static volatile u32 * const uart_base = (u32 *)UART0_PA;
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
index b4243e4f1565..92f1c978f35e 100644
--- a/arch/arm/mach-w90x900/mach-nuc910evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -37,6 +37,6 @@ MACHINE_START(W90P910EVB, "W90P910EVB")
        .map_io         = nuc910evb_map_io,
        .init_irq       = nuc900_init_irq,
        .init_machine   = nuc910evb_init,
-        .timer          = &nuc900_timer,
+        .init_time      = nuc900_timer_init,
        .restart        = nuc9xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 500fe5932ce9..26f7189056e3 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -40,6 +40,6 @@ MACHINE_START(W90P950EVB, "W90P950EVB")
        .map_io         = nuc950evb_map_io,
        .init_irq       = nuc900_init_irq,
        .init_machine   = nuc950evb_init,
-        .timer          = &nuc900_timer,
+        .init_time      = nuc900_timer_init,
        .restart        = nuc9xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
index cbb3adc3db10..9b4e73fe10e5 100644
--- a/arch/arm/mach-w90x900/mach-nuc960evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -37,6 +37,6 @@ MACHINE_START(W90N960EVB, "W90N960EVB")
        .map_io         = nuc960evb_map_io,
        .init_irq       = nuc900_init_irq,
        .init_machine   = nuc960evb_init,
-        .timer          = &nuc900_timer,
+        .init_time      = nuc900_timer_init,
        .restart        = nuc9xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 91acb4047793..88ef4b267089 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -15,10 +15,9 @@
 *
 */
 struct map_desc;
-struct sys_timer;
 /* core initialisation functions */
 extern void nuc900_init_irq(void);
-extern struct sys_timer nuc900_timer;
+extern void nuc900_timer_init(void);
 extern void nuc9xx_restart(char, const char *);
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index fa27c498ac09..30fbca844575 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -91,7 +91,6 @@ static int nuc900_clockevent_setnextevent(unsigned long evt,
 static struct clock_event_device nuc900_clockevent_device = {
        .name           = "nuc900-timer0",
-        .shift          = 32,
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_mode       = nuc900_clockevent_setmode,
        .set_next_event = nuc900_clockevent_setnextevent,
@@ -133,15 +132,10 @@ static void __init nuc900_clockevents_init(void)
        __raw_writel(RESETINT, REG_TISR);
        setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
-        nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
-                                        nuc900_clockevent_device.shift);
-        nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
-                                        &nuc900_clockevent_device);
-        nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
-                                        &nuc900_clockevent_device);
        nuc900_clockevent_device.cpumask = cpumask_of(0);
-        clockevents_register_device(&nuc900_clockevent_device);
+        clockevents_config_and_register(&nuc900_clockevent_device, rate,
+                                        0xf, 0xffffffff);
 }
 static void __init nuc900_clocksource_init(void)
@@ -167,12 +161,8 @@ static void __init nuc900_clocksource_init(void)
                TDR_SHIFT, clocksource_mmio_readl_down);
 }
-static void __init nuc900_timer_init(void)
+void __init nuc900_timer_init(void)
 {
        nuc900_clocksource_init();
        nuc900_clockevents_init();
 }
-struct sys_timer nuc900_timer = {
-        .init           = nuc900_timer_init,
-};
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index e16d4bed0f7a..5c8983218183 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -24,6 +24,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
+#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -31,7 +32,6 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "common.h"
@@ -55,19 +55,6 @@ static void __init xilinx_init_machine(void)
        of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
 }
-static struct of_device_id irq_match[] __initdata = {
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { }
-};
-/**
- * xilinx_irq_init() - Interrupt controller initialization for the GIC.
- */
-static void __init xilinx_irq_init(void)
-{
-        of_irq_init(irq_match);
-}
 #define SCU_PERIPH_PHYS         0xF8F00000
 #define SCU_PERIPH_SIZE         SZ_8K
 #define SCU_PERIPH_VIRT         (VMALLOC_END - SCU_PERIPH_SIZE)
@@ -90,16 +77,9 @@ static void __init xilinx_zynq_timer_init(void)
        xilinx_zynq_clocks_init(slcr);
-        xttcpss_timer_init();
+        xttcps_timer_init();
 }
-/*
- * Instantiate and initialize the system timer structure
- */
-static struct sys_timer xttcpss_sys_timer = {
-        .init           = xilinx_zynq_timer_init,
-};
 /**
 * xilinx_map_io() - Create memory mappings needed for early I/O.
 */
@@ -117,9 +97,8 @@ static const char *xilinx_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
        .map_io         = xilinx_map_io,
-        .init_irq       = xilinx_irq_init,
+        .init_irq       = irqchip_init,
-        .handle_irq     = gic_handle_irq,
        .init_machine   = xilinx_init_machine,
-        .timer          = &xttcpss_sys_timer,
+        .init_time      = xilinx_zynq_timer_init,
        .dt_compat      = xilinx_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 954b91c13c91..8b4dbbaa01cf 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,6 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
-void __init xttcpss_timer_init(void);
+void __init xttcps_timer_init(void);
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index de3df283da74..f9fbc9c1e7a6 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -15,39 +15,29 @@
 * GNU General Public License for more details.
 */
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/clocksource.h>
 #include <linux/clockchips.h>
-#include <linux/io.h>
-#include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/slab.h>
 #include <linux/clk-provider.h>
 #include "common.h"
 /*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
-#define XTTCPSS_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
+#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPSS_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
+#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPSS_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
+#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPSS_INTR_VAL_OFFSET         0x24 /* Interval Count Reg, RW */
+#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPSS_MATCH_1_OFFSET          0x30 /* Match 1 Value Reg, RW */
+#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPSS_MATCH_2_OFFSET          0x3C /* Match 2 Value Reg, RW */
+#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-#define XTTCPSS_MATCH_3_OFFSET          0x48 /* Match 3 Value Reg, RW */
-#define XTTCPSS_ISR_OFFSET              0x54 /* Interrupt Status Reg, RO */
+#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-#define XTTCPSS_IER_OFFSET              0x60 /* Interrupt Enable Reg, RW */
+/*
-#define XTTCPSS_CNT_CNTRL_DISABLE_MASK  0x1
+ * Setup the timers to use pre-scaling, using a fixed value for now that will
-/* Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
@@ -57,72 +47,73 @@
 #define CNT_CNTRL_RESET         (1<<4)
 /**
- * struct xttcpss_timer - This definition defines local timer structure
+ * struct xttcps_timer - This definition defines local timer structure
 *
 * @base_addr:  Base address of timer
 **/
-struct xttcpss_timer {
+struct xttcps_timer {
        void __iomem    *base_addr;
 };
-struct xttcpss_timer_clocksource {
+struct xttcps_timer_clocksource {
-        struct xttcpss_timer    xttc;
+        struct xttcps_timer     xttc;
        struct clocksource      cs;
 };
-#define to_xttcpss_timer_clksrc(x) \
+#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcpss_timer_clocksource, cs)
+                container_of(x, struct xttcps_timer_clocksource, cs)
-struct xttcpss_timer_clockevent {
+struct xttcps_timer_clockevent {
-        struct xttcpss_timer            xttc;
+        struct xttcps_timer             xttc;
        struct clock_event_device       ce;
        struct clk                      *clk;
 };
-#define to_xttcpss_timer_clkevent(x) \
+#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcpss_timer_clockevent, ce)
+                container_of(x, struct xttcps_timer_clockevent, ce)
 /**
- * xttcpss_set_interval - Set the timer interval value
+ * xttcps_set_interval - Set the timer interval value
 *
 * @timer:      Pointer to the timer instance
 * @cycles:     Timer interval ticks
 **/
-static void xttcpss_set_interval(struct xttcpss_timer *timer,
+static void xttcps_set_interval(struct xttcps_timer *timer,
                                        unsigned long cycles)
 {
        u32 ctrl_reg;
        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-        /* Reset the counter (0x10) so that it starts from 0, one-shot
+        /*
-           mode makes this needed for timing to be right. */
+         * Reset the counter (0x10) so that it starts from 0, one-shot
+         * mode makes this needed for timing to be right.
+         */
        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 }
 /**
- * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcpss_timer instance
+ * @dev_id:     void pointer to the xttcps_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
-static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
 {
-        struct xttcpss_timer_clockevent *xttce = dev_id;
+        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
        /* Acknowledge the interrupt and call event handler */
-        __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-                        timer->base_addr + XTTCPSS_ISR_OFFSET);
        xttce->ce.event_handler(&xttce->ce);
@@ -136,46 +127,46 @@ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
 **/
 static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 {
-        struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
+        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPSS_COUNT_VAL_OFFSET);
+                                XTTCPS_COUNT_VAL_OFFSET);
 }
 /**
- * xttcpss_set_next_event - Sets the time interval for next event
+ * xttcps_set_next_event - Sets the time interval for next event
 *
 * @cycles:     Timer interval ticks
 * @evt:        Address of clock event instance
 *
 * returns: Always 0 - success
 **/
-static int xttcpss_set_next_event(unsigned long cycles,
+static int xttcps_set_next_event(unsigned long cycles,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
-        xttcpss_set_interval(timer, cycles);
+        xttcps_set_interval(timer, cycles);
        return 0;
 }
 /**
- * xttcpss_set_mode - Sets the mode of timer
+ * xttcps_set_mode - Sets the mode of timer
 *
 * @mode:       Mode to be set
 * @evt:        Address of clock event instance
 **/
-static void xttcpss_set_mode(enum clock_event_mode mode,
+static void xttcps_set_mode(enum clock_event_mode mode,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcpss_timer *timer = &xttce->xttc;
+        struct xttcps_timer *timer = &xttce->xttc;
        u32 ctrl_reg;
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                xttcpss_set_interval(timer,
+                xttcps_set_interval(timer,
                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
                                                       PRESCALE * HZ));
                break;
@@ -183,17 +174,17 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPSS_CNT_CNTRL_OFFSET);
+                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
                break;
        case CLOCK_EVT_MODE_RESUME:
                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPSS_CNT_CNTRL_OFFSET);
+                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
                break;
        }
 }
@@ -201,7 +192,7 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
 static void __init zynq_ttc_setup_clocksource(struct device_node *np,
                                             void __iomem *base)
 {
-        struct xttcpss_timer_clocksource *ttccs;
+        struct xttcps_timer_clocksource *ttccs;
        struct clk *clk;
        int err;
        u32 reg;
@@ -230,11 +221,11 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np,
        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
        if (WARN_ON(err))
@@ -244,7 +235,7 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np,
 static void __init zynq_ttc_setup_clockevent(struct device_node *np,
                                            void __iomem *base)
 {
-        struct xttcpss_timer_clockevent *ttcce;
+        struct xttcps_timer_clockevent *ttcce;
        int err, irq;
        u32 reg;
@@ -272,17 +263,18 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np,
        ttcce->ce.name = np->name;
        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcpss_set_next_event;
+        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcpss_set_mode;
+        ttcce->ce.set_mode = xttcps_set_mode;
        ttcce->ce.rating = 200;
        ttcce->ce.irq = irq;
+        ttcce->ce.cpumask = cpu_possible_mask;
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-        err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
+        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
                          np->name, ttcce);
        if (WARN_ON(err))
                return;
@@ -301,12 +293,12 @@ static const __initconst struct of_device_id zynq_ttc_match[] = {
 };
 /**
- * xttcpss_timer_init - Initialize the timer
+ * xttcps_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
-void __init xttcpss_timer_init(void)
+void __init xttcps_timer_init(void)
 {
        struct device_node *np;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 8defd638c79e..cb812a13e299 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -636,8 +636,9 @@ config ARM_THUMBEE
          make use of it. Say N for code that can run on CPUs without ThumbEE.
 config ARM_VIRT_EXT
-        bool "Native support for the ARM Virtualization Extensions"
+        bool
-        depends on MMU && CPU_V7
+        depends on MMU
+        default y if CPU_V7
        help
          Enable the kernel to make use of the ARM Virtualization
          Extensions to install hypervisors without run-time firmware
@@ -647,11 +648,6 @@ config ARM_VIRT_EXT
          use of this feature.  Refer to Documentation/arm/Booting for
          details.
-          It is safe to enable this option even if the kernel may not be
-          booted in HYP mode, may not have support for the
-          virtualization extensions, or may be booted with a
-          non-compliant bootloader.
 config SWP_EMULATE
        bool "Emulate SWP/SWPB instructions"
        depends on !CPU_USE_DOMAINS && CPU_V7
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 8a9c4cb50a93..4e333fa2756f 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -6,7 +6,7 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
                                   iomap.o
 obj-$(CONFIG_MMU)               += fault-armv.o flush.o idmap.o ioremap.o \
-                                   mmap.o pgd.o mmu.o vmregion.o
+                                   mmap.o pgd.o mmu.o
 ifneq ($(CONFIG_MMU),y)
 obj-y                           += nommu.o
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index feeb3eaccb1c..6f4585b89078 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -749,7 +749,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        unsigned long instr = 0, instrptr;
        int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
        unsigned int type;
-        mm_segment_t fs;
        unsigned int fault;
        u16 tinstr = 0;
        int isize = 4;
@@ -760,16 +759,15 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        instrptr = instruction_pointer(regs);
-        fs = get_fs();
-        set_fs(KERNEL_DS);
        if (thumb_mode(regs)) {
-                fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
+                u16 *ptr = (u16 *)(instrptr & ~1);
+                fault = probe_kernel_address(ptr, tinstr);
                if (!fault) {
                        if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
                            IS_T32(tinstr)) {
                                /* Thumb-2 32-bit */
                                u16 tinst2 = 0;
-                                fault = __get_user(tinst2, (u16 *)(instrptr+2));
+                                fault = probe_kernel_address(ptr + 1, tinst2);
                                instr = (tinstr << 16) | tinst2;
                                thumb2_32b = 1;
                        } else {
@@ -778,8 +776,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                        }
                }
        } else
-                fault = __get_user(instr, (u32 *)instrptr);
+                fault = probe_kernel_address(instrptr, instr);
-        set_fs(fs);
        if (fault) {
                type = TYPE_FAULT;
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7539ec275065..15451ee4acc8 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -19,6 +19,52 @@
 #include "proc-macros.S"
 /*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+ENTRY(v7_invalidate_l1)
+       mov     r0, #0
+       mcr     p15, 2, r0, c0, c0, 0
+       mrc     p15, 1, r0, c0, c0, 0
+       ldr     r1, =0x7fff
+       and     r2, r1, r0, lsr #13
+       ldr     r1, =0x3ff
+       and     r3, r1, r0, lsr #3      @ NumWays - 1
+       add     r2, r2, #1              @ NumSets
+       and     r0, r0, #0x7
+       add     r0, r0, #4      @ SetShift
+       clz     r1, r3          @ WayShift
+       add     r4, r3, #1      @ NumWays
+1:     sub     r2, r2, #1      @ NumSets--
+       mov     r3, r4          @ Temp = NumWays
+2:     subs    r3, r3, #1      @ Temp--
+       mov     r5, r3, lsl r1
+       mov     r6, r2, lsl r0
+       orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+       mcr     p15, 0, r5, c7, c6, 2
+       bgt     2b
+       cmp     r2, #0
+       bgt     1b
+       dsb
+       isb
+       mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+/*
 *      v7_flush_icache_all()
 *
 *      Flush the whole I-cache.
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index bc4a5e9ebb78..7a0511191f6b 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -34,6 +34,9 @@
 * The ASID is used to tag entries in the CPU caches and TLBs.
 * The context ID is used by debuggers and trace logic, and
 * should be unique within all running processes.
+ *
+ * In big endian operation, the two 32 bit words are swapped if accesed by
+ * non 64-bit operations.
 */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
 #define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 076c26d43864..c7e3759f16d3 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -186,13 +186,24 @@ static u64 get_coherent_dma_mask(struct device *dev)
 static void __dma_clear_buffer(struct page *page, size_t size)
 {
-        void *ptr;
        /*
         * Ensure that the allocated pages are zeroed, and that any data
         * lurking in the kernel direct-mapped region is invalidated.
         */
-        ptr = page_address(page);
+        if (PageHighMem(page)) {
-        if (ptr) {
+                phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
+                phys_addr_t end = base + size;
+                while (size > 0) {
+                        void *ptr = kmap_atomic(page);
+                        memset(ptr, 0, PAGE_SIZE);
+                        dmac_flush_range(ptr, ptr + PAGE_SIZE);
+                        kunmap_atomic(ptr);
+                        page++;
+                        size -= PAGE_SIZE;
+                }
+                outer_flush_range(base, end);
+        } else {
+                void *ptr = page_address(page);
                memset(ptr, 0, size);
                dmac_flush_range(ptr, ptr + size);
                outer_flush_range(__pa(ptr), __pa(ptr) + size);
@@ -243,7 +254,8 @@ static void __dma_free_buffer(struct page *page, size_t size)
 #endif
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
-                                     pgprot_t prot, struct page **ret_page);
+                                     pgprot_t prot, struct page **ret_page,
+                                     const void *caller);
 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
                                 pgprot_t prot, struct page **ret_page,
@@ -346,10 +358,11 @@ static int __init atomic_pool_init(void)
                goto no_pages;
        if (IS_ENABLED(CONFIG_CMA))
-                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
+                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
+                                              atomic_pool_init);
        else
                ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
-                                           &page, NULL);
+                                           &page, atomic_pool_init);
        if (ptr) {
                int i;
@@ -542,27 +555,41 @@ static int __free_from_pool(void *start, size_t size)
 }
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
-                                     pgprot_t prot, struct page **ret_page)
+                                     pgprot_t prot, struct page **ret_page,
+                                     const void *caller)
 {
        unsigned long order = get_order(size);
        size_t count = size >> PAGE_SHIFT;
        struct page *page;
+        void *ptr;
        page = dma_alloc_from_contiguous(dev, count, order);
        if (!page)
                return NULL;
        __dma_clear_buffer(page, size);
-        __dma_remap(page, size, prot);
+        if (PageHighMem(page)) {
+                ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
+                if (!ptr) {
+                        dma_release_from_contiguous(dev, page, count);
+                        return NULL;
+                }
+        } else {
+                __dma_remap(page, size, prot);
+                ptr = page_address(page);
+        }
        *ret_page = page;
-        return page_address(page);
+        return ptr;
 }
 static void __free_from_contiguous(struct device *dev, struct page *page,
-                                   size_t size)
+                                   void *cpu_addr, size_t size)
 {
-        __dma_remap(page, size, pgprot_kernel);
+        if (PageHighMem(page))
+                __dma_free_remap(cpu_addr, size);
+        else
+                __dma_remap(page, size, pgprot_kernel);
        dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
 }
@@ -583,9 +610,9 @@ static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
 #define __get_dma_pgprot(attrs, prot)   __pgprot(0)
 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c)      NULL
 #define __alloc_from_pool(size, ret_page)                       NULL
-#define __alloc_from_contiguous(dev, size, prot, ret)           NULL
+#define __alloc_from_contiguous(dev, size, prot, ret, c)        NULL
 #define __free_from_pool(cpu_addr, size)                        0
-#define __free_from_contiguous(dev, page, size)                 do { } while (0)
+#define __free_from_contiguous(dev, page, cpu_addr, size)       do { } while (0)
 #define __dma_free_remap(cpu_addr, size)                        do { } while (0)
 #endif  /* CONFIG_MMU */
@@ -640,12 +667,12 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
        if (is_coherent || nommu())
                addr = __alloc_simple_buffer(dev, size, gfp, &page);
-        else if (gfp & GFP_ATOMIC)
+        else if (!(gfp & __GFP_WAIT))
                addr = __alloc_from_pool(size, &page);
        else if (!IS_ENABLED(CONFIG_CMA))
                addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
        else
-                addr = __alloc_from_contiguous(dev, size, prot, &page);
+                addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
        if (addr)
                *handle = pfn_to_dma(dev, page_to_pfn(page));
@@ -739,7 +766,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
                 * Non-atomic allocations cannot be freed with IRQs disabled
                 */
                WARN_ON(irqs_disabled());
-                __free_from_contiguous(dev, page, size);
+                __free_from_contiguous(dev, page, cpu_addr, size);
        }
 }
@@ -1002,6 +1029,9 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
        unsigned int count, start;
        unsigned long flags;
+        if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
+                order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
        count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
                 (1 << mapping->order) - 1) >> mapping->order;
@@ -1068,12 +1098,17 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
                return pages;
        }
+        /*
+         * IOMMU can map any pages, so himem can also be used here
+         */
+        gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
        while (count) {
                int j, order = __fls(count);
-                pages[i] = alloc_pages(gfp | __GFP_NOWARN, order);
+                pages[i] = alloc_pages(gfp, order);
                while (!pages[i] && order)
-                        pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order);
+                        pages[i] = alloc_pages(gfp, --order);
                if (!pages[i])
                        goto error;
@@ -1257,11 +1292,11 @@ err_mapping:
        return NULL;
 }
-static void __iommu_free_atomic(struct device *dev, struct page **pages,
+static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
                                dma_addr_t handle, size_t size)
 {
        __iommu_remove_mapping(dev, handle, size);
-        __free_from_pool(page_address(pages[0]), size);
+        __free_from_pool(cpu_addr, size);
 }
 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
@@ -1344,7 +1379,7 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
        }
        if (__in_atomic_pool(cpu_addr, size)) {
-                __iommu_free_atomic(dev, pages, handle, size);
+                __iommu_free_atomic(dev, cpu_addr, handle, size);
                return;
        }
@@ -1732,6 +1767,8 @@ struct dma_map_ops iommu_ops = {
        .unmap_sg               = arm_iommu_unmap_sg,
        .sync_sg_for_cpu        = arm_iommu_sync_sg_for_cpu,
        .sync_sg_for_device     = arm_iommu_sync_sg_for_device,
+        .set_dma_mask           = arm_dma_set_mask,
 };
 struct dma_map_ops iommu_coherent_ops = {
@@ -1745,6 +1782,8 @@ struct dma_map_ops iommu_coherent_ops = {
        .map_sg         = arm_coherent_iommu_map_sg,
        .unmap_sg       = arm_coherent_iommu_unmap_sg,
+        .set_dma_mask   = arm_dma_set_mask,
 };
 /**
@@ -1799,6 +1838,7 @@ err2:
 err:
        return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
 static void release_iommu_mapping(struct kref *kref)
 {
@@ -1815,6 +1855,7 @@ void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
        if (mapping)
                kref_put(&mapping->kref, release_iommu_mapping);
 }
+EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
 /**
 * arm_iommu_attach_device
@@ -1843,5 +1884,32 @@ int arm_iommu_attach_device(struct device *dev,
        pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
        return 0;
 }
+EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
+/**
+ * arm_iommu_detach_device
+ * @dev: valid struct device pointer
+ *
+ * Detaches the provided device from a previously attached map.
+ * This voids the dma operations (dma_map_ops pointer)
+ */
+void arm_iommu_detach_device(struct device *dev)
+{
+        struct dma_iommu_mapping *mapping;
+        mapping = to_dma_iommu_mapping(dev);
+        if (!mapping) {
+                dev_warn(dev, "Not attached\n");
+                return;
+        }
+        iommu_detach_device(mapping->domain, dev);
+        kref_put(&mapping->kref, release_iommu_mapping);
+        mapping = NULL;
+        set_dma_ops(dev, NULL);
+        pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
+}
+EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
 #endif
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 99db769307ec..2dffc010cc41 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -1,4 +1,6 @@
+#include <linux/module.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <asm/cputype.h>
 #include <asm/idmap.h>
@@ -6,6 +8,7 @@
 #include <asm/pgtable.h>
 #include <asm/sections.h>
 #include <asm/system_info.h>
+#include <asm/virt.h>
 pgd_t *idmap_pgd;
@@ -59,11 +62,17 @@ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
        } while (pud++, addr = next, addr != end);
 }
-static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
+static void identity_mapping_add(pgd_t *pgd, const char *text_start,
+                                 const char *text_end, unsigned long prot)
 {
-        unsigned long prot, next;
+        unsigned long addr, end;
+        unsigned long next;
+        addr = virt_to_phys(text_start);
+        end = virt_to_phys(text_end);
+        prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
-        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF;
        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
                prot |= PMD_BIT4;
@@ -74,28 +83,52 @@ static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long e
        } while (pgd++, addr = next, addr != end);
 }
+#if defined(CONFIG_ARM_VIRT_EXT) && defined(CONFIG_ARM_LPAE)
+pgd_t *hyp_pgd;
+extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
+static int __init init_static_idmap_hyp(void)
+{
+        hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        if (!hyp_pgd)
+                return -ENOMEM;
+        pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n",
+                __hyp_idmap_text_start, __hyp_idmap_text_end);
+        identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
+                             __hyp_idmap_text_end, PMD_SECT_AP1);
+        return 0;
+}
+#else
+static int __init init_static_idmap_hyp(void)
+{
+        return 0;
+}
+#endif
 extern char  __idmap_text_start[], __idmap_text_end[];
 static int __init init_static_idmap(void)
 {
-        phys_addr_t idmap_start, idmap_end;
+        int ret;
        idmap_pgd = pgd_alloc(&init_mm);
        if (!idmap_pgd)
                return -ENOMEM;
-        /* Add an identity mapping for the physical address of the section. */
+        pr_info("Setting up static identity map for 0x%p - 0x%p\n",
-        idmap_start = virt_to_phys((void *)__idmap_text_start);
+                __idmap_text_start, __idmap_text_end);
-        idmap_end = virt_to_phys((void *)__idmap_text_end);
+        identity_mapping_add(idmap_pgd, __idmap_text_start,
+                             __idmap_text_end, 0);
-        pr_info("Setting up static identity map for 0x%llx - 0x%llx\n",
+        ret = init_static_idmap_hyp();
-                (long long)idmap_start, (long long)idmap_end);
-        identity_mapping_add(idmap_pgd, idmap_start, idmap_end);
        /* Flush L1 for the hardware to see this page table content */
        flush_cache_louis();
-        return 0;
+        return ret;
 }
 early_initcall(init_static_idmap);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 88fd86cf3d9a..04d9006eab1f 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -39,6 +39,70 @@
 #include <asm/mach/pci.h>
 #include "mm.h"
+LIST_HEAD(static_vmlist);
+static struct static_vm *find_static_vm_paddr(phys_addr_t paddr,
+                        size_t size, unsigned int mtype)
+{
+        struct static_vm *svm;
+        struct vm_struct *vm;
+        list_for_each_entry(svm, &static_vmlist, list) {
+                vm = &svm->vm;
+                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                        continue;
+                if ((vm->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
+                        continue;
+                if (vm->phys_addr > paddr ||
+                        paddr + size - 1 > vm->phys_addr + vm->size - 1)
+                        continue;
+                return svm;
+        }
+        return NULL;
+}
+struct static_vm *find_static_vm_vaddr(void *vaddr)
+{
+        struct static_vm *svm;
+        struct vm_struct *vm;
+        list_for_each_entry(svm, &static_vmlist, list) {
+                vm = &svm->vm;
+                /* static_vmlist is ascending order */
+                if (vm->addr > vaddr)
+                        break;
+                if (vm->addr <= vaddr && vm->addr + vm->size > vaddr)
+                        return svm;
+        }
+        return NULL;
+}
+void __init add_static_vm_early(struct static_vm *svm)
+{
+        struct static_vm *curr_svm;
+        struct vm_struct *vm;
+        void *vaddr;
+        vm = &svm->vm;
+        vm_area_add_early(vm);
+        vaddr = vm->addr;
+        list_for_each_entry(curr_svm, &static_vmlist, list) {
+                vm = &curr_svm->vm;
+                if (vm->addr > vaddr)
+                        break;
+        }
+        list_add_tail(&svm->list, &curr_svm->list);
+}
 int ioremap_page(unsigned long virt, unsigned long phys,
                 const struct mem_type *mtype)
 {
@@ -197,13 +261,14 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        const struct mem_type *type;
        int err;
        unsigned long addr;
-        struct vm_struct * area;
+        struct vm_struct *area;
+        phys_addr_t paddr = __pfn_to_phys(pfn);
 #ifndef CONFIG_ARM_LPAE
        /*
         * High mappings must be supersection aligned
         */
-        if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
+        if (pfn >= 0x100000 && (paddr & ~SUPERSECTION_MASK))
                return NULL;
 #endif
@@ -219,24 +284,16 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        /*
         * Try to reuse one of the static mapping whenever possible.
         */
-        read_lock(&vmlist_lock);
+        if (size && !(sizeof(phys_addr_t) == 4 && pfn >= 0x100000)) {
-        for (area = vmlist; area; area = area->next) {
+                struct static_vm *svm;
-                if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
-                        break;
+                svm = find_static_vm_paddr(paddr, size, mtype);
-                if (!(area->flags & VM_ARM_STATIC_MAPPING))
+                if (svm) {
-                        continue;
+                        addr = (unsigned long)svm->vm.addr;
-                if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
+                        addr += paddr - svm->vm.phys_addr;
-                        continue;
+                        return (void __iomem *) (offset + addr);
-                if (__phys_to_pfn(area->phys_addr) > pfn ||
+                }
-                    __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
-                        continue;
-                /* we can drop the lock here as we know *area is static */
-                read_unlock(&vmlist_lock);
-                addr = (unsigned long)area->addr;
-                addr += __pfn_to_phys(pfn) - area->phys_addr;
-                return (void __iomem *) (offset + addr);
        }
-        read_unlock(&vmlist_lock);
        /*
         * Don't allow RAM to be mapped - this causes problems with ARMv6+
@@ -248,21 +305,21 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        if (!area)
                return NULL;
        addr = (unsigned long)area->addr;
-        area->phys_addr = __pfn_to_phys(pfn);
+        area->phys_addr = paddr;
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
        if (DOMAIN_IO == 0 &&
            (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
               cpu_is_xsc3()) && pfn >= 0x100000 &&
-               !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
+               !((paddr | size | addr) & ~SUPERSECTION_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
                err = remap_area_supersections(addr, pfn, size, type);
-        } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
+        } else if (!((paddr | size | addr) & ~PMD_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
                err = remap_area_sections(addr, pfn, size, type);
        } else
 #endif
-                err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
+                err = ioremap_page_range(addr, addr + size, paddr,
                                         __pgprot(type->prot_pte));
        if (err) {
@@ -346,34 +403,28 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
 void __iounmap(volatile void __iomem *io_addr)
 {
        void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
-        struct vm_struct *vm;
+        struct static_vm *svm;
+        /* If this is a static mapping, we must leave it alone */
+        svm = find_static_vm_vaddr(addr);
+        if (svm)
+                return;
-        read_lock(&vmlist_lock);
-        for (vm = vmlist; vm; vm = vm->next) {
-                if (vm->addr > addr)
-                        break;
-                if (!(vm->flags & VM_IOREMAP))
-                        continue;
-                /* If this is a static mapping we must leave it alone */
-                if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
-                    (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
-                        read_unlock(&vmlist_lock);
-                        return;
-                }
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
+        {
+                struct vm_struct *vm;
+                vm = find_vm_area(addr);
                /*
                 * If this is a section based mapping we need to handle it
                 * specially as the VM subsystem does not know how to handle
                 * such a beast.
                 */
-                if ((vm->addr == addr) &&
+                if (vm && (vm->flags & VM_ARM_SECTION_MAPPING))
-                    (vm->flags & VM_ARM_SECTION_MAPPING)) {
                        unmap_area_sections((unsigned long)vm->addr, vm->size);
-                        break;
-                }
-#endif
        }
-        read_unlock(&vmlist_lock);
+#endif
        vunmap(addr);
 }
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index a8ee92da3544..d5a4e9ad8f0f 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,4 +1,6 @@
 #ifdef CONFIG_MMU
+#include <linux/list.h>
+#include <linux/vmalloc.h>
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
@@ -65,6 +67,16 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 /* consistent regions used by dma_alloc_attrs() */
 #define VM_ARM_DMA_CONSISTENT   0x20000000
+struct static_vm {
+        struct vm_struct vm;
+        struct list_head list;
+};
+extern struct list_head static_vmlist;
+extern struct static_vm *find_static_vm_vaddr(void *vaddr);
+extern __init void add_static_vm_early(struct static_vm *svm);
 #endif
 #ifdef CONFIG_ZONE_DMA
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 7c347bcc9421..c6d45c87540e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -57,6 +57,9 @@ static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
 static unsigned int ecc_mask __initdata = 0;
 pgprot_t pgprot_user;
 pgprot_t pgprot_kernel;
+pgprot_t pgprot_hyp_device;
+pgprot_t pgprot_s2;
+pgprot_t pgprot_s2_device;
 EXPORT_SYMBOL(pgprot_user);
 EXPORT_SYMBOL(pgprot_kernel);
@@ -66,34 +69,46 @@ struct cachepolicy {
        unsigned int    cr_mask;
        pmdval_t        pmd;
        pteval_t        pte;
+        pteval_t        pte_s2;
 };
+#ifdef CONFIG_ARM_LPAE
+#define s2_policy(policy)       policy
+#else
+#define s2_policy(policy)       0
+#endif
 static struct cachepolicy cache_policies[] __initdata = {
        {
                .policy         = "uncached",
                .cr_mask        = CR_W|CR_C,
                .pmd            = PMD_SECT_UNCACHED,
                .pte            = L_PTE_MT_UNCACHED,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
        }, {
                .policy         = "buffered",
                .cr_mask        = CR_C,
                .pmd            = PMD_SECT_BUFFERED,
                .pte            = L_PTE_MT_BUFFERABLE,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
        }, {
                .policy         = "writethrough",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WT,
                .pte            = L_PTE_MT_WRITETHROUGH,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
        }, {
                .policy         = "writeback",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WB,
                .pte            = L_PTE_MT_WRITEBACK,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
        }, {
                .policy         = "writealloc",
                .cr_mask        = 0,
                .pmd            = PMD_SECT_WBWA,
                .pte            = L_PTE_MT_WRITEALLOC,
+                .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
        }
 };
@@ -327,6 +342,7 @@ static void __init build_mem_type_table(void)
        struct cachepolicy *cp;
        unsigned int cr = get_cr();
        pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
+        pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
        int cpu_arch = cpu_architecture();
        int i;
@@ -438,6 +454,8 @@ static void __init build_mem_type_table(void)
         */
        cp = &cache_policies[cachepolicy];
        vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+        s2_pgprot = cp->pte_s2;
+        hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
        /*
         * ARMv6 and above have extended page tables.
@@ -461,6 +479,7 @@ static void __init build_mem_type_table(void)
                        user_pgprot |= L_PTE_SHARED;
                        kern_pgprot |= L_PTE_SHARED;
                        vecs_pgprot |= L_PTE_SHARED;
+                        s2_pgprot |= L_PTE_SHARED;
                        mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
                        mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
                        mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
@@ -515,6 +534,9 @@ static void __init build_mem_type_table(void)
        pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
        pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
                                 L_PTE_DIRTY | kern_pgprot);
+        pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
+        pgprot_s2_device  = __pgprot(s2_device_pgprot);
+        pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
        mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
        mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
@@ -774,21 +796,24 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 {
        struct map_desc *md;
        struct vm_struct *vm;
+        struct static_vm *svm;
        if (!nr)
                return;
-        vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
+        svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
        for (md = io_desc; nr; md++, nr--) {
                create_mapping(md);
+                vm = &svm->vm;
                vm->addr = (void *)(md->virtual & PAGE_MASK);
                vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
                vm->phys_addr = __pfn_to_phys(md->pfn);
                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
                vm->flags |= VM_ARM_MTYPE(md->type);
                vm->caller = iotable_init;
-                vm_area_add_early(vm++);
+                add_static_vm_early(svm++);
        }
 }
@@ -796,13 +821,16 @@ void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
                                  void *caller)
 {
        struct vm_struct *vm;
+        struct static_vm *svm;
+        svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
-        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+        vm = &svm->vm;
        vm->addr = (void *)addr;
        vm->size = size;
        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
        vm->caller = caller;
-        vm_area_add_early(vm);
+        add_static_vm_early(svm);
 }
 #ifndef CONFIG_ARM_LPAE
@@ -827,14 +855,13 @@ static void __init pmd_empty_section_gap(unsigned long addr)
 static void __init fill_pmd_gaps(void)
 {
+        struct static_vm *svm;
        struct vm_struct *vm;
        unsigned long addr, next = 0;
        pmd_t *pmd;
-        /* we're still single threaded hence no lock needed here */
+        list_for_each_entry(svm, &static_vmlist, list) {
-        for (vm = vmlist; vm; vm = vm->next) {
+                vm = &svm->vm;
-                if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
-                        continue;
                addr = (unsigned long)vm->addr;
                if (addr < next)
                        continue;
@@ -874,19 +901,12 @@ static void __init fill_pmd_gaps(void)
 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 static void __init pci_reserve_io(void)
 {
-        struct vm_struct *vm;
+        struct static_vm *svm;
-        unsigned long addr;
-        /* we're still single threaded hence no lock needed here */
+        svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
-        for (vm = vmlist; vm; vm = vm->next) {
+        if (svm)
-                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                return;
-                        continue;
-                addr = (unsigned long)vm->addr;
-                addr &= ~(SZ_2M - 1);
-                if (addr == PCI_IO_VIRT_BASE)
-                        return;
-        }
        vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 }
 #else
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index eb6aa73bc8b7..f9a0aa725ea9 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -38,9 +38,14 @@
 /*
 * mmid - get context id from mm pointer (mm->context.id)
+ * note, this field is 64bit, so in big-endian the two words are swapped too.
 */
        .macro  mmid, rd, rn
+#ifdef __ARMEB__
+        ldr     \rd, [\rn, #MM_CONTEXT_ID + 4 ]
+#else
        ldr     \rd, [\rn, #MM_CONTEXT_ID]
+#endif
        .endm
 /*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 09c5233f4dfc..bcaaa8de9325 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -101,7 +101,7 @@ ENTRY(cpu_v6_dcache_clean_area)
 ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 6d98c13ab827..78f520bc0e99 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -40,7 +40,7 @@
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 7b56386f9496..50bf1dafc9ea 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -47,7 +47,7 @@
 */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        mmid    r1, r1                          @ get mm->context.id
        and     r3, r1, #0xff
        mov     r3, r3, lsl #(48 - 32)          @ ASID
        mcrr    p15, 0, r0, r3, c2              @ set TTB 0
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
deleted file mode 100644
index a631016e1f8f..000000000000
--- a/arch/arm/mm/vmregion.c
+++ /dev/null
@@ -1,205 +0,0 @@
-#include <linux/fs.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-#include "vmregion.h"
-/*
- * VM region handling support.
- *
- * This should become something generic, handling VM region allocations for
- * vmalloc and similar (ioremap, module space, etc).
- *
- * I envisage vmalloc()'s supporting vm_struct becoming:
- *
- *  struct vm_struct {
- *    struct vmregion   region;
- *    unsigned long     flags;
- *    struct page       **pages;
- *    unsigned int      nr_pages;
- *    unsigned long     phys_addr;
- *  };
- *
- * get_vm_area() would then call vmregion_alloc with an appropriate
- * struct vmregion head (eg):
- *
- *  struct vmregion vmalloc_head = {
- *      .vm_list        = LIST_HEAD_INIT(vmalloc_head.vm_list),
- *      .vm_start       = VMALLOC_START,
- *      .vm_end         = VMALLOC_END,
- *  };
- *
- * However, vmalloc_head.vm_start is variable (typically, it is dependent on
- * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
- * would have to initialise this each time prior to calling vmregion_alloc().
- */
-struct arm_vmregion *
-arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
-                   size_t size, gfp_t gfp, const void *caller)
-{
-        unsigned long start = head->vm_start, addr = head->vm_end;
-        unsigned long flags;
-        struct arm_vmregion *c, *new;
-        if (head->vm_end - head->vm_start < size) {
-                printk(KERN_WARNING "%s: allocation too big (requested %#x)\n",
-                        __func__, size);
-                goto out;
-        }
-        new = kmalloc(sizeof(struct arm_vmregion), gfp);
-        if (!new)
-                goto out;
-        new->caller = caller;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        addr = rounddown(addr - size, align);
-        list_for_each_entry_reverse(c, &head->vm_list, vm_list) {
-                if (addr >= c->vm_end)
-                        goto found;
-                addr = rounddown(c->vm_start - size, align);
-                if (addr < start)
-                        goto nospc;
-        }
- found:
-        /*
-         * Insert this entry after the one we found.
-         */
-        list_add(&new->vm_list, &c->vm_list);
-        new->vm_start = addr;
-        new->vm_end = addr + size;
-        new->vm_active = 1;
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return new;
- nospc:
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        kfree(new);
- out:
-        return NULL;
-}
-static struct arm_vmregion *__arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        list_for_each_entry(c, &head->vm_list, vm_list) {
-                if (c->vm_active && c->vm_start == addr)
-                        goto out;
-        }
-        c = NULL;
- out:
-        return c;
-}
-struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        c = __arm_vmregion_find(head, addr);
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return c;
-}
-struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *head, unsigned long addr)
-{
-        struct arm_vmregion *c;
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        c = __arm_vmregion_find(head, addr);
-        if (c)
-                c->vm_active = 0;
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        return c;
-}
-void arm_vmregion_free(struct arm_vmregion_head *head, struct arm_vmregion *c)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&head->vm_lock, flags);
-        list_del(&c->vm_list);
-        spin_unlock_irqrestore(&head->vm_lock, flags);
-        kfree(c);
-}
-#ifdef CONFIG_PROC_FS
-static int arm_vmregion_show(struct seq_file *m, void *p)
-{
-        struct arm_vmregion *c = list_entry(p, struct arm_vmregion, vm_list);
-        seq_printf(m, "0x%08lx-0x%08lx %7lu", c->vm_start, c->vm_end,
-                c->vm_end - c->vm_start);
-        if (c->caller)
-                seq_printf(m, " %pS", (void *)c->caller);
-        seq_putc(m, '\n');
-        return 0;
-}
-static void *arm_vmregion_start(struct seq_file *m, loff_t *pos)
-{
-        struct arm_vmregion_head *h = m->private;
-        spin_lock_irq(&h->vm_lock);
-        return seq_list_start(&h->vm_list, *pos);
-}
-static void *arm_vmregion_next(struct seq_file *m, void *p, loff_t *pos)
-{
-        struct arm_vmregion_head *h = m->private;
-        return seq_list_next(p, &h->vm_list, pos);
-}
-static void arm_vmregion_stop(struct seq_file *m, void *p)
-{
-        struct arm_vmregion_head *h = m->private;
-        spin_unlock_irq(&h->vm_lock);
-}
-static const struct seq_operations arm_vmregion_ops = {
-        .start  = arm_vmregion_start,
-        .stop   = arm_vmregion_stop,
-        .next   = arm_vmregion_next,
-        .show   = arm_vmregion_show,
-};
-static int arm_vmregion_open(struct inode *inode, struct file *file)
-{
-        struct arm_vmregion_head *h = PDE(inode)->data;
-        int ret = seq_open(file, &arm_vmregion_ops);
-        if (!ret) {
-                struct seq_file *m = file->private_data;
-                m->private = h;
-        }
-        return ret;
-}
-static const struct file_operations arm_vmregion_fops = {
-        .open   = arm_vmregion_open,
-        .read   = seq_read,
-        .llseek = seq_lseek,
-        .release = seq_release,
-};
-int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h)
-{
-        proc_create_data(path, S_IRUSR, NULL, &arm_vmregion_fops, h);
-        return 0;
-}
-#else
-int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h)
-{
-        return 0;
-}
-#endif
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
deleted file mode 100644
index 0f5a5f2a2c7b..000000000000
--- a/arch/arm/mm/vmregion.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef VMREGION_H
-#define VMREGION_H
-#include <linux/spinlock.h>
-#include <linux/list.h>
-struct page;
-struct arm_vmregion_head {
-        spinlock_t              vm_lock;
-        struct list_head        vm_list;
-        unsigned long           vm_start;
-        unsigned long           vm_end;
-};
-struct arm_vmregion {
-        struct list_head        vm_list;
-        unsigned long           vm_start;
-        unsigned long           vm_end;
-        int                     vm_active;
-        const void              *caller;
-};
-struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t, const void *);
-struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
-struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
-void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
-int arm_vmregion_create_proc(const char *, struct arm_vmregion_head *);
-#endif
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index a34f1e214116..6828ef6ce80e 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
 static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
 {
-        emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
+        /* r_dst = (r_src << 8) | (r_src >> 8) */
-        emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
+        emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
-        emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
+        emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
-        emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
+        /*
+         * we need to mask out the bits set in r_dst[23:16] due to
+         * the first shift instruction.
+         *
+         * note that 0x8ff is the encoded immediate 0x00ff0000.
+         */
+        emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
 }
 #else  /* ARMv6+ */
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index cbfbbe461788..837a2d52e9db 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -156,14 +156,9 @@ void __init iop_init_time(unsigned long tick_rate)
        write_tmr0(timer_ctl & ~IOP_TMR_EN);
        write_tisr(1);
        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
-        clockevents_calc_mult_shift(&iop_clockevent,
-                                    tick_rate, IOP_MIN_RANGE);
-        iop_clockevent.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &iop_clockevent);
-        iop_clockevent.min_delta_ns =
-                clockevent_delta2ns(0xf, &iop_clockevent);
        iop_clockevent.cpumask = cpumask_of(0);
-        clockevents_register_device(&iop_clockevent);
+        clockevents_config_and_register(&iop_clockevent, tick_rate,
+                                        0xf, 0xfffffffe);
        /*
         * Set up free-running clocksource timer 1.
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 665870dce3c8..ce66eb9be481 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -5,36 +5,6 @@ menu "TI OMAP Common Features"
 config ARCH_OMAP_OTG
        bool
-choice
-        prompt "OMAP System Type"
-        default ARCH_OMAP2PLUS
-config ARCH_OMAP1
-        bool "TI OMAP1"
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select GENERIC_IRQ_CHIP
-        select HAVE_IDE
-        select IRQ_DOMAIN
-        select NEED_MACH_IO_H if PCCARD
-        select NEED_MACH_MEMORY_H
-        help
-          "Systems based on omap7xx, omap15xx or omap16xx"
-config ARCH_OMAP2PLUS
-        bool "TI OMAP2/3/4"
-        select CLKDEV_LOOKUP
-        select GENERIC_IRQ_CHIP
-        select OMAP_DM_TIMER
-        select PINCTRL
-        select PROC_DEVICETREE if PROC_FS
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
-endchoice
 comment "OMAP Feature Selections"
 config OMAP_DEBUG_DEVICES
@@ -118,7 +88,7 @@ config OMAP_MUX_WARNINGS
 config OMAP_MBOX_FWK
        tristate "Mailbox framework support"
-        depends on ARCH_OMAP
+        depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
        help
          Say Y here if you want to use OMAP Mailbox framework support for
          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
@@ -177,15 +147,6 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
        help
          PPA routine service ID for setting L2 auxiliary control register.
-config OMAP_32K_TIMER_HZ
-        int "Kernel internal timer frequency for 32KHz timer"
-        range 32 1024
-        depends on OMAP_32K_TIMER
-        default "128"
-        help
-          Kernel internal timer frequency should be a divisor of 32768,
-          such as 64 or 128.
 config OMAP_DM_TIMER
        bool "Use dual-mode timer"
        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a14a78a2f149..31199417b56a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include
 # Common support
 obj-y := sram.o dma.o counter_32k.o
 obj-m :=
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 4136b20cba3c..e06c34bdc34a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2019,7 +2019,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
        errata                  = p->errata;
        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
-                        && (omap_dma_reserve_channels <= dma_lch_count))
+                        && (omap_dma_reserve_channels < d->lch_count))
                d->lch_count    = omap_dma_reserve_channels;
        dma_lch_count           = d->lch_count;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 7b433f3bddca..a0daa2fb5de6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -808,11 +808,9 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
                return  -ENOMEM;
        }
-        timer->io_base = devm_request_and_ioremap(dev, mem);
+        timer->io_base = devm_ioremap_resource(dev, mem);
-        if (!timer->io_base) {
+        if (IS_ERR(timer->io_base))
-                dev_err(dev, "%s: region already claimed.\n", __func__);
+                return PTR_ERR(timer->io_base);
-                return -ENOMEM;
-        }
        if (dev->of_node) {
                if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index f9df624d108c..58213d9714cd 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -68,7 +68,7 @@ __setup("i2c_bus=", omap_i2c_bus_setup);
 * Register busses defined in command line but that are not registered with
 * omap_register_i2c_bus from board initialization code.
 */
-static int __init omap_register_i2c_bus_cmdline(void)
+int __init omap_register_i2c_bus_cmdline(void)
 {
        int i, err = 0;
@@ -83,7 +83,6 @@ static int __init omap_register_i2c_bus_cmdline(void)
 out:
        return err;
 }
-subsys_initcall(omap_register_i2c_bus_cmdline);
 /**
 * omap_register_i2c_bus - register I2C bus with device descriptors
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7a9028cb5a75..810629d79668 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -32,6 +32,7 @@ int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
                                 struct i2c_board_info const *info,
                                 unsigned len);
+extern int omap_register_i2c_bus_cmdline(void);
 #else
 static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
                                 struct i2c_board_info const *info,
@@ -39,6 +40,11 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 {
        return 0;
 }
+static inline int omap_register_i2c_bus_cmdline(void)
+{
+        return 0;
+}
 #endif
 struct omap_hwmod;
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..e27d2daa7790 100644
--- a/arch/arm/plat-omap/include/plat/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
@@ -28,14 +28,6 @@
 #if !defined(__ASM_ARCH_OMAP_TIMEX_H)
 #define __ASM_ARCH_OMAP_TIMEX_H
-/*
- * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
- * and that's why the CLOCK_TICK_RATE is not 32768.
- */
-#ifdef CONFIG_OMAP_32K_TIMER
-#define CLOCK_TICK_RATE         (CONFIG_OMAP_32K_TIMER_HZ)
-#else
 #define CLOCK_TICK_RATE         (HZ * 100000UL)
-#endif
 #endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index e686fe76a96b..7310bcfb299f 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -49,7 +49,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
                                        "number (%u)\n", num);
                        continue;
                }
-                if (variant_mask & !(*mpp_list & variant_mask)) {
+                if (variant_mask && !(*mpp_list & variant_mask)) {
                        printk(KERN_WARNING
                               "orion_mpp_conf: requested MPP%u config "
                               "unavailable on this hardware\n", num);
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 0f4fa863dd55..5d5ac0f05422 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 static struct clock_event_device orion_clkevt = {
        .name           = "orion_tick",
        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-        .shift          = 32,
        .rating         = 300,
        .set_next_event = orion_clkevt_next_event,
        .set_mode       = orion_clkevt_mode,
@@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
         * Setup clockevent timer (interrupt-driven).
         */
        setup_irq(irq, &orion_timer_irq);
-        orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
-        orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
-        orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
        orion_clkevt.cpumask = cpumask_of(0);
-        clockevents_register_device(&orion_clkevt);
+        clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
 }
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
deleted file mode 100644
index eef3b6a2f8a8..000000000000
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-config PLAT_S3C24XX
-        bool
-        depends on ARCH_S3C24XX
-        default y
-        select ARCH_REQUIRE_GPIOLIB
-        select NO_IOPORT
-        select S3C_DEV_NAND
-        help
-          Base platform code for any Samsung S3C24XX device
-if PLAT_S3C24XX
-# low-level serial option nodes
-config CPU_LLSERIAL_S3C2410_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
-config CPU_LLSERIAL_S3C2440_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
-config CPU_LLSERIAL_S3C2410
-        bool
-        help
-          Selected if there is an S3C2410 (or register compatible) serial
-          low-level implementation needed
-config CPU_LLSERIAL_S3C2440
-        bool
-        help
-          Selected if there is an S3C2440 (or register compatible) serial
-          low-level implementation needed
-# code that is shared between a number of the s3c24xx implementations
-config S3C2410_CLOCK
-        bool
-        help
-          Clock code for the S3C2410, and similar processors which
-          is currently includes the S3C2410, S3C2440, S3C2442.
-config S3C24XX_DCLK
-        bool
-        help
-          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-# gpio configurations
-config S3C24XX_GPIO_EXTRA
-        int
-        default 128 if S3C24XX_GPIO_EXTRA128
-        default 64 if S3C24XX_GPIO_EXTRA64
-        default 16 if ARCH_H1940
-        default 0
-config S3C24XX_GPIO_EXTRA64
-        bool
-        help
-          Add an extra 64 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-config S3C24XX_GPIO_EXTRA128
-        bool
-        help
-          Add an extra 128 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-config S3C24XX_DMA
-        bool "S3C2410 DMA support"
-        depends on ARCH_S3C24XX
-        select S3C_DMA
-        help
-          S3C2410 DMA support. This is needed for drivers like sound which
-          use the S3C2410's DMA system to move data to and from the
-          peripheral blocks.
-config S3C2410_DMA_DEBUG
-        bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C24XX && S3C2410_DMA
-        help
-          Enable debugging output for the DMA code. This option sends info
-          to the kernel log, at priority KERN_DEBUG.
-# common code for s3c24xx based machines, such as the SMDKs.
-# cpu frequency items common between s3c2410 and s3c2440/s3c2442
-config S3C2410_IOTIMING
-        bool
-        depends on CPU_FREQ_S3C24XX
-        help
-          Internal node to select io timing code that is common to the s3c2410
-          and s3c2440/s3c2442 cpu frequency support.
-config S3C2410_CPUFREQ_UTILS
-        bool
-        depends on CPU_FREQ_S3C24XX
-        help
-          Internal node to select timing code that is common to the s3c2410
-          and s3c2440/s3c244 cpu frequency support.
-# cpu frequency support common to s3c2412, s3c2413 and s3c2442
-config S3C2412_IOTIMING
-        bool
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
-        help
-          Intel node to select io timing code that is common to the s3c2412
-          and the s3c2443.
-endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
deleted file mode 100644
index 9f60549c8da1..000000000000
--- a/arch/arm/plat-s3c24xx/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-# arch/arm/plat-s3c24xx/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-# Core files
-obj-y                           += irq.o
-obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpu-freq.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
-# Architecture dependent builds
-obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
-obj-$(CONFIG_S3C24XX_DMA)       += dma.o
-obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
-obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
-obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
deleted file mode 100644
index fe57bbbf166b..000000000000
--- a/arch/arm/plat-s3c24xx/irq.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <plat/regs-irqtype.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-static void
-s3c_irq_mask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - IRQ_EINT0;
-        unsigned long mask;
-        mask = __raw_readl(S3C2410_INTMSK);
-        mask |= 1UL << irqno;
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-static inline void
-s3c_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-static inline void
-s3c_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-static void
-s3c_irq_unmask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq;
-        unsigned long mask;
-        if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
-                irqdbf2("s3c_irq_unmask %d\n", irqno);
-        irqno -= IRQ_EINT0;
-        mask = __raw_readl(S3C2410_INTMSK);
-        mask &= ~(1UL << irqno);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-struct irq_chip s3c_irq_level_chip = {
-        .name           = "s3c-level",
-        .irq_ack        = s3c_irq_maskack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-struct irq_chip s3c_irq_chip = {
-        .name           = "s3c",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-static void
-s3c_irqext_mask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - EXTINT_OFF;
-        unsigned long mask;
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        mask |= ( 1UL << irqno);
-        __raw_writel(mask, S3C24XX_EINTMASK);
-}
-static void
-s3c_irqext_ack(struct irq_data *data)
-{
-        unsigned long req;
-        unsigned long bit;
-        unsigned long mask;
-        bit = 1UL << (data->irq - EXTINT_OFF);
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        __raw_writel(bit, S3C24XX_EINTPEND);
-        req = __raw_readl(S3C24XX_EINTPEND);
-        req &= ~mask;
-        /* not sure if we should be acking the parent irq... */
-        if (data->irq <= IRQ_EINT7) {
-                if ((req & 0xf0) == 0)
-                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
-        } else {
-                if ((req >> 8) == 0)
-                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
-        }
-}
-static void
-s3c_irqext_unmask(struct irq_data *data)
-{
-        unsigned int irqno = data->irq - EXTINT_OFF;
-        unsigned long mask;
-        mask = __raw_readl(S3C24XX_EINTMASK);
-        mask &= ~(1UL << irqno);
-        __raw_writel(mask, S3C24XX_EINTMASK);
-}
-int
-s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-        unsigned long newvalue = 0, value;
-        if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->irq - IRQ_EINT0) * 2;
-                extint_offset = (data->irq - IRQ_EINT0) * 4;
-        } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
-                extint_offset = (data->irq - (EXTINT_OFF)) * 4;
-        } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
-                extint_offset = (data->irq - IRQ_EINT8) * 4;
-        } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
-                extint_offset = (data->irq - IRQ_EINT16) * 4;
-        } else {
-                return -1;
-        }
-        /* Set the GPIO to external interrupt mode */
-        value = __raw_readl(gpcon_reg);
-        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-        __raw_writel(value, gpcon_reg);
-        /* Set the external interrupt to pointed trigger type */
-        switch (type)
-        {
-                case IRQ_TYPE_NONE:
-                        printk(KERN_WARNING "No edge setting!\n");
-                        break;
-                case IRQ_TYPE_EDGE_RISING:
-                        newvalue = S3C2410_EXTINT_RISEEDGE;
-                        break;
-                case IRQ_TYPE_EDGE_FALLING:
-                        newvalue = S3C2410_EXTINT_FALLEDGE;
-                        break;
-                case IRQ_TYPE_EDGE_BOTH:
-                        newvalue = S3C2410_EXTINT_BOTHEDGE;
-                        break;
-                case IRQ_TYPE_LEVEL_LOW:
-                        newvalue = S3C2410_EXTINT_LOWLEV;
-                        break;
-                case IRQ_TYPE_LEVEL_HIGH:
-                        newvalue = S3C2410_EXTINT_HILEV;
-                        break;
-                default:
-                        printk(KERN_ERR "No such irq type %d", type);
-                        return -1;
-        }
-        value = __raw_readl(extint_reg);
-        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-        __raw_writel(value, extint_reg);
-        return 0;
-}
-static struct irq_chip s3c_irqext_chip = {
-        .name           = "s3c-ext",
-        .irq_mask       = s3c_irqext_mask,
-        .irq_unmask     = s3c_irqext_unmask,
-        .irq_ack        = s3c_irqext_ack,
-        .irq_set_type   = s3c_irqext_type,
-        .irq_set_wake   = s3c_irqext_wake
-};
-static struct irq_chip s3c_irq_eint0t4 = {
-        .name           = "s3c-ext0",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-/* mask values for the parent registers for each of the interrupt types */
-#define INTMSK_UART0     (1UL << (IRQ_UART0 - IRQ_EINT0))
-#define INTMSK_UART1     (1UL << (IRQ_UART1 - IRQ_EINT0))
-#define INTMSK_UART2     (1UL << (IRQ_UART2 - IRQ_EINT0))
-#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
-/* UART0 */
-static void
-s3c_irq_uart0_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
-}
-static void
-s3c_irq_uart0_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART0);
-}
-static void
-s3c_irq_uart0_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
-}
-static struct irq_chip s3c_irq_uart0 = {
-        .name           = "s3c-uart0",
-        .irq_mask       = s3c_irq_uart0_mask,
-        .irq_unmask     = s3c_irq_uart0_unmask,
-        .irq_ack        = s3c_irq_uart0_ack,
-};
-/* UART1 */
-static void
-s3c_irq_uart1_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
-}
-static void
-s3c_irq_uart1_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART1);
-}
-static void
-s3c_irq_uart1_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
-}
-static struct irq_chip s3c_irq_uart1 = {
-        .name           = "s3c-uart1",
-        .irq_mask       = s3c_irq_uart1_mask,
-        .irq_unmask     = s3c_irq_uart1_unmask,
-        .irq_ack        = s3c_irq_uart1_ack,
-};
-/* UART2 */
-static void
-s3c_irq_uart2_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
-}
-static void
-s3c_irq_uart2_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_UART2);
-}
-static void
-s3c_irq_uart2_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
-}
-static struct irq_chip s3c_irq_uart2 = {
-        .name           = "s3c-uart2",
-        .irq_mask       = s3c_irq_uart2_mask,
-        .irq_unmask     = s3c_irq_uart2_unmask,
-        .irq_ack        = s3c_irq_uart2_ack,
-};
-/* ADC and Touchscreen */
-static void
-s3c_irq_adc_mask(struct irq_data *d)
-{
-        s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
-}
-static void
-s3c_irq_adc_unmask(struct irq_data *d)
-{
-        s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
-}
-static void
-s3c_irq_adc_ack(struct irq_data *d)
-{
-        s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
-}
-static struct irq_chip s3c_irq_adc = {
-        .name           = "s3c-adc",
-        .irq_mask       = s3c_irq_adc_mask,
-        .irq_unmask     = s3c_irq_adc_unmask,
-        .irq_ack        = s3c_irq_adc_ack,
-};
-/* irq demux for adc */
-static void s3c_irq_demux_adc(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-        unsigned int offset = 9;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        subsrc &= ~submsk;
-        subsrc >>= offset;
-        subsrc &= 3;
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_TC);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_ADC);
-                }
-        }
-}
-static void s3c_irq_demux_uart(unsigned int start)
-{
-        unsigned int subsrc, submsk;
-        unsigned int offset = start - IRQ_S3CUART_RX0;
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-        irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
-                start, offset, subsrc, submsk);
-        subsrc &= ~submsk;
-        subsrc >>= offset;
-        subsrc &= 7;
-        if (subsrc != 0) {
-                if (subsrc & 1)
-                        generic_handle_irq(start);
-                if (subsrc & 2)
-                        generic_handle_irq(start+1);
-                if (subsrc & 4)
-                        generic_handle_irq(start+2);
-        }
-}
-/* uart demux entry points */
-static void
-s3c_irq_demux_uart0(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX0);
-}
-static void
-s3c_irq_demux_uart1(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX1);
-}
-static void
-s3c_irq_demux_uart2(unsigned int irq,
-                    struct irq_desc *desc)
-{
-        irq = irq;
-        s3c_irq_demux_uart(IRQ_S3CUART_RX2);
-}
-static void
-s3c_irq_demux_extint8(unsigned int irq,
-                      struct irq_desc *desc)
-{
-        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
-        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
-        eintpnd &= ~eintmsk;
-        eintpnd &= ~0xff;       /* ignore lower irqs */
-        /* we may as well handle all the pending IRQs here */
-        while (eintpnd) {
-                irq = __ffs(eintpnd);
-                eintpnd &= ~(1<<irq);
-                irq += (IRQ_EINT4 - 4);
-                generic_handle_irq(irq);
-        }
-}
-static void
-s3c_irq_demux_extint4t7(unsigned int irq,
-                        struct irq_desc *desc)
-{
-        unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
-        unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
-        eintpnd &= ~eintmsk;
-        eintpnd &= 0xff;        /* only lower irqs */
-        /* we may as well handle all the pending IRQs here */
-        while (eintpnd) {
-                irq = __ffs(eintpnd);
-                eintpnd &= ~(1<<irq);
-                irq += (IRQ_EINT4 - 4);
-                generic_handle_irq(irq);
-        }
-}
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- */
-int s3c24xx_set_fiq(unsigned int irq, bool on)
-{
-        u32 intmod;
-        unsigned offs;
-        if (on) {
-                offs = irq - FIQ_START;
-                if (offs > 31)
-                        return -EINVAL;
-                intmod = 1 << offs;
-        } else {
-                intmod = 0;
-        }
-        __raw_writel(intmod, S3C2410_INTMOD);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
-void __init s3c24xx_init_irq(void)
-{
-        unsigned long pend;
-        unsigned long last;
-        int irqno;
-        int i;
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-        irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
-        /* first, clear all interrupts pending... */
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C24XX_EINTPEND);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C24XX_EINTPEND);
-                printk("irq: clearing pending ext status %08x\n", (int)pend);
-                last = pend;
-        }
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2410_INTPND);
-                if (pend == 0 || pend == last)
-                        break;
-                __raw_writel(pend, S3C2410_SRCPND);
-                __raw_writel(pend, S3C2410_INTPND);
-                printk("irq: clearing pending status %08x\n", (int)pend);
-                last = pend;
-        }
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(S3C2410_SUBSRCPND);
-                if (pend == 0 || pend == last)
-                        break;
-                printk("irq: clearing subpending status %08x\n", (int)pend);
-                __raw_writel(pend, S3C2410_SUBSRCPND);
-                last = pend;
-        }
-        /* register the main interrupts */
-        irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
-        for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
-                /* set all the s3c2410 internal irqs */
-                switch (irqno) {
-                        /* deal with the special IRQs (cascaded) */
-                case IRQ_EINT4t7:
-                case IRQ_EINT8t23:
-                case IRQ_UART0:
-                case IRQ_UART1:
-                case IRQ_UART2:
-                case IRQ_ADCPARENT:
-                        irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
-                                                 handle_level_irq);
-                        break;
-                case IRQ_RESERVED6:
-                case IRQ_RESERVED24:
-                        /* no IRQ here */
-                        break;
-                default:
-                        //irqdbf("registering irq %d (s3c irq)\n", irqno);
-                        irq_set_chip_and_handler(irqno, &s3c_irq_chip,
-                                                 handle_edge_irq);
-                        set_irq_flags(irqno, IRQF_VALID);
-                }
-        }
-        /* setup the cascade irq handlers */
-        irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
-        irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
-        irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
-        irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
-        irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
-        irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
-        /* external interrupts */
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irqdbf("registering irq %d (ext int)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
-                irqdbf("registering irq %d (extended s3c irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        /* register the uart interrupts */
-        irqdbf("s3c2410: registering external interrupts\n");
-        for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
-                irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
-                irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
-                irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
-                irqdbf("registering irq %d (s3c adc irq)\n", irqno);
-                irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-        irqdbf("s3c2410: registered interrupt handlers\n");
-}
-struct syscore_ops s3c24xx_irq_syscore_ops = {
-        .suspend        = s3c24xx_irq_suspend,
-        .resume         = s3c24xx_irq_resume,
-};
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 2d676ab50f73..ca07cb1b155a 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -386,11 +386,9 @@ static int s3c_adc_probe(struct platform_device *pdev)
                return -ENXIO;
        }
-        adc->regs = devm_request_and_ioremap(dev, regs);
+        adc->regs = devm_ioremap_resource(dev, regs);
-        if (!adc->regs) {
+        if (IS_ERR(adc->regs))
-                dev_err(dev, "failed to map registers\n");
+                return PTR_ERR(adc->regs);
-                return -ENXIO;
-        }
        ret = regulator_enable(adc->vdd);
        if (ret)
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index d088afa034e8..71d58ddea9c1 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -19,7 +19,8 @@
 #include <mach/dma.h>
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
-                                struct samsung_dma_req *param)
+                                struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name)
 {
        dma_cap_mask_t mask;
        void *filter_param;
@@ -33,7 +34,12 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
         */
        filter_param = (dma_ch == DMACH_DT_PROP) ?
                (void *)param->dt_dmach_prop : (void *)dma_ch;
-        return (unsigned)dma_request_channel(mask, pl330_filter, filter_param);
+        if (dev->of_node)
+                return (unsigned)dma_request_slave_channel(dev, ch_name);
+        else
+                return (unsigned)dma_request_channel(mask, pl330_filter,
+                                                        filter_param);
 }
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
index b258a08de591..2fc89315553f 100644
--- a/arch/arm/plat-samsung/include/plat/adc.h
+++ b/arch/arm/plat-samsung/include/plat/adc.h
@@ -15,6 +15,7 @@
 #define __ASM_PLAT_ADC_H __FILE__
 struct s3c_adc_client;
+struct platform_device;
 extern int s3c_adc_start(struct s3c_adc_client *client,
                         unsigned int channel, unsigned int nr_samples);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index b69e11dc679d..37703ef6dfc7 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -194,8 +194,7 @@ extern void s3c24xx_init_uartdevs(char *name,
 /* timer for 2410/2440 */
-struct sys_timer;
+extern void s3c24xx_timer_init(void);
-extern struct sys_timer s3c24xx_timer;
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
index 207e275362a8..f3a9cff6d5d4 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -14,12 +14,12 @@
 /* The S5PV210/S5PC110 implementations are as belows. */
        .macro fifo_level_s5pv210 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S5PV210_UFSTAT_TXMASK
        .endm
        .macro  fifo_full_s5pv210 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S5PV210_UFSTAT_TXFULL
        .endm
@@ -27,7 +27,7 @@
 * most widely re-used */
        .macro fifo_level_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
        .endm
@@ -36,7 +36,7 @@
 #endif
        .macro  fifo_full_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
                tst     \rd, #S3C2440_UFSTAT_TXFULL
        .endm
@@ -45,11 +45,11 @@
 #endif
        .macro  senduart,rd,rx
-                strb    \rd, [\rx, # S3C2410_UTXH ]
+                strb    \rd, [\rx, # S3C2410_UTXH]
        .endm
        .macro  busyuart, rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                ldr     \rd, [\rx, # S3C2410_UFCON]
                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
                beq     1001f                           @
                @ FIFO enabled...
@@ -60,7 +60,7 @@
 1001:
                @ busy waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UTRSTAT]
                tst     \rd, #S3C2410_UTRSTAT_TXFE
                beq     1001b
@@ -68,7 +68,7 @@
        .endm
        .macro  waituart,rd,rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                ldr     \rd, [\rx, # S3C2410_UFCON]
                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
                beq     1001f                           @
                @ FIFO enabled...
@@ -79,7 +79,7 @@
                b       1002f
 1001:
                @ idle waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                ldr     \rd, [\rx, # S3C2410_UTRSTAT]
                tst     \rd, #S3C2410_UTRSTAT_TXFE
                beq     1001b
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index f5144cdd3001..114178268b75 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -39,7 +39,8 @@ struct samsung_dma_config {
 };
 struct samsung_dma_ops {
-        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param);
+        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name);
        int (*release)(unsigned ch, void *param);
        int (*config)(unsigned ch, struct samsung_dma_config *param);
        int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
index 945a99d59563..1d6cb2b8b094 100644
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ b/arch/arm/plat-samsung/include/plat/fimc-core.h
@@ -43,6 +43,8 @@ static inline void s3c_fimc_setname(int id, char *name)
                s5p_device_fimc3.name = name;
                break;
 #endif
+        default:
+                break;
        }
 }
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index f7a3ea2c498a..cf5aae5b0975 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -106,7 +106,18 @@ static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chi
 #else
 /* machine specific code should provide samsung_gpiolib_getchip */
-#include <mach/gpio-track.h>
+extern struct samsung_gpio_chip s3c24xx_gpios[];
+static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
+{
+        struct samsung_gpio_chip *chip;
+        if (pin > S3C_GPIO_END)
+                return NULL;
+        chip = &s3c24xx_gpios[pin/32];
+        return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
+}
 static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
 #endif
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
deleted file mode 100644
index d1ecef0e38e0..000000000000
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <plat/gpio-cfg.h>
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 887a0c954379..f6fcadeee969 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -109,17 +109,11 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 #ifdef CONFIG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
-extern int s3c24xx_irq_suspend(void);
-extern void s3c24xx_irq_resume(void);
 #else
 #define s3c_irq_wake NULL
 #define s3c_irqext_wake NULL
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
 #endif
-extern struct syscore_ops s3c24xx_irq_syscore_ops;
 /* PM debug functions */
 #ifdef CONFIG_SAMSUNG_PM_DEBUG
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index 7178e338e25e..f27399a3c68d 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -25,6 +25,7 @@ extern  int s3c2416_baseclk_add(void);
 extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
 extern struct syscore_ops s3c2416_irq_syscore_ops;
 #else
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index a5b794ff838b..71b88ec48956 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -25,6 +25,8 @@ extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
 extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
 #define s3c2443_init_uarts NULL
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
index 3a70aebc9205..9c96f3586ce0 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-time.h
@@ -36,5 +36,5 @@ struct s5p_timer_source {
 extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
                                        enum s5p_timer_mode source);
-extern  struct sys_timer s5p_timer;
+extern  void s5p_timer_init(void);
 #endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 151cc9195cf6..9b87f38fc4f4 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -374,6 +374,8 @@ static inline void s3c_sdhci_setname(int id, char *name)
                s3c_device_hsmmc3.name = name;
                break;
 #endif
+        default:
+                break;
        }
 }
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7e068d182c3d..438b24846e7f 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -97,33 +97,6 @@ static inline void flush(void)
                *((volatile unsigned int __force *)(ad)) = (d); \
        } while (0)
-/* CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-#define WDOG_COUNT (0xff00)
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
 #ifdef CONFIG_S3C_BOOT_ERROR_RESET
 static void arch_decomp_error(const char *x)
@@ -173,7 +146,6 @@ arch_decomp_setup(void)
         */
        arch_detect_cpu();
-        arch_decomp_wdog_start();
        /* Enable the UART FIFOs if they where not enabled and our
         * configuration says we should turn them on.
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 15070284343e..002b1472293b 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -51,7 +51,7 @@ void s3c_pm_dbg(const char *fmt, ...)
        char buff[256];
        va_start(va, fmt);
-        vsprintf(buff, fmt, va);
+        vsnprintf(buff, sizeof(buff), fmt, va);
        va_end(va);
        printascii(buff);
@@ -243,6 +243,7 @@ int (*pm_cpu_sleep)(unsigned long);
 static int s3c_pm_enter(suspend_state_t state)
 {
+        int ret;
        /* ensure the debug is initialised (if enabled) */
        s3c_pm_debug_init();
@@ -300,7 +301,9 @@ static int s3c_pm_enter(suspend_state_t state)
         * we resume as it saves its own register state and restores it
         * during the resume.  */
-        cpu_suspend(0, pm_cpu_sleep);
+        ret = cpu_suspend(0, pm_cpu_sleep);
+        if (ret)
+                return ret;
        /* restore the system state */
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
index f99448c48d30..0cc40aea3f5a 100644
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -36,7 +36,8 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
 }
 static unsigned s3c_dma_request(enum dma_ch dma_ch,
-                                        struct samsung_dma_req *param)
+                                struct samsung_dma_req *param,
+                                struct device *dev, char *ch_name)
 {
        struct cb_data *data;
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
index 33bd3f3d20f5..faa651602780 100644
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ b/arch/arm/plat-samsung/s5p-irq-eint.c
@@ -15,8 +15,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/gpio.h>
+#include <linux/irqchip/arm-vic.h>
-#include <asm/hardware/vic.h>
 #include <plat/regs-irqtype.h>
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
index dfb47d638f03..103e371f5e35 100644
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -13,8 +13,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-vic.h>
-#include <asm/hardware/vic.h>
 #include <mach/map.h>
 #include <plat/regs-timer.h>
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c
index 028b6e877eb9..e92510cf82ee 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/s5p-time.c
@@ -274,15 +274,8 @@ static void __init s5p_clockevent_init(void)
        clock_rate = clk_get_rate(tin_event);
        clock_count_per_tick = clock_rate / HZ;
-        clockevents_calc_mult_shift(&time_event_device,
-                                    clock_rate, S5PTIMER_MIN_RANGE);
-        time_event_device.max_delta_ns =
-                clockevent_delta2ns(-1, &time_event_device);
-        time_event_device.min_delta_ns =
-                clockevent_delta2ns(1, &time_event_device);
        time_event_device.cpumask = cpumask_of(0);
-        clockevents_register_device(&time_event_device);
+        clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
        irq_number = timer_source.event_id + IRQ_TIMER0;
        setup_irq(irq_number, &s5p_clock_event_irq);
@@ -393,13 +386,9 @@ static void __init s5p_timer_resources(void)
        clk_enable(tin_source);
 }
-static void __init s5p_timer_init(void)
+void __init s5p_timer_init(void)
 {
        s5p_timer_resources();
        s5p_clockevent_init();
        s5p_clocksource_init();
 }
-struct sys_timer s5p_timer = {
-        .init           = s5p_timer_init,
-};
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 60552e22f22e..73defd00c3e4 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -27,6 +27,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
 #include <asm/mach-types.h>
@@ -95,7 +96,7 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
 * IRQs are disabled before entering here from do_gettimeofday()
 */
-static unsigned long s3c2410_gettimeoffset (void)
+static u32 s3c2410_gettimeoffset(void)
 {
        unsigned long tdone;
        unsigned long tval;
@@ -120,7 +121,7 @@ static unsigned long s3c2410_gettimeoffset (void)
                        tdone += timer_startval;
        }
-        return timer_ticks_to_usec(tdone);
+        return timer_ticks_to_usec(tdone) * 1000;
 }
@@ -271,15 +272,16 @@ static void __init s3c2410_timer_resources(void)
        clk_enable(tin);
 }
-static void __init s3c2410_timer_init(void)
+static struct syscore_ops s3c24xx_syscore_ops = {
+        .resume         = s3c2410_timer_setup,
+};
+void __init s3c24xx_timer_init(void)
 {
+        arch_gettimeoffset = s3c2410_gettimeoffset;
        s3c2410_timer_resources();
        s3c2410_timer_setup();
        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
+        register_syscore_ops(&s3c24xx_syscore_ops);
 }
-struct sys_timer s3c24xx_timer = {
-        .init           = s3c2410_timer_init,
-        .offset         = s3c2410_gettimeoffset,
-        .resume         = s3c2410_timer_setup
-};
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 87dbd81bdf51..739d016eb273 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -10,6 +10,7 @@ choice
 config ARCH_SPEAR13XX
        bool "ST SPEAr13xx with Device Tree"
+        select ARCH_HAVE_CPUFREQ
        select ARM_GIC
        select CPU_V7
        select GPIO_SPEAR_SPICS
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 2ce6cb17a98b..51b2dc93e4da 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -38,6 +38,5 @@ static inline void flush(void)
 * nothing to do
 */
 #define arch_decomp_setup()
-#define arch_decomp_wdog()
 #endif /* __PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 4f990115b1bd..7d4616d5df11 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,8 +11,8 @@
 * warranty of any kind, whether express or implied.
 */
 #include <linux/io.h>
+#include <linux/amba/sp810.h>
 #include <asm/system_misc.h>
-#include <asm/hardware/sp810.h>
 #include <mach/spear.h>
 #include <mach/generic.h>
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 03321af5de9f..bd5c53cd6962 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -186,15 +186,9 @@ static void __init spear_clockevent_init(int irq)
        tick_rate = clk_get_rate(gpt_clk);
        tick_rate >>= CTRL_PRESCALER16;
-        clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
-        clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
-                        &clkevt);
-        clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
        clkevt.cpumask = cpumask_of(0);
-        clockevents_register_device(&clkevt);
+        clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
        setup_irq(irq, &spear_timer_irq);
 }
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 04ca4937d8ca..f2ac15561778 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -14,10 +14,10 @@
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
+#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <asm/hardware/gic.h>
 /*
 * Write pen_release in a way that is guaranteed to be visible to all
@@ -79,7 +79,7 @@ int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idl
         * the boot monitor to read the system wide flags register,
         * and branch to the address found there.
         */
-        gic_raise_softirq(cpumask_of(cpu), 0);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index dd5e56f95f3f..8d10dc8a1e17 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -22,12 +22,14 @@
        .macro  DBGSTR, str
 #ifdef DEBUG
        stmfd   sp!, {r0-r3, ip, lr}
-        add     r0, pc, #4
+        ldr     r0, =1f
        bl      printk
-        b       1f
+        ldmfd   sp!, {r0-r3, ip, lr}
-        .asciz  KERN_DEBUG "VFP: \str\n"
-        .balign 4
+        .pushsection .rodata, "a"
-1:      ldmfd   sp!, {r0-r3, ip, lr}
+1:      .ascii  KERN_DEBUG "VFP: \str\n"
+        .byte   0
+        .previous
 #endif
        .endm
@@ -35,12 +37,14 @@
 #ifdef DEBUG
        stmfd   sp!, {r0-r3, ip, lr}
        mov     r1, \arg
-        add     r0, pc, #4
+        ldr     r0, =1f
        bl      printk
-        b       1f
+        ldmfd   sp!, {r0-r3, ip, lr}
-        .asciz  KERN_DEBUG "VFP: \str\n"
-        .balign 4
+        .pushsection .rodata, "a"
-1:      ldmfd   sp!, {r0-r3, ip, lr}
+1:      .ascii  KERN_DEBUG "VFP: \str\n"
+        .byte   0
+        .previous
 #endif
        .endm
@@ -50,12 +54,14 @@
        mov     r3, \arg3
        mov     r2, \arg2
        mov     r1, \arg1
-        add     r0, pc, #4
+        ldr     r0, =1f
        bl      printk
-        b       1f
+        ldmfd   sp!, {r0-r3, ip, lr}
-        .asciz  KERN_DEBUG "VFP: \str\n"
-        .balign 4
+        .pushsection .rodata, "a"
-1:      ldmfd   sp!, {r0-r3, ip, lr}
+1:      .ascii  KERN_DEBUG "VFP: \str\n"
+        .byte   0
+        .previous
 #endif
        .endm
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 3b44e0dd0a93..5dfbb0b8e7f4 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -413,7 +413,7 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
         * If there isn't a second FP instruction, exit now. Note that
         * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
         */
-        if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
+        if ((fpexc & (FPEXC_EX | FPEXC_FP2V)) != (FPEXC_EX | FPEXC_FP2V))
                goto exit;
        /*
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 7a32976fa2a3..8dc0605a9ce9 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -59,14 +59,16 @@ static int map_foreign_page(unsigned long lpfn, unsigned long fgmfn,
        };
        xen_ulong_t idx = fgmfn;
        xen_pfn_t gpfn = lpfn;
+        int err = 0;
        set_xen_guest_handle(xatp.idxs, &idx);
        set_xen_guest_handle(xatp.gpfns, &gpfn);
+        set_xen_guest_handle(xatp.errs, &err);
        rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap_range, &xatp);
-        if (rc) {
+        if (rc || err) {
-                pr_warn("Failed to map pfn to mfn rc:%d pfn:%lx mfn:%lx\n",
+                pr_warn("Failed to map pfn to mfn rc:%d:%d pfn:%lx mfn:%lx\n",
-                        rc, lpfn, fgmfn);
+                        rc, err, lpfn, fgmfn);
                return 1;
        }
        return 0;